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radv: adjust CB_SHADER_MASK for dual-source blending in the shader info pass
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/disk_cache.h"
29 #include "util/mesa-sha1.h"
30 #include "util/u_atomic.h"
31 #include "radv_debug.h"
32 #include "radv_private.h"
33 #include "radv_cs.h"
34 #include "radv_shader.h"
35 #include "nir/nir.h"
36 #include "nir/nir_builder.h"
37 #include "nir/nir_xfb_info.h"
38 #include "spirv/nir_spirv.h"
39 #include "vk_util.h"
40
41 #include "sid.h"
42 #include "ac_binary.h"
43 #include "ac_llvm_util.h"
44 #include "ac_nir_to_llvm.h"
45 #include "vk_format.h"
46 #include "util/debug.h"
47 #include "ac_exp_param.h"
48 #include "ac_shader_util.h"
49
50 struct radv_blend_state {
51 uint32_t blend_enable_4bit;
52 uint32_t need_src_alpha;
53
54 uint32_t cb_color_control;
55 uint32_t cb_target_mask;
56 uint32_t cb_target_enabled_4bit;
57 uint32_t sx_mrt_blend_opt[8];
58 uint32_t cb_blend_control[8];
59
60 uint32_t spi_shader_col_format;
61 uint32_t cb_shader_mask;
62 uint32_t db_alpha_to_mask;
63
64 uint32_t commutative_4bit;
65
66 bool single_cb_enable;
67 bool mrt0_is_dual_src;
68 };
69
70 struct radv_dsa_order_invariance {
71 /* Whether the final result in Z/S buffers is guaranteed to be
72 * invariant under changes to the order in which fragments arrive.
73 */
74 bool zs;
75
76 /* Whether the set of fragments that pass the combined Z/S test is
77 * guaranteed to be invariant under changes to the order in which
78 * fragments arrive.
79 */
80 bool pass_set;
81 };
82
83 struct radv_tessellation_state {
84 uint32_t ls_hs_config;
85 unsigned num_patches;
86 unsigned lds_size;
87 uint32_t tf_param;
88 };
89
90 static const VkPipelineMultisampleStateCreateInfo *
91 radv_pipeline_get_multisample_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
92 {
93 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
94 return pCreateInfo->pMultisampleState;
95 return NULL;
96 }
97
98 static const VkPipelineTessellationStateCreateInfo *
99 radv_pipeline_get_tessellation_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
100 {
101 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
102 if (pCreateInfo->pStages[i].stage == VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT ||
103 pCreateInfo->pStages[i].stage == VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) {
104 return pCreateInfo->pTessellationState;
105 }
106 }
107 return NULL;
108 }
109
110 static const VkPipelineDepthStencilStateCreateInfo *
111 radv_pipeline_get_depth_stencil_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
112 {
113 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
114 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
115
116 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
117 subpass->depth_stencil_attachment)
118 return pCreateInfo->pDepthStencilState;
119 return NULL;
120 }
121
122 static const VkPipelineColorBlendStateCreateInfo *
123 radv_pipeline_get_color_blend_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
124 {
125 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
126 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
127
128 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
129 subpass->has_color_att)
130 return pCreateInfo->pColorBlendState;
131 return NULL;
132 }
133
134 bool radv_pipeline_has_ngg(const struct radv_pipeline *pipeline)
135 {
136 struct radv_shader_variant *variant = NULL;
137 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
138 variant = pipeline->shaders[MESA_SHADER_GEOMETRY];
139 else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
140 variant = pipeline->shaders[MESA_SHADER_TESS_EVAL];
141 else if (pipeline->shaders[MESA_SHADER_VERTEX])
142 variant = pipeline->shaders[MESA_SHADER_VERTEX];
143 else
144 return false;
145 return variant->info.is_ngg;
146 }
147
148 bool radv_pipeline_has_ngg_passthrough(const struct radv_pipeline *pipeline)
149 {
150 assert(radv_pipeline_has_ngg(pipeline));
151
152 struct radv_shader_variant *variant = NULL;
153 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
154 variant = pipeline->shaders[MESA_SHADER_GEOMETRY];
155 else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
156 variant = pipeline->shaders[MESA_SHADER_TESS_EVAL];
157 else if (pipeline->shaders[MESA_SHADER_VERTEX])
158 variant = pipeline->shaders[MESA_SHADER_VERTEX];
159 else
160 return false;
161 return variant->info.is_ngg_passthrough;
162 }
163
164 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline *pipeline)
165 {
166 if (!radv_pipeline_has_gs(pipeline))
167 return false;
168
169 /* The GS copy shader is required if the pipeline has GS on GFX6-GFX9.
170 * On GFX10, it might be required in rare cases if it's not possible to
171 * enable NGG.
172 */
173 if (radv_pipeline_has_ngg(pipeline))
174 return false;
175
176 assert(pipeline->gs_copy_shader);
177 return true;
178 }
179
180 static void
181 radv_pipeline_destroy(struct radv_device *device,
182 struct radv_pipeline *pipeline,
183 const VkAllocationCallbacks* allocator)
184 {
185 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
186 if (pipeline->shaders[i])
187 radv_shader_variant_destroy(device, pipeline->shaders[i]);
188
189 if (pipeline->gs_copy_shader)
190 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
191
192 if(pipeline->cs.buf)
193 free(pipeline->cs.buf);
194
195 vk_object_base_finish(&pipeline->base);
196 vk_free2(&device->vk.alloc, allocator, pipeline);
197 }
198
199 void radv_DestroyPipeline(
200 VkDevice _device,
201 VkPipeline _pipeline,
202 const VkAllocationCallbacks* pAllocator)
203 {
204 RADV_FROM_HANDLE(radv_device, device, _device);
205 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
206
207 if (!_pipeline)
208 return;
209
210 radv_pipeline_destroy(device, pipeline, pAllocator);
211 }
212
213 static uint32_t get_hash_flags(struct radv_device *device)
214 {
215 uint32_t hash_flags = 0;
216
217 if (device->instance->debug_flags & RADV_DEBUG_NO_NGG)
218 hash_flags |= RADV_HASH_SHADER_NO_NGG;
219 if (device->physical_device->cs_wave_size == 32)
220 hash_flags |= RADV_HASH_SHADER_CS_WAVE32;
221 if (device->physical_device->ps_wave_size == 32)
222 hash_flags |= RADV_HASH_SHADER_PS_WAVE32;
223 if (device->physical_device->ge_wave_size == 32)
224 hash_flags |= RADV_HASH_SHADER_GE_WAVE32;
225 if (device->physical_device->use_llvm)
226 hash_flags |= RADV_HASH_SHADER_LLVM;
227 return hash_flags;
228 }
229
230 static VkResult
231 radv_pipeline_scratch_init(struct radv_device *device,
232 struct radv_pipeline *pipeline)
233 {
234 unsigned scratch_bytes_per_wave = 0;
235 unsigned max_waves = 0;
236 unsigned min_waves = 1;
237
238 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
239 if (pipeline->shaders[i] &&
240 pipeline->shaders[i]->config.scratch_bytes_per_wave) {
241 unsigned max_stage_waves = device->scratch_waves;
242
243 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
244 pipeline->shaders[i]->config.scratch_bytes_per_wave);
245
246 max_stage_waves = MIN2(max_stage_waves,
247 4 * device->physical_device->rad_info.num_good_compute_units *
248 (256 / pipeline->shaders[i]->config.num_vgprs));
249 max_waves = MAX2(max_waves, max_stage_waves);
250 }
251 }
252
253 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
254 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
255 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
256 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
257 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
258 }
259
260 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
261 pipeline->max_waves = max_waves;
262 return VK_SUCCESS;
263 }
264
265 static uint32_t si_translate_blend_logic_op(VkLogicOp op)
266 {
267 switch (op) {
268 case VK_LOGIC_OP_CLEAR:
269 return V_028808_ROP3_CLEAR;
270 case VK_LOGIC_OP_AND:
271 return V_028808_ROP3_AND;
272 case VK_LOGIC_OP_AND_REVERSE:
273 return V_028808_ROP3_AND_REVERSE;
274 case VK_LOGIC_OP_COPY:
275 return V_028808_ROP3_COPY;
276 case VK_LOGIC_OP_AND_INVERTED:
277 return V_028808_ROP3_AND_INVERTED;
278 case VK_LOGIC_OP_NO_OP:
279 return V_028808_ROP3_NO_OP;
280 case VK_LOGIC_OP_XOR:
281 return V_028808_ROP3_XOR;
282 case VK_LOGIC_OP_OR:
283 return V_028808_ROP3_OR;
284 case VK_LOGIC_OP_NOR:
285 return V_028808_ROP3_NOR;
286 case VK_LOGIC_OP_EQUIVALENT:
287 return V_028808_ROP3_EQUIVALENT;
288 case VK_LOGIC_OP_INVERT:
289 return V_028808_ROP3_INVERT;
290 case VK_LOGIC_OP_OR_REVERSE:
291 return V_028808_ROP3_OR_REVERSE;
292 case VK_LOGIC_OP_COPY_INVERTED:
293 return V_028808_ROP3_COPY_INVERTED;
294 case VK_LOGIC_OP_OR_INVERTED:
295 return V_028808_ROP3_OR_INVERTED;
296 case VK_LOGIC_OP_NAND:
297 return V_028808_ROP3_NAND;
298 case VK_LOGIC_OP_SET:
299 return V_028808_ROP3_SET;
300 default:
301 unreachable("Unhandled logic op");
302 }
303 }
304
305
306 static uint32_t si_translate_blend_function(VkBlendOp op)
307 {
308 switch (op) {
309 case VK_BLEND_OP_ADD:
310 return V_028780_COMB_DST_PLUS_SRC;
311 case VK_BLEND_OP_SUBTRACT:
312 return V_028780_COMB_SRC_MINUS_DST;
313 case VK_BLEND_OP_REVERSE_SUBTRACT:
314 return V_028780_COMB_DST_MINUS_SRC;
315 case VK_BLEND_OP_MIN:
316 return V_028780_COMB_MIN_DST_SRC;
317 case VK_BLEND_OP_MAX:
318 return V_028780_COMB_MAX_DST_SRC;
319 default:
320 return 0;
321 }
322 }
323
324 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
325 {
326 switch (factor) {
327 case VK_BLEND_FACTOR_ZERO:
328 return V_028780_BLEND_ZERO;
329 case VK_BLEND_FACTOR_ONE:
330 return V_028780_BLEND_ONE;
331 case VK_BLEND_FACTOR_SRC_COLOR:
332 return V_028780_BLEND_SRC_COLOR;
333 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
334 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
335 case VK_BLEND_FACTOR_DST_COLOR:
336 return V_028780_BLEND_DST_COLOR;
337 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
338 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
339 case VK_BLEND_FACTOR_SRC_ALPHA:
340 return V_028780_BLEND_SRC_ALPHA;
341 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
342 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
343 case VK_BLEND_FACTOR_DST_ALPHA:
344 return V_028780_BLEND_DST_ALPHA;
345 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
346 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
347 case VK_BLEND_FACTOR_CONSTANT_COLOR:
348 return V_028780_BLEND_CONSTANT_COLOR;
349 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
350 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
351 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
352 return V_028780_BLEND_CONSTANT_ALPHA;
353 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
354 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
355 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
356 return V_028780_BLEND_SRC_ALPHA_SATURATE;
357 case VK_BLEND_FACTOR_SRC1_COLOR:
358 return V_028780_BLEND_SRC1_COLOR;
359 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
360 return V_028780_BLEND_INV_SRC1_COLOR;
361 case VK_BLEND_FACTOR_SRC1_ALPHA:
362 return V_028780_BLEND_SRC1_ALPHA;
363 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
364 return V_028780_BLEND_INV_SRC1_ALPHA;
365 default:
366 return 0;
367 }
368 }
369
370 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
371 {
372 switch (op) {
373 case VK_BLEND_OP_ADD:
374 return V_028760_OPT_COMB_ADD;
375 case VK_BLEND_OP_SUBTRACT:
376 return V_028760_OPT_COMB_SUBTRACT;
377 case VK_BLEND_OP_REVERSE_SUBTRACT:
378 return V_028760_OPT_COMB_REVSUBTRACT;
379 case VK_BLEND_OP_MIN:
380 return V_028760_OPT_COMB_MIN;
381 case VK_BLEND_OP_MAX:
382 return V_028760_OPT_COMB_MAX;
383 default:
384 return V_028760_OPT_COMB_BLEND_DISABLED;
385 }
386 }
387
388 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
389 {
390 switch (factor) {
391 case VK_BLEND_FACTOR_ZERO:
392 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
393 case VK_BLEND_FACTOR_ONE:
394 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
395 case VK_BLEND_FACTOR_SRC_COLOR:
396 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
397 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
398 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
399 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
400 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
401 case VK_BLEND_FACTOR_SRC_ALPHA:
402 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
403 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
404 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
405 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
406 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
407 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
408 default:
409 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
410 }
411 }
412
413 /**
414 * Get rid of DST in the blend factors by commuting the operands:
415 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
416 */
417 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
418 unsigned *dst_factor, unsigned expected_dst,
419 unsigned replacement_src)
420 {
421 if (*src_factor == expected_dst &&
422 *dst_factor == VK_BLEND_FACTOR_ZERO) {
423 *src_factor = VK_BLEND_FACTOR_ZERO;
424 *dst_factor = replacement_src;
425
426 /* Commuting the operands requires reversing subtractions. */
427 if (*func == VK_BLEND_OP_SUBTRACT)
428 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
429 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
430 *func = VK_BLEND_OP_SUBTRACT;
431 }
432 }
433
434 static bool si_blend_factor_uses_dst(unsigned factor)
435 {
436 return factor == VK_BLEND_FACTOR_DST_COLOR ||
437 factor == VK_BLEND_FACTOR_DST_ALPHA ||
438 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
439 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
440 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
441 }
442
443 static bool is_dual_src(VkBlendFactor factor)
444 {
445 switch (factor) {
446 case VK_BLEND_FACTOR_SRC1_COLOR:
447 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
448 case VK_BLEND_FACTOR_SRC1_ALPHA:
449 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
450 return true;
451 default:
452 return false;
453 }
454 }
455
456 static unsigned radv_choose_spi_color_format(VkFormat vk_format,
457 bool blend_enable,
458 bool blend_need_alpha)
459 {
460 const struct vk_format_description *desc = vk_format_description(vk_format);
461 struct ac_spi_color_formats formats = {};
462 unsigned format, ntype, swap;
463
464 format = radv_translate_colorformat(vk_format);
465 ntype = radv_translate_color_numformat(vk_format, desc,
466 vk_format_get_first_non_void_channel(vk_format));
467 swap = radv_translate_colorswap(vk_format, false);
468
469 ac_choose_spi_color_formats(format, swap, ntype, false, &formats);
470
471 if (blend_enable && blend_need_alpha)
472 return formats.blend_alpha;
473 else if(blend_need_alpha)
474 return formats.alpha;
475 else if(blend_enable)
476 return formats.blend;
477 else
478 return formats.normal;
479 }
480
481 static void
482 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
483 const VkGraphicsPipelineCreateInfo *pCreateInfo,
484 struct radv_blend_state *blend)
485 {
486 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
487 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
488 unsigned col_format = 0;
489 unsigned num_targets;
490
491 for (unsigned i = 0; i < (blend->single_cb_enable ? 1 : subpass->color_count); ++i) {
492 unsigned cf;
493
494 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
495 cf = V_028714_SPI_SHADER_ZERO;
496 } else {
497 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
498 bool blend_enable =
499 blend->blend_enable_4bit & (0xfu << (i * 4));
500
501 cf = radv_choose_spi_color_format(attachment->format,
502 blend_enable,
503 blend->need_src_alpha & (1 << i));
504 }
505
506 col_format |= cf << (4 * i);
507 }
508
509 if (!(col_format & 0xf) && blend->need_src_alpha & (1 << 0)) {
510 /* When a subpass doesn't have any color attachments, write the
511 * alpha channel of MRT0 when alpha coverage is enabled because
512 * the depth attachment needs it.
513 */
514 col_format |= V_028714_SPI_SHADER_32_AR;
515 }
516
517 /* If the i-th target format is set, all previous target formats must
518 * be non-zero to avoid hangs.
519 */
520 num_targets = (util_last_bit(col_format) + 3) / 4;
521 for (unsigned i = 0; i < num_targets; i++) {
522 if (!(col_format & (0xf << (i * 4)))) {
523 col_format |= V_028714_SPI_SHADER_32_R << (i * 4);
524 }
525 }
526
527 /* The output for dual source blending should have the same format as
528 * the first output.
529 */
530 if (blend->mrt0_is_dual_src)
531 col_format |= (col_format & 0xf) << 4;
532
533 blend->spi_shader_col_format = col_format;
534 }
535
536 static bool
537 format_is_int8(VkFormat format)
538 {
539 const struct vk_format_description *desc = vk_format_description(format);
540 int channel = vk_format_get_first_non_void_channel(format);
541
542 return channel >= 0 && desc->channel[channel].pure_integer &&
543 desc->channel[channel].size == 8;
544 }
545
546 static bool
547 format_is_int10(VkFormat format)
548 {
549 const struct vk_format_description *desc = vk_format_description(format);
550
551 if (desc->nr_channels != 4)
552 return false;
553 for (unsigned i = 0; i < 4; i++) {
554 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
555 return true;
556 }
557 return false;
558 }
559
560 /*
561 * Ordered so that for each i,
562 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
563 */
564 const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS] = {
565 VK_FORMAT_R32_SFLOAT,
566 VK_FORMAT_R32G32_SFLOAT,
567 VK_FORMAT_R8G8B8A8_UNORM,
568 VK_FORMAT_R16G16B16A16_UNORM,
569 VK_FORMAT_R16G16B16A16_SNORM,
570 VK_FORMAT_R16G16B16A16_UINT,
571 VK_FORMAT_R16G16B16A16_SINT,
572 VK_FORMAT_R32G32B32A32_SFLOAT,
573 VK_FORMAT_R8G8B8A8_UINT,
574 VK_FORMAT_R8G8B8A8_SINT,
575 VK_FORMAT_A2R10G10B10_UINT_PACK32,
576 VK_FORMAT_A2R10G10B10_SINT_PACK32,
577 };
578
579 unsigned radv_format_meta_fs_key(VkFormat format)
580 {
581 unsigned col_format = radv_choose_spi_color_format(format, false, false);
582
583 assert(col_format != V_028714_SPI_SHADER_32_AR);
584 if (col_format >= V_028714_SPI_SHADER_32_AR)
585 --col_format; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
586
587 --col_format; /* Skip V_028714_SPI_SHADER_ZERO */
588 bool is_int8 = format_is_int8(format);
589 bool is_int10 = format_is_int10(format);
590
591 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
592 }
593
594 static void
595 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo *pCreateInfo,
596 unsigned *is_int8, unsigned *is_int10)
597 {
598 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
599 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
600 *is_int8 = 0;
601 *is_int10 = 0;
602
603 for (unsigned i = 0; i < subpass->color_count; ++i) {
604 struct radv_render_pass_attachment *attachment;
605
606 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
607 continue;
608
609 attachment = pass->attachments + subpass->color_attachments[i].attachment;
610
611 if (format_is_int8(attachment->format))
612 *is_int8 |= 1 << i;
613 if (format_is_int10(attachment->format))
614 *is_int10 |= 1 << i;
615 }
616 }
617
618 static void
619 radv_blend_check_commutativity(struct radv_blend_state *blend,
620 VkBlendOp op, VkBlendFactor src,
621 VkBlendFactor dst, unsigned chanmask)
622 {
623 /* Src factor is allowed when it does not depend on Dst. */
624 static const uint32_t src_allowed =
625 (1u << VK_BLEND_FACTOR_ONE) |
626 (1u << VK_BLEND_FACTOR_SRC_COLOR) |
627 (1u << VK_BLEND_FACTOR_SRC_ALPHA) |
628 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE) |
629 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR) |
630 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA) |
631 (1u << VK_BLEND_FACTOR_SRC1_COLOR) |
632 (1u << VK_BLEND_FACTOR_SRC1_ALPHA) |
633 (1u << VK_BLEND_FACTOR_ZERO) |
634 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR) |
635 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA) |
636 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR) |
637 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA) |
638 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR) |
639 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA);
640
641 if (dst == VK_BLEND_FACTOR_ONE &&
642 (src_allowed & (1u << src))) {
643 /* Addition is commutative, but floating point addition isn't
644 * associative: subtle changes can be introduced via different
645 * rounding. Be conservative, only enable for min and max.
646 */
647 if (op == VK_BLEND_OP_MAX || op == VK_BLEND_OP_MIN)
648 blend->commutative_4bit |= chanmask;
649 }
650 }
651
652 static struct radv_blend_state
653 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
654 const VkGraphicsPipelineCreateInfo *pCreateInfo,
655 const struct radv_graphics_pipeline_create_info *extra)
656 {
657 const VkPipelineColorBlendStateCreateInfo *vkblend = radv_pipeline_get_color_blend_state(pCreateInfo);
658 const VkPipelineMultisampleStateCreateInfo *vkms = radv_pipeline_get_multisample_state(pCreateInfo);
659 struct radv_blend_state blend = {0};
660 unsigned mode = V_028808_CB_NORMAL;
661 int i;
662
663 if (extra && extra->custom_blend_mode) {
664 blend.single_cb_enable = true;
665 mode = extra->custom_blend_mode;
666 }
667
668 blend.cb_color_control = 0;
669 if (vkblend) {
670 if (vkblend->logicOpEnable)
671 blend.cb_color_control |= S_028808_ROP3(si_translate_blend_logic_op(vkblend->logicOp));
672 else
673 blend.cb_color_control |= S_028808_ROP3(V_028808_ROP3_COPY);
674 }
675
676 blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
677 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
678 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
679 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
680 S_028B70_OFFSET_ROUND(1);
681
682 if (vkms && vkms->alphaToCoverageEnable) {
683 blend.db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
684 blend.need_src_alpha |= 0x1;
685 }
686
687 blend.cb_target_mask = 0;
688 if (vkblend) {
689 for (i = 0; i < vkblend->attachmentCount; i++) {
690 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
691 unsigned blend_cntl = 0;
692 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
693 VkBlendOp eqRGB = att->colorBlendOp;
694 VkBlendFactor srcRGB = att->srcColorBlendFactor;
695 VkBlendFactor dstRGB = att->dstColorBlendFactor;
696 VkBlendOp eqA = att->alphaBlendOp;
697 VkBlendFactor srcA = att->srcAlphaBlendFactor;
698 VkBlendFactor dstA = att->dstAlphaBlendFactor;
699
700 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
701
702 if (!att->colorWriteMask)
703 continue;
704
705 blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
706 blend.cb_target_enabled_4bit |= 0xf << (4 * i);
707 if (!att->blendEnable) {
708 blend.cb_blend_control[i] = blend_cntl;
709 continue;
710 }
711
712 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
713 if (i == 0)
714 blend.mrt0_is_dual_src = true;
715
716 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
717 srcRGB = VK_BLEND_FACTOR_ONE;
718 dstRGB = VK_BLEND_FACTOR_ONE;
719 }
720 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
721 srcA = VK_BLEND_FACTOR_ONE;
722 dstA = VK_BLEND_FACTOR_ONE;
723 }
724
725 radv_blend_check_commutativity(&blend, eqRGB, srcRGB, dstRGB,
726 0x7 << (4 * i));
727 radv_blend_check_commutativity(&blend, eqA, srcA, dstA,
728 0x8 << (4 * i));
729
730 /* Blending optimizations for RB+.
731 * These transformations don't change the behavior.
732 *
733 * First, get rid of DST in the blend factors:
734 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
735 */
736 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
737 VK_BLEND_FACTOR_DST_COLOR,
738 VK_BLEND_FACTOR_SRC_COLOR);
739
740 si_blend_remove_dst(&eqA, &srcA, &dstA,
741 VK_BLEND_FACTOR_DST_COLOR,
742 VK_BLEND_FACTOR_SRC_COLOR);
743
744 si_blend_remove_dst(&eqA, &srcA, &dstA,
745 VK_BLEND_FACTOR_DST_ALPHA,
746 VK_BLEND_FACTOR_SRC_ALPHA);
747
748 /* Look up the ideal settings from tables. */
749 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
750 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
751 srcA_opt = si_translate_blend_opt_factor(srcA, true);
752 dstA_opt = si_translate_blend_opt_factor(dstA, true);
753
754 /* Handle interdependencies. */
755 if (si_blend_factor_uses_dst(srcRGB))
756 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
757 if (si_blend_factor_uses_dst(srcA))
758 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
759
760 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
761 (dstRGB == VK_BLEND_FACTOR_ZERO ||
762 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
763 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
764 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
765
766 /* Set the final value. */
767 blend.sx_mrt_blend_opt[i] =
768 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
769 S_028760_COLOR_DST_OPT(dstRGB_opt) |
770 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
771 S_028760_ALPHA_SRC_OPT(srcA_opt) |
772 S_028760_ALPHA_DST_OPT(dstA_opt) |
773 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
774 blend_cntl |= S_028780_ENABLE(1);
775
776 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
777 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
778 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
779 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
780 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
781 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
782 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
783 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
784 }
785 blend.cb_blend_control[i] = blend_cntl;
786
787 blend.blend_enable_4bit |= 0xfu << (i * 4);
788
789 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
790 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
791 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
792 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
793 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
794 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
795 blend.need_src_alpha |= 1 << i;
796 }
797 for (i = vkblend->attachmentCount; i < 8; i++) {
798 blend.cb_blend_control[i] = 0;
799 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
800 }
801 }
802
803 if (pipeline->device->physical_device->rad_info.has_rbplus) {
804 /* Disable RB+ blend optimizations for dual source blending. */
805 if (blend.mrt0_is_dual_src) {
806 for (i = 0; i < 8; i++) {
807 blend.sx_mrt_blend_opt[i] =
808 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
809 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
810 }
811 }
812
813 /* RB+ doesn't work with dual source blending, logic op and
814 * RESOLVE.
815 */
816 if (blend.mrt0_is_dual_src ||
817 (vkblend && vkblend->logicOpEnable) ||
818 mode == V_028808_CB_RESOLVE)
819 blend.cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
820 }
821
822 if (blend.cb_target_mask)
823 blend.cb_color_control |= S_028808_MODE(mode);
824 else
825 blend.cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
826
827 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo, &blend);
828 return blend;
829 }
830
831 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
832 {
833 switch (op) {
834 case VK_STENCIL_OP_KEEP:
835 return V_02842C_STENCIL_KEEP;
836 case VK_STENCIL_OP_ZERO:
837 return V_02842C_STENCIL_ZERO;
838 case VK_STENCIL_OP_REPLACE:
839 return V_02842C_STENCIL_REPLACE_TEST;
840 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
841 return V_02842C_STENCIL_ADD_CLAMP;
842 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
843 return V_02842C_STENCIL_SUB_CLAMP;
844 case VK_STENCIL_OP_INVERT:
845 return V_02842C_STENCIL_INVERT;
846 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
847 return V_02842C_STENCIL_ADD_WRAP;
848 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
849 return V_02842C_STENCIL_SUB_WRAP;
850 default:
851 return 0;
852 }
853 }
854
855 static uint32_t si_translate_fill(VkPolygonMode func)
856 {
857 switch(func) {
858 case VK_POLYGON_MODE_FILL:
859 return V_028814_X_DRAW_TRIANGLES;
860 case VK_POLYGON_MODE_LINE:
861 return V_028814_X_DRAW_LINES;
862 case VK_POLYGON_MODE_POINT:
863 return V_028814_X_DRAW_POINTS;
864 default:
865 assert(0);
866 return V_028814_X_DRAW_POINTS;
867 }
868 }
869
870 static uint8_t radv_pipeline_get_ps_iter_samples(const VkGraphicsPipelineCreateInfo *pCreateInfo)
871 {
872 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
873 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
874 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
875 uint32_t ps_iter_samples = 1;
876 uint32_t num_samples;
877
878 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
879 *
880 * "If the VK_AMD_mixed_attachment_samples extension is enabled and the
881 * subpass uses color attachments, totalSamples is the number of
882 * samples of the color attachments. Otherwise, totalSamples is the
883 * value of VkPipelineMultisampleStateCreateInfo::rasterizationSamples
884 * specified at pipeline creation time."
885 */
886 if (subpass->has_color_att) {
887 num_samples = subpass->color_sample_count;
888 } else {
889 num_samples = vkms->rasterizationSamples;
890 }
891
892 if (vkms->sampleShadingEnable) {
893 ps_iter_samples = ceilf(vkms->minSampleShading * num_samples);
894 ps_iter_samples = util_next_power_of_two(ps_iter_samples);
895 }
896 return ps_iter_samples;
897 }
898
899 static bool
900 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
901 {
902 return pCreateInfo->depthTestEnable &&
903 pCreateInfo->depthWriteEnable &&
904 pCreateInfo->depthCompareOp != VK_COMPARE_OP_NEVER;
905 }
906
907 static bool
908 radv_writes_stencil(const VkStencilOpState *state)
909 {
910 return state->writeMask &&
911 (state->failOp != VK_STENCIL_OP_KEEP ||
912 state->passOp != VK_STENCIL_OP_KEEP ||
913 state->depthFailOp != VK_STENCIL_OP_KEEP);
914 }
915
916 static bool
917 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
918 {
919 return pCreateInfo->stencilTestEnable &&
920 (radv_writes_stencil(&pCreateInfo->front) ||
921 radv_writes_stencil(&pCreateInfo->back));
922 }
923
924 static bool
925 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
926 {
927 return radv_is_depth_write_enabled(pCreateInfo) ||
928 radv_is_stencil_write_enabled(pCreateInfo);
929 }
930
931 static bool
932 radv_order_invariant_stencil_op(VkStencilOp op)
933 {
934 /* REPLACE is normally order invariant, except when the stencil
935 * reference value is written by the fragment shader. Tracking this
936 * interaction does not seem worth the effort, so be conservative.
937 */
938 return op != VK_STENCIL_OP_INCREMENT_AND_CLAMP &&
939 op != VK_STENCIL_OP_DECREMENT_AND_CLAMP &&
940 op != VK_STENCIL_OP_REPLACE;
941 }
942
943 static bool
944 radv_order_invariant_stencil_state(const VkStencilOpState *state)
945 {
946 /* Compute whether, assuming Z writes are disabled, this stencil state
947 * is order invariant in the sense that the set of passing fragments as
948 * well as the final stencil buffer result does not depend on the order
949 * of fragments.
950 */
951 return !state->writeMask ||
952 /* The following assumes that Z writes are disabled. */
953 (state->compareOp == VK_COMPARE_OP_ALWAYS &&
954 radv_order_invariant_stencil_op(state->passOp) &&
955 radv_order_invariant_stencil_op(state->depthFailOp)) ||
956 (state->compareOp == VK_COMPARE_OP_NEVER &&
957 radv_order_invariant_stencil_op(state->failOp));
958 }
959
960 static bool
961 radv_pipeline_out_of_order_rast(struct radv_pipeline *pipeline,
962 struct radv_blend_state *blend,
963 const VkGraphicsPipelineCreateInfo *pCreateInfo)
964 {
965 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
966 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
967 const VkPipelineDepthStencilStateCreateInfo *vkds = radv_pipeline_get_depth_stencil_state(pCreateInfo);
968 const VkPipelineColorBlendStateCreateInfo *vkblend = radv_pipeline_get_color_blend_state(pCreateInfo);
969 unsigned colormask = blend->cb_target_enabled_4bit;
970
971 if (!pipeline->device->physical_device->out_of_order_rast_allowed)
972 return false;
973
974 /* Be conservative if a logic operation is enabled with color buffers. */
975 if (colormask && vkblend && vkblend->logicOpEnable)
976 return false;
977
978 /* Default depth/stencil invariance when no attachment is bound. */
979 struct radv_dsa_order_invariance dsa_order_invariant = {
980 .zs = true, .pass_set = true
981 };
982
983 if (vkds) {
984 struct radv_render_pass_attachment *attachment =
985 pass->attachments + subpass->depth_stencil_attachment->attachment;
986 bool has_stencil = vk_format_is_stencil(attachment->format);
987 struct radv_dsa_order_invariance order_invariance[2];
988 struct radv_shader_variant *ps =
989 pipeline->shaders[MESA_SHADER_FRAGMENT];
990
991 /* Compute depth/stencil order invariance in order to know if
992 * it's safe to enable out-of-order.
993 */
994 bool zfunc_is_ordered =
995 vkds->depthCompareOp == VK_COMPARE_OP_NEVER ||
996 vkds->depthCompareOp == VK_COMPARE_OP_LESS ||
997 vkds->depthCompareOp == VK_COMPARE_OP_LESS_OR_EQUAL ||
998 vkds->depthCompareOp == VK_COMPARE_OP_GREATER ||
999 vkds->depthCompareOp == VK_COMPARE_OP_GREATER_OR_EQUAL;
1000
1001 bool nozwrite_and_order_invariant_stencil =
1002 !radv_is_ds_write_enabled(vkds) ||
1003 (!radv_is_depth_write_enabled(vkds) &&
1004 radv_order_invariant_stencil_state(&vkds->front) &&
1005 radv_order_invariant_stencil_state(&vkds->back));
1006
1007 order_invariance[1].zs =
1008 nozwrite_and_order_invariant_stencil ||
1009 (!radv_is_stencil_write_enabled(vkds) &&
1010 zfunc_is_ordered);
1011 order_invariance[0].zs =
1012 !radv_is_depth_write_enabled(vkds) || zfunc_is_ordered;
1013
1014 order_invariance[1].pass_set =
1015 nozwrite_and_order_invariant_stencil ||
1016 (!radv_is_stencil_write_enabled(vkds) &&
1017 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1018 vkds->depthCompareOp == VK_COMPARE_OP_NEVER));
1019 order_invariance[0].pass_set =
1020 !radv_is_depth_write_enabled(vkds) ||
1021 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1022 vkds->depthCompareOp == VK_COMPARE_OP_NEVER);
1023
1024 dsa_order_invariant = order_invariance[has_stencil];
1025 if (!dsa_order_invariant.zs)
1026 return false;
1027
1028 /* The set of PS invocations is always order invariant,
1029 * except when early Z/S tests are requested.
1030 */
1031 if (ps &&
1032 ps->info.ps.writes_memory &&
1033 ps->info.ps.early_fragment_test &&
1034 !dsa_order_invariant.pass_set)
1035 return false;
1036
1037 /* Determine if out-of-order rasterization should be disabled
1038 * when occlusion queries are used.
1039 */
1040 pipeline->graphics.disable_out_of_order_rast_for_occlusion =
1041 !dsa_order_invariant.pass_set;
1042 }
1043
1044 /* No color buffers are enabled for writing. */
1045 if (!colormask)
1046 return true;
1047
1048 unsigned blendmask = colormask & blend->blend_enable_4bit;
1049
1050 if (blendmask) {
1051 /* Only commutative blending. */
1052 if (blendmask & ~blend->commutative_4bit)
1053 return false;
1054
1055 if (!dsa_order_invariant.pass_set)
1056 return false;
1057 }
1058
1059 if (colormask & ~blendmask)
1060 return false;
1061
1062 return true;
1063 }
1064
1065 static void
1066 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1067 struct radv_blend_state *blend,
1068 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1069 {
1070 const VkPipelineMultisampleStateCreateInfo *vkms = radv_pipeline_get_multisample_state(pCreateInfo);
1071 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1072 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1073 bool out_of_order_rast = false;
1074 int ps_iter_samples = 1;
1075 uint32_t mask = 0xffff;
1076
1077 if (vkms) {
1078 ms->num_samples = vkms->rasterizationSamples;
1079
1080 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
1081 *
1082 * "Sample shading is enabled for a graphics pipeline:
1083 *
1084 * - If the interface of the fragment shader entry point of the
1085 * graphics pipeline includes an input variable decorated
1086 * with SampleId or SamplePosition. In this case
1087 * minSampleShadingFactor takes the value 1.0.
1088 * - Else if the sampleShadingEnable member of the
1089 * VkPipelineMultisampleStateCreateInfo structure specified
1090 * when creating the graphics pipeline is set to VK_TRUE. In
1091 * this case minSampleShadingFactor takes the value of
1092 * VkPipelineMultisampleStateCreateInfo::minSampleShading.
1093 *
1094 * Otherwise, sample shading is considered disabled."
1095 */
1096 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.force_persample) {
1097 ps_iter_samples = ms->num_samples;
1098 } else {
1099 ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo);
1100 }
1101 } else {
1102 ms->num_samples = 1;
1103 }
1104
1105 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
1106 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
1107 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
1108 /* Out-of-order rasterization is explicitly enabled by the
1109 * application.
1110 */
1111 out_of_order_rast = true;
1112 } else {
1113 /* Determine if the driver can enable out-of-order
1114 * rasterization internally.
1115 */
1116 out_of_order_rast =
1117 radv_pipeline_out_of_order_rast(pipeline, blend, pCreateInfo);
1118 }
1119
1120 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1121 ms->pa_sc_aa_config = 0;
1122 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1123 S_028804_INCOHERENT_EQAA_READS(1) |
1124 S_028804_INTERPOLATE_COMP_Z(1) |
1125 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1126 ms->pa_sc_mode_cntl_1 =
1127 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1128 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1129 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
1130 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1131 /* always 1: */
1132 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1133 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1134 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1135 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1136 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1137 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1138 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9) |
1139 S_028A48_VPORT_SCISSOR_ENABLE(1);
1140
1141 const VkPipelineRasterizationLineStateCreateInfoEXT *rast_line =
1142 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
1143 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT);
1144 if (rast_line) {
1145 ms->pa_sc_mode_cntl_0 |= S_028A48_LINE_STIPPLE_ENABLE(rast_line->stippledLineEnable);
1146 if (rast_line->lineRasterizationMode == VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT) {
1147 /* From the Vulkan spec 1.1.129:
1148 *
1149 * "When VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT lines
1150 * are being rasterized, sample locations may all be
1151 * treated as being at the pixel center (this may
1152 * affect attribute and depth interpolation)."
1153 */
1154 ms->num_samples = 1;
1155 }
1156 }
1157
1158 if (ms->num_samples > 1) {
1159 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1160 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1161 uint32_t z_samples = subpass->depth_stencil_attachment ? subpass->depth_sample_count : ms->num_samples;
1162 unsigned log_samples = util_logbase2(ms->num_samples);
1163 unsigned log_z_samples = util_logbase2(z_samples);
1164 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
1165 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
1166 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1167 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples) |
1168 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1169 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1170 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1171 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1172 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples)) |
1173 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples) | /* CM_R_028BE0_PA_SC_AA_CONFIG */
1174 S_028BE0_COVERED_CENTROID_IS_CENTER_GFX103(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3);
1175 ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1176 if (ps_iter_samples > 1)
1177 pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1178 }
1179
1180 if (vkms && vkms->pSampleMask) {
1181 mask = vkms->pSampleMask[0] & 0xffff;
1182 }
1183
1184 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1185 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1186 }
1187
1188 static bool
1189 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1190 {
1191 switch (topology) {
1192 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1193 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1194 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1195 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1196 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1197 return false;
1198 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1199 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1200 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1201 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1202 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1203 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1204 return true;
1205 default:
1206 unreachable("unhandled primitive type");
1207 }
1208 }
1209
1210 static uint32_t
1211 si_translate_prim(enum VkPrimitiveTopology topology)
1212 {
1213 switch (topology) {
1214 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1215 return V_008958_DI_PT_POINTLIST;
1216 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1217 return V_008958_DI_PT_LINELIST;
1218 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1219 return V_008958_DI_PT_LINESTRIP;
1220 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1221 return V_008958_DI_PT_TRILIST;
1222 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1223 return V_008958_DI_PT_TRISTRIP;
1224 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1225 return V_008958_DI_PT_TRIFAN;
1226 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1227 return V_008958_DI_PT_LINELIST_ADJ;
1228 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1229 return V_008958_DI_PT_LINESTRIP_ADJ;
1230 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1231 return V_008958_DI_PT_TRILIST_ADJ;
1232 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1233 return V_008958_DI_PT_TRISTRIP_ADJ;
1234 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1235 return V_008958_DI_PT_PATCH;
1236 default:
1237 assert(0);
1238 return 0;
1239 }
1240 }
1241
1242 static uint32_t
1243 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1244 {
1245 switch (gl_prim) {
1246 case 0: /* GL_POINTS */
1247 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1248 case 1: /* GL_LINES */
1249 case 3: /* GL_LINE_STRIP */
1250 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1251 case 0x8E7A: /* GL_ISOLINES */
1252 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1253
1254 case 4: /* GL_TRIANGLES */
1255 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1256 case 5: /* GL_TRIANGLE_STRIP */
1257 case 7: /* GL_QUADS */
1258 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1259 default:
1260 assert(0);
1261 return 0;
1262 }
1263 }
1264
1265 static uint32_t
1266 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1267 {
1268 switch (topology) {
1269 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1270 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1271 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1272 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1273 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1274 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1275 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1276 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1277 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1278 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1279 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1280 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1281 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1282 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1283 default:
1284 assert(0);
1285 return 0;
1286 }
1287 }
1288
1289 static unsigned radv_dynamic_state_mask(VkDynamicState state)
1290 {
1291 switch(state) {
1292 case VK_DYNAMIC_STATE_VIEWPORT:
1293 return RADV_DYNAMIC_VIEWPORT;
1294 case VK_DYNAMIC_STATE_SCISSOR:
1295 return RADV_DYNAMIC_SCISSOR;
1296 case VK_DYNAMIC_STATE_LINE_WIDTH:
1297 return RADV_DYNAMIC_LINE_WIDTH;
1298 case VK_DYNAMIC_STATE_DEPTH_BIAS:
1299 return RADV_DYNAMIC_DEPTH_BIAS;
1300 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
1301 return RADV_DYNAMIC_BLEND_CONSTANTS;
1302 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
1303 return RADV_DYNAMIC_DEPTH_BOUNDS;
1304 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
1305 return RADV_DYNAMIC_STENCIL_COMPARE_MASK;
1306 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
1307 return RADV_DYNAMIC_STENCIL_WRITE_MASK;
1308 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
1309 return RADV_DYNAMIC_STENCIL_REFERENCE;
1310 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT:
1311 return RADV_DYNAMIC_DISCARD_RECTANGLE;
1312 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT:
1313 return RADV_DYNAMIC_SAMPLE_LOCATIONS;
1314 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT:
1315 return RADV_DYNAMIC_LINE_STIPPLE;
1316 default:
1317 unreachable("Unhandled dynamic state");
1318 }
1319 }
1320
1321 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
1322 {
1323 uint32_t states = RADV_DYNAMIC_ALL;
1324
1325 /* If rasterization is disabled we do not care about any of the dynamic states,
1326 * since they are all rasterization related only. */
1327 if (pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
1328 return 0;
1329
1330 if (!pCreateInfo->pRasterizationState->depthBiasEnable)
1331 states &= ~RADV_DYNAMIC_DEPTH_BIAS;
1332
1333 if (!pCreateInfo->pDepthStencilState ||
1334 !pCreateInfo->pDepthStencilState->depthBoundsTestEnable)
1335 states &= ~RADV_DYNAMIC_DEPTH_BOUNDS;
1336
1337 if (!pCreateInfo->pDepthStencilState ||
1338 !pCreateInfo->pDepthStencilState->stencilTestEnable)
1339 states &= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK |
1340 RADV_DYNAMIC_STENCIL_WRITE_MASK |
1341 RADV_DYNAMIC_STENCIL_REFERENCE);
1342
1343 if (!vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT))
1344 states &= ~RADV_DYNAMIC_DISCARD_RECTANGLE;
1345
1346 if (!pCreateInfo->pMultisampleState ||
1347 !vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1348 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT))
1349 states &= ~RADV_DYNAMIC_SAMPLE_LOCATIONS;
1350
1351 if (!pCreateInfo->pRasterizationState ||
1352 !vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
1353 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT))
1354 states &= ~RADV_DYNAMIC_LINE_STIPPLE;
1355
1356 /* TODO: blend constants & line width. */
1357
1358 return states;
1359 }
1360
1361
1362 static void
1363 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1364 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1365 {
1366 uint32_t needed_states = radv_pipeline_needed_dynamic_state(pCreateInfo);
1367 uint32_t states = needed_states;
1368 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1369 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1370
1371 pipeline->dynamic_state = default_dynamic_state;
1372 pipeline->graphics.needed_dynamic_state = needed_states;
1373
1374 if (pCreateInfo->pDynamicState) {
1375 /* Remove all of the states that are marked as dynamic */
1376 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1377 for (uint32_t s = 0; s < count; s++)
1378 states &= ~radv_dynamic_state_mask(pCreateInfo->pDynamicState->pDynamicStates[s]);
1379 }
1380
1381 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1382
1383 if (needed_states & RADV_DYNAMIC_VIEWPORT) {
1384 assert(pCreateInfo->pViewportState);
1385
1386 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1387 if (states & RADV_DYNAMIC_VIEWPORT) {
1388 typed_memcpy(dynamic->viewport.viewports,
1389 pCreateInfo->pViewportState->pViewports,
1390 pCreateInfo->pViewportState->viewportCount);
1391 }
1392 }
1393
1394 if (needed_states & RADV_DYNAMIC_SCISSOR) {
1395 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1396 if (states & RADV_DYNAMIC_SCISSOR) {
1397 typed_memcpy(dynamic->scissor.scissors,
1398 pCreateInfo->pViewportState->pScissors,
1399 pCreateInfo->pViewportState->scissorCount);
1400 }
1401 }
1402
1403 if (states & RADV_DYNAMIC_LINE_WIDTH) {
1404 assert(pCreateInfo->pRasterizationState);
1405 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1406 }
1407
1408 if (states & RADV_DYNAMIC_DEPTH_BIAS) {
1409 assert(pCreateInfo->pRasterizationState);
1410 dynamic->depth_bias.bias =
1411 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1412 dynamic->depth_bias.clamp =
1413 pCreateInfo->pRasterizationState->depthBiasClamp;
1414 dynamic->depth_bias.slope =
1415 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1416 }
1417
1418 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1419 *
1420 * pColorBlendState is [...] NULL if the pipeline has rasterization
1421 * disabled or if the subpass of the render pass the pipeline is
1422 * created against does not use any color attachments.
1423 */
1424 if (subpass->has_color_att && states & RADV_DYNAMIC_BLEND_CONSTANTS) {
1425 assert(pCreateInfo->pColorBlendState);
1426 typed_memcpy(dynamic->blend_constants,
1427 pCreateInfo->pColorBlendState->blendConstants, 4);
1428 }
1429
1430 /* If there is no depthstencil attachment, then don't read
1431 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1432 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1433 * no need to override the depthstencil defaults in
1434 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1435 *
1436 * Section 9.2 of the Vulkan 1.0.15 spec says:
1437 *
1438 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1439 * disabled or if the subpass of the render pass the pipeline is created
1440 * against does not use a depth/stencil attachment.
1441 */
1442 if (needed_states && subpass->depth_stencil_attachment) {
1443 assert(pCreateInfo->pDepthStencilState);
1444
1445 if (states & RADV_DYNAMIC_DEPTH_BOUNDS) {
1446 dynamic->depth_bounds.min =
1447 pCreateInfo->pDepthStencilState->minDepthBounds;
1448 dynamic->depth_bounds.max =
1449 pCreateInfo->pDepthStencilState->maxDepthBounds;
1450 }
1451
1452 if (states & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
1453 dynamic->stencil_compare_mask.front =
1454 pCreateInfo->pDepthStencilState->front.compareMask;
1455 dynamic->stencil_compare_mask.back =
1456 pCreateInfo->pDepthStencilState->back.compareMask;
1457 }
1458
1459 if (states & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
1460 dynamic->stencil_write_mask.front =
1461 pCreateInfo->pDepthStencilState->front.writeMask;
1462 dynamic->stencil_write_mask.back =
1463 pCreateInfo->pDepthStencilState->back.writeMask;
1464 }
1465
1466 if (states & RADV_DYNAMIC_STENCIL_REFERENCE) {
1467 dynamic->stencil_reference.front =
1468 pCreateInfo->pDepthStencilState->front.reference;
1469 dynamic->stencil_reference.back =
1470 pCreateInfo->pDepthStencilState->back.reference;
1471 }
1472 }
1473
1474 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
1475 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
1476 if (needed_states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1477 dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount;
1478 if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1479 typed_memcpy(dynamic->discard_rectangle.rectangles,
1480 discard_rectangle_info->pDiscardRectangles,
1481 discard_rectangle_info->discardRectangleCount);
1482 }
1483 }
1484
1485 if (needed_states & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
1486 const VkPipelineSampleLocationsStateCreateInfoEXT *sample_location_info =
1487 vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1488 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
1489 /* If sampleLocationsEnable is VK_FALSE, the default sample
1490 * locations are used and the values specified in
1491 * sampleLocationsInfo are ignored.
1492 */
1493 if (sample_location_info->sampleLocationsEnable) {
1494 const VkSampleLocationsInfoEXT *pSampleLocationsInfo =
1495 &sample_location_info->sampleLocationsInfo;
1496
1497 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
1498
1499 dynamic->sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
1500 dynamic->sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
1501 dynamic->sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
1502 typed_memcpy(&dynamic->sample_location.locations[0],
1503 pSampleLocationsInfo->pSampleLocations,
1504 pSampleLocationsInfo->sampleLocationsCount);
1505 }
1506 }
1507
1508 const VkPipelineRasterizationLineStateCreateInfoEXT *rast_line_info =
1509 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
1510 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT);
1511 if (needed_states & RADV_DYNAMIC_LINE_STIPPLE) {
1512 dynamic->line_stipple.factor = rast_line_info->lineStippleFactor;
1513 dynamic->line_stipple.pattern = rast_line_info->lineStipplePattern;
1514 }
1515
1516 pipeline->dynamic_state.mask = states;
1517 }
1518
1519 static void
1520 gfx9_get_gs_info(const struct radv_pipeline_key *key,
1521 const struct radv_pipeline *pipeline,
1522 nir_shader **nir,
1523 struct radv_shader_info *infos,
1524 struct gfx9_gs_info *out)
1525 {
1526 struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY];
1527 struct radv_es_output_info *es_info;
1528 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
1529 es_info = nir[MESA_SHADER_TESS_CTRL] ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1530 else
1531 es_info = nir[MESA_SHADER_TESS_CTRL] ?
1532 &infos[MESA_SHADER_TESS_EVAL].tes.es_info :
1533 &infos[MESA_SHADER_VERTEX].vs.es_info;
1534
1535 unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
1536 bool uses_adjacency;
1537 switch(key->topology) {
1538 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1539 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1540 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1541 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1542 uses_adjacency = true;
1543 break;
1544 default:
1545 uses_adjacency = false;
1546 break;
1547 }
1548
1549 /* All these are in dwords: */
1550 /* We can't allow using the whole LDS, because GS waves compete with
1551 * other shader stages for LDS space. */
1552 const unsigned max_lds_size = 8 * 1024;
1553 const unsigned esgs_itemsize = es_info->esgs_itemsize / 4;
1554 unsigned esgs_lds_size;
1555
1556 /* All these are per subgroup: */
1557 const unsigned max_out_prims = 32 * 1024;
1558 const unsigned max_es_verts = 255;
1559 const unsigned ideal_gs_prims = 64;
1560 unsigned max_gs_prims, gs_prims;
1561 unsigned min_es_verts, es_verts, worst_case_es_verts;
1562
1563 if (uses_adjacency || gs_num_invocations > 1)
1564 max_gs_prims = 127 / gs_num_invocations;
1565 else
1566 max_gs_prims = 255;
1567
1568 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1569 * Make sure we don't go over the maximum value.
1570 */
1571 if (gs_info->gs.vertices_out > 0) {
1572 max_gs_prims = MIN2(max_gs_prims,
1573 max_out_prims /
1574 (gs_info->gs.vertices_out * gs_num_invocations));
1575 }
1576 assert(max_gs_prims > 0);
1577
1578 /* If the primitive has adjacency, halve the number of vertices
1579 * that will be reused in multiple primitives.
1580 */
1581 min_es_verts = gs_info->gs.vertices_in / (uses_adjacency ? 2 : 1);
1582
1583 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
1584 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
1585
1586 /* Compute ESGS LDS size based on the worst case number of ES vertices
1587 * needed to create the target number of GS prims per subgroup.
1588 */
1589 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1590
1591 /* If total LDS usage is too big, refactor partitions based on ratio
1592 * of ESGS item sizes.
1593 */
1594 if (esgs_lds_size > max_lds_size) {
1595 /* Our target GS Prims Per Subgroup was too large. Calculate
1596 * the maximum number of GS Prims Per Subgroup that will fit
1597 * into LDS, capped by the maximum that the hardware can support.
1598 */
1599 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
1600 max_gs_prims);
1601 assert(gs_prims > 0);
1602 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
1603 max_es_verts);
1604
1605 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1606 assert(esgs_lds_size <= max_lds_size);
1607 }
1608
1609 /* Now calculate remaining ESGS information. */
1610 if (esgs_lds_size)
1611 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
1612 else
1613 es_verts = max_es_verts;
1614
1615 /* Vertices for adjacency primitives are not always reused, so restore
1616 * it for ES_VERTS_PER_SUBGRP.
1617 */
1618 min_es_verts = gs_info->gs.vertices_in;
1619
1620 /* For normal primitives, the VGT only checks if they are past the ES
1621 * verts per subgroup after allocating a full GS primitive and if they
1622 * are, kick off a new subgroup. But if those additional ES verts are
1623 * unique (e.g. not reused) we need to make sure there is enough LDS
1624 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1625 */
1626 es_verts -= min_es_verts - 1;
1627
1628 uint32_t es_verts_per_subgroup = es_verts;
1629 uint32_t gs_prims_per_subgroup = gs_prims;
1630 uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
1631 uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out;
1632 out->lds_size = align(esgs_lds_size, 128) / 128;
1633 out->vgt_gs_onchip_cntl = S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) |
1634 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) |
1635 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup);
1636 out->vgt_gs_max_prims_per_subgroup = S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup);
1637 out->vgt_esgs_ring_itemsize = esgs_itemsize;
1638 assert(max_prims_per_subgroup <= max_out_prims);
1639 }
1640
1641 static void clamp_gsprims_to_esverts(unsigned *max_gsprims, unsigned max_esverts,
1642 unsigned min_verts_per_prim, bool use_adjacency)
1643 {
1644 unsigned max_reuse = max_esverts - min_verts_per_prim;
1645 if (use_adjacency)
1646 max_reuse /= 2;
1647 *max_gsprims = MIN2(*max_gsprims, 1 + max_reuse);
1648 }
1649
1650 static unsigned
1651 radv_get_num_input_vertices(nir_shader **nir)
1652 {
1653 if (nir[MESA_SHADER_GEOMETRY]) {
1654 nir_shader *gs = nir[MESA_SHADER_GEOMETRY];
1655
1656 return gs->info.gs.vertices_in;
1657 }
1658
1659 if (nir[MESA_SHADER_TESS_CTRL]) {
1660 nir_shader *tes = nir[MESA_SHADER_TESS_EVAL];
1661
1662 if (tes->info.tess.point_mode)
1663 return 1;
1664 if (tes->info.tess.primitive_mode == GL_ISOLINES)
1665 return 2;
1666 return 3;
1667 }
1668
1669 return 3;
1670 }
1671
1672 static void
1673 gfx10_get_ngg_info(const struct radv_pipeline_key *key,
1674 struct radv_pipeline *pipeline,
1675 nir_shader **nir,
1676 struct radv_shader_info *infos,
1677 struct gfx10_ngg_info *ngg)
1678 {
1679 struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY];
1680 struct radv_es_output_info *es_info =
1681 nir[MESA_SHADER_TESS_CTRL] ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1682 unsigned gs_type = nir[MESA_SHADER_GEOMETRY] ? MESA_SHADER_GEOMETRY : MESA_SHADER_VERTEX;
1683 unsigned max_verts_per_prim = radv_get_num_input_vertices(nir);
1684 unsigned min_verts_per_prim =
1685 gs_type == MESA_SHADER_GEOMETRY ? max_verts_per_prim : 1;
1686 unsigned gs_num_invocations = nir[MESA_SHADER_GEOMETRY] ? MAX2(gs_info->gs.invocations, 1) : 1;
1687 bool uses_adjacency;
1688 switch(key->topology) {
1689 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1690 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1691 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1692 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1693 uses_adjacency = true;
1694 break;
1695 default:
1696 uses_adjacency = false;
1697 break;
1698 }
1699
1700 /* All these are in dwords: */
1701 /* We can't allow using the whole LDS, because GS waves compete with
1702 * other shader stages for LDS space.
1703 *
1704 * TODO: We should really take the shader's internal LDS use into
1705 * account. The linker will fail if the size is greater than
1706 * 8K dwords.
1707 */
1708 const unsigned max_lds_size = 8 * 1024 - 768;
1709 const unsigned target_lds_size = max_lds_size;
1710 unsigned esvert_lds_size = 0;
1711 unsigned gsprim_lds_size = 0;
1712
1713 /* All these are per subgroup: */
1714 bool max_vert_out_per_gs_instance = false;
1715 unsigned max_esverts_base = 256;
1716 unsigned max_gsprims_base = 128; /* default prim group size clamp */
1717
1718 /* Hardware has the following non-natural restrictions on the value
1719 * of GE_CNTL.VERT_GRP_SIZE based on based on the primitive type of
1720 * the draw:
1721 * - at most 252 for any line input primitive type
1722 * - at most 251 for any quad input primitive type
1723 * - at most 251 for triangle strips with adjacency (this happens to
1724 * be the natural limit for triangle *lists* with adjacency)
1725 */
1726 max_esverts_base = MIN2(max_esverts_base, 251 + max_verts_per_prim - 1);
1727
1728 if (gs_type == MESA_SHADER_GEOMETRY) {
1729 unsigned max_out_verts_per_gsprim =
1730 gs_info->gs.vertices_out * gs_num_invocations;
1731
1732 if (max_out_verts_per_gsprim <= 256) {
1733 if (max_out_verts_per_gsprim) {
1734 max_gsprims_base = MIN2(max_gsprims_base,
1735 256 / max_out_verts_per_gsprim);
1736 }
1737 } else {
1738 /* Use special multi-cycling mode in which each GS
1739 * instance gets its own subgroup. Does not work with
1740 * tessellation. */
1741 max_vert_out_per_gs_instance = true;
1742 max_gsprims_base = 1;
1743 max_out_verts_per_gsprim = gs_info->gs.vertices_out;
1744 }
1745
1746 esvert_lds_size = es_info->esgs_itemsize / 4;
1747 gsprim_lds_size = (gs_info->gs.gsvs_vertex_size / 4 + 1) * max_out_verts_per_gsprim;
1748 } else {
1749 /* VS and TES. */
1750 /* LDS size for passing data from GS to ES. */
1751 struct radv_streamout_info *so_info = nir[MESA_SHADER_TESS_CTRL]
1752 ? &infos[MESA_SHADER_TESS_EVAL].so
1753 : &infos[MESA_SHADER_VERTEX].so;
1754
1755 if (so_info->num_outputs)
1756 esvert_lds_size = 4 * so_info->num_outputs + 1;
1757
1758 /* GS stores Primitive IDs (one DWORD) into LDS at the address
1759 * corresponding to the ES thread of the provoking vertex. All
1760 * ES threads load and export PrimitiveID for their thread.
1761 */
1762 if (!nir[MESA_SHADER_TESS_CTRL] &&
1763 infos[MESA_SHADER_VERTEX].vs.outinfo.export_prim_id)
1764 esvert_lds_size = MAX2(esvert_lds_size, 1);
1765 }
1766
1767 unsigned max_gsprims = max_gsprims_base;
1768 unsigned max_esverts = max_esverts_base;
1769
1770 if (esvert_lds_size)
1771 max_esverts = MIN2(max_esverts, target_lds_size / esvert_lds_size);
1772 if (gsprim_lds_size)
1773 max_gsprims = MIN2(max_gsprims, target_lds_size / gsprim_lds_size);
1774
1775 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1776 clamp_gsprims_to_esverts(&max_gsprims, max_esverts, min_verts_per_prim, uses_adjacency);
1777 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1778
1779 if (esvert_lds_size || gsprim_lds_size) {
1780 /* Now that we have a rough proportionality between esverts
1781 * and gsprims based on the primitive type, scale both of them
1782 * down simultaneously based on required LDS space.
1783 *
1784 * We could be smarter about this if we knew how much vertex
1785 * reuse to expect.
1786 */
1787 unsigned lds_total = max_esverts * esvert_lds_size +
1788 max_gsprims * gsprim_lds_size;
1789 if (lds_total > target_lds_size) {
1790 max_esverts = max_esverts * target_lds_size / lds_total;
1791 max_gsprims = max_gsprims * target_lds_size / lds_total;
1792
1793 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1794 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1795 min_verts_per_prim, uses_adjacency);
1796 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1797 }
1798 }
1799
1800 /* Round up towards full wave sizes for better ALU utilization. */
1801 if (!max_vert_out_per_gs_instance) {
1802 unsigned orig_max_esverts;
1803 unsigned orig_max_gsprims;
1804 unsigned wavesize;
1805
1806 if (gs_type == MESA_SHADER_GEOMETRY) {
1807 wavesize = gs_info->wave_size;
1808 } else {
1809 wavesize = nir[MESA_SHADER_TESS_CTRL]
1810 ? infos[MESA_SHADER_TESS_EVAL].wave_size
1811 : infos[MESA_SHADER_VERTEX].wave_size;
1812 }
1813
1814 do {
1815 orig_max_esverts = max_esverts;
1816 orig_max_gsprims = max_gsprims;
1817
1818 max_esverts = align(max_esverts, wavesize);
1819 max_esverts = MIN2(max_esverts, max_esverts_base);
1820 if (esvert_lds_size)
1821 max_esverts = MIN2(max_esverts,
1822 (max_lds_size - max_gsprims * gsprim_lds_size) /
1823 esvert_lds_size);
1824 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1825
1826 max_gsprims = align(max_gsprims, wavesize);
1827 max_gsprims = MIN2(max_gsprims, max_gsprims_base);
1828 if (gsprim_lds_size)
1829 max_gsprims = MIN2(max_gsprims,
1830 (max_lds_size - max_esverts * esvert_lds_size) /
1831 gsprim_lds_size);
1832 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1833 min_verts_per_prim, uses_adjacency);
1834 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1835 } while (orig_max_esverts != max_esverts || orig_max_gsprims != max_gsprims);
1836 }
1837
1838 /* Hardware restriction: minimum value of max_esverts */
1839 max_esverts = MAX2(max_esverts, 23 + max_verts_per_prim);
1840
1841 unsigned max_out_vertices =
1842 max_vert_out_per_gs_instance ? gs_info->gs.vertices_out :
1843 gs_type == MESA_SHADER_GEOMETRY ?
1844 max_gsprims * gs_num_invocations * gs_info->gs.vertices_out :
1845 max_esverts;
1846 assert(max_out_vertices <= 256);
1847
1848 unsigned prim_amp_factor = 1;
1849 if (gs_type == MESA_SHADER_GEOMETRY) {
1850 /* Number of output primitives per GS input primitive after
1851 * GS instancing. */
1852 prim_amp_factor = gs_info->gs.vertices_out;
1853 }
1854
1855 /* The GE only checks against the maximum number of ES verts after
1856 * allocating a full GS primitive. So we need to ensure that whenever
1857 * this check passes, there is enough space for a full primitive without
1858 * vertex reuse.
1859 */
1860 ngg->hw_max_esverts = max_esverts - max_verts_per_prim + 1;
1861 ngg->max_gsprims = max_gsprims;
1862 ngg->max_out_verts = max_out_vertices;
1863 ngg->prim_amp_factor = prim_amp_factor;
1864 ngg->max_vert_out_per_gs_instance = max_vert_out_per_gs_instance;
1865 ngg->ngg_emit_size = max_gsprims * gsprim_lds_size;
1866 ngg->esgs_ring_size = 4 * max_esverts * esvert_lds_size;
1867
1868 if (gs_type == MESA_SHADER_GEOMETRY) {
1869 ngg->vgt_esgs_ring_itemsize = es_info->esgs_itemsize / 4;
1870 } else {
1871 ngg->vgt_esgs_ring_itemsize = 1;
1872 }
1873
1874 pipeline->graphics.esgs_ring_size = ngg->esgs_ring_size;
1875
1876 assert(ngg->hw_max_esverts >= 24); /* HW limitation */
1877 }
1878
1879 static void
1880 calculate_gs_ring_sizes(struct radv_pipeline *pipeline,
1881 const struct gfx9_gs_info *gs)
1882 {
1883 struct radv_device *device = pipeline->device;
1884 unsigned num_se = device->physical_device->rad_info.max_se;
1885 unsigned wave_size = 64;
1886 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1887 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
1888 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
1889 */
1890 unsigned gs_vertex_reuse =
1891 (device->physical_device->rad_info.chip_class >= GFX8 ? 32 : 16) * num_se;
1892 unsigned alignment = 256 * num_se;
1893 /* The maximum size is 63.999 MB per SE. */
1894 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1895 struct radv_shader_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1896
1897 /* Calculate the minimum size. */
1898 unsigned min_esgs_ring_size = align(gs->vgt_esgs_ring_itemsize * 4 * gs_vertex_reuse *
1899 wave_size, alignment);
1900 /* These are recommended sizes, not minimum sizes. */
1901 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1902 gs->vgt_esgs_ring_itemsize * 4 * gs_info->gs.vertices_in;
1903 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1904 gs_info->gs.max_gsvs_emit_size;
1905
1906 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1907 esgs_ring_size = align(esgs_ring_size, alignment);
1908 gsvs_ring_size = align(gsvs_ring_size, alignment);
1909
1910 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
1911 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1912
1913 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1914 }
1915
1916 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1917 unsigned *lds_size)
1918 {
1919 /* If tessellation is all offchip and on-chip GS isn't used, this
1920 * workaround is not needed.
1921 */
1922 return;
1923
1924 /* SPI barrier management bug:
1925 * Make sure we have at least 4k of LDS in use to avoid the bug.
1926 * It applies to workgroup sizes of more than one wavefront.
1927 */
1928 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1929 device->physical_device->rad_info.family == CHIP_KABINI)
1930 *lds_size = MAX2(*lds_size, 8);
1931 }
1932
1933 struct radv_shader_variant *
1934 radv_get_shader(struct radv_pipeline *pipeline,
1935 gl_shader_stage stage)
1936 {
1937 if (stage == MESA_SHADER_VERTEX) {
1938 if (pipeline->shaders[MESA_SHADER_VERTEX])
1939 return pipeline->shaders[MESA_SHADER_VERTEX];
1940 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
1941 return pipeline->shaders[MESA_SHADER_TESS_CTRL];
1942 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1943 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1944 } else if (stage == MESA_SHADER_TESS_EVAL) {
1945 if (!radv_pipeline_has_tess(pipeline))
1946 return NULL;
1947 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
1948 return pipeline->shaders[MESA_SHADER_TESS_EVAL];
1949 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1950 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1951 }
1952 return pipeline->shaders[stage];
1953 }
1954
1955 static struct radv_tessellation_state
1956 calculate_tess_state(struct radv_pipeline *pipeline,
1957 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1958 {
1959 unsigned num_tcs_input_cp;
1960 unsigned num_tcs_output_cp;
1961 unsigned lds_size;
1962 unsigned num_patches;
1963 struct radv_tessellation_state tess = {0};
1964
1965 num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1966 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1967 num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
1968
1969 lds_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.lds_size;
1970
1971 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
1972 assert(lds_size <= 65536);
1973 lds_size = align(lds_size, 512) / 512;
1974 } else {
1975 assert(lds_size <= 32768);
1976 lds_size = align(lds_size, 256) / 256;
1977 }
1978 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1979
1980 tess.lds_size = lds_size;
1981
1982 tess.ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1983 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1984 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1985 tess.num_patches = num_patches;
1986
1987 struct radv_shader_variant *tes = radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL);
1988 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1989
1990 switch (tes->info.tes.primitive_mode) {
1991 case GL_TRIANGLES:
1992 type = V_028B6C_TESS_TRIANGLE;
1993 break;
1994 case GL_QUADS:
1995 type = V_028B6C_TESS_QUAD;
1996 break;
1997 case GL_ISOLINES:
1998 type = V_028B6C_TESS_ISOLINE;
1999 break;
2000 }
2001
2002 switch (tes->info.tes.spacing) {
2003 case TESS_SPACING_EQUAL:
2004 partitioning = V_028B6C_PART_INTEGER;
2005 break;
2006 case TESS_SPACING_FRACTIONAL_ODD:
2007 partitioning = V_028B6C_PART_FRAC_ODD;
2008 break;
2009 case TESS_SPACING_FRACTIONAL_EVEN:
2010 partitioning = V_028B6C_PART_FRAC_EVEN;
2011 break;
2012 default:
2013 break;
2014 }
2015
2016 bool ccw = tes->info.tes.ccw;
2017 const VkPipelineTessellationDomainOriginStateCreateInfo *domain_origin_state =
2018 vk_find_struct_const(pCreateInfo->pTessellationState,
2019 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO);
2020
2021 if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT)
2022 ccw = !ccw;
2023
2024 if (tes->info.tes.point_mode)
2025 topology = V_028B6C_OUTPUT_POINT;
2026 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
2027 topology = V_028B6C_OUTPUT_LINE;
2028 else if (ccw)
2029 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
2030 else
2031 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
2032
2033 if (pipeline->device->physical_device->rad_info.has_distributed_tess) {
2034 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
2035 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
2036 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
2037 else
2038 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
2039 } else
2040 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
2041
2042 tess.tf_param = S_028B6C_TYPE(type) |
2043 S_028B6C_PARTITIONING(partitioning) |
2044 S_028B6C_TOPOLOGY(topology) |
2045 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
2046
2047 return tess;
2048 }
2049
2050 static const struct radv_prim_vertex_count prim_size_table[] = {
2051 [V_008958_DI_PT_NONE] = {0, 0},
2052 [V_008958_DI_PT_POINTLIST] = {1, 1},
2053 [V_008958_DI_PT_LINELIST] = {2, 2},
2054 [V_008958_DI_PT_LINESTRIP] = {2, 1},
2055 [V_008958_DI_PT_TRILIST] = {3, 3},
2056 [V_008958_DI_PT_TRIFAN] = {3, 1},
2057 [V_008958_DI_PT_TRISTRIP] = {3, 1},
2058 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
2059 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
2060 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
2061 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
2062 [V_008958_DI_PT_RECTLIST] = {3, 3},
2063 [V_008958_DI_PT_LINELOOP] = {2, 1},
2064 [V_008958_DI_PT_POLYGON] = {3, 1},
2065 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
2066 };
2067
2068 static const struct radv_vs_output_info *get_vs_output_info(const struct radv_pipeline *pipeline)
2069 {
2070 if (radv_pipeline_has_gs(pipeline))
2071 if (radv_pipeline_has_ngg(pipeline))
2072 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.vs.outinfo;
2073 else
2074 return &pipeline->gs_copy_shader->info.vs.outinfo;
2075 else if (radv_pipeline_has_tess(pipeline))
2076 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
2077 else
2078 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
2079 }
2080
2081 static void
2082 radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
2083 {
2084 nir_shader* ordered_shaders[MESA_SHADER_STAGES];
2085 int shader_count = 0;
2086
2087 if(shaders[MESA_SHADER_FRAGMENT]) {
2088 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
2089 }
2090 if(shaders[MESA_SHADER_GEOMETRY]) {
2091 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
2092 }
2093 if(shaders[MESA_SHADER_TESS_EVAL]) {
2094 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
2095 }
2096 if(shaders[MESA_SHADER_TESS_CTRL]) {
2097 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
2098 }
2099 if(shaders[MESA_SHADER_VERTEX]) {
2100 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
2101 }
2102
2103 if (shader_count > 1) {
2104 unsigned first = ordered_shaders[shader_count - 1]->info.stage;
2105 unsigned last = ordered_shaders[0]->info.stage;
2106
2107 if (ordered_shaders[0]->info.stage == MESA_SHADER_FRAGMENT &&
2108 ordered_shaders[1]->info.has_transform_feedback_varyings)
2109 nir_link_xfb_varyings(ordered_shaders[1], ordered_shaders[0]);
2110
2111 for (int i = 0; i < shader_count; ++i) {
2112 nir_variable_mode mask = 0;
2113
2114 if (ordered_shaders[i]->info.stage != first)
2115 mask = mask | nir_var_shader_in;
2116
2117 if (ordered_shaders[i]->info.stage != last)
2118 mask = mask | nir_var_shader_out;
2119
2120 nir_lower_io_to_scalar_early(ordered_shaders[i], mask);
2121 radv_optimize_nir(ordered_shaders[i], false, false);
2122 }
2123 }
2124
2125 for (int i = 1; i < shader_count; ++i) {
2126 nir_lower_io_arrays_to_elements(ordered_shaders[i],
2127 ordered_shaders[i - 1]);
2128
2129 if (nir_link_opt_varyings(ordered_shaders[i],
2130 ordered_shaders[i - 1]))
2131 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2132
2133 nir_remove_dead_variables(ordered_shaders[i],
2134 nir_var_shader_out, NULL);
2135 nir_remove_dead_variables(ordered_shaders[i - 1],
2136 nir_var_shader_in, NULL);
2137
2138 bool progress = nir_remove_unused_varyings(ordered_shaders[i],
2139 ordered_shaders[i - 1]);
2140
2141 nir_compact_varyings(ordered_shaders[i],
2142 ordered_shaders[i - 1], true);
2143
2144 if (progress) {
2145 if (nir_lower_global_vars_to_local(ordered_shaders[i])) {
2146 ac_lower_indirect_derefs(ordered_shaders[i],
2147 pipeline->device->physical_device->rad_info.chip_class);
2148 }
2149 radv_optimize_nir(ordered_shaders[i], false, false);
2150
2151 if (nir_lower_global_vars_to_local(ordered_shaders[i - 1])) {
2152 ac_lower_indirect_derefs(ordered_shaders[i - 1],
2153 pipeline->device->physical_device->rad_info.chip_class);
2154 }
2155 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2156 }
2157 }
2158 }
2159
2160 static void
2161 radv_set_linked_driver_locations(struct radv_pipeline *pipeline, nir_shader **shaders,
2162 struct radv_shader_info infos[MESA_SHADER_STAGES])
2163 {
2164 bool has_tess = shaders[MESA_SHADER_TESS_CTRL];
2165 bool has_gs = shaders[MESA_SHADER_GEOMETRY];
2166
2167 if (!has_tess && !has_gs)
2168 return;
2169
2170 unsigned vs_info_idx = MESA_SHADER_VERTEX;
2171 unsigned tes_info_idx = MESA_SHADER_TESS_EVAL;
2172
2173 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
2174 /* These are merged into the next stage */
2175 vs_info_idx = has_tess ? MESA_SHADER_TESS_CTRL : MESA_SHADER_GEOMETRY;
2176 tes_info_idx = has_gs ? MESA_SHADER_GEOMETRY : MESA_SHADER_TESS_EVAL;
2177 }
2178
2179 if (has_tess) {
2180 nir_linked_io_var_info vs2tcs =
2181 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_VERTEX], shaders[MESA_SHADER_TESS_CTRL]);
2182 nir_linked_io_var_info tcs2tes =
2183 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_TESS_CTRL], shaders[MESA_SHADER_TESS_EVAL]);
2184
2185 infos[vs_info_idx].vs.num_linked_outputs = vs2tcs.num_linked_io_vars;
2186 infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_inputs = vs2tcs.num_linked_io_vars;
2187 infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_outputs = tcs2tes.num_linked_io_vars;
2188 infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_patch_outputs = tcs2tes.num_linked_patch_io_vars;
2189 infos[tes_info_idx].tes.num_linked_inputs = tcs2tes.num_linked_io_vars;
2190 infos[tes_info_idx].tes.num_linked_patch_inputs = tcs2tes.num_linked_patch_io_vars;
2191
2192 if (has_gs) {
2193 nir_linked_io_var_info tes2gs =
2194 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_TESS_EVAL], shaders[MESA_SHADER_GEOMETRY]);
2195
2196 infos[tes_info_idx].tes.num_linked_outputs = tes2gs.num_linked_io_vars;
2197 infos[MESA_SHADER_GEOMETRY].gs.num_linked_inputs = tes2gs.num_linked_io_vars;
2198 }
2199 } else if (has_gs) {
2200 nir_linked_io_var_info vs2gs =
2201 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_VERTEX], shaders[MESA_SHADER_GEOMETRY]);
2202
2203 infos[vs_info_idx].vs.num_linked_outputs = vs2gs.num_linked_io_vars;
2204 infos[MESA_SHADER_GEOMETRY].gs.num_linked_inputs = vs2gs.num_linked_io_vars;
2205 }
2206 }
2207
2208 static uint32_t
2209 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo *input_state,
2210 uint32_t attrib_binding)
2211 {
2212 for (uint32_t i = 0; i < input_state->vertexBindingDescriptionCount; i++) {
2213 const VkVertexInputBindingDescription *input_binding =
2214 &input_state->pVertexBindingDescriptions[i];
2215
2216 if (input_binding->binding == attrib_binding)
2217 return input_binding->stride;
2218 }
2219
2220 return 0;
2221 }
2222
2223 static struct radv_pipeline_key
2224 radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
2225 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2226 const struct radv_blend_state *blend,
2227 bool has_view_index)
2228 {
2229 const VkPipelineVertexInputStateCreateInfo *input_state =
2230 pCreateInfo->pVertexInputState;
2231 const VkPipelineVertexInputDivisorStateCreateInfoEXT *divisor_state =
2232 vk_find_struct_const(input_state->pNext, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT);
2233
2234 struct radv_pipeline_key key;
2235 memset(&key, 0, sizeof(key));
2236
2237 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
2238 key.optimisations_disabled = 1;
2239
2240 key.has_multiview_view_index = has_view_index;
2241
2242 uint32_t binding_input_rate = 0;
2243 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
2244 for (unsigned i = 0; i < input_state->vertexBindingDescriptionCount; ++i) {
2245 if (input_state->pVertexBindingDescriptions[i].inputRate) {
2246 unsigned binding = input_state->pVertexBindingDescriptions[i].binding;
2247 binding_input_rate |= 1u << binding;
2248 instance_rate_divisors[binding] = 1;
2249 }
2250 }
2251 if (divisor_state) {
2252 for (unsigned i = 0; i < divisor_state->vertexBindingDivisorCount; ++i) {
2253 instance_rate_divisors[divisor_state->pVertexBindingDivisors[i].binding] =
2254 divisor_state->pVertexBindingDivisors[i].divisor;
2255 }
2256 }
2257
2258 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
2259 const VkVertexInputAttributeDescription *desc =
2260 &input_state->pVertexAttributeDescriptions[i];
2261 const struct vk_format_description *format_desc;
2262 unsigned location = desc->location;
2263 unsigned binding = desc->binding;
2264 unsigned num_format, data_format;
2265 int first_non_void;
2266
2267 if (binding_input_rate & (1u << binding)) {
2268 key.instance_rate_inputs |= 1u << location;
2269 key.instance_rate_divisors[location] = instance_rate_divisors[binding];
2270 }
2271
2272 format_desc = vk_format_description(desc->format);
2273 first_non_void = vk_format_get_first_non_void_channel(desc->format);
2274
2275 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
2276 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
2277
2278 key.vertex_attribute_formats[location] = data_format | (num_format << 4);
2279 key.vertex_attribute_bindings[location] = desc->binding;
2280 key.vertex_attribute_offsets[location] = desc->offset;
2281 key.vertex_attribute_strides[location] = radv_get_attrib_stride(input_state, desc->binding);
2282
2283 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8 &&
2284 pipeline->device->physical_device->rad_info.family != CHIP_STONEY) {
2285 VkFormat format = input_state->pVertexAttributeDescriptions[i].format;
2286 uint64_t adjust;
2287 switch(format) {
2288 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2289 case VK_FORMAT_A2B10G10R10_SNORM_PACK32:
2290 adjust = RADV_ALPHA_ADJUST_SNORM;
2291 break;
2292 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2293 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32:
2294 adjust = RADV_ALPHA_ADJUST_SSCALED;
2295 break;
2296 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2297 case VK_FORMAT_A2B10G10R10_SINT_PACK32:
2298 adjust = RADV_ALPHA_ADJUST_SINT;
2299 break;
2300 default:
2301 adjust = 0;
2302 break;
2303 }
2304 key.vertex_alpha_adjust |= adjust << (2 * location);
2305 }
2306
2307 switch (desc->format) {
2308 case VK_FORMAT_B8G8R8A8_UNORM:
2309 case VK_FORMAT_B8G8R8A8_SNORM:
2310 case VK_FORMAT_B8G8R8A8_USCALED:
2311 case VK_FORMAT_B8G8R8A8_SSCALED:
2312 case VK_FORMAT_B8G8R8A8_UINT:
2313 case VK_FORMAT_B8G8R8A8_SINT:
2314 case VK_FORMAT_B8G8R8A8_SRGB:
2315 case VK_FORMAT_A2R10G10B10_UNORM_PACK32:
2316 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2317 case VK_FORMAT_A2R10G10B10_USCALED_PACK32:
2318 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2319 case VK_FORMAT_A2R10G10B10_UINT_PACK32:
2320 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2321 key.vertex_post_shuffle |= 1 << location;
2322 break;
2323 default:
2324 break;
2325 }
2326 }
2327
2328 const VkPipelineTessellationStateCreateInfo *tess =
2329 radv_pipeline_get_tessellation_state(pCreateInfo);
2330 if (tess)
2331 key.tess_input_vertices = tess->patchControlPoints;
2332
2333 const VkPipelineMultisampleStateCreateInfo *vkms =
2334 radv_pipeline_get_multisample_state(pCreateInfo);
2335 if (vkms && vkms->rasterizationSamples > 1) {
2336 uint32_t num_samples = vkms->rasterizationSamples;
2337 uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo);
2338 key.num_samples = num_samples;
2339 key.log2_ps_iter_samples = util_logbase2(ps_iter_samples);
2340 }
2341
2342 key.col_format = blend->spi_shader_col_format;
2343 key.is_dual_src = blend->mrt0_is_dual_src;
2344 if (pipeline->device->physical_device->rad_info.chip_class < GFX8)
2345 radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.is_int8, &key.is_int10);
2346
2347 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10)
2348 key.topology = pCreateInfo->pInputAssemblyState->topology;
2349
2350 return key;
2351 }
2352
2353 static bool
2354 radv_nir_stage_uses_xfb(const nir_shader *nir)
2355 {
2356 nir_xfb_info *xfb = nir_gather_xfb_info(nir, NULL);
2357 bool uses_xfb = !!xfb;
2358
2359 ralloc_free(xfb);
2360 return uses_xfb;
2361 }
2362
2363 static void
2364 radv_fill_shader_keys(struct radv_device *device,
2365 struct radv_shader_variant_key *keys,
2366 const struct radv_pipeline_key *key,
2367 nir_shader **nir)
2368 {
2369 keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
2370 keys[MESA_SHADER_VERTEX].vs.alpha_adjust = key->vertex_alpha_adjust;
2371 keys[MESA_SHADER_VERTEX].vs.post_shuffle = key->vertex_post_shuffle;
2372 for (unsigned i = 0; i < MAX_VERTEX_ATTRIBS; ++i) {
2373 keys[MESA_SHADER_VERTEX].vs.instance_rate_divisors[i] = key->instance_rate_divisors[i];
2374 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_formats[i] = key->vertex_attribute_formats[i];
2375 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_bindings[i] = key->vertex_attribute_bindings[i];
2376 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_offsets[i] = key->vertex_attribute_offsets[i];
2377 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_strides[i] = key->vertex_attribute_strides[i];
2378 }
2379 keys[MESA_SHADER_VERTEX].vs.outprim = si_conv_prim_to_gs_out(key->topology);
2380
2381 if (nir[MESA_SHADER_TESS_CTRL]) {
2382 keys[MESA_SHADER_VERTEX].vs_common_out.as_ls = true;
2383 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = 0;
2384 keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices;
2385 keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
2386
2387 keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
2388 }
2389
2390 if (nir[MESA_SHADER_GEOMETRY]) {
2391 if (nir[MESA_SHADER_TESS_CTRL])
2392 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_es = true;
2393 else
2394 keys[MESA_SHADER_VERTEX].vs_common_out.as_es = true;
2395 }
2396
2397 if (device->physical_device->use_ngg) {
2398 if (nir[MESA_SHADER_TESS_CTRL]) {
2399 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = true;
2400 } else {
2401 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = true;
2402 }
2403
2404 if (nir[MESA_SHADER_TESS_CTRL] &&
2405 nir[MESA_SHADER_GEOMETRY] &&
2406 nir[MESA_SHADER_GEOMETRY]->info.gs.invocations *
2407 nir[MESA_SHADER_GEOMETRY]->info.gs.vertices_out > 256) {
2408 /* Fallback to the legacy path if tessellation is
2409 * enabled with extreme geometry because
2410 * EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it
2411 * might hang.
2412 */
2413 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2414 }
2415
2416 if (!device->physical_device->use_ngg_gs) {
2417 if (nir[MESA_SHADER_GEOMETRY]) {
2418 if (nir[MESA_SHADER_TESS_CTRL])
2419 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2420 else
2421 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2422 }
2423 }
2424
2425 gl_shader_stage last_xfb_stage = MESA_SHADER_VERTEX;
2426
2427 for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
2428 if (nir[i])
2429 last_xfb_stage = i;
2430 }
2431
2432 bool uses_xfb = nir[last_xfb_stage] &&
2433 radv_nir_stage_uses_xfb(nir[last_xfb_stage]);
2434
2435 if (!device->physical_device->use_ngg_streamout && uses_xfb) {
2436 if (nir[MESA_SHADER_TESS_CTRL])
2437 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2438 else
2439 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2440 }
2441
2442 /* Determine if the pipeline is eligible for the NGG passthrough
2443 * mode. It can't be enabled for geometry shaders, for NGG
2444 * streamout or for vertex shaders that export the primitive ID
2445 * (this is checked later because we don't have the info here.)
2446 */
2447 if (!nir[MESA_SHADER_GEOMETRY] && !uses_xfb) {
2448 if (nir[MESA_SHADER_TESS_CTRL] &&
2449 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg) {
2450 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg_passthrough = true;
2451 } else if (nir[MESA_SHADER_VERTEX] &&
2452 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg) {
2453 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg_passthrough = true;
2454 }
2455 }
2456 }
2457
2458 for(int i = 0; i < MESA_SHADER_STAGES; ++i)
2459 keys[i].has_multiview_view_index = key->has_multiview_view_index;
2460
2461 keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format;
2462 keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8;
2463 keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
2464 keys[MESA_SHADER_FRAGMENT].fs.log2_ps_iter_samples = key->log2_ps_iter_samples;
2465 keys[MESA_SHADER_FRAGMENT].fs.num_samples = key->num_samples;
2466 keys[MESA_SHADER_FRAGMENT].fs.is_dual_src = key->is_dual_src;
2467
2468 if (nir[MESA_SHADER_COMPUTE]) {
2469 keys[MESA_SHADER_COMPUTE].cs.subgroup_size = key->compute_subgroup_size;
2470 }
2471 }
2472
2473 static uint8_t
2474 radv_get_wave_size(struct radv_device *device,
2475 const VkPipelineShaderStageCreateInfo *pStage,
2476 gl_shader_stage stage,
2477 const struct radv_shader_variant_key *key)
2478 {
2479 if (stage == MESA_SHADER_GEOMETRY && !key->vs_common_out.as_ngg)
2480 return 64;
2481 else if (stage == MESA_SHADER_COMPUTE) {
2482 if (key->cs.subgroup_size) {
2483 /* Return the required subgroup size if specified. */
2484 return key->cs.subgroup_size;
2485 }
2486 return device->physical_device->cs_wave_size;
2487 }
2488 else if (stage == MESA_SHADER_FRAGMENT)
2489 return device->physical_device->ps_wave_size;
2490 else
2491 return device->physical_device->ge_wave_size;
2492 }
2493
2494 static uint8_t
2495 radv_get_ballot_bit_size(struct radv_device *device,
2496 const VkPipelineShaderStageCreateInfo *pStage,
2497 gl_shader_stage stage,
2498 const struct radv_shader_variant_key *key)
2499 {
2500 if (stage == MESA_SHADER_COMPUTE && key->cs.subgroup_size)
2501 return key->cs.subgroup_size;
2502 return 64;
2503 }
2504
2505 static void
2506 radv_fill_shader_info(struct radv_pipeline *pipeline,
2507 const VkPipelineShaderStageCreateInfo **pStages,
2508 struct radv_shader_variant_key *keys,
2509 struct radv_shader_info *infos,
2510 nir_shader **nir)
2511 {
2512 unsigned active_stages = 0;
2513 unsigned filled_stages = 0;
2514
2515 for (int i = 0; i < MESA_SHADER_STAGES; i++) {
2516 if (nir[i])
2517 active_stages |= (1 << i);
2518 }
2519
2520 if (nir[MESA_SHADER_FRAGMENT]) {
2521 radv_nir_shader_info_init(&infos[MESA_SHADER_FRAGMENT]);
2522 radv_nir_shader_info_pass(nir[MESA_SHADER_FRAGMENT],
2523 pipeline->layout,
2524 &keys[MESA_SHADER_FRAGMENT],
2525 &infos[MESA_SHADER_FRAGMENT],
2526 pipeline->device->physical_device->use_llvm);
2527
2528 /* TODO: These are no longer used as keys we should refactor this */
2529 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id =
2530 infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
2531 keys[MESA_SHADER_VERTEX].vs_common_out.export_layer_id =
2532 infos[MESA_SHADER_FRAGMENT].ps.layer_input;
2533 keys[MESA_SHADER_VERTEX].vs_common_out.export_clip_dists =
2534 !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
2535 keys[MESA_SHADER_VERTEX].vs_common_out.export_viewport_index =
2536 infos[MESA_SHADER_FRAGMENT].ps.viewport_index_input;
2537 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_prim_id =
2538 infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
2539 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_layer_id =
2540 infos[MESA_SHADER_FRAGMENT].ps.layer_input;
2541 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_clip_dists =
2542 !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
2543 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_viewport_index =
2544 infos[MESA_SHADER_FRAGMENT].ps.viewport_index_input;
2545
2546 /* NGG passthrough mode can't be enabled for vertex shaders
2547 * that export the primitive ID.
2548 *
2549 * TODO: I should really refactor the keys logic.
2550 */
2551 if (nir[MESA_SHADER_VERTEX] &&
2552 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id) {
2553 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg_passthrough = false;
2554 }
2555
2556 filled_stages |= (1 << MESA_SHADER_FRAGMENT);
2557 }
2558
2559 if (nir[MESA_SHADER_TESS_CTRL]) {
2560 infos[MESA_SHADER_TESS_CTRL].tcs.tes_inputs_read =
2561 nir[MESA_SHADER_TESS_EVAL]->info.inputs_read;
2562 infos[MESA_SHADER_TESS_CTRL].tcs.tes_patch_inputs_read =
2563 nir[MESA_SHADER_TESS_EVAL]->info.patch_inputs_read;
2564 }
2565
2566 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
2567 nir[MESA_SHADER_TESS_CTRL]) {
2568 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2569 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2570 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2571
2572 radv_nir_shader_info_init(&infos[MESA_SHADER_TESS_CTRL]);
2573
2574 for (int i = 0; i < 2; i++) {
2575 radv_nir_shader_info_pass(combined_nir[i],
2576 pipeline->layout, &key,
2577 &infos[MESA_SHADER_TESS_CTRL],
2578 pipeline->device->physical_device->use_llvm);
2579 }
2580
2581 keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
2582 infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
2583 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs =
2584 util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written);
2585
2586 filled_stages |= (1 << MESA_SHADER_VERTEX);
2587 filled_stages |= (1 << MESA_SHADER_TESS_CTRL);
2588 }
2589
2590 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
2591 nir[MESA_SHADER_GEOMETRY]) {
2592 gl_shader_stage pre_stage = nir[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2593 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2594
2595 radv_nir_shader_info_init(&infos[MESA_SHADER_GEOMETRY]);
2596
2597 for (int i = 0; i < 2; i++) {
2598 radv_nir_shader_info_pass(combined_nir[i],
2599 pipeline->layout,
2600 &keys[pre_stage],
2601 &infos[MESA_SHADER_GEOMETRY],
2602 pipeline->device->physical_device->use_llvm);
2603 }
2604
2605 filled_stages |= (1 << pre_stage);
2606 filled_stages |= (1 << MESA_SHADER_GEOMETRY);
2607 }
2608
2609 active_stages ^= filled_stages;
2610 while (active_stages) {
2611 int i = u_bit_scan(&active_stages);
2612
2613 if (i == MESA_SHADER_TESS_CTRL) {
2614 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs =
2615 util_last_bit64(infos[MESA_SHADER_VERTEX].vs.ls_outputs_written);
2616 }
2617
2618 if (i == MESA_SHADER_TESS_EVAL) {
2619 keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
2620 infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
2621 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs =
2622 util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written);
2623 }
2624
2625 radv_nir_shader_info_init(&infos[i]);
2626 radv_nir_shader_info_pass(nir[i], pipeline->layout,
2627 &keys[i], &infos[i], pipeline->device->physical_device->use_llvm);
2628 }
2629
2630 for (int i = 0; i < MESA_SHADER_STAGES; i++) {
2631 if (nir[i]) {
2632 infos[i].wave_size =
2633 radv_get_wave_size(pipeline->device, pStages[i],
2634 i, &keys[i]);
2635 infos[i].ballot_bit_size =
2636 radv_get_ballot_bit_size(pipeline->device,
2637 pStages[i], i,
2638 &keys[i]);
2639 }
2640 }
2641 }
2642
2643 static void
2644 merge_tess_info(struct shader_info *tes_info,
2645 const struct shader_info *tcs_info)
2646 {
2647 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2648 *
2649 * "PointMode. Controls generation of points rather than triangles
2650 * or lines. This functionality defaults to disabled, and is
2651 * enabled if either shader stage includes the execution mode.
2652 *
2653 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2654 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2655 * and OutputVertices, it says:
2656 *
2657 * "One mode must be set in at least one of the tessellation
2658 * shader stages."
2659 *
2660 * So, the fields can be set in either the TCS or TES, but they must
2661 * agree if set in both. Our backend looks at TES, so bitwise-or in
2662 * the values from the TCS.
2663 */
2664 assert(tcs_info->tess.tcs_vertices_out == 0 ||
2665 tes_info->tess.tcs_vertices_out == 0 ||
2666 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
2667 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
2668
2669 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2670 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2671 tcs_info->tess.spacing == tes_info->tess.spacing);
2672 tes_info->tess.spacing |= tcs_info->tess.spacing;
2673
2674 assert(tcs_info->tess.primitive_mode == 0 ||
2675 tes_info->tess.primitive_mode == 0 ||
2676 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
2677 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
2678 tes_info->tess.ccw |= tcs_info->tess.ccw;
2679 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
2680 }
2681
2682 static
2683 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT *ext)
2684 {
2685 if (!ext)
2686 return;
2687
2688 if (ext->pPipelineCreationFeedback) {
2689 ext->pPipelineCreationFeedback->flags = 0;
2690 ext->pPipelineCreationFeedback->duration = 0;
2691 }
2692
2693 for (unsigned i = 0; i < ext->pipelineStageCreationFeedbackCount; ++i) {
2694 ext->pPipelineStageCreationFeedbacks[i].flags = 0;
2695 ext->pPipelineStageCreationFeedbacks[i].duration = 0;
2696 }
2697 }
2698
2699 static
2700 void radv_start_feedback(VkPipelineCreationFeedbackEXT *feedback)
2701 {
2702 if (!feedback)
2703 return;
2704
2705 feedback->duration -= radv_get_current_time();
2706 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT;
2707 }
2708
2709 static
2710 void radv_stop_feedback(VkPipelineCreationFeedbackEXT *feedback, bool cache_hit)
2711 {
2712 if (!feedback)
2713 return;
2714
2715 feedback->duration += radv_get_current_time();
2716 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT |
2717 (cache_hit ? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT : 0);
2718 }
2719
2720 VkResult radv_create_shaders(struct radv_pipeline *pipeline,
2721 struct radv_device *device,
2722 struct radv_pipeline_cache *cache,
2723 const struct radv_pipeline_key *key,
2724 const VkPipelineShaderStageCreateInfo **pStages,
2725 const VkPipelineCreateFlags flags,
2726 VkPipelineCreationFeedbackEXT *pipeline_feedback,
2727 VkPipelineCreationFeedbackEXT **stage_feedbacks)
2728 {
2729 struct radv_shader_module fs_m = {0};
2730 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
2731 nir_shader *nir[MESA_SHADER_STAGES] = {0};
2732 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2733 struct radv_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{{0}}}}};
2734 struct radv_shader_info infos[MESA_SHADER_STAGES] = {0};
2735 unsigned char hash[20], gs_copy_hash[20];
2736 bool keep_executable_info = (flags & VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR) || device->keep_shader_info;
2737 bool keep_statistic_info = (flags & VK_PIPELINE_CREATE_CAPTURE_STATISTICS_BIT_KHR) ||
2738 (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) ||
2739 device->keep_shader_info;
2740
2741 radv_start_feedback(pipeline_feedback);
2742
2743 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2744 if (pStages[i]) {
2745 modules[i] = radv_shader_module_from_handle(pStages[i]->module);
2746 if (modules[i]->nir)
2747 _mesa_sha1_compute(modules[i]->nir->info.name,
2748 strlen(modules[i]->nir->info.name),
2749 modules[i]->sha1);
2750
2751 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
2752 }
2753 }
2754
2755 radv_hash_shaders(hash, pStages, pipeline->layout, key, get_hash_flags(device));
2756 memcpy(gs_copy_hash, hash, 20);
2757 gs_copy_hash[0] ^= 1;
2758
2759 bool found_in_application_cache = true;
2760 if (modules[MESA_SHADER_GEOMETRY] && !keep_executable_info && !keep_statistic_info) {
2761 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2762 radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants,
2763 &found_in_application_cache);
2764 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
2765 }
2766
2767 if (!keep_executable_info && !keep_statistic_info &&
2768 radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders,
2769 &found_in_application_cache) &&
2770 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
2771 radv_stop_feedback(pipeline_feedback, found_in_application_cache);
2772 return VK_SUCCESS;
2773 }
2774
2775 if (flags & VK_PIPELINE_CREATE_FAIL_ON_PIPELINE_COMPILE_REQUIRED_BIT_EXT) {
2776 radv_stop_feedback(pipeline_feedback, found_in_application_cache);
2777 return VK_PIPELINE_COMPILE_REQUIRED_EXT;
2778 }
2779
2780 if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
2781 nir_builder fs_b;
2782 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
2783 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
2784 fs_m.nir = fs_b.shader;
2785 modules[MESA_SHADER_FRAGMENT] = &fs_m;
2786 }
2787
2788 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2789 const VkPipelineShaderStageCreateInfo *stage = pStages[i];
2790 unsigned subgroup_size = 64, ballot_bit_size = 64;
2791
2792 if (!modules[i])
2793 continue;
2794
2795 radv_start_feedback(stage_feedbacks[i]);
2796
2797 if (key->compute_subgroup_size) {
2798 /* Only compute shaders currently support requiring a
2799 * specific subgroup size.
2800 */
2801 assert(i == MESA_SHADER_COMPUTE);
2802 subgroup_size = key->compute_subgroup_size;
2803 ballot_bit_size = key->compute_subgroup_size;
2804 }
2805
2806 nir[i] = radv_shader_compile_to_nir(device, modules[i],
2807 stage ? stage->pName : "main", i,
2808 stage ? stage->pSpecializationInfo : NULL,
2809 flags, pipeline->layout,
2810 subgroup_size, ballot_bit_size);
2811
2812 /* We don't want to alter meta shaders IR directly so clone it
2813 * first.
2814 */
2815 if (nir[i]->info.name) {
2816 nir[i] = nir_shader_clone(NULL, nir[i]);
2817 }
2818
2819 radv_stop_feedback(stage_feedbacks[i], false);
2820 }
2821
2822 if (nir[MESA_SHADER_TESS_CTRL]) {
2823 nir_lower_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out, NULL);
2824 merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
2825 }
2826
2827 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
2828 radv_link_shaders(pipeline, nir);
2829
2830 radv_set_linked_driver_locations(pipeline, nir, infos);
2831
2832 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2833 if (nir[i]) {
2834 /* do this again since information such as outputs_read can be out-of-date */
2835 nir_shader_gather_info(nir[i], nir_shader_get_entrypoint(nir[i]));
2836
2837 if (device->physical_device->use_llvm) {
2838 NIR_PASS_V(nir[i], nir_lower_bool_to_int32);
2839 } else {
2840 NIR_PASS_V(nir[i], nir_lower_non_uniform_access,
2841 nir_lower_non_uniform_ubo_access |
2842 nir_lower_non_uniform_ssbo_access |
2843 nir_lower_non_uniform_texture_access |
2844 nir_lower_non_uniform_image_access);
2845 }
2846 }
2847 }
2848
2849 if (nir[MESA_SHADER_FRAGMENT])
2850 radv_lower_fs_io(nir[MESA_SHADER_FRAGMENT]);
2851
2852 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2853 if (radv_can_dump_shader(device, modules[i], false))
2854 nir_print_shader(nir[i], stderr);
2855 }
2856
2857 radv_fill_shader_keys(device, keys, key, nir);
2858
2859 radv_fill_shader_info(pipeline, pStages, keys, infos, nir);
2860
2861 if ((nir[MESA_SHADER_VERTEX] &&
2862 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg) ||
2863 (nir[MESA_SHADER_TESS_EVAL] &&
2864 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg)) {
2865 struct gfx10_ngg_info *ngg_info;
2866
2867 if (nir[MESA_SHADER_GEOMETRY])
2868 ngg_info = &infos[MESA_SHADER_GEOMETRY].ngg_info;
2869 else if (nir[MESA_SHADER_TESS_CTRL])
2870 ngg_info = &infos[MESA_SHADER_TESS_EVAL].ngg_info;
2871 else
2872 ngg_info = &infos[MESA_SHADER_VERTEX].ngg_info;
2873
2874 gfx10_get_ngg_info(key, pipeline, nir, infos, ngg_info);
2875 } else if (nir[MESA_SHADER_GEOMETRY]) {
2876 struct gfx9_gs_info *gs_info =
2877 &infos[MESA_SHADER_GEOMETRY].gs_ring_info;
2878
2879 gfx9_get_gs_info(key, pipeline, nir, infos, gs_info);
2880 }
2881
2882 if(modules[MESA_SHADER_GEOMETRY]) {
2883 struct radv_shader_binary *gs_copy_binary = NULL;
2884 if (!pipeline->gs_copy_shader &&
2885 !radv_pipeline_has_ngg(pipeline)) {
2886 struct radv_shader_info info = {};
2887 struct radv_shader_variant_key key = {};
2888
2889 key.has_multiview_view_index =
2890 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index;
2891
2892 radv_nir_shader_info_pass(nir[MESA_SHADER_GEOMETRY],
2893 pipeline->layout, &key,
2894 &info, pipeline->device->physical_device->use_llvm);
2895 info.wave_size = 64; /* Wave32 not supported. */
2896 info.ballot_bit_size = 64;
2897
2898 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
2899 device, nir[MESA_SHADER_GEOMETRY], &info,
2900 &gs_copy_binary, keep_executable_info, keep_statistic_info,
2901 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
2902 }
2903
2904 if (!keep_executable_info && !keep_statistic_info && pipeline->gs_copy_shader) {
2905 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2906 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2907
2908 binaries[MESA_SHADER_GEOMETRY] = gs_copy_binary;
2909 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
2910
2911 radv_pipeline_cache_insert_shaders(device, cache,
2912 gs_copy_hash,
2913 variants,
2914 binaries);
2915 }
2916 free(gs_copy_binary);
2917 }
2918
2919 if (nir[MESA_SHADER_FRAGMENT]) {
2920 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
2921 radv_start_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT]);
2922
2923 pipeline->shaders[MESA_SHADER_FRAGMENT] =
2924 radv_shader_variant_compile(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
2925 pipeline->layout, keys + MESA_SHADER_FRAGMENT,
2926 infos + MESA_SHADER_FRAGMENT,
2927 keep_executable_info, keep_statistic_info,
2928 &binaries[MESA_SHADER_FRAGMENT]);
2929
2930 radv_stop_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT], false);
2931 }
2932 }
2933
2934 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
2935 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
2936 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2937 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2938 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2939
2940 radv_start_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL]);
2941
2942 pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_compile(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
2943 pipeline->layout,
2944 &key, &infos[MESA_SHADER_TESS_CTRL], keep_executable_info,
2945 keep_statistic_info, &binaries[MESA_SHADER_TESS_CTRL]);
2946
2947 radv_stop_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL], false);
2948 }
2949 modules[MESA_SHADER_VERTEX] = NULL;
2950 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2951 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written);
2952 }
2953
2954 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
2955 gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2956 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
2957 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2958
2959 radv_start_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY]);
2960
2961 pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_compile(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
2962 pipeline->layout,
2963 &keys[pre_stage], &infos[MESA_SHADER_GEOMETRY], keep_executable_info,
2964 keep_statistic_info, &binaries[MESA_SHADER_GEOMETRY]);
2965
2966 radv_stop_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY], false);
2967 }
2968 modules[pre_stage] = NULL;
2969 }
2970
2971 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2972 if(modules[i] && !pipeline->shaders[i]) {
2973 if (i == MESA_SHADER_TESS_CTRL) {
2974 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.ls_outputs_written);
2975 }
2976 if (i == MESA_SHADER_TESS_EVAL) {
2977 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2978 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written);
2979 }
2980
2981 radv_start_feedback(stage_feedbacks[i]);
2982
2983 pipeline->shaders[i] = radv_shader_variant_compile(device, modules[i], &nir[i], 1,
2984 pipeline->layout,
2985 keys + i, infos + i, keep_executable_info,
2986 keep_statistic_info, &binaries[i]);
2987
2988 radv_stop_feedback(stage_feedbacks[i], false);
2989 }
2990 }
2991
2992 if (!keep_executable_info && !keep_statistic_info) {
2993 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
2994 binaries);
2995 }
2996
2997 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2998 free(binaries[i]);
2999 if (nir[i]) {
3000 ralloc_free(nir[i]);
3001
3002 if (radv_can_dump_shader_stats(device, modules[i]))
3003 radv_shader_dump_stats(device,
3004 pipeline->shaders[i],
3005 i, stderr);
3006 }
3007 }
3008
3009 if (fs_m.nir)
3010 ralloc_free(fs_m.nir);
3011
3012 radv_stop_feedback(pipeline_feedback, false);
3013 return VK_SUCCESS;
3014 }
3015
3016 static uint32_t
3017 radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
3018 gl_shader_stage stage, enum chip_class chip_class)
3019 {
3020 bool has_gs = radv_pipeline_has_gs(pipeline);
3021 bool has_tess = radv_pipeline_has_tess(pipeline);
3022 bool has_ngg = radv_pipeline_has_ngg(pipeline);
3023
3024 switch (stage) {
3025 case MESA_SHADER_FRAGMENT:
3026 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
3027 case MESA_SHADER_VERTEX:
3028 if (has_tess) {
3029 if (chip_class >= GFX10) {
3030 return R_00B430_SPI_SHADER_USER_DATA_HS_0;
3031 } else if (chip_class == GFX9) {
3032 return R_00B430_SPI_SHADER_USER_DATA_LS_0;
3033 } else {
3034 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
3035 }
3036
3037 }
3038
3039 if (has_gs) {
3040 if (chip_class >= GFX10) {
3041 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
3042 } else {
3043 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
3044 }
3045 }
3046
3047 if (has_ngg)
3048 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
3049
3050 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
3051 case MESA_SHADER_GEOMETRY:
3052 return chip_class == GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
3053 R_00B230_SPI_SHADER_USER_DATA_GS_0;
3054 case MESA_SHADER_COMPUTE:
3055 return R_00B900_COMPUTE_USER_DATA_0;
3056 case MESA_SHADER_TESS_CTRL:
3057 return chip_class == GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
3058 R_00B430_SPI_SHADER_USER_DATA_HS_0;
3059 case MESA_SHADER_TESS_EVAL:
3060 if (has_gs) {
3061 return chip_class >= GFX10 ? R_00B230_SPI_SHADER_USER_DATA_GS_0 :
3062 R_00B330_SPI_SHADER_USER_DATA_ES_0;
3063 } else if (has_ngg) {
3064 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
3065 } else {
3066 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
3067 }
3068 default:
3069 unreachable("unknown shader");
3070 }
3071 }
3072
3073 struct radv_bin_size_entry {
3074 unsigned bpp;
3075 VkExtent2D extent;
3076 };
3077
3078 static VkExtent2D
3079 radv_gfx9_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
3080 {
3081 static const struct radv_bin_size_entry color_size_table[][3][9] = {
3082 {
3083 /* One RB / SE */
3084 {
3085 /* One shader engine */
3086 { 0, {128, 128}},
3087 { 1, { 64, 128}},
3088 { 2, { 32, 128}},
3089 { 3, { 16, 128}},
3090 { 17, { 0, 0}},
3091 { UINT_MAX, { 0, 0}},
3092 },
3093 {
3094 /* Two shader engines */
3095 { 0, {128, 128}},
3096 { 2, { 64, 128}},
3097 { 3, { 32, 128}},
3098 { 5, { 16, 128}},
3099 { 17, { 0, 0}},
3100 { UINT_MAX, { 0, 0}},
3101 },
3102 {
3103 /* Four shader engines */
3104 { 0, {128, 128}},
3105 { 3, { 64, 128}},
3106 { 5, { 16, 128}},
3107 { 17, { 0, 0}},
3108 { UINT_MAX, { 0, 0}},
3109 },
3110 },
3111 {
3112 /* Two RB / SE */
3113 {
3114 /* One shader engine */
3115 { 0, {128, 128}},
3116 { 2, { 64, 128}},
3117 { 3, { 32, 128}},
3118 { 5, { 16, 128}},
3119 { 33, { 0, 0}},
3120 { UINT_MAX, { 0, 0}},
3121 },
3122 {
3123 /* Two shader engines */
3124 { 0, {128, 128}},
3125 { 3, { 64, 128}},
3126 { 5, { 32, 128}},
3127 { 9, { 16, 128}},
3128 { 33, { 0, 0}},
3129 { UINT_MAX, { 0, 0}},
3130 },
3131 {
3132 /* Four shader engines */
3133 { 0, {256, 256}},
3134 { 2, {128, 256}},
3135 { 3, {128, 128}},
3136 { 5, { 64, 128}},
3137 { 9, { 16, 128}},
3138 { 33, { 0, 0}},
3139 { UINT_MAX, { 0, 0}},
3140 },
3141 },
3142 {
3143 /* Four RB / SE */
3144 {
3145 /* One shader engine */
3146 { 0, {128, 256}},
3147 { 2, {128, 128}},
3148 { 3, { 64, 128}},
3149 { 5, { 32, 128}},
3150 { 9, { 16, 128}},
3151 { 33, { 0, 0}},
3152 { UINT_MAX, { 0, 0}},
3153 },
3154 {
3155 /* Two shader engines */
3156 { 0, {256, 256}},
3157 { 2, {128, 256}},
3158 { 3, {128, 128}},
3159 { 5, { 64, 128}},
3160 { 9, { 32, 128}},
3161 { 17, { 16, 128}},
3162 { 33, { 0, 0}},
3163 { UINT_MAX, { 0, 0}},
3164 },
3165 {
3166 /* Four shader engines */
3167 { 0, {256, 512}},
3168 { 2, {256, 256}},
3169 { 3, {128, 256}},
3170 { 5, {128, 128}},
3171 { 9, { 64, 128}},
3172 { 17, { 16, 128}},
3173 { 33, { 0, 0}},
3174 { UINT_MAX, { 0, 0}},
3175 },
3176 },
3177 };
3178 static const struct radv_bin_size_entry ds_size_table[][3][9] = {
3179 {
3180 // One RB / SE
3181 {
3182 // One shader engine
3183 { 0, {128, 256}},
3184 { 2, {128, 128}},
3185 { 4, { 64, 128}},
3186 { 7, { 32, 128}},
3187 { 13, { 16, 128}},
3188 { 49, { 0, 0}},
3189 { UINT_MAX, { 0, 0}},
3190 },
3191 {
3192 // Two shader engines
3193 { 0, {256, 256}},
3194 { 2, {128, 256}},
3195 { 4, {128, 128}},
3196 { 7, { 64, 128}},
3197 { 13, { 32, 128}},
3198 { 25, { 16, 128}},
3199 { 49, { 0, 0}},
3200 { UINT_MAX, { 0, 0}},
3201 },
3202 {
3203 // Four shader engines
3204 { 0, {256, 512}},
3205 { 2, {256, 256}},
3206 { 4, {128, 256}},
3207 { 7, {128, 128}},
3208 { 13, { 64, 128}},
3209 { 25, { 16, 128}},
3210 { 49, { 0, 0}},
3211 { UINT_MAX, { 0, 0}},
3212 },
3213 },
3214 {
3215 // Two RB / SE
3216 {
3217 // One shader engine
3218 { 0, {256, 256}},
3219 { 2, {128, 256}},
3220 { 4, {128, 128}},
3221 { 7, { 64, 128}},
3222 { 13, { 32, 128}},
3223 { 25, { 16, 128}},
3224 { 97, { 0, 0}},
3225 { UINT_MAX, { 0, 0}},
3226 },
3227 {
3228 // Two shader engines
3229 { 0, {256, 512}},
3230 { 2, {256, 256}},
3231 { 4, {128, 256}},
3232 { 7, {128, 128}},
3233 { 13, { 64, 128}},
3234 { 25, { 32, 128}},
3235 { 49, { 16, 128}},
3236 { 97, { 0, 0}},
3237 { UINT_MAX, { 0, 0}},
3238 },
3239 {
3240 // Four shader engines
3241 { 0, {512, 512}},
3242 { 2, {256, 512}},
3243 { 4, {256, 256}},
3244 { 7, {128, 256}},
3245 { 13, {128, 128}},
3246 { 25, { 64, 128}},
3247 { 49, { 16, 128}},
3248 { 97, { 0, 0}},
3249 { UINT_MAX, { 0, 0}},
3250 },
3251 },
3252 {
3253 // Four RB / SE
3254 {
3255 // One shader engine
3256 { 0, {256, 512}},
3257 { 2, {256, 256}},
3258 { 4, {128, 256}},
3259 { 7, {128, 128}},
3260 { 13, { 64, 128}},
3261 { 25, { 32, 128}},
3262 { 49, { 16, 128}},
3263 { UINT_MAX, { 0, 0}},
3264 },
3265 {
3266 // Two shader engines
3267 { 0, {512, 512}},
3268 { 2, {256, 512}},
3269 { 4, {256, 256}},
3270 { 7, {128, 256}},
3271 { 13, {128, 128}},
3272 { 25, { 64, 128}},
3273 { 49, { 32, 128}},
3274 { 97, { 16, 128}},
3275 { UINT_MAX, { 0, 0}},
3276 },
3277 {
3278 // Four shader engines
3279 { 0, {512, 512}},
3280 { 4, {256, 512}},
3281 { 7, {256, 256}},
3282 { 13, {128, 256}},
3283 { 25, {128, 128}},
3284 { 49, { 64, 128}},
3285 { 97, { 16, 128}},
3286 { UINT_MAX, { 0, 0}},
3287 },
3288 },
3289 };
3290
3291 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3292 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3293 VkExtent2D extent = {512, 512};
3294
3295 unsigned log_num_rb_per_se =
3296 util_logbase2_ceil(pipeline->device->physical_device->rad_info.num_render_backends /
3297 pipeline->device->physical_device->rad_info.max_se);
3298 unsigned log_num_se = util_logbase2_ceil(pipeline->device->physical_device->rad_info.max_se);
3299
3300 unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
3301 unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->graphics.ms.db_eqaa);
3302 unsigned effective_samples = total_samples;
3303 unsigned color_bytes_per_pixel = 0;
3304
3305 const VkPipelineColorBlendStateCreateInfo *vkblend =
3306 radv_pipeline_get_color_blend_state(pCreateInfo);
3307 if (vkblend) {
3308 for (unsigned i = 0; i < subpass->color_count; i++) {
3309 if (!vkblend->pAttachments[i].colorWriteMask)
3310 continue;
3311
3312 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3313 continue;
3314
3315 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3316 color_bytes_per_pixel += vk_format_get_blocksize(format);
3317 }
3318
3319 /* MSAA images typically don't use all samples all the time. */
3320 if (effective_samples >= 2 && ps_iter_samples <= 1)
3321 effective_samples = 2;
3322 color_bytes_per_pixel *= effective_samples;
3323 }
3324
3325 const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se];
3326 while(color_entry[1].bpp <= color_bytes_per_pixel)
3327 ++color_entry;
3328
3329 extent = color_entry->extent;
3330
3331 if (subpass->depth_stencil_attachment) {
3332 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3333
3334 /* Coefficients taken from AMDVLK */
3335 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
3336 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
3337 unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples;
3338
3339 const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se];
3340 while(ds_entry[1].bpp <= ds_bytes_per_pixel)
3341 ++ds_entry;
3342
3343 if (ds_entry->extent.width * ds_entry->extent.height < extent.width * extent.height)
3344 extent = ds_entry->extent;
3345 }
3346
3347 return extent;
3348 }
3349
3350 static VkExtent2D
3351 radv_gfx10_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
3352 {
3353 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3354 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3355 VkExtent2D extent = {512, 512};
3356
3357 const unsigned db_tag_size = 64;
3358 const unsigned db_tag_count = 312;
3359 const unsigned color_tag_size = 1024;
3360 const unsigned color_tag_count = 31;
3361 const unsigned fmask_tag_size = 256;
3362 const unsigned fmask_tag_count = 44;
3363
3364 const unsigned rb_count = pipeline->device->physical_device->rad_info.num_render_backends;
3365 const unsigned pipe_count = MAX2(rb_count, pipeline->device->physical_device->rad_info.num_sdp_interfaces);
3366
3367 const unsigned db_tag_part = (db_tag_count * rb_count / pipe_count) * db_tag_size * pipe_count;
3368 const unsigned color_tag_part = (color_tag_count * rb_count / pipe_count) * color_tag_size * pipe_count;
3369 const unsigned fmask_tag_part = (fmask_tag_count * rb_count / pipe_count) * fmask_tag_size * pipe_count;
3370
3371 const unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
3372 const unsigned samples_log = util_logbase2_ceil(total_samples);
3373
3374 unsigned color_bytes_per_pixel = 0;
3375 unsigned fmask_bytes_per_pixel = 0;
3376
3377 const VkPipelineColorBlendStateCreateInfo *vkblend =
3378 radv_pipeline_get_color_blend_state(pCreateInfo);
3379 if (vkblend) {
3380 for (unsigned i = 0; i < subpass->color_count; i++) {
3381 if (!vkblend->pAttachments[i].colorWriteMask)
3382 continue;
3383
3384 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3385 continue;
3386
3387 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3388 color_bytes_per_pixel += vk_format_get_blocksize(format);
3389
3390 if (total_samples > 1) {
3391 assert(samples_log <= 3);
3392 const unsigned fmask_array[] = {0, 1, 1, 4};
3393 fmask_bytes_per_pixel += fmask_array[samples_log];
3394 }
3395 }
3396
3397 color_bytes_per_pixel *= total_samples;
3398 }
3399 color_bytes_per_pixel = MAX2(color_bytes_per_pixel, 1);
3400
3401 const unsigned color_pixel_count_log = util_logbase2(color_tag_part / color_bytes_per_pixel);
3402 extent.width = 1ull << ((color_pixel_count_log + 1) / 2);
3403 extent.height = 1ull << (color_pixel_count_log / 2);
3404
3405 if (fmask_bytes_per_pixel) {
3406 const unsigned fmask_pixel_count_log = util_logbase2(fmask_tag_part / fmask_bytes_per_pixel);
3407
3408 const VkExtent2D fmask_extent = (VkExtent2D){
3409 .width = 1ull << ((fmask_pixel_count_log + 1) / 2),
3410 .height = 1ull << (color_pixel_count_log / 2)
3411 };
3412
3413 if (fmask_extent.width * fmask_extent.height < extent.width * extent.height)
3414 extent = fmask_extent;
3415 }
3416
3417 if (subpass->depth_stencil_attachment) {
3418 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3419
3420 /* Coefficients taken from AMDVLK */
3421 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
3422 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
3423 unsigned db_bytes_per_pixel = (depth_coeff + stencil_coeff) * total_samples;
3424
3425 const unsigned db_pixel_count_log = util_logbase2(db_tag_part / db_bytes_per_pixel);
3426
3427 const VkExtent2D db_extent = (VkExtent2D){
3428 .width = 1ull << ((db_pixel_count_log + 1) / 2),
3429 .height = 1ull << (color_pixel_count_log / 2)
3430 };
3431
3432 if (db_extent.width * db_extent.height < extent.width * extent.height)
3433 extent = db_extent;
3434 }
3435
3436 extent.width = MAX2(extent.width, 128);
3437 extent.height = MAX2(extent.width, 64);
3438
3439 return extent;
3440 }
3441
3442 static void
3443 radv_pipeline_generate_disabled_binning_state(struct radeon_cmdbuf *ctx_cs,
3444 struct radv_pipeline *pipeline,
3445 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3446 {
3447 uint32_t pa_sc_binner_cntl_0 =
3448 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
3449 S_028C44_DISABLE_START_OF_PRIM(1);
3450 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
3451
3452 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3453 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3454 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3455 const VkPipelineColorBlendStateCreateInfo *vkblend =
3456 radv_pipeline_get_color_blend_state(pCreateInfo);
3457 unsigned min_bytes_per_pixel = 0;
3458
3459 if (vkblend) {
3460 for (unsigned i = 0; i < subpass->color_count; i++) {
3461 if (!vkblend->pAttachments[i].colorWriteMask)
3462 continue;
3463
3464 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3465 continue;
3466
3467 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3468 unsigned bytes = vk_format_get_blocksize(format);
3469 if (!min_bytes_per_pixel || bytes < min_bytes_per_pixel)
3470 min_bytes_per_pixel = bytes;
3471 }
3472 }
3473
3474 pa_sc_binner_cntl_0 =
3475 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC) |
3476 S_028C44_BIN_SIZE_X(0) |
3477 S_028C44_BIN_SIZE_Y(0) |
3478 S_028C44_BIN_SIZE_X_EXTEND(2) | /* 128 */
3479 S_028C44_BIN_SIZE_Y_EXTEND(min_bytes_per_pixel <= 4 ? 2 : 1) | /* 128 or 64 */
3480 S_028C44_DISABLE_START_OF_PRIM(1);
3481 }
3482
3483 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
3484 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
3485 }
3486
3487 struct radv_binning_settings
3488 radv_get_binning_settings(const struct radv_physical_device *pdev)
3489 {
3490 struct radv_binning_settings settings;
3491 if (pdev->rad_info.has_dedicated_vram) {
3492 if (pdev->rad_info.num_render_backends > 4) {
3493 settings.context_states_per_bin = 1;
3494 settings.persistent_states_per_bin = 1;
3495 } else {
3496 settings.context_states_per_bin = 3;
3497 settings.persistent_states_per_bin = 8;
3498 }
3499 settings.fpovs_per_batch = 63;
3500 } else {
3501 /* The context states are affected by the scissor bug. */
3502 settings.context_states_per_bin = 6;
3503 /* 32 causes hangs for RAVEN. */
3504 settings.persistent_states_per_bin = 16;
3505 settings.fpovs_per_batch = 63;
3506 }
3507
3508 if (pdev->rad_info.has_gfx9_scissor_bug)
3509 settings.context_states_per_bin = 1;
3510
3511 return settings;
3512 }
3513
3514 static void
3515 radv_pipeline_generate_binning_state(struct radeon_cmdbuf *ctx_cs,
3516 struct radv_pipeline *pipeline,
3517 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3518 const struct radv_blend_state *blend)
3519 {
3520 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
3521 return;
3522
3523 VkExtent2D bin_size;
3524 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3525 bin_size = radv_gfx10_compute_bin_size(pipeline, pCreateInfo);
3526 } else if (pipeline->device->physical_device->rad_info.chip_class == GFX9) {
3527 bin_size = radv_gfx9_compute_bin_size(pipeline, pCreateInfo);
3528 } else
3529 unreachable("Unhandled generation for binning bin size calculation");
3530
3531 if (pipeline->device->pbb_allowed && bin_size.width && bin_size.height) {
3532 struct radv_binning_settings settings =
3533 radv_get_binning_settings(pipeline->device->physical_device);
3534
3535 bool disable_start_of_prim = true;
3536 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
3537
3538 const struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3539
3540 if (pipeline->device->dfsm_allowed && ps &&
3541 !ps->info.ps.can_discard &&
3542 !ps->info.ps.writes_memory &&
3543 blend->cb_target_enabled_4bit) {
3544 db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_AUTO);
3545 disable_start_of_prim = (blend->blend_enable_4bit & blend->cb_target_enabled_4bit) != 0;
3546 }
3547
3548 const uint32_t pa_sc_binner_cntl_0 =
3549 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
3550 S_028C44_BIN_SIZE_X(bin_size.width == 16) |
3551 S_028C44_BIN_SIZE_Y(bin_size.height == 16) |
3552 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size.width, 32)) - 5) |
3553 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size.height, 32)) - 5) |
3554 S_028C44_CONTEXT_STATES_PER_BIN(settings.context_states_per_bin - 1) |
3555 S_028C44_PERSISTENT_STATES_PER_BIN(settings.persistent_states_per_bin - 1) |
3556 S_028C44_DISABLE_START_OF_PRIM(disable_start_of_prim) |
3557 S_028C44_FPOVS_PER_BATCH(settings.fpovs_per_batch) |
3558 S_028C44_OPTIMAL_BIN_SELECTION(1);
3559
3560 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
3561 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
3562 } else
3563 radv_pipeline_generate_disabled_binning_state(ctx_cs, pipeline, pCreateInfo);
3564 }
3565
3566
3567 static void
3568 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf *ctx_cs,
3569 struct radv_pipeline *pipeline,
3570 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3571 const struct radv_graphics_pipeline_create_info *extra)
3572 {
3573 const VkPipelineDepthStencilStateCreateInfo *vkds = radv_pipeline_get_depth_stencil_state(pCreateInfo);
3574 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3575 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3576 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3577 struct radv_render_pass_attachment *attachment = NULL;
3578 uint32_t db_depth_control = 0, db_stencil_control = 0;
3579 uint32_t db_render_control = 0, db_render_override2 = 0;
3580 uint32_t db_render_override = 0;
3581
3582 if (subpass->depth_stencil_attachment)
3583 attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3584
3585 bool has_depth_attachment = attachment && vk_format_is_depth(attachment->format);
3586 bool has_stencil_attachment = attachment && vk_format_is_stencil(attachment->format);
3587
3588 if (vkds && has_depth_attachment) {
3589 db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
3590 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
3591 S_028800_ZFUNC(vkds->depthCompareOp) |
3592 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
3593
3594 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
3595 db_render_override2 |= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment->samples > 2);
3596
3597 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10_3)
3598 db_render_override2 |= S_028010_CENTROID_COMPUTATION_MODE_GFX103(2);
3599 }
3600
3601 if (has_stencil_attachment && vkds && vkds->stencilTestEnable) {
3602 db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
3603 db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
3604 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
3605 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
3606 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
3607
3608 db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
3609 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
3610 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
3611 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
3612 }
3613
3614 if (attachment && extra) {
3615 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
3616 db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
3617
3618 db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->resummarize_enable);
3619 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->depth_compress_disable);
3620 db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->stencil_compress_disable);
3621 db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
3622 db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
3623 }
3624
3625 db_render_override |= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3626 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
3627
3628 if (!pCreateInfo->pRasterizationState->depthClampEnable &&
3629 ps->info.ps.writes_z) {
3630 /* From VK_EXT_depth_range_unrestricted spec:
3631 *
3632 * "The behavior described in Primitive Clipping still applies.
3633 * If depth clamping is disabled the depth values are still
3634 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
3635 * depth clamping is enabled the above equation is ignored and
3636 * the depth values are instead clamped to the VkViewport
3637 * minDepth and maxDepth values, which in the case of this
3638 * extension can be outside of the 0.0 to 1.0 range."
3639 */
3640 db_render_override |= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
3641 }
3642
3643 radeon_set_context_reg(ctx_cs, R_028800_DB_DEPTH_CONTROL, db_depth_control);
3644 radeon_set_context_reg(ctx_cs, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
3645
3646 radeon_set_context_reg(ctx_cs, R_028000_DB_RENDER_CONTROL, db_render_control);
3647 radeon_set_context_reg(ctx_cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
3648 radeon_set_context_reg(ctx_cs, R_028010_DB_RENDER_OVERRIDE2, db_render_override2);
3649 }
3650
3651 static void
3652 radv_pipeline_generate_blend_state(struct radeon_cmdbuf *ctx_cs,
3653 struct radv_pipeline *pipeline,
3654 const struct radv_blend_state *blend)
3655 {
3656 radeon_set_context_reg_seq(ctx_cs, R_028780_CB_BLEND0_CONTROL, 8);
3657 radeon_emit_array(ctx_cs, blend->cb_blend_control,
3658 8);
3659 radeon_set_context_reg(ctx_cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control);
3660 radeon_set_context_reg(ctx_cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask);
3661
3662 if (pipeline->device->physical_device->rad_info.has_rbplus) {
3663
3664 radeon_set_context_reg_seq(ctx_cs, R_028760_SX_MRT0_BLEND_OPT, 8);
3665 radeon_emit_array(ctx_cs, blend->sx_mrt_blend_opt, 8);
3666 }
3667
3668 radeon_set_context_reg(ctx_cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
3669
3670 radeon_set_context_reg(ctx_cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
3671 radeon_set_context_reg(ctx_cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
3672
3673 pipeline->graphics.col_format = blend->spi_shader_col_format;
3674 pipeline->graphics.cb_target_mask = blend->cb_target_mask;
3675 }
3676
3677 static const VkConservativeRasterizationModeEXT
3678 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo *pCreateInfo)
3679 {
3680 const VkPipelineRasterizationConservativeStateCreateInfoEXT *conservative_raster =
3681 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT);
3682
3683 if (!conservative_raster)
3684 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT;
3685 return conservative_raster->conservativeRasterizationMode;
3686 }
3687
3688 static void
3689 radv_pipeline_generate_raster_state(struct radeon_cmdbuf *ctx_cs,
3690 struct radv_pipeline *pipeline,
3691 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3692 {
3693 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
3694 const VkConservativeRasterizationModeEXT mode =
3695 radv_get_conservative_raster_mode(vkraster);
3696 uint32_t pa_sc_conservative_rast = S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
3697 bool depth_clip_disable = vkraster->depthClampEnable;
3698
3699 const VkPipelineRasterizationDepthClipStateCreateInfoEXT *depth_clip_state =
3700 vk_find_struct_const(vkraster->pNext, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT);
3701 if (depth_clip_state) {
3702 depth_clip_disable = !depth_clip_state->depthClipEnable;
3703 }
3704
3705 radeon_set_context_reg(ctx_cs, R_028810_PA_CL_CLIP_CNTL,
3706 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
3707 S_028810_ZCLIP_NEAR_DISABLE(depth_clip_disable ? 1 : 0) |
3708 S_028810_ZCLIP_FAR_DISABLE(depth_clip_disable ? 1 : 0) |
3709 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
3710 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
3711
3712 radeon_set_context_reg(ctx_cs, R_0286D4_SPI_INTERP_CONTROL_0,
3713 S_0286D4_FLAT_SHADE_ENA(1) |
3714 S_0286D4_PNT_SPRITE_ENA(1) |
3715 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
3716 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
3717 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
3718 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
3719 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
3720
3721 radeon_set_context_reg(ctx_cs, R_028BE4_PA_SU_VTX_CNTL,
3722 S_028BE4_PIX_CENTER(1) | // TODO verify
3723 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
3724 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
3725
3726 radeon_set_context_reg(ctx_cs, R_028814_PA_SU_SC_MODE_CNTL,
3727 S_028814_FACE(vkraster->frontFace) |
3728 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
3729 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
3730 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
3731 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
3732 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
3733 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
3734 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
3735 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0));
3736
3737 /* Conservative rasterization. */
3738 if (mode != VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT) {
3739 struct radv_multisample_state *ms = &pipeline->graphics.ms;
3740
3741 ms->pa_sc_aa_config |= S_028BE0_AA_MASK_CENTROID_DTMN(1);
3742 ms->db_eqaa |= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
3743 S_028804_OVERRASTERIZATION_AMOUNT(4);
3744
3745 pa_sc_conservative_rast = S_028C4C_PREZ_AA_MASK_ENABLE(1) |
3746 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
3747 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
3748
3749 if (mode == VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT) {
3750 pa_sc_conservative_rast |=
3751 S_028C4C_OVER_RAST_ENABLE(1) |
3752 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
3753 S_028C4C_UNDER_RAST_ENABLE(0) |
3754 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
3755 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
3756 } else {
3757 assert(mode == VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT);
3758 pa_sc_conservative_rast |=
3759 S_028C4C_OVER_RAST_ENABLE(0) |
3760 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
3761 S_028C4C_UNDER_RAST_ENABLE(1) |
3762 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
3763 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
3764 }
3765 }
3766
3767 radeon_set_context_reg(ctx_cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
3768 pa_sc_conservative_rast);
3769 }
3770
3771
3772 static void
3773 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf *ctx_cs,
3774 struct radv_pipeline *pipeline)
3775 {
3776 struct radv_multisample_state *ms = &pipeline->graphics.ms;
3777
3778 radeon_set_context_reg_seq(ctx_cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3779 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[0]);
3780 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[1]);
3781
3782 radeon_set_context_reg(ctx_cs, R_028804_DB_EQAA, ms->db_eqaa);
3783 radeon_set_context_reg(ctx_cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
3784 radeon_set_context_reg(ctx_cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
3785 radeon_set_context_reg(ctx_cs, R_028BDC_PA_SC_LINE_CNTL, ms->pa_sc_line_cntl);
3786 radeon_set_context_reg(ctx_cs, R_028BE0_PA_SC_AA_CONFIG, ms->pa_sc_aa_config);
3787
3788 /* The exclusion bits can be set to improve rasterization efficiency
3789 * if no sample lies on the pixel boundary (-8 sample offset). It's
3790 * currently always TRUE because the driver doesn't support 16 samples.
3791 */
3792 bool exclusion = pipeline->device->physical_device->rad_info.chip_class >= GFX7;
3793 radeon_set_context_reg(ctx_cs, R_02882C_PA_SU_PRIM_FILTER_CNTL,
3794 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
3795 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
3796
3797 /* GFX9: Flush DFSM when the AA mode changes. */
3798 if (pipeline->device->dfsm_allowed) {
3799 radeon_emit(ctx_cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3800 radeon_emit(ctx_cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3801 }
3802 }
3803
3804 static void
3805 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf *ctx_cs,
3806 struct radv_pipeline *pipeline)
3807 {
3808 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3809 const struct radv_shader_variant *vs =
3810 pipeline->shaders[MESA_SHADER_TESS_EVAL] ?
3811 pipeline->shaders[MESA_SHADER_TESS_EVAL] :
3812 pipeline->shaders[MESA_SHADER_VERTEX];
3813 unsigned vgt_primitiveid_en = 0;
3814 uint32_t vgt_gs_mode = 0;
3815
3816 if (radv_pipeline_has_ngg(pipeline))
3817 return;
3818
3819 if (radv_pipeline_has_gs(pipeline)) {
3820 const struct radv_shader_variant *gs =
3821 pipeline->shaders[MESA_SHADER_GEOMETRY];
3822
3823 vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out,
3824 pipeline->device->physical_device->rad_info.chip_class);
3825 } else if (outinfo->export_prim_id || vs->info.uses_prim_id) {
3826 vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
3827 vgt_primitiveid_en |= S_028A84_PRIMITIVEID_EN(1);
3828 }
3829
3830 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN, vgt_primitiveid_en);
3831 radeon_set_context_reg(ctx_cs, R_028A40_VGT_GS_MODE, vgt_gs_mode);
3832 }
3833
3834 static void
3835 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs,
3836 struct radeon_cmdbuf *cs,
3837 struct radv_pipeline *pipeline,
3838 struct radv_shader_variant *shader)
3839 {
3840 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3841
3842 radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
3843 radeon_emit(cs, va >> 8);
3844 radeon_emit(cs, S_00B124_MEM_BASE(va >> 40));
3845 radeon_emit(cs, shader->config.rsrc1);
3846 radeon_emit(cs, shader->config.rsrc2);
3847
3848 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3849 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3850 clip_dist_mask = outinfo->clip_dist_mask;
3851 cull_dist_mask = outinfo->cull_dist_mask;
3852 total_mask = clip_dist_mask | cull_dist_mask;
3853 bool misc_vec_ena = outinfo->writes_pointsize ||
3854 outinfo->writes_layer ||
3855 outinfo->writes_viewport_index;
3856 unsigned spi_vs_out_config, nparams;
3857
3858 /* VS is required to export at least one param. */
3859 nparams = MAX2(outinfo->param_exports, 1);
3860 spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
3861
3862 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3863 spi_vs_out_config |= S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0);
3864 }
3865
3866 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG, spi_vs_out_config);
3867
3868 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
3869 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
3870 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
3871 V_02870C_SPI_SHADER_4COMP :
3872 V_02870C_SPI_SHADER_NONE) |
3873 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
3874 V_02870C_SPI_SHADER_4COMP :
3875 V_02870C_SPI_SHADER_NONE) |
3876 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
3877 V_02870C_SPI_SHADER_4COMP :
3878 V_02870C_SPI_SHADER_NONE));
3879
3880 radeon_set_context_reg(ctx_cs, R_028818_PA_CL_VTE_CNTL,
3881 S_028818_VTX_W0_FMT(1) |
3882 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3883 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3884 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3885
3886 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
3887 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
3888 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
3889 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
3890 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
3891 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
3892 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
3893 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
3894 S_02881C_BYPASS_PRIM_RATE_COMBINER_GFX103(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3) |
3895 cull_dist_mask << 8 |
3896 clip_dist_mask);
3897
3898 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
3899 radeon_set_context_reg(ctx_cs, R_028AB4_VGT_REUSE_OFF,
3900 outinfo->writes_viewport_index);
3901 }
3902
3903 static void
3904 radv_pipeline_generate_hw_es(struct radeon_cmdbuf *cs,
3905 struct radv_pipeline *pipeline,
3906 struct radv_shader_variant *shader)
3907 {
3908 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3909
3910 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
3911 radeon_emit(cs, va >> 8);
3912 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3913 radeon_emit(cs, shader->config.rsrc1);
3914 radeon_emit(cs, shader->config.rsrc2);
3915 }
3916
3917 static void
3918 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf *cs,
3919 struct radv_pipeline *pipeline,
3920 struct radv_shader_variant *shader,
3921 const struct radv_tessellation_state *tess)
3922 {
3923 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3924 uint32_t rsrc2 = shader->config.rsrc2;
3925
3926 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
3927 radeon_emit(cs, va >> 8);
3928 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
3929
3930 rsrc2 |= S_00B52C_LDS_SIZE(tess->lds_size);
3931 if (pipeline->device->physical_device->rad_info.chip_class == GFX7 &&
3932 pipeline->device->physical_device->rad_info.family != CHIP_HAWAII)
3933 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
3934
3935 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
3936 radeon_emit(cs, shader->config.rsrc1);
3937 radeon_emit(cs, rsrc2);
3938 }
3939
3940 static void
3941 radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs,
3942 struct radeon_cmdbuf *cs,
3943 struct radv_pipeline *pipeline,
3944 struct radv_shader_variant *shader)
3945 {
3946 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3947 gl_shader_stage es_type =
3948 radv_pipeline_has_tess(pipeline) ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
3949 struct radv_shader_variant *es =
3950 es_type == MESA_SHADER_TESS_EVAL ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX];
3951 const struct gfx10_ngg_info *ngg_state = &shader->info.ngg_info;
3952
3953 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
3954 radeon_emit(cs, va >> 8);
3955 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3956 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
3957 radeon_emit(cs, shader->config.rsrc1);
3958 radeon_emit(cs, shader->config.rsrc2);
3959
3960 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3961 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3962 clip_dist_mask = outinfo->clip_dist_mask;
3963 cull_dist_mask = outinfo->cull_dist_mask;
3964 total_mask = clip_dist_mask | cull_dist_mask;
3965 bool misc_vec_ena = outinfo->writes_pointsize ||
3966 outinfo->writes_layer ||
3967 outinfo->writes_viewport_index;
3968 bool es_enable_prim_id = outinfo->export_prim_id ||
3969 (es && es->info.uses_prim_id);
3970 bool break_wave_at_eoi = false;
3971 unsigned ge_cntl;
3972 unsigned nparams;
3973
3974 if (es_type == MESA_SHADER_TESS_EVAL) {
3975 struct radv_shader_variant *gs =
3976 pipeline->shaders[MESA_SHADER_GEOMETRY];
3977
3978 if (es_enable_prim_id || (gs && gs->info.uses_prim_id))
3979 break_wave_at_eoi = true;
3980 }
3981
3982 nparams = MAX2(outinfo->param_exports, 1);
3983 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG,
3984 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
3985 S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0));
3986
3987 radeon_set_context_reg(ctx_cs, R_028708_SPI_SHADER_IDX_FORMAT,
3988 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP));
3989 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
3990 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
3991 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
3992 V_02870C_SPI_SHADER_4COMP :
3993 V_02870C_SPI_SHADER_NONE) |
3994 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
3995 V_02870C_SPI_SHADER_4COMP :
3996 V_02870C_SPI_SHADER_NONE) |
3997 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
3998 V_02870C_SPI_SHADER_4COMP :
3999 V_02870C_SPI_SHADER_NONE));
4000
4001 radeon_set_context_reg(ctx_cs, R_028818_PA_CL_VTE_CNTL,
4002 S_028818_VTX_W0_FMT(1) |
4003 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
4004 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
4005 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
4006 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
4007 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
4008 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
4009 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
4010 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
4011 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
4012 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
4013 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
4014 S_02881C_BYPASS_PRIM_RATE_COMBINER_GFX103(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3) |
4015 cull_dist_mask << 8 |
4016 clip_dist_mask);
4017
4018 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN,
4019 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
4020 S_028A84_NGG_DISABLE_PROVOK_REUSE(outinfo->export_prim_id));
4021
4022 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
4023 ngg_state->vgt_esgs_ring_itemsize);
4024
4025 /* NGG specific registers. */
4026 struct radv_shader_variant *gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
4027 uint32_t gs_num_invocations = gs ? gs->info.gs.invocations : 1;
4028
4029 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
4030 S_028A44_ES_VERTS_PER_SUBGRP(ngg_state->hw_max_esverts) |
4031 S_028A44_GS_PRIMS_PER_SUBGRP(ngg_state->max_gsprims) |
4032 S_028A44_GS_INST_PRIMS_IN_SUBGRP(ngg_state->max_gsprims * gs_num_invocations));
4033 radeon_set_context_reg(ctx_cs, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
4034 S_0287FC_MAX_VERTS_PER_SUBGROUP(ngg_state->max_out_verts));
4035 radeon_set_context_reg(ctx_cs, R_028B4C_GE_NGG_SUBGRP_CNTL,
4036 S_028B4C_PRIM_AMP_FACTOR(ngg_state->prim_amp_factor) |
4037 S_028B4C_THDS_PER_SUBGRP(0)); /* for fast launch */
4038 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
4039 S_028B90_CNT(gs_num_invocations) |
4040 S_028B90_ENABLE(gs_num_invocations > 1) |
4041 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(ngg_state->max_vert_out_per_gs_instance));
4042
4043 /* User edge flags are set by the pos exports. If user edge flags are
4044 * not used, we must use hw-generated edge flags and pass them via
4045 * the prim export to prevent drawing lines on internal edges of
4046 * decomposed primitives (such as quads) with polygon mode = lines.
4047 *
4048 * TODO: We should combine hw-generated edge flags with user edge
4049 * flags in the shader.
4050 */
4051 radeon_set_context_reg(ctx_cs, R_028838_PA_CL_NGG_CNTL,
4052 S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline) &&
4053 !radv_pipeline_has_gs(pipeline)) |
4054 /* Reuse for NGG. */
4055 S_028838_VERTEX_REUSE_DEPTH_GFX103(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3 ? 30 : 0));
4056
4057 ge_cntl = S_03096C_PRIM_GRP_SIZE(ngg_state->max_gsprims) |
4058 S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
4059 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
4060
4061 /* Bug workaround for a possible hang with non-tessellation cases.
4062 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
4063 *
4064 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
4065 */
4066 if (pipeline->device->physical_device->rad_info.chip_class == GFX10 &&
4067 !radv_pipeline_has_tess(pipeline) &&
4068 ngg_state->hw_max_esverts != 256) {
4069 ge_cntl &= C_03096C_VERT_GRP_SIZE;
4070
4071 if (ngg_state->hw_max_esverts > 5) {
4072 ge_cntl |= S_03096C_VERT_GRP_SIZE(ngg_state->hw_max_esverts - 5);
4073 }
4074 }
4075
4076 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL, ge_cntl);
4077 }
4078
4079 static void
4080 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf *cs,
4081 struct radv_pipeline *pipeline,
4082 struct radv_shader_variant *shader,
4083 const struct radv_tessellation_state *tess)
4084 {
4085 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
4086
4087 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
4088 unsigned hs_rsrc2 = shader->config.rsrc2;
4089
4090 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4091 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX10(tess->lds_size);
4092 } else {
4093 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX9(tess->lds_size);
4094 }
4095
4096 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4097 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
4098 radeon_emit(cs, va >> 8);
4099 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
4100 } else {
4101 radeon_set_sh_reg_seq(cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
4102 radeon_emit(cs, va >> 8);
4103 radeon_emit(cs, S_00B414_MEM_BASE(va >> 40));
4104 }
4105
4106 radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
4107 radeon_emit(cs, shader->config.rsrc1);
4108 radeon_emit(cs, hs_rsrc2);
4109 } else {
4110 radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
4111 radeon_emit(cs, va >> 8);
4112 radeon_emit(cs, S_00B424_MEM_BASE(va >> 40));
4113 radeon_emit(cs, shader->config.rsrc1);
4114 radeon_emit(cs, shader->config.rsrc2);
4115 }
4116 }
4117
4118 static void
4119 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf *ctx_cs,
4120 struct radeon_cmdbuf *cs,
4121 struct radv_pipeline *pipeline,
4122 const struct radv_tessellation_state *tess)
4123 {
4124 struct radv_shader_variant *vs;
4125
4126 /* Skip shaders merged into HS/GS */
4127 vs = pipeline->shaders[MESA_SHADER_VERTEX];
4128 if (!vs)
4129 return;
4130
4131 if (vs->info.vs.as_ls)
4132 radv_pipeline_generate_hw_ls(cs, pipeline, vs, tess);
4133 else if (vs->info.vs.as_es)
4134 radv_pipeline_generate_hw_es(cs, pipeline, vs);
4135 else if (vs->info.is_ngg)
4136 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, vs);
4137 else
4138 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, vs);
4139 }
4140
4141 static void
4142 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf *ctx_cs,
4143 struct radeon_cmdbuf *cs,
4144 struct radv_pipeline *pipeline,
4145 const struct radv_tessellation_state *tess)
4146 {
4147 if (!radv_pipeline_has_tess(pipeline))
4148 return;
4149
4150 struct radv_shader_variant *tes, *tcs;
4151
4152 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
4153 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
4154
4155 if (tes) {
4156 if (tes->info.is_ngg) {
4157 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, tes);
4158 } else if (tes->info.tes.as_es)
4159 radv_pipeline_generate_hw_es(cs, pipeline, tes);
4160 else
4161 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, tes);
4162 }
4163
4164 radv_pipeline_generate_hw_hs(cs, pipeline, tcs, tess);
4165
4166 radeon_set_context_reg(ctx_cs, R_028B6C_VGT_TF_PARAM,
4167 tess->tf_param);
4168
4169 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7)
4170 radeon_set_context_reg_idx(ctx_cs, R_028B58_VGT_LS_HS_CONFIG, 2,
4171 tess->ls_hs_config);
4172 else
4173 radeon_set_context_reg(ctx_cs, R_028B58_VGT_LS_HS_CONFIG,
4174 tess->ls_hs_config);
4175
4176 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 &&
4177 !radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) {
4178 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
4179 S_028A44_ES_VERTS_PER_SUBGRP(250) |
4180 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
4181 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
4182 }
4183 }
4184
4185 static void
4186 radv_pipeline_generate_hw_gs(struct radeon_cmdbuf *ctx_cs,
4187 struct radeon_cmdbuf *cs,
4188 struct radv_pipeline *pipeline,
4189 struct radv_shader_variant *gs)
4190 {
4191 const struct gfx9_gs_info *gs_state = &gs->info.gs_ring_info;
4192 unsigned gs_max_out_vertices;
4193 uint8_t *num_components;
4194 uint8_t max_stream;
4195 unsigned offset;
4196 uint64_t va;
4197
4198 gs_max_out_vertices = gs->info.gs.vertices_out;
4199 max_stream = gs->info.gs.max_stream;
4200 num_components = gs->info.gs.num_stream_output_components;
4201
4202 offset = num_components[0] * gs_max_out_vertices;
4203
4204 radeon_set_context_reg_seq(ctx_cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
4205 radeon_emit(ctx_cs, offset);
4206 if (max_stream >= 1)
4207 offset += num_components[1] * gs_max_out_vertices;
4208 radeon_emit(ctx_cs, offset);
4209 if (max_stream >= 2)
4210 offset += num_components[2] * gs_max_out_vertices;
4211 radeon_emit(ctx_cs, offset);
4212 if (max_stream >= 3)
4213 offset += num_components[3] * gs_max_out_vertices;
4214 radeon_set_context_reg(ctx_cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
4215
4216 radeon_set_context_reg_seq(ctx_cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
4217 radeon_emit(ctx_cs, num_components[0]);
4218 radeon_emit(ctx_cs, (max_stream >= 1) ? num_components[1] : 0);
4219 radeon_emit(ctx_cs, (max_stream >= 2) ? num_components[2] : 0);
4220 radeon_emit(ctx_cs, (max_stream >= 3) ? num_components[3] : 0);
4221
4222 uint32_t gs_num_invocations = gs->info.gs.invocations;
4223 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
4224 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
4225 S_028B90_ENABLE(gs_num_invocations > 0));
4226
4227 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
4228 gs_state->vgt_esgs_ring_itemsize);
4229
4230 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
4231
4232 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
4233 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4234 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
4235 radeon_emit(cs, va >> 8);
4236 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
4237 } else {
4238 radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
4239 radeon_emit(cs, va >> 8);
4240 radeon_emit(cs, S_00B214_MEM_BASE(va >> 40));
4241 }
4242
4243 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
4244 radeon_emit(cs, gs->config.rsrc1);
4245 radeon_emit(cs, gs->config.rsrc2 | S_00B22C_LDS_SIZE(gs_state->lds_size));
4246
4247 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL, gs_state->vgt_gs_onchip_cntl);
4248 radeon_set_context_reg(ctx_cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, gs_state->vgt_gs_max_prims_per_subgroup);
4249 } else {
4250 radeon_set_sh_reg_seq(cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
4251 radeon_emit(cs, va >> 8);
4252 radeon_emit(cs, S_00B224_MEM_BASE(va >> 40));
4253 radeon_emit(cs, gs->config.rsrc1);
4254 radeon_emit(cs, gs->config.rsrc2);
4255 }
4256
4257 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, pipeline->gs_copy_shader);
4258 }
4259
4260 static void
4261 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf *ctx_cs,
4262 struct radeon_cmdbuf *cs,
4263 struct radv_pipeline *pipeline)
4264 {
4265 struct radv_shader_variant *gs;
4266
4267 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
4268 if (!gs)
4269 return;
4270
4271 if (gs->info.is_ngg)
4272 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, gs);
4273 else
4274 radv_pipeline_generate_hw_gs(ctx_cs, cs, pipeline, gs);
4275
4276 radeon_set_context_reg(ctx_cs, R_028B38_VGT_GS_MAX_VERT_OUT,
4277 gs->info.gs.vertices_out);
4278 }
4279
4280 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade,
4281 bool explicit, bool float16)
4282 {
4283 uint32_t ps_input_cntl;
4284 if (offset <= AC_EXP_PARAM_OFFSET_31) {
4285 ps_input_cntl = S_028644_OFFSET(offset);
4286 if (flat_shade || explicit)
4287 ps_input_cntl |= S_028644_FLAT_SHADE(1);
4288 if (explicit) {
4289 /* Force parameter cache to be read in passthrough
4290 * mode.
4291 */
4292 ps_input_cntl |= S_028644_OFFSET(1 << 5);
4293 }
4294 if (float16) {
4295 ps_input_cntl |= S_028644_FP16_INTERP_MODE(1) |
4296 S_028644_ATTR0_VALID(1);
4297 }
4298 } else {
4299 /* The input is a DEFAULT_VAL constant. */
4300 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
4301 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
4302 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
4303 ps_input_cntl = S_028644_OFFSET(0x20) |
4304 S_028644_DEFAULT_VAL(offset);
4305 }
4306 return ps_input_cntl;
4307 }
4308
4309 static void
4310 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf *ctx_cs,
4311 struct radv_pipeline *pipeline)
4312 {
4313 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4314 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
4315 uint32_t ps_input_cntl[32];
4316
4317 unsigned ps_offset = 0;
4318
4319 if (ps->info.ps.prim_id_input) {
4320 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
4321 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
4322 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false, false);
4323 ++ps_offset;
4324 }
4325 }
4326
4327 if (ps->info.ps.layer_input ||
4328 ps->info.needs_multiview_view_index) {
4329 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
4330 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
4331 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false, false);
4332 else
4333 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true, false, false);
4334 ++ps_offset;
4335 }
4336
4337 if (ps->info.ps.viewport_index_input) {
4338 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VIEWPORT];
4339 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
4340 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false, false);
4341 else
4342 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true, false, false);
4343 ++ps_offset;
4344 }
4345
4346 if (ps->info.ps.has_pcoord) {
4347 unsigned val;
4348 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
4349 ps_input_cntl[ps_offset] = val;
4350 ps_offset++;
4351 }
4352
4353 if (ps->info.ps.num_input_clips_culls) {
4354 unsigned vs_offset;
4355
4356 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST0];
4357 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
4358 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false, false);
4359 ++ps_offset;
4360 }
4361
4362 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST1];
4363 if (vs_offset != AC_EXP_PARAM_UNDEFINED &&
4364 ps->info.ps.num_input_clips_culls > 4) {
4365 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false, false);
4366 ++ps_offset;
4367 }
4368 }
4369
4370 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.ps.input_mask; ++i) {
4371 unsigned vs_offset;
4372 bool flat_shade;
4373 bool explicit;
4374 bool float16;
4375 if (!(ps->info.ps.input_mask & (1u << i)))
4376 continue;
4377
4378 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
4379 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
4380 ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
4381 ++ps_offset;
4382 continue;
4383 }
4384
4385 flat_shade = !!(ps->info.ps.flat_shaded_mask & (1u << ps_offset));
4386 explicit = !!(ps->info.ps.explicit_shaded_mask & (1u << ps_offset));
4387 float16 = !!(ps->info.ps.float16_shaded_mask & (1u << ps_offset));
4388
4389 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade, explicit, float16);
4390 ++ps_offset;
4391 }
4392
4393 if (ps_offset) {
4394 radeon_set_context_reg_seq(ctx_cs, R_028644_SPI_PS_INPUT_CNTL_0, ps_offset);
4395 for (unsigned i = 0; i < ps_offset; i++) {
4396 radeon_emit(ctx_cs, ps_input_cntl[i]);
4397 }
4398 }
4399 }
4400
4401 static uint32_t
4402 radv_compute_db_shader_control(const struct radv_device *device,
4403 const struct radv_pipeline *pipeline,
4404 const struct radv_shader_variant *ps)
4405 {
4406 unsigned conservative_z_export = V_02880C_EXPORT_ANY_Z;
4407 unsigned z_order;
4408 if (ps->info.ps.early_fragment_test || !ps->info.ps.writes_memory)
4409 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
4410 else
4411 z_order = V_02880C_LATE_Z;
4412
4413 if (ps->info.ps.depth_layout == FRAG_DEPTH_LAYOUT_GREATER)
4414 conservative_z_export = V_02880C_EXPORT_GREATER_THAN_Z;
4415 else if (ps->info.ps.depth_layout == FRAG_DEPTH_LAYOUT_LESS)
4416 conservative_z_export = V_02880C_EXPORT_LESS_THAN_Z;
4417
4418 bool disable_rbplus = device->physical_device->rad_info.has_rbplus &&
4419 !device->physical_device->rad_info.rbplus_allowed;
4420
4421 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
4422 * but this appears to break Project Cars (DXVK). See
4423 * https://bugs.freedesktop.org/show_bug.cgi?id=109401
4424 */
4425 bool mask_export_enable = ps->info.ps.writes_sample_mask;
4426
4427 return S_02880C_Z_EXPORT_ENABLE(ps->info.ps.writes_z) |
4428 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.ps.writes_stencil) |
4429 S_02880C_KILL_ENABLE(!!ps->info.ps.can_discard) |
4430 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable) |
4431 S_02880C_CONSERVATIVE_Z_EXPORT(conservative_z_export) |
4432 S_02880C_Z_ORDER(z_order) |
4433 S_02880C_DEPTH_BEFORE_SHADER(ps->info.ps.early_fragment_test) |
4434 S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps->info.ps.post_depth_coverage) |
4435 S_02880C_EXEC_ON_HIER_FAIL(ps->info.ps.writes_memory) |
4436 S_02880C_EXEC_ON_NOOP(ps->info.ps.writes_memory) |
4437 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus);
4438 }
4439
4440 static void
4441 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf *ctx_cs,
4442 struct radeon_cmdbuf *cs,
4443 struct radv_pipeline *pipeline)
4444 {
4445 struct radv_shader_variant *ps;
4446 uint64_t va;
4447 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
4448
4449 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4450 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
4451
4452 radeon_set_sh_reg_seq(cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
4453 radeon_emit(cs, va >> 8);
4454 radeon_emit(cs, S_00B024_MEM_BASE(va >> 40));
4455 radeon_emit(cs, ps->config.rsrc1);
4456 radeon_emit(cs, ps->config.rsrc2);
4457
4458 radeon_set_context_reg(ctx_cs, R_02880C_DB_SHADER_CONTROL,
4459 radv_compute_db_shader_control(pipeline->device,
4460 pipeline, ps));
4461
4462 radeon_set_context_reg(ctx_cs, R_0286CC_SPI_PS_INPUT_ENA,
4463 ps->config.spi_ps_input_ena);
4464
4465 radeon_set_context_reg(ctx_cs, R_0286D0_SPI_PS_INPUT_ADDR,
4466 ps->config.spi_ps_input_addr);
4467
4468 radeon_set_context_reg(ctx_cs, R_0286D8_SPI_PS_IN_CONTROL,
4469 S_0286D8_NUM_INTERP(ps->info.ps.num_interp) |
4470 S_0286D8_PS_W32_EN(ps->info.wave_size == 32));
4471
4472 radeon_set_context_reg(ctx_cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl);
4473
4474 radeon_set_context_reg(ctx_cs, R_028710_SPI_SHADER_Z_FORMAT,
4475 ac_get_spi_shader_z_format(ps->info.ps.writes_z,
4476 ps->info.ps.writes_stencil,
4477 ps->info.ps.writes_sample_mask));
4478
4479 if (pipeline->device->dfsm_allowed) {
4480 /* optimise this? */
4481 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
4482 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
4483 }
4484 }
4485
4486 static void
4487 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf *ctx_cs,
4488 struct radv_pipeline *pipeline)
4489 {
4490 if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10 ||
4491 pipeline->device->physical_device->rad_info.chip_class >= GFX10)
4492 return;
4493
4494 unsigned vtx_reuse_depth = 30;
4495 if (radv_pipeline_has_tess(pipeline) &&
4496 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
4497 vtx_reuse_depth = 14;
4498 }
4499 radeon_set_context_reg(ctx_cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
4500 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth));
4501 }
4502
4503 static uint32_t
4504 radv_compute_vgt_shader_stages_en(const struct radv_pipeline *pipeline)
4505 {
4506 uint32_t stages = 0;
4507 if (radv_pipeline_has_tess(pipeline)) {
4508 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
4509 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
4510
4511 if (radv_pipeline_has_gs(pipeline))
4512 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
4513 S_028B54_GS_EN(1);
4514 else if (radv_pipeline_has_ngg(pipeline))
4515 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
4516 else
4517 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
4518 } else if (radv_pipeline_has_gs(pipeline)) {
4519 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
4520 S_028B54_GS_EN(1);
4521 } else if (radv_pipeline_has_ngg(pipeline)) {
4522 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
4523 }
4524
4525 if (radv_pipeline_has_ngg(pipeline)) {
4526 stages |= S_028B54_PRIMGEN_EN(1);
4527 if (pipeline->streamout_shader)
4528 stages |= S_028B54_NGG_WAVE_ID_EN(1);
4529 if (radv_pipeline_has_ngg_passthrough(pipeline))
4530 stages |= S_028B54_PRIMGEN_PASSTHRU_EN(1);
4531 } else if (radv_pipeline_has_gs(pipeline)) {
4532 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
4533 }
4534
4535 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
4536 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
4537
4538 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4539 uint8_t hs_size = 64, gs_size = 64, vs_size = 64;
4540
4541 if (radv_pipeline_has_tess(pipeline))
4542 hs_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.wave_size;
4543
4544 if (pipeline->shaders[MESA_SHADER_GEOMETRY]) {
4545 vs_size = gs_size = pipeline->shaders[MESA_SHADER_GEOMETRY]->info.wave_size;
4546 if (pipeline->gs_copy_shader)
4547 vs_size = pipeline->gs_copy_shader->info.wave_size;
4548 } else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
4549 vs_size = pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.wave_size;
4550 else if (pipeline->shaders[MESA_SHADER_VERTEX])
4551 vs_size = pipeline->shaders[MESA_SHADER_VERTEX]->info.wave_size;
4552
4553 if (radv_pipeline_has_ngg(pipeline))
4554 gs_size = vs_size;
4555
4556 /* legacy GS only supports Wave64 */
4557 stages |= S_028B54_HS_W32_EN(hs_size == 32 ? 1 : 0) |
4558 S_028B54_GS_W32_EN(gs_size == 32 ? 1 : 0) |
4559 S_028B54_VS_W32_EN(vs_size == 32 ? 1 : 0);
4560 }
4561
4562 return stages;
4563 }
4564
4565 static uint32_t
4566 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo *pCreateInfo)
4567 {
4568 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
4569 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
4570
4571 if (!discard_rectangle_info)
4572 return 0xffff;
4573
4574 unsigned mask = 0;
4575
4576 for (unsigned i = 0; i < (1u << MAX_DISCARD_RECTANGLES); ++i) {
4577 /* Interpret i as a bitmask, and then set the bit in the mask if
4578 * that combination of rectangles in which the pixel is contained
4579 * should pass the cliprect test. */
4580 unsigned relevant_subset = i & ((1u << discard_rectangle_info->discardRectangleCount) - 1);
4581
4582 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT &&
4583 !relevant_subset)
4584 continue;
4585
4586 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT &&
4587 relevant_subset)
4588 continue;
4589
4590 mask |= 1u << i;
4591 }
4592
4593 return mask;
4594 }
4595
4596 static void
4597 gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf *ctx_cs,
4598 struct radv_pipeline *pipeline,
4599 const struct radv_tessellation_state *tess)
4600 {
4601 bool break_wave_at_eoi = false;
4602 unsigned primgroup_size;
4603 unsigned vertgroup_size = 256; /* 256 = disable vertex grouping */
4604
4605 if (radv_pipeline_has_tess(pipeline)) {
4606 primgroup_size = tess->num_patches; /* must be a multiple of NUM_PATCHES */
4607 } else if (radv_pipeline_has_gs(pipeline)) {
4608 const struct gfx9_gs_info *gs_state =
4609 &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs_ring_info;
4610 unsigned vgt_gs_onchip_cntl = gs_state->vgt_gs_onchip_cntl;
4611 primgroup_size = G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl);
4612 } else {
4613 primgroup_size = 128; /* recommended without a GS and tess */
4614 }
4615
4616 if (radv_pipeline_has_tess(pipeline)) {
4617 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
4618 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.uses_prim_id)
4619 break_wave_at_eoi = true;
4620 }
4621
4622 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL,
4623 S_03096C_PRIM_GRP_SIZE(primgroup_size) |
4624 S_03096C_VERT_GRP_SIZE(vertgroup_size) |
4625 S_03096C_PACKET_TO_ONE_PA(0) /* line stipple */ |
4626 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi));
4627 }
4628
4629 static void
4630 radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
4631 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4632 const struct radv_graphics_pipeline_create_info *extra,
4633 const struct radv_blend_state *blend,
4634 const struct radv_tessellation_state *tess,
4635 unsigned prim, unsigned gs_out)
4636 {
4637 struct radeon_cmdbuf *ctx_cs = &pipeline->ctx_cs;
4638 struct radeon_cmdbuf *cs = &pipeline->cs;
4639
4640 cs->max_dw = 64;
4641 ctx_cs->max_dw = 256;
4642 cs->buf = malloc(4 * (cs->max_dw + ctx_cs->max_dw));
4643 ctx_cs->buf = cs->buf + cs->max_dw;
4644
4645 radv_pipeline_generate_depth_stencil_state(ctx_cs, pipeline, pCreateInfo, extra);
4646 radv_pipeline_generate_blend_state(ctx_cs, pipeline, blend);
4647 radv_pipeline_generate_raster_state(ctx_cs, pipeline, pCreateInfo);
4648 radv_pipeline_generate_multisample_state(ctx_cs, pipeline);
4649 radv_pipeline_generate_vgt_gs_mode(ctx_cs, pipeline);
4650 radv_pipeline_generate_vertex_shader(ctx_cs, cs, pipeline, tess);
4651 radv_pipeline_generate_tess_shaders(ctx_cs, cs, pipeline, tess);
4652 radv_pipeline_generate_geometry_shader(ctx_cs, cs, pipeline);
4653 radv_pipeline_generate_fragment_shader(ctx_cs, cs, pipeline);
4654 radv_pipeline_generate_ps_inputs(ctx_cs, pipeline);
4655 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs, pipeline);
4656 radv_pipeline_generate_binning_state(ctx_cs, pipeline, pCreateInfo, blend);
4657
4658 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 && !radv_pipeline_has_ngg(pipeline))
4659 gfx10_pipeline_generate_ge_cntl(ctx_cs, pipeline, tess);
4660
4661 radeon_set_context_reg(ctx_cs, R_028B54_VGT_SHADER_STAGES_EN, radv_compute_vgt_shader_stages_en(pipeline));
4662
4663 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
4664 radeon_set_uconfig_reg_idx(pipeline->device->physical_device,
4665 cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
4666 } else {
4667 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
4668 }
4669 radeon_set_context_reg(ctx_cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out);
4670
4671 radeon_set_context_reg(ctx_cs, R_02820C_PA_SC_CLIPRECT_RULE, radv_compute_cliprect_rule(pCreateInfo));
4672
4673 pipeline->ctx_cs_hash = _mesa_hash_data(ctx_cs->buf, ctx_cs->cdw * 4);
4674
4675 assert(ctx_cs->cdw <= ctx_cs->max_dw);
4676 assert(cs->cdw <= cs->max_dw);
4677 }
4678
4679 static struct radv_ia_multi_vgt_param_helpers
4680 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
4681 const struct radv_tessellation_state *tess,
4682 uint32_t prim)
4683 {
4684 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param = {0};
4685 const struct radv_device *device = pipeline->device;
4686
4687 if (radv_pipeline_has_tess(pipeline))
4688 ia_multi_vgt_param.primgroup_size = tess->num_patches;
4689 else if (radv_pipeline_has_gs(pipeline))
4690 ia_multi_vgt_param.primgroup_size = 64;
4691 else
4692 ia_multi_vgt_param.primgroup_size = 128; /* recommended without a GS */
4693
4694 /* GS requirement. */
4695 ia_multi_vgt_param.partial_es_wave = false;
4696 if (radv_pipeline_has_gs(pipeline) && device->physical_device->rad_info.chip_class <= GFX8)
4697 if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3)
4698 ia_multi_vgt_param.partial_es_wave = true;
4699
4700 ia_multi_vgt_param.wd_switch_on_eop = false;
4701 if (device->physical_device->rad_info.chip_class >= GFX7) {
4702 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
4703 * 4 shader engines. Set 1 to pass the assertion below.
4704 * The other cases are hardware requirements. */
4705 if (device->physical_device->rad_info.max_se < 4 ||
4706 prim == V_008958_DI_PT_POLYGON ||
4707 prim == V_008958_DI_PT_LINELOOP ||
4708 prim == V_008958_DI_PT_TRIFAN ||
4709 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
4710 (pipeline->graphics.prim_restart_enable &&
4711 (device->physical_device->rad_info.family < CHIP_POLARIS10 ||
4712 (prim != V_008958_DI_PT_POINTLIST &&
4713 prim != V_008958_DI_PT_LINESTRIP))))
4714 ia_multi_vgt_param.wd_switch_on_eop = true;
4715 }
4716
4717 ia_multi_vgt_param.ia_switch_on_eoi = false;
4718 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.prim_id_input)
4719 ia_multi_vgt_param.ia_switch_on_eoi = true;
4720 if (radv_pipeline_has_gs(pipeline) &&
4721 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.uses_prim_id)
4722 ia_multi_vgt_param.ia_switch_on_eoi = true;
4723 if (radv_pipeline_has_tess(pipeline)) {
4724 /* SWITCH_ON_EOI must be set if PrimID is used. */
4725 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
4726 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.uses_prim_id)
4727 ia_multi_vgt_param.ia_switch_on_eoi = true;
4728 }
4729
4730 ia_multi_vgt_param.partial_vs_wave = false;
4731 if (radv_pipeline_has_tess(pipeline)) {
4732 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
4733 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
4734 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
4735 device->physical_device->rad_info.family == CHIP_BONAIRE) &&
4736 radv_pipeline_has_gs(pipeline))
4737 ia_multi_vgt_param.partial_vs_wave = true;
4738 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
4739 if (device->physical_device->rad_info.has_distributed_tess) {
4740 if (radv_pipeline_has_gs(pipeline)) {
4741 if (device->physical_device->rad_info.chip_class <= GFX8)
4742 ia_multi_vgt_param.partial_es_wave = true;
4743 } else {
4744 ia_multi_vgt_param.partial_vs_wave = true;
4745 }
4746 }
4747 }
4748
4749 /* Workaround for a VGT hang when strip primitive types are used with
4750 * primitive restart.
4751 */
4752 if (pipeline->graphics.prim_restart_enable &&
4753 (prim == V_008958_DI_PT_LINESTRIP ||
4754 prim == V_008958_DI_PT_TRISTRIP ||
4755 prim == V_008958_DI_PT_LINESTRIP_ADJ ||
4756 prim == V_008958_DI_PT_TRISTRIP_ADJ)) {
4757 ia_multi_vgt_param.partial_vs_wave = true;
4758 }
4759
4760 if (radv_pipeline_has_gs(pipeline)) {
4761 /* On these chips there is the possibility of a hang if the
4762 * pipeline uses a GS and partial_vs_wave is not set.
4763 *
4764 * This mostly does not hit 4-SE chips, as those typically set
4765 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
4766 * with GS due to another workaround.
4767 *
4768 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
4769 */
4770 if (device->physical_device->rad_info.family == CHIP_TONGA ||
4771 device->physical_device->rad_info.family == CHIP_FIJI ||
4772 device->physical_device->rad_info.family == CHIP_POLARIS10 ||
4773 device->physical_device->rad_info.family == CHIP_POLARIS11 ||
4774 device->physical_device->rad_info.family == CHIP_POLARIS12 ||
4775 device->physical_device->rad_info.family == CHIP_VEGAM) {
4776 ia_multi_vgt_param.partial_vs_wave = true;
4777 }
4778 }
4779
4780 ia_multi_vgt_param.base =
4781 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param.primgroup_size - 1) |
4782 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
4783 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == GFX8 ? 2 : 0) |
4784 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
4785 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
4786
4787 return ia_multi_vgt_param;
4788 }
4789
4790
4791 static void
4792 radv_compute_vertex_input_state(struct radv_pipeline *pipeline,
4793 const VkGraphicsPipelineCreateInfo *pCreateInfo)
4794 {
4795 const VkPipelineVertexInputStateCreateInfo *vi_info =
4796 pCreateInfo->pVertexInputState;
4797 struct radv_vertex_elements_info *velems = &pipeline->vertex_elements;
4798
4799 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
4800 const VkVertexInputAttributeDescription *desc =
4801 &vi_info->pVertexAttributeDescriptions[i];
4802 unsigned loc = desc->location;
4803 const struct vk_format_description *format_desc;
4804
4805 format_desc = vk_format_description(desc->format);
4806
4807 velems->format_size[loc] = format_desc->block.bits / 8;
4808 }
4809
4810 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
4811 const VkVertexInputBindingDescription *desc =
4812 &vi_info->pVertexBindingDescriptions[i];
4813
4814 pipeline->binding_stride[desc->binding] = desc->stride;
4815 pipeline->num_vertex_bindings =
4816 MAX2(pipeline->num_vertex_bindings, desc->binding + 1);
4817 }
4818 }
4819
4820 static struct radv_shader_variant *
4821 radv_pipeline_get_streamout_shader(struct radv_pipeline *pipeline)
4822 {
4823 int i;
4824
4825 for (i = MESA_SHADER_GEOMETRY; i >= MESA_SHADER_VERTEX; i--) {
4826 struct radv_shader_variant *shader =
4827 radv_get_shader(pipeline, i);
4828
4829 if (shader && shader->info.so.num_outputs > 0)
4830 return shader;
4831 }
4832
4833 return NULL;
4834 }
4835
4836 static VkResult
4837 radv_secure_compile(struct radv_pipeline *pipeline,
4838 struct radv_device *device,
4839 const struct radv_pipeline_key *key,
4840 const VkPipelineShaderStageCreateInfo **pStages,
4841 const VkPipelineCreateFlags flags,
4842 unsigned num_stages)
4843 {
4844 uint8_t allowed_pipeline_hashes[2][20];
4845 radv_hash_shaders(allowed_pipeline_hashes[0], pStages,
4846 pipeline->layout, key, get_hash_flags(device));
4847
4848 /* Generate the GC copy hash */
4849 memcpy(allowed_pipeline_hashes[1], allowed_pipeline_hashes[0], 20);
4850 allowed_pipeline_hashes[1][0] ^= 1;
4851
4852 uint8_t allowed_hashes[2][20];
4853 for (unsigned i = 0; i < 2; ++i) {
4854 disk_cache_compute_key(device->physical_device->disk_cache,
4855 allowed_pipeline_hashes[i], 20,
4856 allowed_hashes[i]);
4857 }
4858
4859 /* Do an early exit if all cache entries are already there. */
4860 bool may_need_copy_shader = pStages[MESA_SHADER_GEOMETRY];
4861 void *main_entry = disk_cache_get(device->physical_device->disk_cache, allowed_hashes[0], NULL);
4862 void *copy_entry = NULL;
4863 if (may_need_copy_shader)
4864 copy_entry = disk_cache_get(device->physical_device->disk_cache, allowed_hashes[1], NULL);
4865
4866 bool has_all_cache_entries = main_entry && (!may_need_copy_shader || copy_entry);
4867 free(main_entry);
4868 free(copy_entry);
4869
4870 if(has_all_cache_entries)
4871 return VK_SUCCESS;
4872
4873 unsigned process = 0;
4874 uint8_t sc_threads = device->instance->num_sc_threads;
4875 while (true) {
4876 mtx_lock(&device->sc_state->secure_compile_mutex);
4877 if (device->sc_state->secure_compile_thread_counter < sc_threads) {
4878 device->sc_state->secure_compile_thread_counter++;
4879 for (unsigned i = 0; i < sc_threads; i++) {
4880 if (!device->sc_state->secure_compile_processes[i].in_use) {
4881 device->sc_state->secure_compile_processes[i].in_use = true;
4882 process = i;
4883 break;
4884 }
4885 }
4886 mtx_unlock(&device->sc_state->secure_compile_mutex);
4887 break;
4888 }
4889 mtx_unlock(&device->sc_state->secure_compile_mutex);
4890 }
4891
4892 int fd_secure_input = device->sc_state->secure_compile_processes[process].fd_secure_input;
4893 int fd_secure_output = device->sc_state->secure_compile_processes[process].fd_secure_output;
4894
4895 /* Fork a copy of the slim untainted secure compile process */
4896 enum radv_secure_compile_type sc_type = RADV_SC_TYPE_FORK_DEVICE;
4897 write(fd_secure_input, &sc_type, sizeof(sc_type));
4898
4899 if (!radv_sc_read(fd_secure_output, &sc_type, sizeof(sc_type), true) ||
4900 sc_type != RADV_SC_TYPE_INIT_SUCCESS)
4901 return VK_ERROR_DEVICE_LOST;
4902
4903 fd_secure_input = device->sc_state->secure_compile_processes[process].fd_server;
4904 fd_secure_output = device->sc_state->secure_compile_processes[process].fd_client;
4905
4906 /* Write pipeline / shader module out to secure process via pipe */
4907 sc_type = RADV_SC_TYPE_COMPILE_PIPELINE;
4908 write(fd_secure_input, &sc_type, sizeof(sc_type));
4909
4910 /* Write pipeline layout out to secure process */
4911 struct radv_pipeline_layout *layout = pipeline->layout;
4912 write(fd_secure_input, layout, sizeof(struct radv_pipeline_layout));
4913 write(fd_secure_input, &layout->num_sets, sizeof(uint32_t));
4914 for (uint32_t set = 0; set < layout->num_sets; set++) {
4915 write(fd_secure_input, &layout->set[set].layout->layout_size, sizeof(uint32_t));
4916 write(fd_secure_input, layout->set[set].layout, layout->set[set].layout->layout_size);
4917 }
4918
4919 /* Write pipeline key out to secure process */
4920 write(fd_secure_input, key, sizeof(struct radv_pipeline_key));
4921
4922 /* Write pipeline create flags out to secure process */
4923 write(fd_secure_input, &flags, sizeof(VkPipelineCreateFlags));
4924
4925 /* Write stage and shader information out to secure process */
4926 write(fd_secure_input, &num_stages, sizeof(uint32_t));
4927 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
4928 if (!pStages[i])
4929 continue;
4930
4931 /* Write stage out to secure process */
4932 gl_shader_stage stage = ffs(pStages[i]->stage) - 1;
4933 write(fd_secure_input, &stage, sizeof(gl_shader_stage));
4934
4935 /* Write entry point name out to secure process */
4936 size_t name_size = strlen(pStages[i]->pName) + 1;
4937 write(fd_secure_input, &name_size, sizeof(size_t));
4938 write(fd_secure_input, pStages[i]->pName, name_size);
4939
4940 /* Write shader module out to secure process */
4941 struct radv_shader_module *module = radv_shader_module_from_handle(pStages[i]->module);
4942 assert(!module->nir);
4943 size_t module_size = sizeof(struct radv_shader_module) + module->size;
4944 write(fd_secure_input, &module_size, sizeof(size_t));
4945 write(fd_secure_input, module, module_size);
4946
4947 /* Write specialization info out to secure process */
4948 const VkSpecializationInfo *specInfo = pStages[i]->pSpecializationInfo;
4949 bool has_spec_info = specInfo ? true : false;
4950 write(fd_secure_input, &has_spec_info, sizeof(bool));
4951 if (specInfo) {
4952 write(fd_secure_input, &specInfo->dataSize, sizeof(size_t));
4953 write(fd_secure_input, specInfo->pData, specInfo->dataSize);
4954
4955 write(fd_secure_input, &specInfo->mapEntryCount, sizeof(uint32_t));
4956 for (uint32_t j = 0; j < specInfo->mapEntryCount; j++)
4957 write(fd_secure_input, &specInfo->pMapEntries[j], sizeof(VkSpecializationMapEntry));
4958 }
4959 }
4960
4961 /* Read the data returned from the secure process */
4962 while (sc_type != RADV_SC_TYPE_COMPILE_PIPELINE_FINISHED) {
4963 if (!radv_sc_read(fd_secure_output, &sc_type, sizeof(sc_type), true))
4964 return VK_ERROR_DEVICE_LOST;
4965
4966 if (sc_type == RADV_SC_TYPE_WRITE_DISK_CACHE) {
4967 assert(device->physical_device->disk_cache);
4968
4969 uint8_t disk_sha1[20];
4970 if (!radv_sc_read(fd_secure_output, disk_sha1, sizeof(uint8_t) * 20, true))
4971 return VK_ERROR_DEVICE_LOST;
4972
4973 if (memcmp(disk_sha1, allowed_hashes[0], 20) &&
4974 memcmp(disk_sha1, allowed_hashes[1], 20))
4975 return VK_ERROR_DEVICE_LOST;
4976
4977 uint32_t entry_size;
4978 if (!radv_sc_read(fd_secure_output, &entry_size, sizeof(uint32_t), true))
4979 return VK_ERROR_DEVICE_LOST;
4980
4981 struct cache_entry *entry = malloc(entry_size);
4982 if (!radv_sc_read(fd_secure_output, entry, entry_size, true))
4983 return VK_ERROR_DEVICE_LOST;
4984
4985 disk_cache_put(device->physical_device->disk_cache,
4986 disk_sha1, entry, entry_size,
4987 NULL);
4988
4989 free(entry);
4990 } else if (sc_type == RADV_SC_TYPE_READ_DISK_CACHE) {
4991 uint8_t disk_sha1[20];
4992 if (!radv_sc_read(fd_secure_output, disk_sha1, sizeof(uint8_t) * 20, true))
4993 return VK_ERROR_DEVICE_LOST;
4994
4995 if (memcmp(disk_sha1, allowed_hashes[0], 20) &&
4996 memcmp(disk_sha1, allowed_hashes[1], 20))
4997 return VK_ERROR_DEVICE_LOST;
4998
4999 size_t size;
5000 struct cache_entry *entry = (struct cache_entry *)
5001 disk_cache_get(device->physical_device->disk_cache,
5002 disk_sha1, &size);
5003
5004 uint8_t found = entry ? 1 : 0;
5005 write(fd_secure_input, &found, sizeof(uint8_t));
5006
5007 if (found) {
5008 write(fd_secure_input, &size, sizeof(size_t));
5009 write(fd_secure_input, entry, size);
5010 }
5011
5012 free(entry);
5013 }
5014 }
5015
5016 sc_type = RADV_SC_TYPE_DESTROY_DEVICE;
5017 write(fd_secure_input, &sc_type, sizeof(sc_type));
5018
5019 mtx_lock(&device->sc_state->secure_compile_mutex);
5020 device->sc_state->secure_compile_thread_counter--;
5021 device->sc_state->secure_compile_processes[process].in_use = false;
5022 mtx_unlock(&device->sc_state->secure_compile_mutex);
5023
5024 return VK_SUCCESS;
5025 }
5026
5027 static VkResult
5028 radv_pipeline_init(struct radv_pipeline *pipeline,
5029 struct radv_device *device,
5030 struct radv_pipeline_cache *cache,
5031 const VkGraphicsPipelineCreateInfo *pCreateInfo,
5032 const struct radv_graphics_pipeline_create_info *extra)
5033 {
5034 VkResult result;
5035 bool has_view_index = false;
5036
5037 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
5038 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
5039 if (subpass->view_mask)
5040 has_view_index = true;
5041
5042 pipeline->device = device;
5043 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
5044 assert(pipeline->layout);
5045
5046 struct radv_blend_state blend = radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
5047
5048 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
5049 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
5050 radv_init_feedback(creation_feedback);
5051
5052 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
5053
5054 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
5055 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
5056 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
5057 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
5058 pStages[stage] = &pCreateInfo->pStages[i];
5059 if(creation_feedback)
5060 stage_feedbacks[stage] = &creation_feedback->pPipelineStageCreationFeedbacks[i];
5061 }
5062
5063 struct radv_pipeline_key key = radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &blend, has_view_index);
5064 if (radv_device_use_secure_compile(device->instance)) {
5065 return radv_secure_compile(pipeline, device, &key, pStages, pCreateInfo->flags, pCreateInfo->stageCount);
5066 } else {
5067 result = radv_create_shaders(pipeline, device, cache, &key, pStages,
5068 pCreateInfo->flags, pipeline_feedback,
5069 stage_feedbacks);
5070 if (result != VK_SUCCESS)
5071 return result;
5072 }
5073
5074 pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
5075 radv_pipeline_init_multisample_state(pipeline, &blend, pCreateInfo);
5076 uint32_t gs_out;
5077 uint32_t prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
5078
5079 pipeline->graphics.topology = pCreateInfo->pInputAssemblyState->topology;
5080 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
5081
5082 if (radv_pipeline_has_gs(pipeline)) {
5083 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
5084 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
5085 } else if (radv_pipeline_has_tess(pipeline)) {
5086 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.point_mode)
5087 gs_out = V_028A6C_OUTPRIM_TYPE_POINTLIST;
5088 else
5089 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.primitive_mode);
5090 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
5091 } else {
5092 gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
5093 }
5094 if (extra && extra->use_rectlist) {
5095 prim = V_008958_DI_PT_RECTLIST;
5096 gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
5097 pipeline->graphics.can_use_guardband = true;
5098 if (radv_pipeline_has_ngg(pipeline))
5099 gs_out = V_028A6C_VGT_OUT_RECT_V0;
5100 }
5101 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
5102 /* prim vertex count will need TESS changes */
5103 pipeline->graphics.prim_vertex_count = prim_size_table[prim];
5104
5105 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
5106
5107 /* Ensure that some export memory is always allocated, for two reasons:
5108 *
5109 * 1) Correctness: The hardware ignores the EXEC mask if no export
5110 * memory is allocated, so KILL and alpha test do not work correctly
5111 * without this.
5112 * 2) Performance: Every shader needs at least a NULL export, even when
5113 * it writes no color/depth output. The NULL export instruction
5114 * stalls without this setting.
5115 *
5116 * Don't add this to CB_SHADER_MASK.
5117 *
5118 * GFX10 supports pixel shaders without exports by setting both the
5119 * color and Z formats to SPI_SHADER_ZERO. The hw will skip export
5120 * instructions if any are present.
5121 */
5122 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
5123 if ((pipeline->device->physical_device->rad_info.chip_class <= GFX9 ||
5124 ps->info.ps.can_discard) &&
5125 !blend.spi_shader_col_format) {
5126 if (!ps->info.ps.writes_z &&
5127 !ps->info.ps.writes_stencil &&
5128 !ps->info.ps.writes_sample_mask)
5129 blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
5130 }
5131
5132 blend.cb_shader_mask = ps->info.ps.cb_shader_mask;
5133
5134 if (extra &&
5135 (extra->custom_blend_mode == V_028808_CB_ELIMINATE_FAST_CLEAR ||
5136 extra->custom_blend_mode == V_028808_CB_FMASK_DECOMPRESS ||
5137 extra->custom_blend_mode == V_028808_CB_DCC_DECOMPRESS ||
5138 extra->custom_blend_mode == V_028808_CB_RESOLVE)) {
5139 /* According to the CB spec states, CB_SHADER_MASK should be
5140 * set to enable writes to all four channels of MRT0.
5141 */
5142 blend.cb_shader_mask = 0xf;
5143 }
5144
5145 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
5146 if (pipeline->shaders[i]) {
5147 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
5148 }
5149 }
5150
5151 if (radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) {
5152 struct radv_shader_variant *gs =
5153 pipeline->shaders[MESA_SHADER_GEOMETRY];
5154
5155 calculate_gs_ring_sizes(pipeline, &gs->info.gs_ring_info);
5156 }
5157
5158 struct radv_tessellation_state tess = {0};
5159 if (radv_pipeline_has_tess(pipeline)) {
5160 if (prim == V_008958_DI_PT_PATCH) {
5161 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
5162 pipeline->graphics.prim_vertex_count.incr = 1;
5163 }
5164 tess = calculate_tess_state(pipeline, pCreateInfo);
5165 }
5166
5167 pipeline->graphics.ia_multi_vgt_param = radv_compute_ia_multi_vgt_param_helpers(pipeline, &tess, prim);
5168
5169 radv_compute_vertex_input_state(pipeline, pCreateInfo);
5170
5171 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
5172 pipeline->user_data_0[i] = radv_pipeline_stage_to_user_data_0(pipeline, i, device->physical_device->rad_info.chip_class);
5173
5174 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
5175 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
5176 if (loc->sgpr_idx != -1) {
5177 pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX];
5178 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
5179 if (radv_get_shader(pipeline, MESA_SHADER_VERTEX)->info.vs.needs_draw_id)
5180 pipeline->graphics.vtx_emit_num = 3;
5181 else
5182 pipeline->graphics.vtx_emit_num = 2;
5183 }
5184
5185 /* Find the last vertex shader stage that eventually uses streamout. */
5186 pipeline->streamout_shader = radv_pipeline_get_streamout_shader(pipeline);
5187
5188 result = radv_pipeline_scratch_init(device, pipeline);
5189 radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend, &tess, prim, gs_out);
5190
5191 return result;
5192 }
5193
5194 VkResult
5195 radv_graphics_pipeline_create(
5196 VkDevice _device,
5197 VkPipelineCache _cache,
5198 const VkGraphicsPipelineCreateInfo *pCreateInfo,
5199 const struct radv_graphics_pipeline_create_info *extra,
5200 const VkAllocationCallbacks *pAllocator,
5201 VkPipeline *pPipeline)
5202 {
5203 RADV_FROM_HANDLE(radv_device, device, _device);
5204 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
5205 struct radv_pipeline *pipeline;
5206 VkResult result;
5207
5208 pipeline = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*pipeline), 8,
5209 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5210 if (pipeline == NULL)
5211 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5212
5213 vk_object_base_init(&device->vk, &pipeline->base,
5214 VK_OBJECT_TYPE_PIPELINE);
5215
5216 result = radv_pipeline_init(pipeline, device, cache,
5217 pCreateInfo, extra);
5218 if (result != VK_SUCCESS) {
5219 radv_pipeline_destroy(device, pipeline, pAllocator);
5220 return result;
5221 }
5222
5223 *pPipeline = radv_pipeline_to_handle(pipeline);
5224
5225 return VK_SUCCESS;
5226 }
5227
5228 VkResult radv_CreateGraphicsPipelines(
5229 VkDevice _device,
5230 VkPipelineCache pipelineCache,
5231 uint32_t count,
5232 const VkGraphicsPipelineCreateInfo* pCreateInfos,
5233 const VkAllocationCallbacks* pAllocator,
5234 VkPipeline* pPipelines)
5235 {
5236 VkResult result = VK_SUCCESS;
5237 unsigned i = 0;
5238
5239 for (; i < count; i++) {
5240 VkResult r;
5241 r = radv_graphics_pipeline_create(_device,
5242 pipelineCache,
5243 &pCreateInfos[i],
5244 NULL, pAllocator, &pPipelines[i]);
5245 if (r != VK_SUCCESS) {
5246 result = r;
5247 pPipelines[i] = VK_NULL_HANDLE;
5248
5249 if (pCreateInfos[i].flags & VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT)
5250 break;
5251 }
5252 }
5253
5254 for (; i < count; ++i)
5255 pPipelines[i] = VK_NULL_HANDLE;
5256
5257 return result;
5258 }
5259
5260
5261 static void
5262 radv_compute_generate_pm4(struct radv_pipeline *pipeline)
5263 {
5264 struct radv_shader_variant *compute_shader;
5265 struct radv_device *device = pipeline->device;
5266 unsigned threads_per_threadgroup;
5267 unsigned threadgroups_per_cu = 1;
5268 unsigned waves_per_threadgroup;
5269 unsigned max_waves_per_sh = 0;
5270 uint64_t va;
5271
5272 pipeline->cs.max_dw = device->physical_device->rad_info.chip_class >= GFX10 ? 22 : 20;
5273 pipeline->cs.buf = malloc(pipeline->cs.max_dw * 4);
5274
5275 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
5276 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
5277
5278 radeon_set_sh_reg_seq(&pipeline->cs, R_00B830_COMPUTE_PGM_LO, 2);
5279 radeon_emit(&pipeline->cs, va >> 8);
5280 radeon_emit(&pipeline->cs, S_00B834_DATA(va >> 40));
5281
5282 radeon_set_sh_reg_seq(&pipeline->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
5283 radeon_emit(&pipeline->cs, compute_shader->config.rsrc1);
5284 radeon_emit(&pipeline->cs, compute_shader->config.rsrc2);
5285 if (device->physical_device->rad_info.chip_class >= GFX10) {
5286 radeon_set_sh_reg(&pipeline->cs, R_00B8A0_COMPUTE_PGM_RSRC3, compute_shader->config.rsrc3);
5287 }
5288
5289 /* Calculate best compute resource limits. */
5290 threads_per_threadgroup = compute_shader->info.cs.block_size[0] *
5291 compute_shader->info.cs.block_size[1] *
5292 compute_shader->info.cs.block_size[2];
5293 waves_per_threadgroup = DIV_ROUND_UP(threads_per_threadgroup,
5294 compute_shader->info.wave_size);
5295
5296 if (device->physical_device->rad_info.chip_class >= GFX10 &&
5297 waves_per_threadgroup == 1)
5298 threadgroups_per_cu = 2;
5299
5300 radeon_set_sh_reg(&pipeline->cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
5301 ac_get_compute_resource_limits(&device->physical_device->rad_info,
5302 waves_per_threadgroup,
5303 max_waves_per_sh,
5304 threadgroups_per_cu));
5305
5306 radeon_set_sh_reg_seq(&pipeline->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
5307 radeon_emit(&pipeline->cs,
5308 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
5309 radeon_emit(&pipeline->cs,
5310 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
5311 radeon_emit(&pipeline->cs,
5312 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
5313
5314 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
5315 }
5316
5317 static struct radv_pipeline_key
5318 radv_generate_compute_pipeline_key(struct radv_pipeline *pipeline,
5319 const VkComputePipelineCreateInfo *pCreateInfo)
5320 {
5321 const VkPipelineShaderStageCreateInfo *stage = &pCreateInfo->stage;
5322 struct radv_pipeline_key key;
5323 memset(&key, 0, sizeof(key));
5324
5325 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
5326 key.optimisations_disabled = 1;
5327
5328 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT *subgroup_size =
5329 vk_find_struct_const(stage->pNext,
5330 PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT);
5331
5332 if (subgroup_size) {
5333 assert(subgroup_size->requiredSubgroupSize == 32 ||
5334 subgroup_size->requiredSubgroupSize == 64);
5335 key.compute_subgroup_size = subgroup_size->requiredSubgroupSize;
5336 }
5337
5338 return key;
5339 }
5340
5341 static VkResult radv_compute_pipeline_create(
5342 VkDevice _device,
5343 VkPipelineCache _cache,
5344 const VkComputePipelineCreateInfo* pCreateInfo,
5345 const VkAllocationCallbacks* pAllocator,
5346 VkPipeline* pPipeline)
5347 {
5348 RADV_FROM_HANDLE(radv_device, device, _device);
5349 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
5350 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
5351 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
5352 struct radv_pipeline *pipeline;
5353 VkResult result;
5354
5355 pipeline = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*pipeline), 8,
5356 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5357 if (pipeline == NULL)
5358 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5359
5360 vk_object_base_init(&device->vk, &pipeline->base,
5361 VK_OBJECT_TYPE_PIPELINE);
5362
5363 pipeline->device = device;
5364 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
5365 assert(pipeline->layout);
5366
5367 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
5368 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
5369 radv_init_feedback(creation_feedback);
5370
5371 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
5372 if (creation_feedback)
5373 stage_feedbacks[MESA_SHADER_COMPUTE] = &creation_feedback->pPipelineStageCreationFeedbacks[0];
5374
5375 pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
5376
5377 struct radv_pipeline_key key =
5378 radv_generate_compute_pipeline_key(pipeline, pCreateInfo);
5379
5380 if (radv_device_use_secure_compile(device->instance)) {
5381 result = radv_secure_compile(pipeline, device, &key, pStages, pCreateInfo->flags, 1);
5382 *pPipeline = radv_pipeline_to_handle(pipeline);
5383
5384 return result;
5385 } else {
5386 result = radv_create_shaders(pipeline, device, cache, &key, pStages,
5387 pCreateInfo->flags, pipeline_feedback,
5388 stage_feedbacks);
5389 if (result != VK_SUCCESS) {
5390 radv_pipeline_destroy(device, pipeline, pAllocator);
5391 return result;
5392 }
5393 }
5394
5395 pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
5396 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
5397 result = radv_pipeline_scratch_init(device, pipeline);
5398 if (result != VK_SUCCESS) {
5399 radv_pipeline_destroy(device, pipeline, pAllocator);
5400 return result;
5401 }
5402
5403 radv_compute_generate_pm4(pipeline);
5404
5405 *pPipeline = radv_pipeline_to_handle(pipeline);
5406
5407 return VK_SUCCESS;
5408 }
5409
5410 VkResult radv_CreateComputePipelines(
5411 VkDevice _device,
5412 VkPipelineCache pipelineCache,
5413 uint32_t count,
5414 const VkComputePipelineCreateInfo* pCreateInfos,
5415 const VkAllocationCallbacks* pAllocator,
5416 VkPipeline* pPipelines)
5417 {
5418 VkResult result = VK_SUCCESS;
5419
5420 unsigned i = 0;
5421 for (; i < count; i++) {
5422 VkResult r;
5423 r = radv_compute_pipeline_create(_device, pipelineCache,
5424 &pCreateInfos[i],
5425 pAllocator, &pPipelines[i]);
5426 if (r != VK_SUCCESS) {
5427 result = r;
5428 pPipelines[i] = VK_NULL_HANDLE;
5429
5430 if (pCreateInfos[i].flags & VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT)
5431 break;
5432 }
5433 }
5434
5435 for (; i < count; ++i)
5436 pPipelines[i] = VK_NULL_HANDLE;
5437
5438 return result;
5439 }
5440
5441
5442 static uint32_t radv_get_executable_count(const struct radv_pipeline *pipeline)
5443 {
5444 uint32_t ret = 0;
5445 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
5446 if (!pipeline->shaders[i])
5447 continue;
5448
5449 if (i == MESA_SHADER_GEOMETRY &&
5450 !radv_pipeline_has_ngg(pipeline)) {
5451 ret += 2u;
5452 } else {
5453 ret += 1u;
5454 }
5455
5456 }
5457 return ret;
5458 }
5459
5460 static struct radv_shader_variant *
5461 radv_get_shader_from_executable_index(const struct radv_pipeline *pipeline, int index, gl_shader_stage *stage)
5462 {
5463 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
5464 if (!pipeline->shaders[i])
5465 continue;
5466 if (!index) {
5467 *stage = i;
5468 return pipeline->shaders[i];
5469 }
5470
5471 --index;
5472
5473 if (i == MESA_SHADER_GEOMETRY &&
5474 !radv_pipeline_has_ngg(pipeline)) {
5475 if (!index) {
5476 *stage = i;
5477 return pipeline->gs_copy_shader;
5478 }
5479 --index;
5480 }
5481 }
5482
5483 *stage = -1;
5484 return NULL;
5485 }
5486
5487 /* Basically strlcpy (which does not exist on linux) specialized for
5488 * descriptions. */
5489 static void desc_copy(char *desc, const char *src) {
5490 int len = strlen(src);
5491 assert(len < VK_MAX_DESCRIPTION_SIZE);
5492 memcpy(desc, src, len);
5493 memset(desc + len, 0, VK_MAX_DESCRIPTION_SIZE - len);
5494 }
5495
5496 VkResult radv_GetPipelineExecutablePropertiesKHR(
5497 VkDevice _device,
5498 const VkPipelineInfoKHR* pPipelineInfo,
5499 uint32_t* pExecutableCount,
5500 VkPipelineExecutablePropertiesKHR* pProperties)
5501 {
5502 RADV_FROM_HANDLE(radv_pipeline, pipeline, pPipelineInfo->pipeline);
5503 const uint32_t total_count = radv_get_executable_count(pipeline);
5504
5505 if (!pProperties) {
5506 *pExecutableCount = total_count;
5507 return VK_SUCCESS;
5508 }
5509
5510 const uint32_t count = MIN2(total_count, *pExecutableCount);
5511 for (unsigned i = 0, executable_idx = 0;
5512 i < MESA_SHADER_STAGES && executable_idx < count; ++i) {
5513 if (!pipeline->shaders[i])
5514 continue;
5515 pProperties[executable_idx].stages = mesa_to_vk_shader_stage(i);
5516 const char *name = NULL;
5517 const char *description = NULL;
5518 switch(i) {
5519 case MESA_SHADER_VERTEX:
5520 name = "Vertex Shader";
5521 description = "Vulkan Vertex Shader";
5522 break;
5523 case MESA_SHADER_TESS_CTRL:
5524 if (!pipeline->shaders[MESA_SHADER_VERTEX]) {
5525 pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT;
5526 name = "Vertex + Tessellation Control Shaders";
5527 description = "Combined Vulkan Vertex and Tessellation Control Shaders";
5528 } else {
5529 name = "Tessellation Control Shader";
5530 description = "Vulkan Tessellation Control Shader";
5531 }
5532 break;
5533 case MESA_SHADER_TESS_EVAL:
5534 name = "Tessellation Evaluation Shader";
5535 description = "Vulkan Tessellation Evaluation Shader";
5536 break;
5537 case MESA_SHADER_GEOMETRY:
5538 if (radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_TESS_EVAL]) {
5539 pProperties[executable_idx].stages |= VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT;
5540 name = "Tessellation Evaluation + Geometry Shaders";
5541 description = "Combined Vulkan Tessellation Evaluation and Geometry Shaders";
5542 } else if (!radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_VERTEX]) {
5543 pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT;
5544 name = "Vertex + Geometry Shader";
5545 description = "Combined Vulkan Vertex and Geometry Shaders";
5546 } else {
5547 name = "Geometry Shader";
5548 description = "Vulkan Geometry Shader";
5549 }
5550 break;
5551 case MESA_SHADER_FRAGMENT:
5552 name = "Fragment Shader";
5553 description = "Vulkan Fragment Shader";
5554 break;
5555 case MESA_SHADER_COMPUTE:
5556 name = "Compute Shader";
5557 description = "Vulkan Compute Shader";
5558 break;
5559 }
5560
5561 pProperties[executable_idx].subgroupSize = pipeline->shaders[i]->info.wave_size;
5562 desc_copy(pProperties[executable_idx].name, name);
5563 desc_copy(pProperties[executable_idx].description, description);
5564
5565 ++executable_idx;
5566 if (i == MESA_SHADER_GEOMETRY &&
5567 !radv_pipeline_has_ngg(pipeline)) {
5568 assert(pipeline->gs_copy_shader);
5569 if (executable_idx >= count)
5570 break;
5571
5572 pProperties[executable_idx].stages = VK_SHADER_STAGE_GEOMETRY_BIT;
5573 pProperties[executable_idx].subgroupSize = 64;
5574 desc_copy(pProperties[executable_idx].name, "GS Copy Shader");
5575 desc_copy(pProperties[executable_idx].description,
5576 "Extra shader stage that loads the GS output ringbuffer into the rasterizer");
5577
5578 ++executable_idx;
5579 }
5580 }
5581
5582 VkResult result = *pExecutableCount < total_count ? VK_INCOMPLETE : VK_SUCCESS;
5583 *pExecutableCount = count;
5584 return result;
5585 }
5586
5587 VkResult radv_GetPipelineExecutableStatisticsKHR(
5588 VkDevice _device,
5589 const VkPipelineExecutableInfoKHR* pExecutableInfo,
5590 uint32_t* pStatisticCount,
5591 VkPipelineExecutableStatisticKHR* pStatistics)
5592 {
5593 RADV_FROM_HANDLE(radv_device, device, _device);
5594 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
5595 gl_shader_stage stage;
5596 struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
5597
5598 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
5599 unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
5600 unsigned max_waves = radv_get_max_waves(device, shader, stage);
5601
5602 VkPipelineExecutableStatisticKHR *s = pStatistics;
5603 VkPipelineExecutableStatisticKHR *end = s + (pStatistics ? *pStatisticCount : 0);
5604 VkResult result = VK_SUCCESS;
5605
5606 if (s < end) {
5607 desc_copy(s->name, "SGPRs");
5608 desc_copy(s->description, "Number of SGPR registers allocated per subgroup");
5609 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5610 s->value.u64 = shader->config.num_sgprs;
5611 }
5612 ++s;
5613
5614 if (s < end) {
5615 desc_copy(s->name, "VGPRs");
5616 desc_copy(s->description, "Number of VGPR registers allocated per subgroup");
5617 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5618 s->value.u64 = shader->config.num_vgprs;
5619 }
5620 ++s;
5621
5622 if (s < end) {
5623 desc_copy(s->name, "Spilled SGPRs");
5624 desc_copy(s->description, "Number of SGPR registers spilled per subgroup");
5625 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5626 s->value.u64 = shader->config.spilled_sgprs;
5627 }
5628 ++s;
5629
5630 if (s < end) {
5631 desc_copy(s->name, "Spilled VGPRs");
5632 desc_copy(s->description, "Number of VGPR registers spilled per subgroup");
5633 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5634 s->value.u64 = shader->config.spilled_vgprs;
5635 }
5636 ++s;
5637
5638 if (s < end) {
5639 desc_copy(s->name, "PrivMem VGPRs");
5640 desc_copy(s->description, "Number of VGPRs stored in private memory per subgroup");
5641 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5642 s->value.u64 = shader->info.private_mem_vgprs;
5643 }
5644 ++s;
5645
5646 if (s < end) {
5647 desc_copy(s->name, "Code size");
5648 desc_copy(s->description, "Code size in bytes");
5649 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5650 s->value.u64 = shader->exec_size;
5651 }
5652 ++s;
5653
5654 if (s < end) {
5655 desc_copy(s->name, "LDS size");
5656 desc_copy(s->description, "LDS size in bytes per workgroup");
5657 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5658 s->value.u64 = shader->config.lds_size * lds_increment;
5659 }
5660 ++s;
5661
5662 if (s < end) {
5663 desc_copy(s->name, "Scratch size");
5664 desc_copy(s->description, "Private memory in bytes per subgroup");
5665 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5666 s->value.u64 = shader->config.scratch_bytes_per_wave;
5667 }
5668 ++s;
5669
5670 if (s < end) {
5671 desc_copy(s->name, "Subgroups per SIMD");
5672 desc_copy(s->description, "The maximum number of subgroups in flight on a SIMD unit");
5673 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5674 s->value.u64 = max_waves;
5675 }
5676 ++s;
5677
5678 if (shader->statistics) {
5679 for (unsigned i = 0; i < shader->statistics->count; i++) {
5680 struct radv_compiler_statistic_info *info = &shader->statistics->infos[i];
5681 uint32_t value = shader->statistics->values[i];
5682 if (s < end) {
5683 desc_copy(s->name, info->name);
5684 desc_copy(s->description, info->desc);
5685 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5686 s->value.u64 = value;
5687 }
5688 ++s;
5689 }
5690 }
5691
5692 if (!pStatistics)
5693 *pStatisticCount = s - pStatistics;
5694 else if (s > end) {
5695 *pStatisticCount = end - pStatistics;
5696 result = VK_INCOMPLETE;
5697 } else {
5698 *pStatisticCount = s - pStatistics;
5699 }
5700
5701 return result;
5702 }
5703
5704 static VkResult radv_copy_representation(void *data, size_t *data_size, const char *src)
5705 {
5706 size_t total_size = strlen(src) + 1;
5707
5708 if (!data) {
5709 *data_size = total_size;
5710 return VK_SUCCESS;
5711 }
5712
5713 size_t size = MIN2(total_size, *data_size);
5714
5715 memcpy(data, src, size);
5716 if (size)
5717 *((char*)data + size - 1) = 0;
5718 return size < total_size ? VK_INCOMPLETE : VK_SUCCESS;
5719 }
5720
5721 VkResult radv_GetPipelineExecutableInternalRepresentationsKHR(
5722 VkDevice device,
5723 const VkPipelineExecutableInfoKHR* pExecutableInfo,
5724 uint32_t* pInternalRepresentationCount,
5725 VkPipelineExecutableInternalRepresentationKHR* pInternalRepresentations)
5726 {
5727 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
5728 gl_shader_stage stage;
5729 struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
5730
5731 VkPipelineExecutableInternalRepresentationKHR *p = pInternalRepresentations;
5732 VkPipelineExecutableInternalRepresentationKHR *end = p + (pInternalRepresentations ? *pInternalRepresentationCount : 0);
5733 VkResult result = VK_SUCCESS;
5734 /* optimized NIR */
5735 if (p < end) {
5736 p->isText = true;
5737 desc_copy(p->name, "NIR Shader(s)");
5738 desc_copy(p->description, "The optimized NIR shader(s)");
5739 if (radv_copy_representation(p->pData, &p->dataSize, shader->nir_string) != VK_SUCCESS)
5740 result = VK_INCOMPLETE;
5741 }
5742 ++p;
5743
5744 /* backend IR */
5745 if (p < end) {
5746 p->isText = true;
5747 if (pipeline->device->physical_device->use_llvm) {
5748 desc_copy(p->name, "LLVM IR");
5749 desc_copy(p->description, "The LLVM IR after some optimizations");
5750 } else {
5751 desc_copy(p->name, "ACO IR");
5752 desc_copy(p->description, "The ACO IR after some optimizations");
5753 }
5754 if (radv_copy_representation(p->pData, &p->dataSize, shader->ir_string) != VK_SUCCESS)
5755 result = VK_INCOMPLETE;
5756 }
5757 ++p;
5758
5759 /* Disassembler */
5760 if (p < end) {
5761 p->isText = true;
5762 desc_copy(p->name, "Assembly");
5763 desc_copy(p->description, "Final Assembly");
5764 if (radv_copy_representation(p->pData, &p->dataSize, shader->disasm_string) != VK_SUCCESS)
5765 result = VK_INCOMPLETE;
5766 }
5767 ++p;
5768
5769 if (!pInternalRepresentations)
5770 *pInternalRepresentationCount = p - pInternalRepresentations;
5771 else if(p > end) {
5772 result = VK_INCOMPLETE;
5773 *pInternalRepresentationCount = end - pInternalRepresentations;
5774 } else {
5775 *pInternalRepresentationCount = p - pInternalRepresentations;
5776 }
5777
5778 return result;
5779 }