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radv: ignore pMultisampleState if rasterization is disabled
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/disk_cache.h"
29 #include "util/mesa-sha1.h"
30 #include "util/u_atomic.h"
31 #include "radv_debug.h"
32 #include "radv_private.h"
33 #include "radv_cs.h"
34 #include "radv_shader.h"
35 #include "nir/nir.h"
36 #include "nir/nir_builder.h"
37 #include "nir/nir_xfb_info.h"
38 #include "spirv/nir_spirv.h"
39 #include "vk_util.h"
40
41 #include <llvm-c/Core.h>
42 #include <llvm-c/TargetMachine.h>
43
44 #include "sid.h"
45 #include "ac_binary.h"
46 #include "ac_llvm_util.h"
47 #include "ac_nir_to_llvm.h"
48 #include "vk_format.h"
49 #include "util/debug.h"
50 #include "ac_exp_param.h"
51 #include "ac_shader_util.h"
52 #include "main/menums.h"
53
54 struct radv_blend_state {
55 uint32_t blend_enable_4bit;
56 uint32_t need_src_alpha;
57
58 uint32_t cb_color_control;
59 uint32_t cb_target_mask;
60 uint32_t cb_target_enabled_4bit;
61 uint32_t sx_mrt_blend_opt[8];
62 uint32_t cb_blend_control[8];
63
64 uint32_t spi_shader_col_format;
65 uint32_t cb_shader_mask;
66 uint32_t db_alpha_to_mask;
67
68 uint32_t commutative_4bit;
69
70 bool single_cb_enable;
71 bool mrt0_is_dual_src;
72 };
73
74 struct radv_dsa_order_invariance {
75 /* Whether the final result in Z/S buffers is guaranteed to be
76 * invariant under changes to the order in which fragments arrive.
77 */
78 bool zs;
79
80 /* Whether the set of fragments that pass the combined Z/S test is
81 * guaranteed to be invariant under changes to the order in which
82 * fragments arrive.
83 */
84 bool pass_set;
85 };
86
87 struct radv_tessellation_state {
88 uint32_t ls_hs_config;
89 unsigned num_patches;
90 unsigned lds_size;
91 uint32_t tf_param;
92 };
93
94 static const VkPipelineMultisampleStateCreateInfo *
95 radv_pipeline_get_multisample_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
96 {
97 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
98 return pCreateInfo->pMultisampleState;
99 return NULL;
100 }
101
102 bool radv_pipeline_has_ngg(const struct radv_pipeline *pipeline)
103 {
104 struct radv_shader_variant *variant = NULL;
105 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
106 variant = pipeline->shaders[MESA_SHADER_GEOMETRY];
107 else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
108 variant = pipeline->shaders[MESA_SHADER_TESS_EVAL];
109 else if (pipeline->shaders[MESA_SHADER_VERTEX])
110 variant = pipeline->shaders[MESA_SHADER_VERTEX];
111 else
112 return false;
113 return variant->info.is_ngg;
114 }
115
116 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline *pipeline)
117 {
118 if (!radv_pipeline_has_gs(pipeline))
119 return false;
120
121 /* The GS copy shader is required if the pipeline has GS on GFX6-GFX9.
122 * On GFX10, it might be required in rare cases if it's not possible to
123 * enable NGG.
124 */
125 if (radv_pipeline_has_ngg(pipeline))
126 return false;
127
128 assert(pipeline->gs_copy_shader);
129 return true;
130 }
131
132 static void
133 radv_pipeline_destroy(struct radv_device *device,
134 struct radv_pipeline *pipeline,
135 const VkAllocationCallbacks* allocator)
136 {
137 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
138 if (pipeline->shaders[i])
139 radv_shader_variant_destroy(device, pipeline->shaders[i]);
140
141 if (pipeline->gs_copy_shader)
142 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
143
144 if(pipeline->cs.buf)
145 free(pipeline->cs.buf);
146 vk_free2(&device->alloc, allocator, pipeline);
147 }
148
149 void radv_DestroyPipeline(
150 VkDevice _device,
151 VkPipeline _pipeline,
152 const VkAllocationCallbacks* pAllocator)
153 {
154 RADV_FROM_HANDLE(radv_device, device, _device);
155 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
156
157 if (!_pipeline)
158 return;
159
160 radv_pipeline_destroy(device, pipeline, pAllocator);
161 }
162
163 static uint32_t get_hash_flags(struct radv_device *device)
164 {
165 uint32_t hash_flags = 0;
166
167 if (device->instance->debug_flags & RADV_DEBUG_NO_NGG)
168 hash_flags |= RADV_HASH_SHADER_NO_NGG;
169 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
170 hash_flags |= RADV_HASH_SHADER_SISCHED;
171 if (device->physical_device->cs_wave_size == 32)
172 hash_flags |= RADV_HASH_SHADER_CS_WAVE32;
173 if (device->physical_device->ps_wave_size == 32)
174 hash_flags |= RADV_HASH_SHADER_PS_WAVE32;
175 if (device->physical_device->ge_wave_size == 32)
176 hash_flags |= RADV_HASH_SHADER_GE_WAVE32;
177 if (device->physical_device->use_aco)
178 hash_flags |= RADV_HASH_SHADER_ACO;
179 return hash_flags;
180 }
181
182 static VkResult
183 radv_pipeline_scratch_init(struct radv_device *device,
184 struct radv_pipeline *pipeline)
185 {
186 unsigned scratch_bytes_per_wave = 0;
187 unsigned max_waves = 0;
188 unsigned min_waves = 1;
189
190 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
191 if (pipeline->shaders[i] &&
192 pipeline->shaders[i]->config.scratch_bytes_per_wave) {
193 unsigned max_stage_waves = device->scratch_waves;
194
195 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
196 pipeline->shaders[i]->config.scratch_bytes_per_wave);
197
198 max_stage_waves = MIN2(max_stage_waves,
199 4 * device->physical_device->rad_info.num_good_compute_units *
200 (256 / pipeline->shaders[i]->config.num_vgprs));
201 max_waves = MAX2(max_waves, max_stage_waves);
202 }
203 }
204
205 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
206 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
207 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
208 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
209 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
210 }
211
212 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
213 pipeline->max_waves = max_waves;
214 return VK_SUCCESS;
215 }
216
217 static uint32_t si_translate_blend_logic_op(VkLogicOp op)
218 {
219 switch (op) {
220 case VK_LOGIC_OP_CLEAR:
221 return V_028808_ROP3_CLEAR;
222 case VK_LOGIC_OP_AND:
223 return V_028808_ROP3_AND;
224 case VK_LOGIC_OP_AND_REVERSE:
225 return V_028808_ROP3_AND_REVERSE;
226 case VK_LOGIC_OP_COPY:
227 return V_028808_ROP3_COPY;
228 case VK_LOGIC_OP_AND_INVERTED:
229 return V_028808_ROP3_AND_INVERTED;
230 case VK_LOGIC_OP_NO_OP:
231 return V_028808_ROP3_NO_OP;
232 case VK_LOGIC_OP_XOR:
233 return V_028808_ROP3_XOR;
234 case VK_LOGIC_OP_OR:
235 return V_028808_ROP3_OR;
236 case VK_LOGIC_OP_NOR:
237 return V_028808_ROP3_NOR;
238 case VK_LOGIC_OP_EQUIVALENT:
239 return V_028808_ROP3_EQUIVALENT;
240 case VK_LOGIC_OP_INVERT:
241 return V_028808_ROP3_INVERT;
242 case VK_LOGIC_OP_OR_REVERSE:
243 return V_028808_ROP3_OR_REVERSE;
244 case VK_LOGIC_OP_COPY_INVERTED:
245 return V_028808_ROP3_COPY_INVERTED;
246 case VK_LOGIC_OP_OR_INVERTED:
247 return V_028808_ROP3_OR_INVERTED;
248 case VK_LOGIC_OP_NAND:
249 return V_028808_ROP3_NAND;
250 case VK_LOGIC_OP_SET:
251 return V_028808_ROP3_SET;
252 default:
253 unreachable("Unhandled logic op");
254 }
255 }
256
257
258 static uint32_t si_translate_blend_function(VkBlendOp op)
259 {
260 switch (op) {
261 case VK_BLEND_OP_ADD:
262 return V_028780_COMB_DST_PLUS_SRC;
263 case VK_BLEND_OP_SUBTRACT:
264 return V_028780_COMB_SRC_MINUS_DST;
265 case VK_BLEND_OP_REVERSE_SUBTRACT:
266 return V_028780_COMB_DST_MINUS_SRC;
267 case VK_BLEND_OP_MIN:
268 return V_028780_COMB_MIN_DST_SRC;
269 case VK_BLEND_OP_MAX:
270 return V_028780_COMB_MAX_DST_SRC;
271 default:
272 return 0;
273 }
274 }
275
276 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
277 {
278 switch (factor) {
279 case VK_BLEND_FACTOR_ZERO:
280 return V_028780_BLEND_ZERO;
281 case VK_BLEND_FACTOR_ONE:
282 return V_028780_BLEND_ONE;
283 case VK_BLEND_FACTOR_SRC_COLOR:
284 return V_028780_BLEND_SRC_COLOR;
285 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
286 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
287 case VK_BLEND_FACTOR_DST_COLOR:
288 return V_028780_BLEND_DST_COLOR;
289 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
290 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
291 case VK_BLEND_FACTOR_SRC_ALPHA:
292 return V_028780_BLEND_SRC_ALPHA;
293 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
294 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
295 case VK_BLEND_FACTOR_DST_ALPHA:
296 return V_028780_BLEND_DST_ALPHA;
297 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
298 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
299 case VK_BLEND_FACTOR_CONSTANT_COLOR:
300 return V_028780_BLEND_CONSTANT_COLOR;
301 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
302 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
303 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
304 return V_028780_BLEND_CONSTANT_ALPHA;
305 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
306 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
307 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
308 return V_028780_BLEND_SRC_ALPHA_SATURATE;
309 case VK_BLEND_FACTOR_SRC1_COLOR:
310 return V_028780_BLEND_SRC1_COLOR;
311 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
312 return V_028780_BLEND_INV_SRC1_COLOR;
313 case VK_BLEND_FACTOR_SRC1_ALPHA:
314 return V_028780_BLEND_SRC1_ALPHA;
315 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
316 return V_028780_BLEND_INV_SRC1_ALPHA;
317 default:
318 return 0;
319 }
320 }
321
322 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
323 {
324 switch (op) {
325 case VK_BLEND_OP_ADD:
326 return V_028760_OPT_COMB_ADD;
327 case VK_BLEND_OP_SUBTRACT:
328 return V_028760_OPT_COMB_SUBTRACT;
329 case VK_BLEND_OP_REVERSE_SUBTRACT:
330 return V_028760_OPT_COMB_REVSUBTRACT;
331 case VK_BLEND_OP_MIN:
332 return V_028760_OPT_COMB_MIN;
333 case VK_BLEND_OP_MAX:
334 return V_028760_OPT_COMB_MAX;
335 default:
336 return V_028760_OPT_COMB_BLEND_DISABLED;
337 }
338 }
339
340 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
341 {
342 switch (factor) {
343 case VK_BLEND_FACTOR_ZERO:
344 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
345 case VK_BLEND_FACTOR_ONE:
346 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
347 case VK_BLEND_FACTOR_SRC_COLOR:
348 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
349 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
350 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
351 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
352 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
353 case VK_BLEND_FACTOR_SRC_ALPHA:
354 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
355 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
356 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
357 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
358 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
359 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
360 default:
361 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
362 }
363 }
364
365 /**
366 * Get rid of DST in the blend factors by commuting the operands:
367 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
368 */
369 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
370 unsigned *dst_factor, unsigned expected_dst,
371 unsigned replacement_src)
372 {
373 if (*src_factor == expected_dst &&
374 *dst_factor == VK_BLEND_FACTOR_ZERO) {
375 *src_factor = VK_BLEND_FACTOR_ZERO;
376 *dst_factor = replacement_src;
377
378 /* Commuting the operands requires reversing subtractions. */
379 if (*func == VK_BLEND_OP_SUBTRACT)
380 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
381 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
382 *func = VK_BLEND_OP_SUBTRACT;
383 }
384 }
385
386 static bool si_blend_factor_uses_dst(unsigned factor)
387 {
388 return factor == VK_BLEND_FACTOR_DST_COLOR ||
389 factor == VK_BLEND_FACTOR_DST_ALPHA ||
390 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
391 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
392 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
393 }
394
395 static bool is_dual_src(VkBlendFactor factor)
396 {
397 switch (factor) {
398 case VK_BLEND_FACTOR_SRC1_COLOR:
399 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
400 case VK_BLEND_FACTOR_SRC1_ALPHA:
401 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
402 return true;
403 default:
404 return false;
405 }
406 }
407
408 static unsigned si_choose_spi_color_format(VkFormat vk_format,
409 bool blend_enable,
410 bool blend_need_alpha)
411 {
412 const struct vk_format_description *desc = vk_format_description(vk_format);
413 unsigned format, ntype, swap;
414
415 /* Alpha is needed for alpha-to-coverage.
416 * Blending may be with or without alpha.
417 */
418 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
419 unsigned alpha = 0; /* exports alpha, but may not support blending */
420 unsigned blend = 0; /* supports blending, but may not export alpha */
421 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
422
423 format = radv_translate_colorformat(vk_format);
424 ntype = radv_translate_color_numformat(vk_format, desc,
425 vk_format_get_first_non_void_channel(vk_format));
426 swap = radv_translate_colorswap(vk_format, false);
427
428 /* Choose the SPI color formats. These are required values for Stoney/RB+.
429 * Other chips have multiple choices, though they are not necessarily better.
430 */
431 switch (format) {
432 case V_028C70_COLOR_5_6_5:
433 case V_028C70_COLOR_1_5_5_5:
434 case V_028C70_COLOR_5_5_5_1:
435 case V_028C70_COLOR_4_4_4_4:
436 case V_028C70_COLOR_10_11_11:
437 case V_028C70_COLOR_11_11_10:
438 case V_028C70_COLOR_8:
439 case V_028C70_COLOR_8_8:
440 case V_028C70_COLOR_8_8_8_8:
441 case V_028C70_COLOR_10_10_10_2:
442 case V_028C70_COLOR_2_10_10_10:
443 if (ntype == V_028C70_NUMBER_UINT)
444 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
445 else if (ntype == V_028C70_NUMBER_SINT)
446 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
447 else
448 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
449 break;
450
451 case V_028C70_COLOR_16:
452 case V_028C70_COLOR_16_16:
453 case V_028C70_COLOR_16_16_16_16:
454 if (ntype == V_028C70_NUMBER_UNORM ||
455 ntype == V_028C70_NUMBER_SNORM) {
456 /* UNORM16 and SNORM16 don't support blending */
457 if (ntype == V_028C70_NUMBER_UNORM)
458 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
459 else
460 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
461
462 /* Use 32 bits per channel for blending. */
463 if (format == V_028C70_COLOR_16) {
464 if (swap == V_028C70_SWAP_STD) { /* R */
465 blend = V_028714_SPI_SHADER_32_R;
466 blend_alpha = V_028714_SPI_SHADER_32_AR;
467 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
468 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
469 else
470 assert(0);
471 } else if (format == V_028C70_COLOR_16_16) {
472 if (swap == V_028C70_SWAP_STD) { /* RG */
473 blend = V_028714_SPI_SHADER_32_GR;
474 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
475 } else if (swap == V_028C70_SWAP_ALT) /* RA */
476 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
477 else
478 assert(0);
479 } else /* 16_16_16_16 */
480 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
481 } else if (ntype == V_028C70_NUMBER_UINT)
482 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
483 else if (ntype == V_028C70_NUMBER_SINT)
484 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
485 else if (ntype == V_028C70_NUMBER_FLOAT)
486 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
487 else
488 assert(0);
489 break;
490
491 case V_028C70_COLOR_32:
492 if (swap == V_028C70_SWAP_STD) { /* R */
493 blend = normal = V_028714_SPI_SHADER_32_R;
494 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
495 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
496 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
497 else
498 assert(0);
499 break;
500
501 case V_028C70_COLOR_32_32:
502 if (swap == V_028C70_SWAP_STD) { /* RG */
503 blend = normal = V_028714_SPI_SHADER_32_GR;
504 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
505 } else if (swap == V_028C70_SWAP_ALT) /* RA */
506 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
507 else
508 assert(0);
509 break;
510
511 case V_028C70_COLOR_32_32_32_32:
512 case V_028C70_COLOR_8_24:
513 case V_028C70_COLOR_24_8:
514 case V_028C70_COLOR_X24_8_32_FLOAT:
515 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
516 break;
517
518 default:
519 unreachable("unhandled blend format");
520 }
521
522 if (blend_enable && blend_need_alpha)
523 return blend_alpha;
524 else if(blend_need_alpha)
525 return alpha;
526 else if(blend_enable)
527 return blend;
528 else
529 return normal;
530 }
531
532 static void
533 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
534 const VkGraphicsPipelineCreateInfo *pCreateInfo,
535 struct radv_blend_state *blend)
536 {
537 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
538 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
539 unsigned col_format = 0;
540 unsigned num_targets;
541
542 for (unsigned i = 0; i < (blend->single_cb_enable ? 1 : subpass->color_count); ++i) {
543 unsigned cf;
544
545 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
546 cf = V_028714_SPI_SHADER_ZERO;
547 } else {
548 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
549 bool blend_enable =
550 blend->blend_enable_4bit & (0xfu << (i * 4));
551
552 cf = si_choose_spi_color_format(attachment->format,
553 blend_enable,
554 blend->need_src_alpha & (1 << i));
555 }
556
557 col_format |= cf << (4 * i);
558 }
559
560 if (!(col_format & 0xf) && blend->need_src_alpha & (1 << 0)) {
561 /* When a subpass doesn't have any color attachments, write the
562 * alpha channel of MRT0 when alpha coverage is enabled because
563 * the depth attachment needs it.
564 */
565 col_format |= V_028714_SPI_SHADER_32_AR;
566 }
567
568 /* If the i-th target format is set, all previous target formats must
569 * be non-zero to avoid hangs.
570 */
571 num_targets = (util_last_bit(col_format) + 3) / 4;
572 for (unsigned i = 0; i < num_targets; i++) {
573 if (!(col_format & (0xf << (i * 4)))) {
574 col_format |= V_028714_SPI_SHADER_32_R << (i * 4);
575 }
576 }
577
578 /* The output for dual source blending should have the same format as
579 * the first output.
580 */
581 if (blend->mrt0_is_dual_src)
582 col_format |= (col_format & 0xf) << 4;
583
584 blend->cb_shader_mask = ac_get_cb_shader_mask(col_format);
585 blend->spi_shader_col_format = col_format;
586 }
587
588 static bool
589 format_is_int8(VkFormat format)
590 {
591 const struct vk_format_description *desc = vk_format_description(format);
592 int channel = vk_format_get_first_non_void_channel(format);
593
594 return channel >= 0 && desc->channel[channel].pure_integer &&
595 desc->channel[channel].size == 8;
596 }
597
598 static bool
599 format_is_int10(VkFormat format)
600 {
601 const struct vk_format_description *desc = vk_format_description(format);
602
603 if (desc->nr_channels != 4)
604 return false;
605 for (unsigned i = 0; i < 4; i++) {
606 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
607 return true;
608 }
609 return false;
610 }
611
612 /*
613 * Ordered so that for each i,
614 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
615 */
616 const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS] = {
617 VK_FORMAT_R32_SFLOAT,
618 VK_FORMAT_R32G32_SFLOAT,
619 VK_FORMAT_R8G8B8A8_UNORM,
620 VK_FORMAT_R16G16B16A16_UNORM,
621 VK_FORMAT_R16G16B16A16_SNORM,
622 VK_FORMAT_R16G16B16A16_UINT,
623 VK_FORMAT_R16G16B16A16_SINT,
624 VK_FORMAT_R32G32B32A32_SFLOAT,
625 VK_FORMAT_R8G8B8A8_UINT,
626 VK_FORMAT_R8G8B8A8_SINT,
627 VK_FORMAT_A2R10G10B10_UINT_PACK32,
628 VK_FORMAT_A2R10G10B10_SINT_PACK32,
629 };
630
631 unsigned radv_format_meta_fs_key(VkFormat format)
632 {
633 unsigned col_format = si_choose_spi_color_format(format, false, false);
634
635 assert(col_format != V_028714_SPI_SHADER_32_AR);
636 if (col_format >= V_028714_SPI_SHADER_32_AR)
637 --col_format; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
638
639 --col_format; /* Skip V_028714_SPI_SHADER_ZERO */
640 bool is_int8 = format_is_int8(format);
641 bool is_int10 = format_is_int10(format);
642
643 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
644 }
645
646 static void
647 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo *pCreateInfo,
648 unsigned *is_int8, unsigned *is_int10)
649 {
650 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
651 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
652 *is_int8 = 0;
653 *is_int10 = 0;
654
655 for (unsigned i = 0; i < subpass->color_count; ++i) {
656 struct radv_render_pass_attachment *attachment;
657
658 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
659 continue;
660
661 attachment = pass->attachments + subpass->color_attachments[i].attachment;
662
663 if (format_is_int8(attachment->format))
664 *is_int8 |= 1 << i;
665 if (format_is_int10(attachment->format))
666 *is_int10 |= 1 << i;
667 }
668 }
669
670 static void
671 radv_blend_check_commutativity(struct radv_blend_state *blend,
672 VkBlendOp op, VkBlendFactor src,
673 VkBlendFactor dst, unsigned chanmask)
674 {
675 /* Src factor is allowed when it does not depend on Dst. */
676 static const uint32_t src_allowed =
677 (1u << VK_BLEND_FACTOR_ONE) |
678 (1u << VK_BLEND_FACTOR_SRC_COLOR) |
679 (1u << VK_BLEND_FACTOR_SRC_ALPHA) |
680 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE) |
681 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR) |
682 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA) |
683 (1u << VK_BLEND_FACTOR_SRC1_COLOR) |
684 (1u << VK_BLEND_FACTOR_SRC1_ALPHA) |
685 (1u << VK_BLEND_FACTOR_ZERO) |
686 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR) |
687 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA) |
688 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR) |
689 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA) |
690 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR) |
691 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA);
692
693 if (dst == VK_BLEND_FACTOR_ONE &&
694 (src_allowed & (1u << src))) {
695 /* Addition is commutative, but floating point addition isn't
696 * associative: subtle changes can be introduced via different
697 * rounding. Be conservative, only enable for min and max.
698 */
699 if (op == VK_BLEND_OP_MAX || op == VK_BLEND_OP_MIN)
700 blend->commutative_4bit |= chanmask;
701 }
702 }
703
704 static struct radv_blend_state
705 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
706 const VkGraphicsPipelineCreateInfo *pCreateInfo,
707 const struct radv_graphics_pipeline_create_info *extra)
708 {
709 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
710 const VkPipelineMultisampleStateCreateInfo *vkms = radv_pipeline_get_multisample_state(pCreateInfo);
711 struct radv_blend_state blend = {0};
712 unsigned mode = V_028808_CB_NORMAL;
713 int i;
714
715 if (!vkblend)
716 return blend;
717
718 if (extra && extra->custom_blend_mode) {
719 blend.single_cb_enable = true;
720 mode = extra->custom_blend_mode;
721 }
722 blend.cb_color_control = 0;
723 if (vkblend->logicOpEnable)
724 blend.cb_color_control |= S_028808_ROP3(si_translate_blend_logic_op(vkblend->logicOp));
725 else
726 blend.cb_color_control |= S_028808_ROP3(V_028808_ROP3_COPY);
727
728 blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
729 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
730 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
731 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
732 S_028B70_OFFSET_ROUND(1);
733
734 if (vkms && vkms->alphaToCoverageEnable) {
735 blend.db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
736 blend.need_src_alpha |= 0x1;
737 }
738
739 blend.cb_target_mask = 0;
740 for (i = 0; i < vkblend->attachmentCount; i++) {
741 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
742 unsigned blend_cntl = 0;
743 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
744 VkBlendOp eqRGB = att->colorBlendOp;
745 VkBlendFactor srcRGB = att->srcColorBlendFactor;
746 VkBlendFactor dstRGB = att->dstColorBlendFactor;
747 VkBlendOp eqA = att->alphaBlendOp;
748 VkBlendFactor srcA = att->srcAlphaBlendFactor;
749 VkBlendFactor dstA = att->dstAlphaBlendFactor;
750
751 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
752
753 if (!att->colorWriteMask)
754 continue;
755
756 blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
757 blend.cb_target_enabled_4bit |= 0xf << (4 * i);
758 if (!att->blendEnable) {
759 blend.cb_blend_control[i] = blend_cntl;
760 continue;
761 }
762
763 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
764 if (i == 0)
765 blend.mrt0_is_dual_src = true;
766
767 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
768 srcRGB = VK_BLEND_FACTOR_ONE;
769 dstRGB = VK_BLEND_FACTOR_ONE;
770 }
771 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
772 srcA = VK_BLEND_FACTOR_ONE;
773 dstA = VK_BLEND_FACTOR_ONE;
774 }
775
776 radv_blend_check_commutativity(&blend, eqRGB, srcRGB, dstRGB,
777 0x7 << (4 * i));
778 radv_blend_check_commutativity(&blend, eqA, srcA, dstA,
779 0x8 << (4 * i));
780
781 /* Blending optimizations for RB+.
782 * These transformations don't change the behavior.
783 *
784 * First, get rid of DST in the blend factors:
785 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
786 */
787 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
788 VK_BLEND_FACTOR_DST_COLOR,
789 VK_BLEND_FACTOR_SRC_COLOR);
790
791 si_blend_remove_dst(&eqA, &srcA, &dstA,
792 VK_BLEND_FACTOR_DST_COLOR,
793 VK_BLEND_FACTOR_SRC_COLOR);
794
795 si_blend_remove_dst(&eqA, &srcA, &dstA,
796 VK_BLEND_FACTOR_DST_ALPHA,
797 VK_BLEND_FACTOR_SRC_ALPHA);
798
799 /* Look up the ideal settings from tables. */
800 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
801 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
802 srcA_opt = si_translate_blend_opt_factor(srcA, true);
803 dstA_opt = si_translate_blend_opt_factor(dstA, true);
804
805 /* Handle interdependencies. */
806 if (si_blend_factor_uses_dst(srcRGB))
807 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
808 if (si_blend_factor_uses_dst(srcA))
809 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
810
811 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
812 (dstRGB == VK_BLEND_FACTOR_ZERO ||
813 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
814 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
815 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
816
817 /* Set the final value. */
818 blend.sx_mrt_blend_opt[i] =
819 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
820 S_028760_COLOR_DST_OPT(dstRGB_opt) |
821 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
822 S_028760_ALPHA_SRC_OPT(srcA_opt) |
823 S_028760_ALPHA_DST_OPT(dstA_opt) |
824 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
825 blend_cntl |= S_028780_ENABLE(1);
826
827 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
828 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
829 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
830 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
831 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
832 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
833 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
834 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
835 }
836 blend.cb_blend_control[i] = blend_cntl;
837
838 blend.blend_enable_4bit |= 0xfu << (i * 4);
839
840 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
841 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
842 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
843 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
844 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
845 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
846 blend.need_src_alpha |= 1 << i;
847 }
848 for (i = vkblend->attachmentCount; i < 8; i++) {
849 blend.cb_blend_control[i] = 0;
850 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
851 }
852
853 if (pipeline->device->physical_device->rad_info.has_rbplus) {
854 /* Disable RB+ blend optimizations for dual source blending. */
855 if (blend.mrt0_is_dual_src) {
856 for (i = 0; i < 8; i++) {
857 blend.sx_mrt_blend_opt[i] =
858 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
859 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
860 }
861 }
862
863 /* RB+ doesn't work with dual source blending, logic op and
864 * RESOLVE.
865 */
866 if (blend.mrt0_is_dual_src || vkblend->logicOpEnable ||
867 mode == V_028808_CB_RESOLVE)
868 blend.cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
869 }
870
871 if (blend.cb_target_mask)
872 blend.cb_color_control |= S_028808_MODE(mode);
873 else
874 blend.cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
875
876 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo, &blend);
877 return blend;
878 }
879
880 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
881 {
882 switch (op) {
883 case VK_STENCIL_OP_KEEP:
884 return V_02842C_STENCIL_KEEP;
885 case VK_STENCIL_OP_ZERO:
886 return V_02842C_STENCIL_ZERO;
887 case VK_STENCIL_OP_REPLACE:
888 return V_02842C_STENCIL_REPLACE_TEST;
889 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
890 return V_02842C_STENCIL_ADD_CLAMP;
891 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
892 return V_02842C_STENCIL_SUB_CLAMP;
893 case VK_STENCIL_OP_INVERT:
894 return V_02842C_STENCIL_INVERT;
895 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
896 return V_02842C_STENCIL_ADD_WRAP;
897 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
898 return V_02842C_STENCIL_SUB_WRAP;
899 default:
900 return 0;
901 }
902 }
903
904 static uint32_t si_translate_fill(VkPolygonMode func)
905 {
906 switch(func) {
907 case VK_POLYGON_MODE_FILL:
908 return V_028814_X_DRAW_TRIANGLES;
909 case VK_POLYGON_MODE_LINE:
910 return V_028814_X_DRAW_LINES;
911 case VK_POLYGON_MODE_POINT:
912 return V_028814_X_DRAW_POINTS;
913 default:
914 assert(0);
915 return V_028814_X_DRAW_POINTS;
916 }
917 }
918
919 static uint8_t radv_pipeline_get_ps_iter_samples(const VkPipelineMultisampleStateCreateInfo *vkms)
920 {
921 uint32_t num_samples = vkms->rasterizationSamples;
922 uint32_t ps_iter_samples = 1;
923
924 if (vkms->sampleShadingEnable) {
925 ps_iter_samples = ceil(vkms->minSampleShading * num_samples);
926 ps_iter_samples = util_next_power_of_two(ps_iter_samples);
927 }
928 return ps_iter_samples;
929 }
930
931 static bool
932 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
933 {
934 return pCreateInfo->depthTestEnable &&
935 pCreateInfo->depthWriteEnable &&
936 pCreateInfo->depthCompareOp != VK_COMPARE_OP_NEVER;
937 }
938
939 static bool
940 radv_writes_stencil(const VkStencilOpState *state)
941 {
942 return state->writeMask &&
943 (state->failOp != VK_STENCIL_OP_KEEP ||
944 state->passOp != VK_STENCIL_OP_KEEP ||
945 state->depthFailOp != VK_STENCIL_OP_KEEP);
946 }
947
948 static bool
949 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
950 {
951 return pCreateInfo->stencilTestEnable &&
952 (radv_writes_stencil(&pCreateInfo->front) ||
953 radv_writes_stencil(&pCreateInfo->back));
954 }
955
956 static bool
957 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
958 {
959 return radv_is_depth_write_enabled(pCreateInfo) ||
960 radv_is_stencil_write_enabled(pCreateInfo);
961 }
962
963 static bool
964 radv_order_invariant_stencil_op(VkStencilOp op)
965 {
966 /* REPLACE is normally order invariant, except when the stencil
967 * reference value is written by the fragment shader. Tracking this
968 * interaction does not seem worth the effort, so be conservative.
969 */
970 return op != VK_STENCIL_OP_INCREMENT_AND_CLAMP &&
971 op != VK_STENCIL_OP_DECREMENT_AND_CLAMP &&
972 op != VK_STENCIL_OP_REPLACE;
973 }
974
975 static bool
976 radv_order_invariant_stencil_state(const VkStencilOpState *state)
977 {
978 /* Compute whether, assuming Z writes are disabled, this stencil state
979 * is order invariant in the sense that the set of passing fragments as
980 * well as the final stencil buffer result does not depend on the order
981 * of fragments.
982 */
983 return !state->writeMask ||
984 /* The following assumes that Z writes are disabled. */
985 (state->compareOp == VK_COMPARE_OP_ALWAYS &&
986 radv_order_invariant_stencil_op(state->passOp) &&
987 radv_order_invariant_stencil_op(state->depthFailOp)) ||
988 (state->compareOp == VK_COMPARE_OP_NEVER &&
989 radv_order_invariant_stencil_op(state->failOp));
990 }
991
992 static bool
993 radv_pipeline_out_of_order_rast(struct radv_pipeline *pipeline,
994 struct radv_blend_state *blend,
995 const VkGraphicsPipelineCreateInfo *pCreateInfo)
996 {
997 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
998 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
999 unsigned colormask = blend->cb_target_enabled_4bit;
1000
1001 if (!pipeline->device->physical_device->out_of_order_rast_allowed)
1002 return false;
1003
1004 /* Be conservative if a logic operation is enabled with color buffers. */
1005 if (colormask && pCreateInfo->pColorBlendState->logicOpEnable)
1006 return false;
1007
1008 /* Default depth/stencil invariance when no attachment is bound. */
1009 struct radv_dsa_order_invariance dsa_order_invariant = {
1010 .zs = true, .pass_set = true
1011 };
1012
1013 if (pCreateInfo->pDepthStencilState &&
1014 subpass->depth_stencil_attachment) {
1015 const VkPipelineDepthStencilStateCreateInfo *vkds =
1016 pCreateInfo->pDepthStencilState;
1017 struct radv_render_pass_attachment *attachment =
1018 pass->attachments + subpass->depth_stencil_attachment->attachment;
1019 bool has_stencil = vk_format_is_stencil(attachment->format);
1020 struct radv_dsa_order_invariance order_invariance[2];
1021 struct radv_shader_variant *ps =
1022 pipeline->shaders[MESA_SHADER_FRAGMENT];
1023
1024 /* Compute depth/stencil order invariance in order to know if
1025 * it's safe to enable out-of-order.
1026 */
1027 bool zfunc_is_ordered =
1028 vkds->depthCompareOp == VK_COMPARE_OP_NEVER ||
1029 vkds->depthCompareOp == VK_COMPARE_OP_LESS ||
1030 vkds->depthCompareOp == VK_COMPARE_OP_LESS_OR_EQUAL ||
1031 vkds->depthCompareOp == VK_COMPARE_OP_GREATER ||
1032 vkds->depthCompareOp == VK_COMPARE_OP_GREATER_OR_EQUAL;
1033
1034 bool nozwrite_and_order_invariant_stencil =
1035 !radv_is_ds_write_enabled(vkds) ||
1036 (!radv_is_depth_write_enabled(vkds) &&
1037 radv_order_invariant_stencil_state(&vkds->front) &&
1038 radv_order_invariant_stencil_state(&vkds->back));
1039
1040 order_invariance[1].zs =
1041 nozwrite_and_order_invariant_stencil ||
1042 (!radv_is_stencil_write_enabled(vkds) &&
1043 zfunc_is_ordered);
1044 order_invariance[0].zs =
1045 !radv_is_depth_write_enabled(vkds) || zfunc_is_ordered;
1046
1047 order_invariance[1].pass_set =
1048 nozwrite_and_order_invariant_stencil ||
1049 (!radv_is_stencil_write_enabled(vkds) &&
1050 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1051 vkds->depthCompareOp == VK_COMPARE_OP_NEVER));
1052 order_invariance[0].pass_set =
1053 !radv_is_depth_write_enabled(vkds) ||
1054 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1055 vkds->depthCompareOp == VK_COMPARE_OP_NEVER);
1056
1057 dsa_order_invariant = order_invariance[has_stencil];
1058 if (!dsa_order_invariant.zs)
1059 return false;
1060
1061 /* The set of PS invocations is always order invariant,
1062 * except when early Z/S tests are requested.
1063 */
1064 if (ps &&
1065 ps->info.ps.writes_memory &&
1066 ps->info.ps.early_fragment_test &&
1067 !dsa_order_invariant.pass_set)
1068 return false;
1069
1070 /* Determine if out-of-order rasterization should be disabled
1071 * when occlusion queries are used.
1072 */
1073 pipeline->graphics.disable_out_of_order_rast_for_occlusion =
1074 !dsa_order_invariant.pass_set;
1075 }
1076
1077 /* No color buffers are enabled for writing. */
1078 if (!colormask)
1079 return true;
1080
1081 unsigned blendmask = colormask & blend->blend_enable_4bit;
1082
1083 if (blendmask) {
1084 /* Only commutative blending. */
1085 if (blendmask & ~blend->commutative_4bit)
1086 return false;
1087
1088 if (!dsa_order_invariant.pass_set)
1089 return false;
1090 }
1091
1092 if (colormask & ~blendmask)
1093 return false;
1094
1095 return true;
1096 }
1097
1098 static void
1099 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1100 struct radv_blend_state *blend,
1101 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1102 {
1103 const VkPipelineMultisampleStateCreateInfo *vkms = radv_pipeline_get_multisample_state(pCreateInfo);
1104 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1105 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1106 bool out_of_order_rast = false;
1107 int ps_iter_samples = 1;
1108 uint32_t mask = 0xffff;
1109
1110 if (vkms) {
1111 ms->num_samples = vkms->rasterizationSamples;
1112
1113 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
1114 *
1115 * "Sample shading is enabled for a graphics pipeline:
1116 *
1117 * - If the interface of the fragment shader entry point of the
1118 * graphics pipeline includes an input variable decorated
1119 * with SampleId or SamplePosition. In this case
1120 * minSampleShadingFactor takes the value 1.0.
1121 * - Else if the sampleShadingEnable member of the
1122 * VkPipelineMultisampleStateCreateInfo structure specified
1123 * when creating the graphics pipeline is set to VK_TRUE. In
1124 * this case minSampleShadingFactor takes the value of
1125 * VkPipelineMultisampleStateCreateInfo::minSampleShading.
1126 *
1127 * Otherwise, sample shading is considered disabled."
1128 */
1129 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.force_persample) {
1130 ps_iter_samples = ms->num_samples;
1131 } else {
1132 ps_iter_samples = radv_pipeline_get_ps_iter_samples(vkms);
1133 }
1134 } else {
1135 ms->num_samples = 1;
1136 }
1137
1138 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
1139 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
1140 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
1141 /* Out-of-order rasterization is explicitly enabled by the
1142 * application.
1143 */
1144 out_of_order_rast = true;
1145 } else {
1146 /* Determine if the driver can enable out-of-order
1147 * rasterization internally.
1148 */
1149 out_of_order_rast =
1150 radv_pipeline_out_of_order_rast(pipeline, blend, pCreateInfo);
1151 }
1152
1153 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1154 ms->pa_sc_aa_config = 0;
1155 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1156 S_028804_INCOHERENT_EQAA_READS(1) |
1157 S_028804_INTERPOLATE_COMP_Z(1) |
1158 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1159 ms->pa_sc_mode_cntl_1 =
1160 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1161 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1162 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
1163 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1164 /* always 1: */
1165 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1166 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1167 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1168 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1169 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1170 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1171 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9) |
1172 S_028A48_VPORT_SCISSOR_ENABLE(1);
1173
1174 if (ms->num_samples > 1) {
1175 unsigned log_samples = util_logbase2(ms->num_samples);
1176 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
1177 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
1178 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1179 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1180 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1181 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1182 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1183 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1184 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples)) |
1185 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1186 ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1187 if (ps_iter_samples > 1)
1188 pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1189 }
1190
1191 if (vkms && vkms->pSampleMask) {
1192 mask = vkms->pSampleMask[0] & 0xffff;
1193 }
1194
1195 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1196 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1197 }
1198
1199 static bool
1200 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1201 {
1202 switch (topology) {
1203 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1204 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1205 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1206 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1207 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1208 return false;
1209 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1210 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1211 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1212 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1213 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1214 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1215 return true;
1216 default:
1217 unreachable("unhandled primitive type");
1218 }
1219 }
1220
1221 static uint32_t
1222 si_translate_prim(enum VkPrimitiveTopology topology)
1223 {
1224 switch (topology) {
1225 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1226 return V_008958_DI_PT_POINTLIST;
1227 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1228 return V_008958_DI_PT_LINELIST;
1229 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1230 return V_008958_DI_PT_LINESTRIP;
1231 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1232 return V_008958_DI_PT_TRILIST;
1233 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1234 return V_008958_DI_PT_TRISTRIP;
1235 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1236 return V_008958_DI_PT_TRIFAN;
1237 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1238 return V_008958_DI_PT_LINELIST_ADJ;
1239 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1240 return V_008958_DI_PT_LINESTRIP_ADJ;
1241 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1242 return V_008958_DI_PT_TRILIST_ADJ;
1243 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1244 return V_008958_DI_PT_TRISTRIP_ADJ;
1245 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1246 return V_008958_DI_PT_PATCH;
1247 default:
1248 assert(0);
1249 return 0;
1250 }
1251 }
1252
1253 static uint32_t
1254 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1255 {
1256 switch (gl_prim) {
1257 case 0: /* GL_POINTS */
1258 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1259 case 1: /* GL_LINES */
1260 case 3: /* GL_LINE_STRIP */
1261 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1262 case 0x8E7A: /* GL_ISOLINES */
1263 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1264
1265 case 4: /* GL_TRIANGLES */
1266 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1267 case 5: /* GL_TRIANGLE_STRIP */
1268 case 7: /* GL_QUADS */
1269 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1270 default:
1271 assert(0);
1272 return 0;
1273 }
1274 }
1275
1276 static uint32_t
1277 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1278 {
1279 switch (topology) {
1280 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1281 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1282 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1283 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1284 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1285 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1286 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1287 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1288 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1289 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1290 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1291 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1292 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1293 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1294 default:
1295 assert(0);
1296 return 0;
1297 }
1298 }
1299
1300 static unsigned radv_dynamic_state_mask(VkDynamicState state)
1301 {
1302 switch(state) {
1303 case VK_DYNAMIC_STATE_VIEWPORT:
1304 return RADV_DYNAMIC_VIEWPORT;
1305 case VK_DYNAMIC_STATE_SCISSOR:
1306 return RADV_DYNAMIC_SCISSOR;
1307 case VK_DYNAMIC_STATE_LINE_WIDTH:
1308 return RADV_DYNAMIC_LINE_WIDTH;
1309 case VK_DYNAMIC_STATE_DEPTH_BIAS:
1310 return RADV_DYNAMIC_DEPTH_BIAS;
1311 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
1312 return RADV_DYNAMIC_BLEND_CONSTANTS;
1313 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
1314 return RADV_DYNAMIC_DEPTH_BOUNDS;
1315 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
1316 return RADV_DYNAMIC_STENCIL_COMPARE_MASK;
1317 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
1318 return RADV_DYNAMIC_STENCIL_WRITE_MASK;
1319 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
1320 return RADV_DYNAMIC_STENCIL_REFERENCE;
1321 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT:
1322 return RADV_DYNAMIC_DISCARD_RECTANGLE;
1323 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT:
1324 return RADV_DYNAMIC_SAMPLE_LOCATIONS;
1325 default:
1326 unreachable("Unhandled dynamic state");
1327 }
1328 }
1329
1330 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
1331 {
1332 uint32_t states = RADV_DYNAMIC_ALL;
1333
1334 /* If rasterization is disabled we do not care about any of the dynamic states,
1335 * since they are all rasterization related only. */
1336 if (pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
1337 return 0;
1338
1339 if (!pCreateInfo->pRasterizationState->depthBiasEnable)
1340 states &= ~RADV_DYNAMIC_DEPTH_BIAS;
1341
1342 if (!pCreateInfo->pDepthStencilState ||
1343 !pCreateInfo->pDepthStencilState->depthBoundsTestEnable)
1344 states &= ~RADV_DYNAMIC_DEPTH_BOUNDS;
1345
1346 if (!pCreateInfo->pDepthStencilState ||
1347 !pCreateInfo->pDepthStencilState->stencilTestEnable)
1348 states &= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK |
1349 RADV_DYNAMIC_STENCIL_WRITE_MASK |
1350 RADV_DYNAMIC_STENCIL_REFERENCE);
1351
1352 if (!vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT))
1353 states &= ~RADV_DYNAMIC_DISCARD_RECTANGLE;
1354
1355 if (!pCreateInfo->pMultisampleState ||
1356 !vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1357 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT))
1358 states &= ~RADV_DYNAMIC_SAMPLE_LOCATIONS;
1359
1360 /* TODO: blend constants & line width. */
1361
1362 return states;
1363 }
1364
1365
1366 static void
1367 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1368 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1369 {
1370 uint32_t needed_states = radv_pipeline_needed_dynamic_state(pCreateInfo);
1371 uint32_t states = needed_states;
1372 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1373 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1374
1375 pipeline->dynamic_state = default_dynamic_state;
1376 pipeline->graphics.needed_dynamic_state = needed_states;
1377
1378 if (pCreateInfo->pDynamicState) {
1379 /* Remove all of the states that are marked as dynamic */
1380 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1381 for (uint32_t s = 0; s < count; s++)
1382 states &= ~radv_dynamic_state_mask(pCreateInfo->pDynamicState->pDynamicStates[s]);
1383 }
1384
1385 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1386
1387 if (needed_states & RADV_DYNAMIC_VIEWPORT) {
1388 assert(pCreateInfo->pViewportState);
1389
1390 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1391 if (states & RADV_DYNAMIC_VIEWPORT) {
1392 typed_memcpy(dynamic->viewport.viewports,
1393 pCreateInfo->pViewportState->pViewports,
1394 pCreateInfo->pViewportState->viewportCount);
1395 }
1396 }
1397
1398 if (needed_states & RADV_DYNAMIC_SCISSOR) {
1399 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1400 if (states & RADV_DYNAMIC_SCISSOR) {
1401 typed_memcpy(dynamic->scissor.scissors,
1402 pCreateInfo->pViewportState->pScissors,
1403 pCreateInfo->pViewportState->scissorCount);
1404 }
1405 }
1406
1407 if (states & RADV_DYNAMIC_LINE_WIDTH) {
1408 assert(pCreateInfo->pRasterizationState);
1409 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1410 }
1411
1412 if (states & RADV_DYNAMIC_DEPTH_BIAS) {
1413 assert(pCreateInfo->pRasterizationState);
1414 dynamic->depth_bias.bias =
1415 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1416 dynamic->depth_bias.clamp =
1417 pCreateInfo->pRasterizationState->depthBiasClamp;
1418 dynamic->depth_bias.slope =
1419 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1420 }
1421
1422 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1423 *
1424 * pColorBlendState is [...] NULL if the pipeline has rasterization
1425 * disabled or if the subpass of the render pass the pipeline is
1426 * created against does not use any color attachments.
1427 */
1428 if (subpass->has_color_att && states & RADV_DYNAMIC_BLEND_CONSTANTS) {
1429 assert(pCreateInfo->pColorBlendState);
1430 typed_memcpy(dynamic->blend_constants,
1431 pCreateInfo->pColorBlendState->blendConstants, 4);
1432 }
1433
1434 /* If there is no depthstencil attachment, then don't read
1435 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1436 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1437 * no need to override the depthstencil defaults in
1438 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1439 *
1440 * Section 9.2 of the Vulkan 1.0.15 spec says:
1441 *
1442 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1443 * disabled or if the subpass of the render pass the pipeline is created
1444 * against does not use a depth/stencil attachment.
1445 */
1446 if (needed_states && subpass->depth_stencil_attachment) {
1447 assert(pCreateInfo->pDepthStencilState);
1448
1449 if (states & RADV_DYNAMIC_DEPTH_BOUNDS) {
1450 dynamic->depth_bounds.min =
1451 pCreateInfo->pDepthStencilState->minDepthBounds;
1452 dynamic->depth_bounds.max =
1453 pCreateInfo->pDepthStencilState->maxDepthBounds;
1454 }
1455
1456 if (states & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
1457 dynamic->stencil_compare_mask.front =
1458 pCreateInfo->pDepthStencilState->front.compareMask;
1459 dynamic->stencil_compare_mask.back =
1460 pCreateInfo->pDepthStencilState->back.compareMask;
1461 }
1462
1463 if (states & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
1464 dynamic->stencil_write_mask.front =
1465 pCreateInfo->pDepthStencilState->front.writeMask;
1466 dynamic->stencil_write_mask.back =
1467 pCreateInfo->pDepthStencilState->back.writeMask;
1468 }
1469
1470 if (states & RADV_DYNAMIC_STENCIL_REFERENCE) {
1471 dynamic->stencil_reference.front =
1472 pCreateInfo->pDepthStencilState->front.reference;
1473 dynamic->stencil_reference.back =
1474 pCreateInfo->pDepthStencilState->back.reference;
1475 }
1476 }
1477
1478 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
1479 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
1480 if (needed_states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1481 dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount;
1482 if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1483 typed_memcpy(dynamic->discard_rectangle.rectangles,
1484 discard_rectangle_info->pDiscardRectangles,
1485 discard_rectangle_info->discardRectangleCount);
1486 }
1487 }
1488
1489 if (needed_states & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
1490 const VkPipelineSampleLocationsStateCreateInfoEXT *sample_location_info =
1491 vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1492 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
1493 /* If sampleLocationsEnable is VK_FALSE, the default sample
1494 * locations are used and the values specified in
1495 * sampleLocationsInfo are ignored.
1496 */
1497 if (sample_location_info->sampleLocationsEnable) {
1498 const VkSampleLocationsInfoEXT *pSampleLocationsInfo =
1499 &sample_location_info->sampleLocationsInfo;
1500
1501 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
1502
1503 dynamic->sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
1504 dynamic->sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
1505 dynamic->sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
1506 typed_memcpy(&dynamic->sample_location.locations[0],
1507 pSampleLocationsInfo->pSampleLocations,
1508 pSampleLocationsInfo->sampleLocationsCount);
1509 }
1510 }
1511
1512 pipeline->dynamic_state.mask = states;
1513 }
1514
1515 static void
1516 gfx9_get_gs_info(const struct radv_pipeline_key *key,
1517 const struct radv_pipeline *pipeline,
1518 nir_shader **nir,
1519 struct radv_shader_info *infos,
1520 struct gfx9_gs_info *out)
1521 {
1522 struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY];
1523 struct radv_es_output_info *es_info;
1524 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
1525 es_info = nir[MESA_SHADER_TESS_CTRL] ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1526 else
1527 es_info = nir[MESA_SHADER_TESS_CTRL] ?
1528 &infos[MESA_SHADER_TESS_EVAL].tes.es_info :
1529 &infos[MESA_SHADER_VERTEX].vs.es_info;
1530
1531 unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
1532 bool uses_adjacency;
1533 switch(key->topology) {
1534 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1535 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1536 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1537 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1538 uses_adjacency = true;
1539 break;
1540 default:
1541 uses_adjacency = false;
1542 break;
1543 }
1544
1545 /* All these are in dwords: */
1546 /* We can't allow using the whole LDS, because GS waves compete with
1547 * other shader stages for LDS space. */
1548 const unsigned max_lds_size = 8 * 1024;
1549 const unsigned esgs_itemsize = es_info->esgs_itemsize / 4;
1550 unsigned esgs_lds_size;
1551
1552 /* All these are per subgroup: */
1553 const unsigned max_out_prims = 32 * 1024;
1554 const unsigned max_es_verts = 255;
1555 const unsigned ideal_gs_prims = 64;
1556 unsigned max_gs_prims, gs_prims;
1557 unsigned min_es_verts, es_verts, worst_case_es_verts;
1558
1559 if (uses_adjacency || gs_num_invocations > 1)
1560 max_gs_prims = 127 / gs_num_invocations;
1561 else
1562 max_gs_prims = 255;
1563
1564 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1565 * Make sure we don't go over the maximum value.
1566 */
1567 if (gs_info->gs.vertices_out > 0) {
1568 max_gs_prims = MIN2(max_gs_prims,
1569 max_out_prims /
1570 (gs_info->gs.vertices_out * gs_num_invocations));
1571 }
1572 assert(max_gs_prims > 0);
1573
1574 /* If the primitive has adjacency, halve the number of vertices
1575 * that will be reused in multiple primitives.
1576 */
1577 min_es_verts = gs_info->gs.vertices_in / (uses_adjacency ? 2 : 1);
1578
1579 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
1580 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
1581
1582 /* Compute ESGS LDS size based on the worst case number of ES vertices
1583 * needed to create the target number of GS prims per subgroup.
1584 */
1585 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1586
1587 /* If total LDS usage is too big, refactor partitions based on ratio
1588 * of ESGS item sizes.
1589 */
1590 if (esgs_lds_size > max_lds_size) {
1591 /* Our target GS Prims Per Subgroup was too large. Calculate
1592 * the maximum number of GS Prims Per Subgroup that will fit
1593 * into LDS, capped by the maximum that the hardware can support.
1594 */
1595 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
1596 max_gs_prims);
1597 assert(gs_prims > 0);
1598 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
1599 max_es_verts);
1600
1601 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1602 assert(esgs_lds_size <= max_lds_size);
1603 }
1604
1605 /* Now calculate remaining ESGS information. */
1606 if (esgs_lds_size)
1607 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
1608 else
1609 es_verts = max_es_verts;
1610
1611 /* Vertices for adjacency primitives are not always reused, so restore
1612 * it for ES_VERTS_PER_SUBGRP.
1613 */
1614 min_es_verts = gs_info->gs.vertices_in;
1615
1616 /* For normal primitives, the VGT only checks if they are past the ES
1617 * verts per subgroup after allocating a full GS primitive and if they
1618 * are, kick off a new subgroup. But if those additional ES verts are
1619 * unique (e.g. not reused) we need to make sure there is enough LDS
1620 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1621 */
1622 es_verts -= min_es_verts - 1;
1623
1624 uint32_t es_verts_per_subgroup = es_verts;
1625 uint32_t gs_prims_per_subgroup = gs_prims;
1626 uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
1627 uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out;
1628 out->lds_size = align(esgs_lds_size, 128) / 128;
1629 out->vgt_gs_onchip_cntl = S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) |
1630 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) |
1631 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup);
1632 out->vgt_gs_max_prims_per_subgroup = S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup);
1633 out->vgt_esgs_ring_itemsize = esgs_itemsize;
1634 assert(max_prims_per_subgroup <= max_out_prims);
1635 }
1636
1637 static void clamp_gsprims_to_esverts(unsigned *max_gsprims, unsigned max_esverts,
1638 unsigned min_verts_per_prim, bool use_adjacency)
1639 {
1640 unsigned max_reuse = max_esverts - min_verts_per_prim;
1641 if (use_adjacency)
1642 max_reuse /= 2;
1643 *max_gsprims = MIN2(*max_gsprims, 1 + max_reuse);
1644 }
1645
1646 static unsigned
1647 radv_get_num_input_vertices(nir_shader **nir)
1648 {
1649 if (nir[MESA_SHADER_GEOMETRY]) {
1650 nir_shader *gs = nir[MESA_SHADER_GEOMETRY];
1651
1652 return gs->info.gs.vertices_in;
1653 }
1654
1655 if (nir[MESA_SHADER_TESS_CTRL]) {
1656 nir_shader *tes = nir[MESA_SHADER_TESS_EVAL];
1657
1658 if (tes->info.tess.point_mode)
1659 return 1;
1660 if (tes->info.tess.primitive_mode == GL_ISOLINES)
1661 return 2;
1662 return 3;
1663 }
1664
1665 return 3;
1666 }
1667
1668 static void
1669 gfx10_get_ngg_info(const struct radv_pipeline_key *key,
1670 struct radv_pipeline *pipeline,
1671 nir_shader **nir,
1672 struct radv_shader_info *infos,
1673 struct gfx10_ngg_info *ngg)
1674 {
1675 struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY];
1676 struct radv_es_output_info *es_info =
1677 nir[MESA_SHADER_TESS_CTRL] ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1678 unsigned gs_type = nir[MESA_SHADER_GEOMETRY] ? MESA_SHADER_GEOMETRY : MESA_SHADER_VERTEX;
1679 unsigned max_verts_per_prim = radv_get_num_input_vertices(nir);
1680 unsigned min_verts_per_prim =
1681 gs_type == MESA_SHADER_GEOMETRY ? max_verts_per_prim : 1;
1682 unsigned gs_num_invocations = nir[MESA_SHADER_GEOMETRY] ? MAX2(gs_info->gs.invocations, 1) : 1;
1683 bool uses_adjacency;
1684 switch(key->topology) {
1685 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1686 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1687 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1688 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1689 uses_adjacency = true;
1690 break;
1691 default:
1692 uses_adjacency = false;
1693 break;
1694 }
1695
1696 /* All these are in dwords: */
1697 /* We can't allow using the whole LDS, because GS waves compete with
1698 * other shader stages for LDS space.
1699 *
1700 * TODO: We should really take the shader's internal LDS use into
1701 * account. The linker will fail if the size is greater than
1702 * 8K dwords.
1703 */
1704 const unsigned max_lds_size = 8 * 1024 - 768;
1705 const unsigned target_lds_size = max_lds_size;
1706 unsigned esvert_lds_size = 0;
1707 unsigned gsprim_lds_size = 0;
1708
1709 /* All these are per subgroup: */
1710 bool max_vert_out_per_gs_instance = false;
1711 unsigned max_esverts_base = 256;
1712 unsigned max_gsprims_base = 128; /* default prim group size clamp */
1713
1714 /* Hardware has the following non-natural restrictions on the value
1715 * of GE_CNTL.VERT_GRP_SIZE based on based on the primitive type of
1716 * the draw:
1717 * - at most 252 for any line input primitive type
1718 * - at most 251 for any quad input primitive type
1719 * - at most 251 for triangle strips with adjacency (this happens to
1720 * be the natural limit for triangle *lists* with adjacency)
1721 */
1722 max_esverts_base = MIN2(max_esverts_base, 251 + max_verts_per_prim - 1);
1723
1724 if (gs_type == MESA_SHADER_GEOMETRY) {
1725 unsigned max_out_verts_per_gsprim =
1726 gs_info->gs.vertices_out * gs_num_invocations;
1727
1728 if (max_out_verts_per_gsprim <= 256) {
1729 if (max_out_verts_per_gsprim) {
1730 max_gsprims_base = MIN2(max_gsprims_base,
1731 256 / max_out_verts_per_gsprim);
1732 }
1733 } else {
1734 /* Use special multi-cycling mode in which each GS
1735 * instance gets its own subgroup. Does not work with
1736 * tessellation. */
1737 max_vert_out_per_gs_instance = true;
1738 max_gsprims_base = 1;
1739 max_out_verts_per_gsprim = gs_info->gs.vertices_out;
1740 }
1741
1742 esvert_lds_size = es_info->esgs_itemsize / 4;
1743 gsprim_lds_size = (gs_info->gs.gsvs_vertex_size / 4 + 1) * max_out_verts_per_gsprim;
1744 } else {
1745 /* VS and TES. */
1746 /* LDS size for passing data from GS to ES. */
1747 struct radv_streamout_info *so_info = nir[MESA_SHADER_TESS_CTRL]
1748 ? &infos[MESA_SHADER_TESS_EVAL].so
1749 : &infos[MESA_SHADER_VERTEX].so;
1750
1751 if (so_info->num_outputs)
1752 esvert_lds_size = 4 * so_info->num_outputs + 1;
1753
1754 /* GS stores Primitive IDs (one DWORD) into LDS at the address
1755 * corresponding to the ES thread of the provoking vertex. All
1756 * ES threads load and export PrimitiveID for their thread.
1757 */
1758 if (!nir[MESA_SHADER_TESS_CTRL] &&
1759 infos[MESA_SHADER_VERTEX].vs.outinfo.export_prim_id)
1760 esvert_lds_size = MAX2(esvert_lds_size, 1);
1761 }
1762
1763 unsigned max_gsprims = max_gsprims_base;
1764 unsigned max_esverts = max_esverts_base;
1765
1766 if (esvert_lds_size)
1767 max_esverts = MIN2(max_esverts, target_lds_size / esvert_lds_size);
1768 if (gsprim_lds_size)
1769 max_gsprims = MIN2(max_gsprims, target_lds_size / gsprim_lds_size);
1770
1771 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1772 clamp_gsprims_to_esverts(&max_gsprims, max_esverts, min_verts_per_prim, uses_adjacency);
1773 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1774
1775 if (esvert_lds_size || gsprim_lds_size) {
1776 /* Now that we have a rough proportionality between esverts
1777 * and gsprims based on the primitive type, scale both of them
1778 * down simultaneously based on required LDS space.
1779 *
1780 * We could be smarter about this if we knew how much vertex
1781 * reuse to expect.
1782 */
1783 unsigned lds_total = max_esverts * esvert_lds_size +
1784 max_gsprims * gsprim_lds_size;
1785 if (lds_total > target_lds_size) {
1786 max_esverts = max_esverts * target_lds_size / lds_total;
1787 max_gsprims = max_gsprims * target_lds_size / lds_total;
1788
1789 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1790 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1791 min_verts_per_prim, uses_adjacency);
1792 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1793 }
1794 }
1795
1796 /* Round up towards full wave sizes for better ALU utilization. */
1797 if (!max_vert_out_per_gs_instance) {
1798 unsigned orig_max_esverts;
1799 unsigned orig_max_gsprims;
1800 unsigned wavesize;
1801
1802 if (gs_type == MESA_SHADER_GEOMETRY) {
1803 wavesize = gs_info->wave_size;
1804 } else {
1805 wavesize = nir[MESA_SHADER_TESS_CTRL]
1806 ? infos[MESA_SHADER_TESS_EVAL].wave_size
1807 : infos[MESA_SHADER_VERTEX].wave_size;
1808 }
1809
1810 do {
1811 orig_max_esverts = max_esverts;
1812 orig_max_gsprims = max_gsprims;
1813
1814 max_esverts = align(max_esverts, wavesize);
1815 max_esverts = MIN2(max_esverts, max_esverts_base);
1816 if (esvert_lds_size)
1817 max_esverts = MIN2(max_esverts,
1818 (max_lds_size - max_gsprims * gsprim_lds_size) /
1819 esvert_lds_size);
1820 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1821
1822 max_gsprims = align(max_gsprims, wavesize);
1823 max_gsprims = MIN2(max_gsprims, max_gsprims_base);
1824 if (gsprim_lds_size)
1825 max_gsprims = MIN2(max_gsprims,
1826 (max_lds_size - max_esverts * esvert_lds_size) /
1827 gsprim_lds_size);
1828 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1829 min_verts_per_prim, uses_adjacency);
1830 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1831 } while (orig_max_esverts != max_esverts || orig_max_gsprims != max_gsprims);
1832 }
1833
1834 /* Hardware restriction: minimum value of max_esverts */
1835 max_esverts = MAX2(max_esverts, 23 + max_verts_per_prim);
1836
1837 unsigned max_out_vertices =
1838 max_vert_out_per_gs_instance ? gs_info->gs.vertices_out :
1839 gs_type == MESA_SHADER_GEOMETRY ?
1840 max_gsprims * gs_num_invocations * gs_info->gs.vertices_out :
1841 max_esverts;
1842 assert(max_out_vertices <= 256);
1843
1844 unsigned prim_amp_factor = 1;
1845 if (gs_type == MESA_SHADER_GEOMETRY) {
1846 /* Number of output primitives per GS input primitive after
1847 * GS instancing. */
1848 prim_amp_factor = gs_info->gs.vertices_out;
1849 }
1850
1851 /* The GE only checks against the maximum number of ES verts after
1852 * allocating a full GS primitive. So we need to ensure that whenever
1853 * this check passes, there is enough space for a full primitive without
1854 * vertex reuse.
1855 */
1856 ngg->hw_max_esverts = max_esverts - max_verts_per_prim + 1;
1857 ngg->max_gsprims = max_gsprims;
1858 ngg->max_out_verts = max_out_vertices;
1859 ngg->prim_amp_factor = prim_amp_factor;
1860 ngg->max_vert_out_per_gs_instance = max_vert_out_per_gs_instance;
1861 ngg->ngg_emit_size = max_gsprims * gsprim_lds_size;
1862 ngg->esgs_ring_size = 4 * max_esverts * esvert_lds_size;
1863
1864 if (gs_type == MESA_SHADER_GEOMETRY) {
1865 ngg->vgt_esgs_ring_itemsize = es_info->esgs_itemsize / 4;
1866 } else {
1867 ngg->vgt_esgs_ring_itemsize = 1;
1868 }
1869
1870 pipeline->graphics.esgs_ring_size = ngg->esgs_ring_size;
1871
1872 assert(ngg->hw_max_esverts >= 24); /* HW limitation */
1873 }
1874
1875 static void
1876 calculate_gs_ring_sizes(struct radv_pipeline *pipeline,
1877 const struct gfx9_gs_info *gs)
1878 {
1879 struct radv_device *device = pipeline->device;
1880 unsigned num_se = device->physical_device->rad_info.max_se;
1881 unsigned wave_size = 64;
1882 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1883 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
1884 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
1885 */
1886 unsigned gs_vertex_reuse =
1887 (device->physical_device->rad_info.chip_class >= GFX8 ? 32 : 16) * num_se;
1888 unsigned alignment = 256 * num_se;
1889 /* The maximum size is 63.999 MB per SE. */
1890 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1891 struct radv_shader_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1892
1893 /* Calculate the minimum size. */
1894 unsigned min_esgs_ring_size = align(gs->vgt_esgs_ring_itemsize * 4 * gs_vertex_reuse *
1895 wave_size, alignment);
1896 /* These are recommended sizes, not minimum sizes. */
1897 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1898 gs->vgt_esgs_ring_itemsize * 4 * gs_info->gs.vertices_in;
1899 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1900 gs_info->gs.max_gsvs_emit_size;
1901
1902 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1903 esgs_ring_size = align(esgs_ring_size, alignment);
1904 gsvs_ring_size = align(gsvs_ring_size, alignment);
1905
1906 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
1907 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1908
1909 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1910 }
1911
1912 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1913 unsigned *lds_size)
1914 {
1915 /* If tessellation is all offchip and on-chip GS isn't used, this
1916 * workaround is not needed.
1917 */
1918 return;
1919
1920 /* SPI barrier management bug:
1921 * Make sure we have at least 4k of LDS in use to avoid the bug.
1922 * It applies to workgroup sizes of more than one wavefront.
1923 */
1924 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1925 device->physical_device->rad_info.family == CHIP_KABINI)
1926 *lds_size = MAX2(*lds_size, 8);
1927 }
1928
1929 struct radv_shader_variant *
1930 radv_get_shader(struct radv_pipeline *pipeline,
1931 gl_shader_stage stage)
1932 {
1933 if (stage == MESA_SHADER_VERTEX) {
1934 if (pipeline->shaders[MESA_SHADER_VERTEX])
1935 return pipeline->shaders[MESA_SHADER_VERTEX];
1936 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
1937 return pipeline->shaders[MESA_SHADER_TESS_CTRL];
1938 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1939 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1940 } else if (stage == MESA_SHADER_TESS_EVAL) {
1941 if (!radv_pipeline_has_tess(pipeline))
1942 return NULL;
1943 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
1944 return pipeline->shaders[MESA_SHADER_TESS_EVAL];
1945 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1946 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1947 }
1948 return pipeline->shaders[stage];
1949 }
1950
1951 static struct radv_tessellation_state
1952 calculate_tess_state(struct radv_pipeline *pipeline,
1953 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1954 {
1955 unsigned num_tcs_input_cp;
1956 unsigned num_tcs_output_cp;
1957 unsigned lds_size;
1958 unsigned num_patches;
1959 struct radv_tessellation_state tess = {0};
1960
1961 num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1962 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1963 num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
1964
1965 lds_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.lds_size;
1966
1967 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
1968 assert(lds_size <= 65536);
1969 lds_size = align(lds_size, 512) / 512;
1970 } else {
1971 assert(lds_size <= 32768);
1972 lds_size = align(lds_size, 256) / 256;
1973 }
1974 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1975
1976 tess.lds_size = lds_size;
1977
1978 tess.ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1979 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1980 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1981 tess.num_patches = num_patches;
1982
1983 struct radv_shader_variant *tes = radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL);
1984 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1985
1986 switch (tes->info.tes.primitive_mode) {
1987 case GL_TRIANGLES:
1988 type = V_028B6C_TESS_TRIANGLE;
1989 break;
1990 case GL_QUADS:
1991 type = V_028B6C_TESS_QUAD;
1992 break;
1993 case GL_ISOLINES:
1994 type = V_028B6C_TESS_ISOLINE;
1995 break;
1996 }
1997
1998 switch (tes->info.tes.spacing) {
1999 case TESS_SPACING_EQUAL:
2000 partitioning = V_028B6C_PART_INTEGER;
2001 break;
2002 case TESS_SPACING_FRACTIONAL_ODD:
2003 partitioning = V_028B6C_PART_FRAC_ODD;
2004 break;
2005 case TESS_SPACING_FRACTIONAL_EVEN:
2006 partitioning = V_028B6C_PART_FRAC_EVEN;
2007 break;
2008 default:
2009 break;
2010 }
2011
2012 bool ccw = tes->info.tes.ccw;
2013 const VkPipelineTessellationDomainOriginStateCreateInfo *domain_origin_state =
2014 vk_find_struct_const(pCreateInfo->pTessellationState,
2015 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO);
2016
2017 if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT)
2018 ccw = !ccw;
2019
2020 if (tes->info.tes.point_mode)
2021 topology = V_028B6C_OUTPUT_POINT;
2022 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
2023 topology = V_028B6C_OUTPUT_LINE;
2024 else if (ccw)
2025 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
2026 else
2027 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
2028
2029 if (pipeline->device->physical_device->rad_info.has_distributed_tess) {
2030 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
2031 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
2032 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
2033 else
2034 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
2035 } else
2036 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
2037
2038 tess.tf_param = S_028B6C_TYPE(type) |
2039 S_028B6C_PARTITIONING(partitioning) |
2040 S_028B6C_TOPOLOGY(topology) |
2041 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
2042
2043 return tess;
2044 }
2045
2046 static const struct radv_prim_vertex_count prim_size_table[] = {
2047 [V_008958_DI_PT_NONE] = {0, 0},
2048 [V_008958_DI_PT_POINTLIST] = {1, 1},
2049 [V_008958_DI_PT_LINELIST] = {2, 2},
2050 [V_008958_DI_PT_LINESTRIP] = {2, 1},
2051 [V_008958_DI_PT_TRILIST] = {3, 3},
2052 [V_008958_DI_PT_TRIFAN] = {3, 1},
2053 [V_008958_DI_PT_TRISTRIP] = {3, 1},
2054 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
2055 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
2056 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
2057 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
2058 [V_008958_DI_PT_RECTLIST] = {3, 3},
2059 [V_008958_DI_PT_LINELOOP] = {2, 1},
2060 [V_008958_DI_PT_POLYGON] = {3, 1},
2061 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
2062 };
2063
2064 static const struct radv_vs_output_info *get_vs_output_info(const struct radv_pipeline *pipeline)
2065 {
2066 if (radv_pipeline_has_gs(pipeline))
2067 if (radv_pipeline_has_ngg(pipeline))
2068 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.vs.outinfo;
2069 else
2070 return &pipeline->gs_copy_shader->info.vs.outinfo;
2071 else if (radv_pipeline_has_tess(pipeline))
2072 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
2073 else
2074 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
2075 }
2076
2077 static void
2078 radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
2079 {
2080 nir_shader* ordered_shaders[MESA_SHADER_STAGES];
2081 int shader_count = 0;
2082
2083 if(shaders[MESA_SHADER_FRAGMENT]) {
2084 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
2085 }
2086 if(shaders[MESA_SHADER_GEOMETRY]) {
2087 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
2088 }
2089 if(shaders[MESA_SHADER_TESS_EVAL]) {
2090 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
2091 }
2092 if(shaders[MESA_SHADER_TESS_CTRL]) {
2093 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
2094 }
2095 if(shaders[MESA_SHADER_VERTEX]) {
2096 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
2097 }
2098
2099 if (shader_count > 1) {
2100 unsigned first = ordered_shaders[shader_count - 1]->info.stage;
2101 unsigned last = ordered_shaders[0]->info.stage;
2102
2103 if (ordered_shaders[0]->info.stage == MESA_SHADER_FRAGMENT &&
2104 ordered_shaders[1]->info.has_transform_feedback_varyings)
2105 nir_link_xfb_varyings(ordered_shaders[1], ordered_shaders[0]);
2106
2107 for (int i = 0; i < shader_count; ++i) {
2108 nir_variable_mode mask = 0;
2109
2110 if (ordered_shaders[i]->info.stage != first)
2111 mask = mask | nir_var_shader_in;
2112
2113 if (ordered_shaders[i]->info.stage != last)
2114 mask = mask | nir_var_shader_out;
2115
2116 nir_lower_io_to_scalar_early(ordered_shaders[i], mask);
2117 radv_optimize_nir(ordered_shaders[i], false, false);
2118 }
2119 }
2120
2121 for (int i = 1; i < shader_count; ++i) {
2122 nir_lower_io_arrays_to_elements(ordered_shaders[i],
2123 ordered_shaders[i - 1]);
2124
2125 if (nir_link_opt_varyings(ordered_shaders[i],
2126 ordered_shaders[i - 1]))
2127 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2128
2129 nir_remove_dead_variables(ordered_shaders[i],
2130 nir_var_shader_out);
2131 nir_remove_dead_variables(ordered_shaders[i - 1],
2132 nir_var_shader_in);
2133
2134 bool progress = nir_remove_unused_varyings(ordered_shaders[i],
2135 ordered_shaders[i - 1]);
2136
2137 nir_compact_varyings(ordered_shaders[i],
2138 ordered_shaders[i - 1], true);
2139
2140 if (progress) {
2141 if (nir_lower_global_vars_to_local(ordered_shaders[i])) {
2142 ac_lower_indirect_derefs(ordered_shaders[i],
2143 pipeline->device->physical_device->rad_info.chip_class);
2144 }
2145 radv_optimize_nir(ordered_shaders[i], false, false);
2146
2147 if (nir_lower_global_vars_to_local(ordered_shaders[i - 1])) {
2148 ac_lower_indirect_derefs(ordered_shaders[i - 1],
2149 pipeline->device->physical_device->rad_info.chip_class);
2150 }
2151 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2152 }
2153 }
2154 }
2155
2156 static uint32_t
2157 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo *input_state,
2158 uint32_t attrib_binding)
2159 {
2160 for (uint32_t i = 0; i < input_state->vertexBindingDescriptionCount; i++) {
2161 const VkVertexInputBindingDescription *input_binding =
2162 &input_state->pVertexBindingDescriptions[i];
2163
2164 if (input_binding->binding == attrib_binding)
2165 return input_binding->stride;
2166 }
2167
2168 return 0;
2169 }
2170
2171 static struct radv_pipeline_key
2172 radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
2173 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2174 const struct radv_blend_state *blend,
2175 bool has_view_index)
2176 {
2177 const VkPipelineVertexInputStateCreateInfo *input_state =
2178 pCreateInfo->pVertexInputState;
2179 const VkPipelineVertexInputDivisorStateCreateInfoEXT *divisor_state =
2180 vk_find_struct_const(input_state->pNext, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT);
2181
2182 struct radv_pipeline_key key;
2183 memset(&key, 0, sizeof(key));
2184
2185 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
2186 key.optimisations_disabled = 1;
2187
2188 key.has_multiview_view_index = has_view_index;
2189
2190 uint32_t binding_input_rate = 0;
2191 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
2192 for (unsigned i = 0; i < input_state->vertexBindingDescriptionCount; ++i) {
2193 if (input_state->pVertexBindingDescriptions[i].inputRate) {
2194 unsigned binding = input_state->pVertexBindingDescriptions[i].binding;
2195 binding_input_rate |= 1u << binding;
2196 instance_rate_divisors[binding] = 1;
2197 }
2198 }
2199 if (divisor_state) {
2200 for (unsigned i = 0; i < divisor_state->vertexBindingDivisorCount; ++i) {
2201 instance_rate_divisors[divisor_state->pVertexBindingDivisors[i].binding] =
2202 divisor_state->pVertexBindingDivisors[i].divisor;
2203 }
2204 }
2205
2206 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
2207 const VkVertexInputAttributeDescription *desc =
2208 &input_state->pVertexAttributeDescriptions[i];
2209 const struct vk_format_description *format_desc;
2210 unsigned location = desc->location;
2211 unsigned binding = desc->binding;
2212 unsigned num_format, data_format;
2213 int first_non_void;
2214
2215 if (binding_input_rate & (1u << binding)) {
2216 key.instance_rate_inputs |= 1u << location;
2217 key.instance_rate_divisors[location] = instance_rate_divisors[binding];
2218 }
2219
2220 format_desc = vk_format_description(desc->format);
2221 first_non_void = vk_format_get_first_non_void_channel(desc->format);
2222
2223 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
2224 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
2225
2226 key.vertex_attribute_formats[location] = data_format | (num_format << 4);
2227 key.vertex_attribute_bindings[location] = desc->binding;
2228 key.vertex_attribute_offsets[location] = desc->offset;
2229 key.vertex_attribute_strides[location] = radv_get_attrib_stride(input_state, desc->binding);
2230
2231 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8 &&
2232 pipeline->device->physical_device->rad_info.family != CHIP_STONEY) {
2233 VkFormat format = input_state->pVertexAttributeDescriptions[i].format;
2234 uint64_t adjust;
2235 switch(format) {
2236 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2237 case VK_FORMAT_A2B10G10R10_SNORM_PACK32:
2238 adjust = RADV_ALPHA_ADJUST_SNORM;
2239 break;
2240 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2241 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32:
2242 adjust = RADV_ALPHA_ADJUST_SSCALED;
2243 break;
2244 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2245 case VK_FORMAT_A2B10G10R10_SINT_PACK32:
2246 adjust = RADV_ALPHA_ADJUST_SINT;
2247 break;
2248 default:
2249 adjust = 0;
2250 break;
2251 }
2252 key.vertex_alpha_adjust |= adjust << (2 * location);
2253 }
2254
2255 switch (desc->format) {
2256 case VK_FORMAT_B8G8R8A8_UNORM:
2257 case VK_FORMAT_B8G8R8A8_SNORM:
2258 case VK_FORMAT_B8G8R8A8_USCALED:
2259 case VK_FORMAT_B8G8R8A8_SSCALED:
2260 case VK_FORMAT_B8G8R8A8_UINT:
2261 case VK_FORMAT_B8G8R8A8_SINT:
2262 case VK_FORMAT_B8G8R8A8_SRGB:
2263 case VK_FORMAT_A2R10G10B10_UNORM_PACK32:
2264 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2265 case VK_FORMAT_A2R10G10B10_USCALED_PACK32:
2266 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2267 case VK_FORMAT_A2R10G10B10_UINT_PACK32:
2268 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2269 key.vertex_post_shuffle |= 1 << location;
2270 break;
2271 default:
2272 break;
2273 }
2274 }
2275
2276 if (pCreateInfo->pTessellationState)
2277 key.tess_input_vertices = pCreateInfo->pTessellationState->patchControlPoints;
2278
2279 const VkPipelineMultisampleStateCreateInfo *vkms =
2280 radv_pipeline_get_multisample_state(pCreateInfo);
2281 if (vkms && vkms->rasterizationSamples > 1) {
2282 uint32_t num_samples = vkms->rasterizationSamples;
2283 uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(vkms);
2284 key.num_samples = num_samples;
2285 key.log2_ps_iter_samples = util_logbase2(ps_iter_samples);
2286 }
2287
2288 key.col_format = blend->spi_shader_col_format;
2289 if (pipeline->device->physical_device->rad_info.chip_class < GFX8)
2290 radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.is_int8, &key.is_int10);
2291
2292 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10)
2293 key.topology = pCreateInfo->pInputAssemblyState->topology;
2294
2295 return key;
2296 }
2297
2298 static bool
2299 radv_nir_stage_uses_xfb(const nir_shader *nir)
2300 {
2301 nir_xfb_info *xfb = nir_gather_xfb_info(nir, NULL);
2302 bool uses_xfb = !!xfb;
2303
2304 ralloc_free(xfb);
2305 return uses_xfb;
2306 }
2307
2308 static void
2309 radv_fill_shader_keys(struct radv_device *device,
2310 struct radv_shader_variant_key *keys,
2311 const struct radv_pipeline_key *key,
2312 nir_shader **nir)
2313 {
2314 keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
2315 keys[MESA_SHADER_VERTEX].vs.alpha_adjust = key->vertex_alpha_adjust;
2316 keys[MESA_SHADER_VERTEX].vs.post_shuffle = key->vertex_post_shuffle;
2317 for (unsigned i = 0; i < MAX_VERTEX_ATTRIBS; ++i) {
2318 keys[MESA_SHADER_VERTEX].vs.instance_rate_divisors[i] = key->instance_rate_divisors[i];
2319 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_formats[i] = key->vertex_attribute_formats[i];
2320 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_bindings[i] = key->vertex_attribute_bindings[i];
2321 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_offsets[i] = key->vertex_attribute_offsets[i];
2322 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_strides[i] = key->vertex_attribute_strides[i];
2323 }
2324 keys[MESA_SHADER_VERTEX].vs.outprim = si_conv_prim_to_gs_out(key->topology);
2325
2326 if (nir[MESA_SHADER_TESS_CTRL]) {
2327 keys[MESA_SHADER_VERTEX].vs_common_out.as_ls = true;
2328 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = 0;
2329 keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices;
2330 keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
2331
2332 keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
2333 }
2334
2335 if (nir[MESA_SHADER_GEOMETRY]) {
2336 if (nir[MESA_SHADER_TESS_CTRL])
2337 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_es = true;
2338 else
2339 keys[MESA_SHADER_VERTEX].vs_common_out.as_es = true;
2340 }
2341
2342 if (device->physical_device->use_ngg) {
2343 if (nir[MESA_SHADER_TESS_CTRL]) {
2344 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = true;
2345 } else {
2346 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = true;
2347 }
2348
2349 if (nir[MESA_SHADER_TESS_CTRL] &&
2350 nir[MESA_SHADER_GEOMETRY] &&
2351 nir[MESA_SHADER_GEOMETRY]->info.gs.invocations *
2352 nir[MESA_SHADER_GEOMETRY]->info.gs.vertices_out > 256) {
2353 /* Fallback to the legacy path if tessellation is
2354 * enabled with extreme geometry because
2355 * EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it
2356 * might hang.
2357 */
2358 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2359 }
2360
2361 /*
2362 * Disable NGG with geometry shaders. There are a bunch of
2363 * issues still:
2364 * * GS primitives in pipeline statistic queries do not get
2365 * updates. See dEQP-VK.query_pool.statistics_query.geometry_shader_primitives
2366 *
2367 * Furthermore, XGL/AMDVLK also disables this as of 9b632ef.
2368 */
2369 if (nir[MESA_SHADER_GEOMETRY]) {
2370 if (nir[MESA_SHADER_TESS_CTRL])
2371 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2372 else
2373 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2374 }
2375
2376 if (!device->physical_device->use_ngg_streamout) {
2377 gl_shader_stage last_xfb_stage = MESA_SHADER_VERTEX;
2378
2379 for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
2380 if (nir[i])
2381 last_xfb_stage = i;
2382 }
2383
2384 if (nir[last_xfb_stage] &&
2385 radv_nir_stage_uses_xfb(nir[last_xfb_stage])) {
2386 if (nir[MESA_SHADER_TESS_CTRL])
2387 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2388 else
2389 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2390 }
2391 }
2392 }
2393
2394 for(int i = 0; i < MESA_SHADER_STAGES; ++i)
2395 keys[i].has_multiview_view_index = key->has_multiview_view_index;
2396
2397 keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format;
2398 keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8;
2399 keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
2400 keys[MESA_SHADER_FRAGMENT].fs.log2_ps_iter_samples = key->log2_ps_iter_samples;
2401 keys[MESA_SHADER_FRAGMENT].fs.num_samples = key->num_samples;
2402
2403 if (nir[MESA_SHADER_COMPUTE]) {
2404 keys[MESA_SHADER_COMPUTE].cs.subgroup_size = key->compute_subgroup_size;
2405 }
2406 }
2407
2408 static uint8_t
2409 radv_get_wave_size(struct radv_device *device,
2410 const VkPipelineShaderStageCreateInfo *pStage,
2411 gl_shader_stage stage,
2412 const struct radv_shader_variant_key *key)
2413 {
2414 if (stage == MESA_SHADER_GEOMETRY && !key->vs_common_out.as_ngg)
2415 return 64;
2416 else if (stage == MESA_SHADER_COMPUTE) {
2417 if (key->cs.subgroup_size) {
2418 /* Return the required subgroup size if specified. */
2419 return key->cs.subgroup_size;
2420 }
2421 return device->physical_device->cs_wave_size;
2422 }
2423 else if (stage == MESA_SHADER_FRAGMENT)
2424 return device->physical_device->ps_wave_size;
2425 else
2426 return device->physical_device->ge_wave_size;
2427 }
2428
2429 static void
2430 radv_fill_shader_info(struct radv_pipeline *pipeline,
2431 const VkPipelineShaderStageCreateInfo **pStages,
2432 struct radv_shader_variant_key *keys,
2433 struct radv_shader_info *infos,
2434 nir_shader **nir)
2435 {
2436 unsigned active_stages = 0;
2437 unsigned filled_stages = 0;
2438
2439 for (int i = 0; i < MESA_SHADER_STAGES; i++) {
2440 if (nir[i])
2441 active_stages |= (1 << i);
2442 }
2443
2444 if (nir[MESA_SHADER_FRAGMENT]) {
2445 radv_nir_shader_info_init(&infos[MESA_SHADER_FRAGMENT]);
2446 radv_nir_shader_info_pass(nir[MESA_SHADER_FRAGMENT],
2447 pipeline->layout,
2448 &keys[MESA_SHADER_FRAGMENT],
2449 &infos[MESA_SHADER_FRAGMENT]);
2450
2451 /* TODO: These are no longer used as keys we should refactor this */
2452 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id =
2453 infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
2454 keys[MESA_SHADER_VERTEX].vs_common_out.export_layer_id =
2455 infos[MESA_SHADER_FRAGMENT].ps.layer_input;
2456 keys[MESA_SHADER_VERTEX].vs_common_out.export_clip_dists =
2457 !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
2458 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_prim_id =
2459 infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
2460 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_layer_id =
2461 infos[MESA_SHADER_FRAGMENT].ps.layer_input;
2462 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_clip_dists =
2463 !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
2464
2465 filled_stages |= (1 << MESA_SHADER_FRAGMENT);
2466 }
2467
2468 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
2469 nir[MESA_SHADER_TESS_CTRL]) {
2470 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2471 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2472 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2473
2474 radv_nir_shader_info_init(&infos[MESA_SHADER_TESS_CTRL]);
2475
2476 for (int i = 0; i < 2; i++) {
2477 radv_nir_shader_info_pass(combined_nir[i],
2478 pipeline->layout, &key,
2479 &infos[MESA_SHADER_TESS_CTRL]);
2480 }
2481
2482 keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
2483 infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
2484 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs =
2485 util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written);
2486
2487 filled_stages |= (1 << MESA_SHADER_VERTEX);
2488 filled_stages |= (1 << MESA_SHADER_TESS_CTRL);
2489 }
2490
2491 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
2492 nir[MESA_SHADER_GEOMETRY]) {
2493 gl_shader_stage pre_stage = nir[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2494 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2495
2496 radv_nir_shader_info_init(&infos[MESA_SHADER_GEOMETRY]);
2497
2498 for (int i = 0; i < 2; i++) {
2499 radv_nir_shader_info_pass(combined_nir[i],
2500 pipeline->layout,
2501 &keys[pre_stage],
2502 &infos[MESA_SHADER_GEOMETRY]);
2503 }
2504
2505 filled_stages |= (1 << pre_stage);
2506 filled_stages |= (1 << MESA_SHADER_GEOMETRY);
2507 }
2508
2509 active_stages ^= filled_stages;
2510 while (active_stages) {
2511 int i = u_bit_scan(&active_stages);
2512
2513 if (i == MESA_SHADER_TESS_CTRL) {
2514 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs =
2515 util_last_bit64(infos[MESA_SHADER_VERTEX].vs.ls_outputs_written);
2516 }
2517
2518 if (i == MESA_SHADER_TESS_EVAL) {
2519 keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
2520 infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
2521 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs =
2522 util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written);
2523 }
2524
2525 radv_nir_shader_info_init(&infos[i]);
2526 radv_nir_shader_info_pass(nir[i], pipeline->layout,
2527 &keys[i], &infos[i]);
2528 }
2529
2530 for (int i = 0; i < MESA_SHADER_STAGES; i++) {
2531 if (nir[i])
2532 infos[i].wave_size =
2533 radv_get_wave_size(pipeline->device, pStages[i],
2534 i, &keys[i]);
2535 }
2536 }
2537
2538 static void
2539 merge_tess_info(struct shader_info *tes_info,
2540 const struct shader_info *tcs_info)
2541 {
2542 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2543 *
2544 * "PointMode. Controls generation of points rather than triangles
2545 * or lines. This functionality defaults to disabled, and is
2546 * enabled if either shader stage includes the execution mode.
2547 *
2548 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2549 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2550 * and OutputVertices, it says:
2551 *
2552 * "One mode must be set in at least one of the tessellation
2553 * shader stages."
2554 *
2555 * So, the fields can be set in either the TCS or TES, but they must
2556 * agree if set in both. Our backend looks at TES, so bitwise-or in
2557 * the values from the TCS.
2558 */
2559 assert(tcs_info->tess.tcs_vertices_out == 0 ||
2560 tes_info->tess.tcs_vertices_out == 0 ||
2561 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
2562 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
2563
2564 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2565 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2566 tcs_info->tess.spacing == tes_info->tess.spacing);
2567 tes_info->tess.spacing |= tcs_info->tess.spacing;
2568
2569 assert(tcs_info->tess.primitive_mode == 0 ||
2570 tes_info->tess.primitive_mode == 0 ||
2571 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
2572 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
2573 tes_info->tess.ccw |= tcs_info->tess.ccw;
2574 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
2575 }
2576
2577 static
2578 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT *ext)
2579 {
2580 if (!ext)
2581 return;
2582
2583 if (ext->pPipelineCreationFeedback) {
2584 ext->pPipelineCreationFeedback->flags = 0;
2585 ext->pPipelineCreationFeedback->duration = 0;
2586 }
2587
2588 for (unsigned i = 0; i < ext->pipelineStageCreationFeedbackCount; ++i) {
2589 ext->pPipelineStageCreationFeedbacks[i].flags = 0;
2590 ext->pPipelineStageCreationFeedbacks[i].duration = 0;
2591 }
2592 }
2593
2594 static
2595 void radv_start_feedback(VkPipelineCreationFeedbackEXT *feedback)
2596 {
2597 if (!feedback)
2598 return;
2599
2600 feedback->duration -= radv_get_current_time();
2601 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT;
2602 }
2603
2604 static
2605 void radv_stop_feedback(VkPipelineCreationFeedbackEXT *feedback, bool cache_hit)
2606 {
2607 if (!feedback)
2608 return;
2609
2610 feedback->duration += radv_get_current_time();
2611 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT |
2612 (cache_hit ? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT : 0);
2613 }
2614
2615 static
2616 bool radv_aco_supported_stage(gl_shader_stage stage, bool has_gs, bool has_ts)
2617 {
2618 return (stage == MESA_SHADER_VERTEX && !has_gs && !has_ts) ||
2619 stage == MESA_SHADER_FRAGMENT ||
2620 stage == MESA_SHADER_COMPUTE;
2621 }
2622
2623 void radv_create_shaders(struct radv_pipeline *pipeline,
2624 struct radv_device *device,
2625 struct radv_pipeline_cache *cache,
2626 const struct radv_pipeline_key *key,
2627 const VkPipelineShaderStageCreateInfo **pStages,
2628 const VkPipelineCreateFlags flags,
2629 VkPipelineCreationFeedbackEXT *pipeline_feedback,
2630 VkPipelineCreationFeedbackEXT **stage_feedbacks)
2631 {
2632 struct radv_shader_module fs_m = {0};
2633 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
2634 nir_shader *nir[MESA_SHADER_STAGES] = {0};
2635 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2636 struct radv_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{{0}}}}};
2637 struct radv_shader_info infos[MESA_SHADER_STAGES] = {0};
2638 unsigned char hash[20], gs_copy_hash[20];
2639 bool keep_executable_info = (flags & VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR) || device->keep_shader_info;
2640
2641 radv_start_feedback(pipeline_feedback);
2642
2643 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2644 if (pStages[i]) {
2645 modules[i] = radv_shader_module_from_handle(pStages[i]->module);
2646 if (modules[i]->nir)
2647 _mesa_sha1_compute(modules[i]->nir->info.name,
2648 strlen(modules[i]->nir->info.name),
2649 modules[i]->sha1);
2650
2651 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
2652 }
2653 }
2654
2655 radv_hash_shaders(hash, pStages, pipeline->layout, key, get_hash_flags(device));
2656 memcpy(gs_copy_hash, hash, 20);
2657 gs_copy_hash[0] ^= 1;
2658
2659 bool found_in_application_cache = true;
2660 if (modules[MESA_SHADER_GEOMETRY] && !keep_executable_info) {
2661 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2662 radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants,
2663 &found_in_application_cache);
2664 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
2665 }
2666
2667 if (!keep_executable_info &&
2668 radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders,
2669 &found_in_application_cache) &&
2670 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
2671 radv_stop_feedback(pipeline_feedback, found_in_application_cache);
2672 return;
2673 }
2674
2675 if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
2676 nir_builder fs_b;
2677 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
2678 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
2679 fs_m.nir = fs_b.shader;
2680 modules[MESA_SHADER_FRAGMENT] = &fs_m;
2681 }
2682
2683 bool has_gs = modules[MESA_SHADER_GEOMETRY];
2684 bool has_ts = modules[MESA_SHADER_TESS_CTRL] || modules[MESA_SHADER_TESS_EVAL];
2685 bool use_aco = device->physical_device->use_aco;
2686
2687 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2688 const VkPipelineShaderStageCreateInfo *stage = pStages[i];
2689
2690 if (!modules[i])
2691 continue;
2692
2693 radv_start_feedback(stage_feedbacks[i]);
2694
2695 bool aco = use_aco && radv_aco_supported_stage(i, has_gs, has_ts);
2696 nir[i] = radv_shader_compile_to_nir(device, modules[i],
2697 stage ? stage->pName : "main", i,
2698 stage ? stage->pSpecializationInfo : NULL,
2699 flags, pipeline->layout, aco);
2700
2701 /* We don't want to alter meta shaders IR directly so clone it
2702 * first.
2703 */
2704 if (nir[i]->info.name) {
2705 nir[i] = nir_shader_clone(NULL, nir[i]);
2706 }
2707
2708 radv_stop_feedback(stage_feedbacks[i], false);
2709 }
2710
2711 if (nir[MESA_SHADER_TESS_CTRL]) {
2712 nir_lower_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out, NULL);
2713 merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
2714 }
2715
2716 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
2717 radv_link_shaders(pipeline, nir);
2718
2719 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2720 if (nir[i]) {
2721 NIR_PASS_V(nir[i], nir_lower_non_uniform_access,
2722 nir_lower_non_uniform_ubo_access |
2723 nir_lower_non_uniform_ssbo_access |
2724 nir_lower_non_uniform_texture_access |
2725 nir_lower_non_uniform_image_access);
2726
2727 bool aco = use_aco && radv_aco_supported_stage(i, has_gs, has_ts);
2728 if (!aco)
2729 NIR_PASS_V(nir[i], nir_lower_bool_to_int32);
2730 }
2731
2732 if (radv_can_dump_shader(device, modules[i], false))
2733 nir_print_shader(nir[i], stderr);
2734 }
2735
2736 if (nir[MESA_SHADER_FRAGMENT])
2737 radv_lower_fs_io(nir[MESA_SHADER_FRAGMENT]);
2738
2739 radv_fill_shader_keys(device, keys, key, nir);
2740
2741 radv_fill_shader_info(pipeline, pStages, keys, infos, nir);
2742
2743 if ((nir[MESA_SHADER_VERTEX] &&
2744 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg) ||
2745 (nir[MESA_SHADER_TESS_EVAL] &&
2746 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg)) {
2747 struct gfx10_ngg_info *ngg_info;
2748
2749 if (nir[MESA_SHADER_GEOMETRY])
2750 ngg_info = &infos[MESA_SHADER_GEOMETRY].ngg_info;
2751 else if (nir[MESA_SHADER_TESS_CTRL])
2752 ngg_info = &infos[MESA_SHADER_TESS_EVAL].ngg_info;
2753 else
2754 ngg_info = &infos[MESA_SHADER_VERTEX].ngg_info;
2755
2756 gfx10_get_ngg_info(key, pipeline, nir, infos, ngg_info);
2757 } else if (nir[MESA_SHADER_GEOMETRY]) {
2758 struct gfx9_gs_info *gs_info =
2759 &infos[MESA_SHADER_GEOMETRY].gs_ring_info;
2760
2761 gfx9_get_gs_info(key, pipeline, nir, infos, gs_info);
2762 }
2763
2764 if (nir[MESA_SHADER_FRAGMENT]) {
2765 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
2766 radv_start_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT]);
2767
2768 bool aco = use_aco && radv_aco_supported_stage(MESA_SHADER_FRAGMENT, has_gs, has_ts);
2769 pipeline->shaders[MESA_SHADER_FRAGMENT] =
2770 radv_shader_variant_compile(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
2771 pipeline->layout, keys + MESA_SHADER_FRAGMENT,
2772 infos + MESA_SHADER_FRAGMENT,
2773 keep_executable_info, aco,
2774 &binaries[MESA_SHADER_FRAGMENT]);
2775
2776 radv_stop_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT], false);
2777 }
2778
2779 /* TODO: These are no longer used as keys we should refactor this */
2780 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id =
2781 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.prim_id_input;
2782 keys[MESA_SHADER_VERTEX].vs_common_out.export_layer_id =
2783 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.layer_input;
2784 keys[MESA_SHADER_VERTEX].vs_common_out.export_clip_dists =
2785 !!pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.num_input_clips_culls;
2786 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_prim_id =
2787 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.prim_id_input;
2788 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_layer_id =
2789 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.layer_input;
2790 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_clip_dists =
2791 !!pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.num_input_clips_culls;
2792 }
2793
2794 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
2795 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
2796 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2797 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2798 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2799
2800 radv_start_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL]);
2801
2802 pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_compile(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
2803 pipeline->layout,
2804 &key, &infos[MESA_SHADER_TESS_CTRL], keep_executable_info,
2805 false, &binaries[MESA_SHADER_TESS_CTRL]);
2806
2807 radv_stop_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL], false);
2808 }
2809 modules[MESA_SHADER_VERTEX] = NULL;
2810 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2811 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written);
2812 }
2813
2814 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
2815 gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2816 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
2817 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2818
2819 radv_start_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY]);
2820
2821 pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_compile(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
2822 pipeline->layout,
2823 &keys[pre_stage], &infos[MESA_SHADER_GEOMETRY], keep_executable_info,
2824 false, &binaries[MESA_SHADER_GEOMETRY]);
2825
2826 radv_stop_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY], false);
2827 }
2828 modules[pre_stage] = NULL;
2829 }
2830
2831 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2832 if(modules[i] && !pipeline->shaders[i]) {
2833 if (i == MESA_SHADER_TESS_CTRL) {
2834 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.ls_outputs_written);
2835 }
2836 if (i == MESA_SHADER_TESS_EVAL) {
2837 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2838 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written);
2839 }
2840
2841 radv_start_feedback(stage_feedbacks[i]);
2842
2843 bool aco = use_aco && radv_aco_supported_stage(i, has_gs, has_ts);
2844 pipeline->shaders[i] = radv_shader_variant_compile(device, modules[i], &nir[i], 1,
2845 pipeline->layout,
2846 keys + i, infos + i,keep_executable_info,
2847 aco, &binaries[i]);
2848
2849 radv_stop_feedback(stage_feedbacks[i], false);
2850 }
2851 }
2852
2853 if(modules[MESA_SHADER_GEOMETRY]) {
2854 struct radv_shader_binary *gs_copy_binary = NULL;
2855 if (!pipeline->gs_copy_shader &&
2856 !radv_pipeline_has_ngg(pipeline)) {
2857 struct radv_shader_info info = {};
2858 struct radv_shader_variant_key key = {};
2859
2860 key.has_multiview_view_index =
2861 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index;
2862
2863 radv_nir_shader_info_pass(nir[MESA_SHADER_GEOMETRY],
2864 pipeline->layout, &key,
2865 &info);
2866 info.wave_size = 64; /* Wave32 not supported. */
2867
2868 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
2869 device, nir[MESA_SHADER_GEOMETRY], &info,
2870 &gs_copy_binary, keep_executable_info,
2871 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
2872 }
2873
2874 if (!keep_executable_info && pipeline->gs_copy_shader) {
2875 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2876 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2877
2878 binaries[MESA_SHADER_GEOMETRY] = gs_copy_binary;
2879 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
2880
2881 radv_pipeline_cache_insert_shaders(device, cache,
2882 gs_copy_hash,
2883 variants,
2884 binaries);
2885 }
2886 free(gs_copy_binary);
2887 }
2888
2889 if (!keep_executable_info) {
2890 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
2891 binaries);
2892 }
2893
2894 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2895 free(binaries[i]);
2896 if (nir[i]) {
2897 ralloc_free(nir[i]);
2898
2899 if (radv_can_dump_shader_stats(device, modules[i]))
2900 radv_shader_dump_stats(device,
2901 pipeline->shaders[i],
2902 i, stderr);
2903 }
2904 }
2905
2906 if (fs_m.nir)
2907 ralloc_free(fs_m.nir);
2908
2909 radv_stop_feedback(pipeline_feedback, false);
2910 }
2911
2912 static uint32_t
2913 radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
2914 gl_shader_stage stage, enum chip_class chip_class)
2915 {
2916 bool has_gs = radv_pipeline_has_gs(pipeline);
2917 bool has_tess = radv_pipeline_has_tess(pipeline);
2918 bool has_ngg = radv_pipeline_has_ngg(pipeline);
2919
2920 switch (stage) {
2921 case MESA_SHADER_FRAGMENT:
2922 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
2923 case MESA_SHADER_VERTEX:
2924 if (has_tess) {
2925 if (chip_class >= GFX10) {
2926 return R_00B430_SPI_SHADER_USER_DATA_HS_0;
2927 } else if (chip_class == GFX9) {
2928 return R_00B430_SPI_SHADER_USER_DATA_LS_0;
2929 } else {
2930 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
2931 }
2932
2933 }
2934
2935 if (has_gs) {
2936 if (chip_class >= GFX10) {
2937 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
2938 } else {
2939 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
2940 }
2941 }
2942
2943 if (has_ngg)
2944 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
2945
2946 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
2947 case MESA_SHADER_GEOMETRY:
2948 return chip_class == GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
2949 R_00B230_SPI_SHADER_USER_DATA_GS_0;
2950 case MESA_SHADER_COMPUTE:
2951 return R_00B900_COMPUTE_USER_DATA_0;
2952 case MESA_SHADER_TESS_CTRL:
2953 return chip_class == GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
2954 R_00B430_SPI_SHADER_USER_DATA_HS_0;
2955 case MESA_SHADER_TESS_EVAL:
2956 if (has_gs) {
2957 return chip_class >= GFX10 ? R_00B230_SPI_SHADER_USER_DATA_GS_0 :
2958 R_00B330_SPI_SHADER_USER_DATA_ES_0;
2959 } else if (has_ngg) {
2960 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
2961 } else {
2962 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
2963 }
2964 default:
2965 unreachable("unknown shader");
2966 }
2967 }
2968
2969 struct radv_bin_size_entry {
2970 unsigned bpp;
2971 VkExtent2D extent;
2972 };
2973
2974 static VkExtent2D
2975 radv_gfx9_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
2976 {
2977 static const struct radv_bin_size_entry color_size_table[][3][9] = {
2978 {
2979 /* One RB / SE */
2980 {
2981 /* One shader engine */
2982 { 0, {128, 128}},
2983 { 1, { 64, 128}},
2984 { 2, { 32, 128}},
2985 { 3, { 16, 128}},
2986 { 17, { 0, 0}},
2987 { UINT_MAX, { 0, 0}},
2988 },
2989 {
2990 /* Two shader engines */
2991 { 0, {128, 128}},
2992 { 2, { 64, 128}},
2993 { 3, { 32, 128}},
2994 { 5, { 16, 128}},
2995 { 17, { 0, 0}},
2996 { UINT_MAX, { 0, 0}},
2997 },
2998 {
2999 /* Four shader engines */
3000 { 0, {128, 128}},
3001 { 3, { 64, 128}},
3002 { 5, { 16, 128}},
3003 { 17, { 0, 0}},
3004 { UINT_MAX, { 0, 0}},
3005 },
3006 },
3007 {
3008 /* Two RB / SE */
3009 {
3010 /* One shader engine */
3011 { 0, {128, 128}},
3012 { 2, { 64, 128}},
3013 { 3, { 32, 128}},
3014 { 5, { 16, 128}},
3015 { 33, { 0, 0}},
3016 { UINT_MAX, { 0, 0}},
3017 },
3018 {
3019 /* Two shader engines */
3020 { 0, {128, 128}},
3021 { 3, { 64, 128}},
3022 { 5, { 32, 128}},
3023 { 9, { 16, 128}},
3024 { 33, { 0, 0}},
3025 { UINT_MAX, { 0, 0}},
3026 },
3027 {
3028 /* Four shader engines */
3029 { 0, {256, 256}},
3030 { 2, {128, 256}},
3031 { 3, {128, 128}},
3032 { 5, { 64, 128}},
3033 { 9, { 16, 128}},
3034 { 33, { 0, 0}},
3035 { UINT_MAX, { 0, 0}},
3036 },
3037 },
3038 {
3039 /* Four RB / SE */
3040 {
3041 /* One shader engine */
3042 { 0, {128, 256}},
3043 { 2, {128, 128}},
3044 { 3, { 64, 128}},
3045 { 5, { 32, 128}},
3046 { 9, { 16, 128}},
3047 { 33, { 0, 0}},
3048 { UINT_MAX, { 0, 0}},
3049 },
3050 {
3051 /* Two shader engines */
3052 { 0, {256, 256}},
3053 { 2, {128, 256}},
3054 { 3, {128, 128}},
3055 { 5, { 64, 128}},
3056 { 9, { 32, 128}},
3057 { 17, { 16, 128}},
3058 { 33, { 0, 0}},
3059 { UINT_MAX, { 0, 0}},
3060 },
3061 {
3062 /* Four shader engines */
3063 { 0, {256, 512}},
3064 { 2, {256, 256}},
3065 { 3, {128, 256}},
3066 { 5, {128, 128}},
3067 { 9, { 64, 128}},
3068 { 17, { 16, 128}},
3069 { 33, { 0, 0}},
3070 { UINT_MAX, { 0, 0}},
3071 },
3072 },
3073 };
3074 static const struct radv_bin_size_entry ds_size_table[][3][9] = {
3075 {
3076 // One RB / SE
3077 {
3078 // One shader engine
3079 { 0, {128, 256}},
3080 { 2, {128, 128}},
3081 { 4, { 64, 128}},
3082 { 7, { 32, 128}},
3083 { 13, { 16, 128}},
3084 { 49, { 0, 0}},
3085 { UINT_MAX, { 0, 0}},
3086 },
3087 {
3088 // Two shader engines
3089 { 0, {256, 256}},
3090 { 2, {128, 256}},
3091 { 4, {128, 128}},
3092 { 7, { 64, 128}},
3093 { 13, { 32, 128}},
3094 { 25, { 16, 128}},
3095 { 49, { 0, 0}},
3096 { UINT_MAX, { 0, 0}},
3097 },
3098 {
3099 // Four shader engines
3100 { 0, {256, 512}},
3101 { 2, {256, 256}},
3102 { 4, {128, 256}},
3103 { 7, {128, 128}},
3104 { 13, { 64, 128}},
3105 { 25, { 16, 128}},
3106 { 49, { 0, 0}},
3107 { UINT_MAX, { 0, 0}},
3108 },
3109 },
3110 {
3111 // Two RB / SE
3112 {
3113 // One shader engine
3114 { 0, {256, 256}},
3115 { 2, {128, 256}},
3116 { 4, {128, 128}},
3117 { 7, { 64, 128}},
3118 { 13, { 32, 128}},
3119 { 25, { 16, 128}},
3120 { 97, { 0, 0}},
3121 { UINT_MAX, { 0, 0}},
3122 },
3123 {
3124 // Two shader engines
3125 { 0, {256, 512}},
3126 { 2, {256, 256}},
3127 { 4, {128, 256}},
3128 { 7, {128, 128}},
3129 { 13, { 64, 128}},
3130 { 25, { 32, 128}},
3131 { 49, { 16, 128}},
3132 { 97, { 0, 0}},
3133 { UINT_MAX, { 0, 0}},
3134 },
3135 {
3136 // Four shader engines
3137 { 0, {512, 512}},
3138 { 2, {256, 512}},
3139 { 4, {256, 256}},
3140 { 7, {128, 256}},
3141 { 13, {128, 128}},
3142 { 25, { 64, 128}},
3143 { 49, { 16, 128}},
3144 { 97, { 0, 0}},
3145 { UINT_MAX, { 0, 0}},
3146 },
3147 },
3148 {
3149 // Four RB / SE
3150 {
3151 // One shader engine
3152 { 0, {256, 512}},
3153 { 2, {256, 256}},
3154 { 4, {128, 256}},
3155 { 7, {128, 128}},
3156 { 13, { 64, 128}},
3157 { 25, { 32, 128}},
3158 { 49, { 16, 128}},
3159 { UINT_MAX, { 0, 0}},
3160 },
3161 {
3162 // Two shader engines
3163 { 0, {512, 512}},
3164 { 2, {256, 512}},
3165 { 4, {256, 256}},
3166 { 7, {128, 256}},
3167 { 13, {128, 128}},
3168 { 25, { 64, 128}},
3169 { 49, { 32, 128}},
3170 { 97, { 16, 128}},
3171 { UINT_MAX, { 0, 0}},
3172 },
3173 {
3174 // Four shader engines
3175 { 0, {512, 512}},
3176 { 4, {256, 512}},
3177 { 7, {256, 256}},
3178 { 13, {128, 256}},
3179 { 25, {128, 128}},
3180 { 49, { 64, 128}},
3181 { 97, { 16, 128}},
3182 { UINT_MAX, { 0, 0}},
3183 },
3184 },
3185 };
3186
3187 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3188 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3189 VkExtent2D extent = {512, 512};
3190
3191 unsigned log_num_rb_per_se =
3192 util_logbase2_ceil(pipeline->device->physical_device->rad_info.num_render_backends /
3193 pipeline->device->physical_device->rad_info.max_se);
3194 unsigned log_num_se = util_logbase2_ceil(pipeline->device->physical_device->rad_info.max_se);
3195
3196 unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
3197 unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->graphics.ms.db_eqaa);
3198 unsigned effective_samples = total_samples;
3199 unsigned color_bytes_per_pixel = 0;
3200
3201 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
3202 if (vkblend) {
3203 for (unsigned i = 0; i < subpass->color_count; i++) {
3204 if (!vkblend->pAttachments[i].colorWriteMask)
3205 continue;
3206
3207 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3208 continue;
3209
3210 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3211 color_bytes_per_pixel += vk_format_get_blocksize(format);
3212 }
3213
3214 /* MSAA images typically don't use all samples all the time. */
3215 if (effective_samples >= 2 && ps_iter_samples <= 1)
3216 effective_samples = 2;
3217 color_bytes_per_pixel *= effective_samples;
3218 }
3219
3220 const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se];
3221 while(color_entry[1].bpp <= color_bytes_per_pixel)
3222 ++color_entry;
3223
3224 extent = color_entry->extent;
3225
3226 if (subpass->depth_stencil_attachment) {
3227 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3228
3229 /* Coefficients taken from AMDVLK */
3230 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
3231 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
3232 unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples;
3233
3234 const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se];
3235 while(ds_entry[1].bpp <= ds_bytes_per_pixel)
3236 ++ds_entry;
3237
3238 if (ds_entry->extent.width * ds_entry->extent.height < extent.width * extent.height)
3239 extent = ds_entry->extent;
3240 }
3241
3242 return extent;
3243 }
3244
3245 static VkExtent2D
3246 radv_gfx10_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
3247 {
3248 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3249 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3250 VkExtent2D extent = {512, 512};
3251
3252 const unsigned db_tag_size = 64;
3253 const unsigned db_tag_count = 312;
3254 const unsigned color_tag_size = 1024;
3255 const unsigned color_tag_count = 31;
3256 const unsigned fmask_tag_size = 256;
3257 const unsigned fmask_tag_count = 44;
3258
3259 const unsigned rb_count = pipeline->device->physical_device->rad_info.num_render_backends;
3260 const unsigned pipe_count = MAX2(rb_count, pipeline->device->physical_device->rad_info.num_sdp_interfaces);
3261
3262 const unsigned db_tag_part = (db_tag_count * rb_count / pipe_count) * db_tag_size * pipe_count;
3263 const unsigned color_tag_part = (color_tag_count * rb_count / pipe_count) * color_tag_size * pipe_count;
3264 const unsigned fmask_tag_part = (fmask_tag_count * rb_count / pipe_count) * fmask_tag_size * pipe_count;
3265
3266 const unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
3267 const unsigned samples_log = util_logbase2_ceil(total_samples);
3268
3269 unsigned color_bytes_per_pixel = 0;
3270 unsigned fmask_bytes_per_pixel = 0;
3271
3272 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
3273 if (vkblend) {
3274 for (unsigned i = 0; i < subpass->color_count; i++) {
3275 if (!vkblend->pAttachments[i].colorWriteMask)
3276 continue;
3277
3278 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3279 continue;
3280
3281 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3282 color_bytes_per_pixel += vk_format_get_blocksize(format);
3283
3284 if (total_samples > 1) {
3285 assert(samples_log <= 3);
3286 const unsigned fmask_array[] = {0, 1, 1, 4};
3287 fmask_bytes_per_pixel += fmask_array[samples_log];
3288 }
3289 }
3290
3291 color_bytes_per_pixel *= total_samples;
3292 }
3293 color_bytes_per_pixel = MAX2(color_bytes_per_pixel, 1);
3294
3295 const unsigned color_pixel_count_log = util_logbase2(color_tag_part / color_bytes_per_pixel);
3296 extent.width = 1ull << ((color_pixel_count_log + 1) / 2);
3297 extent.height = 1ull << (color_pixel_count_log / 2);
3298
3299 if (fmask_bytes_per_pixel) {
3300 const unsigned fmask_pixel_count_log = util_logbase2(fmask_tag_part / fmask_bytes_per_pixel);
3301
3302 const VkExtent2D fmask_extent = (VkExtent2D){
3303 .width = 1ull << ((fmask_pixel_count_log + 1) / 2),
3304 .height = 1ull << (color_pixel_count_log / 2)
3305 };
3306
3307 if (fmask_extent.width * fmask_extent.height < extent.width * extent.height)
3308 extent = fmask_extent;
3309 }
3310
3311 if (subpass->depth_stencil_attachment) {
3312 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3313
3314 /* Coefficients taken from AMDVLK */
3315 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
3316 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
3317 unsigned db_bytes_per_pixel = (depth_coeff + stencil_coeff) * total_samples;
3318
3319 const unsigned db_pixel_count_log = util_logbase2(db_tag_part / db_bytes_per_pixel);
3320
3321 const VkExtent2D db_extent = (VkExtent2D){
3322 .width = 1ull << ((db_pixel_count_log + 1) / 2),
3323 .height = 1ull << (color_pixel_count_log / 2)
3324 };
3325
3326 if (db_extent.width * db_extent.height < extent.width * extent.height)
3327 extent = db_extent;
3328 }
3329
3330 extent.width = MAX2(extent.width, 128);
3331 extent.height = MAX2(extent.width, 64);
3332
3333 return extent;
3334 }
3335
3336 static void
3337 radv_pipeline_generate_disabled_binning_state(struct radeon_cmdbuf *ctx_cs,
3338 struct radv_pipeline *pipeline,
3339 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3340 {
3341 uint32_t pa_sc_binner_cntl_0 =
3342 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
3343 S_028C44_DISABLE_START_OF_PRIM(1);
3344 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
3345
3346 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3347 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3348 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3349 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
3350 unsigned min_bytes_per_pixel = 0;
3351
3352 if (vkblend) {
3353 for (unsigned i = 0; i < subpass->color_count; i++) {
3354 if (!vkblend->pAttachments[i].colorWriteMask)
3355 continue;
3356
3357 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3358 continue;
3359
3360 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3361 unsigned bytes = vk_format_get_blocksize(format);
3362 if (!min_bytes_per_pixel || bytes < min_bytes_per_pixel)
3363 min_bytes_per_pixel = bytes;
3364 }
3365 }
3366
3367 pa_sc_binner_cntl_0 =
3368 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC) |
3369 S_028C44_BIN_SIZE_X(0) |
3370 S_028C44_BIN_SIZE_Y(0) |
3371 S_028C44_BIN_SIZE_X_EXTEND(2) | /* 128 */
3372 S_028C44_BIN_SIZE_Y_EXTEND(min_bytes_per_pixel <= 4 ? 2 : 1) | /* 128 or 64 */
3373 S_028C44_DISABLE_START_OF_PRIM(1);
3374 }
3375
3376 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
3377 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
3378 }
3379
3380 static void
3381 radv_pipeline_generate_binning_state(struct radeon_cmdbuf *ctx_cs,
3382 struct radv_pipeline *pipeline,
3383 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3384 const struct radv_blend_state *blend)
3385 {
3386 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
3387 return;
3388
3389 VkExtent2D bin_size;
3390 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3391 bin_size = radv_gfx10_compute_bin_size(pipeline, pCreateInfo);
3392 } else if (pipeline->device->physical_device->rad_info.chip_class == GFX9) {
3393 bin_size = radv_gfx9_compute_bin_size(pipeline, pCreateInfo);
3394 } else
3395 unreachable("Unhandled generation for binning bin size calculation");
3396
3397 if (pipeline->device->pbb_allowed && bin_size.width && bin_size.height) {
3398 unsigned context_states_per_bin; /* allowed range: [1, 6] */
3399 unsigned persistent_states_per_bin; /* allowed range: [1, 32] */
3400 unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */
3401
3402 if (pipeline->device->physical_device->rad_info.has_dedicated_vram) {
3403 context_states_per_bin = 1;
3404 persistent_states_per_bin = 1;
3405 fpovs_per_batch = 63;
3406 } else {
3407 /* The context states are affected by the scissor bug. */
3408 context_states_per_bin = pipeline->device->physical_device->rad_info.has_gfx9_scissor_bug ? 1 : 6;
3409 /* 32 causes hangs for RAVEN. */
3410 persistent_states_per_bin = 16;
3411 fpovs_per_batch = 63;
3412 }
3413
3414 bool disable_start_of_prim = true;
3415 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
3416
3417 const struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3418
3419 if (pipeline->device->dfsm_allowed && ps &&
3420 !ps->info.ps.can_discard &&
3421 !ps->info.ps.writes_memory &&
3422 blend->cb_target_enabled_4bit) {
3423 db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_AUTO);
3424 disable_start_of_prim = (blend->blend_enable_4bit & blend->cb_target_enabled_4bit) != 0;
3425 }
3426
3427 const uint32_t pa_sc_binner_cntl_0 =
3428 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
3429 S_028C44_BIN_SIZE_X(bin_size.width == 16) |
3430 S_028C44_BIN_SIZE_Y(bin_size.height == 16) |
3431 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size.width, 32)) - 5) |
3432 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size.height, 32)) - 5) |
3433 S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin - 1) |
3434 S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin - 1) |
3435 S_028C44_DISABLE_START_OF_PRIM(disable_start_of_prim) |
3436 S_028C44_FPOVS_PER_BATCH(fpovs_per_batch) |
3437 S_028C44_OPTIMAL_BIN_SELECTION(1);
3438
3439 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
3440 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
3441 } else
3442 radv_pipeline_generate_disabled_binning_state(ctx_cs, pipeline, pCreateInfo);
3443 }
3444
3445
3446 static void
3447 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf *ctx_cs,
3448 struct radv_pipeline *pipeline,
3449 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3450 const struct radv_graphics_pipeline_create_info *extra)
3451 {
3452 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
3453 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3454 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3455 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3456 struct radv_render_pass_attachment *attachment = NULL;
3457 uint32_t db_depth_control = 0, db_stencil_control = 0;
3458 uint32_t db_render_control = 0, db_render_override2 = 0;
3459 uint32_t db_render_override = 0;
3460
3461 if (subpass->depth_stencil_attachment)
3462 attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3463
3464 bool has_depth_attachment = attachment && vk_format_is_depth(attachment->format);
3465 bool has_stencil_attachment = attachment && vk_format_is_stencil(attachment->format);
3466
3467 if (vkds && has_depth_attachment) {
3468 db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
3469 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
3470 S_028800_ZFUNC(vkds->depthCompareOp) |
3471 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
3472
3473 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
3474 db_render_override2 |= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment->samples > 2);
3475 }
3476
3477 if (has_stencil_attachment && vkds && vkds->stencilTestEnable) {
3478 db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
3479 db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
3480 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
3481 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
3482 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
3483
3484 db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
3485 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
3486 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
3487 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
3488 }
3489
3490 if (attachment && extra) {
3491 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
3492 db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
3493
3494 db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
3495 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
3496 db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
3497 db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
3498 db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
3499 }
3500
3501 db_render_override |= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3502 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
3503
3504 if (!pCreateInfo->pRasterizationState->depthClampEnable &&
3505 ps->info.ps.writes_z) {
3506 /* From VK_EXT_depth_range_unrestricted spec:
3507 *
3508 * "The behavior described in Primitive Clipping still applies.
3509 * If depth clamping is disabled the depth values are still
3510 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
3511 * depth clamping is enabled the above equation is ignored and
3512 * the depth values are instead clamped to the VkViewport
3513 * minDepth and maxDepth values, which in the case of this
3514 * extension can be outside of the 0.0 to 1.0 range."
3515 */
3516 db_render_override |= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
3517 }
3518
3519 radeon_set_context_reg(ctx_cs, R_028800_DB_DEPTH_CONTROL, db_depth_control);
3520 radeon_set_context_reg(ctx_cs, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
3521
3522 radeon_set_context_reg(ctx_cs, R_028000_DB_RENDER_CONTROL, db_render_control);
3523 radeon_set_context_reg(ctx_cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
3524 radeon_set_context_reg(ctx_cs, R_028010_DB_RENDER_OVERRIDE2, db_render_override2);
3525 }
3526
3527 static void
3528 radv_pipeline_generate_blend_state(struct radeon_cmdbuf *ctx_cs,
3529 struct radv_pipeline *pipeline,
3530 const struct radv_blend_state *blend)
3531 {
3532 radeon_set_context_reg_seq(ctx_cs, R_028780_CB_BLEND0_CONTROL, 8);
3533 radeon_emit_array(ctx_cs, blend->cb_blend_control,
3534 8);
3535 radeon_set_context_reg(ctx_cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control);
3536 radeon_set_context_reg(ctx_cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask);
3537
3538 if (pipeline->device->physical_device->rad_info.has_rbplus) {
3539
3540 radeon_set_context_reg_seq(ctx_cs, R_028760_SX_MRT0_BLEND_OPT, 8);
3541 radeon_emit_array(ctx_cs, blend->sx_mrt_blend_opt, 8);
3542 }
3543
3544 radeon_set_context_reg(ctx_cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
3545
3546 radeon_set_context_reg(ctx_cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
3547 radeon_set_context_reg(ctx_cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
3548
3549 pipeline->graphics.col_format = blend->spi_shader_col_format;
3550 pipeline->graphics.cb_target_mask = blend->cb_target_mask;
3551 }
3552
3553 static const VkConservativeRasterizationModeEXT
3554 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo *pCreateInfo)
3555 {
3556 const VkPipelineRasterizationConservativeStateCreateInfoEXT *conservative_raster =
3557 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT);
3558
3559 if (!conservative_raster)
3560 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT;
3561 return conservative_raster->conservativeRasterizationMode;
3562 }
3563
3564 static void
3565 radv_pipeline_generate_raster_state(struct radeon_cmdbuf *ctx_cs,
3566 struct radv_pipeline *pipeline,
3567 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3568 {
3569 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
3570 const VkConservativeRasterizationModeEXT mode =
3571 radv_get_conservative_raster_mode(vkraster);
3572 uint32_t pa_sc_conservative_rast = S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
3573 bool depth_clip_disable = vkraster->depthClampEnable;
3574
3575 const VkPipelineRasterizationDepthClipStateCreateInfoEXT *depth_clip_state =
3576 vk_find_struct_const(vkraster->pNext, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT);
3577 if (depth_clip_state) {
3578 depth_clip_disable = !depth_clip_state->depthClipEnable;
3579 }
3580
3581 radeon_set_context_reg(ctx_cs, R_028810_PA_CL_CLIP_CNTL,
3582 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
3583 S_028810_ZCLIP_NEAR_DISABLE(depth_clip_disable ? 1 : 0) |
3584 S_028810_ZCLIP_FAR_DISABLE(depth_clip_disable ? 1 : 0) |
3585 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
3586 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
3587
3588 radeon_set_context_reg(ctx_cs, R_0286D4_SPI_INTERP_CONTROL_0,
3589 S_0286D4_FLAT_SHADE_ENA(1) |
3590 S_0286D4_PNT_SPRITE_ENA(1) |
3591 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
3592 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
3593 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
3594 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
3595 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
3596
3597 radeon_set_context_reg(ctx_cs, R_028BE4_PA_SU_VTX_CNTL,
3598 S_028BE4_PIX_CENTER(1) | // TODO verify
3599 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
3600 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
3601
3602 radeon_set_context_reg(ctx_cs, R_028814_PA_SU_SC_MODE_CNTL,
3603 S_028814_FACE(vkraster->frontFace) |
3604 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
3605 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
3606 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
3607 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
3608 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
3609 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
3610 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
3611 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0));
3612
3613 /* Conservative rasterization. */
3614 if (mode != VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT) {
3615 struct radv_multisample_state *ms = &pipeline->graphics.ms;
3616
3617 ms->pa_sc_aa_config |= S_028BE0_AA_MASK_CENTROID_DTMN(1);
3618 ms->db_eqaa |= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
3619 S_028804_OVERRASTERIZATION_AMOUNT(4);
3620
3621 pa_sc_conservative_rast = S_028C4C_PREZ_AA_MASK_ENABLE(1) |
3622 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
3623 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
3624
3625 if (mode == VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT) {
3626 pa_sc_conservative_rast |=
3627 S_028C4C_OVER_RAST_ENABLE(1) |
3628 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
3629 S_028C4C_UNDER_RAST_ENABLE(0) |
3630 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
3631 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
3632 } else {
3633 assert(mode == VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT);
3634 pa_sc_conservative_rast |=
3635 S_028C4C_OVER_RAST_ENABLE(0) |
3636 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
3637 S_028C4C_UNDER_RAST_ENABLE(1) |
3638 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
3639 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
3640 }
3641 }
3642
3643 radeon_set_context_reg(ctx_cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
3644 pa_sc_conservative_rast);
3645 }
3646
3647
3648 static void
3649 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf *ctx_cs,
3650 struct radv_pipeline *pipeline)
3651 {
3652 struct radv_multisample_state *ms = &pipeline->graphics.ms;
3653
3654 radeon_set_context_reg_seq(ctx_cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3655 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[0]);
3656 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[1]);
3657
3658 radeon_set_context_reg(ctx_cs, R_028804_DB_EQAA, ms->db_eqaa);
3659 radeon_set_context_reg(ctx_cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
3660 radeon_set_context_reg(ctx_cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
3661 radeon_set_context_reg(ctx_cs, R_028BDC_PA_SC_LINE_CNTL, ms->pa_sc_line_cntl);
3662 radeon_set_context_reg(ctx_cs, R_028BE0_PA_SC_AA_CONFIG, ms->pa_sc_aa_config);
3663
3664 /* The exclusion bits can be set to improve rasterization efficiency
3665 * if no sample lies on the pixel boundary (-8 sample offset). It's
3666 * currently always TRUE because the driver doesn't support 16 samples.
3667 */
3668 bool exclusion = pipeline->device->physical_device->rad_info.chip_class >= GFX7;
3669 radeon_set_context_reg(ctx_cs, R_02882C_PA_SU_PRIM_FILTER_CNTL,
3670 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
3671 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
3672
3673 /* GFX9: Flush DFSM when the AA mode changes. */
3674 if (pipeline->device->dfsm_allowed) {
3675 radeon_emit(ctx_cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3676 radeon_emit(ctx_cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3677 }
3678 }
3679
3680 static void
3681 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf *ctx_cs,
3682 struct radv_pipeline *pipeline)
3683 {
3684 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3685 const struct radv_shader_variant *vs =
3686 pipeline->shaders[MESA_SHADER_TESS_EVAL] ?
3687 pipeline->shaders[MESA_SHADER_TESS_EVAL] :
3688 pipeline->shaders[MESA_SHADER_VERTEX];
3689 unsigned vgt_primitiveid_en = 0;
3690 uint32_t vgt_gs_mode = 0;
3691
3692 if (radv_pipeline_has_ngg(pipeline))
3693 return;
3694
3695 if (radv_pipeline_has_gs(pipeline)) {
3696 const struct radv_shader_variant *gs =
3697 pipeline->shaders[MESA_SHADER_GEOMETRY];
3698
3699 vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out,
3700 pipeline->device->physical_device->rad_info.chip_class);
3701 } else if (outinfo->export_prim_id || vs->info.uses_prim_id) {
3702 vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
3703 vgt_primitiveid_en |= S_028A84_PRIMITIVEID_EN(1);
3704 }
3705
3706 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN, vgt_primitiveid_en);
3707 radeon_set_context_reg(ctx_cs, R_028A40_VGT_GS_MODE, vgt_gs_mode);
3708 }
3709
3710 static void
3711 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs,
3712 struct radeon_cmdbuf *cs,
3713 struct radv_pipeline *pipeline,
3714 struct radv_shader_variant *shader)
3715 {
3716 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3717
3718 radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
3719 radeon_emit(cs, va >> 8);
3720 radeon_emit(cs, S_00B124_MEM_BASE(va >> 40));
3721 radeon_emit(cs, shader->config.rsrc1);
3722 radeon_emit(cs, shader->config.rsrc2);
3723
3724 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3725 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3726 clip_dist_mask = outinfo->clip_dist_mask;
3727 cull_dist_mask = outinfo->cull_dist_mask;
3728 total_mask = clip_dist_mask | cull_dist_mask;
3729 bool misc_vec_ena = outinfo->writes_pointsize ||
3730 outinfo->writes_layer ||
3731 outinfo->writes_viewport_index;
3732 unsigned spi_vs_out_config, nparams;
3733
3734 /* VS is required to export at least one param. */
3735 nparams = MAX2(outinfo->param_exports, 1);
3736 spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
3737
3738 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3739 spi_vs_out_config |= S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0);
3740 }
3741
3742 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG, spi_vs_out_config);
3743
3744 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
3745 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
3746 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
3747 V_02870C_SPI_SHADER_4COMP :
3748 V_02870C_SPI_SHADER_NONE) |
3749 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
3750 V_02870C_SPI_SHADER_4COMP :
3751 V_02870C_SPI_SHADER_NONE) |
3752 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
3753 V_02870C_SPI_SHADER_4COMP :
3754 V_02870C_SPI_SHADER_NONE));
3755
3756 radeon_set_context_reg(ctx_cs, R_028818_PA_CL_VTE_CNTL,
3757 S_028818_VTX_W0_FMT(1) |
3758 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3759 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3760 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3761
3762 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
3763 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
3764 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
3765 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
3766 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
3767 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
3768 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
3769 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
3770 cull_dist_mask << 8 |
3771 clip_dist_mask);
3772
3773 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
3774 radeon_set_context_reg(ctx_cs, R_028AB4_VGT_REUSE_OFF,
3775 outinfo->writes_viewport_index);
3776 }
3777
3778 static void
3779 radv_pipeline_generate_hw_es(struct radeon_cmdbuf *cs,
3780 struct radv_pipeline *pipeline,
3781 struct radv_shader_variant *shader)
3782 {
3783 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3784
3785 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
3786 radeon_emit(cs, va >> 8);
3787 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3788 radeon_emit(cs, shader->config.rsrc1);
3789 radeon_emit(cs, shader->config.rsrc2);
3790 }
3791
3792 static void
3793 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf *cs,
3794 struct radv_pipeline *pipeline,
3795 struct radv_shader_variant *shader,
3796 const struct radv_tessellation_state *tess)
3797 {
3798 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3799 uint32_t rsrc2 = shader->config.rsrc2;
3800
3801 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
3802 radeon_emit(cs, va >> 8);
3803 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
3804
3805 rsrc2 |= S_00B52C_LDS_SIZE(tess->lds_size);
3806 if (pipeline->device->physical_device->rad_info.chip_class == GFX7 &&
3807 pipeline->device->physical_device->rad_info.family != CHIP_HAWAII)
3808 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
3809
3810 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
3811 radeon_emit(cs, shader->config.rsrc1);
3812 radeon_emit(cs, rsrc2);
3813 }
3814
3815 static void
3816 radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs,
3817 struct radeon_cmdbuf *cs,
3818 struct radv_pipeline *pipeline,
3819 struct radv_shader_variant *shader)
3820 {
3821 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3822 gl_shader_stage es_type =
3823 radv_pipeline_has_tess(pipeline) ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
3824 struct radv_shader_variant *es =
3825 es_type == MESA_SHADER_TESS_EVAL ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX];
3826 const struct gfx10_ngg_info *ngg_state = &shader->info.ngg_info;
3827
3828 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
3829 radeon_emit(cs, va >> 8);
3830 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3831 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
3832 radeon_emit(cs, shader->config.rsrc1);
3833 radeon_emit(cs, shader->config.rsrc2);
3834
3835 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3836 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3837 clip_dist_mask = outinfo->clip_dist_mask;
3838 cull_dist_mask = outinfo->cull_dist_mask;
3839 total_mask = clip_dist_mask | cull_dist_mask;
3840 bool misc_vec_ena = outinfo->writes_pointsize ||
3841 outinfo->writes_layer ||
3842 outinfo->writes_viewport_index;
3843 bool es_enable_prim_id = outinfo->export_prim_id ||
3844 (es && es->info.uses_prim_id);
3845 bool break_wave_at_eoi = false;
3846 unsigned ge_cntl;
3847 unsigned nparams;
3848
3849 if (es_type == MESA_SHADER_TESS_EVAL) {
3850 struct radv_shader_variant *gs =
3851 pipeline->shaders[MESA_SHADER_GEOMETRY];
3852
3853 if (es_enable_prim_id || (gs && gs->info.uses_prim_id))
3854 break_wave_at_eoi = true;
3855 }
3856
3857 nparams = MAX2(outinfo->param_exports, 1);
3858 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG,
3859 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
3860 S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0));
3861
3862 radeon_set_context_reg(ctx_cs, R_028708_SPI_SHADER_IDX_FORMAT,
3863 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP));
3864 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
3865 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
3866 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
3867 V_02870C_SPI_SHADER_4COMP :
3868 V_02870C_SPI_SHADER_NONE) |
3869 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
3870 V_02870C_SPI_SHADER_4COMP :
3871 V_02870C_SPI_SHADER_NONE) |
3872 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
3873 V_02870C_SPI_SHADER_4COMP :
3874 V_02870C_SPI_SHADER_NONE));
3875
3876 radeon_set_context_reg(ctx_cs, R_028818_PA_CL_VTE_CNTL,
3877 S_028818_VTX_W0_FMT(1) |
3878 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3879 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3880 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3881 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
3882 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
3883 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
3884 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
3885 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
3886 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
3887 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
3888 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
3889 cull_dist_mask << 8 |
3890 clip_dist_mask);
3891
3892 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN,
3893 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
3894 S_028A84_NGG_DISABLE_PROVOK_REUSE(es_enable_prim_id));
3895
3896 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
3897 ngg_state->vgt_esgs_ring_itemsize);
3898
3899 /* NGG specific registers. */
3900 struct radv_shader_variant *gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
3901 uint32_t gs_num_invocations = gs ? gs->info.gs.invocations : 1;
3902
3903 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
3904 S_028A44_ES_VERTS_PER_SUBGRP(ngg_state->hw_max_esverts) |
3905 S_028A44_GS_PRIMS_PER_SUBGRP(ngg_state->max_gsprims) |
3906 S_028A44_GS_INST_PRIMS_IN_SUBGRP(ngg_state->max_gsprims * gs_num_invocations));
3907 radeon_set_context_reg(ctx_cs, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
3908 S_0287FC_MAX_VERTS_PER_SUBGROUP(ngg_state->max_out_verts));
3909 radeon_set_context_reg(ctx_cs, R_028B4C_GE_NGG_SUBGRP_CNTL,
3910 S_028B4C_PRIM_AMP_FACTOR(ngg_state->prim_amp_factor) |
3911 S_028B4C_THDS_PER_SUBGRP(0)); /* for fast launch */
3912 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
3913 S_028B90_CNT(gs_num_invocations) |
3914 S_028B90_ENABLE(gs_num_invocations > 1) |
3915 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(ngg_state->max_vert_out_per_gs_instance));
3916
3917 /* User edge flags are set by the pos exports. If user edge flags are
3918 * not used, we must use hw-generated edge flags and pass them via
3919 * the prim export to prevent drawing lines on internal edges of
3920 * decomposed primitives (such as quads) with polygon mode = lines.
3921 *
3922 * TODO: We should combine hw-generated edge flags with user edge
3923 * flags in the shader.
3924 */
3925 radeon_set_context_reg(ctx_cs, R_028838_PA_CL_NGG_CNTL,
3926 S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline) &&
3927 !radv_pipeline_has_gs(pipeline)));
3928
3929 ge_cntl = S_03096C_PRIM_GRP_SIZE(ngg_state->max_gsprims) |
3930 S_03096C_VERT_GRP_SIZE(ngg_state->hw_max_esverts) |
3931 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
3932
3933 /* Bug workaround for a possible hang with non-tessellation cases.
3934 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
3935 *
3936 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
3937 */
3938 if ((pipeline->device->physical_device->rad_info.family == CHIP_NAVI10 ||
3939 pipeline->device->physical_device->rad_info.family == CHIP_NAVI12 ||
3940 pipeline->device->physical_device->rad_info.family == CHIP_NAVI14) &&
3941 !radv_pipeline_has_tess(pipeline) &&
3942 ngg_state->hw_max_esverts != 256) {
3943 ge_cntl &= C_03096C_VERT_GRP_SIZE;
3944
3945 if (ngg_state->hw_max_esverts > 5) {
3946 ge_cntl |= S_03096C_VERT_GRP_SIZE(ngg_state->hw_max_esverts - 5);
3947 }
3948 }
3949
3950 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL, ge_cntl);
3951 }
3952
3953 static void
3954 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf *cs,
3955 struct radv_pipeline *pipeline,
3956 struct radv_shader_variant *shader,
3957 const struct radv_tessellation_state *tess)
3958 {
3959 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3960
3961 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
3962 unsigned hs_rsrc2 = shader->config.rsrc2;
3963
3964 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3965 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX10(tess->lds_size);
3966 } else {
3967 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX9(tess->lds_size);
3968 }
3969
3970 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3971 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
3972 radeon_emit(cs, va >> 8);
3973 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
3974 } else {
3975 radeon_set_sh_reg_seq(cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
3976 radeon_emit(cs, va >> 8);
3977 radeon_emit(cs, S_00B414_MEM_BASE(va >> 40));
3978 }
3979
3980 radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
3981 radeon_emit(cs, shader->config.rsrc1);
3982 radeon_emit(cs, hs_rsrc2);
3983 } else {
3984 radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
3985 radeon_emit(cs, va >> 8);
3986 radeon_emit(cs, S_00B424_MEM_BASE(va >> 40));
3987 radeon_emit(cs, shader->config.rsrc1);
3988 radeon_emit(cs, shader->config.rsrc2);
3989 }
3990 }
3991
3992 static void
3993 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf *ctx_cs,
3994 struct radeon_cmdbuf *cs,
3995 struct radv_pipeline *pipeline,
3996 const struct radv_tessellation_state *tess)
3997 {
3998 struct radv_shader_variant *vs;
3999
4000 /* Skip shaders merged into HS/GS */
4001 vs = pipeline->shaders[MESA_SHADER_VERTEX];
4002 if (!vs)
4003 return;
4004
4005 if (vs->info.vs.as_ls)
4006 radv_pipeline_generate_hw_ls(cs, pipeline, vs, tess);
4007 else if (vs->info.vs.as_es)
4008 radv_pipeline_generate_hw_es(cs, pipeline, vs);
4009 else if (vs->info.is_ngg)
4010 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, vs);
4011 else
4012 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, vs);
4013 }
4014
4015 static void
4016 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf *ctx_cs,
4017 struct radeon_cmdbuf *cs,
4018 struct radv_pipeline *pipeline,
4019 const struct radv_tessellation_state *tess)
4020 {
4021 if (!radv_pipeline_has_tess(pipeline))
4022 return;
4023
4024 struct radv_shader_variant *tes, *tcs;
4025
4026 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
4027 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
4028
4029 if (tes) {
4030 if (tes->info.is_ngg) {
4031 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, tes);
4032 } else if (tes->info.tes.as_es)
4033 radv_pipeline_generate_hw_es(cs, pipeline, tes);
4034 else
4035 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, tes);
4036 }
4037
4038 radv_pipeline_generate_hw_hs(cs, pipeline, tcs, tess);
4039
4040 radeon_set_context_reg(ctx_cs, R_028B6C_VGT_TF_PARAM,
4041 tess->tf_param);
4042
4043 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7)
4044 radeon_set_context_reg_idx(ctx_cs, R_028B58_VGT_LS_HS_CONFIG, 2,
4045 tess->ls_hs_config);
4046 else
4047 radeon_set_context_reg(ctx_cs, R_028B58_VGT_LS_HS_CONFIG,
4048 tess->ls_hs_config);
4049
4050 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 &&
4051 !radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) {
4052 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
4053 S_028A44_ES_VERTS_PER_SUBGRP(250) |
4054 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
4055 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
4056 }
4057 }
4058
4059 static void
4060 radv_pipeline_generate_hw_gs(struct radeon_cmdbuf *ctx_cs,
4061 struct radeon_cmdbuf *cs,
4062 struct radv_pipeline *pipeline,
4063 struct radv_shader_variant *gs)
4064 {
4065 const struct gfx9_gs_info *gs_state = &gs->info.gs_ring_info;
4066 unsigned gs_max_out_vertices;
4067 uint8_t *num_components;
4068 uint8_t max_stream;
4069 unsigned offset;
4070 uint64_t va;
4071
4072 gs_max_out_vertices = gs->info.gs.vertices_out;
4073 max_stream = gs->info.gs.max_stream;
4074 num_components = gs->info.gs.num_stream_output_components;
4075
4076 offset = num_components[0] * gs_max_out_vertices;
4077
4078 radeon_set_context_reg_seq(ctx_cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
4079 radeon_emit(ctx_cs, offset);
4080 if (max_stream >= 1)
4081 offset += num_components[1] * gs_max_out_vertices;
4082 radeon_emit(ctx_cs, offset);
4083 if (max_stream >= 2)
4084 offset += num_components[2] * gs_max_out_vertices;
4085 radeon_emit(ctx_cs, offset);
4086 if (max_stream >= 3)
4087 offset += num_components[3] * gs_max_out_vertices;
4088 radeon_set_context_reg(ctx_cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
4089
4090 radeon_set_context_reg_seq(ctx_cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
4091 radeon_emit(ctx_cs, num_components[0]);
4092 radeon_emit(ctx_cs, (max_stream >= 1) ? num_components[1] : 0);
4093 radeon_emit(ctx_cs, (max_stream >= 2) ? num_components[2] : 0);
4094 radeon_emit(ctx_cs, (max_stream >= 3) ? num_components[3] : 0);
4095
4096 uint32_t gs_num_invocations = gs->info.gs.invocations;
4097 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
4098 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
4099 S_028B90_ENABLE(gs_num_invocations > 0));
4100
4101 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
4102 gs_state->vgt_esgs_ring_itemsize);
4103
4104 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
4105
4106 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
4107 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4108 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
4109 radeon_emit(cs, va >> 8);
4110 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
4111 } else {
4112 radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
4113 radeon_emit(cs, va >> 8);
4114 radeon_emit(cs, S_00B214_MEM_BASE(va >> 40));
4115 }
4116
4117 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
4118 radeon_emit(cs, gs->config.rsrc1);
4119 radeon_emit(cs, gs->config.rsrc2 | S_00B22C_LDS_SIZE(gs_state->lds_size));
4120
4121 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL, gs_state->vgt_gs_onchip_cntl);
4122 radeon_set_context_reg(ctx_cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, gs_state->vgt_gs_max_prims_per_subgroup);
4123 } else {
4124 radeon_set_sh_reg_seq(cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
4125 radeon_emit(cs, va >> 8);
4126 radeon_emit(cs, S_00B224_MEM_BASE(va >> 40));
4127 radeon_emit(cs, gs->config.rsrc1);
4128 radeon_emit(cs, gs->config.rsrc2);
4129 }
4130
4131 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, pipeline->gs_copy_shader);
4132 }
4133
4134 static void
4135 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf *ctx_cs,
4136 struct radeon_cmdbuf *cs,
4137 struct radv_pipeline *pipeline)
4138 {
4139 struct radv_shader_variant *gs;
4140
4141 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
4142 if (!gs)
4143 return;
4144
4145 if (gs->info.is_ngg)
4146 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, gs);
4147 else
4148 radv_pipeline_generate_hw_gs(ctx_cs, cs, pipeline, gs);
4149
4150 radeon_set_context_reg(ctx_cs, R_028B38_VGT_GS_MAX_VERT_OUT,
4151 gs->info.gs.vertices_out);
4152 }
4153
4154 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade, bool float16)
4155 {
4156 uint32_t ps_input_cntl;
4157 if (offset <= AC_EXP_PARAM_OFFSET_31) {
4158 ps_input_cntl = S_028644_OFFSET(offset);
4159 if (flat_shade)
4160 ps_input_cntl |= S_028644_FLAT_SHADE(1);
4161 if (float16) {
4162 ps_input_cntl |= S_028644_FP16_INTERP_MODE(1) |
4163 S_028644_ATTR0_VALID(1);
4164 }
4165 } else {
4166 /* The input is a DEFAULT_VAL constant. */
4167 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
4168 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
4169 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
4170 ps_input_cntl = S_028644_OFFSET(0x20) |
4171 S_028644_DEFAULT_VAL(offset);
4172 }
4173 return ps_input_cntl;
4174 }
4175
4176 static void
4177 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf *ctx_cs,
4178 struct radv_pipeline *pipeline)
4179 {
4180 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4181 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
4182 uint32_t ps_input_cntl[32];
4183
4184 unsigned ps_offset = 0;
4185
4186 if (ps->info.ps.prim_id_input) {
4187 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
4188 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
4189 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false);
4190 ++ps_offset;
4191 }
4192 }
4193
4194 if (ps->info.ps.layer_input ||
4195 ps->info.needs_multiview_view_index) {
4196 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
4197 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
4198 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false);
4199 else
4200 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true, false);
4201 ++ps_offset;
4202 }
4203
4204 if (ps->info.ps.has_pcoord) {
4205 unsigned val;
4206 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
4207 ps_input_cntl[ps_offset] = val;
4208 ps_offset++;
4209 }
4210
4211 if (ps->info.ps.num_input_clips_culls) {
4212 unsigned vs_offset;
4213
4214 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST0];
4215 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
4216 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false);
4217 ++ps_offset;
4218 }
4219
4220 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST1];
4221 if (vs_offset != AC_EXP_PARAM_UNDEFINED &&
4222 ps->info.ps.num_input_clips_culls > 4) {
4223 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false);
4224 ++ps_offset;
4225 }
4226 }
4227
4228 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.ps.input_mask; ++i) {
4229 unsigned vs_offset;
4230 bool flat_shade;
4231 bool float16;
4232 if (!(ps->info.ps.input_mask & (1u << i)))
4233 continue;
4234
4235 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
4236 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
4237 ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
4238 ++ps_offset;
4239 continue;
4240 }
4241
4242 flat_shade = !!(ps->info.ps.flat_shaded_mask & (1u << ps_offset));
4243 float16 = !!(ps->info.ps.float16_shaded_mask & (1u << ps_offset));
4244
4245 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade, float16);
4246 ++ps_offset;
4247 }
4248
4249 if (ps_offset) {
4250 radeon_set_context_reg_seq(ctx_cs, R_028644_SPI_PS_INPUT_CNTL_0, ps_offset);
4251 for (unsigned i = 0; i < ps_offset; i++) {
4252 radeon_emit(ctx_cs, ps_input_cntl[i]);
4253 }
4254 }
4255 }
4256
4257 static uint32_t
4258 radv_compute_db_shader_control(const struct radv_device *device,
4259 const struct radv_pipeline *pipeline,
4260 const struct radv_shader_variant *ps)
4261 {
4262 unsigned z_order;
4263 if (ps->info.ps.early_fragment_test || !ps->info.ps.writes_memory)
4264 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
4265 else
4266 z_order = V_02880C_LATE_Z;
4267
4268 bool disable_rbplus = device->physical_device->rad_info.has_rbplus &&
4269 !device->physical_device->rad_info.rbplus_allowed;
4270
4271 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
4272 * but this appears to break Project Cars (DXVK). See
4273 * https://bugs.freedesktop.org/show_bug.cgi?id=109401
4274 */
4275 bool mask_export_enable = ps->info.ps.writes_sample_mask;
4276
4277 return S_02880C_Z_EXPORT_ENABLE(ps->info.ps.writes_z) |
4278 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.ps.writes_stencil) |
4279 S_02880C_KILL_ENABLE(!!ps->info.ps.can_discard) |
4280 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable) |
4281 S_02880C_Z_ORDER(z_order) |
4282 S_02880C_DEPTH_BEFORE_SHADER(ps->info.ps.early_fragment_test) |
4283 S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps->info.ps.post_depth_coverage) |
4284 S_02880C_EXEC_ON_HIER_FAIL(ps->info.ps.writes_memory) |
4285 S_02880C_EXEC_ON_NOOP(ps->info.ps.writes_memory) |
4286 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus);
4287 }
4288
4289 static void
4290 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf *ctx_cs,
4291 struct radeon_cmdbuf *cs,
4292 struct radv_pipeline *pipeline)
4293 {
4294 struct radv_shader_variant *ps;
4295 uint64_t va;
4296 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
4297
4298 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4299 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
4300
4301 radeon_set_sh_reg_seq(cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
4302 radeon_emit(cs, va >> 8);
4303 radeon_emit(cs, S_00B024_MEM_BASE(va >> 40));
4304 radeon_emit(cs, ps->config.rsrc1);
4305 radeon_emit(cs, ps->config.rsrc2);
4306
4307 radeon_set_context_reg(ctx_cs, R_02880C_DB_SHADER_CONTROL,
4308 radv_compute_db_shader_control(pipeline->device,
4309 pipeline, ps));
4310
4311 radeon_set_context_reg(ctx_cs, R_0286CC_SPI_PS_INPUT_ENA,
4312 ps->config.spi_ps_input_ena);
4313
4314 radeon_set_context_reg(ctx_cs, R_0286D0_SPI_PS_INPUT_ADDR,
4315 ps->config.spi_ps_input_addr);
4316
4317 radeon_set_context_reg(ctx_cs, R_0286D8_SPI_PS_IN_CONTROL,
4318 S_0286D8_NUM_INTERP(ps->info.ps.num_interp) |
4319 S_0286D8_PS_W32_EN(ps->info.wave_size == 32));
4320
4321 radeon_set_context_reg(ctx_cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl);
4322
4323 radeon_set_context_reg(ctx_cs, R_028710_SPI_SHADER_Z_FORMAT,
4324 ac_get_spi_shader_z_format(ps->info.ps.writes_z,
4325 ps->info.ps.writes_stencil,
4326 ps->info.ps.writes_sample_mask));
4327
4328 if (pipeline->device->dfsm_allowed) {
4329 /* optimise this? */
4330 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
4331 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
4332 }
4333 }
4334
4335 static void
4336 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf *ctx_cs,
4337 struct radv_pipeline *pipeline)
4338 {
4339 if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10 ||
4340 pipeline->device->physical_device->rad_info.chip_class >= GFX10)
4341 return;
4342
4343 unsigned vtx_reuse_depth = 30;
4344 if (radv_pipeline_has_tess(pipeline) &&
4345 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
4346 vtx_reuse_depth = 14;
4347 }
4348 radeon_set_context_reg(ctx_cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
4349 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth));
4350 }
4351
4352 static uint32_t
4353 radv_compute_vgt_shader_stages_en(const struct radv_pipeline *pipeline)
4354 {
4355 uint32_t stages = 0;
4356 if (radv_pipeline_has_tess(pipeline)) {
4357 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
4358 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
4359
4360 if (radv_pipeline_has_gs(pipeline))
4361 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
4362 S_028B54_GS_EN(1);
4363 else if (radv_pipeline_has_ngg(pipeline))
4364 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
4365 else
4366 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
4367 } else if (radv_pipeline_has_gs(pipeline)) {
4368 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
4369 S_028B54_GS_EN(1);
4370 } else if (radv_pipeline_has_ngg(pipeline)) {
4371 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
4372 }
4373
4374 if (radv_pipeline_has_ngg(pipeline)) {
4375 stages |= S_028B54_PRIMGEN_EN(1);
4376 if (pipeline->streamout_shader)
4377 stages |= S_028B54_NGG_WAVE_ID_EN(1);
4378 } else if (radv_pipeline_has_gs(pipeline)) {
4379 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
4380 }
4381
4382 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
4383 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
4384
4385 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4386 uint8_t hs_size = 64, gs_size = 64, vs_size = 64;
4387
4388 if (radv_pipeline_has_tess(pipeline))
4389 hs_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.wave_size;
4390
4391 if (pipeline->shaders[MESA_SHADER_GEOMETRY]) {
4392 vs_size = gs_size = pipeline->shaders[MESA_SHADER_GEOMETRY]->info.wave_size;
4393 if (pipeline->gs_copy_shader)
4394 vs_size = pipeline->gs_copy_shader->info.wave_size;
4395 } else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
4396 vs_size = pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.wave_size;
4397 else if (pipeline->shaders[MESA_SHADER_VERTEX])
4398 vs_size = pipeline->shaders[MESA_SHADER_VERTEX]->info.wave_size;
4399
4400 if (radv_pipeline_has_ngg(pipeline))
4401 gs_size = vs_size;
4402
4403 /* legacy GS only supports Wave64 */
4404 stages |= S_028B54_HS_W32_EN(hs_size == 32 ? 1 : 0) |
4405 S_028B54_GS_W32_EN(gs_size == 32 ? 1 : 0) |
4406 S_028B54_VS_W32_EN(vs_size == 32 ? 1 : 0);
4407 }
4408
4409 return stages;
4410 }
4411
4412 static uint32_t
4413 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo *pCreateInfo)
4414 {
4415 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
4416 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
4417
4418 if (!discard_rectangle_info)
4419 return 0xffff;
4420
4421 unsigned mask = 0;
4422
4423 for (unsigned i = 0; i < (1u << MAX_DISCARD_RECTANGLES); ++i) {
4424 /* Interpret i as a bitmask, and then set the bit in the mask if
4425 * that combination of rectangles in which the pixel is contained
4426 * should pass the cliprect test. */
4427 unsigned relevant_subset = i & ((1u << discard_rectangle_info->discardRectangleCount) - 1);
4428
4429 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT &&
4430 !relevant_subset)
4431 continue;
4432
4433 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT &&
4434 relevant_subset)
4435 continue;
4436
4437 mask |= 1u << i;
4438 }
4439
4440 return mask;
4441 }
4442
4443 static void
4444 gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf *ctx_cs,
4445 struct radv_pipeline *pipeline,
4446 const struct radv_tessellation_state *tess)
4447 {
4448 bool break_wave_at_eoi = false;
4449 unsigned primgroup_size;
4450 unsigned vertgroup_size;
4451
4452 if (radv_pipeline_has_tess(pipeline)) {
4453 primgroup_size = tess->num_patches; /* must be a multiple of NUM_PATCHES */
4454 vertgroup_size = 0;
4455 } else if (radv_pipeline_has_gs(pipeline)) {
4456 const struct gfx9_gs_info *gs_state =
4457 &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs_ring_info;
4458 unsigned vgt_gs_onchip_cntl = gs_state->vgt_gs_onchip_cntl;
4459 primgroup_size = G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl);
4460 vertgroup_size = G_028A44_ES_VERTS_PER_SUBGRP(vgt_gs_onchip_cntl);
4461 } else {
4462 primgroup_size = 128; /* recommended without a GS and tess */
4463 vertgroup_size = 0;
4464 }
4465
4466 if (radv_pipeline_has_tess(pipeline)) {
4467 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
4468 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.uses_prim_id)
4469 break_wave_at_eoi = true;
4470 }
4471
4472 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL,
4473 S_03096C_PRIM_GRP_SIZE(primgroup_size) |
4474 S_03096C_VERT_GRP_SIZE(vertgroup_size) |
4475 S_03096C_PACKET_TO_ONE_PA(0) /* line stipple */ |
4476 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi));
4477 }
4478
4479 static void
4480 radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
4481 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4482 const struct radv_graphics_pipeline_create_info *extra,
4483 const struct radv_blend_state *blend,
4484 const struct radv_tessellation_state *tess,
4485 unsigned prim, unsigned gs_out)
4486 {
4487 struct radeon_cmdbuf *ctx_cs = &pipeline->ctx_cs;
4488 struct radeon_cmdbuf *cs = &pipeline->cs;
4489
4490 cs->max_dw = 64;
4491 ctx_cs->max_dw = 256;
4492 cs->buf = malloc(4 * (cs->max_dw + ctx_cs->max_dw));
4493 ctx_cs->buf = cs->buf + cs->max_dw;
4494
4495 radv_pipeline_generate_depth_stencil_state(ctx_cs, pipeline, pCreateInfo, extra);
4496 radv_pipeline_generate_blend_state(ctx_cs, pipeline, blend);
4497 radv_pipeline_generate_raster_state(ctx_cs, pipeline, pCreateInfo);
4498 radv_pipeline_generate_multisample_state(ctx_cs, pipeline);
4499 radv_pipeline_generate_vgt_gs_mode(ctx_cs, pipeline);
4500 radv_pipeline_generate_vertex_shader(ctx_cs, cs, pipeline, tess);
4501 radv_pipeline_generate_tess_shaders(ctx_cs, cs, pipeline, tess);
4502 radv_pipeline_generate_geometry_shader(ctx_cs, cs, pipeline);
4503 radv_pipeline_generate_fragment_shader(ctx_cs, cs, pipeline);
4504 radv_pipeline_generate_ps_inputs(ctx_cs, pipeline);
4505 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs, pipeline);
4506 radv_pipeline_generate_binning_state(ctx_cs, pipeline, pCreateInfo, blend);
4507
4508 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 && !radv_pipeline_has_ngg(pipeline))
4509 gfx10_pipeline_generate_ge_cntl(ctx_cs, pipeline, tess);
4510
4511 radeon_set_context_reg(ctx_cs, R_028B54_VGT_SHADER_STAGES_EN, radv_compute_vgt_shader_stages_en(pipeline));
4512
4513 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
4514 radeon_set_uconfig_reg_idx(pipeline->device->physical_device,
4515 cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
4516 } else {
4517 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
4518 }
4519 radeon_set_context_reg(ctx_cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out);
4520
4521 radeon_set_context_reg(ctx_cs, R_02820C_PA_SC_CLIPRECT_RULE, radv_compute_cliprect_rule(pCreateInfo));
4522
4523 pipeline->ctx_cs_hash = _mesa_hash_data(ctx_cs->buf, ctx_cs->cdw * 4);
4524
4525 assert(ctx_cs->cdw <= ctx_cs->max_dw);
4526 assert(cs->cdw <= cs->max_dw);
4527 }
4528
4529 static struct radv_ia_multi_vgt_param_helpers
4530 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
4531 const struct radv_tessellation_state *tess,
4532 uint32_t prim)
4533 {
4534 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param = {0};
4535 const struct radv_device *device = pipeline->device;
4536
4537 if (radv_pipeline_has_tess(pipeline))
4538 ia_multi_vgt_param.primgroup_size = tess->num_patches;
4539 else if (radv_pipeline_has_gs(pipeline))
4540 ia_multi_vgt_param.primgroup_size = 64;
4541 else
4542 ia_multi_vgt_param.primgroup_size = 128; /* recommended without a GS */
4543
4544 /* GS requirement. */
4545 ia_multi_vgt_param.partial_es_wave = false;
4546 if (radv_pipeline_has_gs(pipeline) && device->physical_device->rad_info.chip_class <= GFX8)
4547 if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3)
4548 ia_multi_vgt_param.partial_es_wave = true;
4549
4550 ia_multi_vgt_param.wd_switch_on_eop = false;
4551 if (device->physical_device->rad_info.chip_class >= GFX7) {
4552 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
4553 * 4 shader engines. Set 1 to pass the assertion below.
4554 * The other cases are hardware requirements. */
4555 if (device->physical_device->rad_info.max_se < 4 ||
4556 prim == V_008958_DI_PT_POLYGON ||
4557 prim == V_008958_DI_PT_LINELOOP ||
4558 prim == V_008958_DI_PT_TRIFAN ||
4559 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
4560 (pipeline->graphics.prim_restart_enable &&
4561 (device->physical_device->rad_info.family < CHIP_POLARIS10 ||
4562 (prim != V_008958_DI_PT_POINTLIST &&
4563 prim != V_008958_DI_PT_LINESTRIP))))
4564 ia_multi_vgt_param.wd_switch_on_eop = true;
4565 }
4566
4567 ia_multi_vgt_param.ia_switch_on_eoi = false;
4568 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.prim_id_input)
4569 ia_multi_vgt_param.ia_switch_on_eoi = true;
4570 if (radv_pipeline_has_gs(pipeline) &&
4571 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.uses_prim_id)
4572 ia_multi_vgt_param.ia_switch_on_eoi = true;
4573 if (radv_pipeline_has_tess(pipeline)) {
4574 /* SWITCH_ON_EOI must be set if PrimID is used. */
4575 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
4576 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.uses_prim_id)
4577 ia_multi_vgt_param.ia_switch_on_eoi = true;
4578 }
4579
4580 ia_multi_vgt_param.partial_vs_wave = false;
4581 if (radv_pipeline_has_tess(pipeline)) {
4582 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
4583 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
4584 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
4585 device->physical_device->rad_info.family == CHIP_BONAIRE) &&
4586 radv_pipeline_has_gs(pipeline))
4587 ia_multi_vgt_param.partial_vs_wave = true;
4588 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
4589 if (device->physical_device->rad_info.has_distributed_tess) {
4590 if (radv_pipeline_has_gs(pipeline)) {
4591 if (device->physical_device->rad_info.chip_class <= GFX8)
4592 ia_multi_vgt_param.partial_es_wave = true;
4593 } else {
4594 ia_multi_vgt_param.partial_vs_wave = true;
4595 }
4596 }
4597 }
4598
4599 /* Workaround for a VGT hang when strip primitive types are used with
4600 * primitive restart.
4601 */
4602 if (pipeline->graphics.prim_restart_enable &&
4603 (prim == V_008958_DI_PT_LINESTRIP ||
4604 prim == V_008958_DI_PT_TRISTRIP ||
4605 prim == V_008958_DI_PT_LINESTRIP_ADJ ||
4606 prim == V_008958_DI_PT_TRISTRIP_ADJ)) {
4607 ia_multi_vgt_param.partial_vs_wave = true;
4608 }
4609
4610 if (radv_pipeline_has_gs(pipeline)) {
4611 /* On these chips there is the possibility of a hang if the
4612 * pipeline uses a GS and partial_vs_wave is not set.
4613 *
4614 * This mostly does not hit 4-SE chips, as those typically set
4615 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
4616 * with GS due to another workaround.
4617 *
4618 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
4619 */
4620 if (device->physical_device->rad_info.family == CHIP_TONGA ||
4621 device->physical_device->rad_info.family == CHIP_FIJI ||
4622 device->physical_device->rad_info.family == CHIP_POLARIS10 ||
4623 device->physical_device->rad_info.family == CHIP_POLARIS11 ||
4624 device->physical_device->rad_info.family == CHIP_POLARIS12 ||
4625 device->physical_device->rad_info.family == CHIP_VEGAM) {
4626 ia_multi_vgt_param.partial_vs_wave = true;
4627 }
4628 }
4629
4630 ia_multi_vgt_param.base =
4631 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param.primgroup_size - 1) |
4632 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
4633 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == GFX8 ? 2 : 0) |
4634 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
4635 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
4636
4637 return ia_multi_vgt_param;
4638 }
4639
4640
4641 static void
4642 radv_compute_vertex_input_state(struct radv_pipeline *pipeline,
4643 const VkGraphicsPipelineCreateInfo *pCreateInfo)
4644 {
4645 const VkPipelineVertexInputStateCreateInfo *vi_info =
4646 pCreateInfo->pVertexInputState;
4647 struct radv_vertex_elements_info *velems = &pipeline->vertex_elements;
4648
4649 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
4650 const VkVertexInputAttributeDescription *desc =
4651 &vi_info->pVertexAttributeDescriptions[i];
4652 unsigned loc = desc->location;
4653 const struct vk_format_description *format_desc;
4654
4655 format_desc = vk_format_description(desc->format);
4656
4657 velems->format_size[loc] = format_desc->block.bits / 8;
4658 }
4659
4660 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
4661 const VkVertexInputBindingDescription *desc =
4662 &vi_info->pVertexBindingDescriptions[i];
4663
4664 pipeline->binding_stride[desc->binding] = desc->stride;
4665 pipeline->num_vertex_bindings =
4666 MAX2(pipeline->num_vertex_bindings, desc->binding + 1);
4667 }
4668 }
4669
4670 static struct radv_shader_variant *
4671 radv_pipeline_get_streamout_shader(struct radv_pipeline *pipeline)
4672 {
4673 int i;
4674
4675 for (i = MESA_SHADER_GEOMETRY; i >= MESA_SHADER_VERTEX; i--) {
4676 struct radv_shader_variant *shader =
4677 radv_get_shader(pipeline, i);
4678
4679 if (shader && shader->info.so.num_outputs > 0)
4680 return shader;
4681 }
4682
4683 return NULL;
4684 }
4685
4686 static VkResult
4687 radv_secure_compile(struct radv_pipeline *pipeline,
4688 struct radv_device *device,
4689 const struct radv_pipeline_key *key,
4690 const VkPipelineShaderStageCreateInfo **pStages,
4691 const VkPipelineCreateFlags flags,
4692 unsigned num_stages)
4693 {
4694 uint8_t allowed_pipeline_hashes[2][20];
4695 radv_hash_shaders(allowed_pipeline_hashes[0], pStages,
4696 pipeline->layout, key, get_hash_flags(device));
4697
4698 /* Generate the GC copy hash */
4699 memcpy(allowed_pipeline_hashes[1], allowed_pipeline_hashes[0], 20);
4700 allowed_pipeline_hashes[1][0] ^= 1;
4701
4702 uint8_t allowed_hashes[2][20];
4703 for (unsigned i = 0; i < 2; ++i) {
4704 disk_cache_compute_key(device->physical_device->disk_cache,
4705 allowed_pipeline_hashes[i], 20,
4706 allowed_hashes[i]);
4707 }
4708
4709 /* Do an early exit if all cache entries are already there. */
4710 bool may_need_copy_shader = pStages[MESA_SHADER_GEOMETRY];
4711 void *main_entry = disk_cache_get(device->physical_device->disk_cache, allowed_hashes[0], NULL);
4712 void *copy_entry = NULL;
4713 if (may_need_copy_shader)
4714 copy_entry = disk_cache_get(device->physical_device->disk_cache, allowed_hashes[1], NULL);
4715
4716 bool has_all_cache_entries = main_entry && (!may_need_copy_shader || copy_entry);
4717 free(main_entry);
4718 free(copy_entry);
4719
4720 if(has_all_cache_entries)
4721 return VK_SUCCESS;
4722
4723 unsigned process = 0;
4724 uint8_t sc_threads = device->instance->num_sc_threads;
4725 while (true) {
4726 mtx_lock(&device->sc_state->secure_compile_mutex);
4727 if (device->sc_state->secure_compile_thread_counter < sc_threads) {
4728 device->sc_state->secure_compile_thread_counter++;
4729 for (unsigned i = 0; i < sc_threads; i++) {
4730 if (!device->sc_state->secure_compile_processes[i].in_use) {
4731 device->sc_state->secure_compile_processes[i].in_use = true;
4732 process = i;
4733 break;
4734 }
4735 }
4736 mtx_unlock(&device->sc_state->secure_compile_mutex);
4737 break;
4738 }
4739 mtx_unlock(&device->sc_state->secure_compile_mutex);
4740 }
4741
4742 int fd_secure_input = device->sc_state->secure_compile_processes[process].fd_secure_input;
4743 int fd_secure_output = device->sc_state->secure_compile_processes[process].fd_secure_output;
4744
4745 /* Fork a copy of the slim untainted secure compile process */
4746 enum radv_secure_compile_type sc_type = RADV_SC_TYPE_FORK_DEVICE;
4747 write(fd_secure_input, &sc_type, sizeof(sc_type));
4748
4749 if (!radv_sc_read(fd_secure_output, &sc_type, sizeof(sc_type), true) ||
4750 sc_type != RADV_SC_TYPE_INIT_SUCCESS)
4751 return VK_ERROR_DEVICE_LOST;
4752
4753 fd_secure_input = device->sc_state->secure_compile_processes[process].fd_server;
4754 fd_secure_output = device->sc_state->secure_compile_processes[process].fd_client;
4755
4756 /* Write pipeline / shader module out to secure process via pipe */
4757 sc_type = RADV_SC_TYPE_COMPILE_PIPELINE;
4758 write(fd_secure_input, &sc_type, sizeof(sc_type));
4759
4760 /* Write pipeline layout out to secure process */
4761 struct radv_pipeline_layout *layout = pipeline->layout;
4762 write(fd_secure_input, layout, sizeof(struct radv_pipeline_layout));
4763 write(fd_secure_input, &layout->num_sets, sizeof(uint32_t));
4764 for (uint32_t set = 0; set < layout->num_sets; set++) {
4765 write(fd_secure_input, &layout->set[set].layout->layout_size, sizeof(uint32_t));
4766 write(fd_secure_input, layout->set[set].layout, layout->set[set].layout->layout_size);
4767 }
4768
4769 /* Write pipeline key out to secure process */
4770 write(fd_secure_input, key, sizeof(struct radv_pipeline_key));
4771
4772 /* Write pipeline create flags out to secure process */
4773 write(fd_secure_input, &flags, sizeof(VkPipelineCreateFlags));
4774
4775 /* Write stage and shader information out to secure process */
4776 write(fd_secure_input, &num_stages, sizeof(uint32_t));
4777 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
4778 if (!pStages[i])
4779 continue;
4780
4781 /* Write stage out to secure process */
4782 gl_shader_stage stage = ffs(pStages[i]->stage) - 1;
4783 write(fd_secure_input, &stage, sizeof(gl_shader_stage));
4784
4785 /* Write entry point name out to secure process */
4786 size_t name_size = strlen(pStages[i]->pName) + 1;
4787 write(fd_secure_input, &name_size, sizeof(size_t));
4788 write(fd_secure_input, pStages[i]->pName, name_size);
4789
4790 /* Write shader module out to secure process */
4791 struct radv_shader_module *module = radv_shader_module_from_handle(pStages[i]->module);
4792 assert(!module->nir);
4793 size_t module_size = sizeof(struct radv_shader_module) + module->size;
4794 write(fd_secure_input, &module_size, sizeof(size_t));
4795 write(fd_secure_input, module, module_size);
4796
4797 /* Write specialization info out to secure process */
4798 const VkSpecializationInfo *specInfo = pStages[i]->pSpecializationInfo;
4799 bool has_spec_info = specInfo ? true : false;
4800 write(fd_secure_input, &has_spec_info, sizeof(bool));
4801 if (specInfo) {
4802 write(fd_secure_input, &specInfo->dataSize, sizeof(size_t));
4803 write(fd_secure_input, specInfo->pData, specInfo->dataSize);
4804
4805 write(fd_secure_input, &specInfo->mapEntryCount, sizeof(uint32_t));
4806 for (uint32_t j = 0; j < specInfo->mapEntryCount; j++)
4807 write(fd_secure_input, &specInfo->pMapEntries[j], sizeof(VkSpecializationMapEntry));
4808 }
4809 }
4810
4811 /* Read the data returned from the secure process */
4812 while (sc_type != RADV_SC_TYPE_COMPILE_PIPELINE_FINISHED) {
4813 if (!radv_sc_read(fd_secure_output, &sc_type, sizeof(sc_type), true))
4814 return VK_ERROR_DEVICE_LOST;
4815
4816 if (sc_type == RADV_SC_TYPE_WRITE_DISK_CACHE) {
4817 assert(device->physical_device->disk_cache);
4818
4819 uint8_t disk_sha1[20];
4820 if (!radv_sc_read(fd_secure_output, disk_sha1, sizeof(uint8_t) * 20, true))
4821 return VK_ERROR_DEVICE_LOST;
4822
4823 if (memcmp(disk_sha1, allowed_hashes[0], 20) &&
4824 memcmp(disk_sha1, allowed_hashes[1], 20))
4825 return VK_ERROR_DEVICE_LOST;
4826
4827 uint32_t entry_size;
4828 if (!radv_sc_read(fd_secure_output, &entry_size, sizeof(uint32_t), true))
4829 return VK_ERROR_DEVICE_LOST;
4830
4831 struct cache_entry *entry = malloc(entry_size);
4832 if (!radv_sc_read(fd_secure_output, entry, entry_size, true))
4833 return VK_ERROR_DEVICE_LOST;
4834
4835 disk_cache_put(device->physical_device->disk_cache,
4836 disk_sha1, entry, entry_size,
4837 NULL);
4838
4839 free(entry);
4840 } else if (sc_type == RADV_SC_TYPE_READ_DISK_CACHE) {
4841 uint8_t disk_sha1[20];
4842 if (!radv_sc_read(fd_secure_output, disk_sha1, sizeof(uint8_t) * 20, true))
4843 return VK_ERROR_DEVICE_LOST;
4844
4845 if (memcmp(disk_sha1, allowed_hashes[0], 20) &&
4846 memcmp(disk_sha1, allowed_hashes[1], 20))
4847 return VK_ERROR_DEVICE_LOST;
4848
4849 size_t size;
4850 struct cache_entry *entry = (struct cache_entry *)
4851 disk_cache_get(device->physical_device->disk_cache,
4852 disk_sha1, &size);
4853
4854 uint8_t found = entry ? 1 : 0;
4855 write(fd_secure_input, &found, sizeof(uint8_t));
4856
4857 if (found) {
4858 write(fd_secure_input, &size, sizeof(size_t));
4859 write(fd_secure_input, entry, size);
4860 }
4861
4862 free(entry);
4863 }
4864 }
4865
4866 sc_type = RADV_SC_TYPE_DESTROY_DEVICE;
4867 write(fd_secure_input, &sc_type, sizeof(sc_type));
4868
4869 mtx_lock(&device->sc_state->secure_compile_mutex);
4870 device->sc_state->secure_compile_thread_counter--;
4871 device->sc_state->secure_compile_processes[process].in_use = false;
4872 mtx_unlock(&device->sc_state->secure_compile_mutex);
4873
4874 return VK_SUCCESS;
4875 }
4876
4877 static VkResult
4878 radv_pipeline_init(struct radv_pipeline *pipeline,
4879 struct radv_device *device,
4880 struct radv_pipeline_cache *cache,
4881 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4882 const struct radv_graphics_pipeline_create_info *extra)
4883 {
4884 VkResult result;
4885 bool has_view_index = false;
4886
4887 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
4888 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
4889 if (subpass->view_mask)
4890 has_view_index = true;
4891
4892 pipeline->device = device;
4893 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
4894 assert(pipeline->layout);
4895
4896 struct radv_blend_state blend = radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
4897
4898 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
4899 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
4900 radv_init_feedback(creation_feedback);
4901
4902 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
4903
4904 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
4905 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
4906 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
4907 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
4908 pStages[stage] = &pCreateInfo->pStages[i];
4909 if(creation_feedback)
4910 stage_feedbacks[stage] = &creation_feedback->pPipelineStageCreationFeedbacks[i];
4911 }
4912
4913 struct radv_pipeline_key key = radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &blend, has_view_index);
4914 if (radv_device_use_secure_compile(device->instance)) {
4915 return radv_secure_compile(pipeline, device, &key, pStages, pCreateInfo->flags, pCreateInfo->stageCount);
4916 } else {
4917 radv_create_shaders(pipeline, device, cache, &key, pStages, pCreateInfo->flags, pipeline_feedback, stage_feedbacks);
4918 }
4919
4920 pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
4921 radv_pipeline_init_multisample_state(pipeline, &blend, pCreateInfo);
4922 uint32_t gs_out;
4923 uint32_t prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
4924
4925 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
4926
4927 if (radv_pipeline_has_gs(pipeline)) {
4928 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
4929 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
4930 } else if (radv_pipeline_has_tess(pipeline)) {
4931 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.point_mode)
4932 gs_out = V_028A6C_OUTPRIM_TYPE_POINTLIST;
4933 else
4934 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.primitive_mode);
4935 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
4936 } else {
4937 gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
4938 }
4939 if (extra && extra->use_rectlist) {
4940 prim = V_008958_DI_PT_RECTLIST;
4941 gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
4942 pipeline->graphics.can_use_guardband = true;
4943 if (radv_pipeline_has_ngg(pipeline))
4944 gs_out = V_028A6C_VGT_OUT_RECT_V0;
4945 }
4946 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
4947 /* prim vertex count will need TESS changes */
4948 pipeline->graphics.prim_vertex_count = prim_size_table[prim];
4949
4950 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
4951
4952 /* Ensure that some export memory is always allocated, for two reasons:
4953 *
4954 * 1) Correctness: The hardware ignores the EXEC mask if no export
4955 * memory is allocated, so KILL and alpha test do not work correctly
4956 * without this.
4957 * 2) Performance: Every shader needs at least a NULL export, even when
4958 * it writes no color/depth output. The NULL export instruction
4959 * stalls without this setting.
4960 *
4961 * Don't add this to CB_SHADER_MASK.
4962 *
4963 * GFX10 supports pixel shaders without exports by setting both the
4964 * color and Z formats to SPI_SHADER_ZERO. The hw will skip export
4965 * instructions if any are present.
4966 */
4967 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4968 if ((pipeline->device->physical_device->rad_info.chip_class <= GFX9 ||
4969 ps->info.ps.can_discard) &&
4970 !blend.spi_shader_col_format) {
4971 if (!ps->info.ps.writes_z &&
4972 !ps->info.ps.writes_stencil &&
4973 !ps->info.ps.writes_sample_mask)
4974 blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
4975 }
4976
4977 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
4978 if (pipeline->shaders[i]) {
4979 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
4980 }
4981 }
4982
4983 if (radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) {
4984 struct radv_shader_variant *gs =
4985 pipeline->shaders[MESA_SHADER_GEOMETRY];
4986
4987 calculate_gs_ring_sizes(pipeline, &gs->info.gs_ring_info);
4988 }
4989
4990 struct radv_tessellation_state tess = {0};
4991 if (radv_pipeline_has_tess(pipeline)) {
4992 if (prim == V_008958_DI_PT_PATCH) {
4993 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
4994 pipeline->graphics.prim_vertex_count.incr = 1;
4995 }
4996 tess = calculate_tess_state(pipeline, pCreateInfo);
4997 }
4998
4999 pipeline->graphics.ia_multi_vgt_param = radv_compute_ia_multi_vgt_param_helpers(pipeline, &tess, prim);
5000
5001 radv_compute_vertex_input_state(pipeline, pCreateInfo);
5002
5003 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
5004 pipeline->user_data_0[i] = radv_pipeline_stage_to_user_data_0(pipeline, i, device->physical_device->rad_info.chip_class);
5005
5006 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
5007 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
5008 if (loc->sgpr_idx != -1) {
5009 pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX];
5010 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
5011 if (radv_get_shader(pipeline, MESA_SHADER_VERTEX)->info.vs.needs_draw_id)
5012 pipeline->graphics.vtx_emit_num = 3;
5013 else
5014 pipeline->graphics.vtx_emit_num = 2;
5015 }
5016
5017 /* Find the last vertex shader stage that eventually uses streamout. */
5018 pipeline->streamout_shader = radv_pipeline_get_streamout_shader(pipeline);
5019
5020 result = radv_pipeline_scratch_init(device, pipeline);
5021 radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend, &tess, prim, gs_out);
5022
5023 return result;
5024 }
5025
5026 VkResult
5027 radv_graphics_pipeline_create(
5028 VkDevice _device,
5029 VkPipelineCache _cache,
5030 const VkGraphicsPipelineCreateInfo *pCreateInfo,
5031 const struct radv_graphics_pipeline_create_info *extra,
5032 const VkAllocationCallbacks *pAllocator,
5033 VkPipeline *pPipeline)
5034 {
5035 RADV_FROM_HANDLE(radv_device, device, _device);
5036 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
5037 struct radv_pipeline *pipeline;
5038 VkResult result;
5039
5040 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
5041 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5042 if (pipeline == NULL)
5043 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5044
5045 result = radv_pipeline_init(pipeline, device, cache,
5046 pCreateInfo, extra);
5047 if (result != VK_SUCCESS) {
5048 radv_pipeline_destroy(device, pipeline, pAllocator);
5049 return result;
5050 }
5051
5052 *pPipeline = radv_pipeline_to_handle(pipeline);
5053
5054 return VK_SUCCESS;
5055 }
5056
5057 VkResult radv_CreateGraphicsPipelines(
5058 VkDevice _device,
5059 VkPipelineCache pipelineCache,
5060 uint32_t count,
5061 const VkGraphicsPipelineCreateInfo* pCreateInfos,
5062 const VkAllocationCallbacks* pAllocator,
5063 VkPipeline* pPipelines)
5064 {
5065 VkResult result = VK_SUCCESS;
5066 unsigned i = 0;
5067
5068 for (; i < count; i++) {
5069 VkResult r;
5070 r = radv_graphics_pipeline_create(_device,
5071 pipelineCache,
5072 &pCreateInfos[i],
5073 NULL, pAllocator, &pPipelines[i]);
5074 if (r != VK_SUCCESS) {
5075 result = r;
5076 pPipelines[i] = VK_NULL_HANDLE;
5077 }
5078 }
5079
5080 return result;
5081 }
5082
5083
5084 static void
5085 radv_compute_generate_pm4(struct radv_pipeline *pipeline)
5086 {
5087 struct radv_shader_variant *compute_shader;
5088 struct radv_device *device = pipeline->device;
5089 unsigned threads_per_threadgroup;
5090 unsigned threadgroups_per_cu = 1;
5091 unsigned waves_per_threadgroup;
5092 unsigned max_waves_per_sh = 0;
5093 uint64_t va;
5094
5095 pipeline->cs.max_dw = device->physical_device->rad_info.chip_class >= GFX10 ? 22 : 20;
5096 pipeline->cs.buf = malloc(pipeline->cs.max_dw * 4);
5097
5098 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
5099 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
5100
5101 radeon_set_sh_reg_seq(&pipeline->cs, R_00B830_COMPUTE_PGM_LO, 2);
5102 radeon_emit(&pipeline->cs, va >> 8);
5103 radeon_emit(&pipeline->cs, S_00B834_DATA(va >> 40));
5104
5105 radeon_set_sh_reg_seq(&pipeline->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
5106 radeon_emit(&pipeline->cs, compute_shader->config.rsrc1);
5107 radeon_emit(&pipeline->cs, compute_shader->config.rsrc2);
5108 if (device->physical_device->rad_info.chip_class >= GFX10) {
5109 radeon_set_sh_reg(&pipeline->cs, R_00B8A0_COMPUTE_PGM_RSRC3, compute_shader->config.rsrc3);
5110 }
5111
5112 /* Calculate best compute resource limits. */
5113 threads_per_threadgroup = compute_shader->info.cs.block_size[0] *
5114 compute_shader->info.cs.block_size[1] *
5115 compute_shader->info.cs.block_size[2];
5116 waves_per_threadgroup = DIV_ROUND_UP(threads_per_threadgroup,
5117 compute_shader->info.wave_size);
5118
5119 if (device->physical_device->rad_info.chip_class >= GFX10 &&
5120 waves_per_threadgroup == 1)
5121 threadgroups_per_cu = 2;
5122
5123 radeon_set_sh_reg(&pipeline->cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
5124 ac_get_compute_resource_limits(&device->physical_device->rad_info,
5125 waves_per_threadgroup,
5126 max_waves_per_sh,
5127 threadgroups_per_cu));
5128
5129 radeon_set_sh_reg_seq(&pipeline->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
5130 radeon_emit(&pipeline->cs,
5131 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
5132 radeon_emit(&pipeline->cs,
5133 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
5134 radeon_emit(&pipeline->cs,
5135 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
5136
5137 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
5138 }
5139
5140 static struct radv_pipeline_key
5141 radv_generate_compute_pipeline_key(struct radv_pipeline *pipeline,
5142 const VkComputePipelineCreateInfo *pCreateInfo)
5143 {
5144 const VkPipelineShaderStageCreateInfo *stage = &pCreateInfo->stage;
5145 struct radv_pipeline_key key;
5146 memset(&key, 0, sizeof(key));
5147
5148 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
5149 key.optimisations_disabled = 1;
5150
5151 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT *subgroup_size =
5152 vk_find_struct_const(stage->pNext,
5153 PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT);
5154
5155 if (subgroup_size) {
5156 assert(subgroup_size->requiredSubgroupSize == 32 ||
5157 subgroup_size->requiredSubgroupSize == 64);
5158 key.compute_subgroup_size = subgroup_size->requiredSubgroupSize;
5159 }
5160
5161 return key;
5162 }
5163
5164 static VkResult radv_compute_pipeline_create(
5165 VkDevice _device,
5166 VkPipelineCache _cache,
5167 const VkComputePipelineCreateInfo* pCreateInfo,
5168 const VkAllocationCallbacks* pAllocator,
5169 VkPipeline* pPipeline)
5170 {
5171 RADV_FROM_HANDLE(radv_device, device, _device);
5172 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
5173 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
5174 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
5175 struct radv_pipeline *pipeline;
5176 VkResult result;
5177
5178 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
5179 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5180 if (pipeline == NULL)
5181 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5182
5183 pipeline->device = device;
5184 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
5185 assert(pipeline->layout);
5186
5187 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
5188 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
5189 radv_init_feedback(creation_feedback);
5190
5191 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
5192 if (creation_feedback)
5193 stage_feedbacks[MESA_SHADER_COMPUTE] = &creation_feedback->pPipelineStageCreationFeedbacks[0];
5194
5195 pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
5196
5197 struct radv_pipeline_key key =
5198 radv_generate_compute_pipeline_key(pipeline, pCreateInfo);
5199
5200 if (radv_device_use_secure_compile(device->instance)) {
5201 result = radv_secure_compile(pipeline, device, &key, pStages, pCreateInfo->flags, 1);
5202 *pPipeline = radv_pipeline_to_handle(pipeline);
5203
5204 return result;
5205 } else {
5206 radv_create_shaders(pipeline, device, cache, &key, pStages, pCreateInfo->flags, pipeline_feedback, stage_feedbacks);
5207 }
5208
5209 pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
5210 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
5211 result = radv_pipeline_scratch_init(device, pipeline);
5212 if (result != VK_SUCCESS) {
5213 radv_pipeline_destroy(device, pipeline, pAllocator);
5214 return result;
5215 }
5216
5217 radv_compute_generate_pm4(pipeline);
5218
5219 *pPipeline = radv_pipeline_to_handle(pipeline);
5220
5221 return VK_SUCCESS;
5222 }
5223
5224 VkResult radv_CreateComputePipelines(
5225 VkDevice _device,
5226 VkPipelineCache pipelineCache,
5227 uint32_t count,
5228 const VkComputePipelineCreateInfo* pCreateInfos,
5229 const VkAllocationCallbacks* pAllocator,
5230 VkPipeline* pPipelines)
5231 {
5232 VkResult result = VK_SUCCESS;
5233
5234 unsigned i = 0;
5235 for (; i < count; i++) {
5236 VkResult r;
5237 r = radv_compute_pipeline_create(_device, pipelineCache,
5238 &pCreateInfos[i],
5239 pAllocator, &pPipelines[i]);
5240 if (r != VK_SUCCESS) {
5241 result = r;
5242 pPipelines[i] = VK_NULL_HANDLE;
5243 }
5244 }
5245
5246 return result;
5247 }
5248
5249
5250 static uint32_t radv_get_executable_count(const struct radv_pipeline *pipeline)
5251 {
5252 uint32_t ret = 0;
5253 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
5254 if (!pipeline->shaders[i])
5255 continue;
5256
5257 if (i == MESA_SHADER_GEOMETRY &&
5258 !radv_pipeline_has_ngg(pipeline)) {
5259 ret += 2u;
5260 } else {
5261 ret += 1u;
5262 }
5263
5264 }
5265 return ret;
5266 }
5267
5268 static struct radv_shader_variant *
5269 radv_get_shader_from_executable_index(const struct radv_pipeline *pipeline, int index, gl_shader_stage *stage)
5270 {
5271 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
5272 if (!pipeline->shaders[i])
5273 continue;
5274 if (!index) {
5275 *stage = i;
5276 return pipeline->shaders[i];
5277 }
5278
5279 --index;
5280
5281 if (i == MESA_SHADER_GEOMETRY &&
5282 !radv_pipeline_has_ngg(pipeline)) {
5283 if (!index) {
5284 *stage = i;
5285 return pipeline->gs_copy_shader;
5286 }
5287 --index;
5288 }
5289 }
5290
5291 *stage = -1;
5292 return NULL;
5293 }
5294
5295 /* Basically strlcpy (which does not exist on linux) specialized for
5296 * descriptions. */
5297 static void desc_copy(char *desc, const char *src) {
5298 int len = strlen(src);
5299 assert(len < VK_MAX_DESCRIPTION_SIZE);
5300 memcpy(desc, src, len);
5301 memset(desc + len, 0, VK_MAX_DESCRIPTION_SIZE - len);
5302 }
5303
5304 VkResult radv_GetPipelineExecutablePropertiesKHR(
5305 VkDevice _device,
5306 const VkPipelineInfoKHR* pPipelineInfo,
5307 uint32_t* pExecutableCount,
5308 VkPipelineExecutablePropertiesKHR* pProperties)
5309 {
5310 RADV_FROM_HANDLE(radv_pipeline, pipeline, pPipelineInfo->pipeline);
5311 const uint32_t total_count = radv_get_executable_count(pipeline);
5312
5313 if (!pProperties) {
5314 *pExecutableCount = total_count;
5315 return VK_SUCCESS;
5316 }
5317
5318 const uint32_t count = MIN2(total_count, *pExecutableCount);
5319 for (unsigned i = 0, executable_idx = 0;
5320 i < MESA_SHADER_STAGES && executable_idx < count; ++i) {
5321 if (!pipeline->shaders[i])
5322 continue;
5323 pProperties[executable_idx].stages = mesa_to_vk_shader_stage(i);
5324 const char *name = NULL;
5325 const char *description = NULL;
5326 switch(i) {
5327 case MESA_SHADER_VERTEX:
5328 name = "Vertex Shader";
5329 description = "Vulkan Vertex Shader";
5330 break;
5331 case MESA_SHADER_TESS_CTRL:
5332 if (!pipeline->shaders[MESA_SHADER_VERTEX]) {
5333 pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT;
5334 name = "Vertex + Tessellation Control Shaders";
5335 description = "Combined Vulkan Vertex and Tessellation Control Shaders";
5336 } else {
5337 name = "Tessellation Control Shader";
5338 description = "Vulkan Tessellation Control Shader";
5339 }
5340 break;
5341 case MESA_SHADER_TESS_EVAL:
5342 name = "Tessellation Evaluation Shader";
5343 description = "Vulkan Tessellation Evaluation Shader";
5344 break;
5345 case MESA_SHADER_GEOMETRY:
5346 if (radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_TESS_EVAL]) {
5347 pProperties[executable_idx].stages |= VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT;
5348 name = "Tessellation Evaluation + Geometry Shaders";
5349 description = "Combined Vulkan Tessellation Evaluation and Geometry Shaders";
5350 } else if (!radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_VERTEX]) {
5351 pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT;
5352 name = "Vertex + Geometry Shader";
5353 description = "Combined Vulkan Vertex and Geometry Shaders";
5354 } else {
5355 name = "Geometry Shader";
5356 description = "Vulkan Geometry Shader";
5357 }
5358 break;
5359 case MESA_SHADER_FRAGMENT:
5360 name = "Fragment Shader";
5361 description = "Vulkan Fragment Shader";
5362 break;
5363 case MESA_SHADER_COMPUTE:
5364 name = "Compute Shader";
5365 description = "Vulkan Compute Shader";
5366 break;
5367 }
5368
5369 pProperties[executable_idx].subgroupSize = pipeline->shaders[i]->info.wave_size;
5370 desc_copy(pProperties[executable_idx].name, name);
5371 desc_copy(pProperties[executable_idx].description, description);
5372
5373 ++executable_idx;
5374 if (i == MESA_SHADER_GEOMETRY &&
5375 !radv_pipeline_has_ngg(pipeline)) {
5376 assert(pipeline->gs_copy_shader);
5377 if (executable_idx >= count)
5378 break;
5379
5380 pProperties[executable_idx].stages = VK_SHADER_STAGE_GEOMETRY_BIT;
5381 pProperties[executable_idx].subgroupSize = 64;
5382 desc_copy(pProperties[executable_idx].name, "GS Copy Shader");
5383 desc_copy(pProperties[executable_idx].description,
5384 "Extra shader stage that loads the GS output ringbuffer into the rasterizer");
5385
5386 ++executable_idx;
5387 }
5388 }
5389
5390 VkResult result = *pExecutableCount < total_count ? VK_INCOMPLETE : VK_SUCCESS;
5391 *pExecutableCount = count;
5392 return result;
5393 }
5394
5395 VkResult radv_GetPipelineExecutableStatisticsKHR(
5396 VkDevice _device,
5397 const VkPipelineExecutableInfoKHR* pExecutableInfo,
5398 uint32_t* pStatisticCount,
5399 VkPipelineExecutableStatisticKHR* pStatistics)
5400 {
5401 RADV_FROM_HANDLE(radv_device, device, _device);
5402 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
5403 gl_shader_stage stage;
5404 struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
5405
5406 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
5407 unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
5408 unsigned max_waves = radv_get_max_waves(device, shader, stage);
5409
5410 VkPipelineExecutableStatisticKHR *s = pStatistics;
5411 VkPipelineExecutableStatisticKHR *end = s + (pStatistics ? *pStatisticCount : 0);
5412 VkResult result = VK_SUCCESS;
5413
5414 if (s < end) {
5415 desc_copy(s->name, "SGPRs");
5416 desc_copy(s->description, "Number of SGPR registers allocated per subgroup");
5417 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5418 s->value.u64 = shader->config.num_sgprs;
5419 }
5420 ++s;
5421
5422 if (s < end) {
5423 desc_copy(s->name, "VGPRs");
5424 desc_copy(s->description, "Number of VGPR registers allocated per subgroup");
5425 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5426 s->value.u64 = shader->config.num_vgprs;
5427 }
5428 ++s;
5429
5430 if (s < end) {
5431 desc_copy(s->name, "Spilled SGPRs");
5432 desc_copy(s->description, "Number of SGPR registers spilled per subgroup");
5433 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5434 s->value.u64 = shader->config.spilled_sgprs;
5435 }
5436 ++s;
5437
5438 if (s < end) {
5439 desc_copy(s->name, "Spilled VGPRs");
5440 desc_copy(s->description, "Number of VGPR registers spilled per subgroup");
5441 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5442 s->value.u64 = shader->config.spilled_vgprs;
5443 }
5444 ++s;
5445
5446 if (s < end) {
5447 desc_copy(s->name, "PrivMem VGPRs");
5448 desc_copy(s->description, "Number of VGPRs stored in private memory per subgroup");
5449 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5450 s->value.u64 = shader->info.private_mem_vgprs;
5451 }
5452 ++s;
5453
5454 if (s < end) {
5455 desc_copy(s->name, "Code size");
5456 desc_copy(s->description, "Code size in bytes");
5457 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5458 s->value.u64 = shader->exec_size;
5459 }
5460 ++s;
5461
5462 if (s < end) {
5463 desc_copy(s->name, "LDS size");
5464 desc_copy(s->description, "LDS size in bytes per workgroup");
5465 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5466 s->value.u64 = shader->config.lds_size * lds_increment;
5467 }
5468 ++s;
5469
5470 if (s < end) {
5471 desc_copy(s->name, "Scratch size");
5472 desc_copy(s->description, "Private memory in bytes per subgroup");
5473 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5474 s->value.u64 = shader->config.scratch_bytes_per_wave;
5475 }
5476 ++s;
5477
5478 if (s < end) {
5479 desc_copy(s->name, "Subgroups per SIMD");
5480 desc_copy(s->description, "The maximum number of subgroups in flight on a SIMD unit");
5481 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5482 s->value.u64 = max_waves;
5483 }
5484 ++s;
5485
5486 if (!pStatistics)
5487 *pStatisticCount = s - pStatistics;
5488 else if (s > end) {
5489 *pStatisticCount = end - pStatistics;
5490 result = VK_INCOMPLETE;
5491 } else {
5492 *pStatisticCount = s - pStatistics;
5493 }
5494
5495 return result;
5496 }
5497
5498 static VkResult radv_copy_representation(void *data, size_t *data_size, const char *src)
5499 {
5500 size_t total_size = strlen(src) + 1;
5501
5502 if (!data) {
5503 *data_size = total_size;
5504 return VK_SUCCESS;
5505 }
5506
5507 size_t size = MIN2(total_size, *data_size);
5508
5509 memcpy(data, src, size);
5510 if (size)
5511 *((char*)data + size - 1) = 0;
5512 return size < total_size ? VK_INCOMPLETE : VK_SUCCESS;
5513 }
5514
5515 VkResult radv_GetPipelineExecutableInternalRepresentationsKHR(
5516 VkDevice device,
5517 const VkPipelineExecutableInfoKHR* pExecutableInfo,
5518 uint32_t* pInternalRepresentationCount,
5519 VkPipelineExecutableInternalRepresentationKHR* pInternalRepresentations)
5520 {
5521 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
5522 gl_shader_stage stage;
5523 struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
5524
5525 VkPipelineExecutableInternalRepresentationKHR *p = pInternalRepresentations;
5526 VkPipelineExecutableInternalRepresentationKHR *end = p + (pInternalRepresentations ? *pInternalRepresentationCount : 0);
5527 VkResult result = VK_SUCCESS;
5528 /* optimized NIR */
5529 if (p < end) {
5530 p->isText = true;
5531 desc_copy(p->name, "NIR Shader(s)");
5532 desc_copy(p->description, "The optimized NIR shader(s)");
5533 if (radv_copy_representation(p->pData, &p->dataSize, shader->nir_string) != VK_SUCCESS)
5534 result = VK_INCOMPLETE;
5535 }
5536 ++p;
5537
5538 /* backend IR */
5539 if (p < end) {
5540 p->isText = true;
5541 if (shader->aco_used) {
5542 desc_copy(p->name, "ACO IR");
5543 desc_copy(p->description, "The ACO IR after some optimizations");
5544 } else {
5545 desc_copy(p->name, "LLVM IR");
5546 desc_copy(p->description, "The LLVM IR after some optimizations");
5547 }
5548 if (radv_copy_representation(p->pData, &p->dataSize, shader->ir_string) != VK_SUCCESS)
5549 result = VK_INCOMPLETE;
5550 }
5551 ++p;
5552
5553 /* Disassembler */
5554 if (p < end) {
5555 p->isText = true;
5556 desc_copy(p->name, "Assembly");
5557 desc_copy(p->description, "Final Assembly");
5558 if (radv_copy_representation(p->pData, &p->dataSize, shader->disasm_string) != VK_SUCCESS)
5559 result = VK_INCOMPLETE;
5560 }
5561 ++p;
5562
5563 if (!pInternalRepresentations)
5564 *pInternalRepresentationCount = p - pInternalRepresentations;
5565 else if(p > end) {
5566 result = VK_INCOMPLETE;
5567 *pInternalRepresentationCount = end - pInternalRepresentations;
5568 } else {
5569 *pInternalRepresentationCount = p - pInternalRepresentations;
5570 }
5571
5572 return result;
5573 }