2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "util/disk_cache.h"
29 #include "util/mesa-sha1.h"
30 #include "util/u_atomic.h"
31 #include "radv_debug.h"
32 #include "radv_private.h"
34 #include "radv_shader.h"
36 #include "nir/nir_builder.h"
37 #include "nir/nir_xfb_info.h"
38 #include "spirv/nir_spirv.h"
42 #include "ac_binary.h"
43 #include "ac_llvm_util.h"
44 #include "ac_nir_to_llvm.h"
45 #include "vk_format.h"
46 #include "util/debug.h"
47 #include "ac_exp_param.h"
48 #include "ac_shader_util.h"
50 struct radv_blend_state
{
51 uint32_t blend_enable_4bit
;
52 uint32_t need_src_alpha
;
54 uint32_t cb_color_control
;
55 uint32_t cb_target_mask
;
56 uint32_t cb_target_enabled_4bit
;
57 uint32_t sx_mrt_blend_opt
[8];
58 uint32_t cb_blend_control
[8];
60 uint32_t spi_shader_col_format
;
61 uint32_t col_format_is_int8
;
62 uint32_t col_format_is_int10
;
63 uint32_t cb_shader_mask
;
64 uint32_t db_alpha_to_mask
;
66 uint32_t commutative_4bit
;
68 bool single_cb_enable
;
69 bool mrt0_is_dual_src
;
72 struct radv_dsa_order_invariance
{
73 /* Whether the final result in Z/S buffers is guaranteed to be
74 * invariant under changes to the order in which fragments arrive.
78 /* Whether the set of fragments that pass the combined Z/S test is
79 * guaranteed to be invariant under changes to the order in which
85 struct radv_tessellation_state
{
86 uint32_t ls_hs_config
;
92 static const VkPipelineMultisampleStateCreateInfo
*
93 radv_pipeline_get_multisample_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
95 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
)
96 return pCreateInfo
->pMultisampleState
;
100 static const VkPipelineTessellationStateCreateInfo
*
101 radv_pipeline_get_tessellation_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
103 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
104 if (pCreateInfo
->pStages
[i
].stage
== VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
||
105 pCreateInfo
->pStages
[i
].stage
== VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
) {
106 return pCreateInfo
->pTessellationState
;
112 static const VkPipelineDepthStencilStateCreateInfo
*
113 radv_pipeline_get_depth_stencil_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
115 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
116 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
118 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
119 subpass
->depth_stencil_attachment
)
120 return pCreateInfo
->pDepthStencilState
;
124 static const VkPipelineColorBlendStateCreateInfo
*
125 radv_pipeline_get_color_blend_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
127 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
128 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
130 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
131 subpass
->has_color_att
)
132 return pCreateInfo
->pColorBlendState
;
136 bool radv_pipeline_has_ngg(const struct radv_pipeline
*pipeline
)
138 struct radv_shader_variant
*variant
= NULL
;
139 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
140 variant
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
141 else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
142 variant
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
143 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
144 variant
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
147 return variant
->info
.is_ngg
;
150 bool radv_pipeline_has_ngg_passthrough(const struct radv_pipeline
*pipeline
)
152 assert(radv_pipeline_has_ngg(pipeline
));
154 struct radv_shader_variant
*variant
= NULL
;
155 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
156 variant
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
157 else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
158 variant
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
159 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
160 variant
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
163 return variant
->info
.is_ngg_passthrough
;
166 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline
*pipeline
)
168 if (!radv_pipeline_has_gs(pipeline
))
171 /* The GS copy shader is required if the pipeline has GS on GFX6-GFX9.
172 * On GFX10, it might be required in rare cases if it's not possible to
175 if (radv_pipeline_has_ngg(pipeline
))
178 assert(pipeline
->gs_copy_shader
);
183 radv_pipeline_destroy(struct radv_device
*device
,
184 struct radv_pipeline
*pipeline
,
185 const VkAllocationCallbacks
* allocator
)
187 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
188 if (pipeline
->shaders
[i
])
189 radv_shader_variant_destroy(device
, pipeline
->shaders
[i
]);
191 if (pipeline
->gs_copy_shader
)
192 radv_shader_variant_destroy(device
, pipeline
->gs_copy_shader
);
195 free(pipeline
->cs
.buf
);
197 vk_object_base_finish(&pipeline
->base
);
198 vk_free2(&device
->vk
.alloc
, allocator
, pipeline
);
201 void radv_DestroyPipeline(
203 VkPipeline _pipeline
,
204 const VkAllocationCallbacks
* pAllocator
)
206 RADV_FROM_HANDLE(radv_device
, device
, _device
);
207 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
212 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
215 static uint32_t get_hash_flags(struct radv_device
*device
)
217 uint32_t hash_flags
= 0;
219 if (device
->instance
->debug_flags
& RADV_DEBUG_NO_NGG
)
220 hash_flags
|= RADV_HASH_SHADER_NO_NGG
;
221 if (device
->physical_device
->cs_wave_size
== 32)
222 hash_flags
|= RADV_HASH_SHADER_CS_WAVE32
;
223 if (device
->physical_device
->ps_wave_size
== 32)
224 hash_flags
|= RADV_HASH_SHADER_PS_WAVE32
;
225 if (device
->physical_device
->ge_wave_size
== 32)
226 hash_flags
|= RADV_HASH_SHADER_GE_WAVE32
;
227 if (device
->physical_device
->use_llvm
)
228 hash_flags
|= RADV_HASH_SHADER_LLVM
;
233 radv_pipeline_scratch_init(struct radv_device
*device
,
234 struct radv_pipeline
*pipeline
)
236 unsigned scratch_bytes_per_wave
= 0;
237 unsigned max_waves
= 0;
238 unsigned min_waves
= 1;
240 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
241 if (pipeline
->shaders
[i
] &&
242 pipeline
->shaders
[i
]->config
.scratch_bytes_per_wave
) {
243 unsigned max_stage_waves
= device
->scratch_waves
;
245 scratch_bytes_per_wave
= MAX2(scratch_bytes_per_wave
,
246 pipeline
->shaders
[i
]->config
.scratch_bytes_per_wave
);
248 max_stage_waves
= MIN2(max_stage_waves
,
249 4 * device
->physical_device
->rad_info
.num_good_compute_units
*
250 (256 / pipeline
->shaders
[i
]->config
.num_vgprs
));
251 max_waves
= MAX2(max_waves
, max_stage_waves
);
255 if (pipeline
->shaders
[MESA_SHADER_COMPUTE
]) {
256 unsigned group_size
= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[0] *
257 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[1] *
258 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[2];
259 min_waves
= MAX2(min_waves
, round_up_u32(group_size
, 64));
262 pipeline
->scratch_bytes_per_wave
= scratch_bytes_per_wave
;
263 pipeline
->max_waves
= max_waves
;
267 static uint32_t si_translate_blend_logic_op(VkLogicOp op
)
270 case VK_LOGIC_OP_CLEAR
:
271 return V_028808_ROP3_CLEAR
;
272 case VK_LOGIC_OP_AND
:
273 return V_028808_ROP3_AND
;
274 case VK_LOGIC_OP_AND_REVERSE
:
275 return V_028808_ROP3_AND_REVERSE
;
276 case VK_LOGIC_OP_COPY
:
277 return V_028808_ROP3_COPY
;
278 case VK_LOGIC_OP_AND_INVERTED
:
279 return V_028808_ROP3_AND_INVERTED
;
280 case VK_LOGIC_OP_NO_OP
:
281 return V_028808_ROP3_NO_OP
;
282 case VK_LOGIC_OP_XOR
:
283 return V_028808_ROP3_XOR
;
285 return V_028808_ROP3_OR
;
286 case VK_LOGIC_OP_NOR
:
287 return V_028808_ROP3_NOR
;
288 case VK_LOGIC_OP_EQUIVALENT
:
289 return V_028808_ROP3_EQUIVALENT
;
290 case VK_LOGIC_OP_INVERT
:
291 return V_028808_ROP3_INVERT
;
292 case VK_LOGIC_OP_OR_REVERSE
:
293 return V_028808_ROP3_OR_REVERSE
;
294 case VK_LOGIC_OP_COPY_INVERTED
:
295 return V_028808_ROP3_COPY_INVERTED
;
296 case VK_LOGIC_OP_OR_INVERTED
:
297 return V_028808_ROP3_OR_INVERTED
;
298 case VK_LOGIC_OP_NAND
:
299 return V_028808_ROP3_NAND
;
300 case VK_LOGIC_OP_SET
:
301 return V_028808_ROP3_SET
;
303 unreachable("Unhandled logic op");
308 static uint32_t si_translate_blend_function(VkBlendOp op
)
311 case VK_BLEND_OP_ADD
:
312 return V_028780_COMB_DST_PLUS_SRC
;
313 case VK_BLEND_OP_SUBTRACT
:
314 return V_028780_COMB_SRC_MINUS_DST
;
315 case VK_BLEND_OP_REVERSE_SUBTRACT
:
316 return V_028780_COMB_DST_MINUS_SRC
;
317 case VK_BLEND_OP_MIN
:
318 return V_028780_COMB_MIN_DST_SRC
;
319 case VK_BLEND_OP_MAX
:
320 return V_028780_COMB_MAX_DST_SRC
;
326 static uint32_t si_translate_blend_factor(VkBlendFactor factor
)
329 case VK_BLEND_FACTOR_ZERO
:
330 return V_028780_BLEND_ZERO
;
331 case VK_BLEND_FACTOR_ONE
:
332 return V_028780_BLEND_ONE
;
333 case VK_BLEND_FACTOR_SRC_COLOR
:
334 return V_028780_BLEND_SRC_COLOR
;
335 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
336 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
337 case VK_BLEND_FACTOR_DST_COLOR
:
338 return V_028780_BLEND_DST_COLOR
;
339 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
:
340 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
341 case VK_BLEND_FACTOR_SRC_ALPHA
:
342 return V_028780_BLEND_SRC_ALPHA
;
343 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
344 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
345 case VK_BLEND_FACTOR_DST_ALPHA
:
346 return V_028780_BLEND_DST_ALPHA
;
347 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
:
348 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
349 case VK_BLEND_FACTOR_CONSTANT_COLOR
:
350 return V_028780_BLEND_CONSTANT_COLOR
;
351 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
:
352 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
353 case VK_BLEND_FACTOR_CONSTANT_ALPHA
:
354 return V_028780_BLEND_CONSTANT_ALPHA
;
355 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
:
356 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
357 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
358 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
359 case VK_BLEND_FACTOR_SRC1_COLOR
:
360 return V_028780_BLEND_SRC1_COLOR
;
361 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
362 return V_028780_BLEND_INV_SRC1_COLOR
;
363 case VK_BLEND_FACTOR_SRC1_ALPHA
:
364 return V_028780_BLEND_SRC1_ALPHA
;
365 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
366 return V_028780_BLEND_INV_SRC1_ALPHA
;
372 static uint32_t si_translate_blend_opt_function(VkBlendOp op
)
375 case VK_BLEND_OP_ADD
:
376 return V_028760_OPT_COMB_ADD
;
377 case VK_BLEND_OP_SUBTRACT
:
378 return V_028760_OPT_COMB_SUBTRACT
;
379 case VK_BLEND_OP_REVERSE_SUBTRACT
:
380 return V_028760_OPT_COMB_REVSUBTRACT
;
381 case VK_BLEND_OP_MIN
:
382 return V_028760_OPT_COMB_MIN
;
383 case VK_BLEND_OP_MAX
:
384 return V_028760_OPT_COMB_MAX
;
386 return V_028760_OPT_COMB_BLEND_DISABLED
;
390 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor
, bool is_alpha
)
393 case VK_BLEND_FACTOR_ZERO
:
394 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
;
395 case VK_BLEND_FACTOR_ONE
:
396 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
;
397 case VK_BLEND_FACTOR_SRC_COLOR
:
398 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
399 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0
;
400 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
401 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
402 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1
;
403 case VK_BLEND_FACTOR_SRC_ALPHA
:
404 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
;
405 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
406 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
;
407 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
408 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
409 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
411 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
416 * Get rid of DST in the blend factors by commuting the operands:
417 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
419 static void si_blend_remove_dst(unsigned *func
, unsigned *src_factor
,
420 unsigned *dst_factor
, unsigned expected_dst
,
421 unsigned replacement_src
)
423 if (*src_factor
== expected_dst
&&
424 *dst_factor
== VK_BLEND_FACTOR_ZERO
) {
425 *src_factor
= VK_BLEND_FACTOR_ZERO
;
426 *dst_factor
= replacement_src
;
428 /* Commuting the operands requires reversing subtractions. */
429 if (*func
== VK_BLEND_OP_SUBTRACT
)
430 *func
= VK_BLEND_OP_REVERSE_SUBTRACT
;
431 else if (*func
== VK_BLEND_OP_REVERSE_SUBTRACT
)
432 *func
= VK_BLEND_OP_SUBTRACT
;
436 static bool si_blend_factor_uses_dst(unsigned factor
)
438 return factor
== VK_BLEND_FACTOR_DST_COLOR
||
439 factor
== VK_BLEND_FACTOR_DST_ALPHA
||
440 factor
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
441 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
||
442 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
;
445 static bool is_dual_src(VkBlendFactor factor
)
448 case VK_BLEND_FACTOR_SRC1_COLOR
:
449 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
450 case VK_BLEND_FACTOR_SRC1_ALPHA
:
451 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
458 static unsigned radv_choose_spi_color_format(VkFormat vk_format
,
460 bool blend_need_alpha
)
462 const struct vk_format_description
*desc
= vk_format_description(vk_format
);
463 struct ac_spi_color_formats formats
= {};
464 unsigned format
, ntype
, swap
;
466 format
= radv_translate_colorformat(vk_format
);
467 ntype
= radv_translate_color_numformat(vk_format
, desc
,
468 vk_format_get_first_non_void_channel(vk_format
));
469 swap
= radv_translate_colorswap(vk_format
, false);
471 ac_choose_spi_color_formats(format
, swap
, ntype
, false, &formats
);
473 if (blend_enable
&& blend_need_alpha
)
474 return formats
.blend_alpha
;
475 else if(blend_need_alpha
)
476 return formats
.alpha
;
477 else if(blend_enable
)
478 return formats
.blend
;
480 return formats
.normal
;
484 format_is_int8(VkFormat format
)
486 const struct vk_format_description
*desc
= vk_format_description(format
);
487 int channel
= vk_format_get_first_non_void_channel(format
);
489 return channel
>= 0 && desc
->channel
[channel
].pure_integer
&&
490 desc
->channel
[channel
].size
== 8;
494 format_is_int10(VkFormat format
)
496 const struct vk_format_description
*desc
= vk_format_description(format
);
498 if (desc
->nr_channels
!= 4)
500 for (unsigned i
= 0; i
< 4; i
++) {
501 if (desc
->channel
[i
].pure_integer
&& desc
->channel
[i
].size
== 10)
508 radv_pipeline_compute_spi_color_formats(struct radv_pipeline
*pipeline
,
509 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
510 struct radv_blend_state
*blend
)
512 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
513 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
514 unsigned exp_fmt
[MAX_RTS
] = {0};
515 unsigned is_int8
[MAX_RTS
] = {0}, is_int10
[MAX_RTS
] = {0};
516 unsigned col_format
= 0;
517 unsigned col_format_is_int8
= 0, col_format_is_int10
= 0;
519 for (unsigned i
= 0; i
< (blend
->single_cb_enable
? 1 : subpass
->color_count
); ++i
) {
522 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
||
523 !(blend
->cb_target_mask
& (0xfu
<< (i
* 4)))) {
524 cf
= V_028714_SPI_SHADER_ZERO
;
526 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
528 blend
->blend_enable_4bit
& (0xfu
<< (i
* 4));
530 cf
= radv_choose_spi_color_format(attachment
->format
,
532 blend
->need_src_alpha
& (1 << i
));
534 is_int8
[i
] = format_is_int8(attachment
->format
);
535 is_int10
[i
] = format_is_int10(attachment
->format
);
541 if (!exp_fmt
[0] && blend
->need_src_alpha
& (1 << 0)) {
542 /* When a subpass doesn't have any color attachments, write the
543 * alpha channel of MRT0 when alpha coverage is enabled because
544 * the depth attachment needs it.
546 exp_fmt
[0] = V_028714_SPI_SHADER_32_AR
;
549 /* The output for dual source blending should have the same format as
552 if (blend
->mrt0_is_dual_src
) {
553 col_format
|= (exp_fmt
[0] << 4) | exp_fmt
[0];
554 col_format_is_int8
|= (is_int8
[0] << 1) | is_int8
[0];
555 col_format_is_int10
|= (is_int10
[0] << 1) | is_int10
[0];
557 /* Remove holes in SPI_SHADER_COL_FORMAT. */
558 unsigned num_color_targets
= 0;
559 for (unsigned i
= 0; i
< MAX_RTS
; i
++) {
563 col_format
|= exp_fmt
[i
] << (4 * num_color_targets
);
564 col_format_is_int8
|= is_int8
[i
] << num_color_targets
;
565 col_format_is_int10
|= is_int10
[i
] << num_color_targets
;
570 blend
->spi_shader_col_format
= col_format
;
571 blend
->col_format_is_int8
= col_format_is_int8
;
572 blend
->col_format_is_int10
= col_format_is_int10
;
576 * Ordered so that for each i,
577 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
579 const VkFormat radv_fs_key_format_exemplars
[NUM_META_FS_KEYS
] = {
580 VK_FORMAT_R32_SFLOAT
,
581 VK_FORMAT_R32G32_SFLOAT
,
582 VK_FORMAT_R8G8B8A8_UNORM
,
583 VK_FORMAT_R16G16B16A16_UNORM
,
584 VK_FORMAT_R16G16B16A16_SNORM
,
585 VK_FORMAT_R16G16B16A16_UINT
,
586 VK_FORMAT_R16G16B16A16_SINT
,
587 VK_FORMAT_R32G32B32A32_SFLOAT
,
588 VK_FORMAT_R8G8B8A8_UINT
,
589 VK_FORMAT_R8G8B8A8_SINT
,
590 VK_FORMAT_A2R10G10B10_UINT_PACK32
,
591 VK_FORMAT_A2R10G10B10_SINT_PACK32
,
594 unsigned radv_format_meta_fs_key(VkFormat format
)
596 unsigned col_format
= radv_choose_spi_color_format(format
, false, false);
598 assert(col_format
!= V_028714_SPI_SHADER_32_AR
);
599 if (col_format
>= V_028714_SPI_SHADER_32_AR
)
600 --col_format
; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
602 --col_format
; /* Skip V_028714_SPI_SHADER_ZERO */
603 bool is_int8
= format_is_int8(format
);
604 bool is_int10
= format_is_int10(format
);
606 return col_format
+ (is_int8
? 3 : is_int10
? 5 : 0);
610 radv_blend_check_commutativity(struct radv_blend_state
*blend
,
611 VkBlendOp op
, VkBlendFactor src
,
612 VkBlendFactor dst
, unsigned chanmask
)
614 /* Src factor is allowed when it does not depend on Dst. */
615 static const uint32_t src_allowed
=
616 (1u << VK_BLEND_FACTOR_ONE
) |
617 (1u << VK_BLEND_FACTOR_SRC_COLOR
) |
618 (1u << VK_BLEND_FACTOR_SRC_ALPHA
) |
619 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
) |
620 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR
) |
621 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA
) |
622 (1u << VK_BLEND_FACTOR_SRC1_COLOR
) |
623 (1u << VK_BLEND_FACTOR_SRC1_ALPHA
) |
624 (1u << VK_BLEND_FACTOR_ZERO
) |
625 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
) |
626 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
) |
627 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
) |
628 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
) |
629 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
) |
630 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
);
632 if (dst
== VK_BLEND_FACTOR_ONE
&&
633 (src_allowed
& (1u << src
))) {
634 /* Addition is commutative, but floating point addition isn't
635 * associative: subtle changes can be introduced via different
636 * rounding. Be conservative, only enable for min and max.
638 if (op
== VK_BLEND_OP_MAX
|| op
== VK_BLEND_OP_MIN
)
639 blend
->commutative_4bit
|= chanmask
;
643 static struct radv_blend_state
644 radv_pipeline_init_blend_state(struct radv_pipeline
*pipeline
,
645 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
646 const struct radv_graphics_pipeline_create_info
*extra
)
648 const VkPipelineColorBlendStateCreateInfo
*vkblend
= radv_pipeline_get_color_blend_state(pCreateInfo
);
649 const VkPipelineMultisampleStateCreateInfo
*vkms
= radv_pipeline_get_multisample_state(pCreateInfo
);
650 struct radv_blend_state blend
= {0};
651 unsigned mode
= V_028808_CB_NORMAL
;
654 if (extra
&& extra
->custom_blend_mode
) {
655 blend
.single_cb_enable
= true;
656 mode
= extra
->custom_blend_mode
;
659 blend
.cb_color_control
= 0;
661 if (vkblend
->logicOpEnable
)
662 blend
.cb_color_control
|= S_028808_ROP3(si_translate_blend_logic_op(vkblend
->logicOp
));
664 blend
.cb_color_control
|= S_028808_ROP3(V_028808_ROP3_COPY
);
667 blend
.db_alpha_to_mask
= S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
668 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
669 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
670 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
671 S_028B70_OFFSET_ROUND(1);
673 if (vkms
&& vkms
->alphaToCoverageEnable
) {
674 blend
.db_alpha_to_mask
|= S_028B70_ALPHA_TO_MASK_ENABLE(1);
675 blend
.need_src_alpha
|= 0x1;
678 blend
.cb_target_mask
= 0;
680 for (i
= 0; i
< vkblend
->attachmentCount
; i
++) {
681 const VkPipelineColorBlendAttachmentState
*att
= &vkblend
->pAttachments
[i
];
682 unsigned blend_cntl
= 0;
683 unsigned srcRGB_opt
, dstRGB_opt
, srcA_opt
, dstA_opt
;
684 VkBlendOp eqRGB
= att
->colorBlendOp
;
685 VkBlendFactor srcRGB
= att
->srcColorBlendFactor
;
686 VkBlendFactor dstRGB
= att
->dstColorBlendFactor
;
687 VkBlendOp eqA
= att
->alphaBlendOp
;
688 VkBlendFactor srcA
= att
->srcAlphaBlendFactor
;
689 VkBlendFactor dstA
= att
->dstAlphaBlendFactor
;
691 blend
.sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
693 if (!att
->colorWriteMask
)
696 blend
.cb_target_mask
|= (unsigned)att
->colorWriteMask
<< (4 * i
);
697 blend
.cb_target_enabled_4bit
|= 0xf << (4 * i
);
698 if (!att
->blendEnable
) {
699 blend
.cb_blend_control
[i
] = blend_cntl
;
703 if (is_dual_src(srcRGB
) || is_dual_src(dstRGB
) || is_dual_src(srcA
) || is_dual_src(dstA
))
705 blend
.mrt0_is_dual_src
= true;
707 if (eqRGB
== VK_BLEND_OP_MIN
|| eqRGB
== VK_BLEND_OP_MAX
) {
708 srcRGB
= VK_BLEND_FACTOR_ONE
;
709 dstRGB
= VK_BLEND_FACTOR_ONE
;
711 if (eqA
== VK_BLEND_OP_MIN
|| eqA
== VK_BLEND_OP_MAX
) {
712 srcA
= VK_BLEND_FACTOR_ONE
;
713 dstA
= VK_BLEND_FACTOR_ONE
;
716 radv_blend_check_commutativity(&blend
, eqRGB
, srcRGB
, dstRGB
,
718 radv_blend_check_commutativity(&blend
, eqA
, srcA
, dstA
,
721 /* Blending optimizations for RB+.
722 * These transformations don't change the behavior.
724 * First, get rid of DST in the blend factors:
725 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
727 si_blend_remove_dst(&eqRGB
, &srcRGB
, &dstRGB
,
728 VK_BLEND_FACTOR_DST_COLOR
,
729 VK_BLEND_FACTOR_SRC_COLOR
);
731 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
732 VK_BLEND_FACTOR_DST_COLOR
,
733 VK_BLEND_FACTOR_SRC_COLOR
);
735 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
736 VK_BLEND_FACTOR_DST_ALPHA
,
737 VK_BLEND_FACTOR_SRC_ALPHA
);
739 /* Look up the ideal settings from tables. */
740 srcRGB_opt
= si_translate_blend_opt_factor(srcRGB
, false);
741 dstRGB_opt
= si_translate_blend_opt_factor(dstRGB
, false);
742 srcA_opt
= si_translate_blend_opt_factor(srcA
, true);
743 dstA_opt
= si_translate_blend_opt_factor(dstA
, true);
745 /* Handle interdependencies. */
746 if (si_blend_factor_uses_dst(srcRGB
))
747 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
748 if (si_blend_factor_uses_dst(srcA
))
749 dstA_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
751 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
&&
752 (dstRGB
== VK_BLEND_FACTOR_ZERO
||
753 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
754 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
))
755 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
757 /* Set the final value. */
758 blend
.sx_mrt_blend_opt
[i
] =
759 S_028760_COLOR_SRC_OPT(srcRGB_opt
) |
760 S_028760_COLOR_DST_OPT(dstRGB_opt
) |
761 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB
)) |
762 S_028760_ALPHA_SRC_OPT(srcA_opt
) |
763 S_028760_ALPHA_DST_OPT(dstA_opt
) |
764 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA
));
765 blend_cntl
|= S_028780_ENABLE(1);
767 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
768 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
769 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
770 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
771 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
772 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
773 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
774 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
776 blend
.cb_blend_control
[i
] = blend_cntl
;
778 blend
.blend_enable_4bit
|= 0xfu
<< (i
* 4);
780 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
781 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
782 srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
783 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
784 srcRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
||
785 dstRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
)
786 blend
.need_src_alpha
|= 1 << i
;
788 for (i
= vkblend
->attachmentCount
; i
< 8; i
++) {
789 blend
.cb_blend_control
[i
] = 0;
790 blend
.sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
794 if (pipeline
->device
->physical_device
->rad_info
.has_rbplus
) {
795 /* Disable RB+ blend optimizations for dual source blending. */
796 if (blend
.mrt0_is_dual_src
) {
797 for (i
= 0; i
< 8; i
++) {
798 blend
.sx_mrt_blend_opt
[i
] =
799 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE
) |
800 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE
);
804 /* RB+ doesn't work with dual source blending, logic op and
807 if (blend
.mrt0_is_dual_src
||
808 (vkblend
&& vkblend
->logicOpEnable
) ||
809 mode
== V_028808_CB_RESOLVE
)
810 blend
.cb_color_control
|= S_028808_DISABLE_DUAL_QUAD(1);
813 if (blend
.cb_target_mask
)
814 blend
.cb_color_control
|= S_028808_MODE(mode
);
816 blend
.cb_color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
818 radv_pipeline_compute_spi_color_formats(pipeline
, pCreateInfo
, &blend
);
822 static uint32_t si_translate_stencil_op(enum VkStencilOp op
)
825 case VK_STENCIL_OP_KEEP
:
826 return V_02842C_STENCIL_KEEP
;
827 case VK_STENCIL_OP_ZERO
:
828 return V_02842C_STENCIL_ZERO
;
829 case VK_STENCIL_OP_REPLACE
:
830 return V_02842C_STENCIL_REPLACE_TEST
;
831 case VK_STENCIL_OP_INCREMENT_AND_CLAMP
:
832 return V_02842C_STENCIL_ADD_CLAMP
;
833 case VK_STENCIL_OP_DECREMENT_AND_CLAMP
:
834 return V_02842C_STENCIL_SUB_CLAMP
;
835 case VK_STENCIL_OP_INVERT
:
836 return V_02842C_STENCIL_INVERT
;
837 case VK_STENCIL_OP_INCREMENT_AND_WRAP
:
838 return V_02842C_STENCIL_ADD_WRAP
;
839 case VK_STENCIL_OP_DECREMENT_AND_WRAP
:
840 return V_02842C_STENCIL_SUB_WRAP
;
846 static uint32_t si_translate_fill(VkPolygonMode func
)
849 case VK_POLYGON_MODE_FILL
:
850 return V_028814_X_DRAW_TRIANGLES
;
851 case VK_POLYGON_MODE_LINE
:
852 return V_028814_X_DRAW_LINES
;
853 case VK_POLYGON_MODE_POINT
:
854 return V_028814_X_DRAW_POINTS
;
857 return V_028814_X_DRAW_POINTS
;
861 static uint8_t radv_pipeline_get_ps_iter_samples(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
863 const VkPipelineMultisampleStateCreateInfo
*vkms
= pCreateInfo
->pMultisampleState
;
864 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
865 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
866 uint32_t ps_iter_samples
= 1;
867 uint32_t num_samples
;
869 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
871 * "If the VK_AMD_mixed_attachment_samples extension is enabled and the
872 * subpass uses color attachments, totalSamples is the number of
873 * samples of the color attachments. Otherwise, totalSamples is the
874 * value of VkPipelineMultisampleStateCreateInfo::rasterizationSamples
875 * specified at pipeline creation time."
877 if (subpass
->has_color_att
) {
878 num_samples
= subpass
->color_sample_count
;
880 num_samples
= vkms
->rasterizationSamples
;
883 if (vkms
->sampleShadingEnable
) {
884 ps_iter_samples
= ceilf(vkms
->minSampleShading
* num_samples
);
885 ps_iter_samples
= util_next_power_of_two(ps_iter_samples
);
887 return ps_iter_samples
;
891 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
893 return pCreateInfo
->depthTestEnable
&&
894 pCreateInfo
->depthWriteEnable
&&
895 pCreateInfo
->depthCompareOp
!= VK_COMPARE_OP_NEVER
;
899 radv_writes_stencil(const VkStencilOpState
*state
)
901 return state
->writeMask
&&
902 (state
->failOp
!= VK_STENCIL_OP_KEEP
||
903 state
->passOp
!= VK_STENCIL_OP_KEEP
||
904 state
->depthFailOp
!= VK_STENCIL_OP_KEEP
);
908 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
910 return pCreateInfo
->stencilTestEnable
&&
911 (radv_writes_stencil(&pCreateInfo
->front
) ||
912 radv_writes_stencil(&pCreateInfo
->back
));
916 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
918 return radv_is_depth_write_enabled(pCreateInfo
) ||
919 radv_is_stencil_write_enabled(pCreateInfo
);
923 radv_order_invariant_stencil_op(VkStencilOp op
)
925 /* REPLACE is normally order invariant, except when the stencil
926 * reference value is written by the fragment shader. Tracking this
927 * interaction does not seem worth the effort, so be conservative.
929 return op
!= VK_STENCIL_OP_INCREMENT_AND_CLAMP
&&
930 op
!= VK_STENCIL_OP_DECREMENT_AND_CLAMP
&&
931 op
!= VK_STENCIL_OP_REPLACE
;
935 radv_order_invariant_stencil_state(const VkStencilOpState
*state
)
937 /* Compute whether, assuming Z writes are disabled, this stencil state
938 * is order invariant in the sense that the set of passing fragments as
939 * well as the final stencil buffer result does not depend on the order
942 return !state
->writeMask
||
943 /* The following assumes that Z writes are disabled. */
944 (state
->compareOp
== VK_COMPARE_OP_ALWAYS
&&
945 radv_order_invariant_stencil_op(state
->passOp
) &&
946 radv_order_invariant_stencil_op(state
->depthFailOp
)) ||
947 (state
->compareOp
== VK_COMPARE_OP_NEVER
&&
948 radv_order_invariant_stencil_op(state
->failOp
));
952 radv_pipeline_out_of_order_rast(struct radv_pipeline
*pipeline
,
953 struct radv_blend_state
*blend
,
954 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
956 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
957 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
958 const VkPipelineDepthStencilStateCreateInfo
*vkds
= radv_pipeline_get_depth_stencil_state(pCreateInfo
);
959 const VkPipelineColorBlendStateCreateInfo
*vkblend
= radv_pipeline_get_color_blend_state(pCreateInfo
);
960 unsigned colormask
= blend
->cb_target_enabled_4bit
;
962 if (!pipeline
->device
->physical_device
->out_of_order_rast_allowed
)
965 /* Be conservative if a logic operation is enabled with color buffers. */
966 if (colormask
&& vkblend
&& vkblend
->logicOpEnable
)
969 /* Default depth/stencil invariance when no attachment is bound. */
970 struct radv_dsa_order_invariance dsa_order_invariant
= {
971 .zs
= true, .pass_set
= true
975 struct radv_render_pass_attachment
*attachment
=
976 pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
977 bool has_stencil
= vk_format_is_stencil(attachment
->format
);
978 struct radv_dsa_order_invariance order_invariance
[2];
979 struct radv_shader_variant
*ps
=
980 pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
982 /* Compute depth/stencil order invariance in order to know if
983 * it's safe to enable out-of-order.
985 bool zfunc_is_ordered
=
986 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
||
987 vkds
->depthCompareOp
== VK_COMPARE_OP_LESS
||
988 vkds
->depthCompareOp
== VK_COMPARE_OP_LESS_OR_EQUAL
||
989 vkds
->depthCompareOp
== VK_COMPARE_OP_GREATER
||
990 vkds
->depthCompareOp
== VK_COMPARE_OP_GREATER_OR_EQUAL
;
992 bool nozwrite_and_order_invariant_stencil
=
993 !radv_is_ds_write_enabled(vkds
) ||
994 (!radv_is_depth_write_enabled(vkds
) &&
995 radv_order_invariant_stencil_state(&vkds
->front
) &&
996 radv_order_invariant_stencil_state(&vkds
->back
));
998 order_invariance
[1].zs
=
999 nozwrite_and_order_invariant_stencil
||
1000 (!radv_is_stencil_write_enabled(vkds
) &&
1002 order_invariance
[0].zs
=
1003 !radv_is_depth_write_enabled(vkds
) || zfunc_is_ordered
;
1005 order_invariance
[1].pass_set
=
1006 nozwrite_and_order_invariant_stencil
||
1007 (!radv_is_stencil_write_enabled(vkds
) &&
1008 (vkds
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
||
1009 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
));
1010 order_invariance
[0].pass_set
=
1011 !radv_is_depth_write_enabled(vkds
) ||
1012 (vkds
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
||
1013 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
);
1015 dsa_order_invariant
= order_invariance
[has_stencil
];
1016 if (!dsa_order_invariant
.zs
)
1019 /* The set of PS invocations is always order invariant,
1020 * except when early Z/S tests are requested.
1023 ps
->info
.ps
.writes_memory
&&
1024 ps
->info
.ps
.early_fragment_test
&&
1025 !dsa_order_invariant
.pass_set
)
1028 /* Determine if out-of-order rasterization should be disabled
1029 * when occlusion queries are used.
1031 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
=
1032 !dsa_order_invariant
.pass_set
;
1035 /* No color buffers are enabled for writing. */
1039 unsigned blendmask
= colormask
& blend
->blend_enable_4bit
;
1042 /* Only commutative blending. */
1043 if (blendmask
& ~blend
->commutative_4bit
)
1046 if (!dsa_order_invariant
.pass_set
)
1050 if (colormask
& ~blendmask
)
1057 radv_pipeline_init_multisample_state(struct radv_pipeline
*pipeline
,
1058 struct radv_blend_state
*blend
,
1059 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1061 const VkPipelineMultisampleStateCreateInfo
*vkms
= radv_pipeline_get_multisample_state(pCreateInfo
);
1062 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
1063 unsigned num_tile_pipes
= pipeline
->device
->physical_device
->rad_info
.num_tile_pipes
;
1064 bool out_of_order_rast
= false;
1065 int ps_iter_samples
= 1;
1066 uint32_t mask
= 0xffff;
1069 ms
->num_samples
= vkms
->rasterizationSamples
;
1071 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
1073 * "Sample shading is enabled for a graphics pipeline:
1075 * - If the interface of the fragment shader entry point of the
1076 * graphics pipeline includes an input variable decorated
1077 * with SampleId or SamplePosition. In this case
1078 * minSampleShadingFactor takes the value 1.0.
1079 * - Else if the sampleShadingEnable member of the
1080 * VkPipelineMultisampleStateCreateInfo structure specified
1081 * when creating the graphics pipeline is set to VK_TRUE. In
1082 * this case minSampleShadingFactor takes the value of
1083 * VkPipelineMultisampleStateCreateInfo::minSampleShading.
1085 * Otherwise, sample shading is considered disabled."
1087 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.force_persample
) {
1088 ps_iter_samples
= ms
->num_samples
;
1090 ps_iter_samples
= radv_pipeline_get_ps_iter_samples(pCreateInfo
);
1093 ms
->num_samples
= 1;
1096 const struct VkPipelineRasterizationStateRasterizationOrderAMD
*raster_order
=
1097 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD
);
1098 if (raster_order
&& raster_order
->rasterizationOrder
== VK_RASTERIZATION_ORDER_RELAXED_AMD
) {
1099 /* Out-of-order rasterization is explicitly enabled by the
1102 out_of_order_rast
= true;
1104 /* Determine if the driver can enable out-of-order
1105 * rasterization internally.
1108 radv_pipeline_out_of_order_rast(pipeline
, blend
, pCreateInfo
);
1111 ms
->pa_sc_line_cntl
= S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1112 ms
->pa_sc_aa_config
= 0;
1113 ms
->db_eqaa
= S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1114 S_028804_INCOHERENT_EQAA_READS(1) |
1115 S_028804_INTERPOLATE_COMP_Z(1) |
1116 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1117 ms
->pa_sc_mode_cntl_1
=
1118 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1119 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
1120 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast
) |
1121 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1123 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1124 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1125 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1126 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1127 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1128 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1129 ms
->pa_sc_mode_cntl_0
= S_028A48_ALTERNATE_RBS_PER_TILE(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
1130 S_028A48_VPORT_SCISSOR_ENABLE(1);
1132 const VkPipelineRasterizationLineStateCreateInfoEXT
*rast_line
=
1133 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1134 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
);
1136 ms
->pa_sc_mode_cntl_0
|= S_028A48_LINE_STIPPLE_ENABLE(rast_line
->stippledLineEnable
);
1137 if (rast_line
->lineRasterizationMode
== VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT
) {
1138 /* From the Vulkan spec 1.1.129:
1140 * "When VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT lines
1141 * are being rasterized, sample locations may all be
1142 * treated as being at the pixel center (this may
1143 * affect attribute and depth interpolation)."
1145 ms
->num_samples
= 1;
1149 if (ms
->num_samples
> 1) {
1150 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1151 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
1152 uint32_t z_samples
= subpass
->depth_stencil_attachment
? subpass
->depth_sample_count
: ms
->num_samples
;
1153 unsigned log_samples
= util_logbase2(ms
->num_samples
);
1154 unsigned log_z_samples
= util_logbase2(z_samples
);
1155 unsigned log_ps_iter_samples
= util_logbase2(ps_iter_samples
);
1156 ms
->pa_sc_mode_cntl_0
|= S_028A48_MSAA_ENABLE(1);
1157 ms
->pa_sc_line_cntl
|= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1158 ms
->db_eqaa
|= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples
) |
1159 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples
) |
1160 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
1161 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
);
1162 ms
->pa_sc_aa_config
|= S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
1163 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples
)) |
1164 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
) | /* CM_R_028BE0_PA_SC_AA_CONFIG */
1165 S_028BE0_COVERED_CENTROID_IS_CENTER_GFX103(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10_3
);
1166 ms
->pa_sc_mode_cntl_1
|= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1);
1167 if (ps_iter_samples
> 1)
1168 pipeline
->graphics
.spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
1171 if (vkms
&& vkms
->pSampleMask
) {
1172 mask
= vkms
->pSampleMask
[0] & 0xffff;
1175 ms
->pa_sc_aa_mask
[0] = mask
| (mask
<< 16);
1176 ms
->pa_sc_aa_mask
[1] = mask
| (mask
<< 16);
1180 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology
)
1183 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1184 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1185 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1186 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1187 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1189 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1190 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1191 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1192 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1193 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1194 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1197 unreachable("unhandled primitive type");
1202 si_translate_prim(enum VkPrimitiveTopology topology
)
1205 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1206 return V_008958_DI_PT_POINTLIST
;
1207 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1208 return V_008958_DI_PT_LINELIST
;
1209 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1210 return V_008958_DI_PT_LINESTRIP
;
1211 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1212 return V_008958_DI_PT_TRILIST
;
1213 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1214 return V_008958_DI_PT_TRISTRIP
;
1215 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1216 return V_008958_DI_PT_TRIFAN
;
1217 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1218 return V_008958_DI_PT_LINELIST_ADJ
;
1219 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1220 return V_008958_DI_PT_LINESTRIP_ADJ
;
1221 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1222 return V_008958_DI_PT_TRILIST_ADJ
;
1223 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1224 return V_008958_DI_PT_TRISTRIP_ADJ
;
1225 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1226 return V_008958_DI_PT_PATCH
;
1234 si_conv_gl_prim_to_gs_out(unsigned gl_prim
)
1237 case 0: /* GL_POINTS */
1238 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1239 case 1: /* GL_LINES */
1240 case 3: /* GL_LINE_STRIP */
1241 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1242 case 0x8E7A: /* GL_ISOLINES */
1243 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1245 case 4: /* GL_TRIANGLES */
1246 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1247 case 5: /* GL_TRIANGLE_STRIP */
1248 case 7: /* GL_QUADS */
1249 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1257 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology
)
1260 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1261 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1262 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1263 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1264 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1265 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1266 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1267 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1268 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1269 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1270 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1271 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1272 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1273 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1280 static unsigned radv_dynamic_state_mask(VkDynamicState state
)
1283 case VK_DYNAMIC_STATE_VIEWPORT
:
1284 return RADV_DYNAMIC_VIEWPORT
;
1285 case VK_DYNAMIC_STATE_SCISSOR
:
1286 return RADV_DYNAMIC_SCISSOR
;
1287 case VK_DYNAMIC_STATE_LINE_WIDTH
:
1288 return RADV_DYNAMIC_LINE_WIDTH
;
1289 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
1290 return RADV_DYNAMIC_DEPTH_BIAS
;
1291 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
1292 return RADV_DYNAMIC_BLEND_CONSTANTS
;
1293 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
1294 return RADV_DYNAMIC_DEPTH_BOUNDS
;
1295 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
1296 return RADV_DYNAMIC_STENCIL_COMPARE_MASK
;
1297 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
1298 return RADV_DYNAMIC_STENCIL_WRITE_MASK
;
1299 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
1300 return RADV_DYNAMIC_STENCIL_REFERENCE
;
1301 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT
:
1302 return RADV_DYNAMIC_DISCARD_RECTANGLE
;
1303 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT
:
1304 return RADV_DYNAMIC_SAMPLE_LOCATIONS
;
1305 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT
:
1306 return RADV_DYNAMIC_LINE_STIPPLE
;
1308 unreachable("Unhandled dynamic state");
1312 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1314 uint32_t states
= RADV_DYNAMIC_ALL
;
1316 /* If rasterization is disabled we do not care about any of the dynamic states,
1317 * since they are all rasterization related only. */
1318 if (pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
)
1321 if (!pCreateInfo
->pRasterizationState
->depthBiasEnable
)
1322 states
&= ~RADV_DYNAMIC_DEPTH_BIAS
;
1324 if (!pCreateInfo
->pDepthStencilState
||
1325 !pCreateInfo
->pDepthStencilState
->depthBoundsTestEnable
)
1326 states
&= ~RADV_DYNAMIC_DEPTH_BOUNDS
;
1328 if (!pCreateInfo
->pDepthStencilState
||
1329 !pCreateInfo
->pDepthStencilState
->stencilTestEnable
)
1330 states
&= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK
|
1331 RADV_DYNAMIC_STENCIL_WRITE_MASK
|
1332 RADV_DYNAMIC_STENCIL_REFERENCE
);
1334 if (!vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
))
1335 states
&= ~RADV_DYNAMIC_DISCARD_RECTANGLE
;
1337 if (!pCreateInfo
->pMultisampleState
||
1338 !vk_find_struct_const(pCreateInfo
->pMultisampleState
->pNext
,
1339 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
))
1340 states
&= ~RADV_DYNAMIC_SAMPLE_LOCATIONS
;
1342 if (!pCreateInfo
->pRasterizationState
||
1343 !vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1344 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
))
1345 states
&= ~RADV_DYNAMIC_LINE_STIPPLE
;
1347 /* TODO: blend constants & line width. */
1354 radv_pipeline_init_dynamic_state(struct radv_pipeline
*pipeline
,
1355 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1357 uint32_t needed_states
= radv_pipeline_needed_dynamic_state(pCreateInfo
);
1358 uint32_t states
= needed_states
;
1359 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1360 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
1362 pipeline
->dynamic_state
= default_dynamic_state
;
1363 pipeline
->graphics
.needed_dynamic_state
= needed_states
;
1365 if (pCreateInfo
->pDynamicState
) {
1366 /* Remove all of the states that are marked as dynamic */
1367 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1368 for (uint32_t s
= 0; s
< count
; s
++)
1369 states
&= ~radv_dynamic_state_mask(pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1372 struct radv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1374 if (needed_states
& RADV_DYNAMIC_VIEWPORT
) {
1375 assert(pCreateInfo
->pViewportState
);
1377 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1378 if (states
& RADV_DYNAMIC_VIEWPORT
) {
1379 typed_memcpy(dynamic
->viewport
.viewports
,
1380 pCreateInfo
->pViewportState
->pViewports
,
1381 pCreateInfo
->pViewportState
->viewportCount
);
1385 if (needed_states
& RADV_DYNAMIC_SCISSOR
) {
1386 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1387 if (states
& RADV_DYNAMIC_SCISSOR
) {
1388 typed_memcpy(dynamic
->scissor
.scissors
,
1389 pCreateInfo
->pViewportState
->pScissors
,
1390 pCreateInfo
->pViewportState
->scissorCount
);
1394 if (states
& RADV_DYNAMIC_LINE_WIDTH
) {
1395 assert(pCreateInfo
->pRasterizationState
);
1396 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1399 if (states
& RADV_DYNAMIC_DEPTH_BIAS
) {
1400 assert(pCreateInfo
->pRasterizationState
);
1401 dynamic
->depth_bias
.bias
=
1402 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1403 dynamic
->depth_bias
.clamp
=
1404 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1405 dynamic
->depth_bias
.slope
=
1406 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1409 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1411 * pColorBlendState is [...] NULL if the pipeline has rasterization
1412 * disabled or if the subpass of the render pass the pipeline is
1413 * created against does not use any color attachments.
1415 if (subpass
->has_color_att
&& states
& RADV_DYNAMIC_BLEND_CONSTANTS
) {
1416 assert(pCreateInfo
->pColorBlendState
);
1417 typed_memcpy(dynamic
->blend_constants
,
1418 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1421 /* If there is no depthstencil attachment, then don't read
1422 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1423 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1424 * no need to override the depthstencil defaults in
1425 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1427 * Section 9.2 of the Vulkan 1.0.15 spec says:
1429 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1430 * disabled or if the subpass of the render pass the pipeline is created
1431 * against does not use a depth/stencil attachment.
1433 if (needed_states
&& subpass
->depth_stencil_attachment
) {
1434 assert(pCreateInfo
->pDepthStencilState
);
1436 if (states
& RADV_DYNAMIC_DEPTH_BOUNDS
) {
1437 dynamic
->depth_bounds
.min
=
1438 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1439 dynamic
->depth_bounds
.max
=
1440 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1443 if (states
& RADV_DYNAMIC_STENCIL_COMPARE_MASK
) {
1444 dynamic
->stencil_compare_mask
.front
=
1445 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1446 dynamic
->stencil_compare_mask
.back
=
1447 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1450 if (states
& RADV_DYNAMIC_STENCIL_WRITE_MASK
) {
1451 dynamic
->stencil_write_mask
.front
=
1452 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1453 dynamic
->stencil_write_mask
.back
=
1454 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1457 if (states
& RADV_DYNAMIC_STENCIL_REFERENCE
) {
1458 dynamic
->stencil_reference
.front
=
1459 pCreateInfo
->pDepthStencilState
->front
.reference
;
1460 dynamic
->stencil_reference
.back
=
1461 pCreateInfo
->pDepthStencilState
->back
.reference
;
1465 const VkPipelineDiscardRectangleStateCreateInfoEXT
*discard_rectangle_info
=
1466 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
);
1467 if (needed_states
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
1468 dynamic
->discard_rectangle
.count
= discard_rectangle_info
->discardRectangleCount
;
1469 if (states
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
1470 typed_memcpy(dynamic
->discard_rectangle
.rectangles
,
1471 discard_rectangle_info
->pDiscardRectangles
,
1472 discard_rectangle_info
->discardRectangleCount
);
1476 if (needed_states
& RADV_DYNAMIC_SAMPLE_LOCATIONS
) {
1477 const VkPipelineSampleLocationsStateCreateInfoEXT
*sample_location_info
=
1478 vk_find_struct_const(pCreateInfo
->pMultisampleState
->pNext
,
1479 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
);
1480 /* If sampleLocationsEnable is VK_FALSE, the default sample
1481 * locations are used and the values specified in
1482 * sampleLocationsInfo are ignored.
1484 if (sample_location_info
->sampleLocationsEnable
) {
1485 const VkSampleLocationsInfoEXT
*pSampleLocationsInfo
=
1486 &sample_location_info
->sampleLocationsInfo
;
1488 assert(pSampleLocationsInfo
->sampleLocationsCount
<= MAX_SAMPLE_LOCATIONS
);
1490 dynamic
->sample_location
.per_pixel
= pSampleLocationsInfo
->sampleLocationsPerPixel
;
1491 dynamic
->sample_location
.grid_size
= pSampleLocationsInfo
->sampleLocationGridSize
;
1492 dynamic
->sample_location
.count
= pSampleLocationsInfo
->sampleLocationsCount
;
1493 typed_memcpy(&dynamic
->sample_location
.locations
[0],
1494 pSampleLocationsInfo
->pSampleLocations
,
1495 pSampleLocationsInfo
->sampleLocationsCount
);
1499 const VkPipelineRasterizationLineStateCreateInfoEXT
*rast_line_info
=
1500 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1501 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
);
1502 if (needed_states
& RADV_DYNAMIC_LINE_STIPPLE
) {
1503 dynamic
->line_stipple
.factor
= rast_line_info
->lineStippleFactor
;
1504 dynamic
->line_stipple
.pattern
= rast_line_info
->lineStipplePattern
;
1507 pipeline
->dynamic_state
.mask
= states
;
1511 gfx9_get_gs_info(const struct radv_pipeline_key
*key
,
1512 const struct radv_pipeline
*pipeline
,
1514 struct radv_shader_info
*infos
,
1515 struct gfx9_gs_info
*out
)
1517 struct radv_shader_info
*gs_info
= &infos
[MESA_SHADER_GEOMETRY
];
1518 struct radv_es_output_info
*es_info
;
1519 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1520 es_info
= nir
[MESA_SHADER_TESS_CTRL
] ? &gs_info
->tes
.es_info
: &gs_info
->vs
.es_info
;
1522 es_info
= nir
[MESA_SHADER_TESS_CTRL
] ?
1523 &infos
[MESA_SHADER_TESS_EVAL
].tes
.es_info
:
1524 &infos
[MESA_SHADER_VERTEX
].vs
.es_info
;
1526 unsigned gs_num_invocations
= MAX2(gs_info
->gs
.invocations
, 1);
1527 bool uses_adjacency
;
1528 switch(key
->topology
) {
1529 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1530 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1531 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1532 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1533 uses_adjacency
= true;
1536 uses_adjacency
= false;
1540 /* All these are in dwords: */
1541 /* We can't allow using the whole LDS, because GS waves compete with
1542 * other shader stages for LDS space. */
1543 const unsigned max_lds_size
= 8 * 1024;
1544 const unsigned esgs_itemsize
= es_info
->esgs_itemsize
/ 4;
1545 unsigned esgs_lds_size
;
1547 /* All these are per subgroup: */
1548 const unsigned max_out_prims
= 32 * 1024;
1549 const unsigned max_es_verts
= 255;
1550 const unsigned ideal_gs_prims
= 64;
1551 unsigned max_gs_prims
, gs_prims
;
1552 unsigned min_es_verts
, es_verts
, worst_case_es_verts
;
1554 if (uses_adjacency
|| gs_num_invocations
> 1)
1555 max_gs_prims
= 127 / gs_num_invocations
;
1559 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1560 * Make sure we don't go over the maximum value.
1562 if (gs_info
->gs
.vertices_out
> 0) {
1563 max_gs_prims
= MIN2(max_gs_prims
,
1565 (gs_info
->gs
.vertices_out
* gs_num_invocations
));
1567 assert(max_gs_prims
> 0);
1569 /* If the primitive has adjacency, halve the number of vertices
1570 * that will be reused in multiple primitives.
1572 min_es_verts
= gs_info
->gs
.vertices_in
/ (uses_adjacency
? 2 : 1);
1574 gs_prims
= MIN2(ideal_gs_prims
, max_gs_prims
);
1575 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
, max_es_verts
);
1577 /* Compute ESGS LDS size based on the worst case number of ES vertices
1578 * needed to create the target number of GS prims per subgroup.
1580 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
1582 /* If total LDS usage is too big, refactor partitions based on ratio
1583 * of ESGS item sizes.
1585 if (esgs_lds_size
> max_lds_size
) {
1586 /* Our target GS Prims Per Subgroup was too large. Calculate
1587 * the maximum number of GS Prims Per Subgroup that will fit
1588 * into LDS, capped by the maximum that the hardware can support.
1590 gs_prims
= MIN2((max_lds_size
/ (esgs_itemsize
* min_es_verts
)),
1592 assert(gs_prims
> 0);
1593 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
,
1596 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
1597 assert(esgs_lds_size
<= max_lds_size
);
1600 /* Now calculate remaining ESGS information. */
1602 es_verts
= MIN2(esgs_lds_size
/ esgs_itemsize
, max_es_verts
);
1604 es_verts
= max_es_verts
;
1606 /* Vertices for adjacency primitives are not always reused, so restore
1607 * it for ES_VERTS_PER_SUBGRP.
1609 min_es_verts
= gs_info
->gs
.vertices_in
;
1611 /* For normal primitives, the VGT only checks if they are past the ES
1612 * verts per subgroup after allocating a full GS primitive and if they
1613 * are, kick off a new subgroup. But if those additional ES verts are
1614 * unique (e.g. not reused) we need to make sure there is enough LDS
1615 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1617 es_verts
-= min_es_verts
- 1;
1619 uint32_t es_verts_per_subgroup
= es_verts
;
1620 uint32_t gs_prims_per_subgroup
= gs_prims
;
1621 uint32_t gs_inst_prims_in_subgroup
= gs_prims
* gs_num_invocations
;
1622 uint32_t max_prims_per_subgroup
= gs_inst_prims_in_subgroup
* gs_info
->gs
.vertices_out
;
1623 out
->lds_size
= align(esgs_lds_size
, 128) / 128;
1624 out
->vgt_gs_onchip_cntl
= S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup
) |
1625 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup
) |
1626 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup
);
1627 out
->vgt_gs_max_prims_per_subgroup
= S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup
);
1628 out
->vgt_esgs_ring_itemsize
= esgs_itemsize
;
1629 assert(max_prims_per_subgroup
<= max_out_prims
);
1632 static void clamp_gsprims_to_esverts(unsigned *max_gsprims
, unsigned max_esverts
,
1633 unsigned min_verts_per_prim
, bool use_adjacency
)
1635 unsigned max_reuse
= max_esverts
- min_verts_per_prim
;
1638 *max_gsprims
= MIN2(*max_gsprims
, 1 + max_reuse
);
1642 radv_get_num_input_vertices(nir_shader
**nir
)
1644 if (nir
[MESA_SHADER_GEOMETRY
]) {
1645 nir_shader
*gs
= nir
[MESA_SHADER_GEOMETRY
];
1647 return gs
->info
.gs
.vertices_in
;
1650 if (nir
[MESA_SHADER_TESS_CTRL
]) {
1651 nir_shader
*tes
= nir
[MESA_SHADER_TESS_EVAL
];
1653 if (tes
->info
.tess
.point_mode
)
1655 if (tes
->info
.tess
.primitive_mode
== GL_ISOLINES
)
1664 gfx10_get_ngg_info(const struct radv_pipeline_key
*key
,
1665 struct radv_pipeline
*pipeline
,
1667 struct radv_shader_info
*infos
,
1668 struct gfx10_ngg_info
*ngg
)
1670 struct radv_shader_info
*gs_info
= &infos
[MESA_SHADER_GEOMETRY
];
1671 struct radv_es_output_info
*es_info
=
1672 nir
[MESA_SHADER_TESS_CTRL
] ? &gs_info
->tes
.es_info
: &gs_info
->vs
.es_info
;
1673 unsigned gs_type
= nir
[MESA_SHADER_GEOMETRY
] ? MESA_SHADER_GEOMETRY
: MESA_SHADER_VERTEX
;
1674 unsigned max_verts_per_prim
= radv_get_num_input_vertices(nir
);
1675 unsigned min_verts_per_prim
=
1676 gs_type
== MESA_SHADER_GEOMETRY
? max_verts_per_prim
: 1;
1677 unsigned gs_num_invocations
= nir
[MESA_SHADER_GEOMETRY
] ? MAX2(gs_info
->gs
.invocations
, 1) : 1;
1678 bool uses_adjacency
;
1679 switch(key
->topology
) {
1680 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1681 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1682 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1683 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1684 uses_adjacency
= true;
1687 uses_adjacency
= false;
1691 /* All these are in dwords: */
1692 /* We can't allow using the whole LDS, because GS waves compete with
1693 * other shader stages for LDS space.
1695 * TODO: We should really take the shader's internal LDS use into
1696 * account. The linker will fail if the size is greater than
1699 const unsigned max_lds_size
= 8 * 1024 - 768;
1700 const unsigned target_lds_size
= max_lds_size
;
1701 unsigned esvert_lds_size
= 0;
1702 unsigned gsprim_lds_size
= 0;
1704 /* All these are per subgroup: */
1705 bool max_vert_out_per_gs_instance
= false;
1706 unsigned max_esverts_base
= 256;
1707 unsigned max_gsprims_base
= 128; /* default prim group size clamp */
1709 /* Hardware has the following non-natural restrictions on the value
1710 * of GE_CNTL.VERT_GRP_SIZE based on based on the primitive type of
1712 * - at most 252 for any line input primitive type
1713 * - at most 251 for any quad input primitive type
1714 * - at most 251 for triangle strips with adjacency (this happens to
1715 * be the natural limit for triangle *lists* with adjacency)
1717 max_esverts_base
= MIN2(max_esverts_base
, 251 + max_verts_per_prim
- 1);
1719 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1720 unsigned max_out_verts_per_gsprim
=
1721 gs_info
->gs
.vertices_out
* gs_num_invocations
;
1723 if (max_out_verts_per_gsprim
<= 256) {
1724 if (max_out_verts_per_gsprim
) {
1725 max_gsprims_base
= MIN2(max_gsprims_base
,
1726 256 / max_out_verts_per_gsprim
);
1729 /* Use special multi-cycling mode in which each GS
1730 * instance gets its own subgroup. Does not work with
1732 max_vert_out_per_gs_instance
= true;
1733 max_gsprims_base
= 1;
1734 max_out_verts_per_gsprim
= gs_info
->gs
.vertices_out
;
1737 esvert_lds_size
= es_info
->esgs_itemsize
/ 4;
1738 gsprim_lds_size
= (gs_info
->gs
.gsvs_vertex_size
/ 4 + 1) * max_out_verts_per_gsprim
;
1741 /* LDS size for passing data from GS to ES. */
1742 struct radv_streamout_info
*so_info
= nir
[MESA_SHADER_TESS_CTRL
]
1743 ? &infos
[MESA_SHADER_TESS_EVAL
].so
1744 : &infos
[MESA_SHADER_VERTEX
].so
;
1746 if (so_info
->num_outputs
)
1747 esvert_lds_size
= 4 * so_info
->num_outputs
+ 1;
1749 /* GS stores Primitive IDs (one DWORD) into LDS at the address
1750 * corresponding to the ES thread of the provoking vertex. All
1751 * ES threads load and export PrimitiveID for their thread.
1753 if (!nir
[MESA_SHADER_TESS_CTRL
] &&
1754 infos
[MESA_SHADER_VERTEX
].vs
.outinfo
.export_prim_id
)
1755 esvert_lds_size
= MAX2(esvert_lds_size
, 1);
1758 unsigned max_gsprims
= max_gsprims_base
;
1759 unsigned max_esverts
= max_esverts_base
;
1761 if (esvert_lds_size
)
1762 max_esverts
= MIN2(max_esverts
, target_lds_size
/ esvert_lds_size
);
1763 if (gsprim_lds_size
)
1764 max_gsprims
= MIN2(max_gsprims
, target_lds_size
/ gsprim_lds_size
);
1766 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1767 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
, min_verts_per_prim
, uses_adjacency
);
1768 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1770 if (esvert_lds_size
|| gsprim_lds_size
) {
1771 /* Now that we have a rough proportionality between esverts
1772 * and gsprims based on the primitive type, scale both of them
1773 * down simultaneously based on required LDS space.
1775 * We could be smarter about this if we knew how much vertex
1778 unsigned lds_total
= max_esverts
* esvert_lds_size
+
1779 max_gsprims
* gsprim_lds_size
;
1780 if (lds_total
> target_lds_size
) {
1781 max_esverts
= max_esverts
* target_lds_size
/ lds_total
;
1782 max_gsprims
= max_gsprims
* target_lds_size
/ lds_total
;
1784 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1785 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
,
1786 min_verts_per_prim
, uses_adjacency
);
1787 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1791 /* Round up towards full wave sizes for better ALU utilization. */
1792 if (!max_vert_out_per_gs_instance
) {
1793 unsigned orig_max_esverts
;
1794 unsigned orig_max_gsprims
;
1797 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1798 wavesize
= gs_info
->wave_size
;
1800 wavesize
= nir
[MESA_SHADER_TESS_CTRL
]
1801 ? infos
[MESA_SHADER_TESS_EVAL
].wave_size
1802 : infos
[MESA_SHADER_VERTEX
].wave_size
;
1806 orig_max_esverts
= max_esverts
;
1807 orig_max_gsprims
= max_gsprims
;
1809 max_esverts
= align(max_esverts
, wavesize
);
1810 max_esverts
= MIN2(max_esverts
, max_esverts_base
);
1811 if (esvert_lds_size
)
1812 max_esverts
= MIN2(max_esverts
,
1813 (max_lds_size
- max_gsprims
* gsprim_lds_size
) /
1815 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1817 max_gsprims
= align(max_gsprims
, wavesize
);
1818 max_gsprims
= MIN2(max_gsprims
, max_gsprims_base
);
1819 if (gsprim_lds_size
)
1820 max_gsprims
= MIN2(max_gsprims
,
1821 (max_lds_size
- max_esverts
* esvert_lds_size
) /
1823 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
,
1824 min_verts_per_prim
, uses_adjacency
);
1825 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1826 } while (orig_max_esverts
!= max_esverts
|| orig_max_gsprims
!= max_gsprims
);
1829 /* Hardware restriction: minimum value of max_esverts */
1830 max_esverts
= MAX2(max_esverts
, 23 + max_verts_per_prim
);
1832 unsigned max_out_vertices
=
1833 max_vert_out_per_gs_instance
? gs_info
->gs
.vertices_out
:
1834 gs_type
== MESA_SHADER_GEOMETRY
?
1835 max_gsprims
* gs_num_invocations
* gs_info
->gs
.vertices_out
:
1837 assert(max_out_vertices
<= 256);
1839 unsigned prim_amp_factor
= 1;
1840 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1841 /* Number of output primitives per GS input primitive after
1843 prim_amp_factor
= gs_info
->gs
.vertices_out
;
1846 /* The GE only checks against the maximum number of ES verts after
1847 * allocating a full GS primitive. So we need to ensure that whenever
1848 * this check passes, there is enough space for a full primitive without
1851 ngg
->hw_max_esverts
= max_esverts
- max_verts_per_prim
+ 1;
1852 ngg
->max_gsprims
= max_gsprims
;
1853 ngg
->max_out_verts
= max_out_vertices
;
1854 ngg
->prim_amp_factor
= prim_amp_factor
;
1855 ngg
->max_vert_out_per_gs_instance
= max_vert_out_per_gs_instance
;
1856 ngg
->ngg_emit_size
= max_gsprims
* gsprim_lds_size
;
1857 ngg
->esgs_ring_size
= 4 * max_esverts
* esvert_lds_size
;
1859 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1860 ngg
->vgt_esgs_ring_itemsize
= es_info
->esgs_itemsize
/ 4;
1862 ngg
->vgt_esgs_ring_itemsize
= 1;
1865 pipeline
->graphics
.esgs_ring_size
= ngg
->esgs_ring_size
;
1867 assert(ngg
->hw_max_esverts
>= 24); /* HW limitation */
1871 calculate_gs_ring_sizes(struct radv_pipeline
*pipeline
,
1872 const struct gfx9_gs_info
*gs
)
1874 struct radv_device
*device
= pipeline
->device
;
1875 unsigned num_se
= device
->physical_device
->rad_info
.max_se
;
1876 unsigned wave_size
= 64;
1877 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
1878 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
1879 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
1881 unsigned gs_vertex_reuse
=
1882 (device
->physical_device
->rad_info
.chip_class
>= GFX8
? 32 : 16) * num_se
;
1883 unsigned alignment
= 256 * num_se
;
1884 /* The maximum size is 63.999 MB per SE. */
1885 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
1886 struct radv_shader_info
*gs_info
= &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
;
1888 /* Calculate the minimum size. */
1889 unsigned min_esgs_ring_size
= align(gs
->vgt_esgs_ring_itemsize
* 4 * gs_vertex_reuse
*
1890 wave_size
, alignment
);
1891 /* These are recommended sizes, not minimum sizes. */
1892 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
1893 gs
->vgt_esgs_ring_itemsize
* 4 * gs_info
->gs
.vertices_in
;
1894 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
1895 gs_info
->gs
.max_gsvs_emit_size
;
1897 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
1898 esgs_ring_size
= align(esgs_ring_size
, alignment
);
1899 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
1901 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
)
1902 pipeline
->graphics
.esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
1904 pipeline
->graphics
.gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
1907 static void si_multiwave_lds_size_workaround(struct radv_device
*device
,
1910 /* If tessellation is all offchip and on-chip GS isn't used, this
1911 * workaround is not needed.
1915 /* SPI barrier management bug:
1916 * Make sure we have at least 4k of LDS in use to avoid the bug.
1917 * It applies to workgroup sizes of more than one wavefront.
1919 if (device
->physical_device
->rad_info
.family
== CHIP_BONAIRE
||
1920 device
->physical_device
->rad_info
.family
== CHIP_KABINI
)
1921 *lds_size
= MAX2(*lds_size
, 8);
1924 struct radv_shader_variant
*
1925 radv_get_shader(struct radv_pipeline
*pipeline
,
1926 gl_shader_stage stage
)
1928 if (stage
== MESA_SHADER_VERTEX
) {
1929 if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
1930 return pipeline
->shaders
[MESA_SHADER_VERTEX
];
1931 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
])
1932 return pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
1933 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
1934 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
1935 } else if (stage
== MESA_SHADER_TESS_EVAL
) {
1936 if (!radv_pipeline_has_tess(pipeline
))
1938 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
1939 return pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
1940 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
1941 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
1943 return pipeline
->shaders
[stage
];
1946 static struct radv_tessellation_state
1947 calculate_tess_state(struct radv_pipeline
*pipeline
,
1948 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1950 unsigned num_tcs_input_cp
;
1951 unsigned num_tcs_output_cp
;
1953 unsigned num_patches
;
1954 struct radv_tessellation_state tess
= {0};
1956 num_tcs_input_cp
= pCreateInfo
->pTessellationState
->patchControlPoints
;
1957 num_tcs_output_cp
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.tcs_vertices_out
; //TCS VERTICES OUT
1958 num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
1960 lds_size
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.lds_size
;
1962 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
1963 assert(lds_size
<= 65536);
1964 lds_size
= align(lds_size
, 512) / 512;
1966 assert(lds_size
<= 32768);
1967 lds_size
= align(lds_size
, 256) / 256;
1969 si_multiwave_lds_size_workaround(pipeline
->device
, &lds_size
);
1971 tess
.lds_size
= lds_size
;
1973 tess
.ls_hs_config
= S_028B58_NUM_PATCHES(num_patches
) |
1974 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp
) |
1975 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp
);
1976 tess
.num_patches
= num_patches
;
1978 struct radv_shader_variant
*tes
= radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
);
1979 unsigned type
= 0, partitioning
= 0, topology
= 0, distribution_mode
= 0;
1981 switch (tes
->info
.tes
.primitive_mode
) {
1983 type
= V_028B6C_TESS_TRIANGLE
;
1986 type
= V_028B6C_TESS_QUAD
;
1989 type
= V_028B6C_TESS_ISOLINE
;
1993 switch (tes
->info
.tes
.spacing
) {
1994 case TESS_SPACING_EQUAL
:
1995 partitioning
= V_028B6C_PART_INTEGER
;
1997 case TESS_SPACING_FRACTIONAL_ODD
:
1998 partitioning
= V_028B6C_PART_FRAC_ODD
;
2000 case TESS_SPACING_FRACTIONAL_EVEN
:
2001 partitioning
= V_028B6C_PART_FRAC_EVEN
;
2007 bool ccw
= tes
->info
.tes
.ccw
;
2008 const VkPipelineTessellationDomainOriginStateCreateInfo
*domain_origin_state
=
2009 vk_find_struct_const(pCreateInfo
->pTessellationState
,
2010 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO
);
2012 if (domain_origin_state
&& domain_origin_state
->domainOrigin
!= VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT
)
2015 if (tes
->info
.tes
.point_mode
)
2016 topology
= V_028B6C_OUTPUT_POINT
;
2017 else if (tes
->info
.tes
.primitive_mode
== GL_ISOLINES
)
2018 topology
= V_028B6C_OUTPUT_LINE
;
2020 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
2022 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
2024 if (pipeline
->device
->physical_device
->rad_info
.has_distributed_tess
) {
2025 if (pipeline
->device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
2026 pipeline
->device
->physical_device
->rad_info
.family
>= CHIP_POLARIS10
)
2027 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
2029 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
2031 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
2033 tess
.tf_param
= S_028B6C_TYPE(type
) |
2034 S_028B6C_PARTITIONING(partitioning
) |
2035 S_028B6C_TOPOLOGY(topology
) |
2036 S_028B6C_DISTRIBUTION_MODE(distribution_mode
);
2041 static const struct radv_prim_vertex_count prim_size_table
[] = {
2042 [V_008958_DI_PT_NONE
] = {0, 0},
2043 [V_008958_DI_PT_POINTLIST
] = {1, 1},
2044 [V_008958_DI_PT_LINELIST
] = {2, 2},
2045 [V_008958_DI_PT_LINESTRIP
] = {2, 1},
2046 [V_008958_DI_PT_TRILIST
] = {3, 3},
2047 [V_008958_DI_PT_TRIFAN
] = {3, 1},
2048 [V_008958_DI_PT_TRISTRIP
] = {3, 1},
2049 [V_008958_DI_PT_LINELIST_ADJ
] = {4, 4},
2050 [V_008958_DI_PT_LINESTRIP_ADJ
] = {4, 1},
2051 [V_008958_DI_PT_TRILIST_ADJ
] = {6, 6},
2052 [V_008958_DI_PT_TRISTRIP_ADJ
] = {6, 2},
2053 [V_008958_DI_PT_RECTLIST
] = {3, 3},
2054 [V_008958_DI_PT_LINELOOP
] = {2, 1},
2055 [V_008958_DI_PT_POLYGON
] = {3, 1},
2056 [V_008958_DI_PT_2D_TRI_STRIP
] = {0, 0},
2059 static const struct radv_vs_output_info
*get_vs_output_info(const struct radv_pipeline
*pipeline
)
2061 if (radv_pipeline_has_gs(pipeline
))
2062 if (radv_pipeline_has_ngg(pipeline
))
2063 return &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.vs
.outinfo
;
2065 return &pipeline
->gs_copy_shader
->info
.vs
.outinfo
;
2066 else if (radv_pipeline_has_tess(pipeline
))
2067 return &pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.outinfo
;
2069 return &pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.outinfo
;
2073 radv_link_shaders(struct radv_pipeline
*pipeline
, nir_shader
**shaders
)
2075 nir_shader
* ordered_shaders
[MESA_SHADER_STAGES
];
2076 int shader_count
= 0;
2078 if(shaders
[MESA_SHADER_FRAGMENT
]) {
2079 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_FRAGMENT
];
2081 if(shaders
[MESA_SHADER_GEOMETRY
]) {
2082 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_GEOMETRY
];
2084 if(shaders
[MESA_SHADER_TESS_EVAL
]) {
2085 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_EVAL
];
2087 if(shaders
[MESA_SHADER_TESS_CTRL
]) {
2088 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_CTRL
];
2090 if(shaders
[MESA_SHADER_VERTEX
]) {
2091 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_VERTEX
];
2094 if (shader_count
> 1) {
2095 unsigned first
= ordered_shaders
[shader_count
- 1]->info
.stage
;
2096 unsigned last
= ordered_shaders
[0]->info
.stage
;
2098 if (ordered_shaders
[0]->info
.stage
== MESA_SHADER_FRAGMENT
&&
2099 ordered_shaders
[1]->info
.has_transform_feedback_varyings
)
2100 nir_link_xfb_varyings(ordered_shaders
[1], ordered_shaders
[0]);
2102 for (int i
= 0; i
< shader_count
; ++i
) {
2103 nir_variable_mode mask
= 0;
2105 if (ordered_shaders
[i
]->info
.stage
!= first
)
2106 mask
= mask
| nir_var_shader_in
;
2108 if (ordered_shaders
[i
]->info
.stage
!= last
)
2109 mask
= mask
| nir_var_shader_out
;
2111 nir_lower_io_to_scalar_early(ordered_shaders
[i
], mask
);
2112 radv_optimize_nir(ordered_shaders
[i
], false, false);
2116 for (int i
= 1; i
< shader_count
; ++i
) {
2117 nir_lower_io_arrays_to_elements(ordered_shaders
[i
],
2118 ordered_shaders
[i
- 1]);
2120 if (nir_link_opt_varyings(ordered_shaders
[i
],
2121 ordered_shaders
[i
- 1]))
2122 radv_optimize_nir(ordered_shaders
[i
- 1], false, false);
2124 nir_remove_dead_variables(ordered_shaders
[i
],
2125 nir_var_shader_out
, NULL
);
2126 nir_remove_dead_variables(ordered_shaders
[i
- 1],
2127 nir_var_shader_in
, NULL
);
2129 bool progress
= nir_remove_unused_varyings(ordered_shaders
[i
],
2130 ordered_shaders
[i
- 1]);
2132 nir_compact_varyings(ordered_shaders
[i
],
2133 ordered_shaders
[i
- 1], true);
2136 if (nir_lower_global_vars_to_local(ordered_shaders
[i
])) {
2137 ac_lower_indirect_derefs(ordered_shaders
[i
],
2138 pipeline
->device
->physical_device
->rad_info
.chip_class
);
2140 radv_optimize_nir(ordered_shaders
[i
], false, false);
2142 if (nir_lower_global_vars_to_local(ordered_shaders
[i
- 1])) {
2143 ac_lower_indirect_derefs(ordered_shaders
[i
- 1],
2144 pipeline
->device
->physical_device
->rad_info
.chip_class
);
2146 radv_optimize_nir(ordered_shaders
[i
- 1], false, false);
2152 radv_set_linked_driver_locations(struct radv_pipeline
*pipeline
, nir_shader
**shaders
,
2153 struct radv_shader_info infos
[MESA_SHADER_STAGES
])
2155 bool has_tess
= shaders
[MESA_SHADER_TESS_CTRL
];
2156 bool has_gs
= shaders
[MESA_SHADER_GEOMETRY
];
2158 if (!has_tess
&& !has_gs
)
2161 unsigned vs_info_idx
= MESA_SHADER_VERTEX
;
2162 unsigned tes_info_idx
= MESA_SHADER_TESS_EVAL
;
2164 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2165 /* These are merged into the next stage */
2166 vs_info_idx
= has_tess
? MESA_SHADER_TESS_CTRL
: MESA_SHADER_GEOMETRY
;
2167 tes_info_idx
= has_gs
? MESA_SHADER_GEOMETRY
: MESA_SHADER_TESS_EVAL
;
2171 nir_linked_io_var_info vs2tcs
=
2172 nir_assign_linked_io_var_locations(shaders
[MESA_SHADER_VERTEX
], shaders
[MESA_SHADER_TESS_CTRL
]);
2173 nir_linked_io_var_info tcs2tes
=
2174 nir_assign_linked_io_var_locations(shaders
[MESA_SHADER_TESS_CTRL
], shaders
[MESA_SHADER_TESS_EVAL
]);
2176 infos
[vs_info_idx
].vs
.num_linked_outputs
= vs2tcs
.num_linked_io_vars
;
2177 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_linked_inputs
= vs2tcs
.num_linked_io_vars
;
2178 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_linked_outputs
= tcs2tes
.num_linked_io_vars
;
2179 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_linked_patch_outputs
= tcs2tes
.num_linked_patch_io_vars
;
2180 infos
[tes_info_idx
].tes
.num_linked_inputs
= tcs2tes
.num_linked_io_vars
;
2181 infos
[tes_info_idx
].tes
.num_linked_patch_inputs
= tcs2tes
.num_linked_patch_io_vars
;
2184 nir_linked_io_var_info tes2gs
=
2185 nir_assign_linked_io_var_locations(shaders
[MESA_SHADER_TESS_EVAL
], shaders
[MESA_SHADER_GEOMETRY
]);
2187 infos
[tes_info_idx
].tes
.num_linked_outputs
= tes2gs
.num_linked_io_vars
;
2188 infos
[MESA_SHADER_GEOMETRY
].gs
.num_linked_inputs
= tes2gs
.num_linked_io_vars
;
2190 } else if (has_gs
) {
2191 nir_linked_io_var_info vs2gs
=
2192 nir_assign_linked_io_var_locations(shaders
[MESA_SHADER_VERTEX
], shaders
[MESA_SHADER_GEOMETRY
]);
2194 infos
[vs_info_idx
].vs
.num_linked_outputs
= vs2gs
.num_linked_io_vars
;
2195 infos
[MESA_SHADER_GEOMETRY
].gs
.num_linked_inputs
= vs2gs
.num_linked_io_vars
;
2200 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo
*input_state
,
2201 uint32_t attrib_binding
)
2203 for (uint32_t i
= 0; i
< input_state
->vertexBindingDescriptionCount
; i
++) {
2204 const VkVertexInputBindingDescription
*input_binding
=
2205 &input_state
->pVertexBindingDescriptions
[i
];
2207 if (input_binding
->binding
== attrib_binding
)
2208 return input_binding
->stride
;
2214 static struct radv_pipeline_key
2215 radv_generate_graphics_pipeline_key(struct radv_pipeline
*pipeline
,
2216 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2217 const struct radv_blend_state
*blend
,
2218 bool has_view_index
)
2220 const VkPipelineVertexInputStateCreateInfo
*input_state
=
2221 pCreateInfo
->pVertexInputState
;
2222 const VkPipelineVertexInputDivisorStateCreateInfoEXT
*divisor_state
=
2223 vk_find_struct_const(input_state
->pNext
, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT
);
2225 struct radv_pipeline_key key
;
2226 memset(&key
, 0, sizeof(key
));
2228 if (pCreateInfo
->flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
)
2229 key
.optimisations_disabled
= 1;
2231 key
.has_multiview_view_index
= has_view_index
;
2233 uint32_t binding_input_rate
= 0;
2234 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
2235 for (unsigned i
= 0; i
< input_state
->vertexBindingDescriptionCount
; ++i
) {
2236 if (input_state
->pVertexBindingDescriptions
[i
].inputRate
) {
2237 unsigned binding
= input_state
->pVertexBindingDescriptions
[i
].binding
;
2238 binding_input_rate
|= 1u << binding
;
2239 instance_rate_divisors
[binding
] = 1;
2242 if (divisor_state
) {
2243 for (unsigned i
= 0; i
< divisor_state
->vertexBindingDivisorCount
; ++i
) {
2244 instance_rate_divisors
[divisor_state
->pVertexBindingDivisors
[i
].binding
] =
2245 divisor_state
->pVertexBindingDivisors
[i
].divisor
;
2249 for (unsigned i
= 0; i
< input_state
->vertexAttributeDescriptionCount
; ++i
) {
2250 const VkVertexInputAttributeDescription
*desc
=
2251 &input_state
->pVertexAttributeDescriptions
[i
];
2252 const struct vk_format_description
*format_desc
;
2253 unsigned location
= desc
->location
;
2254 unsigned binding
= desc
->binding
;
2255 unsigned num_format
, data_format
;
2258 if (binding_input_rate
& (1u << binding
)) {
2259 key
.instance_rate_inputs
|= 1u << location
;
2260 key
.instance_rate_divisors
[location
] = instance_rate_divisors
[binding
];
2263 format_desc
= vk_format_description(desc
->format
);
2264 first_non_void
= vk_format_get_first_non_void_channel(desc
->format
);
2266 num_format
= radv_translate_buffer_numformat(format_desc
, first_non_void
);
2267 data_format
= radv_translate_buffer_dataformat(format_desc
, first_non_void
);
2269 key
.vertex_attribute_formats
[location
] = data_format
| (num_format
<< 4);
2270 key
.vertex_attribute_bindings
[location
] = desc
->binding
;
2271 key
.vertex_attribute_offsets
[location
] = desc
->offset
;
2272 key
.vertex_attribute_strides
[location
] = radv_get_attrib_stride(input_state
, desc
->binding
);
2274 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
&&
2275 pipeline
->device
->physical_device
->rad_info
.family
!= CHIP_STONEY
) {
2276 VkFormat format
= input_state
->pVertexAttributeDescriptions
[i
].format
;
2279 case VK_FORMAT_A2R10G10B10_SNORM_PACK32
:
2280 case VK_FORMAT_A2B10G10R10_SNORM_PACK32
:
2281 adjust
= RADV_ALPHA_ADJUST_SNORM
;
2283 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32
:
2284 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32
:
2285 adjust
= RADV_ALPHA_ADJUST_SSCALED
;
2287 case VK_FORMAT_A2R10G10B10_SINT_PACK32
:
2288 case VK_FORMAT_A2B10G10R10_SINT_PACK32
:
2289 adjust
= RADV_ALPHA_ADJUST_SINT
;
2295 key
.vertex_alpha_adjust
|= adjust
<< (2 * location
);
2298 switch (desc
->format
) {
2299 case VK_FORMAT_B8G8R8A8_UNORM
:
2300 case VK_FORMAT_B8G8R8A8_SNORM
:
2301 case VK_FORMAT_B8G8R8A8_USCALED
:
2302 case VK_FORMAT_B8G8R8A8_SSCALED
:
2303 case VK_FORMAT_B8G8R8A8_UINT
:
2304 case VK_FORMAT_B8G8R8A8_SINT
:
2305 case VK_FORMAT_B8G8R8A8_SRGB
:
2306 case VK_FORMAT_A2R10G10B10_UNORM_PACK32
:
2307 case VK_FORMAT_A2R10G10B10_SNORM_PACK32
:
2308 case VK_FORMAT_A2R10G10B10_USCALED_PACK32
:
2309 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32
:
2310 case VK_FORMAT_A2R10G10B10_UINT_PACK32
:
2311 case VK_FORMAT_A2R10G10B10_SINT_PACK32
:
2312 key
.vertex_post_shuffle
|= 1 << location
;
2319 const VkPipelineTessellationStateCreateInfo
*tess
=
2320 radv_pipeline_get_tessellation_state(pCreateInfo
);
2322 key
.tess_input_vertices
= tess
->patchControlPoints
;
2324 const VkPipelineMultisampleStateCreateInfo
*vkms
=
2325 radv_pipeline_get_multisample_state(pCreateInfo
);
2326 if (vkms
&& vkms
->rasterizationSamples
> 1) {
2327 uint32_t num_samples
= vkms
->rasterizationSamples
;
2328 uint32_t ps_iter_samples
= radv_pipeline_get_ps_iter_samples(pCreateInfo
);
2329 key
.num_samples
= num_samples
;
2330 key
.log2_ps_iter_samples
= util_logbase2(ps_iter_samples
);
2333 key
.col_format
= blend
->spi_shader_col_format
;
2334 key
.is_dual_src
= blend
->mrt0_is_dual_src
;
2335 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX8
) {
2336 key
.is_int8
= blend
->col_format_is_int8
;
2337 key
.is_int10
= blend
->col_format_is_int10
;
2340 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
)
2341 key
.topology
= pCreateInfo
->pInputAssemblyState
->topology
;
2347 radv_nir_stage_uses_xfb(const nir_shader
*nir
)
2349 nir_xfb_info
*xfb
= nir_gather_xfb_info(nir
, NULL
);
2350 bool uses_xfb
= !!xfb
;
2357 radv_fill_shader_keys(struct radv_device
*device
,
2358 struct radv_shader_variant_key
*keys
,
2359 const struct radv_pipeline_key
*key
,
2362 keys
[MESA_SHADER_VERTEX
].vs
.instance_rate_inputs
= key
->instance_rate_inputs
;
2363 keys
[MESA_SHADER_VERTEX
].vs
.alpha_adjust
= key
->vertex_alpha_adjust
;
2364 keys
[MESA_SHADER_VERTEX
].vs
.post_shuffle
= key
->vertex_post_shuffle
;
2365 for (unsigned i
= 0; i
< MAX_VERTEX_ATTRIBS
; ++i
) {
2366 keys
[MESA_SHADER_VERTEX
].vs
.instance_rate_divisors
[i
] = key
->instance_rate_divisors
[i
];
2367 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_formats
[i
] = key
->vertex_attribute_formats
[i
];
2368 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_bindings
[i
] = key
->vertex_attribute_bindings
[i
];
2369 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_offsets
[i
] = key
->vertex_attribute_offsets
[i
];
2370 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_strides
[i
] = key
->vertex_attribute_strides
[i
];
2372 keys
[MESA_SHADER_VERTEX
].vs
.outprim
= si_conv_prim_to_gs_out(key
->topology
);
2374 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2375 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ls
= true;
2376 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
= 0;
2377 keys
[MESA_SHADER_TESS_CTRL
].tcs
.input_vertices
= key
->tess_input_vertices
;
2378 keys
[MESA_SHADER_TESS_CTRL
].tcs
.primitive_mode
= nir
[MESA_SHADER_TESS_EVAL
]->info
.tess
.primitive_mode
;
2380 keys
[MESA_SHADER_TESS_CTRL
].tcs
.tes_reads_tess_factors
= !!(nir
[MESA_SHADER_TESS_EVAL
]->info
.inputs_read
& (VARYING_BIT_TESS_LEVEL_INNER
| VARYING_BIT_TESS_LEVEL_OUTER
));
2383 if (nir
[MESA_SHADER_GEOMETRY
]) {
2384 if (nir
[MESA_SHADER_TESS_CTRL
])
2385 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_es
= true;
2387 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_es
= true;
2390 if (device
->physical_device
->use_ngg
) {
2391 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2392 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= true;
2394 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= true;
2397 if (nir
[MESA_SHADER_TESS_CTRL
] &&
2398 nir
[MESA_SHADER_GEOMETRY
] &&
2399 nir
[MESA_SHADER_GEOMETRY
]->info
.gs
.invocations
*
2400 nir
[MESA_SHADER_GEOMETRY
]->info
.gs
.vertices_out
> 256) {
2401 /* Fallback to the legacy path if tessellation is
2402 * enabled with extreme geometry because
2403 * EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it
2406 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2409 if (!device
->physical_device
->use_ngg_gs
) {
2410 if (nir
[MESA_SHADER_GEOMETRY
]) {
2411 if (nir
[MESA_SHADER_TESS_CTRL
])
2412 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2414 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= false;
2418 gl_shader_stage last_xfb_stage
= MESA_SHADER_VERTEX
;
2420 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
2425 bool uses_xfb
= nir
[last_xfb_stage
] &&
2426 radv_nir_stage_uses_xfb(nir
[last_xfb_stage
]);
2428 if (!device
->physical_device
->use_ngg_streamout
&& uses_xfb
) {
2429 if (nir
[MESA_SHADER_TESS_CTRL
])
2430 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2432 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= false;
2435 /* Determine if the pipeline is eligible for the NGG passthrough
2436 * mode. It can't be enabled for geometry shaders, for NGG
2437 * streamout or for vertex shaders that export the primitive ID
2438 * (this is checked later because we don't have the info here.)
2440 if (!nir
[MESA_SHADER_GEOMETRY
] && !uses_xfb
) {
2441 if (nir
[MESA_SHADER_TESS_CTRL
] &&
2442 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
) {
2443 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg_passthrough
= true;
2444 } else if (nir
[MESA_SHADER_VERTEX
] &&
2445 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
) {
2446 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg_passthrough
= true;
2451 for(int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
2452 keys
[i
].has_multiview_view_index
= key
->has_multiview_view_index
;
2454 keys
[MESA_SHADER_FRAGMENT
].fs
.col_format
= key
->col_format
;
2455 keys
[MESA_SHADER_FRAGMENT
].fs
.is_int8
= key
->is_int8
;
2456 keys
[MESA_SHADER_FRAGMENT
].fs
.is_int10
= key
->is_int10
;
2457 keys
[MESA_SHADER_FRAGMENT
].fs
.log2_ps_iter_samples
= key
->log2_ps_iter_samples
;
2458 keys
[MESA_SHADER_FRAGMENT
].fs
.num_samples
= key
->num_samples
;
2459 keys
[MESA_SHADER_FRAGMENT
].fs
.is_dual_src
= key
->is_dual_src
;
2461 if (nir
[MESA_SHADER_COMPUTE
]) {
2462 keys
[MESA_SHADER_COMPUTE
].cs
.subgroup_size
= key
->compute_subgroup_size
;
2467 radv_get_wave_size(struct radv_device
*device
,
2468 const VkPipelineShaderStageCreateInfo
*pStage
,
2469 gl_shader_stage stage
,
2470 const struct radv_shader_variant_key
*key
)
2472 if (stage
== MESA_SHADER_GEOMETRY
&& !key
->vs_common_out
.as_ngg
)
2474 else if (stage
== MESA_SHADER_COMPUTE
) {
2475 if (key
->cs
.subgroup_size
) {
2476 /* Return the required subgroup size if specified. */
2477 return key
->cs
.subgroup_size
;
2479 return device
->physical_device
->cs_wave_size
;
2481 else if (stage
== MESA_SHADER_FRAGMENT
)
2482 return device
->physical_device
->ps_wave_size
;
2484 return device
->physical_device
->ge_wave_size
;
2488 radv_get_ballot_bit_size(struct radv_device
*device
,
2489 const VkPipelineShaderStageCreateInfo
*pStage
,
2490 gl_shader_stage stage
,
2491 const struct radv_shader_variant_key
*key
)
2493 if (stage
== MESA_SHADER_COMPUTE
&& key
->cs
.subgroup_size
)
2494 return key
->cs
.subgroup_size
;
2499 radv_fill_shader_info(struct radv_pipeline
*pipeline
,
2500 const VkPipelineShaderStageCreateInfo
**pStages
,
2501 struct radv_shader_variant_key
*keys
,
2502 struct radv_shader_info
*infos
,
2505 unsigned active_stages
= 0;
2506 unsigned filled_stages
= 0;
2508 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2510 active_stages
|= (1 << i
);
2513 if (nir
[MESA_SHADER_FRAGMENT
]) {
2514 radv_nir_shader_info_init(&infos
[MESA_SHADER_FRAGMENT
]);
2515 radv_nir_shader_info_pass(nir
[MESA_SHADER_FRAGMENT
],
2517 &keys
[MESA_SHADER_FRAGMENT
],
2518 &infos
[MESA_SHADER_FRAGMENT
],
2519 pipeline
->device
->physical_device
->use_llvm
);
2521 /* TODO: These are no longer used as keys we should refactor this */
2522 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_prim_id
=
2523 infos
[MESA_SHADER_FRAGMENT
].ps
.prim_id_input
;
2524 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_layer_id
=
2525 infos
[MESA_SHADER_FRAGMENT
].ps
.layer_input
;
2526 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_clip_dists
=
2527 !!infos
[MESA_SHADER_FRAGMENT
].ps
.num_input_clips_culls
;
2528 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_viewport_index
=
2529 infos
[MESA_SHADER_FRAGMENT
].ps
.viewport_index_input
;
2530 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_prim_id
=
2531 infos
[MESA_SHADER_FRAGMENT
].ps
.prim_id_input
;
2532 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_layer_id
=
2533 infos
[MESA_SHADER_FRAGMENT
].ps
.layer_input
;
2534 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_clip_dists
=
2535 !!infos
[MESA_SHADER_FRAGMENT
].ps
.num_input_clips_culls
;
2536 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_viewport_index
=
2537 infos
[MESA_SHADER_FRAGMENT
].ps
.viewport_index_input
;
2539 /* NGG passthrough mode can't be enabled for vertex shaders
2540 * that export the primitive ID.
2542 * TODO: I should really refactor the keys logic.
2544 if (nir
[MESA_SHADER_VERTEX
] &&
2545 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_prim_id
) {
2546 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg_passthrough
= false;
2549 filled_stages
|= (1 << MESA_SHADER_FRAGMENT
);
2552 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2553 infos
[MESA_SHADER_TESS_CTRL
].tcs
.tes_inputs_read
=
2554 nir
[MESA_SHADER_TESS_EVAL
]->info
.inputs_read
;
2555 infos
[MESA_SHADER_TESS_CTRL
].tcs
.tes_patch_inputs_read
=
2556 nir
[MESA_SHADER_TESS_EVAL
]->info
.patch_inputs_read
;
2559 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
2560 nir
[MESA_SHADER_TESS_CTRL
]) {
2561 struct nir_shader
*combined_nir
[] = {nir
[MESA_SHADER_VERTEX
], nir
[MESA_SHADER_TESS_CTRL
]};
2562 struct radv_shader_variant_key key
= keys
[MESA_SHADER_TESS_CTRL
];
2563 key
.tcs
.vs_key
= keys
[MESA_SHADER_VERTEX
].vs
;
2565 radv_nir_shader_info_init(&infos
[MESA_SHADER_TESS_CTRL
]);
2567 for (int i
= 0; i
< 2; i
++) {
2568 radv_nir_shader_info_pass(combined_nir
[i
],
2569 pipeline
->layout
, &key
,
2570 &infos
[MESA_SHADER_TESS_CTRL
],
2571 pipeline
->device
->physical_device
->use_llvm
);
2574 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
=
2575 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_patches
;
2576 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
=
2577 util_last_bit64(infos
[MESA_SHADER_TESS_CTRL
].tcs
.outputs_written
);
2579 filled_stages
|= (1 << MESA_SHADER_VERTEX
);
2580 filled_stages
|= (1 << MESA_SHADER_TESS_CTRL
);
2583 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
2584 nir
[MESA_SHADER_GEOMETRY
]) {
2585 gl_shader_stage pre_stage
= nir
[MESA_SHADER_TESS_EVAL
] ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
2586 struct nir_shader
*combined_nir
[] = {nir
[pre_stage
], nir
[MESA_SHADER_GEOMETRY
]};
2588 radv_nir_shader_info_init(&infos
[MESA_SHADER_GEOMETRY
]);
2590 for (int i
= 0; i
< 2; i
++) {
2591 radv_nir_shader_info_pass(combined_nir
[i
],
2594 &infos
[MESA_SHADER_GEOMETRY
],
2595 pipeline
->device
->physical_device
->use_llvm
);
2598 filled_stages
|= (1 << pre_stage
);
2599 filled_stages
|= (1 << MESA_SHADER_GEOMETRY
);
2602 active_stages
^= filled_stages
;
2603 while (active_stages
) {
2604 int i
= u_bit_scan(&active_stages
);
2606 if (i
== MESA_SHADER_TESS_CTRL
) {
2607 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
=
2608 util_last_bit64(infos
[MESA_SHADER_VERTEX
].vs
.ls_outputs_written
);
2611 if (i
== MESA_SHADER_TESS_EVAL
) {
2612 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
=
2613 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_patches
;
2614 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
=
2615 util_last_bit64(infos
[MESA_SHADER_TESS_CTRL
].tcs
.outputs_written
);
2618 radv_nir_shader_info_init(&infos
[i
]);
2619 radv_nir_shader_info_pass(nir
[i
], pipeline
->layout
,
2620 &keys
[i
], &infos
[i
], pipeline
->device
->physical_device
->use_llvm
);
2623 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2625 infos
[i
].wave_size
=
2626 radv_get_wave_size(pipeline
->device
, pStages
[i
],
2628 infos
[i
].ballot_bit_size
=
2629 radv_get_ballot_bit_size(pipeline
->device
,
2637 merge_tess_info(struct shader_info
*tes_info
,
2638 const struct shader_info
*tcs_info
)
2640 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2642 * "PointMode. Controls generation of points rather than triangles
2643 * or lines. This functionality defaults to disabled, and is
2644 * enabled if either shader stage includes the execution mode.
2646 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2647 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2648 * and OutputVertices, it says:
2650 * "One mode must be set in at least one of the tessellation
2653 * So, the fields can be set in either the TCS or TES, but they must
2654 * agree if set in both. Our backend looks at TES, so bitwise-or in
2655 * the values from the TCS.
2657 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
2658 tes_info
->tess
.tcs_vertices_out
== 0 ||
2659 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
2660 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
2662 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
2663 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
2664 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
2665 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
2667 assert(tcs_info
->tess
.primitive_mode
== 0 ||
2668 tes_info
->tess
.primitive_mode
== 0 ||
2669 tcs_info
->tess
.primitive_mode
== tes_info
->tess
.primitive_mode
);
2670 tes_info
->tess
.primitive_mode
|= tcs_info
->tess
.primitive_mode
;
2671 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
2672 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
2676 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT
*ext
)
2681 if (ext
->pPipelineCreationFeedback
) {
2682 ext
->pPipelineCreationFeedback
->flags
= 0;
2683 ext
->pPipelineCreationFeedback
->duration
= 0;
2686 for (unsigned i
= 0; i
< ext
->pipelineStageCreationFeedbackCount
; ++i
) {
2687 ext
->pPipelineStageCreationFeedbacks
[i
].flags
= 0;
2688 ext
->pPipelineStageCreationFeedbacks
[i
].duration
= 0;
2693 void radv_start_feedback(VkPipelineCreationFeedbackEXT
*feedback
)
2698 feedback
->duration
-= radv_get_current_time();
2699 feedback
->flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
;
2703 void radv_stop_feedback(VkPipelineCreationFeedbackEXT
*feedback
, bool cache_hit
)
2708 feedback
->duration
+= radv_get_current_time();
2709 feedback
->flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
|
2710 (cache_hit
? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
: 0);
2713 VkResult
radv_create_shaders(struct radv_pipeline
*pipeline
,
2714 struct radv_device
*device
,
2715 struct radv_pipeline_cache
*cache
,
2716 const struct radv_pipeline_key
*key
,
2717 const VkPipelineShaderStageCreateInfo
**pStages
,
2718 const VkPipelineCreateFlags flags
,
2719 VkPipelineCreationFeedbackEXT
*pipeline_feedback
,
2720 VkPipelineCreationFeedbackEXT
**stage_feedbacks
)
2722 struct radv_shader_module fs_m
= {0};
2723 struct radv_shader_module
*modules
[MESA_SHADER_STAGES
] = { 0, };
2724 nir_shader
*nir
[MESA_SHADER_STAGES
] = {0};
2725 struct radv_shader_binary
*binaries
[MESA_SHADER_STAGES
] = {NULL
};
2726 struct radv_shader_variant_key keys
[MESA_SHADER_STAGES
] = {{{{{0}}}}};
2727 struct radv_shader_info infos
[MESA_SHADER_STAGES
] = {0};
2728 unsigned char hash
[20], gs_copy_hash
[20];
2729 bool keep_executable_info
= (flags
& VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR
) || device
->keep_shader_info
;
2730 bool keep_statistic_info
= (flags
& VK_PIPELINE_CREATE_CAPTURE_STATISTICS_BIT_KHR
) ||
2731 (device
->instance
->debug_flags
& RADV_DEBUG_DUMP_SHADER_STATS
) ||
2732 device
->keep_shader_info
;
2734 radv_start_feedback(pipeline_feedback
);
2736 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2738 modules
[i
] = radv_shader_module_from_handle(pStages
[i
]->module
);
2739 if (modules
[i
]->nir
)
2740 _mesa_sha1_compute(modules
[i
]->nir
->info
.name
,
2741 strlen(modules
[i
]->nir
->info
.name
),
2744 pipeline
->active_stages
|= mesa_to_vk_shader_stage(i
);
2748 radv_hash_shaders(hash
, pStages
, pipeline
->layout
, key
, get_hash_flags(device
));
2749 memcpy(gs_copy_hash
, hash
, 20);
2750 gs_copy_hash
[0] ^= 1;
2752 bool found_in_application_cache
= true;
2753 if (modules
[MESA_SHADER_GEOMETRY
] && !keep_executable_info
&& !keep_statistic_info
) {
2754 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
2755 radv_create_shader_variants_from_pipeline_cache(device
, cache
, gs_copy_hash
, variants
,
2756 &found_in_application_cache
);
2757 pipeline
->gs_copy_shader
= variants
[MESA_SHADER_GEOMETRY
];
2760 if (!keep_executable_info
&& !keep_statistic_info
&&
2761 radv_create_shader_variants_from_pipeline_cache(device
, cache
, hash
, pipeline
->shaders
,
2762 &found_in_application_cache
) &&
2763 (!modules
[MESA_SHADER_GEOMETRY
] || pipeline
->gs_copy_shader
)) {
2764 radv_stop_feedback(pipeline_feedback
, found_in_application_cache
);
2768 if (flags
& VK_PIPELINE_CREATE_FAIL_ON_PIPELINE_COMPILE_REQUIRED_BIT_EXT
) {
2769 radv_stop_feedback(pipeline_feedback
, found_in_application_cache
);
2770 return VK_PIPELINE_COMPILE_REQUIRED_EXT
;
2773 if (!modules
[MESA_SHADER_FRAGMENT
] && !modules
[MESA_SHADER_COMPUTE
]) {
2775 nir_builder_init_simple_shader(&fs_b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
2776 fs_b
.shader
->info
.name
= ralloc_strdup(fs_b
.shader
, "noop_fs");
2777 fs_m
.nir
= fs_b
.shader
;
2778 modules
[MESA_SHADER_FRAGMENT
] = &fs_m
;
2781 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2782 const VkPipelineShaderStageCreateInfo
*stage
= pStages
[i
];
2783 unsigned subgroup_size
= 64, ballot_bit_size
= 64;
2788 radv_start_feedback(stage_feedbacks
[i
]);
2790 if (key
->compute_subgroup_size
) {
2791 /* Only compute shaders currently support requiring a
2792 * specific subgroup size.
2794 assert(i
== MESA_SHADER_COMPUTE
);
2795 subgroup_size
= key
->compute_subgroup_size
;
2796 ballot_bit_size
= key
->compute_subgroup_size
;
2799 nir
[i
] = radv_shader_compile_to_nir(device
, modules
[i
],
2800 stage
? stage
->pName
: "main", i
,
2801 stage
? stage
->pSpecializationInfo
: NULL
,
2802 flags
, pipeline
->layout
,
2803 subgroup_size
, ballot_bit_size
);
2805 /* We don't want to alter meta shaders IR directly so clone it
2808 if (nir
[i
]->info
.name
) {
2809 nir
[i
] = nir_shader_clone(NULL
, nir
[i
]);
2812 radv_stop_feedback(stage_feedbacks
[i
], false);
2815 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2816 nir_lower_patch_vertices(nir
[MESA_SHADER_TESS_EVAL
], nir
[MESA_SHADER_TESS_CTRL
]->info
.tess
.tcs_vertices_out
, NULL
);
2817 merge_tess_info(&nir
[MESA_SHADER_TESS_EVAL
]->info
, &nir
[MESA_SHADER_TESS_CTRL
]->info
);
2820 if (!(flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
))
2821 radv_link_shaders(pipeline
, nir
);
2823 radv_set_linked_driver_locations(pipeline
, nir
, infos
);
2825 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2827 /* do this again since information such as outputs_read can be out-of-date */
2828 nir_shader_gather_info(nir
[i
], nir_shader_get_entrypoint(nir
[i
]));
2830 if (device
->physical_device
->use_llvm
) {
2831 NIR_PASS_V(nir
[i
], nir_lower_bool_to_int32
);
2833 NIR_PASS_V(nir
[i
], nir_lower_non_uniform_access
,
2834 nir_lower_non_uniform_ubo_access
|
2835 nir_lower_non_uniform_ssbo_access
|
2836 nir_lower_non_uniform_texture_access
|
2837 nir_lower_non_uniform_image_access
);
2842 if (nir
[MESA_SHADER_FRAGMENT
])
2843 radv_lower_fs_io(nir
[MESA_SHADER_FRAGMENT
]);
2845 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2846 if (radv_can_dump_shader(device
, modules
[i
], false))
2847 nir_print_shader(nir
[i
], stderr
);
2850 radv_fill_shader_keys(device
, keys
, key
, nir
);
2852 radv_fill_shader_info(pipeline
, pStages
, keys
, infos
, nir
);
2854 if ((nir
[MESA_SHADER_VERTEX
] &&
2855 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
) ||
2856 (nir
[MESA_SHADER_TESS_EVAL
] &&
2857 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
)) {
2858 struct gfx10_ngg_info
*ngg_info
;
2860 if (nir
[MESA_SHADER_GEOMETRY
])
2861 ngg_info
= &infos
[MESA_SHADER_GEOMETRY
].ngg_info
;
2862 else if (nir
[MESA_SHADER_TESS_CTRL
])
2863 ngg_info
= &infos
[MESA_SHADER_TESS_EVAL
].ngg_info
;
2865 ngg_info
= &infos
[MESA_SHADER_VERTEX
].ngg_info
;
2867 gfx10_get_ngg_info(key
, pipeline
, nir
, infos
, ngg_info
);
2868 } else if (nir
[MESA_SHADER_GEOMETRY
]) {
2869 struct gfx9_gs_info
*gs_info
=
2870 &infos
[MESA_SHADER_GEOMETRY
].gs_ring_info
;
2872 gfx9_get_gs_info(key
, pipeline
, nir
, infos
, gs_info
);
2875 if(modules
[MESA_SHADER_GEOMETRY
]) {
2876 struct radv_shader_binary
*gs_copy_binary
= NULL
;
2877 if (!pipeline
->gs_copy_shader
&&
2878 !radv_pipeline_has_ngg(pipeline
)) {
2879 struct radv_shader_info info
= {};
2880 struct radv_shader_variant_key key
= {};
2882 key
.has_multiview_view_index
=
2883 keys
[MESA_SHADER_GEOMETRY
].has_multiview_view_index
;
2885 radv_nir_shader_info_pass(nir
[MESA_SHADER_GEOMETRY
],
2886 pipeline
->layout
, &key
,
2887 &info
, pipeline
->device
->physical_device
->use_llvm
);
2888 info
.wave_size
= 64; /* Wave32 not supported. */
2889 info
.ballot_bit_size
= 64;
2891 pipeline
->gs_copy_shader
= radv_create_gs_copy_shader(
2892 device
, nir
[MESA_SHADER_GEOMETRY
], &info
,
2893 &gs_copy_binary
, keep_executable_info
, keep_statistic_info
,
2894 keys
[MESA_SHADER_GEOMETRY
].has_multiview_view_index
);
2897 if (!keep_executable_info
&& !keep_statistic_info
&& pipeline
->gs_copy_shader
) {
2898 struct radv_shader_binary
*binaries
[MESA_SHADER_STAGES
] = {NULL
};
2899 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
2901 binaries
[MESA_SHADER_GEOMETRY
] = gs_copy_binary
;
2902 variants
[MESA_SHADER_GEOMETRY
] = pipeline
->gs_copy_shader
;
2904 radv_pipeline_cache_insert_shaders(device
, cache
,
2909 free(gs_copy_binary
);
2912 if (nir
[MESA_SHADER_FRAGMENT
]) {
2913 if (!pipeline
->shaders
[MESA_SHADER_FRAGMENT
]) {
2914 radv_start_feedback(stage_feedbacks
[MESA_SHADER_FRAGMENT
]);
2916 pipeline
->shaders
[MESA_SHADER_FRAGMENT
] =
2917 radv_shader_variant_compile(device
, modules
[MESA_SHADER_FRAGMENT
], &nir
[MESA_SHADER_FRAGMENT
], 1,
2918 pipeline
->layout
, keys
+ MESA_SHADER_FRAGMENT
,
2919 infos
+ MESA_SHADER_FRAGMENT
,
2920 keep_executable_info
, keep_statistic_info
,
2921 &binaries
[MESA_SHADER_FRAGMENT
]);
2923 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_FRAGMENT
], false);
2927 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&& modules
[MESA_SHADER_TESS_CTRL
]) {
2928 if (!pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]) {
2929 struct nir_shader
*combined_nir
[] = {nir
[MESA_SHADER_VERTEX
], nir
[MESA_SHADER_TESS_CTRL
]};
2930 struct radv_shader_variant_key key
= keys
[MESA_SHADER_TESS_CTRL
];
2931 key
.tcs
.vs_key
= keys
[MESA_SHADER_VERTEX
].vs
;
2933 radv_start_feedback(stage_feedbacks
[MESA_SHADER_TESS_CTRL
]);
2935 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] = radv_shader_variant_compile(device
, modules
[MESA_SHADER_TESS_CTRL
], combined_nir
, 2,
2937 &key
, &infos
[MESA_SHADER_TESS_CTRL
], keep_executable_info
,
2938 keep_statistic_info
, &binaries
[MESA_SHADER_TESS_CTRL
]);
2940 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_TESS_CTRL
], false);
2942 modules
[MESA_SHADER_VERTEX
] = NULL
;
2943 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2944 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.outputs_written
);
2947 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&& modules
[MESA_SHADER_GEOMETRY
]) {
2948 gl_shader_stage pre_stage
= modules
[MESA_SHADER_TESS_EVAL
] ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
2949 if (!pipeline
->shaders
[MESA_SHADER_GEOMETRY
]) {
2950 struct nir_shader
*combined_nir
[] = {nir
[pre_stage
], nir
[MESA_SHADER_GEOMETRY
]};
2952 radv_start_feedback(stage_feedbacks
[MESA_SHADER_GEOMETRY
]);
2954 pipeline
->shaders
[MESA_SHADER_GEOMETRY
] = radv_shader_variant_compile(device
, modules
[MESA_SHADER_GEOMETRY
], combined_nir
, 2,
2956 &keys
[pre_stage
], &infos
[MESA_SHADER_GEOMETRY
], keep_executable_info
,
2957 keep_statistic_info
, &binaries
[MESA_SHADER_GEOMETRY
]);
2959 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_GEOMETRY
], false);
2961 modules
[pre_stage
] = NULL
;
2964 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2965 if(modules
[i
] && !pipeline
->shaders
[i
]) {
2966 if (i
== MESA_SHADER_TESS_CTRL
) {
2967 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.ls_outputs_written
);
2969 if (i
== MESA_SHADER_TESS_EVAL
) {
2970 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2971 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.outputs_written
);
2974 radv_start_feedback(stage_feedbacks
[i
]);
2976 pipeline
->shaders
[i
] = radv_shader_variant_compile(device
, modules
[i
], &nir
[i
], 1,
2978 keys
+ i
, infos
+ i
, keep_executable_info
,
2979 keep_statistic_info
, &binaries
[i
]);
2981 radv_stop_feedback(stage_feedbacks
[i
], false);
2985 if (!keep_executable_info
&& !keep_statistic_info
) {
2986 radv_pipeline_cache_insert_shaders(device
, cache
, hash
, pipeline
->shaders
,
2990 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2993 ralloc_free(nir
[i
]);
2995 if (radv_can_dump_shader_stats(device
, modules
[i
]))
2996 radv_shader_dump_stats(device
,
2997 pipeline
->shaders
[i
],
3003 ralloc_free(fs_m
.nir
);
3005 radv_stop_feedback(pipeline_feedback
, false);
3010 radv_pipeline_stage_to_user_data_0(struct radv_pipeline
*pipeline
,
3011 gl_shader_stage stage
, enum chip_class chip_class
)
3013 bool has_gs
= radv_pipeline_has_gs(pipeline
);
3014 bool has_tess
= radv_pipeline_has_tess(pipeline
);
3015 bool has_ngg
= radv_pipeline_has_ngg(pipeline
);
3018 case MESA_SHADER_FRAGMENT
:
3019 return R_00B030_SPI_SHADER_USER_DATA_PS_0
;
3020 case MESA_SHADER_VERTEX
:
3022 if (chip_class
>= GFX10
) {
3023 return R_00B430_SPI_SHADER_USER_DATA_HS_0
;
3024 } else if (chip_class
== GFX9
) {
3025 return R_00B430_SPI_SHADER_USER_DATA_LS_0
;
3027 return R_00B530_SPI_SHADER_USER_DATA_LS_0
;
3033 if (chip_class
>= GFX10
) {
3034 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3036 return R_00B330_SPI_SHADER_USER_DATA_ES_0
;
3041 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3043 return R_00B130_SPI_SHADER_USER_DATA_VS_0
;
3044 case MESA_SHADER_GEOMETRY
:
3045 return chip_class
== GFX9
? R_00B330_SPI_SHADER_USER_DATA_ES_0
:
3046 R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3047 case MESA_SHADER_COMPUTE
:
3048 return R_00B900_COMPUTE_USER_DATA_0
;
3049 case MESA_SHADER_TESS_CTRL
:
3050 return chip_class
== GFX9
? R_00B430_SPI_SHADER_USER_DATA_LS_0
:
3051 R_00B430_SPI_SHADER_USER_DATA_HS_0
;
3052 case MESA_SHADER_TESS_EVAL
:
3054 return chip_class
>= GFX10
? R_00B230_SPI_SHADER_USER_DATA_GS_0
:
3055 R_00B330_SPI_SHADER_USER_DATA_ES_0
;
3056 } else if (has_ngg
) {
3057 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3059 return R_00B130_SPI_SHADER_USER_DATA_VS_0
;
3062 unreachable("unknown shader");
3066 struct radv_bin_size_entry
{
3072 radv_gfx9_compute_bin_size(struct radv_pipeline
*pipeline
, const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3074 static const struct radv_bin_size_entry color_size_table
[][3][9] = {
3078 /* One shader engine */
3084 { UINT_MAX
, { 0, 0}},
3087 /* Two shader engines */
3093 { UINT_MAX
, { 0, 0}},
3096 /* Four shader engines */
3101 { UINT_MAX
, { 0, 0}},
3107 /* One shader engine */
3113 { UINT_MAX
, { 0, 0}},
3116 /* Two shader engines */
3122 { UINT_MAX
, { 0, 0}},
3125 /* Four shader engines */
3132 { UINT_MAX
, { 0, 0}},
3138 /* One shader engine */
3145 { UINT_MAX
, { 0, 0}},
3148 /* Two shader engines */
3156 { UINT_MAX
, { 0, 0}},
3159 /* Four shader engines */
3167 { UINT_MAX
, { 0, 0}},
3171 static const struct radv_bin_size_entry ds_size_table
[][3][9] = {
3175 // One shader engine
3182 { UINT_MAX
, { 0, 0}},
3185 // Two shader engines
3193 { UINT_MAX
, { 0, 0}},
3196 // Four shader engines
3204 { UINT_MAX
, { 0, 0}},
3210 // One shader engine
3218 { UINT_MAX
, { 0, 0}},
3221 // Two shader engines
3230 { UINT_MAX
, { 0, 0}},
3233 // Four shader engines
3242 { UINT_MAX
, { 0, 0}},
3248 // One shader engine
3256 { UINT_MAX
, { 0, 0}},
3259 // Two shader engines
3268 { UINT_MAX
, { 0, 0}},
3271 // Four shader engines
3279 { UINT_MAX
, { 0, 0}},
3284 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3285 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3286 VkExtent2D extent
= {512, 512};
3288 unsigned log_num_rb_per_se
=
3289 util_logbase2_ceil(pipeline
->device
->physical_device
->rad_info
.num_render_backends
/
3290 pipeline
->device
->physical_device
->rad_info
.max_se
);
3291 unsigned log_num_se
= util_logbase2_ceil(pipeline
->device
->physical_device
->rad_info
.max_se
);
3293 unsigned total_samples
= 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline
->graphics
.ms
.pa_sc_aa_config
);
3294 unsigned ps_iter_samples
= 1u << G_028804_PS_ITER_SAMPLES(pipeline
->graphics
.ms
.db_eqaa
);
3295 unsigned effective_samples
= total_samples
;
3296 unsigned color_bytes_per_pixel
= 0;
3298 const VkPipelineColorBlendStateCreateInfo
*vkblend
=
3299 radv_pipeline_get_color_blend_state(pCreateInfo
);
3301 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3302 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3305 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3308 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3309 color_bytes_per_pixel
+= vk_format_get_blocksize(format
);
3312 /* MSAA images typically don't use all samples all the time. */
3313 if (effective_samples
>= 2 && ps_iter_samples
<= 1)
3314 effective_samples
= 2;
3315 color_bytes_per_pixel
*= effective_samples
;
3318 const struct radv_bin_size_entry
*color_entry
= color_size_table
[log_num_rb_per_se
][log_num_se
];
3319 while(color_entry
[1].bpp
<= color_bytes_per_pixel
)
3322 extent
= color_entry
->extent
;
3324 if (subpass
->depth_stencil_attachment
) {
3325 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3327 /* Coefficients taken from AMDVLK */
3328 unsigned depth_coeff
= vk_format_is_depth(attachment
->format
) ? 5 : 0;
3329 unsigned stencil_coeff
= vk_format_is_stencil(attachment
->format
) ? 1 : 0;
3330 unsigned ds_bytes_per_pixel
= 4 * (depth_coeff
+ stencil_coeff
) * total_samples
;
3332 const struct radv_bin_size_entry
*ds_entry
= ds_size_table
[log_num_rb_per_se
][log_num_se
];
3333 while(ds_entry
[1].bpp
<= ds_bytes_per_pixel
)
3336 if (ds_entry
->extent
.width
* ds_entry
->extent
.height
< extent
.width
* extent
.height
)
3337 extent
= ds_entry
->extent
;
3344 radv_gfx10_compute_bin_size(struct radv_pipeline
*pipeline
, const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3346 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3347 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3348 VkExtent2D extent
= {512, 512};
3350 const unsigned db_tag_size
= 64;
3351 const unsigned db_tag_count
= 312;
3352 const unsigned color_tag_size
= 1024;
3353 const unsigned color_tag_count
= 31;
3354 const unsigned fmask_tag_size
= 256;
3355 const unsigned fmask_tag_count
= 44;
3357 const unsigned rb_count
= pipeline
->device
->physical_device
->rad_info
.num_render_backends
;
3358 const unsigned pipe_count
= MAX2(rb_count
, pipeline
->device
->physical_device
->rad_info
.num_sdp_interfaces
);
3360 const unsigned db_tag_part
= (db_tag_count
* rb_count
/ pipe_count
) * db_tag_size
* pipe_count
;
3361 const unsigned color_tag_part
= (color_tag_count
* rb_count
/ pipe_count
) * color_tag_size
* pipe_count
;
3362 const unsigned fmask_tag_part
= (fmask_tag_count
* rb_count
/ pipe_count
) * fmask_tag_size
* pipe_count
;
3364 const unsigned total_samples
= 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline
->graphics
.ms
.pa_sc_aa_config
);
3365 const unsigned samples_log
= util_logbase2_ceil(total_samples
);
3367 unsigned color_bytes_per_pixel
= 0;
3368 unsigned fmask_bytes_per_pixel
= 0;
3370 const VkPipelineColorBlendStateCreateInfo
*vkblend
=
3371 radv_pipeline_get_color_blend_state(pCreateInfo
);
3373 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3374 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3377 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3380 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3381 color_bytes_per_pixel
+= vk_format_get_blocksize(format
);
3383 if (total_samples
> 1) {
3384 assert(samples_log
<= 3);
3385 const unsigned fmask_array
[] = {0, 1, 1, 4};
3386 fmask_bytes_per_pixel
+= fmask_array
[samples_log
];
3390 color_bytes_per_pixel
*= total_samples
;
3392 color_bytes_per_pixel
= MAX2(color_bytes_per_pixel
, 1);
3394 const unsigned color_pixel_count_log
= util_logbase2(color_tag_part
/ color_bytes_per_pixel
);
3395 extent
.width
= 1ull << ((color_pixel_count_log
+ 1) / 2);
3396 extent
.height
= 1ull << (color_pixel_count_log
/ 2);
3398 if (fmask_bytes_per_pixel
) {
3399 const unsigned fmask_pixel_count_log
= util_logbase2(fmask_tag_part
/ fmask_bytes_per_pixel
);
3401 const VkExtent2D fmask_extent
= (VkExtent2D
){
3402 .width
= 1ull << ((fmask_pixel_count_log
+ 1) / 2),
3403 .height
= 1ull << (color_pixel_count_log
/ 2)
3406 if (fmask_extent
.width
* fmask_extent
.height
< extent
.width
* extent
.height
)
3407 extent
= fmask_extent
;
3410 if (subpass
->depth_stencil_attachment
) {
3411 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3413 /* Coefficients taken from AMDVLK */
3414 unsigned depth_coeff
= vk_format_is_depth(attachment
->format
) ? 5 : 0;
3415 unsigned stencil_coeff
= vk_format_is_stencil(attachment
->format
) ? 1 : 0;
3416 unsigned db_bytes_per_pixel
= (depth_coeff
+ stencil_coeff
) * total_samples
;
3418 const unsigned db_pixel_count_log
= util_logbase2(db_tag_part
/ db_bytes_per_pixel
);
3420 const VkExtent2D db_extent
= (VkExtent2D
){
3421 .width
= 1ull << ((db_pixel_count_log
+ 1) / 2),
3422 .height
= 1ull << (color_pixel_count_log
/ 2)
3425 if (db_extent
.width
* db_extent
.height
< extent
.width
* extent
.height
)
3429 extent
.width
= MAX2(extent
.width
, 128);
3430 extent
.height
= MAX2(extent
.width
, 64);
3436 radv_pipeline_generate_disabled_binning_state(struct radeon_cmdbuf
*ctx_cs
,
3437 struct radv_pipeline
*pipeline
,
3438 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3440 uint32_t pa_sc_binner_cntl_0
=
3441 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC
) |
3442 S_028C44_DISABLE_START_OF_PRIM(1);
3443 uint32_t db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
);
3445 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3446 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3447 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3448 const VkPipelineColorBlendStateCreateInfo
*vkblend
=
3449 radv_pipeline_get_color_blend_state(pCreateInfo
);
3450 unsigned min_bytes_per_pixel
= 0;
3453 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3454 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3457 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3460 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3461 unsigned bytes
= vk_format_get_blocksize(format
);
3462 if (!min_bytes_per_pixel
|| bytes
< min_bytes_per_pixel
)
3463 min_bytes_per_pixel
= bytes
;
3467 pa_sc_binner_cntl_0
=
3468 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC
) |
3469 S_028C44_BIN_SIZE_X(0) |
3470 S_028C44_BIN_SIZE_Y(0) |
3471 S_028C44_BIN_SIZE_X_EXTEND(2) | /* 128 */
3472 S_028C44_BIN_SIZE_Y_EXTEND(min_bytes_per_pixel
<= 4 ? 2 : 1) | /* 128 or 64 */
3473 S_028C44_DISABLE_START_OF_PRIM(1);
3476 pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
= pa_sc_binner_cntl_0
;
3477 pipeline
->graphics
.binning
.db_dfsm_control
= db_dfsm_control
;
3480 struct radv_binning_settings
3481 radv_get_binning_settings(const struct radv_physical_device
*pdev
)
3483 struct radv_binning_settings settings
;
3484 if (pdev
->rad_info
.has_dedicated_vram
) {
3485 if (pdev
->rad_info
.num_render_backends
> 4) {
3486 settings
.context_states_per_bin
= 1;
3487 settings
.persistent_states_per_bin
= 1;
3489 settings
.context_states_per_bin
= 3;
3490 settings
.persistent_states_per_bin
= 8;
3492 settings
.fpovs_per_batch
= 63;
3494 /* The context states are affected by the scissor bug. */
3495 settings
.context_states_per_bin
= 6;
3496 /* 32 causes hangs for RAVEN. */
3497 settings
.persistent_states_per_bin
= 16;
3498 settings
.fpovs_per_batch
= 63;
3501 if (pdev
->rad_info
.has_gfx9_scissor_bug
)
3502 settings
.context_states_per_bin
= 1;
3508 radv_pipeline_generate_binning_state(struct radeon_cmdbuf
*ctx_cs
,
3509 struct radv_pipeline
*pipeline
,
3510 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3511 const struct radv_blend_state
*blend
)
3513 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX9
)
3516 VkExtent2D bin_size
;
3517 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3518 bin_size
= radv_gfx10_compute_bin_size(pipeline
, pCreateInfo
);
3519 } else if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
3520 bin_size
= radv_gfx9_compute_bin_size(pipeline
, pCreateInfo
);
3522 unreachable("Unhandled generation for binning bin size calculation");
3524 if (pipeline
->device
->pbb_allowed
&& bin_size
.width
&& bin_size
.height
) {
3525 struct radv_binning_settings settings
=
3526 radv_get_binning_settings(pipeline
->device
->physical_device
);
3528 bool disable_start_of_prim
= true;
3529 uint32_t db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
);
3531 const struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3533 if (pipeline
->device
->dfsm_allowed
&& ps
&&
3534 !ps
->info
.ps
.can_discard
&&
3535 !ps
->info
.ps
.writes_memory
&&
3536 blend
->cb_target_enabled_4bit
) {
3537 db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_AUTO
);
3538 disable_start_of_prim
= (blend
->blend_enable_4bit
& blend
->cb_target_enabled_4bit
) != 0;
3541 const uint32_t pa_sc_binner_cntl_0
=
3542 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED
) |
3543 S_028C44_BIN_SIZE_X(bin_size
.width
== 16) |
3544 S_028C44_BIN_SIZE_Y(bin_size
.height
== 16) |
3545 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size
.width
, 32)) - 5) |
3546 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size
.height
, 32)) - 5) |
3547 S_028C44_CONTEXT_STATES_PER_BIN(settings
.context_states_per_bin
- 1) |
3548 S_028C44_PERSISTENT_STATES_PER_BIN(settings
.persistent_states_per_bin
- 1) |
3549 S_028C44_DISABLE_START_OF_PRIM(disable_start_of_prim
) |
3550 S_028C44_FPOVS_PER_BATCH(settings
.fpovs_per_batch
) |
3551 S_028C44_OPTIMAL_BIN_SELECTION(1);
3553 pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
= pa_sc_binner_cntl_0
;
3554 pipeline
->graphics
.binning
.db_dfsm_control
= db_dfsm_control
;
3556 radv_pipeline_generate_disabled_binning_state(ctx_cs
, pipeline
, pCreateInfo
);
3561 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf
*ctx_cs
,
3562 struct radv_pipeline
*pipeline
,
3563 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3564 const struct radv_graphics_pipeline_create_info
*extra
)
3566 const VkPipelineDepthStencilStateCreateInfo
*vkds
= radv_pipeline_get_depth_stencil_state(pCreateInfo
);
3567 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3568 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3569 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3570 struct radv_render_pass_attachment
*attachment
= NULL
;
3571 uint32_t db_depth_control
= 0, db_stencil_control
= 0;
3572 uint32_t db_render_control
= 0, db_render_override2
= 0;
3573 uint32_t db_render_override
= 0;
3575 if (subpass
->depth_stencil_attachment
)
3576 attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3578 bool has_depth_attachment
= attachment
&& vk_format_is_depth(attachment
->format
);
3579 bool has_stencil_attachment
= attachment
&& vk_format_is_stencil(attachment
->format
);
3581 if (vkds
&& has_depth_attachment
) {
3582 db_depth_control
= S_028800_Z_ENABLE(vkds
->depthTestEnable
? 1 : 0) |
3583 S_028800_Z_WRITE_ENABLE(vkds
->depthWriteEnable
? 1 : 0) |
3584 S_028800_ZFUNC(vkds
->depthCompareOp
) |
3585 S_028800_DEPTH_BOUNDS_ENABLE(vkds
->depthBoundsTestEnable
? 1 : 0);
3587 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
3588 db_render_override2
|= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment
->samples
> 2);
3590 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10_3
)
3591 db_render_override2
|= S_028010_CENTROID_COMPUTATION_MODE_GFX103(2);
3594 if (has_stencil_attachment
&& vkds
&& vkds
->stencilTestEnable
) {
3595 db_depth_control
|= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
3596 db_depth_control
|= S_028800_STENCILFUNC(vkds
->front
.compareOp
);
3597 db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds
->front
.failOp
));
3598 db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds
->front
.passOp
));
3599 db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds
->front
.depthFailOp
));
3601 db_depth_control
|= S_028800_STENCILFUNC_BF(vkds
->back
.compareOp
);
3602 db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds
->back
.failOp
));
3603 db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds
->back
.passOp
));
3604 db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds
->back
.depthFailOp
));
3607 if (attachment
&& extra
) {
3608 db_render_control
|= S_028000_DEPTH_CLEAR_ENABLE(extra
->db_depth_clear
);
3609 db_render_control
|= S_028000_STENCIL_CLEAR_ENABLE(extra
->db_stencil_clear
);
3611 db_render_control
|= S_028000_RESUMMARIZE_ENABLE(extra
->resummarize_enable
);
3612 db_render_control
|= S_028000_DEPTH_COMPRESS_DISABLE(extra
->depth_compress_disable
);
3613 db_render_control
|= S_028000_STENCIL_COMPRESS_DISABLE(extra
->stencil_compress_disable
);
3614 db_render_override2
|= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra
->db_depth_disable_expclear
);
3615 db_render_override2
|= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra
->db_stencil_disable_expclear
);
3618 db_render_override
|= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
3619 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
);
3621 if (!pCreateInfo
->pRasterizationState
->depthClampEnable
&&
3622 ps
->info
.ps
.writes_z
) {
3623 /* From VK_EXT_depth_range_unrestricted spec:
3625 * "The behavior described in Primitive Clipping still applies.
3626 * If depth clamping is disabled the depth values are still
3627 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
3628 * depth clamping is enabled the above equation is ignored and
3629 * the depth values are instead clamped to the VkViewport
3630 * minDepth and maxDepth values, which in the case of this
3631 * extension can be outside of the 0.0 to 1.0 range."
3633 db_render_override
|= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
3636 radeon_set_context_reg(ctx_cs
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
3637 radeon_set_context_reg(ctx_cs
, R_02842C_DB_STENCIL_CONTROL
, db_stencil_control
);
3639 radeon_set_context_reg(ctx_cs
, R_028000_DB_RENDER_CONTROL
, db_render_control
);
3640 radeon_set_context_reg(ctx_cs
, R_02800C_DB_RENDER_OVERRIDE
, db_render_override
);
3641 radeon_set_context_reg(ctx_cs
, R_028010_DB_RENDER_OVERRIDE2
, db_render_override2
);
3645 radv_pipeline_generate_blend_state(struct radeon_cmdbuf
*ctx_cs
,
3646 struct radv_pipeline
*pipeline
,
3647 const struct radv_blend_state
*blend
)
3649 radeon_set_context_reg_seq(ctx_cs
, R_028780_CB_BLEND0_CONTROL
, 8);
3650 radeon_emit_array(ctx_cs
, blend
->cb_blend_control
,
3652 radeon_set_context_reg(ctx_cs
, R_028808_CB_COLOR_CONTROL
, blend
->cb_color_control
);
3653 radeon_set_context_reg(ctx_cs
, R_028B70_DB_ALPHA_TO_MASK
, blend
->db_alpha_to_mask
);
3655 if (pipeline
->device
->physical_device
->rad_info
.has_rbplus
) {
3657 radeon_set_context_reg_seq(ctx_cs
, R_028760_SX_MRT0_BLEND_OPT
, 8);
3658 radeon_emit_array(ctx_cs
, blend
->sx_mrt_blend_opt
, 8);
3661 radeon_set_context_reg(ctx_cs
, R_028714_SPI_SHADER_COL_FORMAT
, blend
->spi_shader_col_format
);
3663 radeon_set_context_reg(ctx_cs
, R_028238_CB_TARGET_MASK
, blend
->cb_target_mask
);
3664 radeon_set_context_reg(ctx_cs
, R_02823C_CB_SHADER_MASK
, blend
->cb_shader_mask
);
3666 pipeline
->graphics
.col_format
= blend
->spi_shader_col_format
;
3667 pipeline
->graphics
.cb_target_mask
= blend
->cb_target_mask
;
3670 static const VkConservativeRasterizationModeEXT
3671 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo
*pCreateInfo
)
3673 const VkPipelineRasterizationConservativeStateCreateInfoEXT
*conservative_raster
=
3674 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT
);
3676 if (!conservative_raster
)
3677 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT
;
3678 return conservative_raster
->conservativeRasterizationMode
;
3682 radv_pipeline_generate_raster_state(struct radeon_cmdbuf
*ctx_cs
,
3683 struct radv_pipeline
*pipeline
,
3684 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3686 const VkPipelineRasterizationStateCreateInfo
*vkraster
= pCreateInfo
->pRasterizationState
;
3687 const VkConservativeRasterizationModeEXT mode
=
3688 radv_get_conservative_raster_mode(vkraster
);
3689 uint32_t pa_sc_conservative_rast
= S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
3690 bool depth_clip_disable
= vkraster
->depthClampEnable
;
3692 const VkPipelineRasterizationDepthClipStateCreateInfoEXT
*depth_clip_state
=
3693 vk_find_struct_const(vkraster
->pNext
, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT
);
3694 if (depth_clip_state
) {
3695 depth_clip_disable
= !depth_clip_state
->depthClipEnable
;
3698 radeon_set_context_reg(ctx_cs
, R_028810_PA_CL_CLIP_CNTL
,
3699 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
3700 S_028810_ZCLIP_NEAR_DISABLE(depth_clip_disable
? 1 : 0) |
3701 S_028810_ZCLIP_FAR_DISABLE(depth_clip_disable
? 1 : 0) |
3702 S_028810_DX_RASTERIZATION_KILL(vkraster
->rasterizerDiscardEnable
? 1 : 0) |
3703 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
3705 radeon_set_context_reg(ctx_cs
, R_0286D4_SPI_INTERP_CONTROL_0
,
3706 S_0286D4_FLAT_SHADE_ENA(1) |
3707 S_0286D4_PNT_SPRITE_ENA(1) |
3708 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
3709 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
3710 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
3711 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
3712 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
3714 radeon_set_context_reg(ctx_cs
, R_028BE4_PA_SU_VTX_CNTL
,
3715 S_028BE4_PIX_CENTER(1) | // TODO verify
3716 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN
) |
3717 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH
));
3719 radeon_set_context_reg(ctx_cs
, R_028814_PA_SU_SC_MODE_CNTL
,
3720 S_028814_FACE(vkraster
->frontFace
) |
3721 S_028814_CULL_FRONT(!!(vkraster
->cullMode
& VK_CULL_MODE_FRONT_BIT
)) |
3722 S_028814_CULL_BACK(!!(vkraster
->cullMode
& VK_CULL_MODE_BACK_BIT
)) |
3723 S_028814_POLY_MODE(vkraster
->polygonMode
!= VK_POLYGON_MODE_FILL
) |
3724 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
3725 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
3726 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
3727 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
3728 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster
->depthBiasEnable
? 1 : 0));
3730 /* Conservative rasterization. */
3731 if (mode
!= VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT
) {
3732 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
3734 ms
->pa_sc_aa_config
|= S_028BE0_AA_MASK_CENTROID_DTMN(1);
3735 ms
->db_eqaa
|= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
3736 S_028804_OVERRASTERIZATION_AMOUNT(4);
3738 pa_sc_conservative_rast
= S_028C4C_PREZ_AA_MASK_ENABLE(1) |
3739 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
3740 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
3742 if (mode
== VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT
) {
3743 pa_sc_conservative_rast
|=
3744 S_028C4C_OVER_RAST_ENABLE(1) |
3745 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
3746 S_028C4C_UNDER_RAST_ENABLE(0) |
3747 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
3748 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
3750 assert(mode
== VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT
);
3751 pa_sc_conservative_rast
|=
3752 S_028C4C_OVER_RAST_ENABLE(0) |
3753 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
3754 S_028C4C_UNDER_RAST_ENABLE(1) |
3755 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
3756 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
3760 radeon_set_context_reg(ctx_cs
, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
,
3761 pa_sc_conservative_rast
);
3766 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf
*ctx_cs
,
3767 struct radv_pipeline
*pipeline
)
3769 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
3771 radeon_set_context_reg_seq(ctx_cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
3772 radeon_emit(ctx_cs
, ms
->pa_sc_aa_mask
[0]);
3773 radeon_emit(ctx_cs
, ms
->pa_sc_aa_mask
[1]);
3775 radeon_set_context_reg(ctx_cs
, R_028804_DB_EQAA
, ms
->db_eqaa
);
3776 radeon_set_context_reg(ctx_cs
, R_028A48_PA_SC_MODE_CNTL_0
, ms
->pa_sc_mode_cntl_0
);
3777 radeon_set_context_reg(ctx_cs
, R_028A4C_PA_SC_MODE_CNTL_1
, ms
->pa_sc_mode_cntl_1
);
3778 radeon_set_context_reg(ctx_cs
, R_028BDC_PA_SC_LINE_CNTL
, ms
->pa_sc_line_cntl
);
3779 radeon_set_context_reg(ctx_cs
, R_028BE0_PA_SC_AA_CONFIG
, ms
->pa_sc_aa_config
);
3781 /* The exclusion bits can be set to improve rasterization efficiency
3782 * if no sample lies on the pixel boundary (-8 sample offset). It's
3783 * currently always TRUE because the driver doesn't support 16 samples.
3785 bool exclusion
= pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
3786 radeon_set_context_reg(ctx_cs
, R_02882C_PA_SU_PRIM_FILTER_CNTL
,
3787 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion
) |
3788 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion
));
3790 /* GFX9: Flush DFSM when the AA mode changes. */
3791 if (pipeline
->device
->dfsm_allowed
) {
3792 radeon_emit(ctx_cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3793 radeon_emit(ctx_cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
3798 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf
*ctx_cs
,
3799 struct radv_pipeline
*pipeline
)
3801 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3802 const struct radv_shader_variant
*vs
=
3803 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] ?
3804 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] :
3805 pipeline
->shaders
[MESA_SHADER_VERTEX
];
3806 unsigned vgt_primitiveid_en
= 0;
3807 uint32_t vgt_gs_mode
= 0;
3809 if (radv_pipeline_has_ngg(pipeline
))
3812 if (radv_pipeline_has_gs(pipeline
)) {
3813 const struct radv_shader_variant
*gs
=
3814 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3816 vgt_gs_mode
= ac_vgt_gs_mode(gs
->info
.gs
.vertices_out
,
3817 pipeline
->device
->physical_device
->rad_info
.chip_class
);
3818 } else if (outinfo
->export_prim_id
|| vs
->info
.uses_prim_id
) {
3819 vgt_gs_mode
= S_028A40_MODE(V_028A40_GS_SCENARIO_A
);
3820 vgt_primitiveid_en
|= S_028A84_PRIMITIVEID_EN(1);
3823 radeon_set_context_reg(ctx_cs
, R_028A84_VGT_PRIMITIVEID_EN
, vgt_primitiveid_en
);
3824 radeon_set_context_reg(ctx_cs
, R_028A40_VGT_GS_MODE
, vgt_gs_mode
);
3828 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf
*ctx_cs
,
3829 struct radeon_cmdbuf
*cs
,
3830 struct radv_pipeline
*pipeline
,
3831 struct radv_shader_variant
*shader
)
3833 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3835 radeon_set_sh_reg_seq(cs
, R_00B120_SPI_SHADER_PGM_LO_VS
, 4);
3836 radeon_emit(cs
, va
>> 8);
3837 radeon_emit(cs
, S_00B124_MEM_BASE(va
>> 40));
3838 radeon_emit(cs
, shader
->config
.rsrc1
);
3839 radeon_emit(cs
, shader
->config
.rsrc2
);
3841 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3842 unsigned clip_dist_mask
, cull_dist_mask
, total_mask
;
3843 clip_dist_mask
= outinfo
->clip_dist_mask
;
3844 cull_dist_mask
= outinfo
->cull_dist_mask
;
3845 total_mask
= clip_dist_mask
| cull_dist_mask
;
3846 bool misc_vec_ena
= outinfo
->writes_pointsize
||
3847 outinfo
->writes_layer
||
3848 outinfo
->writes_viewport_index
;
3849 unsigned spi_vs_out_config
, nparams
;
3851 /* VS is required to export at least one param. */
3852 nparams
= MAX2(outinfo
->param_exports
, 1);
3853 spi_vs_out_config
= S_0286C4_VS_EXPORT_COUNT(nparams
- 1);
3855 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3856 spi_vs_out_config
|= S_0286C4_NO_PC_EXPORT(outinfo
->param_exports
== 0);
3859 radeon_set_context_reg(ctx_cs
, R_0286C4_SPI_VS_OUT_CONFIG
, spi_vs_out_config
);
3861 radeon_set_context_reg(ctx_cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
3862 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
3863 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
3864 V_02870C_SPI_SHADER_4COMP
:
3865 V_02870C_SPI_SHADER_NONE
) |
3866 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
3867 V_02870C_SPI_SHADER_4COMP
:
3868 V_02870C_SPI_SHADER_NONE
) |
3869 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
3870 V_02870C_SPI_SHADER_4COMP
:
3871 V_02870C_SPI_SHADER_NONE
));
3873 radeon_set_context_reg(ctx_cs
, R_028818_PA_CL_VTE_CNTL
,
3874 S_028818_VTX_W0_FMT(1) |
3875 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3876 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3877 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3879 radeon_set_context_reg(ctx_cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
3880 S_02881C_USE_VTX_POINT_SIZE(outinfo
->writes_pointsize
) |
3881 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo
->writes_layer
) |
3882 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo
->writes_viewport_index
) |
3883 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
3884 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
) |
3885 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0f) != 0) |
3886 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xf0) != 0) |
3887 S_02881C_BYPASS_PRIM_RATE_COMBINER_GFX103(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10_3
) |
3888 cull_dist_mask
<< 8 |
3891 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
)
3892 radeon_set_context_reg(ctx_cs
, R_028AB4_VGT_REUSE_OFF
,
3893 outinfo
->writes_viewport_index
);
3897 radv_pipeline_generate_hw_es(struct radeon_cmdbuf
*cs
,
3898 struct radv_pipeline
*pipeline
,
3899 struct radv_shader_variant
*shader
)
3901 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3903 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 4);
3904 radeon_emit(cs
, va
>> 8);
3905 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
3906 radeon_emit(cs
, shader
->config
.rsrc1
);
3907 radeon_emit(cs
, shader
->config
.rsrc2
);
3911 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf
*cs
,
3912 struct radv_pipeline
*pipeline
,
3913 struct radv_shader_variant
*shader
,
3914 const struct radv_tessellation_state
*tess
)
3916 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3917 uint32_t rsrc2
= shader
->config
.rsrc2
;
3919 radeon_set_sh_reg_seq(cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
3920 radeon_emit(cs
, va
>> 8);
3921 radeon_emit(cs
, S_00B524_MEM_BASE(va
>> 40));
3923 rsrc2
|= S_00B52C_LDS_SIZE(tess
->lds_size
);
3924 if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX7
&&
3925 pipeline
->device
->physical_device
->rad_info
.family
!= CHIP_HAWAII
)
3926 radeon_set_sh_reg(cs
, R_00B52C_SPI_SHADER_PGM_RSRC2_LS
, rsrc2
);
3928 radeon_set_sh_reg_seq(cs
, R_00B528_SPI_SHADER_PGM_RSRC1_LS
, 2);
3929 radeon_emit(cs
, shader
->config
.rsrc1
);
3930 radeon_emit(cs
, rsrc2
);
3934 radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf
*ctx_cs
,
3935 struct radeon_cmdbuf
*cs
,
3936 struct radv_pipeline
*pipeline
,
3937 struct radv_shader_variant
*shader
)
3939 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3940 gl_shader_stage es_type
=
3941 radv_pipeline_has_tess(pipeline
) ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
3942 struct radv_shader_variant
*es
=
3943 es_type
== MESA_SHADER_TESS_EVAL
? pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] : pipeline
->shaders
[MESA_SHADER_VERTEX
];
3944 const struct gfx10_ngg_info
*ngg_state
= &shader
->info
.ngg_info
;
3946 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 2);
3947 radeon_emit(cs
, va
>> 8);
3948 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
3949 radeon_set_sh_reg_seq(cs
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, 2);
3950 radeon_emit(cs
, shader
->config
.rsrc1
);
3951 radeon_emit(cs
, shader
->config
.rsrc2
);
3953 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3954 unsigned clip_dist_mask
, cull_dist_mask
, total_mask
;
3955 clip_dist_mask
= outinfo
->clip_dist_mask
;
3956 cull_dist_mask
= outinfo
->cull_dist_mask
;
3957 total_mask
= clip_dist_mask
| cull_dist_mask
;
3958 bool misc_vec_ena
= outinfo
->writes_pointsize
||
3959 outinfo
->writes_layer
||
3960 outinfo
->writes_viewport_index
;
3961 bool es_enable_prim_id
= outinfo
->export_prim_id
||
3962 (es
&& es
->info
.uses_prim_id
);
3963 bool break_wave_at_eoi
= false;
3967 if (es_type
== MESA_SHADER_TESS_EVAL
) {
3968 struct radv_shader_variant
*gs
=
3969 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3971 if (es_enable_prim_id
|| (gs
&& gs
->info
.uses_prim_id
))
3972 break_wave_at_eoi
= true;
3975 nparams
= MAX2(outinfo
->param_exports
, 1);
3976 radeon_set_context_reg(ctx_cs
, R_0286C4_SPI_VS_OUT_CONFIG
,
3977 S_0286C4_VS_EXPORT_COUNT(nparams
- 1) |
3978 S_0286C4_NO_PC_EXPORT(outinfo
->param_exports
== 0));
3980 radeon_set_context_reg(ctx_cs
, R_028708_SPI_SHADER_IDX_FORMAT
,
3981 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP
));
3982 radeon_set_context_reg(ctx_cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
3983 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
3984 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
3985 V_02870C_SPI_SHADER_4COMP
:
3986 V_02870C_SPI_SHADER_NONE
) |
3987 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
3988 V_02870C_SPI_SHADER_4COMP
:
3989 V_02870C_SPI_SHADER_NONE
) |
3990 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
3991 V_02870C_SPI_SHADER_4COMP
:
3992 V_02870C_SPI_SHADER_NONE
));
3994 radeon_set_context_reg(ctx_cs
, R_028818_PA_CL_VTE_CNTL
,
3995 S_028818_VTX_W0_FMT(1) |
3996 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3997 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3998 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3999 radeon_set_context_reg(ctx_cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
4000 S_02881C_USE_VTX_POINT_SIZE(outinfo
->writes_pointsize
) |
4001 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo
->writes_layer
) |
4002 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo
->writes_viewport_index
) |
4003 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
4004 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
) |
4005 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0f) != 0) |
4006 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xf0) != 0) |
4007 S_02881C_BYPASS_PRIM_RATE_COMBINER_GFX103(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10_3
) |
4008 cull_dist_mask
<< 8 |
4011 radeon_set_context_reg(ctx_cs
, R_028A84_VGT_PRIMITIVEID_EN
,
4012 S_028A84_PRIMITIVEID_EN(es_enable_prim_id
) |
4013 S_028A84_NGG_DISABLE_PROVOK_REUSE(outinfo
->export_prim_id
));
4015 radeon_set_context_reg(ctx_cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
4016 ngg_state
->vgt_esgs_ring_itemsize
);
4018 /* NGG specific registers. */
4019 struct radv_shader_variant
*gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
4020 uint32_t gs_num_invocations
= gs
? gs
->info
.gs
.invocations
: 1;
4022 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
,
4023 S_028A44_ES_VERTS_PER_SUBGRP(ngg_state
->hw_max_esverts
) |
4024 S_028A44_GS_PRIMS_PER_SUBGRP(ngg_state
->max_gsprims
) |
4025 S_028A44_GS_INST_PRIMS_IN_SUBGRP(ngg_state
->max_gsprims
* gs_num_invocations
));
4026 radeon_set_context_reg(ctx_cs
, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP
,
4027 S_0287FC_MAX_VERTS_PER_SUBGROUP(ngg_state
->max_out_verts
));
4028 radeon_set_context_reg(ctx_cs
, R_028B4C_GE_NGG_SUBGRP_CNTL
,
4029 S_028B4C_PRIM_AMP_FACTOR(ngg_state
->prim_amp_factor
) |
4030 S_028B4C_THDS_PER_SUBGRP(0)); /* for fast launch */
4031 radeon_set_context_reg(ctx_cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
4032 S_028B90_CNT(gs_num_invocations
) |
4033 S_028B90_ENABLE(gs_num_invocations
> 1) |
4034 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(ngg_state
->max_vert_out_per_gs_instance
));
4036 /* User edge flags are set by the pos exports. If user edge flags are
4037 * not used, we must use hw-generated edge flags and pass them via
4038 * the prim export to prevent drawing lines on internal edges of
4039 * decomposed primitives (such as quads) with polygon mode = lines.
4041 * TODO: We should combine hw-generated edge flags with user edge
4042 * flags in the shader.
4044 radeon_set_context_reg(ctx_cs
, R_028838_PA_CL_NGG_CNTL
,
4045 S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline
) &&
4046 !radv_pipeline_has_gs(pipeline
)) |
4047 /* Reuse for NGG. */
4048 S_028838_VERTEX_REUSE_DEPTH_GFX103(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10_3
? 30 : 0));
4050 ge_cntl
= S_03096C_PRIM_GRP_SIZE(ngg_state
->max_gsprims
) |
4051 S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
4052 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
);
4054 /* Bug workaround for a possible hang with non-tessellation cases.
4055 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
4057 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
4059 if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX10
&&
4060 !radv_pipeline_has_tess(pipeline
) &&
4061 ngg_state
->hw_max_esverts
!= 256) {
4062 ge_cntl
&= C_03096C_VERT_GRP_SIZE
;
4064 if (ngg_state
->hw_max_esverts
> 5) {
4065 ge_cntl
|= S_03096C_VERT_GRP_SIZE(ngg_state
->hw_max_esverts
- 5);
4069 radeon_set_uconfig_reg(ctx_cs
, R_03096C_GE_CNTL
, ge_cntl
);
4073 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf
*cs
,
4074 struct radv_pipeline
*pipeline
,
4075 struct radv_shader_variant
*shader
,
4076 const struct radv_tessellation_state
*tess
)
4078 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
4080 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4081 unsigned hs_rsrc2
= shader
->config
.rsrc2
;
4083 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4084 hs_rsrc2
|= S_00B42C_LDS_SIZE_GFX10(tess
->lds_size
);
4086 hs_rsrc2
|= S_00B42C_LDS_SIZE_GFX9(tess
->lds_size
);
4089 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4090 radeon_set_sh_reg_seq(cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
4091 radeon_emit(cs
, va
>> 8);
4092 radeon_emit(cs
, S_00B524_MEM_BASE(va
>> 40));
4094 radeon_set_sh_reg_seq(cs
, R_00B410_SPI_SHADER_PGM_LO_LS
, 2);
4095 radeon_emit(cs
, va
>> 8);
4096 radeon_emit(cs
, S_00B414_MEM_BASE(va
>> 40));
4099 radeon_set_sh_reg_seq(cs
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
, 2);
4100 radeon_emit(cs
, shader
->config
.rsrc1
);
4101 radeon_emit(cs
, hs_rsrc2
);
4103 radeon_set_sh_reg_seq(cs
, R_00B420_SPI_SHADER_PGM_LO_HS
, 4);
4104 radeon_emit(cs
, va
>> 8);
4105 radeon_emit(cs
, S_00B424_MEM_BASE(va
>> 40));
4106 radeon_emit(cs
, shader
->config
.rsrc1
);
4107 radeon_emit(cs
, shader
->config
.rsrc2
);
4112 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf
*ctx_cs
,
4113 struct radeon_cmdbuf
*cs
,
4114 struct radv_pipeline
*pipeline
,
4115 const struct radv_tessellation_state
*tess
)
4117 struct radv_shader_variant
*vs
;
4119 /* Skip shaders merged into HS/GS */
4120 vs
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
4124 if (vs
->info
.vs
.as_ls
)
4125 radv_pipeline_generate_hw_ls(cs
, pipeline
, vs
, tess
);
4126 else if (vs
->info
.vs
.as_es
)
4127 radv_pipeline_generate_hw_es(cs
, pipeline
, vs
);
4128 else if (vs
->info
.is_ngg
)
4129 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, vs
);
4131 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, vs
);
4135 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf
*ctx_cs
,
4136 struct radeon_cmdbuf
*cs
,
4137 struct radv_pipeline
*pipeline
,
4138 const struct radv_tessellation_state
*tess
)
4140 if (!radv_pipeline_has_tess(pipeline
))
4143 struct radv_shader_variant
*tes
, *tcs
;
4145 tcs
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
4146 tes
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
4149 if (tes
->info
.is_ngg
) {
4150 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, tes
);
4151 } else if (tes
->info
.tes
.as_es
)
4152 radv_pipeline_generate_hw_es(cs
, pipeline
, tes
);
4154 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, tes
);
4157 radv_pipeline_generate_hw_hs(cs
, pipeline
, tcs
, tess
);
4159 radeon_set_context_reg(ctx_cs
, R_028B6C_VGT_TF_PARAM
,
4162 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
)
4163 radeon_set_context_reg_idx(ctx_cs
, R_028B58_VGT_LS_HS_CONFIG
, 2,
4164 tess
->ls_hs_config
);
4166 radeon_set_context_reg(ctx_cs
, R_028B58_VGT_LS_HS_CONFIG
,
4167 tess
->ls_hs_config
);
4169 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
&&
4170 !radv_pipeline_has_gs(pipeline
) && !radv_pipeline_has_ngg(pipeline
)) {
4171 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
,
4172 S_028A44_ES_VERTS_PER_SUBGRP(250) |
4173 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
4174 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
4179 radv_pipeline_generate_hw_gs(struct radeon_cmdbuf
*ctx_cs
,
4180 struct radeon_cmdbuf
*cs
,
4181 struct radv_pipeline
*pipeline
,
4182 struct radv_shader_variant
*gs
)
4184 const struct gfx9_gs_info
*gs_state
= &gs
->info
.gs_ring_info
;
4185 unsigned gs_max_out_vertices
;
4186 uint8_t *num_components
;
4191 gs_max_out_vertices
= gs
->info
.gs
.vertices_out
;
4192 max_stream
= gs
->info
.gs
.max_stream
;
4193 num_components
= gs
->info
.gs
.num_stream_output_components
;
4195 offset
= num_components
[0] * gs_max_out_vertices
;
4197 radeon_set_context_reg_seq(ctx_cs
, R_028A60_VGT_GSVS_RING_OFFSET_1
, 3);
4198 radeon_emit(ctx_cs
, offset
);
4199 if (max_stream
>= 1)
4200 offset
+= num_components
[1] * gs_max_out_vertices
;
4201 radeon_emit(ctx_cs
, offset
);
4202 if (max_stream
>= 2)
4203 offset
+= num_components
[2] * gs_max_out_vertices
;
4204 radeon_emit(ctx_cs
, offset
);
4205 if (max_stream
>= 3)
4206 offset
+= num_components
[3] * gs_max_out_vertices
;
4207 radeon_set_context_reg(ctx_cs
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, offset
);
4209 radeon_set_context_reg_seq(ctx_cs
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, 4);
4210 radeon_emit(ctx_cs
, num_components
[0]);
4211 radeon_emit(ctx_cs
, (max_stream
>= 1) ? num_components
[1] : 0);
4212 radeon_emit(ctx_cs
, (max_stream
>= 2) ? num_components
[2] : 0);
4213 radeon_emit(ctx_cs
, (max_stream
>= 3) ? num_components
[3] : 0);
4215 uint32_t gs_num_invocations
= gs
->info
.gs
.invocations
;
4216 radeon_set_context_reg(ctx_cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
4217 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
4218 S_028B90_ENABLE(gs_num_invocations
> 0));
4220 radeon_set_context_reg(ctx_cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
4221 gs_state
->vgt_esgs_ring_itemsize
);
4223 va
= radv_buffer_get_va(gs
->bo
) + gs
->bo_offset
;
4225 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4226 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4227 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 2);
4228 radeon_emit(cs
, va
>> 8);
4229 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
4231 radeon_set_sh_reg_seq(cs
, R_00B210_SPI_SHADER_PGM_LO_ES
, 2);
4232 radeon_emit(cs
, va
>> 8);
4233 radeon_emit(cs
, S_00B214_MEM_BASE(va
>> 40));
4236 radeon_set_sh_reg_seq(cs
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, 2);
4237 radeon_emit(cs
, gs
->config
.rsrc1
);
4238 radeon_emit(cs
, gs
->config
.rsrc2
| S_00B22C_LDS_SIZE(gs_state
->lds_size
));
4240 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
, gs_state
->vgt_gs_onchip_cntl
);
4241 radeon_set_context_reg(ctx_cs
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
, gs_state
->vgt_gs_max_prims_per_subgroup
);
4243 radeon_set_sh_reg_seq(cs
, R_00B220_SPI_SHADER_PGM_LO_GS
, 4);
4244 radeon_emit(cs
, va
>> 8);
4245 radeon_emit(cs
, S_00B224_MEM_BASE(va
>> 40));
4246 radeon_emit(cs
, gs
->config
.rsrc1
);
4247 radeon_emit(cs
, gs
->config
.rsrc2
);
4250 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, pipeline
->gs_copy_shader
);
4254 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf
*ctx_cs
,
4255 struct radeon_cmdbuf
*cs
,
4256 struct radv_pipeline
*pipeline
)
4258 struct radv_shader_variant
*gs
;
4260 gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
4264 if (gs
->info
.is_ngg
)
4265 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, gs
);
4267 radv_pipeline_generate_hw_gs(ctx_cs
, cs
, pipeline
, gs
);
4269 radeon_set_context_reg(ctx_cs
, R_028B38_VGT_GS_MAX_VERT_OUT
,
4270 gs
->info
.gs
.vertices_out
);
4273 static uint32_t offset_to_ps_input(uint32_t offset
, bool flat_shade
,
4274 bool explicit, bool float16
)
4276 uint32_t ps_input_cntl
;
4277 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
4278 ps_input_cntl
= S_028644_OFFSET(offset
);
4279 if (flat_shade
|| explicit)
4280 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
4282 /* Force parameter cache to be read in passthrough
4285 ps_input_cntl
|= S_028644_OFFSET(1 << 5);
4288 ps_input_cntl
|= S_028644_FP16_INTERP_MODE(1) |
4289 S_028644_ATTR0_VALID(1);
4292 /* The input is a DEFAULT_VAL constant. */
4293 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
4294 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
4295 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
4296 ps_input_cntl
= S_028644_OFFSET(0x20) |
4297 S_028644_DEFAULT_VAL(offset
);
4299 return ps_input_cntl
;
4303 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf
*ctx_cs
,
4304 struct radv_pipeline
*pipeline
)
4306 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4307 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
4308 uint32_t ps_input_cntl
[32];
4310 unsigned ps_offset
= 0;
4312 if (ps
->info
.ps
.prim_id_input
) {
4313 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
];
4314 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
4315 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false, false);
4320 if (ps
->info
.ps
.layer_input
||
4321 ps
->info
.needs_multiview_view_index
) {
4322 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
];
4323 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
)
4324 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false, false);
4326 ps_input_cntl
[ps_offset
] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000
, true, false, false);
4330 if (ps
->info
.ps
.viewport_index_input
) {
4331 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_VIEWPORT
];
4332 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
)
4333 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false, false);
4335 ps_input_cntl
[ps_offset
] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000
, true, false, false);
4339 if (ps
->info
.ps
.has_pcoord
) {
4341 val
= S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
4342 ps_input_cntl
[ps_offset
] = val
;
4346 if (ps
->info
.ps
.num_input_clips_culls
) {
4349 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST0
];
4350 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
4351 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, false, false, false);
4355 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST1
];
4356 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
&&
4357 ps
->info
.ps
.num_input_clips_culls
> 4) {
4358 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, false, false, false);
4363 for (unsigned i
= 0; i
< 32 && (1u << i
) <= ps
->info
.ps
.input_mask
; ++i
) {
4368 if (!(ps
->info
.ps
.input_mask
& (1u << i
)))
4371 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_VAR0
+ i
];
4372 if (vs_offset
== AC_EXP_PARAM_UNDEFINED
) {
4373 ps_input_cntl
[ps_offset
] = S_028644_OFFSET(0x20);
4378 flat_shade
= !!(ps
->info
.ps
.flat_shaded_mask
& (1u << ps_offset
));
4379 explicit = !!(ps
->info
.ps
.explicit_shaded_mask
& (1u << ps_offset
));
4380 float16
= !!(ps
->info
.ps
.float16_shaded_mask
& (1u << ps_offset
));
4382 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, flat_shade
, explicit, float16
);
4387 radeon_set_context_reg_seq(ctx_cs
, R_028644_SPI_PS_INPUT_CNTL_0
, ps_offset
);
4388 for (unsigned i
= 0; i
< ps_offset
; i
++) {
4389 radeon_emit(ctx_cs
, ps_input_cntl
[i
]);
4395 radv_compute_db_shader_control(const struct radv_device
*device
,
4396 const struct radv_pipeline
*pipeline
,
4397 const struct radv_shader_variant
*ps
)
4399 unsigned conservative_z_export
= V_02880C_EXPORT_ANY_Z
;
4401 if (ps
->info
.ps
.early_fragment_test
|| !ps
->info
.ps
.writes_memory
)
4402 z_order
= V_02880C_EARLY_Z_THEN_LATE_Z
;
4404 z_order
= V_02880C_LATE_Z
;
4406 if (ps
->info
.ps
.depth_layout
== FRAG_DEPTH_LAYOUT_GREATER
)
4407 conservative_z_export
= V_02880C_EXPORT_GREATER_THAN_Z
;
4408 else if (ps
->info
.ps
.depth_layout
== FRAG_DEPTH_LAYOUT_LESS
)
4409 conservative_z_export
= V_02880C_EXPORT_LESS_THAN_Z
;
4411 bool disable_rbplus
= device
->physical_device
->rad_info
.has_rbplus
&&
4412 !device
->physical_device
->rad_info
.rbplus_allowed
;
4414 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
4415 * but this appears to break Project Cars (DXVK). See
4416 * https://bugs.freedesktop.org/show_bug.cgi?id=109401
4418 bool mask_export_enable
= ps
->info
.ps
.writes_sample_mask
;
4420 return S_02880C_Z_EXPORT_ENABLE(ps
->info
.ps
.writes_z
) |
4421 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps
->info
.ps
.writes_stencil
) |
4422 S_02880C_KILL_ENABLE(!!ps
->info
.ps
.can_discard
) |
4423 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable
) |
4424 S_02880C_CONSERVATIVE_Z_EXPORT(conservative_z_export
) |
4425 S_02880C_Z_ORDER(z_order
) |
4426 S_02880C_DEPTH_BEFORE_SHADER(ps
->info
.ps
.early_fragment_test
) |
4427 S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps
->info
.ps
.post_depth_coverage
) |
4428 S_02880C_EXEC_ON_HIER_FAIL(ps
->info
.ps
.writes_memory
) |
4429 S_02880C_EXEC_ON_NOOP(ps
->info
.ps
.writes_memory
) |
4430 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus
);
4434 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf
*ctx_cs
,
4435 struct radeon_cmdbuf
*cs
,
4436 struct radv_pipeline
*pipeline
)
4438 struct radv_shader_variant
*ps
;
4440 assert (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
4442 ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4443 va
= radv_buffer_get_va(ps
->bo
) + ps
->bo_offset
;
4445 radeon_set_sh_reg_seq(cs
, R_00B020_SPI_SHADER_PGM_LO_PS
, 4);
4446 radeon_emit(cs
, va
>> 8);
4447 radeon_emit(cs
, S_00B024_MEM_BASE(va
>> 40));
4448 radeon_emit(cs
, ps
->config
.rsrc1
);
4449 radeon_emit(cs
, ps
->config
.rsrc2
);
4451 radeon_set_context_reg(ctx_cs
, R_02880C_DB_SHADER_CONTROL
,
4452 radv_compute_db_shader_control(pipeline
->device
,
4455 radeon_set_context_reg(ctx_cs
, R_0286CC_SPI_PS_INPUT_ENA
,
4456 ps
->config
.spi_ps_input_ena
);
4458 radeon_set_context_reg(ctx_cs
, R_0286D0_SPI_PS_INPUT_ADDR
,
4459 ps
->config
.spi_ps_input_addr
);
4461 radeon_set_context_reg(ctx_cs
, R_0286D8_SPI_PS_IN_CONTROL
,
4462 S_0286D8_NUM_INTERP(ps
->info
.ps
.num_interp
) |
4463 S_0286D8_PS_W32_EN(ps
->info
.wave_size
== 32));
4465 radeon_set_context_reg(ctx_cs
, R_0286E0_SPI_BARYC_CNTL
, pipeline
->graphics
.spi_baryc_cntl
);
4467 radeon_set_context_reg(ctx_cs
, R_028710_SPI_SHADER_Z_FORMAT
,
4468 ac_get_spi_shader_z_format(ps
->info
.ps
.writes_z
,
4469 ps
->info
.ps
.writes_stencil
,
4470 ps
->info
.ps
.writes_sample_mask
));
4472 if (pipeline
->device
->dfsm_allowed
) {
4473 /* optimise this? */
4474 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
4475 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
4480 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf
*ctx_cs
,
4481 struct radv_pipeline
*pipeline
)
4483 if (pipeline
->device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
||
4484 pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
)
4487 unsigned vtx_reuse_depth
= 30;
4488 if (radv_pipeline_has_tess(pipeline
) &&
4489 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.tes
.spacing
== TESS_SPACING_FRACTIONAL_ODD
) {
4490 vtx_reuse_depth
= 14;
4492 radeon_set_context_reg(ctx_cs
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
4493 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth
));
4497 radv_compute_vgt_shader_stages_en(const struct radv_pipeline
*pipeline
)
4499 uint32_t stages
= 0;
4500 if (radv_pipeline_has_tess(pipeline
)) {
4501 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
4502 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
4504 if (radv_pipeline_has_gs(pipeline
))
4505 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
4507 else if (radv_pipeline_has_ngg(pipeline
))
4508 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
);
4510 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
4511 } else if (radv_pipeline_has_gs(pipeline
)) {
4512 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
4514 } else if (radv_pipeline_has_ngg(pipeline
)) {
4515 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
);
4518 if (radv_pipeline_has_ngg(pipeline
)) {
4519 stages
|= S_028B54_PRIMGEN_EN(1);
4520 if (pipeline
->streamout_shader
)
4521 stages
|= S_028B54_NGG_WAVE_ID_EN(1);
4522 if (radv_pipeline_has_ngg_passthrough(pipeline
))
4523 stages
|= S_028B54_PRIMGEN_PASSTHRU_EN(1);
4524 } else if (radv_pipeline_has_gs(pipeline
)) {
4525 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
4528 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
4529 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
4531 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4532 uint8_t hs_size
= 64, gs_size
= 64, vs_size
= 64;
4534 if (radv_pipeline_has_tess(pipeline
))
4535 hs_size
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.wave_size
;
4537 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
]) {
4538 vs_size
= gs_size
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.wave_size
;
4539 if (pipeline
->gs_copy_shader
)
4540 vs_size
= pipeline
->gs_copy_shader
->info
.wave_size
;
4541 } else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
4542 vs_size
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.wave_size
;
4543 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
4544 vs_size
= pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.wave_size
;
4546 if (radv_pipeline_has_ngg(pipeline
))
4549 /* legacy GS only supports Wave64 */
4550 stages
|= S_028B54_HS_W32_EN(hs_size
== 32 ? 1 : 0) |
4551 S_028B54_GS_W32_EN(gs_size
== 32 ? 1 : 0) |
4552 S_028B54_VS_W32_EN(vs_size
== 32 ? 1 : 0);
4559 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
4561 const VkPipelineDiscardRectangleStateCreateInfoEXT
*discard_rectangle_info
=
4562 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
);
4564 if (!discard_rectangle_info
)
4569 for (unsigned i
= 0; i
< (1u << MAX_DISCARD_RECTANGLES
); ++i
) {
4570 /* Interpret i as a bitmask, and then set the bit in the mask if
4571 * that combination of rectangles in which the pixel is contained
4572 * should pass the cliprect test. */
4573 unsigned relevant_subset
= i
& ((1u << discard_rectangle_info
->discardRectangleCount
) - 1);
4575 if (discard_rectangle_info
->discardRectangleMode
== VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT
&&
4579 if (discard_rectangle_info
->discardRectangleMode
== VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT
&&
4590 gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf
*ctx_cs
,
4591 struct radv_pipeline
*pipeline
,
4592 const struct radv_tessellation_state
*tess
)
4594 bool break_wave_at_eoi
= false;
4595 unsigned primgroup_size
;
4596 unsigned vertgroup_size
= 256; /* 256 = disable vertex grouping */
4598 if (radv_pipeline_has_tess(pipeline
)) {
4599 primgroup_size
= tess
->num_patches
; /* must be a multiple of NUM_PATCHES */
4600 } else if (radv_pipeline_has_gs(pipeline
)) {
4601 const struct gfx9_gs_info
*gs_state
=
4602 &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.gs_ring_info
;
4603 unsigned vgt_gs_onchip_cntl
= gs_state
->vgt_gs_onchip_cntl
;
4604 primgroup_size
= G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl
);
4606 primgroup_size
= 128; /* recommended without a GS and tess */
4609 if (radv_pipeline_has_tess(pipeline
)) {
4610 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.uses_prim_id
||
4611 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.uses_prim_id
)
4612 break_wave_at_eoi
= true;
4615 radeon_set_uconfig_reg(ctx_cs
, R_03096C_GE_CNTL
,
4616 S_03096C_PRIM_GRP_SIZE(primgroup_size
) |
4617 S_03096C_VERT_GRP_SIZE(vertgroup_size
) |
4618 S_03096C_PACKET_TO_ONE_PA(0) /* line stipple */ |
4619 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
));
4623 radv_pipeline_generate_pm4(struct radv_pipeline
*pipeline
,
4624 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
4625 const struct radv_graphics_pipeline_create_info
*extra
,
4626 const struct radv_blend_state
*blend
,
4627 const struct radv_tessellation_state
*tess
,
4628 unsigned prim
, unsigned gs_out
)
4630 struct radeon_cmdbuf
*ctx_cs
= &pipeline
->ctx_cs
;
4631 struct radeon_cmdbuf
*cs
= &pipeline
->cs
;
4634 ctx_cs
->max_dw
= 256;
4635 cs
->buf
= malloc(4 * (cs
->max_dw
+ ctx_cs
->max_dw
));
4636 ctx_cs
->buf
= cs
->buf
+ cs
->max_dw
;
4638 radv_pipeline_generate_depth_stencil_state(ctx_cs
, pipeline
, pCreateInfo
, extra
);
4639 radv_pipeline_generate_blend_state(ctx_cs
, pipeline
, blend
);
4640 radv_pipeline_generate_raster_state(ctx_cs
, pipeline
, pCreateInfo
);
4641 radv_pipeline_generate_multisample_state(ctx_cs
, pipeline
);
4642 radv_pipeline_generate_vgt_gs_mode(ctx_cs
, pipeline
);
4643 radv_pipeline_generate_vertex_shader(ctx_cs
, cs
, pipeline
, tess
);
4644 radv_pipeline_generate_tess_shaders(ctx_cs
, cs
, pipeline
, tess
);
4645 radv_pipeline_generate_geometry_shader(ctx_cs
, cs
, pipeline
);
4646 radv_pipeline_generate_fragment_shader(ctx_cs
, cs
, pipeline
);
4647 radv_pipeline_generate_ps_inputs(ctx_cs
, pipeline
);
4648 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs
, pipeline
);
4649 radv_pipeline_generate_binning_state(ctx_cs
, pipeline
, pCreateInfo
, blend
);
4651 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
&& !radv_pipeline_has_ngg(pipeline
))
4652 gfx10_pipeline_generate_ge_cntl(ctx_cs
, pipeline
, tess
);
4654 radeon_set_context_reg(ctx_cs
, R_028B54_VGT_SHADER_STAGES_EN
, radv_compute_vgt_shader_stages_en(pipeline
));
4656 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
4657 radeon_set_uconfig_reg_idx(pipeline
->device
->physical_device
,
4658 cs
, R_030908_VGT_PRIMITIVE_TYPE
, 1, prim
);
4660 radeon_set_config_reg(cs
, R_008958_VGT_PRIMITIVE_TYPE
, prim
);
4662 radeon_set_context_reg(ctx_cs
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
, gs_out
);
4664 radeon_set_context_reg(ctx_cs
, R_02820C_PA_SC_CLIPRECT_RULE
, radv_compute_cliprect_rule(pCreateInfo
));
4666 pipeline
->ctx_cs_hash
= _mesa_hash_data(ctx_cs
->buf
, ctx_cs
->cdw
* 4);
4668 assert(ctx_cs
->cdw
<= ctx_cs
->max_dw
);
4669 assert(cs
->cdw
<= cs
->max_dw
);
4672 static struct radv_ia_multi_vgt_param_helpers
4673 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline
*pipeline
,
4674 const struct radv_tessellation_state
*tess
,
4677 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param
= {0};
4678 const struct radv_device
*device
= pipeline
->device
;
4680 if (radv_pipeline_has_tess(pipeline
))
4681 ia_multi_vgt_param
.primgroup_size
= tess
->num_patches
;
4682 else if (radv_pipeline_has_gs(pipeline
))
4683 ia_multi_vgt_param
.primgroup_size
= 64;
4685 ia_multi_vgt_param
.primgroup_size
= 128; /* recommended without a GS */
4687 /* GS requirement. */
4688 ia_multi_vgt_param
.partial_es_wave
= false;
4689 if (radv_pipeline_has_gs(pipeline
) && device
->physical_device
->rad_info
.chip_class
<= GFX8
)
4690 if (SI_GS_PER_ES
/ ia_multi_vgt_param
.primgroup_size
>= pipeline
->device
->gs_table_depth
- 3)
4691 ia_multi_vgt_param
.partial_es_wave
= true;
4693 ia_multi_vgt_param
.wd_switch_on_eop
= false;
4694 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
4695 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
4696 * 4 shader engines. Set 1 to pass the assertion below.
4697 * The other cases are hardware requirements. */
4698 if (device
->physical_device
->rad_info
.max_se
< 4 ||
4699 prim
== V_008958_DI_PT_POLYGON
||
4700 prim
== V_008958_DI_PT_LINELOOP
||
4701 prim
== V_008958_DI_PT_TRIFAN
||
4702 prim
== V_008958_DI_PT_TRISTRIP_ADJ
||
4703 (pipeline
->graphics
.prim_restart_enable
&&
4704 (device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
||
4705 (prim
!= V_008958_DI_PT_POINTLIST
&&
4706 prim
!= V_008958_DI_PT_LINESTRIP
))))
4707 ia_multi_vgt_param
.wd_switch_on_eop
= true;
4710 ia_multi_vgt_param
.ia_switch_on_eoi
= false;
4711 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.prim_id_input
)
4712 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4713 if (radv_pipeline_has_gs(pipeline
) &&
4714 pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.uses_prim_id
)
4715 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4716 if (radv_pipeline_has_tess(pipeline
)) {
4717 /* SWITCH_ON_EOI must be set if PrimID is used. */
4718 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.uses_prim_id
||
4719 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.uses_prim_id
)
4720 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4723 ia_multi_vgt_param
.partial_vs_wave
= false;
4724 if (radv_pipeline_has_tess(pipeline
)) {
4725 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
4726 if ((device
->physical_device
->rad_info
.family
== CHIP_TAHITI
||
4727 device
->physical_device
->rad_info
.family
== CHIP_PITCAIRN
||
4728 device
->physical_device
->rad_info
.family
== CHIP_BONAIRE
) &&
4729 radv_pipeline_has_gs(pipeline
))
4730 ia_multi_vgt_param
.partial_vs_wave
= true;
4731 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
4732 if (device
->physical_device
->rad_info
.has_distributed_tess
) {
4733 if (radv_pipeline_has_gs(pipeline
)) {
4734 if (device
->physical_device
->rad_info
.chip_class
<= GFX8
)
4735 ia_multi_vgt_param
.partial_es_wave
= true;
4737 ia_multi_vgt_param
.partial_vs_wave
= true;
4742 /* Workaround for a VGT hang when strip primitive types are used with
4743 * primitive restart.
4745 if (pipeline
->graphics
.prim_restart_enable
&&
4746 (prim
== V_008958_DI_PT_LINESTRIP
||
4747 prim
== V_008958_DI_PT_TRISTRIP
||
4748 prim
== V_008958_DI_PT_LINESTRIP_ADJ
||
4749 prim
== V_008958_DI_PT_TRISTRIP_ADJ
)) {
4750 ia_multi_vgt_param
.partial_vs_wave
= true;
4753 if (radv_pipeline_has_gs(pipeline
)) {
4754 /* On these chips there is the possibility of a hang if the
4755 * pipeline uses a GS and partial_vs_wave is not set.
4757 * This mostly does not hit 4-SE chips, as those typically set
4758 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
4759 * with GS due to another workaround.
4761 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
4763 if (device
->physical_device
->rad_info
.family
== CHIP_TONGA
||
4764 device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
4765 device
->physical_device
->rad_info
.family
== CHIP_POLARIS10
||
4766 device
->physical_device
->rad_info
.family
== CHIP_POLARIS11
||
4767 device
->physical_device
->rad_info
.family
== CHIP_POLARIS12
||
4768 device
->physical_device
->rad_info
.family
== CHIP_VEGAM
) {
4769 ia_multi_vgt_param
.partial_vs_wave
= true;
4773 ia_multi_vgt_param
.base
=
4774 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param
.primgroup_size
- 1) |
4775 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
4776 S_028AA8_MAX_PRIMGRP_IN_WAVE(device
->physical_device
->rad_info
.chip_class
== GFX8
? 2 : 0) |
4777 S_030960_EN_INST_OPT_BASIC(device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
4778 S_030960_EN_INST_OPT_ADV(device
->physical_device
->rad_info
.chip_class
>= GFX9
);
4780 return ia_multi_vgt_param
;
4785 radv_compute_vertex_input_state(struct radv_pipeline
*pipeline
,
4786 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
4788 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
4789 pCreateInfo
->pVertexInputState
;
4790 struct radv_vertex_elements_info
*velems
= &pipeline
->vertex_elements
;
4792 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
4793 const VkVertexInputAttributeDescription
*desc
=
4794 &vi_info
->pVertexAttributeDescriptions
[i
];
4795 unsigned loc
= desc
->location
;
4796 const struct vk_format_description
*format_desc
;
4798 format_desc
= vk_format_description(desc
->format
);
4800 velems
->format_size
[loc
] = format_desc
->block
.bits
/ 8;
4803 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
4804 const VkVertexInputBindingDescription
*desc
=
4805 &vi_info
->pVertexBindingDescriptions
[i
];
4807 pipeline
->binding_stride
[desc
->binding
] = desc
->stride
;
4808 pipeline
->num_vertex_bindings
=
4809 MAX2(pipeline
->num_vertex_bindings
, desc
->binding
+ 1);
4813 static struct radv_shader_variant
*
4814 radv_pipeline_get_streamout_shader(struct radv_pipeline
*pipeline
)
4818 for (i
= MESA_SHADER_GEOMETRY
; i
>= MESA_SHADER_VERTEX
; i
--) {
4819 struct radv_shader_variant
*shader
=
4820 radv_get_shader(pipeline
, i
);
4822 if (shader
&& shader
->info
.so
.num_outputs
> 0)
4830 radv_secure_compile(struct radv_pipeline
*pipeline
,
4831 struct radv_device
*device
,
4832 const struct radv_pipeline_key
*key
,
4833 const VkPipelineShaderStageCreateInfo
**pStages
,
4834 const VkPipelineCreateFlags flags
,
4835 unsigned num_stages
)
4837 uint8_t allowed_pipeline_hashes
[2][20];
4838 radv_hash_shaders(allowed_pipeline_hashes
[0], pStages
,
4839 pipeline
->layout
, key
, get_hash_flags(device
));
4841 /* Generate the GC copy hash */
4842 memcpy(allowed_pipeline_hashes
[1], allowed_pipeline_hashes
[0], 20);
4843 allowed_pipeline_hashes
[1][0] ^= 1;
4845 uint8_t allowed_hashes
[2][20];
4846 for (unsigned i
= 0; i
< 2; ++i
) {
4847 disk_cache_compute_key(device
->physical_device
->disk_cache
,
4848 allowed_pipeline_hashes
[i
], 20,
4852 /* Do an early exit if all cache entries are already there. */
4853 bool may_need_copy_shader
= pStages
[MESA_SHADER_GEOMETRY
];
4854 void *main_entry
= disk_cache_get(device
->physical_device
->disk_cache
, allowed_hashes
[0], NULL
);
4855 void *copy_entry
= NULL
;
4856 if (may_need_copy_shader
)
4857 copy_entry
= disk_cache_get(device
->physical_device
->disk_cache
, allowed_hashes
[1], NULL
);
4859 bool has_all_cache_entries
= main_entry
&& (!may_need_copy_shader
|| copy_entry
);
4863 if(has_all_cache_entries
)
4866 unsigned process
= 0;
4867 uint8_t sc_threads
= device
->instance
->num_sc_threads
;
4869 mtx_lock(&device
->sc_state
->secure_compile_mutex
);
4870 if (device
->sc_state
->secure_compile_thread_counter
< sc_threads
) {
4871 device
->sc_state
->secure_compile_thread_counter
++;
4872 for (unsigned i
= 0; i
< sc_threads
; i
++) {
4873 if (!device
->sc_state
->secure_compile_processes
[i
].in_use
) {
4874 device
->sc_state
->secure_compile_processes
[i
].in_use
= true;
4879 mtx_unlock(&device
->sc_state
->secure_compile_mutex
);
4882 mtx_unlock(&device
->sc_state
->secure_compile_mutex
);
4885 int fd_secure_input
= device
->sc_state
->secure_compile_processes
[process
].fd_secure_input
;
4886 int fd_secure_output
= device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
;
4888 /* Fork a copy of the slim untainted secure compile process */
4889 enum radv_secure_compile_type sc_type
= RADV_SC_TYPE_FORK_DEVICE
;
4890 write(fd_secure_input
, &sc_type
, sizeof(sc_type
));
4892 if (!radv_sc_read(fd_secure_output
, &sc_type
, sizeof(sc_type
), true) ||
4893 sc_type
!= RADV_SC_TYPE_INIT_SUCCESS
)
4894 return VK_ERROR_DEVICE_LOST
;
4896 fd_secure_input
= device
->sc_state
->secure_compile_processes
[process
].fd_server
;
4897 fd_secure_output
= device
->sc_state
->secure_compile_processes
[process
].fd_client
;
4899 /* Write pipeline / shader module out to secure process via pipe */
4900 sc_type
= RADV_SC_TYPE_COMPILE_PIPELINE
;
4901 write(fd_secure_input
, &sc_type
, sizeof(sc_type
));
4903 /* Write pipeline layout out to secure process */
4904 struct radv_pipeline_layout
*layout
= pipeline
->layout
;
4905 write(fd_secure_input
, layout
, sizeof(struct radv_pipeline_layout
));
4906 write(fd_secure_input
, &layout
->num_sets
, sizeof(uint32_t));
4907 for (uint32_t set
= 0; set
< layout
->num_sets
; set
++) {
4908 write(fd_secure_input
, &layout
->set
[set
].layout
->layout_size
, sizeof(uint32_t));
4909 write(fd_secure_input
, layout
->set
[set
].layout
, layout
->set
[set
].layout
->layout_size
);
4912 /* Write pipeline key out to secure process */
4913 write(fd_secure_input
, key
, sizeof(struct radv_pipeline_key
));
4915 /* Write pipeline create flags out to secure process */
4916 write(fd_secure_input
, &flags
, sizeof(VkPipelineCreateFlags
));
4918 /* Write stage and shader information out to secure process */
4919 write(fd_secure_input
, &num_stages
, sizeof(uint32_t));
4920 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
4924 /* Write stage out to secure process */
4925 gl_shader_stage stage
= ffs(pStages
[i
]->stage
) - 1;
4926 write(fd_secure_input
, &stage
, sizeof(gl_shader_stage
));
4928 /* Write entry point name out to secure process */
4929 size_t name_size
= strlen(pStages
[i
]->pName
) + 1;
4930 write(fd_secure_input
, &name_size
, sizeof(size_t));
4931 write(fd_secure_input
, pStages
[i
]->pName
, name_size
);
4933 /* Write shader module out to secure process */
4934 struct radv_shader_module
*module
= radv_shader_module_from_handle(pStages
[i
]->module
);
4935 assert(!module
->nir
);
4936 size_t module_size
= sizeof(struct radv_shader_module
) + module
->size
;
4937 write(fd_secure_input
, &module_size
, sizeof(size_t));
4938 write(fd_secure_input
, module
, module_size
);
4940 /* Write specialization info out to secure process */
4941 const VkSpecializationInfo
*specInfo
= pStages
[i
]->pSpecializationInfo
;
4942 bool has_spec_info
= specInfo
? true : false;
4943 write(fd_secure_input
, &has_spec_info
, sizeof(bool));
4945 write(fd_secure_input
, &specInfo
->dataSize
, sizeof(size_t));
4946 write(fd_secure_input
, specInfo
->pData
, specInfo
->dataSize
);
4948 write(fd_secure_input
, &specInfo
->mapEntryCount
, sizeof(uint32_t));
4949 for (uint32_t j
= 0; j
< specInfo
->mapEntryCount
; j
++)
4950 write(fd_secure_input
, &specInfo
->pMapEntries
[j
], sizeof(VkSpecializationMapEntry
));
4954 /* Read the data returned from the secure process */
4955 while (sc_type
!= RADV_SC_TYPE_COMPILE_PIPELINE_FINISHED
) {
4956 if (!radv_sc_read(fd_secure_output
, &sc_type
, sizeof(sc_type
), true))
4957 return VK_ERROR_DEVICE_LOST
;
4959 if (sc_type
== RADV_SC_TYPE_WRITE_DISK_CACHE
) {
4960 assert(device
->physical_device
->disk_cache
);
4962 uint8_t disk_sha1
[20];
4963 if (!radv_sc_read(fd_secure_output
, disk_sha1
, sizeof(uint8_t) * 20, true))
4964 return VK_ERROR_DEVICE_LOST
;
4966 if (memcmp(disk_sha1
, allowed_hashes
[0], 20) &&
4967 memcmp(disk_sha1
, allowed_hashes
[1], 20))
4968 return VK_ERROR_DEVICE_LOST
;
4970 uint32_t entry_size
;
4971 if (!radv_sc_read(fd_secure_output
, &entry_size
, sizeof(uint32_t), true))
4972 return VK_ERROR_DEVICE_LOST
;
4974 struct cache_entry
*entry
= malloc(entry_size
);
4975 if (!radv_sc_read(fd_secure_output
, entry
, entry_size
, true))
4976 return VK_ERROR_DEVICE_LOST
;
4978 disk_cache_put(device
->physical_device
->disk_cache
,
4979 disk_sha1
, entry
, entry_size
,
4983 } else if (sc_type
== RADV_SC_TYPE_READ_DISK_CACHE
) {
4984 uint8_t disk_sha1
[20];
4985 if (!radv_sc_read(fd_secure_output
, disk_sha1
, sizeof(uint8_t) * 20, true))
4986 return VK_ERROR_DEVICE_LOST
;
4988 if (memcmp(disk_sha1
, allowed_hashes
[0], 20) &&
4989 memcmp(disk_sha1
, allowed_hashes
[1], 20))
4990 return VK_ERROR_DEVICE_LOST
;
4993 struct cache_entry
*entry
= (struct cache_entry
*)
4994 disk_cache_get(device
->physical_device
->disk_cache
,
4997 uint8_t found
= entry
? 1 : 0;
4998 write(fd_secure_input
, &found
, sizeof(uint8_t));
5001 write(fd_secure_input
, &size
, sizeof(size_t));
5002 write(fd_secure_input
, entry
, size
);
5009 sc_type
= RADV_SC_TYPE_DESTROY_DEVICE
;
5010 write(fd_secure_input
, &sc_type
, sizeof(sc_type
));
5012 mtx_lock(&device
->sc_state
->secure_compile_mutex
);
5013 device
->sc_state
->secure_compile_thread_counter
--;
5014 device
->sc_state
->secure_compile_processes
[process
].in_use
= false;
5015 mtx_unlock(&device
->sc_state
->secure_compile_mutex
);
5021 radv_pipeline_init(struct radv_pipeline
*pipeline
,
5022 struct radv_device
*device
,
5023 struct radv_pipeline_cache
*cache
,
5024 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
5025 const struct radv_graphics_pipeline_create_info
*extra
)
5028 bool has_view_index
= false;
5030 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
5031 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
5032 if (subpass
->view_mask
)
5033 has_view_index
= true;
5035 pipeline
->device
= device
;
5036 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
5037 assert(pipeline
->layout
);
5039 struct radv_blend_state blend
= radv_pipeline_init_blend_state(pipeline
, pCreateInfo
, extra
);
5041 const VkPipelineCreationFeedbackCreateInfoEXT
*creation_feedback
=
5042 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
5043 radv_init_feedback(creation_feedback
);
5045 VkPipelineCreationFeedbackEXT
*pipeline_feedback
= creation_feedback
? creation_feedback
->pPipelineCreationFeedback
: NULL
;
5047 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
5048 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
5049 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
5050 gl_shader_stage stage
= ffs(pCreateInfo
->pStages
[i
].stage
) - 1;
5051 pStages
[stage
] = &pCreateInfo
->pStages
[i
];
5052 if(creation_feedback
)
5053 stage_feedbacks
[stage
] = &creation_feedback
->pPipelineStageCreationFeedbacks
[i
];
5056 struct radv_pipeline_key key
= radv_generate_graphics_pipeline_key(pipeline
, pCreateInfo
, &blend
, has_view_index
);
5057 if (radv_device_use_secure_compile(device
->instance
)) {
5058 return radv_secure_compile(pipeline
, device
, &key
, pStages
, pCreateInfo
->flags
, pCreateInfo
->stageCount
);
5060 result
= radv_create_shaders(pipeline
, device
, cache
, &key
, pStages
,
5061 pCreateInfo
->flags
, pipeline_feedback
,
5063 if (result
!= VK_SUCCESS
)
5067 pipeline
->graphics
.spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
5068 radv_pipeline_init_multisample_state(pipeline
, &blend
, pCreateInfo
);
5070 uint32_t prim
= si_translate_prim(pCreateInfo
->pInputAssemblyState
->topology
);
5072 pipeline
->graphics
.topology
= pCreateInfo
->pInputAssemblyState
->topology
;
5073 pipeline
->graphics
.can_use_guardband
= radv_prim_can_use_guardband(pCreateInfo
->pInputAssemblyState
->topology
);
5075 if (radv_pipeline_has_gs(pipeline
)) {
5076 gs_out
= si_conv_gl_prim_to_gs_out(pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.gs
.output_prim
);
5077 pipeline
->graphics
.can_use_guardband
= gs_out
== V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
5078 } else if (radv_pipeline_has_tess(pipeline
)) {
5079 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.point_mode
)
5080 gs_out
= V_028A6C_OUTPRIM_TYPE_POINTLIST
;
5082 gs_out
= si_conv_gl_prim_to_gs_out(pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.primitive_mode
);
5083 pipeline
->graphics
.can_use_guardband
= gs_out
== V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
5085 gs_out
= si_conv_prim_to_gs_out(pCreateInfo
->pInputAssemblyState
->topology
);
5087 if (extra
&& extra
->use_rectlist
) {
5088 prim
= V_008958_DI_PT_RECTLIST
;
5089 gs_out
= V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
5090 pipeline
->graphics
.can_use_guardband
= true;
5091 if (radv_pipeline_has_ngg(pipeline
))
5092 gs_out
= V_028A6C_VGT_OUT_RECT_V0
;
5094 pipeline
->graphics
.prim_restart_enable
= !!pCreateInfo
->pInputAssemblyState
->primitiveRestartEnable
;
5095 /* prim vertex count will need TESS changes */
5096 pipeline
->graphics
.prim_vertex_count
= prim_size_table
[prim
];
5098 radv_pipeline_init_dynamic_state(pipeline
, pCreateInfo
);
5100 /* Ensure that some export memory is always allocated, for two reasons:
5102 * 1) Correctness: The hardware ignores the EXEC mask if no export
5103 * memory is allocated, so KILL and alpha test do not work correctly
5105 * 2) Performance: Every shader needs at least a NULL export, even when
5106 * it writes no color/depth output. The NULL export instruction
5107 * stalls without this setting.
5109 * Don't add this to CB_SHADER_MASK.
5111 * GFX10 supports pixel shaders without exports by setting both the
5112 * color and Z formats to SPI_SHADER_ZERO. The hw will skip export
5113 * instructions if any are present.
5115 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
5116 if ((pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX9
||
5117 ps
->info
.ps
.can_discard
) &&
5118 !blend
.spi_shader_col_format
) {
5119 if (!ps
->info
.ps
.writes_z
&&
5120 !ps
->info
.ps
.writes_stencil
&&
5121 !ps
->info
.ps
.writes_sample_mask
)
5122 blend
.spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
5125 blend
.cb_shader_mask
= ps
->info
.ps
.cb_shader_mask
;
5128 (extra
->custom_blend_mode
== V_028808_CB_ELIMINATE_FAST_CLEAR
||
5129 extra
->custom_blend_mode
== V_028808_CB_FMASK_DECOMPRESS
||
5130 extra
->custom_blend_mode
== V_028808_CB_DCC_DECOMPRESS
||
5131 extra
->custom_blend_mode
== V_028808_CB_RESOLVE
)) {
5132 /* According to the CB spec states, CB_SHADER_MASK should be
5133 * set to enable writes to all four channels of MRT0.
5135 blend
.cb_shader_mask
= 0xf;
5138 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
5139 if (pipeline
->shaders
[i
]) {
5140 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[i
]->info
.need_indirect_descriptor_sets
;
5144 if (radv_pipeline_has_gs(pipeline
) && !radv_pipeline_has_ngg(pipeline
)) {
5145 struct radv_shader_variant
*gs
=
5146 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
5148 calculate_gs_ring_sizes(pipeline
, &gs
->info
.gs_ring_info
);
5151 struct radv_tessellation_state tess
= {0};
5152 if (radv_pipeline_has_tess(pipeline
)) {
5153 if (prim
== V_008958_DI_PT_PATCH
) {
5154 pipeline
->graphics
.prim_vertex_count
.min
= pCreateInfo
->pTessellationState
->patchControlPoints
;
5155 pipeline
->graphics
.prim_vertex_count
.incr
= 1;
5157 tess
= calculate_tess_state(pipeline
, pCreateInfo
);
5160 pipeline
->graphics
.ia_multi_vgt_param
= radv_compute_ia_multi_vgt_param_helpers(pipeline
, &tess
, prim
);
5162 radv_compute_vertex_input_state(pipeline
, pCreateInfo
);
5164 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++)
5165 pipeline
->user_data_0
[i
] = radv_pipeline_stage_to_user_data_0(pipeline
, i
, device
->physical_device
->rad_info
.chip_class
);
5167 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_VERTEX
,
5168 AC_UD_VS_BASE_VERTEX_START_INSTANCE
);
5169 if (loc
->sgpr_idx
!= -1) {
5170 pipeline
->graphics
.vtx_base_sgpr
= pipeline
->user_data_0
[MESA_SHADER_VERTEX
];
5171 pipeline
->graphics
.vtx_base_sgpr
+= loc
->sgpr_idx
* 4;
5172 if (radv_get_shader(pipeline
, MESA_SHADER_VERTEX
)->info
.vs
.needs_draw_id
)
5173 pipeline
->graphics
.vtx_emit_num
= 3;
5175 pipeline
->graphics
.vtx_emit_num
= 2;
5178 /* Find the last vertex shader stage that eventually uses streamout. */
5179 pipeline
->streamout_shader
= radv_pipeline_get_streamout_shader(pipeline
);
5181 result
= radv_pipeline_scratch_init(device
, pipeline
);
5182 radv_pipeline_generate_pm4(pipeline
, pCreateInfo
, extra
, &blend
, &tess
, prim
, gs_out
);
5188 radv_graphics_pipeline_create(
5190 VkPipelineCache _cache
,
5191 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
5192 const struct radv_graphics_pipeline_create_info
*extra
,
5193 const VkAllocationCallbacks
*pAllocator
,
5194 VkPipeline
*pPipeline
)
5196 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5197 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
5198 struct radv_pipeline
*pipeline
;
5201 pipeline
= vk_zalloc2(&device
->vk
.alloc
, pAllocator
, sizeof(*pipeline
), 8,
5202 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5203 if (pipeline
== NULL
)
5204 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5206 vk_object_base_init(&device
->vk
, &pipeline
->base
,
5207 VK_OBJECT_TYPE_PIPELINE
);
5209 result
= radv_pipeline_init(pipeline
, device
, cache
,
5210 pCreateInfo
, extra
);
5211 if (result
!= VK_SUCCESS
) {
5212 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
5216 *pPipeline
= radv_pipeline_to_handle(pipeline
);
5221 VkResult
radv_CreateGraphicsPipelines(
5223 VkPipelineCache pipelineCache
,
5225 const VkGraphicsPipelineCreateInfo
* pCreateInfos
,
5226 const VkAllocationCallbacks
* pAllocator
,
5227 VkPipeline
* pPipelines
)
5229 VkResult result
= VK_SUCCESS
;
5232 for (; i
< count
; i
++) {
5234 r
= radv_graphics_pipeline_create(_device
,
5237 NULL
, pAllocator
, &pPipelines
[i
]);
5238 if (r
!= VK_SUCCESS
) {
5240 pPipelines
[i
] = VK_NULL_HANDLE
;
5242 if (pCreateInfos
[i
].flags
& VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT
)
5247 for (; i
< count
; ++i
)
5248 pPipelines
[i
] = VK_NULL_HANDLE
;
5255 radv_compute_generate_pm4(struct radv_pipeline
*pipeline
)
5257 struct radv_shader_variant
*compute_shader
;
5258 struct radv_device
*device
= pipeline
->device
;
5259 unsigned threads_per_threadgroup
;
5260 unsigned threadgroups_per_cu
= 1;
5261 unsigned waves_per_threadgroup
;
5262 unsigned max_waves_per_sh
= 0;
5265 pipeline
->cs
.max_dw
= device
->physical_device
->rad_info
.chip_class
>= GFX10
? 22 : 20;
5266 pipeline
->cs
.buf
= malloc(pipeline
->cs
.max_dw
* 4);
5268 compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
5269 va
= radv_buffer_get_va(compute_shader
->bo
) + compute_shader
->bo_offset
;
5271 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B830_COMPUTE_PGM_LO
, 2);
5272 radeon_emit(&pipeline
->cs
, va
>> 8);
5273 radeon_emit(&pipeline
->cs
, S_00B834_DATA(va
>> 40));
5275 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B848_COMPUTE_PGM_RSRC1
, 2);
5276 radeon_emit(&pipeline
->cs
, compute_shader
->config
.rsrc1
);
5277 radeon_emit(&pipeline
->cs
, compute_shader
->config
.rsrc2
);
5278 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
5279 radeon_set_sh_reg(&pipeline
->cs
, R_00B8A0_COMPUTE_PGM_RSRC3
, compute_shader
->config
.rsrc3
);
5282 /* Calculate best compute resource limits. */
5283 threads_per_threadgroup
= compute_shader
->info
.cs
.block_size
[0] *
5284 compute_shader
->info
.cs
.block_size
[1] *
5285 compute_shader
->info
.cs
.block_size
[2];
5286 waves_per_threadgroup
= DIV_ROUND_UP(threads_per_threadgroup
,
5287 compute_shader
->info
.wave_size
);
5289 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
&&
5290 waves_per_threadgroup
== 1)
5291 threadgroups_per_cu
= 2;
5293 radeon_set_sh_reg(&pipeline
->cs
, R_00B854_COMPUTE_RESOURCE_LIMITS
,
5294 ac_get_compute_resource_limits(&device
->physical_device
->rad_info
,
5295 waves_per_threadgroup
,
5297 threadgroups_per_cu
));
5299 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
5300 radeon_emit(&pipeline
->cs
,
5301 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[0]));
5302 radeon_emit(&pipeline
->cs
,
5303 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[1]));
5304 radeon_emit(&pipeline
->cs
,
5305 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[2]));
5307 assert(pipeline
->cs
.cdw
<= pipeline
->cs
.max_dw
);
5310 static struct radv_pipeline_key
5311 radv_generate_compute_pipeline_key(struct radv_pipeline
*pipeline
,
5312 const VkComputePipelineCreateInfo
*pCreateInfo
)
5314 const VkPipelineShaderStageCreateInfo
*stage
= &pCreateInfo
->stage
;
5315 struct radv_pipeline_key key
;
5316 memset(&key
, 0, sizeof(key
));
5318 if (pCreateInfo
->flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
)
5319 key
.optimisations_disabled
= 1;
5321 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT
*subgroup_size
=
5322 vk_find_struct_const(stage
->pNext
,
5323 PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT
);
5325 if (subgroup_size
) {
5326 assert(subgroup_size
->requiredSubgroupSize
== 32 ||
5327 subgroup_size
->requiredSubgroupSize
== 64);
5328 key
.compute_subgroup_size
= subgroup_size
->requiredSubgroupSize
;
5334 static VkResult
radv_compute_pipeline_create(
5336 VkPipelineCache _cache
,
5337 const VkComputePipelineCreateInfo
* pCreateInfo
,
5338 const VkAllocationCallbacks
* pAllocator
,
5339 VkPipeline
* pPipeline
)
5341 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5342 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
5343 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
5344 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
5345 struct radv_pipeline
*pipeline
;
5348 pipeline
= vk_zalloc2(&device
->vk
.alloc
, pAllocator
, sizeof(*pipeline
), 8,
5349 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5350 if (pipeline
== NULL
)
5351 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5353 vk_object_base_init(&device
->vk
, &pipeline
->base
,
5354 VK_OBJECT_TYPE_PIPELINE
);
5356 pipeline
->device
= device
;
5357 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
5358 assert(pipeline
->layout
);
5360 const VkPipelineCreationFeedbackCreateInfoEXT
*creation_feedback
=
5361 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
5362 radv_init_feedback(creation_feedback
);
5364 VkPipelineCreationFeedbackEXT
*pipeline_feedback
= creation_feedback
? creation_feedback
->pPipelineCreationFeedback
: NULL
;
5365 if (creation_feedback
)
5366 stage_feedbacks
[MESA_SHADER_COMPUTE
] = &creation_feedback
->pPipelineStageCreationFeedbacks
[0];
5368 pStages
[MESA_SHADER_COMPUTE
] = &pCreateInfo
->stage
;
5370 struct radv_pipeline_key key
=
5371 radv_generate_compute_pipeline_key(pipeline
, pCreateInfo
);
5373 if (radv_device_use_secure_compile(device
->instance
)) {
5374 result
= radv_secure_compile(pipeline
, device
, &key
, pStages
, pCreateInfo
->flags
, 1);
5375 *pPipeline
= radv_pipeline_to_handle(pipeline
);
5379 result
= radv_create_shaders(pipeline
, device
, cache
, &key
, pStages
,
5380 pCreateInfo
->flags
, pipeline_feedback
,
5382 if (result
!= VK_SUCCESS
) {
5383 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
5388 pipeline
->user_data_0
[MESA_SHADER_COMPUTE
] = radv_pipeline_stage_to_user_data_0(pipeline
, MESA_SHADER_COMPUTE
, device
->physical_device
->rad_info
.chip_class
);
5389 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.need_indirect_descriptor_sets
;
5390 result
= radv_pipeline_scratch_init(device
, pipeline
);
5391 if (result
!= VK_SUCCESS
) {
5392 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
5396 radv_compute_generate_pm4(pipeline
);
5398 *pPipeline
= radv_pipeline_to_handle(pipeline
);
5403 VkResult
radv_CreateComputePipelines(
5405 VkPipelineCache pipelineCache
,
5407 const VkComputePipelineCreateInfo
* pCreateInfos
,
5408 const VkAllocationCallbacks
* pAllocator
,
5409 VkPipeline
* pPipelines
)
5411 VkResult result
= VK_SUCCESS
;
5414 for (; i
< count
; i
++) {
5416 r
= radv_compute_pipeline_create(_device
, pipelineCache
,
5418 pAllocator
, &pPipelines
[i
]);
5419 if (r
!= VK_SUCCESS
) {
5421 pPipelines
[i
] = VK_NULL_HANDLE
;
5423 if (pCreateInfos
[i
].flags
& VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT
)
5428 for (; i
< count
; ++i
)
5429 pPipelines
[i
] = VK_NULL_HANDLE
;
5435 static uint32_t radv_get_executable_count(const struct radv_pipeline
*pipeline
)
5438 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
5439 if (!pipeline
->shaders
[i
])
5442 if (i
== MESA_SHADER_GEOMETRY
&&
5443 !radv_pipeline_has_ngg(pipeline
)) {
5453 static struct radv_shader_variant
*
5454 radv_get_shader_from_executable_index(const struct radv_pipeline
*pipeline
, int index
, gl_shader_stage
*stage
)
5456 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
5457 if (!pipeline
->shaders
[i
])
5461 return pipeline
->shaders
[i
];
5466 if (i
== MESA_SHADER_GEOMETRY
&&
5467 !radv_pipeline_has_ngg(pipeline
)) {
5470 return pipeline
->gs_copy_shader
;
5480 /* Basically strlcpy (which does not exist on linux) specialized for
5482 static void desc_copy(char *desc
, const char *src
) {
5483 int len
= strlen(src
);
5484 assert(len
< VK_MAX_DESCRIPTION_SIZE
);
5485 memcpy(desc
, src
, len
);
5486 memset(desc
+ len
, 0, VK_MAX_DESCRIPTION_SIZE
- len
);
5489 VkResult
radv_GetPipelineExecutablePropertiesKHR(
5491 const VkPipelineInfoKHR
* pPipelineInfo
,
5492 uint32_t* pExecutableCount
,
5493 VkPipelineExecutablePropertiesKHR
* pProperties
)
5495 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pPipelineInfo
->pipeline
);
5496 const uint32_t total_count
= radv_get_executable_count(pipeline
);
5499 *pExecutableCount
= total_count
;
5503 const uint32_t count
= MIN2(total_count
, *pExecutableCount
);
5504 for (unsigned i
= 0, executable_idx
= 0;
5505 i
< MESA_SHADER_STAGES
&& executable_idx
< count
; ++i
) {
5506 if (!pipeline
->shaders
[i
])
5508 pProperties
[executable_idx
].stages
= mesa_to_vk_shader_stage(i
);
5509 const char *name
= NULL
;
5510 const char *description
= NULL
;
5512 case MESA_SHADER_VERTEX
:
5513 name
= "Vertex Shader";
5514 description
= "Vulkan Vertex Shader";
5516 case MESA_SHADER_TESS_CTRL
:
5517 if (!pipeline
->shaders
[MESA_SHADER_VERTEX
]) {
5518 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_VERTEX_BIT
;
5519 name
= "Vertex + Tessellation Control Shaders";
5520 description
= "Combined Vulkan Vertex and Tessellation Control Shaders";
5522 name
= "Tessellation Control Shader";
5523 description
= "Vulkan Tessellation Control Shader";
5526 case MESA_SHADER_TESS_EVAL
:
5527 name
= "Tessellation Evaluation Shader";
5528 description
= "Vulkan Tessellation Evaluation Shader";
5530 case MESA_SHADER_GEOMETRY
:
5531 if (radv_pipeline_has_tess(pipeline
) && !pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]) {
5532 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
;
5533 name
= "Tessellation Evaluation + Geometry Shaders";
5534 description
= "Combined Vulkan Tessellation Evaluation and Geometry Shaders";
5535 } else if (!radv_pipeline_has_tess(pipeline
) && !pipeline
->shaders
[MESA_SHADER_VERTEX
]) {
5536 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_VERTEX_BIT
;
5537 name
= "Vertex + Geometry Shader";
5538 description
= "Combined Vulkan Vertex and Geometry Shaders";
5540 name
= "Geometry Shader";
5541 description
= "Vulkan Geometry Shader";
5544 case MESA_SHADER_FRAGMENT
:
5545 name
= "Fragment Shader";
5546 description
= "Vulkan Fragment Shader";
5548 case MESA_SHADER_COMPUTE
:
5549 name
= "Compute Shader";
5550 description
= "Vulkan Compute Shader";
5554 pProperties
[executable_idx
].subgroupSize
= pipeline
->shaders
[i
]->info
.wave_size
;
5555 desc_copy(pProperties
[executable_idx
].name
, name
);
5556 desc_copy(pProperties
[executable_idx
].description
, description
);
5559 if (i
== MESA_SHADER_GEOMETRY
&&
5560 !radv_pipeline_has_ngg(pipeline
)) {
5561 assert(pipeline
->gs_copy_shader
);
5562 if (executable_idx
>= count
)
5565 pProperties
[executable_idx
].stages
= VK_SHADER_STAGE_GEOMETRY_BIT
;
5566 pProperties
[executable_idx
].subgroupSize
= 64;
5567 desc_copy(pProperties
[executable_idx
].name
, "GS Copy Shader");
5568 desc_copy(pProperties
[executable_idx
].description
,
5569 "Extra shader stage that loads the GS output ringbuffer into the rasterizer");
5575 VkResult result
= *pExecutableCount
< total_count
? VK_INCOMPLETE
: VK_SUCCESS
;
5576 *pExecutableCount
= count
;
5580 VkResult
radv_GetPipelineExecutableStatisticsKHR(
5582 const VkPipelineExecutableInfoKHR
* pExecutableInfo
,
5583 uint32_t* pStatisticCount
,
5584 VkPipelineExecutableStatisticKHR
* pStatistics
)
5586 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5587 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pExecutableInfo
->pipeline
);
5588 gl_shader_stage stage
;
5589 struct radv_shader_variant
*shader
= radv_get_shader_from_executable_index(pipeline
, pExecutableInfo
->executableIndex
, &stage
);
5591 enum chip_class chip_class
= device
->physical_device
->rad_info
.chip_class
;
5592 unsigned lds_increment
= chip_class
>= GFX7
? 512 : 256;
5593 unsigned max_waves
= radv_get_max_waves(device
, shader
, stage
);
5595 VkPipelineExecutableStatisticKHR
*s
= pStatistics
;
5596 VkPipelineExecutableStatisticKHR
*end
= s
+ (pStatistics
? *pStatisticCount
: 0);
5597 VkResult result
= VK_SUCCESS
;
5600 desc_copy(s
->name
, "SGPRs");
5601 desc_copy(s
->description
, "Number of SGPR registers allocated per subgroup");
5602 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5603 s
->value
.u64
= shader
->config
.num_sgprs
;
5608 desc_copy(s
->name
, "VGPRs");
5609 desc_copy(s
->description
, "Number of VGPR registers allocated per subgroup");
5610 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5611 s
->value
.u64
= shader
->config
.num_vgprs
;
5616 desc_copy(s
->name
, "Spilled SGPRs");
5617 desc_copy(s
->description
, "Number of SGPR registers spilled per subgroup");
5618 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5619 s
->value
.u64
= shader
->config
.spilled_sgprs
;
5624 desc_copy(s
->name
, "Spilled VGPRs");
5625 desc_copy(s
->description
, "Number of VGPR registers spilled per subgroup");
5626 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5627 s
->value
.u64
= shader
->config
.spilled_vgprs
;
5632 desc_copy(s
->name
, "PrivMem VGPRs");
5633 desc_copy(s
->description
, "Number of VGPRs stored in private memory per subgroup");
5634 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5635 s
->value
.u64
= shader
->info
.private_mem_vgprs
;
5640 desc_copy(s
->name
, "Code size");
5641 desc_copy(s
->description
, "Code size in bytes");
5642 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5643 s
->value
.u64
= shader
->exec_size
;
5648 desc_copy(s
->name
, "LDS size");
5649 desc_copy(s
->description
, "LDS size in bytes per workgroup");
5650 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5651 s
->value
.u64
= shader
->config
.lds_size
* lds_increment
;
5656 desc_copy(s
->name
, "Scratch size");
5657 desc_copy(s
->description
, "Private memory in bytes per subgroup");
5658 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5659 s
->value
.u64
= shader
->config
.scratch_bytes_per_wave
;
5664 desc_copy(s
->name
, "Subgroups per SIMD");
5665 desc_copy(s
->description
, "The maximum number of subgroups in flight on a SIMD unit");
5666 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5667 s
->value
.u64
= max_waves
;
5671 if (shader
->statistics
) {
5672 for (unsigned i
= 0; i
< shader
->statistics
->count
; i
++) {
5673 struct radv_compiler_statistic_info
*info
= &shader
->statistics
->infos
[i
];
5674 uint32_t value
= shader
->statistics
->values
[i
];
5676 desc_copy(s
->name
, info
->name
);
5677 desc_copy(s
->description
, info
->desc
);
5678 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5679 s
->value
.u64
= value
;
5686 *pStatisticCount
= s
- pStatistics
;
5688 *pStatisticCount
= end
- pStatistics
;
5689 result
= VK_INCOMPLETE
;
5691 *pStatisticCount
= s
- pStatistics
;
5697 static VkResult
radv_copy_representation(void *data
, size_t *data_size
, const char *src
)
5699 size_t total_size
= strlen(src
) + 1;
5702 *data_size
= total_size
;
5706 size_t size
= MIN2(total_size
, *data_size
);
5708 memcpy(data
, src
, size
);
5710 *((char*)data
+ size
- 1) = 0;
5711 return size
< total_size
? VK_INCOMPLETE
: VK_SUCCESS
;
5714 VkResult
radv_GetPipelineExecutableInternalRepresentationsKHR(
5716 const VkPipelineExecutableInfoKHR
* pExecutableInfo
,
5717 uint32_t* pInternalRepresentationCount
,
5718 VkPipelineExecutableInternalRepresentationKHR
* pInternalRepresentations
)
5720 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pExecutableInfo
->pipeline
);
5721 gl_shader_stage stage
;
5722 struct radv_shader_variant
*shader
= radv_get_shader_from_executable_index(pipeline
, pExecutableInfo
->executableIndex
, &stage
);
5724 VkPipelineExecutableInternalRepresentationKHR
*p
= pInternalRepresentations
;
5725 VkPipelineExecutableInternalRepresentationKHR
*end
= p
+ (pInternalRepresentations
? *pInternalRepresentationCount
: 0);
5726 VkResult result
= VK_SUCCESS
;
5730 desc_copy(p
->name
, "NIR Shader(s)");
5731 desc_copy(p
->description
, "The optimized NIR shader(s)");
5732 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->nir_string
) != VK_SUCCESS
)
5733 result
= VK_INCOMPLETE
;
5740 if (pipeline
->device
->physical_device
->use_llvm
) {
5741 desc_copy(p
->name
, "LLVM IR");
5742 desc_copy(p
->description
, "The LLVM IR after some optimizations");
5744 desc_copy(p
->name
, "ACO IR");
5745 desc_copy(p
->description
, "The ACO IR after some optimizations");
5747 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->ir_string
) != VK_SUCCESS
)
5748 result
= VK_INCOMPLETE
;
5755 desc_copy(p
->name
, "Assembly");
5756 desc_copy(p
->description
, "Final Assembly");
5757 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->disasm_string
) != VK_SUCCESS
)
5758 result
= VK_INCOMPLETE
;
5762 if (!pInternalRepresentations
)
5763 *pInternalRepresentationCount
= p
- pInternalRepresentations
;
5765 result
= VK_INCOMPLETE
;
5766 *pInternalRepresentationCount
= end
- pInternalRepresentations
;
5768 *pInternalRepresentationCount
= p
- pInternalRepresentations
;