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radv: remove unnecessary radv_tessellation_state::num_patches
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/disk_cache.h"
29 #include "util/mesa-sha1.h"
30 #include "util/u_atomic.h"
31 #include "radv_debug.h"
32 #include "radv_private.h"
33 #include "radv_cs.h"
34 #include "radv_shader.h"
35 #include "nir/nir.h"
36 #include "nir/nir_builder.h"
37 #include "nir/nir_xfb_info.h"
38 #include "spirv/nir_spirv.h"
39 #include "vk_util.h"
40
41 #include "sid.h"
42 #include "ac_binary.h"
43 #include "ac_llvm_util.h"
44 #include "ac_nir_to_llvm.h"
45 #include "vk_format.h"
46 #include "util/debug.h"
47 #include "ac_exp_param.h"
48 #include "ac_shader_util.h"
49
50 struct radv_blend_state {
51 uint32_t blend_enable_4bit;
52 uint32_t need_src_alpha;
53
54 uint32_t cb_color_control;
55 uint32_t cb_target_mask;
56 uint32_t cb_target_enabled_4bit;
57 uint32_t sx_mrt_blend_opt[8];
58 uint32_t cb_blend_control[8];
59
60 uint32_t spi_shader_col_format;
61 uint32_t col_format_is_int8;
62 uint32_t col_format_is_int10;
63 uint32_t cb_shader_mask;
64 uint32_t db_alpha_to_mask;
65
66 uint32_t commutative_4bit;
67
68 bool single_cb_enable;
69 bool mrt0_is_dual_src;
70 };
71
72 struct radv_dsa_order_invariance {
73 /* Whether the final result in Z/S buffers is guaranteed to be
74 * invariant under changes to the order in which fragments arrive.
75 */
76 bool zs;
77
78 /* Whether the set of fragments that pass the combined Z/S test is
79 * guaranteed to be invariant under changes to the order in which
80 * fragments arrive.
81 */
82 bool pass_set;
83 };
84
85 struct radv_tessellation_state {
86 uint32_t ls_hs_config;
87 unsigned lds_size;
88 uint32_t tf_param;
89 };
90
91 static const VkPipelineMultisampleStateCreateInfo *
92 radv_pipeline_get_multisample_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
93 {
94 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
95 return pCreateInfo->pMultisampleState;
96 return NULL;
97 }
98
99 static const VkPipelineTessellationStateCreateInfo *
100 radv_pipeline_get_tessellation_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
101 {
102 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
103 if (pCreateInfo->pStages[i].stage == VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT ||
104 pCreateInfo->pStages[i].stage == VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) {
105 return pCreateInfo->pTessellationState;
106 }
107 }
108 return NULL;
109 }
110
111 static const VkPipelineDepthStencilStateCreateInfo *
112 radv_pipeline_get_depth_stencil_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
113 {
114 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
115 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
116
117 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
118 subpass->depth_stencil_attachment)
119 return pCreateInfo->pDepthStencilState;
120 return NULL;
121 }
122
123 static const VkPipelineColorBlendStateCreateInfo *
124 radv_pipeline_get_color_blend_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
125 {
126 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
127 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
128
129 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
130 subpass->has_color_att)
131 return pCreateInfo->pColorBlendState;
132 return NULL;
133 }
134
135 bool radv_pipeline_has_ngg(const struct radv_pipeline *pipeline)
136 {
137 struct radv_shader_variant *variant = NULL;
138 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
139 variant = pipeline->shaders[MESA_SHADER_GEOMETRY];
140 else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
141 variant = pipeline->shaders[MESA_SHADER_TESS_EVAL];
142 else if (pipeline->shaders[MESA_SHADER_VERTEX])
143 variant = pipeline->shaders[MESA_SHADER_VERTEX];
144 else
145 return false;
146 return variant->info.is_ngg;
147 }
148
149 bool radv_pipeline_has_ngg_passthrough(const struct radv_pipeline *pipeline)
150 {
151 assert(radv_pipeline_has_ngg(pipeline));
152
153 struct radv_shader_variant *variant = NULL;
154 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
155 variant = pipeline->shaders[MESA_SHADER_GEOMETRY];
156 else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
157 variant = pipeline->shaders[MESA_SHADER_TESS_EVAL];
158 else if (pipeline->shaders[MESA_SHADER_VERTEX])
159 variant = pipeline->shaders[MESA_SHADER_VERTEX];
160 else
161 return false;
162 return variant->info.is_ngg_passthrough;
163 }
164
165 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline *pipeline)
166 {
167 if (!radv_pipeline_has_gs(pipeline))
168 return false;
169
170 /* The GS copy shader is required if the pipeline has GS on GFX6-GFX9.
171 * On GFX10, it might be required in rare cases if it's not possible to
172 * enable NGG.
173 */
174 if (radv_pipeline_has_ngg(pipeline))
175 return false;
176
177 assert(pipeline->gs_copy_shader);
178 return true;
179 }
180
181 static void
182 radv_pipeline_destroy(struct radv_device *device,
183 struct radv_pipeline *pipeline,
184 const VkAllocationCallbacks* allocator)
185 {
186 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
187 if (pipeline->shaders[i])
188 radv_shader_variant_destroy(device, pipeline->shaders[i]);
189
190 if (pipeline->gs_copy_shader)
191 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
192
193 if(pipeline->cs.buf)
194 free(pipeline->cs.buf);
195
196 vk_object_base_finish(&pipeline->base);
197 vk_free2(&device->vk.alloc, allocator, pipeline);
198 }
199
200 void radv_DestroyPipeline(
201 VkDevice _device,
202 VkPipeline _pipeline,
203 const VkAllocationCallbacks* pAllocator)
204 {
205 RADV_FROM_HANDLE(radv_device, device, _device);
206 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
207
208 if (!_pipeline)
209 return;
210
211 radv_pipeline_destroy(device, pipeline, pAllocator);
212 }
213
214 static uint32_t get_hash_flags(struct radv_device *device)
215 {
216 uint32_t hash_flags = 0;
217
218 if (device->instance->debug_flags & RADV_DEBUG_NO_NGG)
219 hash_flags |= RADV_HASH_SHADER_NO_NGG;
220 if (device->physical_device->cs_wave_size == 32)
221 hash_flags |= RADV_HASH_SHADER_CS_WAVE32;
222 if (device->physical_device->ps_wave_size == 32)
223 hash_flags |= RADV_HASH_SHADER_PS_WAVE32;
224 if (device->physical_device->ge_wave_size == 32)
225 hash_flags |= RADV_HASH_SHADER_GE_WAVE32;
226 if (device->physical_device->use_llvm)
227 hash_flags |= RADV_HASH_SHADER_LLVM;
228 return hash_flags;
229 }
230
231 static VkResult
232 radv_pipeline_scratch_init(struct radv_device *device,
233 struct radv_pipeline *pipeline)
234 {
235 unsigned scratch_bytes_per_wave = 0;
236 unsigned max_waves = 0;
237 unsigned min_waves = 1;
238
239 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
240 if (pipeline->shaders[i] &&
241 pipeline->shaders[i]->config.scratch_bytes_per_wave) {
242 unsigned max_stage_waves = device->scratch_waves;
243
244 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
245 pipeline->shaders[i]->config.scratch_bytes_per_wave);
246
247 max_stage_waves = MIN2(max_stage_waves,
248 4 * device->physical_device->rad_info.num_good_compute_units *
249 (256 / pipeline->shaders[i]->config.num_vgprs));
250 max_waves = MAX2(max_waves, max_stage_waves);
251 }
252 }
253
254 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
255 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
256 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
257 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
258 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
259 }
260
261 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
262 pipeline->max_waves = max_waves;
263 return VK_SUCCESS;
264 }
265
266 static uint32_t si_translate_blend_logic_op(VkLogicOp op)
267 {
268 switch (op) {
269 case VK_LOGIC_OP_CLEAR:
270 return V_028808_ROP3_CLEAR;
271 case VK_LOGIC_OP_AND:
272 return V_028808_ROP3_AND;
273 case VK_LOGIC_OP_AND_REVERSE:
274 return V_028808_ROP3_AND_REVERSE;
275 case VK_LOGIC_OP_COPY:
276 return V_028808_ROP3_COPY;
277 case VK_LOGIC_OP_AND_INVERTED:
278 return V_028808_ROP3_AND_INVERTED;
279 case VK_LOGIC_OP_NO_OP:
280 return V_028808_ROP3_NO_OP;
281 case VK_LOGIC_OP_XOR:
282 return V_028808_ROP3_XOR;
283 case VK_LOGIC_OP_OR:
284 return V_028808_ROP3_OR;
285 case VK_LOGIC_OP_NOR:
286 return V_028808_ROP3_NOR;
287 case VK_LOGIC_OP_EQUIVALENT:
288 return V_028808_ROP3_EQUIVALENT;
289 case VK_LOGIC_OP_INVERT:
290 return V_028808_ROP3_INVERT;
291 case VK_LOGIC_OP_OR_REVERSE:
292 return V_028808_ROP3_OR_REVERSE;
293 case VK_LOGIC_OP_COPY_INVERTED:
294 return V_028808_ROP3_COPY_INVERTED;
295 case VK_LOGIC_OP_OR_INVERTED:
296 return V_028808_ROP3_OR_INVERTED;
297 case VK_LOGIC_OP_NAND:
298 return V_028808_ROP3_NAND;
299 case VK_LOGIC_OP_SET:
300 return V_028808_ROP3_SET;
301 default:
302 unreachable("Unhandled logic op");
303 }
304 }
305
306
307 static uint32_t si_translate_blend_function(VkBlendOp op)
308 {
309 switch (op) {
310 case VK_BLEND_OP_ADD:
311 return V_028780_COMB_DST_PLUS_SRC;
312 case VK_BLEND_OP_SUBTRACT:
313 return V_028780_COMB_SRC_MINUS_DST;
314 case VK_BLEND_OP_REVERSE_SUBTRACT:
315 return V_028780_COMB_DST_MINUS_SRC;
316 case VK_BLEND_OP_MIN:
317 return V_028780_COMB_MIN_DST_SRC;
318 case VK_BLEND_OP_MAX:
319 return V_028780_COMB_MAX_DST_SRC;
320 default:
321 return 0;
322 }
323 }
324
325 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
326 {
327 switch (factor) {
328 case VK_BLEND_FACTOR_ZERO:
329 return V_028780_BLEND_ZERO;
330 case VK_BLEND_FACTOR_ONE:
331 return V_028780_BLEND_ONE;
332 case VK_BLEND_FACTOR_SRC_COLOR:
333 return V_028780_BLEND_SRC_COLOR;
334 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
335 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
336 case VK_BLEND_FACTOR_DST_COLOR:
337 return V_028780_BLEND_DST_COLOR;
338 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
339 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
340 case VK_BLEND_FACTOR_SRC_ALPHA:
341 return V_028780_BLEND_SRC_ALPHA;
342 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
343 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
344 case VK_BLEND_FACTOR_DST_ALPHA:
345 return V_028780_BLEND_DST_ALPHA;
346 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
347 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
348 case VK_BLEND_FACTOR_CONSTANT_COLOR:
349 return V_028780_BLEND_CONSTANT_COLOR;
350 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
351 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
352 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
353 return V_028780_BLEND_CONSTANT_ALPHA;
354 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
355 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
356 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
357 return V_028780_BLEND_SRC_ALPHA_SATURATE;
358 case VK_BLEND_FACTOR_SRC1_COLOR:
359 return V_028780_BLEND_SRC1_COLOR;
360 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
361 return V_028780_BLEND_INV_SRC1_COLOR;
362 case VK_BLEND_FACTOR_SRC1_ALPHA:
363 return V_028780_BLEND_SRC1_ALPHA;
364 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
365 return V_028780_BLEND_INV_SRC1_ALPHA;
366 default:
367 return 0;
368 }
369 }
370
371 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
372 {
373 switch (op) {
374 case VK_BLEND_OP_ADD:
375 return V_028760_OPT_COMB_ADD;
376 case VK_BLEND_OP_SUBTRACT:
377 return V_028760_OPT_COMB_SUBTRACT;
378 case VK_BLEND_OP_REVERSE_SUBTRACT:
379 return V_028760_OPT_COMB_REVSUBTRACT;
380 case VK_BLEND_OP_MIN:
381 return V_028760_OPT_COMB_MIN;
382 case VK_BLEND_OP_MAX:
383 return V_028760_OPT_COMB_MAX;
384 default:
385 return V_028760_OPT_COMB_BLEND_DISABLED;
386 }
387 }
388
389 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
390 {
391 switch (factor) {
392 case VK_BLEND_FACTOR_ZERO:
393 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
394 case VK_BLEND_FACTOR_ONE:
395 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
396 case VK_BLEND_FACTOR_SRC_COLOR:
397 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
398 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
399 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
400 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
401 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
402 case VK_BLEND_FACTOR_SRC_ALPHA:
403 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
404 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
405 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
406 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
407 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
408 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
409 default:
410 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
411 }
412 }
413
414 /**
415 * Get rid of DST in the blend factors by commuting the operands:
416 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
417 */
418 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
419 unsigned *dst_factor, unsigned expected_dst,
420 unsigned replacement_src)
421 {
422 if (*src_factor == expected_dst &&
423 *dst_factor == VK_BLEND_FACTOR_ZERO) {
424 *src_factor = VK_BLEND_FACTOR_ZERO;
425 *dst_factor = replacement_src;
426
427 /* Commuting the operands requires reversing subtractions. */
428 if (*func == VK_BLEND_OP_SUBTRACT)
429 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
430 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
431 *func = VK_BLEND_OP_SUBTRACT;
432 }
433 }
434
435 static bool si_blend_factor_uses_dst(unsigned factor)
436 {
437 return factor == VK_BLEND_FACTOR_DST_COLOR ||
438 factor == VK_BLEND_FACTOR_DST_ALPHA ||
439 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
440 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
441 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
442 }
443
444 static bool is_dual_src(VkBlendFactor factor)
445 {
446 switch (factor) {
447 case VK_BLEND_FACTOR_SRC1_COLOR:
448 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
449 case VK_BLEND_FACTOR_SRC1_ALPHA:
450 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
451 return true;
452 default:
453 return false;
454 }
455 }
456
457 static unsigned radv_choose_spi_color_format(VkFormat vk_format,
458 bool blend_enable,
459 bool blend_need_alpha)
460 {
461 const struct vk_format_description *desc = vk_format_description(vk_format);
462 struct ac_spi_color_formats formats = {};
463 unsigned format, ntype, swap;
464
465 format = radv_translate_colorformat(vk_format);
466 ntype = radv_translate_color_numformat(vk_format, desc,
467 vk_format_get_first_non_void_channel(vk_format));
468 swap = radv_translate_colorswap(vk_format, false);
469
470 ac_choose_spi_color_formats(format, swap, ntype, false, &formats);
471
472 if (blend_enable && blend_need_alpha)
473 return formats.blend_alpha;
474 else if(blend_need_alpha)
475 return formats.alpha;
476 else if(blend_enable)
477 return formats.blend;
478 else
479 return formats.normal;
480 }
481
482 static bool
483 format_is_int8(VkFormat format)
484 {
485 const struct vk_format_description *desc = vk_format_description(format);
486 int channel = vk_format_get_first_non_void_channel(format);
487
488 return channel >= 0 && desc->channel[channel].pure_integer &&
489 desc->channel[channel].size == 8;
490 }
491
492 static bool
493 format_is_int10(VkFormat format)
494 {
495 const struct vk_format_description *desc = vk_format_description(format);
496
497 if (desc->nr_channels != 4)
498 return false;
499 for (unsigned i = 0; i < 4; i++) {
500 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
501 return true;
502 }
503 return false;
504 }
505
506 static void
507 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
508 const VkGraphicsPipelineCreateInfo *pCreateInfo,
509 struct radv_blend_state *blend)
510 {
511 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
512 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
513 unsigned col_format = 0, is_int8 = 0, is_int10 = 0;
514 unsigned num_targets;
515
516 for (unsigned i = 0; i < (blend->single_cb_enable ? 1 : subpass->color_count); ++i) {
517 unsigned cf;
518
519 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED ||
520 !(blend->cb_target_mask & (0xfu << (i * 4)))) {
521 cf = V_028714_SPI_SHADER_ZERO;
522 } else {
523 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
524 bool blend_enable =
525 blend->blend_enable_4bit & (0xfu << (i * 4));
526
527 cf = radv_choose_spi_color_format(attachment->format,
528 blend_enable,
529 blend->need_src_alpha & (1 << i));
530
531 if (format_is_int8(attachment->format))
532 is_int8 |= 1 << i;
533 if (format_is_int10(attachment->format))
534 is_int10 |= 1 << i;
535 }
536
537 col_format |= cf << (4 * i);
538 }
539
540 if (!(col_format & 0xf) && blend->need_src_alpha & (1 << 0)) {
541 /* When a subpass doesn't have any color attachments, write the
542 * alpha channel of MRT0 when alpha coverage is enabled because
543 * the depth attachment needs it.
544 */
545 col_format |= V_028714_SPI_SHADER_32_AR;
546 }
547
548 /* If the i-th target format is set, all previous target formats must
549 * be non-zero to avoid hangs.
550 */
551 num_targets = (util_last_bit(col_format) + 3) / 4;
552 for (unsigned i = 0; i < num_targets; i++) {
553 if (!(col_format & (0xf << (i * 4)))) {
554 col_format |= V_028714_SPI_SHADER_32_R << (i * 4);
555 }
556 }
557
558 /* The output for dual source blending should have the same format as
559 * the first output.
560 */
561 if (blend->mrt0_is_dual_src)
562 col_format |= (col_format & 0xf) << 4;
563
564 blend->spi_shader_col_format = col_format;
565 blend->col_format_is_int8 = is_int8;
566 blend->col_format_is_int10 = is_int10;
567 }
568
569 /*
570 * Ordered so that for each i,
571 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
572 */
573 const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS] = {
574 VK_FORMAT_R32_SFLOAT,
575 VK_FORMAT_R32G32_SFLOAT,
576 VK_FORMAT_R8G8B8A8_UNORM,
577 VK_FORMAT_R16G16B16A16_UNORM,
578 VK_FORMAT_R16G16B16A16_SNORM,
579 VK_FORMAT_R16G16B16A16_UINT,
580 VK_FORMAT_R16G16B16A16_SINT,
581 VK_FORMAT_R32G32B32A32_SFLOAT,
582 VK_FORMAT_R8G8B8A8_UINT,
583 VK_FORMAT_R8G8B8A8_SINT,
584 VK_FORMAT_A2R10G10B10_UINT_PACK32,
585 VK_FORMAT_A2R10G10B10_SINT_PACK32,
586 };
587
588 unsigned radv_format_meta_fs_key(VkFormat format)
589 {
590 unsigned col_format = radv_choose_spi_color_format(format, false, false);
591
592 assert(col_format != V_028714_SPI_SHADER_32_AR);
593 if (col_format >= V_028714_SPI_SHADER_32_AR)
594 --col_format; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
595
596 --col_format; /* Skip V_028714_SPI_SHADER_ZERO */
597 bool is_int8 = format_is_int8(format);
598 bool is_int10 = format_is_int10(format);
599
600 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
601 }
602
603 static void
604 radv_blend_check_commutativity(struct radv_blend_state *blend,
605 VkBlendOp op, VkBlendFactor src,
606 VkBlendFactor dst, unsigned chanmask)
607 {
608 /* Src factor is allowed when it does not depend on Dst. */
609 static const uint32_t src_allowed =
610 (1u << VK_BLEND_FACTOR_ONE) |
611 (1u << VK_BLEND_FACTOR_SRC_COLOR) |
612 (1u << VK_BLEND_FACTOR_SRC_ALPHA) |
613 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE) |
614 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR) |
615 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA) |
616 (1u << VK_BLEND_FACTOR_SRC1_COLOR) |
617 (1u << VK_BLEND_FACTOR_SRC1_ALPHA) |
618 (1u << VK_BLEND_FACTOR_ZERO) |
619 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR) |
620 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA) |
621 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR) |
622 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA) |
623 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR) |
624 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA);
625
626 if (dst == VK_BLEND_FACTOR_ONE &&
627 (src_allowed & (1u << src))) {
628 /* Addition is commutative, but floating point addition isn't
629 * associative: subtle changes can be introduced via different
630 * rounding. Be conservative, only enable for min and max.
631 */
632 if (op == VK_BLEND_OP_MAX || op == VK_BLEND_OP_MIN)
633 blend->commutative_4bit |= chanmask;
634 }
635 }
636
637 static struct radv_blend_state
638 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
639 const VkGraphicsPipelineCreateInfo *pCreateInfo,
640 const struct radv_graphics_pipeline_create_info *extra)
641 {
642 const VkPipelineColorBlendStateCreateInfo *vkblend = radv_pipeline_get_color_blend_state(pCreateInfo);
643 const VkPipelineMultisampleStateCreateInfo *vkms = radv_pipeline_get_multisample_state(pCreateInfo);
644 struct radv_blend_state blend = {0};
645 unsigned mode = V_028808_CB_NORMAL;
646 int i;
647
648 if (extra && extra->custom_blend_mode) {
649 blend.single_cb_enable = true;
650 mode = extra->custom_blend_mode;
651 }
652
653 blend.cb_color_control = 0;
654 if (vkblend) {
655 if (vkblend->logicOpEnable)
656 blend.cb_color_control |= S_028808_ROP3(si_translate_blend_logic_op(vkblend->logicOp));
657 else
658 blend.cb_color_control |= S_028808_ROP3(V_028808_ROP3_COPY);
659 }
660
661 blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
662 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
663 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
664 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
665 S_028B70_OFFSET_ROUND(1);
666
667 if (vkms && vkms->alphaToCoverageEnable) {
668 blend.db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
669 blend.need_src_alpha |= 0x1;
670 }
671
672 blend.cb_target_mask = 0;
673 if (vkblend) {
674 for (i = 0; i < vkblend->attachmentCount; i++) {
675 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
676 unsigned blend_cntl = 0;
677 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
678 VkBlendOp eqRGB = att->colorBlendOp;
679 VkBlendFactor srcRGB = att->srcColorBlendFactor;
680 VkBlendFactor dstRGB = att->dstColorBlendFactor;
681 VkBlendOp eqA = att->alphaBlendOp;
682 VkBlendFactor srcA = att->srcAlphaBlendFactor;
683 VkBlendFactor dstA = att->dstAlphaBlendFactor;
684
685 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
686
687 if (!att->colorWriteMask)
688 continue;
689
690 blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
691 blend.cb_target_enabled_4bit |= 0xf << (4 * i);
692 if (!att->blendEnable) {
693 blend.cb_blend_control[i] = blend_cntl;
694 continue;
695 }
696
697 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
698 if (i == 0)
699 blend.mrt0_is_dual_src = true;
700
701 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
702 srcRGB = VK_BLEND_FACTOR_ONE;
703 dstRGB = VK_BLEND_FACTOR_ONE;
704 }
705 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
706 srcA = VK_BLEND_FACTOR_ONE;
707 dstA = VK_BLEND_FACTOR_ONE;
708 }
709
710 radv_blend_check_commutativity(&blend, eqRGB, srcRGB, dstRGB,
711 0x7 << (4 * i));
712 radv_blend_check_commutativity(&blend, eqA, srcA, dstA,
713 0x8 << (4 * i));
714
715 /* Blending optimizations for RB+.
716 * These transformations don't change the behavior.
717 *
718 * First, get rid of DST in the blend factors:
719 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
720 */
721 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
722 VK_BLEND_FACTOR_DST_COLOR,
723 VK_BLEND_FACTOR_SRC_COLOR);
724
725 si_blend_remove_dst(&eqA, &srcA, &dstA,
726 VK_BLEND_FACTOR_DST_COLOR,
727 VK_BLEND_FACTOR_SRC_COLOR);
728
729 si_blend_remove_dst(&eqA, &srcA, &dstA,
730 VK_BLEND_FACTOR_DST_ALPHA,
731 VK_BLEND_FACTOR_SRC_ALPHA);
732
733 /* Look up the ideal settings from tables. */
734 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
735 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
736 srcA_opt = si_translate_blend_opt_factor(srcA, true);
737 dstA_opt = si_translate_blend_opt_factor(dstA, true);
738
739 /* Handle interdependencies. */
740 if (si_blend_factor_uses_dst(srcRGB))
741 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
742 if (si_blend_factor_uses_dst(srcA))
743 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
744
745 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
746 (dstRGB == VK_BLEND_FACTOR_ZERO ||
747 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
748 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
749 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
750
751 /* Set the final value. */
752 blend.sx_mrt_blend_opt[i] =
753 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
754 S_028760_COLOR_DST_OPT(dstRGB_opt) |
755 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
756 S_028760_ALPHA_SRC_OPT(srcA_opt) |
757 S_028760_ALPHA_DST_OPT(dstA_opt) |
758 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
759 blend_cntl |= S_028780_ENABLE(1);
760
761 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
762 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
763 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
764 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
765 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
766 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
767 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
768 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
769 }
770 blend.cb_blend_control[i] = blend_cntl;
771
772 blend.blend_enable_4bit |= 0xfu << (i * 4);
773
774 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
775 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
776 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
777 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
778 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
779 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
780 blend.need_src_alpha |= 1 << i;
781 }
782 for (i = vkblend->attachmentCount; i < 8; i++) {
783 blend.cb_blend_control[i] = 0;
784 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
785 }
786 }
787
788 if (pipeline->device->physical_device->rad_info.has_rbplus) {
789 /* Disable RB+ blend optimizations for dual source blending. */
790 if (blend.mrt0_is_dual_src) {
791 for (i = 0; i < 8; i++) {
792 blend.sx_mrt_blend_opt[i] =
793 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
794 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
795 }
796 }
797
798 /* RB+ doesn't work with dual source blending, logic op and
799 * RESOLVE.
800 */
801 if (blend.mrt0_is_dual_src ||
802 (vkblend && vkblend->logicOpEnable) ||
803 mode == V_028808_CB_RESOLVE)
804 blend.cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
805 }
806
807 if (blend.cb_target_mask)
808 blend.cb_color_control |= S_028808_MODE(mode);
809 else
810 blend.cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
811
812 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo, &blend);
813 return blend;
814 }
815
816 static uint32_t si_translate_fill(VkPolygonMode func)
817 {
818 switch(func) {
819 case VK_POLYGON_MODE_FILL:
820 return V_028814_X_DRAW_TRIANGLES;
821 case VK_POLYGON_MODE_LINE:
822 return V_028814_X_DRAW_LINES;
823 case VK_POLYGON_MODE_POINT:
824 return V_028814_X_DRAW_POINTS;
825 default:
826 assert(0);
827 return V_028814_X_DRAW_POINTS;
828 }
829 }
830
831 static uint8_t radv_pipeline_get_ps_iter_samples(const VkGraphicsPipelineCreateInfo *pCreateInfo)
832 {
833 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
834 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
835 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
836 uint32_t ps_iter_samples = 1;
837 uint32_t num_samples;
838
839 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
840 *
841 * "If the VK_AMD_mixed_attachment_samples extension is enabled and the
842 * subpass uses color attachments, totalSamples is the number of
843 * samples of the color attachments. Otherwise, totalSamples is the
844 * value of VkPipelineMultisampleStateCreateInfo::rasterizationSamples
845 * specified at pipeline creation time."
846 */
847 if (subpass->has_color_att) {
848 num_samples = subpass->color_sample_count;
849 } else {
850 num_samples = vkms->rasterizationSamples;
851 }
852
853 if (vkms->sampleShadingEnable) {
854 ps_iter_samples = ceilf(vkms->minSampleShading * num_samples);
855 ps_iter_samples = util_next_power_of_two(ps_iter_samples);
856 }
857 return ps_iter_samples;
858 }
859
860 static bool
861 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
862 {
863 return pCreateInfo->depthTestEnable &&
864 pCreateInfo->depthWriteEnable &&
865 pCreateInfo->depthCompareOp != VK_COMPARE_OP_NEVER;
866 }
867
868 static bool
869 radv_writes_stencil(const VkStencilOpState *state)
870 {
871 return state->writeMask &&
872 (state->failOp != VK_STENCIL_OP_KEEP ||
873 state->passOp != VK_STENCIL_OP_KEEP ||
874 state->depthFailOp != VK_STENCIL_OP_KEEP);
875 }
876
877 static bool
878 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
879 {
880 return pCreateInfo->stencilTestEnable &&
881 (radv_writes_stencil(&pCreateInfo->front) ||
882 radv_writes_stencil(&pCreateInfo->back));
883 }
884
885 static bool
886 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
887 {
888 return radv_is_depth_write_enabled(pCreateInfo) ||
889 radv_is_stencil_write_enabled(pCreateInfo);
890 }
891
892 static bool
893 radv_order_invariant_stencil_op(VkStencilOp op)
894 {
895 /* REPLACE is normally order invariant, except when the stencil
896 * reference value is written by the fragment shader. Tracking this
897 * interaction does not seem worth the effort, so be conservative.
898 */
899 return op != VK_STENCIL_OP_INCREMENT_AND_CLAMP &&
900 op != VK_STENCIL_OP_DECREMENT_AND_CLAMP &&
901 op != VK_STENCIL_OP_REPLACE;
902 }
903
904 static bool
905 radv_order_invariant_stencil_state(const VkStencilOpState *state)
906 {
907 /* Compute whether, assuming Z writes are disabled, this stencil state
908 * is order invariant in the sense that the set of passing fragments as
909 * well as the final stencil buffer result does not depend on the order
910 * of fragments.
911 */
912 return !state->writeMask ||
913 /* The following assumes that Z writes are disabled. */
914 (state->compareOp == VK_COMPARE_OP_ALWAYS &&
915 radv_order_invariant_stencil_op(state->passOp) &&
916 radv_order_invariant_stencil_op(state->depthFailOp)) ||
917 (state->compareOp == VK_COMPARE_OP_NEVER &&
918 radv_order_invariant_stencil_op(state->failOp));
919 }
920
921 static bool
922 radv_pipeline_has_dynamic_ds_states(const VkGraphicsPipelineCreateInfo *pCreateInfo)
923 {
924 VkDynamicState ds_states[] = {
925 VK_DYNAMIC_STATE_DEPTH_TEST_ENABLE_EXT,
926 VK_DYNAMIC_STATE_DEPTH_WRITE_ENABLE_EXT,
927 VK_DYNAMIC_STATE_DEPTH_COMPARE_OP_EXT,
928 VK_DYNAMIC_STATE_STENCIL_TEST_ENABLE_EXT,
929 VK_DYNAMIC_STATE_STENCIL_OP_EXT,
930 };
931
932 if (pCreateInfo->pDynamicState) {
933 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
934 for (uint32_t i = 0; i < count; i++) {
935 for (uint32_t j = 0; j < ARRAY_SIZE(ds_states); j++) {
936 if (pCreateInfo->pDynamicState->pDynamicStates[i] == ds_states[j])
937 return true;
938 }
939 }
940 }
941
942 return false;
943 }
944
945 static bool
946 radv_pipeline_out_of_order_rast(struct radv_pipeline *pipeline,
947 struct radv_blend_state *blend,
948 const VkGraphicsPipelineCreateInfo *pCreateInfo)
949 {
950 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
951 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
952 const VkPipelineDepthStencilStateCreateInfo *vkds = radv_pipeline_get_depth_stencil_state(pCreateInfo);
953 const VkPipelineColorBlendStateCreateInfo *vkblend = radv_pipeline_get_color_blend_state(pCreateInfo);
954 unsigned colormask = blend->cb_target_enabled_4bit;
955
956 if (!pipeline->device->physical_device->out_of_order_rast_allowed)
957 return false;
958
959 /* Be conservative if a logic operation is enabled with color buffers. */
960 if (colormask && vkblend && vkblend->logicOpEnable)
961 return false;
962
963 /* Be conservative if an extended dynamic depth/stencil state is
964 * enabled because the driver can't update out-of-order rasterization
965 * dynamically.
966 */
967 if (radv_pipeline_has_dynamic_ds_states(pCreateInfo))
968 return false;
969
970 /* Default depth/stencil invariance when no attachment is bound. */
971 struct radv_dsa_order_invariance dsa_order_invariant = {
972 .zs = true, .pass_set = true
973 };
974
975 if (vkds) {
976 struct radv_render_pass_attachment *attachment =
977 pass->attachments + subpass->depth_stencil_attachment->attachment;
978 bool has_stencil = vk_format_is_stencil(attachment->format);
979 struct radv_dsa_order_invariance order_invariance[2];
980 struct radv_shader_variant *ps =
981 pipeline->shaders[MESA_SHADER_FRAGMENT];
982
983 /* Compute depth/stencil order invariance in order to know if
984 * it's safe to enable out-of-order.
985 */
986 bool zfunc_is_ordered =
987 vkds->depthCompareOp == VK_COMPARE_OP_NEVER ||
988 vkds->depthCompareOp == VK_COMPARE_OP_LESS ||
989 vkds->depthCompareOp == VK_COMPARE_OP_LESS_OR_EQUAL ||
990 vkds->depthCompareOp == VK_COMPARE_OP_GREATER ||
991 vkds->depthCompareOp == VK_COMPARE_OP_GREATER_OR_EQUAL;
992
993 bool nozwrite_and_order_invariant_stencil =
994 !radv_is_ds_write_enabled(vkds) ||
995 (!radv_is_depth_write_enabled(vkds) &&
996 radv_order_invariant_stencil_state(&vkds->front) &&
997 radv_order_invariant_stencil_state(&vkds->back));
998
999 order_invariance[1].zs =
1000 nozwrite_and_order_invariant_stencil ||
1001 (!radv_is_stencil_write_enabled(vkds) &&
1002 zfunc_is_ordered);
1003 order_invariance[0].zs =
1004 !radv_is_depth_write_enabled(vkds) || zfunc_is_ordered;
1005
1006 order_invariance[1].pass_set =
1007 nozwrite_and_order_invariant_stencil ||
1008 (!radv_is_stencil_write_enabled(vkds) &&
1009 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1010 vkds->depthCompareOp == VK_COMPARE_OP_NEVER));
1011 order_invariance[0].pass_set =
1012 !radv_is_depth_write_enabled(vkds) ||
1013 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1014 vkds->depthCompareOp == VK_COMPARE_OP_NEVER);
1015
1016 dsa_order_invariant = order_invariance[has_stencil];
1017 if (!dsa_order_invariant.zs)
1018 return false;
1019
1020 /* The set of PS invocations is always order invariant,
1021 * except when early Z/S tests are requested.
1022 */
1023 if (ps &&
1024 ps->info.ps.writes_memory &&
1025 ps->info.ps.early_fragment_test &&
1026 !dsa_order_invariant.pass_set)
1027 return false;
1028
1029 /* Determine if out-of-order rasterization should be disabled
1030 * when occlusion queries are used.
1031 */
1032 pipeline->graphics.disable_out_of_order_rast_for_occlusion =
1033 !dsa_order_invariant.pass_set;
1034 }
1035
1036 /* No color buffers are enabled for writing. */
1037 if (!colormask)
1038 return true;
1039
1040 unsigned blendmask = colormask & blend->blend_enable_4bit;
1041
1042 if (blendmask) {
1043 /* Only commutative blending. */
1044 if (blendmask & ~blend->commutative_4bit)
1045 return false;
1046
1047 if (!dsa_order_invariant.pass_set)
1048 return false;
1049 }
1050
1051 if (colormask & ~blendmask)
1052 return false;
1053
1054 return true;
1055 }
1056
1057 static void
1058 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1059 struct radv_blend_state *blend,
1060 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1061 {
1062 const VkPipelineMultisampleStateCreateInfo *vkms = radv_pipeline_get_multisample_state(pCreateInfo);
1063 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1064 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1065 bool out_of_order_rast = false;
1066 int ps_iter_samples = 1;
1067 uint32_t mask = 0xffff;
1068
1069 if (vkms) {
1070 ms->num_samples = vkms->rasterizationSamples;
1071
1072 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
1073 *
1074 * "Sample shading is enabled for a graphics pipeline:
1075 *
1076 * - If the interface of the fragment shader entry point of the
1077 * graphics pipeline includes an input variable decorated
1078 * with SampleId or SamplePosition. In this case
1079 * minSampleShadingFactor takes the value 1.0.
1080 * - Else if the sampleShadingEnable member of the
1081 * VkPipelineMultisampleStateCreateInfo structure specified
1082 * when creating the graphics pipeline is set to VK_TRUE. In
1083 * this case minSampleShadingFactor takes the value of
1084 * VkPipelineMultisampleStateCreateInfo::minSampleShading.
1085 *
1086 * Otherwise, sample shading is considered disabled."
1087 */
1088 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.force_persample) {
1089 ps_iter_samples = ms->num_samples;
1090 } else {
1091 ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo);
1092 }
1093 } else {
1094 ms->num_samples = 1;
1095 }
1096
1097 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
1098 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
1099 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
1100 /* Out-of-order rasterization is explicitly enabled by the
1101 * application.
1102 */
1103 out_of_order_rast = true;
1104 } else {
1105 /* Determine if the driver can enable out-of-order
1106 * rasterization internally.
1107 */
1108 out_of_order_rast =
1109 radv_pipeline_out_of_order_rast(pipeline, blend, pCreateInfo);
1110 }
1111
1112 ms->pa_sc_aa_config = 0;
1113 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1114 S_028804_INCOHERENT_EQAA_READS(1) |
1115 S_028804_INTERPOLATE_COMP_Z(1) |
1116 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1117 ms->pa_sc_mode_cntl_1 =
1118 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1119 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1120 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
1121 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1122 /* always 1: */
1123 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1124 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1125 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1126 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1127 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1128 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1129 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9) |
1130 S_028A48_VPORT_SCISSOR_ENABLE(1);
1131
1132 const VkPipelineRasterizationLineStateCreateInfoEXT *rast_line =
1133 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
1134 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT);
1135 if (rast_line) {
1136 ms->pa_sc_mode_cntl_0 |= S_028A48_LINE_STIPPLE_ENABLE(rast_line->stippledLineEnable);
1137 if (rast_line->lineRasterizationMode == VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT) {
1138 /* From the Vulkan spec 1.1.129:
1139 *
1140 * "When VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT lines
1141 * are being rasterized, sample locations may all be
1142 * treated as being at the pixel center (this may
1143 * affect attribute and depth interpolation)."
1144 */
1145 ms->num_samples = 1;
1146 }
1147 }
1148
1149 if (ms->num_samples > 1) {
1150 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1151 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1152 uint32_t z_samples = subpass->depth_stencil_attachment ? subpass->depth_sample_count : ms->num_samples;
1153 unsigned log_samples = util_logbase2(ms->num_samples);
1154 unsigned log_z_samples = util_logbase2(z_samples);
1155 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
1156 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
1157 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples) |
1158 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1159 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1160 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1161 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1162 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples)) |
1163 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples) | /* CM_R_028BE0_PA_SC_AA_CONFIG */
1164 S_028BE0_COVERED_CENTROID_IS_CENTER_GFX103(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3);
1165 ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1166 if (ps_iter_samples > 1)
1167 pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1168 }
1169
1170 if (vkms && vkms->pSampleMask) {
1171 mask = vkms->pSampleMask[0] & 0xffff;
1172 }
1173
1174 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1175 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1176 }
1177
1178 static bool
1179 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1180 {
1181 switch (topology) {
1182 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1183 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1184 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1185 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1186 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1187 return false;
1188 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1189 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1190 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1191 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1192 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1193 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1194 return true;
1195 default:
1196 unreachable("unhandled primitive type");
1197 }
1198 }
1199
1200 static uint32_t
1201 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1202 {
1203 switch (gl_prim) {
1204 case 0: /* GL_POINTS */
1205 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1206 case 1: /* GL_LINES */
1207 case 3: /* GL_LINE_STRIP */
1208 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1209 case 0x8E7A: /* GL_ISOLINES */
1210 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1211
1212 case 4: /* GL_TRIANGLES */
1213 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1214 case 5: /* GL_TRIANGLE_STRIP */
1215 case 7: /* GL_QUADS */
1216 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1217 default:
1218 assert(0);
1219 return 0;
1220 }
1221 }
1222
1223 static uint32_t
1224 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1225 {
1226 switch (topology) {
1227 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1228 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1229 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1230 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1231 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1232 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1233 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1234 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1235 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1236 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1237 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1238 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1239 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1240 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1241 default:
1242 assert(0);
1243 return 0;
1244 }
1245 }
1246
1247 static unsigned radv_dynamic_state_mask(VkDynamicState state)
1248 {
1249 switch(state) {
1250 case VK_DYNAMIC_STATE_VIEWPORT:
1251 case VK_DYNAMIC_STATE_VIEWPORT_WITH_COUNT_EXT:
1252 return RADV_DYNAMIC_VIEWPORT;
1253 case VK_DYNAMIC_STATE_SCISSOR:
1254 case VK_DYNAMIC_STATE_SCISSOR_WITH_COUNT_EXT:
1255 return RADV_DYNAMIC_SCISSOR;
1256 case VK_DYNAMIC_STATE_LINE_WIDTH:
1257 return RADV_DYNAMIC_LINE_WIDTH;
1258 case VK_DYNAMIC_STATE_DEPTH_BIAS:
1259 return RADV_DYNAMIC_DEPTH_BIAS;
1260 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
1261 return RADV_DYNAMIC_BLEND_CONSTANTS;
1262 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
1263 return RADV_DYNAMIC_DEPTH_BOUNDS;
1264 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
1265 return RADV_DYNAMIC_STENCIL_COMPARE_MASK;
1266 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
1267 return RADV_DYNAMIC_STENCIL_WRITE_MASK;
1268 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
1269 return RADV_DYNAMIC_STENCIL_REFERENCE;
1270 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT:
1271 return RADV_DYNAMIC_DISCARD_RECTANGLE;
1272 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT:
1273 return RADV_DYNAMIC_SAMPLE_LOCATIONS;
1274 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT:
1275 return RADV_DYNAMIC_LINE_STIPPLE;
1276 case VK_DYNAMIC_STATE_CULL_MODE_EXT:
1277 return RADV_DYNAMIC_CULL_MODE;
1278 case VK_DYNAMIC_STATE_FRONT_FACE_EXT:
1279 return RADV_DYNAMIC_FRONT_FACE;
1280 case VK_DYNAMIC_STATE_PRIMITIVE_TOPOLOGY_EXT:
1281 return RADV_DYNAMIC_PRIMITIVE_TOPOLOGY;
1282 case VK_DYNAMIC_STATE_DEPTH_TEST_ENABLE_EXT:
1283 return RADV_DYNAMIC_DEPTH_TEST_ENABLE;
1284 case VK_DYNAMIC_STATE_DEPTH_WRITE_ENABLE_EXT:
1285 return RADV_DYNAMIC_DEPTH_WRITE_ENABLE;
1286 case VK_DYNAMIC_STATE_DEPTH_COMPARE_OP_EXT:
1287 return RADV_DYNAMIC_DEPTH_COMPARE_OP;
1288 case VK_DYNAMIC_STATE_DEPTH_BOUNDS_TEST_ENABLE_EXT:
1289 return RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE;
1290 case VK_DYNAMIC_STATE_STENCIL_TEST_ENABLE_EXT:
1291 return RADV_DYNAMIC_STENCIL_TEST_ENABLE;
1292 case VK_DYNAMIC_STATE_STENCIL_OP_EXT:
1293 return RADV_DYNAMIC_STENCIL_OP;
1294 case VK_DYNAMIC_STATE_VERTEX_INPUT_BINDING_STRIDE_EXT:
1295 return RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE;
1296 default:
1297 unreachable("Unhandled dynamic state");
1298 }
1299 }
1300
1301 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
1302 {
1303 uint32_t states = RADV_DYNAMIC_ALL;
1304
1305 /* If rasterization is disabled we do not care about any of the
1306 * dynamic states, since they are all rasterization related only,
1307 * except primitive topology and vertex binding stride.
1308 */
1309 if (pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
1310 return RADV_DYNAMIC_PRIMITIVE_TOPOLOGY |
1311 RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE;
1312
1313 if (!pCreateInfo->pRasterizationState->depthBiasEnable)
1314 states &= ~RADV_DYNAMIC_DEPTH_BIAS;
1315
1316 if (!pCreateInfo->pDepthStencilState ||
1317 !pCreateInfo->pDepthStencilState->depthBoundsTestEnable)
1318 states &= ~RADV_DYNAMIC_DEPTH_BOUNDS;
1319
1320 if (!pCreateInfo->pDepthStencilState ||
1321 !pCreateInfo->pDepthStencilState->stencilTestEnable)
1322 states &= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK |
1323 RADV_DYNAMIC_STENCIL_WRITE_MASK |
1324 RADV_DYNAMIC_STENCIL_REFERENCE);
1325
1326 if (!vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT))
1327 states &= ~RADV_DYNAMIC_DISCARD_RECTANGLE;
1328
1329 if (!pCreateInfo->pMultisampleState ||
1330 !vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1331 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT))
1332 states &= ~RADV_DYNAMIC_SAMPLE_LOCATIONS;
1333
1334 if (!pCreateInfo->pRasterizationState ||
1335 !vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
1336 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT))
1337 states &= ~RADV_DYNAMIC_LINE_STIPPLE;
1338
1339 /* TODO: blend constants & line width. */
1340
1341 return states;
1342 }
1343
1344
1345 static void
1346 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1347 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1348 const struct radv_graphics_pipeline_create_info *extra)
1349 {
1350 uint32_t needed_states = radv_pipeline_needed_dynamic_state(pCreateInfo);
1351 uint32_t states = needed_states;
1352 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1353 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1354
1355 pipeline->dynamic_state = default_dynamic_state;
1356 pipeline->graphics.needed_dynamic_state = needed_states;
1357
1358 if (pCreateInfo->pDynamicState) {
1359 /* Remove all of the states that are marked as dynamic */
1360 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1361 for (uint32_t s = 0; s < count; s++)
1362 states &= ~radv_dynamic_state_mask(pCreateInfo->pDynamicState->pDynamicStates[s]);
1363 }
1364
1365 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1366
1367 if (needed_states & RADV_DYNAMIC_VIEWPORT) {
1368 assert(pCreateInfo->pViewportState);
1369
1370 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1371 if (states & RADV_DYNAMIC_VIEWPORT) {
1372 typed_memcpy(dynamic->viewport.viewports,
1373 pCreateInfo->pViewportState->pViewports,
1374 pCreateInfo->pViewportState->viewportCount);
1375 }
1376 }
1377
1378 if (needed_states & RADV_DYNAMIC_SCISSOR) {
1379 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1380 if (states & RADV_DYNAMIC_SCISSOR) {
1381 typed_memcpy(dynamic->scissor.scissors,
1382 pCreateInfo->pViewportState->pScissors,
1383 pCreateInfo->pViewportState->scissorCount);
1384 }
1385 }
1386
1387 if (states & RADV_DYNAMIC_LINE_WIDTH) {
1388 assert(pCreateInfo->pRasterizationState);
1389 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1390 }
1391
1392 if (states & RADV_DYNAMIC_DEPTH_BIAS) {
1393 assert(pCreateInfo->pRasterizationState);
1394 dynamic->depth_bias.bias =
1395 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1396 dynamic->depth_bias.clamp =
1397 pCreateInfo->pRasterizationState->depthBiasClamp;
1398 dynamic->depth_bias.slope =
1399 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1400 }
1401
1402 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1403 *
1404 * pColorBlendState is [...] NULL if the pipeline has rasterization
1405 * disabled or if the subpass of the render pass the pipeline is
1406 * created against does not use any color attachments.
1407 */
1408 if (subpass->has_color_att && states & RADV_DYNAMIC_BLEND_CONSTANTS) {
1409 assert(pCreateInfo->pColorBlendState);
1410 typed_memcpy(dynamic->blend_constants,
1411 pCreateInfo->pColorBlendState->blendConstants, 4);
1412 }
1413
1414 if (states & RADV_DYNAMIC_CULL_MODE) {
1415 dynamic->cull_mode =
1416 pCreateInfo->pRasterizationState->cullMode;
1417 }
1418
1419 if (states & RADV_DYNAMIC_FRONT_FACE) {
1420 dynamic->front_face =
1421 pCreateInfo->pRasterizationState->frontFace;
1422 }
1423
1424 if (states & RADV_DYNAMIC_PRIMITIVE_TOPOLOGY) {
1425 dynamic->primitive_topology =
1426 si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
1427 if (extra && extra->use_rectlist) {
1428 dynamic->primitive_topology = V_008958_DI_PT_RECTLIST;
1429 }
1430 }
1431
1432 /* If there is no depthstencil attachment, then don't read
1433 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1434 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1435 * no need to override the depthstencil defaults in
1436 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1437 *
1438 * Section 9.2 of the Vulkan 1.0.15 spec says:
1439 *
1440 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1441 * disabled or if the subpass of the render pass the pipeline is created
1442 * against does not use a depth/stencil attachment.
1443 */
1444 if (needed_states && subpass->depth_stencil_attachment) {
1445 assert(pCreateInfo->pDepthStencilState);
1446
1447 if (states & RADV_DYNAMIC_DEPTH_BOUNDS) {
1448 dynamic->depth_bounds.min =
1449 pCreateInfo->pDepthStencilState->minDepthBounds;
1450 dynamic->depth_bounds.max =
1451 pCreateInfo->pDepthStencilState->maxDepthBounds;
1452 }
1453
1454 if (states & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
1455 dynamic->stencil_compare_mask.front =
1456 pCreateInfo->pDepthStencilState->front.compareMask;
1457 dynamic->stencil_compare_mask.back =
1458 pCreateInfo->pDepthStencilState->back.compareMask;
1459 }
1460
1461 if (states & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
1462 dynamic->stencil_write_mask.front =
1463 pCreateInfo->pDepthStencilState->front.writeMask;
1464 dynamic->stencil_write_mask.back =
1465 pCreateInfo->pDepthStencilState->back.writeMask;
1466 }
1467
1468 if (states & RADV_DYNAMIC_STENCIL_REFERENCE) {
1469 dynamic->stencil_reference.front =
1470 pCreateInfo->pDepthStencilState->front.reference;
1471 dynamic->stencil_reference.back =
1472 pCreateInfo->pDepthStencilState->back.reference;
1473 }
1474
1475 if (states & RADV_DYNAMIC_DEPTH_TEST_ENABLE) {
1476 dynamic->depth_test_enable =
1477 pCreateInfo->pDepthStencilState->depthTestEnable;
1478 }
1479
1480 if (states & RADV_DYNAMIC_DEPTH_WRITE_ENABLE) {
1481 dynamic->depth_write_enable =
1482 pCreateInfo->pDepthStencilState->depthWriteEnable;
1483 }
1484
1485 if (states & RADV_DYNAMIC_DEPTH_COMPARE_OP) {
1486 dynamic->depth_compare_op =
1487 pCreateInfo->pDepthStencilState->depthCompareOp;
1488 }
1489
1490 if (states & RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE) {
1491 dynamic->depth_bounds_test_enable =
1492 pCreateInfo->pDepthStencilState->depthBoundsTestEnable;
1493 }
1494
1495 if (states & RADV_DYNAMIC_STENCIL_TEST_ENABLE) {
1496 dynamic->stencil_test_enable =
1497 pCreateInfo->pDepthStencilState->stencilTestEnable;
1498 }
1499
1500 if (states & RADV_DYNAMIC_STENCIL_OP) {
1501 dynamic->stencil_op.front.compare_op =
1502 pCreateInfo->pDepthStencilState->front.compareOp;
1503 dynamic->stencil_op.front.fail_op =
1504 pCreateInfo->pDepthStencilState->front.failOp;
1505 dynamic->stencil_op.front.pass_op =
1506 pCreateInfo->pDepthStencilState->front.passOp;
1507 dynamic->stencil_op.front.depth_fail_op =
1508 pCreateInfo->pDepthStencilState->front.depthFailOp;
1509
1510 dynamic->stencil_op.back.compare_op =
1511 pCreateInfo->pDepthStencilState->back.compareOp;
1512 dynamic->stencil_op.back.fail_op =
1513 pCreateInfo->pDepthStencilState->back.failOp;
1514 dynamic->stencil_op.back.pass_op =
1515 pCreateInfo->pDepthStencilState->back.passOp;
1516 dynamic->stencil_op.back.depth_fail_op =
1517 pCreateInfo->pDepthStencilState->back.depthFailOp;
1518 }
1519 }
1520
1521 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
1522 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
1523 if (needed_states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1524 dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount;
1525 if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1526 typed_memcpy(dynamic->discard_rectangle.rectangles,
1527 discard_rectangle_info->pDiscardRectangles,
1528 discard_rectangle_info->discardRectangleCount);
1529 }
1530 }
1531
1532 if (needed_states & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
1533 const VkPipelineSampleLocationsStateCreateInfoEXT *sample_location_info =
1534 vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1535 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
1536 /* If sampleLocationsEnable is VK_FALSE, the default sample
1537 * locations are used and the values specified in
1538 * sampleLocationsInfo are ignored.
1539 */
1540 if (sample_location_info->sampleLocationsEnable) {
1541 const VkSampleLocationsInfoEXT *pSampleLocationsInfo =
1542 &sample_location_info->sampleLocationsInfo;
1543
1544 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
1545
1546 dynamic->sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
1547 dynamic->sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
1548 dynamic->sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
1549 typed_memcpy(&dynamic->sample_location.locations[0],
1550 pSampleLocationsInfo->pSampleLocations,
1551 pSampleLocationsInfo->sampleLocationsCount);
1552 }
1553 }
1554
1555 const VkPipelineRasterizationLineStateCreateInfoEXT *rast_line_info =
1556 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
1557 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT);
1558 if (needed_states & RADV_DYNAMIC_LINE_STIPPLE) {
1559 dynamic->line_stipple.factor = rast_line_info->lineStippleFactor;
1560 dynamic->line_stipple.pattern = rast_line_info->lineStipplePattern;
1561 }
1562
1563 if (!(states & RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE))
1564 pipeline->graphics.uses_dynamic_stride = true;
1565
1566 pipeline->dynamic_state.mask = states;
1567 }
1568
1569 static void
1570 gfx9_get_gs_info(const struct radv_pipeline_key *key,
1571 const struct radv_pipeline *pipeline,
1572 nir_shader **nir,
1573 struct radv_shader_info *infos,
1574 struct gfx9_gs_info *out)
1575 {
1576 struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY];
1577 struct radv_es_output_info *es_info;
1578 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
1579 es_info = nir[MESA_SHADER_TESS_CTRL] ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1580 else
1581 es_info = nir[MESA_SHADER_TESS_CTRL] ?
1582 &infos[MESA_SHADER_TESS_EVAL].tes.es_info :
1583 &infos[MESA_SHADER_VERTEX].vs.es_info;
1584
1585 unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
1586 bool uses_adjacency;
1587 switch(key->topology) {
1588 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1589 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1590 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1591 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1592 uses_adjacency = true;
1593 break;
1594 default:
1595 uses_adjacency = false;
1596 break;
1597 }
1598
1599 /* All these are in dwords: */
1600 /* We can't allow using the whole LDS, because GS waves compete with
1601 * other shader stages for LDS space. */
1602 const unsigned max_lds_size = 8 * 1024;
1603 const unsigned esgs_itemsize = es_info->esgs_itemsize / 4;
1604 unsigned esgs_lds_size;
1605
1606 /* All these are per subgroup: */
1607 const unsigned max_out_prims = 32 * 1024;
1608 const unsigned max_es_verts = 255;
1609 const unsigned ideal_gs_prims = 64;
1610 unsigned max_gs_prims, gs_prims;
1611 unsigned min_es_verts, es_verts, worst_case_es_verts;
1612
1613 if (uses_adjacency || gs_num_invocations > 1)
1614 max_gs_prims = 127 / gs_num_invocations;
1615 else
1616 max_gs_prims = 255;
1617
1618 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1619 * Make sure we don't go over the maximum value.
1620 */
1621 if (gs_info->gs.vertices_out > 0) {
1622 max_gs_prims = MIN2(max_gs_prims,
1623 max_out_prims /
1624 (gs_info->gs.vertices_out * gs_num_invocations));
1625 }
1626 assert(max_gs_prims > 0);
1627
1628 /* If the primitive has adjacency, halve the number of vertices
1629 * that will be reused in multiple primitives.
1630 */
1631 min_es_verts = gs_info->gs.vertices_in / (uses_adjacency ? 2 : 1);
1632
1633 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
1634 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
1635
1636 /* Compute ESGS LDS size based on the worst case number of ES vertices
1637 * needed to create the target number of GS prims per subgroup.
1638 */
1639 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1640
1641 /* If total LDS usage is too big, refactor partitions based on ratio
1642 * of ESGS item sizes.
1643 */
1644 if (esgs_lds_size > max_lds_size) {
1645 /* Our target GS Prims Per Subgroup was too large. Calculate
1646 * the maximum number of GS Prims Per Subgroup that will fit
1647 * into LDS, capped by the maximum that the hardware can support.
1648 */
1649 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
1650 max_gs_prims);
1651 assert(gs_prims > 0);
1652 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
1653 max_es_verts);
1654
1655 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1656 assert(esgs_lds_size <= max_lds_size);
1657 }
1658
1659 /* Now calculate remaining ESGS information. */
1660 if (esgs_lds_size)
1661 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
1662 else
1663 es_verts = max_es_verts;
1664
1665 /* Vertices for adjacency primitives are not always reused, so restore
1666 * it for ES_VERTS_PER_SUBGRP.
1667 */
1668 min_es_verts = gs_info->gs.vertices_in;
1669
1670 /* For normal primitives, the VGT only checks if they are past the ES
1671 * verts per subgroup after allocating a full GS primitive and if they
1672 * are, kick off a new subgroup. But if those additional ES verts are
1673 * unique (e.g. not reused) we need to make sure there is enough LDS
1674 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1675 */
1676 es_verts -= min_es_verts - 1;
1677
1678 uint32_t es_verts_per_subgroup = es_verts;
1679 uint32_t gs_prims_per_subgroup = gs_prims;
1680 uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
1681 uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out;
1682 out->lds_size = align(esgs_lds_size, 128) / 128;
1683 out->vgt_gs_onchip_cntl = S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) |
1684 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) |
1685 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup);
1686 out->vgt_gs_max_prims_per_subgroup = S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup);
1687 out->vgt_esgs_ring_itemsize = esgs_itemsize;
1688 assert(max_prims_per_subgroup <= max_out_prims);
1689 }
1690
1691 static void clamp_gsprims_to_esverts(unsigned *max_gsprims, unsigned max_esverts,
1692 unsigned min_verts_per_prim, bool use_adjacency)
1693 {
1694 unsigned max_reuse = max_esverts - min_verts_per_prim;
1695 if (use_adjacency)
1696 max_reuse /= 2;
1697 *max_gsprims = MIN2(*max_gsprims, 1 + max_reuse);
1698 }
1699
1700 static unsigned
1701 radv_get_num_input_vertices(nir_shader **nir)
1702 {
1703 if (nir[MESA_SHADER_GEOMETRY]) {
1704 nir_shader *gs = nir[MESA_SHADER_GEOMETRY];
1705
1706 return gs->info.gs.vertices_in;
1707 }
1708
1709 if (nir[MESA_SHADER_TESS_CTRL]) {
1710 nir_shader *tes = nir[MESA_SHADER_TESS_EVAL];
1711
1712 if (tes->info.tess.point_mode)
1713 return 1;
1714 if (tes->info.tess.primitive_mode == GL_ISOLINES)
1715 return 2;
1716 return 3;
1717 }
1718
1719 return 3;
1720 }
1721
1722 static void
1723 gfx10_get_ngg_info(const struct radv_pipeline_key *key,
1724 struct radv_pipeline *pipeline,
1725 nir_shader **nir,
1726 struct radv_shader_info *infos,
1727 struct gfx10_ngg_info *ngg)
1728 {
1729 struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY];
1730 struct radv_es_output_info *es_info =
1731 nir[MESA_SHADER_TESS_CTRL] ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1732 unsigned gs_type = nir[MESA_SHADER_GEOMETRY] ? MESA_SHADER_GEOMETRY : MESA_SHADER_VERTEX;
1733 unsigned max_verts_per_prim = radv_get_num_input_vertices(nir);
1734 unsigned min_verts_per_prim =
1735 gs_type == MESA_SHADER_GEOMETRY ? max_verts_per_prim : 1;
1736 unsigned gs_num_invocations = nir[MESA_SHADER_GEOMETRY] ? MAX2(gs_info->gs.invocations, 1) : 1;
1737 bool uses_adjacency;
1738 switch(key->topology) {
1739 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1740 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1741 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1742 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1743 uses_adjacency = true;
1744 break;
1745 default:
1746 uses_adjacency = false;
1747 break;
1748 }
1749
1750 /* All these are in dwords: */
1751 /* We can't allow using the whole LDS, because GS waves compete with
1752 * other shader stages for LDS space.
1753 *
1754 * TODO: We should really take the shader's internal LDS use into
1755 * account. The linker will fail if the size is greater than
1756 * 8K dwords.
1757 */
1758 const unsigned max_lds_size = 8 * 1024 - 768;
1759 const unsigned target_lds_size = max_lds_size;
1760 unsigned esvert_lds_size = 0;
1761 unsigned gsprim_lds_size = 0;
1762
1763 /* All these are per subgroup: */
1764 bool max_vert_out_per_gs_instance = false;
1765 unsigned max_esverts_base = 256;
1766 unsigned max_gsprims_base = 128; /* default prim group size clamp */
1767
1768 /* Hardware has the following non-natural restrictions on the value
1769 * of GE_CNTL.VERT_GRP_SIZE based on based on the primitive type of
1770 * the draw:
1771 * - at most 252 for any line input primitive type
1772 * - at most 251 for any quad input primitive type
1773 * - at most 251 for triangle strips with adjacency (this happens to
1774 * be the natural limit for triangle *lists* with adjacency)
1775 */
1776 max_esverts_base = MIN2(max_esverts_base, 251 + max_verts_per_prim - 1);
1777
1778 if (gs_type == MESA_SHADER_GEOMETRY) {
1779 unsigned max_out_verts_per_gsprim =
1780 gs_info->gs.vertices_out * gs_num_invocations;
1781
1782 if (max_out_verts_per_gsprim <= 256) {
1783 if (max_out_verts_per_gsprim) {
1784 max_gsprims_base = MIN2(max_gsprims_base,
1785 256 / max_out_verts_per_gsprim);
1786 }
1787 } else {
1788 /* Use special multi-cycling mode in which each GS
1789 * instance gets its own subgroup. Does not work with
1790 * tessellation. */
1791 max_vert_out_per_gs_instance = true;
1792 max_gsprims_base = 1;
1793 max_out_verts_per_gsprim = gs_info->gs.vertices_out;
1794 }
1795
1796 esvert_lds_size = es_info->esgs_itemsize / 4;
1797 gsprim_lds_size = (gs_info->gs.gsvs_vertex_size / 4 + 1) * max_out_verts_per_gsprim;
1798 } else {
1799 /* VS and TES. */
1800 /* LDS size for passing data from GS to ES. */
1801 struct radv_streamout_info *so_info = nir[MESA_SHADER_TESS_CTRL]
1802 ? &infos[MESA_SHADER_TESS_EVAL].so
1803 : &infos[MESA_SHADER_VERTEX].so;
1804
1805 if (so_info->num_outputs)
1806 esvert_lds_size = 4 * so_info->num_outputs + 1;
1807
1808 /* GS stores Primitive IDs (one DWORD) into LDS at the address
1809 * corresponding to the ES thread of the provoking vertex. All
1810 * ES threads load and export PrimitiveID for their thread.
1811 */
1812 if (!nir[MESA_SHADER_TESS_CTRL] &&
1813 infos[MESA_SHADER_VERTEX].vs.outinfo.export_prim_id)
1814 esvert_lds_size = MAX2(esvert_lds_size, 1);
1815 }
1816
1817 unsigned max_gsprims = max_gsprims_base;
1818 unsigned max_esverts = max_esverts_base;
1819
1820 if (esvert_lds_size)
1821 max_esverts = MIN2(max_esverts, target_lds_size / esvert_lds_size);
1822 if (gsprim_lds_size)
1823 max_gsprims = MIN2(max_gsprims, target_lds_size / gsprim_lds_size);
1824
1825 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1826 clamp_gsprims_to_esverts(&max_gsprims, max_esverts, min_verts_per_prim, uses_adjacency);
1827 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1828
1829 if (esvert_lds_size || gsprim_lds_size) {
1830 /* Now that we have a rough proportionality between esverts
1831 * and gsprims based on the primitive type, scale both of them
1832 * down simultaneously based on required LDS space.
1833 *
1834 * We could be smarter about this if we knew how much vertex
1835 * reuse to expect.
1836 */
1837 unsigned lds_total = max_esverts * esvert_lds_size +
1838 max_gsprims * gsprim_lds_size;
1839 if (lds_total > target_lds_size) {
1840 max_esverts = max_esverts * target_lds_size / lds_total;
1841 max_gsprims = max_gsprims * target_lds_size / lds_total;
1842
1843 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1844 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1845 min_verts_per_prim, uses_adjacency);
1846 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1847 }
1848 }
1849
1850 /* Round up towards full wave sizes for better ALU utilization. */
1851 if (!max_vert_out_per_gs_instance) {
1852 unsigned orig_max_esverts;
1853 unsigned orig_max_gsprims;
1854 unsigned wavesize;
1855
1856 if (gs_type == MESA_SHADER_GEOMETRY) {
1857 wavesize = gs_info->wave_size;
1858 } else {
1859 wavesize = nir[MESA_SHADER_TESS_CTRL]
1860 ? infos[MESA_SHADER_TESS_EVAL].wave_size
1861 : infos[MESA_SHADER_VERTEX].wave_size;
1862 }
1863
1864 do {
1865 orig_max_esverts = max_esverts;
1866 orig_max_gsprims = max_gsprims;
1867
1868 max_esverts = align(max_esverts, wavesize);
1869 max_esverts = MIN2(max_esverts, max_esverts_base);
1870 if (esvert_lds_size)
1871 max_esverts = MIN2(max_esverts,
1872 (max_lds_size - max_gsprims * gsprim_lds_size) /
1873 esvert_lds_size);
1874 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1875
1876 max_gsprims = align(max_gsprims, wavesize);
1877 max_gsprims = MIN2(max_gsprims, max_gsprims_base);
1878 if (gsprim_lds_size)
1879 max_gsprims = MIN2(max_gsprims,
1880 (max_lds_size - max_esverts * esvert_lds_size) /
1881 gsprim_lds_size);
1882 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1883 min_verts_per_prim, uses_adjacency);
1884 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1885 } while (orig_max_esverts != max_esverts || orig_max_gsprims != max_gsprims);
1886 }
1887
1888 /* Hardware restriction: minimum value of max_esverts */
1889 max_esverts = MAX2(max_esverts, 23 + max_verts_per_prim);
1890
1891 unsigned max_out_vertices =
1892 max_vert_out_per_gs_instance ? gs_info->gs.vertices_out :
1893 gs_type == MESA_SHADER_GEOMETRY ?
1894 max_gsprims * gs_num_invocations * gs_info->gs.vertices_out :
1895 max_esverts;
1896 assert(max_out_vertices <= 256);
1897
1898 unsigned prim_amp_factor = 1;
1899 if (gs_type == MESA_SHADER_GEOMETRY) {
1900 /* Number of output primitives per GS input primitive after
1901 * GS instancing. */
1902 prim_amp_factor = gs_info->gs.vertices_out;
1903 }
1904
1905 /* The GE only checks against the maximum number of ES verts after
1906 * allocating a full GS primitive. So we need to ensure that whenever
1907 * this check passes, there is enough space for a full primitive without
1908 * vertex reuse.
1909 */
1910 ngg->hw_max_esverts = max_esverts - max_verts_per_prim + 1;
1911 ngg->max_gsprims = max_gsprims;
1912 ngg->max_out_verts = max_out_vertices;
1913 ngg->prim_amp_factor = prim_amp_factor;
1914 ngg->max_vert_out_per_gs_instance = max_vert_out_per_gs_instance;
1915 ngg->ngg_emit_size = max_gsprims * gsprim_lds_size;
1916 ngg->esgs_ring_size = 4 * max_esverts * esvert_lds_size;
1917
1918 if (gs_type == MESA_SHADER_GEOMETRY) {
1919 ngg->vgt_esgs_ring_itemsize = es_info->esgs_itemsize / 4;
1920 } else {
1921 ngg->vgt_esgs_ring_itemsize = 1;
1922 }
1923
1924 pipeline->graphics.esgs_ring_size = ngg->esgs_ring_size;
1925
1926 assert(ngg->hw_max_esverts >= 24); /* HW limitation */
1927 }
1928
1929 static void
1930 calculate_gs_ring_sizes(struct radv_pipeline *pipeline,
1931 const struct gfx9_gs_info *gs)
1932 {
1933 struct radv_device *device = pipeline->device;
1934 unsigned num_se = device->physical_device->rad_info.max_se;
1935 unsigned wave_size = 64;
1936 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1937 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
1938 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
1939 */
1940 unsigned gs_vertex_reuse =
1941 (device->physical_device->rad_info.chip_class >= GFX8 ? 32 : 16) * num_se;
1942 unsigned alignment = 256 * num_se;
1943 /* The maximum size is 63.999 MB per SE. */
1944 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1945 struct radv_shader_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1946
1947 /* Calculate the minimum size. */
1948 unsigned min_esgs_ring_size = align(gs->vgt_esgs_ring_itemsize * 4 * gs_vertex_reuse *
1949 wave_size, alignment);
1950 /* These are recommended sizes, not minimum sizes. */
1951 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1952 gs->vgt_esgs_ring_itemsize * 4 * gs_info->gs.vertices_in;
1953 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1954 gs_info->gs.max_gsvs_emit_size;
1955
1956 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1957 esgs_ring_size = align(esgs_ring_size, alignment);
1958 gsvs_ring_size = align(gsvs_ring_size, alignment);
1959
1960 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
1961 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1962
1963 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1964 }
1965
1966 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1967 unsigned *lds_size)
1968 {
1969 /* If tessellation is all offchip and on-chip GS isn't used, this
1970 * workaround is not needed.
1971 */
1972 return;
1973
1974 /* SPI barrier management bug:
1975 * Make sure we have at least 4k of LDS in use to avoid the bug.
1976 * It applies to workgroup sizes of more than one wavefront.
1977 */
1978 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1979 device->physical_device->rad_info.family == CHIP_KABINI)
1980 *lds_size = MAX2(*lds_size, 8);
1981 }
1982
1983 struct radv_shader_variant *
1984 radv_get_shader(struct radv_pipeline *pipeline,
1985 gl_shader_stage stage)
1986 {
1987 if (stage == MESA_SHADER_VERTEX) {
1988 if (pipeline->shaders[MESA_SHADER_VERTEX])
1989 return pipeline->shaders[MESA_SHADER_VERTEX];
1990 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
1991 return pipeline->shaders[MESA_SHADER_TESS_CTRL];
1992 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1993 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1994 } else if (stage == MESA_SHADER_TESS_EVAL) {
1995 if (!radv_pipeline_has_tess(pipeline))
1996 return NULL;
1997 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
1998 return pipeline->shaders[MESA_SHADER_TESS_EVAL];
1999 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
2000 return pipeline->shaders[MESA_SHADER_GEOMETRY];
2001 }
2002 return pipeline->shaders[stage];
2003 }
2004
2005 static struct radv_tessellation_state
2006 calculate_tess_state(struct radv_pipeline *pipeline,
2007 const VkGraphicsPipelineCreateInfo *pCreateInfo)
2008 {
2009 unsigned num_tcs_input_cp;
2010 unsigned num_tcs_output_cp;
2011 unsigned lds_size;
2012 unsigned num_patches;
2013 struct radv_tessellation_state tess = {0};
2014
2015 num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
2016 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
2017 num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2018
2019 lds_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.lds_size;
2020
2021 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
2022 assert(lds_size <= 65536);
2023 lds_size = align(lds_size, 512) / 512;
2024 } else {
2025 assert(lds_size <= 32768);
2026 lds_size = align(lds_size, 256) / 256;
2027 }
2028 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
2029
2030 tess.lds_size = lds_size;
2031
2032 tess.ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
2033 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
2034 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
2035
2036 struct radv_shader_variant *tes = radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL);
2037 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
2038
2039 switch (tes->info.tes.primitive_mode) {
2040 case GL_TRIANGLES:
2041 type = V_028B6C_TESS_TRIANGLE;
2042 break;
2043 case GL_QUADS:
2044 type = V_028B6C_TESS_QUAD;
2045 break;
2046 case GL_ISOLINES:
2047 type = V_028B6C_TESS_ISOLINE;
2048 break;
2049 }
2050
2051 switch (tes->info.tes.spacing) {
2052 case TESS_SPACING_EQUAL:
2053 partitioning = V_028B6C_PART_INTEGER;
2054 break;
2055 case TESS_SPACING_FRACTIONAL_ODD:
2056 partitioning = V_028B6C_PART_FRAC_ODD;
2057 break;
2058 case TESS_SPACING_FRACTIONAL_EVEN:
2059 partitioning = V_028B6C_PART_FRAC_EVEN;
2060 break;
2061 default:
2062 break;
2063 }
2064
2065 bool ccw = tes->info.tes.ccw;
2066 const VkPipelineTessellationDomainOriginStateCreateInfo *domain_origin_state =
2067 vk_find_struct_const(pCreateInfo->pTessellationState,
2068 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO);
2069
2070 if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT)
2071 ccw = !ccw;
2072
2073 if (tes->info.tes.point_mode)
2074 topology = V_028B6C_OUTPUT_POINT;
2075 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
2076 topology = V_028B6C_OUTPUT_LINE;
2077 else if (ccw)
2078 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
2079 else
2080 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
2081
2082 if (pipeline->device->physical_device->rad_info.has_distributed_tess) {
2083 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
2084 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
2085 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
2086 else
2087 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
2088 } else
2089 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
2090
2091 tess.tf_param = S_028B6C_TYPE(type) |
2092 S_028B6C_PARTITIONING(partitioning) |
2093 S_028B6C_TOPOLOGY(topology) |
2094 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
2095
2096 return tess;
2097 }
2098
2099 static const struct radv_vs_output_info *get_vs_output_info(const struct radv_pipeline *pipeline)
2100 {
2101 if (radv_pipeline_has_gs(pipeline))
2102 if (radv_pipeline_has_ngg(pipeline))
2103 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.vs.outinfo;
2104 else
2105 return &pipeline->gs_copy_shader->info.vs.outinfo;
2106 else if (radv_pipeline_has_tess(pipeline))
2107 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
2108 else
2109 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
2110 }
2111
2112 static void
2113 radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
2114 {
2115 nir_shader* ordered_shaders[MESA_SHADER_STAGES];
2116 int shader_count = 0;
2117
2118 if(shaders[MESA_SHADER_FRAGMENT]) {
2119 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
2120 }
2121 if(shaders[MESA_SHADER_GEOMETRY]) {
2122 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
2123 }
2124 if(shaders[MESA_SHADER_TESS_EVAL]) {
2125 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
2126 }
2127 if(shaders[MESA_SHADER_TESS_CTRL]) {
2128 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
2129 }
2130 if(shaders[MESA_SHADER_VERTEX]) {
2131 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
2132 }
2133
2134 if (shader_count > 1) {
2135 unsigned first = ordered_shaders[shader_count - 1]->info.stage;
2136 unsigned last = ordered_shaders[0]->info.stage;
2137
2138 if (ordered_shaders[0]->info.stage == MESA_SHADER_FRAGMENT &&
2139 ordered_shaders[1]->info.has_transform_feedback_varyings)
2140 nir_link_xfb_varyings(ordered_shaders[1], ordered_shaders[0]);
2141
2142 for (int i = 0; i < shader_count; ++i) {
2143 nir_variable_mode mask = 0;
2144
2145 if (ordered_shaders[i]->info.stage != first)
2146 mask = mask | nir_var_shader_in;
2147
2148 if (ordered_shaders[i]->info.stage != last)
2149 mask = mask | nir_var_shader_out;
2150
2151 nir_lower_io_to_scalar_early(ordered_shaders[i], mask);
2152 radv_optimize_nir(ordered_shaders[i], false, false);
2153 }
2154 }
2155
2156 for (int i = 1; i < shader_count; ++i) {
2157 nir_lower_io_arrays_to_elements(ordered_shaders[i],
2158 ordered_shaders[i - 1]);
2159
2160 if (nir_link_opt_varyings(ordered_shaders[i],
2161 ordered_shaders[i - 1]))
2162 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2163
2164 nir_remove_dead_variables(ordered_shaders[i],
2165 nir_var_shader_out, NULL);
2166 nir_remove_dead_variables(ordered_shaders[i - 1],
2167 nir_var_shader_in, NULL);
2168
2169 bool progress = nir_remove_unused_varyings(ordered_shaders[i],
2170 ordered_shaders[i - 1]);
2171
2172 nir_compact_varyings(ordered_shaders[i],
2173 ordered_shaders[i - 1], true);
2174
2175 if (progress) {
2176 if (nir_lower_global_vars_to_local(ordered_shaders[i])) {
2177 ac_lower_indirect_derefs(ordered_shaders[i],
2178 pipeline->device->physical_device->rad_info.chip_class);
2179 }
2180 radv_optimize_nir(ordered_shaders[i], false, false);
2181
2182 if (nir_lower_global_vars_to_local(ordered_shaders[i - 1])) {
2183 ac_lower_indirect_derefs(ordered_shaders[i - 1],
2184 pipeline->device->physical_device->rad_info.chip_class);
2185 }
2186 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2187 }
2188 }
2189 }
2190
2191 static void
2192 radv_set_linked_driver_locations(struct radv_pipeline *pipeline, nir_shader **shaders,
2193 struct radv_shader_info infos[MESA_SHADER_STAGES])
2194 {
2195 bool has_tess = shaders[MESA_SHADER_TESS_CTRL];
2196 bool has_gs = shaders[MESA_SHADER_GEOMETRY];
2197
2198 if (!has_tess && !has_gs)
2199 return;
2200
2201 unsigned vs_info_idx = MESA_SHADER_VERTEX;
2202 unsigned tes_info_idx = MESA_SHADER_TESS_EVAL;
2203
2204 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
2205 /* These are merged into the next stage */
2206 vs_info_idx = has_tess ? MESA_SHADER_TESS_CTRL : MESA_SHADER_GEOMETRY;
2207 tes_info_idx = has_gs ? MESA_SHADER_GEOMETRY : MESA_SHADER_TESS_EVAL;
2208 }
2209
2210 if (has_tess) {
2211 nir_linked_io_var_info vs2tcs =
2212 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_VERTEX], shaders[MESA_SHADER_TESS_CTRL]);
2213 nir_linked_io_var_info tcs2tes =
2214 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_TESS_CTRL], shaders[MESA_SHADER_TESS_EVAL]);
2215
2216 infos[vs_info_idx].vs.num_linked_outputs = vs2tcs.num_linked_io_vars;
2217 infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_inputs = vs2tcs.num_linked_io_vars;
2218 infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_outputs = tcs2tes.num_linked_io_vars;
2219 infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_patch_outputs = tcs2tes.num_linked_patch_io_vars;
2220 infos[tes_info_idx].tes.num_linked_inputs = tcs2tes.num_linked_io_vars;
2221 infos[tes_info_idx].tes.num_linked_patch_inputs = tcs2tes.num_linked_patch_io_vars;
2222
2223 if (has_gs) {
2224 nir_linked_io_var_info tes2gs =
2225 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_TESS_EVAL], shaders[MESA_SHADER_GEOMETRY]);
2226
2227 infos[tes_info_idx].tes.num_linked_outputs = tes2gs.num_linked_io_vars;
2228 infos[MESA_SHADER_GEOMETRY].gs.num_linked_inputs = tes2gs.num_linked_io_vars;
2229 }
2230 } else if (has_gs) {
2231 nir_linked_io_var_info vs2gs =
2232 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_VERTEX], shaders[MESA_SHADER_GEOMETRY]);
2233
2234 infos[vs_info_idx].vs.num_linked_outputs = vs2gs.num_linked_io_vars;
2235 infos[MESA_SHADER_GEOMETRY].gs.num_linked_inputs = vs2gs.num_linked_io_vars;
2236 }
2237 }
2238
2239 static uint32_t
2240 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo *input_state,
2241 uint32_t attrib_binding)
2242 {
2243 for (uint32_t i = 0; i < input_state->vertexBindingDescriptionCount; i++) {
2244 const VkVertexInputBindingDescription *input_binding =
2245 &input_state->pVertexBindingDescriptions[i];
2246
2247 if (input_binding->binding == attrib_binding)
2248 return input_binding->stride;
2249 }
2250
2251 return 0;
2252 }
2253
2254 static struct radv_pipeline_key
2255 radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
2256 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2257 const struct radv_blend_state *blend,
2258 bool has_view_index)
2259 {
2260 const VkPipelineVertexInputStateCreateInfo *input_state =
2261 pCreateInfo->pVertexInputState;
2262 const VkPipelineVertexInputDivisorStateCreateInfoEXT *divisor_state =
2263 vk_find_struct_const(input_state->pNext, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT);
2264
2265 struct radv_pipeline_key key;
2266 memset(&key, 0, sizeof(key));
2267
2268 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
2269 key.optimisations_disabled = 1;
2270
2271 key.has_multiview_view_index = has_view_index;
2272
2273 uint32_t binding_input_rate = 0;
2274 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
2275 for (unsigned i = 0; i < input_state->vertexBindingDescriptionCount; ++i) {
2276 if (input_state->pVertexBindingDescriptions[i].inputRate) {
2277 unsigned binding = input_state->pVertexBindingDescriptions[i].binding;
2278 binding_input_rate |= 1u << binding;
2279 instance_rate_divisors[binding] = 1;
2280 }
2281 }
2282 if (divisor_state) {
2283 for (unsigned i = 0; i < divisor_state->vertexBindingDivisorCount; ++i) {
2284 instance_rate_divisors[divisor_state->pVertexBindingDivisors[i].binding] =
2285 divisor_state->pVertexBindingDivisors[i].divisor;
2286 }
2287 }
2288
2289 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
2290 const VkVertexInputAttributeDescription *desc =
2291 &input_state->pVertexAttributeDescriptions[i];
2292 const struct vk_format_description *format_desc;
2293 unsigned location = desc->location;
2294 unsigned binding = desc->binding;
2295 unsigned num_format, data_format;
2296 int first_non_void;
2297
2298 if (binding_input_rate & (1u << binding)) {
2299 key.instance_rate_inputs |= 1u << location;
2300 key.instance_rate_divisors[location] = instance_rate_divisors[binding];
2301 }
2302
2303 format_desc = vk_format_description(desc->format);
2304 first_non_void = vk_format_get_first_non_void_channel(desc->format);
2305
2306 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
2307 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
2308
2309 key.vertex_attribute_formats[location] = data_format | (num_format << 4);
2310 key.vertex_attribute_bindings[location] = desc->binding;
2311 key.vertex_attribute_offsets[location] = desc->offset;
2312 key.vertex_attribute_strides[location] = radv_get_attrib_stride(input_state, desc->binding);
2313
2314 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8 &&
2315 pipeline->device->physical_device->rad_info.family != CHIP_STONEY) {
2316 VkFormat format = input_state->pVertexAttributeDescriptions[i].format;
2317 uint64_t adjust;
2318 switch(format) {
2319 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2320 case VK_FORMAT_A2B10G10R10_SNORM_PACK32:
2321 adjust = RADV_ALPHA_ADJUST_SNORM;
2322 break;
2323 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2324 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32:
2325 adjust = RADV_ALPHA_ADJUST_SSCALED;
2326 break;
2327 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2328 case VK_FORMAT_A2B10G10R10_SINT_PACK32:
2329 adjust = RADV_ALPHA_ADJUST_SINT;
2330 break;
2331 default:
2332 adjust = 0;
2333 break;
2334 }
2335 key.vertex_alpha_adjust |= adjust << (2 * location);
2336 }
2337
2338 switch (desc->format) {
2339 case VK_FORMAT_B8G8R8A8_UNORM:
2340 case VK_FORMAT_B8G8R8A8_SNORM:
2341 case VK_FORMAT_B8G8R8A8_USCALED:
2342 case VK_FORMAT_B8G8R8A8_SSCALED:
2343 case VK_FORMAT_B8G8R8A8_UINT:
2344 case VK_FORMAT_B8G8R8A8_SINT:
2345 case VK_FORMAT_B8G8R8A8_SRGB:
2346 case VK_FORMAT_A2R10G10B10_UNORM_PACK32:
2347 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2348 case VK_FORMAT_A2R10G10B10_USCALED_PACK32:
2349 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2350 case VK_FORMAT_A2R10G10B10_UINT_PACK32:
2351 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2352 key.vertex_post_shuffle |= 1 << location;
2353 break;
2354 default:
2355 break;
2356 }
2357 }
2358
2359 const VkPipelineTessellationStateCreateInfo *tess =
2360 radv_pipeline_get_tessellation_state(pCreateInfo);
2361 if (tess)
2362 key.tess_input_vertices = tess->patchControlPoints;
2363
2364 const VkPipelineMultisampleStateCreateInfo *vkms =
2365 radv_pipeline_get_multisample_state(pCreateInfo);
2366 if (vkms && vkms->rasterizationSamples > 1) {
2367 uint32_t num_samples = vkms->rasterizationSamples;
2368 uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo);
2369 key.num_samples = num_samples;
2370 key.log2_ps_iter_samples = util_logbase2(ps_iter_samples);
2371 }
2372
2373 key.col_format = blend->spi_shader_col_format;
2374 key.is_dual_src = blend->mrt0_is_dual_src;
2375 if (pipeline->device->physical_device->rad_info.chip_class < GFX8) {
2376 key.is_int8 = blend->col_format_is_int8;
2377 key.is_int10 = blend->col_format_is_int10;
2378 }
2379
2380 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10)
2381 key.topology = pCreateInfo->pInputAssemblyState->topology;
2382
2383 return key;
2384 }
2385
2386 static bool
2387 radv_nir_stage_uses_xfb(const nir_shader *nir)
2388 {
2389 nir_xfb_info *xfb = nir_gather_xfb_info(nir, NULL);
2390 bool uses_xfb = !!xfb;
2391
2392 ralloc_free(xfb);
2393 return uses_xfb;
2394 }
2395
2396 static void
2397 radv_fill_shader_keys(struct radv_device *device,
2398 struct radv_shader_variant_key *keys,
2399 const struct radv_pipeline_key *key,
2400 nir_shader **nir)
2401 {
2402 keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
2403 keys[MESA_SHADER_VERTEX].vs.alpha_adjust = key->vertex_alpha_adjust;
2404 keys[MESA_SHADER_VERTEX].vs.post_shuffle = key->vertex_post_shuffle;
2405 for (unsigned i = 0; i < MAX_VERTEX_ATTRIBS; ++i) {
2406 keys[MESA_SHADER_VERTEX].vs.instance_rate_divisors[i] = key->instance_rate_divisors[i];
2407 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_formats[i] = key->vertex_attribute_formats[i];
2408 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_bindings[i] = key->vertex_attribute_bindings[i];
2409 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_offsets[i] = key->vertex_attribute_offsets[i];
2410 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_strides[i] = key->vertex_attribute_strides[i];
2411 }
2412 keys[MESA_SHADER_VERTEX].vs.outprim = si_conv_prim_to_gs_out(key->topology);
2413
2414 if (nir[MESA_SHADER_TESS_CTRL]) {
2415 keys[MESA_SHADER_VERTEX].vs_common_out.as_ls = true;
2416 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = 0;
2417 keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices;
2418 keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
2419
2420 keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
2421 }
2422
2423 if (nir[MESA_SHADER_GEOMETRY]) {
2424 if (nir[MESA_SHADER_TESS_CTRL])
2425 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_es = true;
2426 else
2427 keys[MESA_SHADER_VERTEX].vs_common_out.as_es = true;
2428 }
2429
2430 if (device->physical_device->use_ngg) {
2431 if (nir[MESA_SHADER_TESS_CTRL]) {
2432 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = true;
2433 } else {
2434 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = true;
2435 }
2436
2437 if (nir[MESA_SHADER_TESS_CTRL] &&
2438 nir[MESA_SHADER_GEOMETRY] &&
2439 nir[MESA_SHADER_GEOMETRY]->info.gs.invocations *
2440 nir[MESA_SHADER_GEOMETRY]->info.gs.vertices_out > 256) {
2441 /* Fallback to the legacy path if tessellation is
2442 * enabled with extreme geometry because
2443 * EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it
2444 * might hang.
2445 */
2446 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2447 }
2448
2449 if (!device->physical_device->use_ngg_gs) {
2450 if (nir[MESA_SHADER_GEOMETRY]) {
2451 if (nir[MESA_SHADER_TESS_CTRL])
2452 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2453 else
2454 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2455 }
2456 }
2457
2458 gl_shader_stage last_xfb_stage = MESA_SHADER_VERTEX;
2459
2460 for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
2461 if (nir[i])
2462 last_xfb_stage = i;
2463 }
2464
2465 bool uses_xfb = nir[last_xfb_stage] &&
2466 radv_nir_stage_uses_xfb(nir[last_xfb_stage]);
2467
2468 if (!device->physical_device->use_ngg_streamout && uses_xfb) {
2469 if (nir[MESA_SHADER_TESS_CTRL])
2470 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2471 else
2472 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2473 }
2474
2475 /* Determine if the pipeline is eligible for the NGG passthrough
2476 * mode. It can't be enabled for geometry shaders, for NGG
2477 * streamout or for vertex shaders that export the primitive ID
2478 * (this is checked later because we don't have the info here.)
2479 */
2480 if (!nir[MESA_SHADER_GEOMETRY] && !uses_xfb) {
2481 if (nir[MESA_SHADER_TESS_CTRL] &&
2482 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg) {
2483 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg_passthrough = true;
2484 } else if (nir[MESA_SHADER_VERTEX] &&
2485 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg) {
2486 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg_passthrough = true;
2487 }
2488 }
2489 }
2490
2491 for(int i = 0; i < MESA_SHADER_STAGES; ++i)
2492 keys[i].has_multiview_view_index = key->has_multiview_view_index;
2493
2494 keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format;
2495 keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8;
2496 keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
2497 keys[MESA_SHADER_FRAGMENT].fs.log2_ps_iter_samples = key->log2_ps_iter_samples;
2498 keys[MESA_SHADER_FRAGMENT].fs.num_samples = key->num_samples;
2499 keys[MESA_SHADER_FRAGMENT].fs.is_dual_src = key->is_dual_src;
2500
2501 if (nir[MESA_SHADER_COMPUTE]) {
2502 keys[MESA_SHADER_COMPUTE].cs.subgroup_size = key->compute_subgroup_size;
2503 }
2504 }
2505
2506 static uint8_t
2507 radv_get_wave_size(struct radv_device *device,
2508 const VkPipelineShaderStageCreateInfo *pStage,
2509 gl_shader_stage stage,
2510 const struct radv_shader_variant_key *key)
2511 {
2512 if (stage == MESA_SHADER_GEOMETRY && !key->vs_common_out.as_ngg)
2513 return 64;
2514 else if (stage == MESA_SHADER_COMPUTE) {
2515 if (key->cs.subgroup_size) {
2516 /* Return the required subgroup size if specified. */
2517 return key->cs.subgroup_size;
2518 }
2519 return device->physical_device->cs_wave_size;
2520 }
2521 else if (stage == MESA_SHADER_FRAGMENT)
2522 return device->physical_device->ps_wave_size;
2523 else
2524 return device->physical_device->ge_wave_size;
2525 }
2526
2527 static uint8_t
2528 radv_get_ballot_bit_size(struct radv_device *device,
2529 const VkPipelineShaderStageCreateInfo *pStage,
2530 gl_shader_stage stage,
2531 const struct radv_shader_variant_key *key)
2532 {
2533 if (stage == MESA_SHADER_COMPUTE && key->cs.subgroup_size)
2534 return key->cs.subgroup_size;
2535 return 64;
2536 }
2537
2538 static void
2539 radv_fill_shader_info(struct radv_pipeline *pipeline,
2540 const VkPipelineShaderStageCreateInfo **pStages,
2541 struct radv_shader_variant_key *keys,
2542 struct radv_shader_info *infos,
2543 nir_shader **nir)
2544 {
2545 unsigned active_stages = 0;
2546 unsigned filled_stages = 0;
2547
2548 for (int i = 0; i < MESA_SHADER_STAGES; i++) {
2549 if (nir[i])
2550 active_stages |= (1 << i);
2551 }
2552
2553 if (nir[MESA_SHADER_FRAGMENT]) {
2554 radv_nir_shader_info_init(&infos[MESA_SHADER_FRAGMENT]);
2555 radv_nir_shader_info_pass(nir[MESA_SHADER_FRAGMENT],
2556 pipeline->layout,
2557 &keys[MESA_SHADER_FRAGMENT],
2558 &infos[MESA_SHADER_FRAGMENT],
2559 pipeline->device->physical_device->use_llvm);
2560
2561 /* TODO: These are no longer used as keys we should refactor this */
2562 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id =
2563 infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
2564 keys[MESA_SHADER_VERTEX].vs_common_out.export_layer_id =
2565 infos[MESA_SHADER_FRAGMENT].ps.layer_input;
2566 keys[MESA_SHADER_VERTEX].vs_common_out.export_clip_dists =
2567 !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
2568 keys[MESA_SHADER_VERTEX].vs_common_out.export_viewport_index =
2569 infos[MESA_SHADER_FRAGMENT].ps.viewport_index_input;
2570 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_prim_id =
2571 infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
2572 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_layer_id =
2573 infos[MESA_SHADER_FRAGMENT].ps.layer_input;
2574 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_clip_dists =
2575 !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
2576 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_viewport_index =
2577 infos[MESA_SHADER_FRAGMENT].ps.viewport_index_input;
2578
2579 /* NGG passthrough mode can't be enabled for vertex shaders
2580 * that export the primitive ID.
2581 *
2582 * TODO: I should really refactor the keys logic.
2583 */
2584 if (nir[MESA_SHADER_VERTEX] &&
2585 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id) {
2586 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg_passthrough = false;
2587 }
2588
2589 filled_stages |= (1 << MESA_SHADER_FRAGMENT);
2590 }
2591
2592 if (nir[MESA_SHADER_TESS_CTRL]) {
2593 infos[MESA_SHADER_TESS_CTRL].tcs.tes_inputs_read =
2594 nir[MESA_SHADER_TESS_EVAL]->info.inputs_read;
2595 infos[MESA_SHADER_TESS_CTRL].tcs.tes_patch_inputs_read =
2596 nir[MESA_SHADER_TESS_EVAL]->info.patch_inputs_read;
2597 }
2598
2599 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
2600 nir[MESA_SHADER_TESS_CTRL]) {
2601 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2602 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2603 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2604
2605 radv_nir_shader_info_init(&infos[MESA_SHADER_TESS_CTRL]);
2606
2607 for (int i = 0; i < 2; i++) {
2608 radv_nir_shader_info_pass(combined_nir[i],
2609 pipeline->layout, &key,
2610 &infos[MESA_SHADER_TESS_CTRL],
2611 pipeline->device->physical_device->use_llvm);
2612 }
2613
2614 keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
2615 infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
2616 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs =
2617 util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written);
2618
2619 filled_stages |= (1 << MESA_SHADER_VERTEX);
2620 filled_stages |= (1 << MESA_SHADER_TESS_CTRL);
2621 }
2622
2623 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
2624 nir[MESA_SHADER_GEOMETRY]) {
2625 gl_shader_stage pre_stage = nir[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2626 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2627
2628 radv_nir_shader_info_init(&infos[MESA_SHADER_GEOMETRY]);
2629
2630 for (int i = 0; i < 2; i++) {
2631 radv_nir_shader_info_pass(combined_nir[i],
2632 pipeline->layout,
2633 &keys[pre_stage],
2634 &infos[MESA_SHADER_GEOMETRY],
2635 pipeline->device->physical_device->use_llvm);
2636 }
2637
2638 filled_stages |= (1 << pre_stage);
2639 filled_stages |= (1 << MESA_SHADER_GEOMETRY);
2640 }
2641
2642 active_stages ^= filled_stages;
2643 while (active_stages) {
2644 int i = u_bit_scan(&active_stages);
2645
2646 if (i == MESA_SHADER_TESS_CTRL) {
2647 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs =
2648 util_last_bit64(infos[MESA_SHADER_VERTEX].vs.ls_outputs_written);
2649 }
2650
2651 if (i == MESA_SHADER_TESS_EVAL) {
2652 keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
2653 infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
2654 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs =
2655 util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written);
2656 }
2657
2658 radv_nir_shader_info_init(&infos[i]);
2659 radv_nir_shader_info_pass(nir[i], pipeline->layout,
2660 &keys[i], &infos[i], pipeline->device->physical_device->use_llvm);
2661 }
2662
2663 for (int i = 0; i < MESA_SHADER_STAGES; i++) {
2664 if (nir[i]) {
2665 infos[i].wave_size =
2666 radv_get_wave_size(pipeline->device, pStages[i],
2667 i, &keys[i]);
2668 infos[i].ballot_bit_size =
2669 radv_get_ballot_bit_size(pipeline->device,
2670 pStages[i], i,
2671 &keys[i]);
2672 }
2673 }
2674 }
2675
2676 static void
2677 merge_tess_info(struct shader_info *tes_info,
2678 const struct shader_info *tcs_info)
2679 {
2680 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2681 *
2682 * "PointMode. Controls generation of points rather than triangles
2683 * or lines. This functionality defaults to disabled, and is
2684 * enabled if either shader stage includes the execution mode.
2685 *
2686 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2687 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2688 * and OutputVertices, it says:
2689 *
2690 * "One mode must be set in at least one of the tessellation
2691 * shader stages."
2692 *
2693 * So, the fields can be set in either the TCS or TES, but they must
2694 * agree if set in both. Our backend looks at TES, so bitwise-or in
2695 * the values from the TCS.
2696 */
2697 assert(tcs_info->tess.tcs_vertices_out == 0 ||
2698 tes_info->tess.tcs_vertices_out == 0 ||
2699 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
2700 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
2701
2702 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2703 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2704 tcs_info->tess.spacing == tes_info->tess.spacing);
2705 tes_info->tess.spacing |= tcs_info->tess.spacing;
2706
2707 assert(tcs_info->tess.primitive_mode == 0 ||
2708 tes_info->tess.primitive_mode == 0 ||
2709 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
2710 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
2711 tes_info->tess.ccw |= tcs_info->tess.ccw;
2712 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
2713 }
2714
2715 static
2716 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT *ext)
2717 {
2718 if (!ext)
2719 return;
2720
2721 if (ext->pPipelineCreationFeedback) {
2722 ext->pPipelineCreationFeedback->flags = 0;
2723 ext->pPipelineCreationFeedback->duration = 0;
2724 }
2725
2726 for (unsigned i = 0; i < ext->pipelineStageCreationFeedbackCount; ++i) {
2727 ext->pPipelineStageCreationFeedbacks[i].flags = 0;
2728 ext->pPipelineStageCreationFeedbacks[i].duration = 0;
2729 }
2730 }
2731
2732 static
2733 void radv_start_feedback(VkPipelineCreationFeedbackEXT *feedback)
2734 {
2735 if (!feedback)
2736 return;
2737
2738 feedback->duration -= radv_get_current_time();
2739 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT;
2740 }
2741
2742 static
2743 void radv_stop_feedback(VkPipelineCreationFeedbackEXT *feedback, bool cache_hit)
2744 {
2745 if (!feedback)
2746 return;
2747
2748 feedback->duration += radv_get_current_time();
2749 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT |
2750 (cache_hit ? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT : 0);
2751 }
2752
2753 VkResult radv_create_shaders(struct radv_pipeline *pipeline,
2754 struct radv_device *device,
2755 struct radv_pipeline_cache *cache,
2756 const struct radv_pipeline_key *key,
2757 const VkPipelineShaderStageCreateInfo **pStages,
2758 const VkPipelineCreateFlags flags,
2759 VkPipelineCreationFeedbackEXT *pipeline_feedback,
2760 VkPipelineCreationFeedbackEXT **stage_feedbacks)
2761 {
2762 struct radv_shader_module fs_m = {0};
2763 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
2764 nir_shader *nir[MESA_SHADER_STAGES] = {0};
2765 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2766 struct radv_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{{0}}}}};
2767 struct radv_shader_info infos[MESA_SHADER_STAGES] = {0};
2768 unsigned char hash[20], gs_copy_hash[20];
2769 bool keep_executable_info = (flags & VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR) || device->keep_shader_info;
2770 bool keep_statistic_info = (flags & VK_PIPELINE_CREATE_CAPTURE_STATISTICS_BIT_KHR) ||
2771 (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) ||
2772 device->keep_shader_info;
2773
2774 radv_start_feedback(pipeline_feedback);
2775
2776 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2777 if (pStages[i]) {
2778 modules[i] = radv_shader_module_from_handle(pStages[i]->module);
2779 if (modules[i]->nir)
2780 _mesa_sha1_compute(modules[i]->nir->info.name,
2781 strlen(modules[i]->nir->info.name),
2782 modules[i]->sha1);
2783
2784 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
2785 }
2786 }
2787
2788 radv_hash_shaders(hash, pStages, pipeline->layout, key, get_hash_flags(device));
2789 memcpy(gs_copy_hash, hash, 20);
2790 gs_copy_hash[0] ^= 1;
2791
2792 bool found_in_application_cache = true;
2793 if (modules[MESA_SHADER_GEOMETRY] && !keep_executable_info && !keep_statistic_info) {
2794 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2795 radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants,
2796 &found_in_application_cache);
2797 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
2798 }
2799
2800 if (!keep_executable_info && !keep_statistic_info &&
2801 radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders,
2802 &found_in_application_cache) &&
2803 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
2804 radv_stop_feedback(pipeline_feedback, found_in_application_cache);
2805 return VK_SUCCESS;
2806 }
2807
2808 if (flags & VK_PIPELINE_CREATE_FAIL_ON_PIPELINE_COMPILE_REQUIRED_BIT_EXT) {
2809 radv_stop_feedback(pipeline_feedback, found_in_application_cache);
2810 return VK_PIPELINE_COMPILE_REQUIRED_EXT;
2811 }
2812
2813 if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
2814 nir_builder fs_b;
2815 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
2816 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
2817 fs_m.nir = fs_b.shader;
2818 modules[MESA_SHADER_FRAGMENT] = &fs_m;
2819 }
2820
2821 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2822 const VkPipelineShaderStageCreateInfo *stage = pStages[i];
2823 unsigned subgroup_size = 64, ballot_bit_size = 64;
2824
2825 if (!modules[i])
2826 continue;
2827
2828 radv_start_feedback(stage_feedbacks[i]);
2829
2830 if (key->compute_subgroup_size) {
2831 /* Only compute shaders currently support requiring a
2832 * specific subgroup size.
2833 */
2834 assert(i == MESA_SHADER_COMPUTE);
2835 subgroup_size = key->compute_subgroup_size;
2836 ballot_bit_size = key->compute_subgroup_size;
2837 }
2838
2839 nir[i] = radv_shader_compile_to_nir(device, modules[i],
2840 stage ? stage->pName : "main", i,
2841 stage ? stage->pSpecializationInfo : NULL,
2842 flags, pipeline->layout,
2843 subgroup_size, ballot_bit_size);
2844
2845 /* We don't want to alter meta shaders IR directly so clone it
2846 * first.
2847 */
2848 if (nir[i]->info.name) {
2849 nir[i] = nir_shader_clone(NULL, nir[i]);
2850 }
2851
2852 radv_stop_feedback(stage_feedbacks[i], false);
2853 }
2854
2855 if (nir[MESA_SHADER_TESS_CTRL]) {
2856 nir_lower_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out, NULL);
2857 merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
2858 }
2859
2860 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
2861 radv_link_shaders(pipeline, nir);
2862
2863 radv_set_linked_driver_locations(pipeline, nir, infos);
2864
2865 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2866 if (nir[i]) {
2867 /* do this again since information such as outputs_read can be out-of-date */
2868 nir_shader_gather_info(nir[i], nir_shader_get_entrypoint(nir[i]));
2869
2870 if (device->physical_device->use_llvm) {
2871 NIR_PASS_V(nir[i], nir_lower_bool_to_int32);
2872 } else {
2873 NIR_PASS_V(nir[i], nir_lower_non_uniform_access,
2874 nir_lower_non_uniform_ubo_access |
2875 nir_lower_non_uniform_ssbo_access |
2876 nir_lower_non_uniform_texture_access |
2877 nir_lower_non_uniform_image_access);
2878 }
2879 }
2880 }
2881
2882 if (nir[MESA_SHADER_FRAGMENT])
2883 radv_lower_fs_io(nir[MESA_SHADER_FRAGMENT]);
2884
2885 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2886 if (radv_can_dump_shader(device, modules[i], false))
2887 nir_print_shader(nir[i], stderr);
2888 }
2889
2890 radv_fill_shader_keys(device, keys, key, nir);
2891
2892 radv_fill_shader_info(pipeline, pStages, keys, infos, nir);
2893
2894 if ((nir[MESA_SHADER_VERTEX] &&
2895 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg) ||
2896 (nir[MESA_SHADER_TESS_EVAL] &&
2897 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg)) {
2898 struct gfx10_ngg_info *ngg_info;
2899
2900 if (nir[MESA_SHADER_GEOMETRY])
2901 ngg_info = &infos[MESA_SHADER_GEOMETRY].ngg_info;
2902 else if (nir[MESA_SHADER_TESS_CTRL])
2903 ngg_info = &infos[MESA_SHADER_TESS_EVAL].ngg_info;
2904 else
2905 ngg_info = &infos[MESA_SHADER_VERTEX].ngg_info;
2906
2907 gfx10_get_ngg_info(key, pipeline, nir, infos, ngg_info);
2908 } else if (nir[MESA_SHADER_GEOMETRY]) {
2909 struct gfx9_gs_info *gs_info =
2910 &infos[MESA_SHADER_GEOMETRY].gs_ring_info;
2911
2912 gfx9_get_gs_info(key, pipeline, nir, infos, gs_info);
2913 }
2914
2915 if(modules[MESA_SHADER_GEOMETRY]) {
2916 struct radv_shader_binary *gs_copy_binary = NULL;
2917 if (!pipeline->gs_copy_shader &&
2918 !radv_pipeline_has_ngg(pipeline)) {
2919 struct radv_shader_info info = {};
2920 struct radv_shader_variant_key key = {};
2921
2922 key.has_multiview_view_index =
2923 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index;
2924
2925 radv_nir_shader_info_pass(nir[MESA_SHADER_GEOMETRY],
2926 pipeline->layout, &key,
2927 &info, pipeline->device->physical_device->use_llvm);
2928 info.wave_size = 64; /* Wave32 not supported. */
2929 info.ballot_bit_size = 64;
2930
2931 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
2932 device, nir[MESA_SHADER_GEOMETRY], &info,
2933 &gs_copy_binary, keep_executable_info, keep_statistic_info,
2934 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
2935 }
2936
2937 if (!keep_executable_info && !keep_statistic_info && pipeline->gs_copy_shader) {
2938 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2939 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2940
2941 binaries[MESA_SHADER_GEOMETRY] = gs_copy_binary;
2942 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
2943
2944 radv_pipeline_cache_insert_shaders(device, cache,
2945 gs_copy_hash,
2946 variants,
2947 binaries);
2948 }
2949 free(gs_copy_binary);
2950 }
2951
2952 if (nir[MESA_SHADER_FRAGMENT]) {
2953 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
2954 radv_start_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT]);
2955
2956 pipeline->shaders[MESA_SHADER_FRAGMENT] =
2957 radv_shader_variant_compile(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
2958 pipeline->layout, keys + MESA_SHADER_FRAGMENT,
2959 infos + MESA_SHADER_FRAGMENT,
2960 keep_executable_info, keep_statistic_info,
2961 &binaries[MESA_SHADER_FRAGMENT]);
2962
2963 radv_stop_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT], false);
2964 }
2965 }
2966
2967 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
2968 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
2969 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2970 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2971 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2972
2973 radv_start_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL]);
2974
2975 pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_compile(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
2976 pipeline->layout,
2977 &key, &infos[MESA_SHADER_TESS_CTRL], keep_executable_info,
2978 keep_statistic_info, &binaries[MESA_SHADER_TESS_CTRL]);
2979
2980 radv_stop_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL], false);
2981 }
2982 modules[MESA_SHADER_VERTEX] = NULL;
2983 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2984 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written);
2985 }
2986
2987 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
2988 gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2989 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
2990 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2991
2992 radv_start_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY]);
2993
2994 pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_compile(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
2995 pipeline->layout,
2996 &keys[pre_stage], &infos[MESA_SHADER_GEOMETRY], keep_executable_info,
2997 keep_statistic_info, &binaries[MESA_SHADER_GEOMETRY]);
2998
2999 radv_stop_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY], false);
3000 }
3001 modules[pre_stage] = NULL;
3002 }
3003
3004 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
3005 if(modules[i] && !pipeline->shaders[i]) {
3006 if (i == MESA_SHADER_TESS_CTRL) {
3007 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.ls_outputs_written);
3008 }
3009 if (i == MESA_SHADER_TESS_EVAL) {
3010 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
3011 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written);
3012 }
3013
3014 radv_start_feedback(stage_feedbacks[i]);
3015
3016 pipeline->shaders[i] = radv_shader_variant_compile(device, modules[i], &nir[i], 1,
3017 pipeline->layout,
3018 keys + i, infos + i, keep_executable_info,
3019 keep_statistic_info, &binaries[i]);
3020
3021 radv_stop_feedback(stage_feedbacks[i], false);
3022 }
3023 }
3024
3025 if (!keep_executable_info && !keep_statistic_info) {
3026 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
3027 binaries);
3028 }
3029
3030 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
3031 free(binaries[i]);
3032 if (nir[i]) {
3033 ralloc_free(nir[i]);
3034
3035 if (radv_can_dump_shader_stats(device, modules[i]))
3036 radv_shader_dump_stats(device,
3037 pipeline->shaders[i],
3038 i, stderr);
3039 }
3040 }
3041
3042 if (fs_m.nir)
3043 ralloc_free(fs_m.nir);
3044
3045 radv_stop_feedback(pipeline_feedback, false);
3046 return VK_SUCCESS;
3047 }
3048
3049 static uint32_t
3050 radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
3051 gl_shader_stage stage, enum chip_class chip_class)
3052 {
3053 bool has_gs = radv_pipeline_has_gs(pipeline);
3054 bool has_tess = radv_pipeline_has_tess(pipeline);
3055 bool has_ngg = radv_pipeline_has_ngg(pipeline);
3056
3057 switch (stage) {
3058 case MESA_SHADER_FRAGMENT:
3059 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
3060 case MESA_SHADER_VERTEX:
3061 if (has_tess) {
3062 if (chip_class >= GFX10) {
3063 return R_00B430_SPI_SHADER_USER_DATA_HS_0;
3064 } else if (chip_class == GFX9) {
3065 return R_00B430_SPI_SHADER_USER_DATA_LS_0;
3066 } else {
3067 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
3068 }
3069
3070 }
3071
3072 if (has_gs) {
3073 if (chip_class >= GFX10) {
3074 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
3075 } else {
3076 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
3077 }
3078 }
3079
3080 if (has_ngg)
3081 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
3082
3083 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
3084 case MESA_SHADER_GEOMETRY:
3085 return chip_class == GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
3086 R_00B230_SPI_SHADER_USER_DATA_GS_0;
3087 case MESA_SHADER_COMPUTE:
3088 return R_00B900_COMPUTE_USER_DATA_0;
3089 case MESA_SHADER_TESS_CTRL:
3090 return chip_class == GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
3091 R_00B430_SPI_SHADER_USER_DATA_HS_0;
3092 case MESA_SHADER_TESS_EVAL:
3093 if (has_gs) {
3094 return chip_class >= GFX10 ? R_00B230_SPI_SHADER_USER_DATA_GS_0 :
3095 R_00B330_SPI_SHADER_USER_DATA_ES_0;
3096 } else if (has_ngg) {
3097 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
3098 } else {
3099 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
3100 }
3101 default:
3102 unreachable("unknown shader");
3103 }
3104 }
3105
3106 struct radv_bin_size_entry {
3107 unsigned bpp;
3108 VkExtent2D extent;
3109 };
3110
3111 static VkExtent2D
3112 radv_gfx9_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
3113 {
3114 static const struct radv_bin_size_entry color_size_table[][3][9] = {
3115 {
3116 /* One RB / SE */
3117 {
3118 /* One shader engine */
3119 { 0, {128, 128}},
3120 { 1, { 64, 128}},
3121 { 2, { 32, 128}},
3122 { 3, { 16, 128}},
3123 { 17, { 0, 0}},
3124 { UINT_MAX, { 0, 0}},
3125 },
3126 {
3127 /* Two shader engines */
3128 { 0, {128, 128}},
3129 { 2, { 64, 128}},
3130 { 3, { 32, 128}},
3131 { 5, { 16, 128}},
3132 { 17, { 0, 0}},
3133 { UINT_MAX, { 0, 0}},
3134 },
3135 {
3136 /* Four shader engines */
3137 { 0, {128, 128}},
3138 { 3, { 64, 128}},
3139 { 5, { 16, 128}},
3140 { 17, { 0, 0}},
3141 { UINT_MAX, { 0, 0}},
3142 },
3143 },
3144 {
3145 /* Two RB / SE */
3146 {
3147 /* One shader engine */
3148 { 0, {128, 128}},
3149 { 2, { 64, 128}},
3150 { 3, { 32, 128}},
3151 { 5, { 16, 128}},
3152 { 33, { 0, 0}},
3153 { UINT_MAX, { 0, 0}},
3154 },
3155 {
3156 /* Two shader engines */
3157 { 0, {128, 128}},
3158 { 3, { 64, 128}},
3159 { 5, { 32, 128}},
3160 { 9, { 16, 128}},
3161 { 33, { 0, 0}},
3162 { UINT_MAX, { 0, 0}},
3163 },
3164 {
3165 /* Four shader engines */
3166 { 0, {256, 256}},
3167 { 2, {128, 256}},
3168 { 3, {128, 128}},
3169 { 5, { 64, 128}},
3170 { 9, { 16, 128}},
3171 { 33, { 0, 0}},
3172 { UINT_MAX, { 0, 0}},
3173 },
3174 },
3175 {
3176 /* Four RB / SE */
3177 {
3178 /* One shader engine */
3179 { 0, {128, 256}},
3180 { 2, {128, 128}},
3181 { 3, { 64, 128}},
3182 { 5, { 32, 128}},
3183 { 9, { 16, 128}},
3184 { 33, { 0, 0}},
3185 { UINT_MAX, { 0, 0}},
3186 },
3187 {
3188 /* Two shader engines */
3189 { 0, {256, 256}},
3190 { 2, {128, 256}},
3191 { 3, {128, 128}},
3192 { 5, { 64, 128}},
3193 { 9, { 32, 128}},
3194 { 17, { 16, 128}},
3195 { 33, { 0, 0}},
3196 { UINT_MAX, { 0, 0}},
3197 },
3198 {
3199 /* Four shader engines */
3200 { 0, {256, 512}},
3201 { 2, {256, 256}},
3202 { 3, {128, 256}},
3203 { 5, {128, 128}},
3204 { 9, { 64, 128}},
3205 { 17, { 16, 128}},
3206 { 33, { 0, 0}},
3207 { UINT_MAX, { 0, 0}},
3208 },
3209 },
3210 };
3211 static const struct radv_bin_size_entry ds_size_table[][3][9] = {
3212 {
3213 // One RB / SE
3214 {
3215 // One shader engine
3216 { 0, {128, 256}},
3217 { 2, {128, 128}},
3218 { 4, { 64, 128}},
3219 { 7, { 32, 128}},
3220 { 13, { 16, 128}},
3221 { 49, { 0, 0}},
3222 { UINT_MAX, { 0, 0}},
3223 },
3224 {
3225 // Two shader engines
3226 { 0, {256, 256}},
3227 { 2, {128, 256}},
3228 { 4, {128, 128}},
3229 { 7, { 64, 128}},
3230 { 13, { 32, 128}},
3231 { 25, { 16, 128}},
3232 { 49, { 0, 0}},
3233 { UINT_MAX, { 0, 0}},
3234 },
3235 {
3236 // Four shader engines
3237 { 0, {256, 512}},
3238 { 2, {256, 256}},
3239 { 4, {128, 256}},
3240 { 7, {128, 128}},
3241 { 13, { 64, 128}},
3242 { 25, { 16, 128}},
3243 { 49, { 0, 0}},
3244 { UINT_MAX, { 0, 0}},
3245 },
3246 },
3247 {
3248 // Two RB / SE
3249 {
3250 // One shader engine
3251 { 0, {256, 256}},
3252 { 2, {128, 256}},
3253 { 4, {128, 128}},
3254 { 7, { 64, 128}},
3255 { 13, { 32, 128}},
3256 { 25, { 16, 128}},
3257 { 97, { 0, 0}},
3258 { UINT_MAX, { 0, 0}},
3259 },
3260 {
3261 // Two shader engines
3262 { 0, {256, 512}},
3263 { 2, {256, 256}},
3264 { 4, {128, 256}},
3265 { 7, {128, 128}},
3266 { 13, { 64, 128}},
3267 { 25, { 32, 128}},
3268 { 49, { 16, 128}},
3269 { 97, { 0, 0}},
3270 { UINT_MAX, { 0, 0}},
3271 },
3272 {
3273 // Four shader engines
3274 { 0, {512, 512}},
3275 { 2, {256, 512}},
3276 { 4, {256, 256}},
3277 { 7, {128, 256}},
3278 { 13, {128, 128}},
3279 { 25, { 64, 128}},
3280 { 49, { 16, 128}},
3281 { 97, { 0, 0}},
3282 { UINT_MAX, { 0, 0}},
3283 },
3284 },
3285 {
3286 // Four RB / SE
3287 {
3288 // One shader engine
3289 { 0, {256, 512}},
3290 { 2, {256, 256}},
3291 { 4, {128, 256}},
3292 { 7, {128, 128}},
3293 { 13, { 64, 128}},
3294 { 25, { 32, 128}},
3295 { 49, { 16, 128}},
3296 { UINT_MAX, { 0, 0}},
3297 },
3298 {
3299 // Two shader engines
3300 { 0, {512, 512}},
3301 { 2, {256, 512}},
3302 { 4, {256, 256}},
3303 { 7, {128, 256}},
3304 { 13, {128, 128}},
3305 { 25, { 64, 128}},
3306 { 49, { 32, 128}},
3307 { 97, { 16, 128}},
3308 { UINT_MAX, { 0, 0}},
3309 },
3310 {
3311 // Four shader engines
3312 { 0, {512, 512}},
3313 { 4, {256, 512}},
3314 { 7, {256, 256}},
3315 { 13, {128, 256}},
3316 { 25, {128, 128}},
3317 { 49, { 64, 128}},
3318 { 97, { 16, 128}},
3319 { UINT_MAX, { 0, 0}},
3320 },
3321 },
3322 };
3323
3324 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3325 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3326 VkExtent2D extent = {512, 512};
3327
3328 unsigned log_num_rb_per_se =
3329 util_logbase2_ceil(pipeline->device->physical_device->rad_info.num_render_backends /
3330 pipeline->device->physical_device->rad_info.max_se);
3331 unsigned log_num_se = util_logbase2_ceil(pipeline->device->physical_device->rad_info.max_se);
3332
3333 unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
3334 unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->graphics.ms.db_eqaa);
3335 unsigned effective_samples = total_samples;
3336 unsigned color_bytes_per_pixel = 0;
3337
3338 const VkPipelineColorBlendStateCreateInfo *vkblend =
3339 radv_pipeline_get_color_blend_state(pCreateInfo);
3340 if (vkblend) {
3341 for (unsigned i = 0; i < subpass->color_count; i++) {
3342 if (!vkblend->pAttachments[i].colorWriteMask)
3343 continue;
3344
3345 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3346 continue;
3347
3348 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3349 color_bytes_per_pixel += vk_format_get_blocksize(format);
3350 }
3351
3352 /* MSAA images typically don't use all samples all the time. */
3353 if (effective_samples >= 2 && ps_iter_samples <= 1)
3354 effective_samples = 2;
3355 color_bytes_per_pixel *= effective_samples;
3356 }
3357
3358 const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se];
3359 while(color_entry[1].bpp <= color_bytes_per_pixel)
3360 ++color_entry;
3361
3362 extent = color_entry->extent;
3363
3364 if (subpass->depth_stencil_attachment) {
3365 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3366
3367 /* Coefficients taken from AMDVLK */
3368 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
3369 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
3370 unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples;
3371
3372 const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se];
3373 while(ds_entry[1].bpp <= ds_bytes_per_pixel)
3374 ++ds_entry;
3375
3376 if (ds_entry->extent.width * ds_entry->extent.height < extent.width * extent.height)
3377 extent = ds_entry->extent;
3378 }
3379
3380 return extent;
3381 }
3382
3383 static VkExtent2D
3384 radv_gfx10_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
3385 {
3386 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3387 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3388 VkExtent2D extent = {512, 512};
3389
3390 const unsigned db_tag_size = 64;
3391 const unsigned db_tag_count = 312;
3392 const unsigned color_tag_size = 1024;
3393 const unsigned color_tag_count = 31;
3394 const unsigned fmask_tag_size = 256;
3395 const unsigned fmask_tag_count = 44;
3396
3397 const unsigned rb_count = pipeline->device->physical_device->rad_info.num_render_backends;
3398 const unsigned pipe_count = MAX2(rb_count, pipeline->device->physical_device->rad_info.num_sdp_interfaces);
3399
3400 const unsigned db_tag_part = (db_tag_count * rb_count / pipe_count) * db_tag_size * pipe_count;
3401 const unsigned color_tag_part = (color_tag_count * rb_count / pipe_count) * color_tag_size * pipe_count;
3402 const unsigned fmask_tag_part = (fmask_tag_count * rb_count / pipe_count) * fmask_tag_size * pipe_count;
3403
3404 const unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
3405 const unsigned samples_log = util_logbase2_ceil(total_samples);
3406
3407 unsigned color_bytes_per_pixel = 0;
3408 unsigned fmask_bytes_per_pixel = 0;
3409
3410 const VkPipelineColorBlendStateCreateInfo *vkblend =
3411 radv_pipeline_get_color_blend_state(pCreateInfo);
3412 if (vkblend) {
3413 for (unsigned i = 0; i < subpass->color_count; i++) {
3414 if (!vkblend->pAttachments[i].colorWriteMask)
3415 continue;
3416
3417 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3418 continue;
3419
3420 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3421 color_bytes_per_pixel += vk_format_get_blocksize(format);
3422
3423 if (total_samples > 1) {
3424 assert(samples_log <= 3);
3425 const unsigned fmask_array[] = {0, 1, 1, 4};
3426 fmask_bytes_per_pixel += fmask_array[samples_log];
3427 }
3428 }
3429
3430 color_bytes_per_pixel *= total_samples;
3431 }
3432 color_bytes_per_pixel = MAX2(color_bytes_per_pixel, 1);
3433
3434 const unsigned color_pixel_count_log = util_logbase2(color_tag_part / color_bytes_per_pixel);
3435 extent.width = 1ull << ((color_pixel_count_log + 1) / 2);
3436 extent.height = 1ull << (color_pixel_count_log / 2);
3437
3438 if (fmask_bytes_per_pixel) {
3439 const unsigned fmask_pixel_count_log = util_logbase2(fmask_tag_part / fmask_bytes_per_pixel);
3440
3441 const VkExtent2D fmask_extent = (VkExtent2D){
3442 .width = 1ull << ((fmask_pixel_count_log + 1) / 2),
3443 .height = 1ull << (color_pixel_count_log / 2)
3444 };
3445
3446 if (fmask_extent.width * fmask_extent.height < extent.width * extent.height)
3447 extent = fmask_extent;
3448 }
3449
3450 if (subpass->depth_stencil_attachment) {
3451 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3452
3453 /* Coefficients taken from AMDVLK */
3454 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
3455 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
3456 unsigned db_bytes_per_pixel = (depth_coeff + stencil_coeff) * total_samples;
3457
3458 const unsigned db_pixel_count_log = util_logbase2(db_tag_part / db_bytes_per_pixel);
3459
3460 const VkExtent2D db_extent = (VkExtent2D){
3461 .width = 1ull << ((db_pixel_count_log + 1) / 2),
3462 .height = 1ull << (color_pixel_count_log / 2)
3463 };
3464
3465 if (db_extent.width * db_extent.height < extent.width * extent.height)
3466 extent = db_extent;
3467 }
3468
3469 extent.width = MAX2(extent.width, 128);
3470 extent.height = MAX2(extent.width, 64);
3471
3472 return extent;
3473 }
3474
3475 static void
3476 radv_pipeline_generate_disabled_binning_state(struct radeon_cmdbuf *ctx_cs,
3477 struct radv_pipeline *pipeline,
3478 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3479 {
3480 uint32_t pa_sc_binner_cntl_0 =
3481 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
3482 S_028C44_DISABLE_START_OF_PRIM(1);
3483 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
3484
3485 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3486 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3487 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3488 const VkPipelineColorBlendStateCreateInfo *vkblend =
3489 radv_pipeline_get_color_blend_state(pCreateInfo);
3490 unsigned min_bytes_per_pixel = 0;
3491
3492 if (vkblend) {
3493 for (unsigned i = 0; i < subpass->color_count; i++) {
3494 if (!vkblend->pAttachments[i].colorWriteMask)
3495 continue;
3496
3497 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3498 continue;
3499
3500 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3501 unsigned bytes = vk_format_get_blocksize(format);
3502 if (!min_bytes_per_pixel || bytes < min_bytes_per_pixel)
3503 min_bytes_per_pixel = bytes;
3504 }
3505 }
3506
3507 pa_sc_binner_cntl_0 =
3508 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC) |
3509 S_028C44_BIN_SIZE_X(0) |
3510 S_028C44_BIN_SIZE_Y(0) |
3511 S_028C44_BIN_SIZE_X_EXTEND(2) | /* 128 */
3512 S_028C44_BIN_SIZE_Y_EXTEND(min_bytes_per_pixel <= 4 ? 2 : 1) | /* 128 or 64 */
3513 S_028C44_DISABLE_START_OF_PRIM(1);
3514 }
3515
3516 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
3517 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
3518 }
3519
3520 struct radv_binning_settings
3521 radv_get_binning_settings(const struct radv_physical_device *pdev)
3522 {
3523 struct radv_binning_settings settings;
3524 if (pdev->rad_info.has_dedicated_vram) {
3525 if (pdev->rad_info.num_render_backends > 4) {
3526 settings.context_states_per_bin = 1;
3527 settings.persistent_states_per_bin = 1;
3528 } else {
3529 settings.context_states_per_bin = 3;
3530 settings.persistent_states_per_bin = 8;
3531 }
3532 settings.fpovs_per_batch = 63;
3533 } else {
3534 /* The context states are affected by the scissor bug. */
3535 settings.context_states_per_bin = 6;
3536 /* 32 causes hangs for RAVEN. */
3537 settings.persistent_states_per_bin = 16;
3538 settings.fpovs_per_batch = 63;
3539 }
3540
3541 if (pdev->rad_info.has_gfx9_scissor_bug)
3542 settings.context_states_per_bin = 1;
3543
3544 return settings;
3545 }
3546
3547 static void
3548 radv_pipeline_generate_binning_state(struct radeon_cmdbuf *ctx_cs,
3549 struct radv_pipeline *pipeline,
3550 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3551 const struct radv_blend_state *blend)
3552 {
3553 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
3554 return;
3555
3556 VkExtent2D bin_size;
3557 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3558 bin_size = radv_gfx10_compute_bin_size(pipeline, pCreateInfo);
3559 } else if (pipeline->device->physical_device->rad_info.chip_class == GFX9) {
3560 bin_size = radv_gfx9_compute_bin_size(pipeline, pCreateInfo);
3561 } else
3562 unreachable("Unhandled generation for binning bin size calculation");
3563
3564 if (pipeline->device->pbb_allowed && bin_size.width && bin_size.height) {
3565 struct radv_binning_settings settings =
3566 radv_get_binning_settings(pipeline->device->physical_device);
3567
3568 bool disable_start_of_prim = true;
3569 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
3570
3571 const struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3572
3573 if (pipeline->device->dfsm_allowed && ps &&
3574 !ps->info.ps.can_discard &&
3575 !ps->info.ps.writes_memory &&
3576 blend->cb_target_enabled_4bit) {
3577 db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_AUTO);
3578 disable_start_of_prim = (blend->blend_enable_4bit & blend->cb_target_enabled_4bit) != 0;
3579 }
3580
3581 const uint32_t pa_sc_binner_cntl_0 =
3582 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
3583 S_028C44_BIN_SIZE_X(bin_size.width == 16) |
3584 S_028C44_BIN_SIZE_Y(bin_size.height == 16) |
3585 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size.width, 32)) - 5) |
3586 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size.height, 32)) - 5) |
3587 S_028C44_CONTEXT_STATES_PER_BIN(settings.context_states_per_bin - 1) |
3588 S_028C44_PERSISTENT_STATES_PER_BIN(settings.persistent_states_per_bin - 1) |
3589 S_028C44_DISABLE_START_OF_PRIM(disable_start_of_prim) |
3590 S_028C44_FPOVS_PER_BATCH(settings.fpovs_per_batch) |
3591 S_028C44_OPTIMAL_BIN_SELECTION(1);
3592
3593 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
3594 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
3595 } else
3596 radv_pipeline_generate_disabled_binning_state(ctx_cs, pipeline, pCreateInfo);
3597 }
3598
3599
3600 static void
3601 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf *ctx_cs,
3602 struct radv_pipeline *pipeline,
3603 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3604 const struct radv_graphics_pipeline_create_info *extra)
3605 {
3606 const VkPipelineDepthStencilStateCreateInfo *vkds = radv_pipeline_get_depth_stencil_state(pCreateInfo);
3607 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3608 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3609 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3610 struct radv_render_pass_attachment *attachment = NULL;
3611 uint32_t db_depth_control = 0;
3612 uint32_t db_render_control = 0, db_render_override2 = 0;
3613 uint32_t db_render_override = 0;
3614
3615 if (subpass->depth_stencil_attachment)
3616 attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3617
3618 bool has_depth_attachment = attachment && vk_format_is_depth(attachment->format);
3619 bool has_stencil_attachment = attachment && vk_format_is_stencil(attachment->format);
3620
3621 if (vkds && has_depth_attachment) {
3622 db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
3623 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
3624 S_028800_ZFUNC(vkds->depthCompareOp) |
3625 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
3626
3627 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
3628 db_render_override2 |= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment->samples > 2);
3629
3630 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10_3)
3631 db_render_override2 |= S_028010_CENTROID_COMPUTATION_MODE_GFX103(2);
3632 }
3633
3634 if (has_stencil_attachment && vkds && vkds->stencilTestEnable) {
3635 db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
3636 db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
3637
3638 db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
3639 }
3640
3641 if (attachment && extra) {
3642 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
3643 db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
3644
3645 db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->resummarize_enable);
3646 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->depth_compress_disable);
3647 db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->stencil_compress_disable);
3648 db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
3649 db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
3650 }
3651
3652 db_render_override |= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3653 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
3654
3655 if (!pCreateInfo->pRasterizationState->depthClampEnable &&
3656 ps->info.ps.writes_z) {
3657 /* From VK_EXT_depth_range_unrestricted spec:
3658 *
3659 * "The behavior described in Primitive Clipping still applies.
3660 * If depth clamping is disabled the depth values are still
3661 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
3662 * depth clamping is enabled the above equation is ignored and
3663 * the depth values are instead clamped to the VkViewport
3664 * minDepth and maxDepth values, which in the case of this
3665 * extension can be outside of the 0.0 to 1.0 range."
3666 */
3667 db_render_override |= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
3668 }
3669
3670 radeon_set_context_reg(ctx_cs, R_028000_DB_RENDER_CONTROL, db_render_control);
3671 radeon_set_context_reg(ctx_cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
3672 radeon_set_context_reg(ctx_cs, R_028010_DB_RENDER_OVERRIDE2, db_render_override2);
3673
3674 pipeline->graphics.db_depth_control = db_depth_control;
3675 }
3676
3677 static void
3678 radv_pipeline_generate_blend_state(struct radeon_cmdbuf *ctx_cs,
3679 struct radv_pipeline *pipeline,
3680 const struct radv_blend_state *blend)
3681 {
3682 radeon_set_context_reg_seq(ctx_cs, R_028780_CB_BLEND0_CONTROL, 8);
3683 radeon_emit_array(ctx_cs, blend->cb_blend_control,
3684 8);
3685 radeon_set_context_reg(ctx_cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control);
3686 radeon_set_context_reg(ctx_cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask);
3687
3688 if (pipeline->device->physical_device->rad_info.has_rbplus) {
3689
3690 radeon_set_context_reg_seq(ctx_cs, R_028760_SX_MRT0_BLEND_OPT, 8);
3691 radeon_emit_array(ctx_cs, blend->sx_mrt_blend_opt, 8);
3692 }
3693
3694 radeon_set_context_reg(ctx_cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
3695
3696 radeon_set_context_reg(ctx_cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
3697 radeon_set_context_reg(ctx_cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
3698
3699 pipeline->graphics.col_format = blend->spi_shader_col_format;
3700 pipeline->graphics.cb_target_mask = blend->cb_target_mask;
3701 }
3702
3703 static const VkConservativeRasterizationModeEXT
3704 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo *pCreateInfo)
3705 {
3706 const VkPipelineRasterizationConservativeStateCreateInfoEXT *conservative_raster =
3707 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT);
3708
3709 if (!conservative_raster)
3710 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT;
3711 return conservative_raster->conservativeRasterizationMode;
3712 }
3713
3714 static void
3715 radv_pipeline_generate_raster_state(struct radeon_cmdbuf *ctx_cs,
3716 struct radv_pipeline *pipeline,
3717 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3718 {
3719 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
3720 const VkConservativeRasterizationModeEXT mode =
3721 radv_get_conservative_raster_mode(vkraster);
3722 uint32_t pa_sc_conservative_rast = S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
3723 bool depth_clip_disable = vkraster->depthClampEnable;
3724
3725 const VkPipelineRasterizationDepthClipStateCreateInfoEXT *depth_clip_state =
3726 vk_find_struct_const(vkraster->pNext, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT);
3727 if (depth_clip_state) {
3728 depth_clip_disable = !depth_clip_state->depthClipEnable;
3729 }
3730
3731 radeon_set_context_reg(ctx_cs, R_028810_PA_CL_CLIP_CNTL,
3732 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
3733 S_028810_ZCLIP_NEAR_DISABLE(depth_clip_disable ? 1 : 0) |
3734 S_028810_ZCLIP_FAR_DISABLE(depth_clip_disable ? 1 : 0) |
3735 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
3736 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
3737
3738 pipeline->graphics.pa_su_sc_mode_cntl =
3739 S_028814_FACE(vkraster->frontFace) |
3740 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
3741 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
3742 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
3743 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
3744 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
3745 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
3746 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
3747 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0);
3748
3749 radeon_set_context_reg(ctx_cs, R_028BDC_PA_SC_LINE_CNTL,
3750 S_028BDC_DX10_DIAMOND_TEST_ENA(1));
3751
3752 /* Conservative rasterization. */
3753 if (mode != VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT) {
3754 struct radv_multisample_state *ms = &pipeline->graphics.ms;
3755
3756 ms->pa_sc_aa_config |= S_028BE0_AA_MASK_CENTROID_DTMN(1);
3757 ms->db_eqaa |= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
3758 S_028804_OVERRASTERIZATION_AMOUNT(4);
3759
3760 pa_sc_conservative_rast = S_028C4C_PREZ_AA_MASK_ENABLE(1) |
3761 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
3762 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
3763
3764 if (mode == VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT) {
3765 pa_sc_conservative_rast |=
3766 S_028C4C_OVER_RAST_ENABLE(1) |
3767 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
3768 S_028C4C_UNDER_RAST_ENABLE(0) |
3769 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
3770 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
3771 } else {
3772 assert(mode == VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT);
3773 pa_sc_conservative_rast |=
3774 S_028C4C_OVER_RAST_ENABLE(0) |
3775 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
3776 S_028C4C_UNDER_RAST_ENABLE(1) |
3777 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
3778 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
3779 }
3780 }
3781
3782 radeon_set_context_reg(ctx_cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
3783 pa_sc_conservative_rast);
3784 }
3785
3786
3787 static void
3788 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf *ctx_cs,
3789 struct radv_pipeline *pipeline)
3790 {
3791 struct radv_multisample_state *ms = &pipeline->graphics.ms;
3792
3793 radeon_set_context_reg_seq(ctx_cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3794 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[0]);
3795 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[1]);
3796
3797 radeon_set_context_reg(ctx_cs, R_028804_DB_EQAA, ms->db_eqaa);
3798 radeon_set_context_reg(ctx_cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
3799 radeon_set_context_reg(ctx_cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
3800 radeon_set_context_reg(ctx_cs, R_028BE0_PA_SC_AA_CONFIG, ms->pa_sc_aa_config);
3801
3802 /* The exclusion bits can be set to improve rasterization efficiency
3803 * if no sample lies on the pixel boundary (-8 sample offset). It's
3804 * currently always TRUE because the driver doesn't support 16 samples.
3805 */
3806 bool exclusion = pipeline->device->physical_device->rad_info.chip_class >= GFX7;
3807 radeon_set_context_reg(ctx_cs, R_02882C_PA_SU_PRIM_FILTER_CNTL,
3808 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
3809 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
3810
3811 /* GFX9: Flush DFSM when the AA mode changes. */
3812 if (pipeline->device->dfsm_allowed) {
3813 radeon_emit(ctx_cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3814 radeon_emit(ctx_cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3815 }
3816 }
3817
3818 static void
3819 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf *ctx_cs,
3820 struct radv_pipeline *pipeline)
3821 {
3822 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3823 const struct radv_shader_variant *vs =
3824 pipeline->shaders[MESA_SHADER_TESS_EVAL] ?
3825 pipeline->shaders[MESA_SHADER_TESS_EVAL] :
3826 pipeline->shaders[MESA_SHADER_VERTEX];
3827 unsigned vgt_primitiveid_en = 0;
3828 uint32_t vgt_gs_mode = 0;
3829
3830 if (radv_pipeline_has_ngg(pipeline))
3831 return;
3832
3833 if (radv_pipeline_has_gs(pipeline)) {
3834 const struct radv_shader_variant *gs =
3835 pipeline->shaders[MESA_SHADER_GEOMETRY];
3836
3837 vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out,
3838 pipeline->device->physical_device->rad_info.chip_class);
3839 } else if (outinfo->export_prim_id || vs->info.uses_prim_id) {
3840 vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
3841 vgt_primitiveid_en |= S_028A84_PRIMITIVEID_EN(1);
3842 }
3843
3844 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN, vgt_primitiveid_en);
3845 radeon_set_context_reg(ctx_cs, R_028A40_VGT_GS_MODE, vgt_gs_mode);
3846 }
3847
3848 static void
3849 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs,
3850 struct radeon_cmdbuf *cs,
3851 struct radv_pipeline *pipeline,
3852 struct radv_shader_variant *shader)
3853 {
3854 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3855
3856 radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
3857 radeon_emit(cs, va >> 8);
3858 radeon_emit(cs, S_00B124_MEM_BASE(va >> 40));
3859 radeon_emit(cs, shader->config.rsrc1);
3860 radeon_emit(cs, shader->config.rsrc2);
3861
3862 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3863 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3864 clip_dist_mask = outinfo->clip_dist_mask;
3865 cull_dist_mask = outinfo->cull_dist_mask;
3866 total_mask = clip_dist_mask | cull_dist_mask;
3867 bool misc_vec_ena = outinfo->writes_pointsize ||
3868 outinfo->writes_layer ||
3869 outinfo->writes_viewport_index;
3870 unsigned spi_vs_out_config, nparams;
3871
3872 /* VS is required to export at least one param. */
3873 nparams = MAX2(outinfo->param_exports, 1);
3874 spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
3875
3876 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3877 spi_vs_out_config |= S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0);
3878 }
3879
3880 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG, spi_vs_out_config);
3881
3882 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
3883 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
3884 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
3885 V_02870C_SPI_SHADER_4COMP :
3886 V_02870C_SPI_SHADER_NONE) |
3887 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
3888 V_02870C_SPI_SHADER_4COMP :
3889 V_02870C_SPI_SHADER_NONE) |
3890 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
3891 V_02870C_SPI_SHADER_4COMP :
3892 V_02870C_SPI_SHADER_NONE));
3893
3894 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
3895 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
3896 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
3897 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
3898 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
3899 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
3900 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
3901 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
3902 S_02881C_BYPASS_PRIM_RATE_COMBINER_GFX103(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3) |
3903 cull_dist_mask << 8 |
3904 clip_dist_mask);
3905
3906 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
3907 radeon_set_context_reg(ctx_cs, R_028AB4_VGT_REUSE_OFF,
3908 outinfo->writes_viewport_index);
3909 }
3910
3911 static void
3912 radv_pipeline_generate_hw_es(struct radeon_cmdbuf *cs,
3913 struct radv_pipeline *pipeline,
3914 struct radv_shader_variant *shader)
3915 {
3916 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3917
3918 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
3919 radeon_emit(cs, va >> 8);
3920 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3921 radeon_emit(cs, shader->config.rsrc1);
3922 radeon_emit(cs, shader->config.rsrc2);
3923 }
3924
3925 static void
3926 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf *cs,
3927 struct radv_pipeline *pipeline,
3928 struct radv_shader_variant *shader,
3929 const struct radv_tessellation_state *tess)
3930 {
3931 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3932 uint32_t rsrc2 = shader->config.rsrc2;
3933
3934 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
3935 radeon_emit(cs, va >> 8);
3936 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
3937
3938 rsrc2 |= S_00B52C_LDS_SIZE(tess->lds_size);
3939 if (pipeline->device->physical_device->rad_info.chip_class == GFX7 &&
3940 pipeline->device->physical_device->rad_info.family != CHIP_HAWAII)
3941 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
3942
3943 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
3944 radeon_emit(cs, shader->config.rsrc1);
3945 radeon_emit(cs, rsrc2);
3946 }
3947
3948 static void
3949 radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs,
3950 struct radeon_cmdbuf *cs,
3951 struct radv_pipeline *pipeline,
3952 struct radv_shader_variant *shader)
3953 {
3954 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3955 gl_shader_stage es_type =
3956 radv_pipeline_has_tess(pipeline) ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
3957 struct radv_shader_variant *es =
3958 es_type == MESA_SHADER_TESS_EVAL ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX];
3959 const struct gfx10_ngg_info *ngg_state = &shader->info.ngg_info;
3960
3961 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
3962 radeon_emit(cs, va >> 8);
3963 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3964 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
3965 radeon_emit(cs, shader->config.rsrc1);
3966 radeon_emit(cs, shader->config.rsrc2);
3967
3968 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3969 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3970 clip_dist_mask = outinfo->clip_dist_mask;
3971 cull_dist_mask = outinfo->cull_dist_mask;
3972 total_mask = clip_dist_mask | cull_dist_mask;
3973 bool misc_vec_ena = outinfo->writes_pointsize ||
3974 outinfo->writes_layer ||
3975 outinfo->writes_viewport_index;
3976 bool es_enable_prim_id = outinfo->export_prim_id ||
3977 (es && es->info.uses_prim_id);
3978 bool break_wave_at_eoi = false;
3979 unsigned ge_cntl;
3980 unsigned nparams;
3981
3982 if (es_type == MESA_SHADER_TESS_EVAL) {
3983 struct radv_shader_variant *gs =
3984 pipeline->shaders[MESA_SHADER_GEOMETRY];
3985
3986 if (es_enable_prim_id || (gs && gs->info.uses_prim_id))
3987 break_wave_at_eoi = true;
3988 }
3989
3990 nparams = MAX2(outinfo->param_exports, 1);
3991 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG,
3992 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
3993 S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0));
3994
3995 radeon_set_context_reg(ctx_cs, R_028708_SPI_SHADER_IDX_FORMAT,
3996 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP));
3997 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
3998 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
3999 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
4000 V_02870C_SPI_SHADER_4COMP :
4001 V_02870C_SPI_SHADER_NONE) |
4002 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
4003 V_02870C_SPI_SHADER_4COMP :
4004 V_02870C_SPI_SHADER_NONE) |
4005 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
4006 V_02870C_SPI_SHADER_4COMP :
4007 V_02870C_SPI_SHADER_NONE));
4008
4009 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
4010 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
4011 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
4012 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
4013 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
4014 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
4015 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
4016 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
4017 S_02881C_BYPASS_PRIM_RATE_COMBINER_GFX103(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3) |
4018 cull_dist_mask << 8 |
4019 clip_dist_mask);
4020
4021 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN,
4022 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
4023 S_028A84_NGG_DISABLE_PROVOK_REUSE(outinfo->export_prim_id));
4024
4025 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
4026 ngg_state->vgt_esgs_ring_itemsize);
4027
4028 /* NGG specific registers. */
4029 struct radv_shader_variant *gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
4030 uint32_t gs_num_invocations = gs ? gs->info.gs.invocations : 1;
4031
4032 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
4033 S_028A44_ES_VERTS_PER_SUBGRP(ngg_state->hw_max_esverts) |
4034 S_028A44_GS_PRIMS_PER_SUBGRP(ngg_state->max_gsprims) |
4035 S_028A44_GS_INST_PRIMS_IN_SUBGRP(ngg_state->max_gsprims * gs_num_invocations));
4036 radeon_set_context_reg(ctx_cs, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
4037 S_0287FC_MAX_VERTS_PER_SUBGROUP(ngg_state->max_out_verts));
4038 radeon_set_context_reg(ctx_cs, R_028B4C_GE_NGG_SUBGRP_CNTL,
4039 S_028B4C_PRIM_AMP_FACTOR(ngg_state->prim_amp_factor) |
4040 S_028B4C_THDS_PER_SUBGRP(0)); /* for fast launch */
4041 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
4042 S_028B90_CNT(gs_num_invocations) |
4043 S_028B90_ENABLE(gs_num_invocations > 1) |
4044 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(ngg_state->max_vert_out_per_gs_instance));
4045
4046 /* User edge flags are set by the pos exports. If user edge flags are
4047 * not used, we must use hw-generated edge flags and pass them via
4048 * the prim export to prevent drawing lines on internal edges of
4049 * decomposed primitives (such as quads) with polygon mode = lines.
4050 *
4051 * TODO: We should combine hw-generated edge flags with user edge
4052 * flags in the shader.
4053 */
4054 radeon_set_context_reg(ctx_cs, R_028838_PA_CL_NGG_CNTL,
4055 S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline) &&
4056 !radv_pipeline_has_gs(pipeline)) |
4057 /* Reuse for NGG. */
4058 S_028838_VERTEX_REUSE_DEPTH_GFX103(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3 ? 30 : 0));
4059
4060 ge_cntl = S_03096C_PRIM_GRP_SIZE(ngg_state->max_gsprims) |
4061 S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
4062 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
4063
4064 /* Bug workaround for a possible hang with non-tessellation cases.
4065 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
4066 *
4067 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
4068 */
4069 if (pipeline->device->physical_device->rad_info.chip_class == GFX10 &&
4070 !radv_pipeline_has_tess(pipeline) &&
4071 ngg_state->hw_max_esverts != 256) {
4072 ge_cntl &= C_03096C_VERT_GRP_SIZE;
4073
4074 if (ngg_state->hw_max_esverts > 5) {
4075 ge_cntl |= S_03096C_VERT_GRP_SIZE(ngg_state->hw_max_esverts - 5);
4076 }
4077 }
4078
4079 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL, ge_cntl);
4080 }
4081
4082 static void
4083 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf *cs,
4084 struct radv_pipeline *pipeline,
4085 struct radv_shader_variant *shader,
4086 const struct radv_tessellation_state *tess)
4087 {
4088 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
4089
4090 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
4091 unsigned hs_rsrc2 = shader->config.rsrc2;
4092
4093 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4094 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX10(tess->lds_size);
4095 } else {
4096 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX9(tess->lds_size);
4097 }
4098
4099 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4100 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
4101 radeon_emit(cs, va >> 8);
4102 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
4103 } else {
4104 radeon_set_sh_reg_seq(cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
4105 radeon_emit(cs, va >> 8);
4106 radeon_emit(cs, S_00B414_MEM_BASE(va >> 40));
4107 }
4108
4109 radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
4110 radeon_emit(cs, shader->config.rsrc1);
4111 radeon_emit(cs, hs_rsrc2);
4112 } else {
4113 radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
4114 radeon_emit(cs, va >> 8);
4115 radeon_emit(cs, S_00B424_MEM_BASE(va >> 40));
4116 radeon_emit(cs, shader->config.rsrc1);
4117 radeon_emit(cs, shader->config.rsrc2);
4118 }
4119 }
4120
4121 static void
4122 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf *ctx_cs,
4123 struct radeon_cmdbuf *cs,
4124 struct radv_pipeline *pipeline,
4125 const struct radv_tessellation_state *tess)
4126 {
4127 struct radv_shader_variant *vs;
4128
4129 /* Skip shaders merged into HS/GS */
4130 vs = pipeline->shaders[MESA_SHADER_VERTEX];
4131 if (!vs)
4132 return;
4133
4134 if (vs->info.vs.as_ls)
4135 radv_pipeline_generate_hw_ls(cs, pipeline, vs, tess);
4136 else if (vs->info.vs.as_es)
4137 radv_pipeline_generate_hw_es(cs, pipeline, vs);
4138 else if (vs->info.is_ngg)
4139 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, vs);
4140 else
4141 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, vs);
4142 }
4143
4144 static void
4145 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf *ctx_cs,
4146 struct radeon_cmdbuf *cs,
4147 struct radv_pipeline *pipeline,
4148 const struct radv_tessellation_state *tess)
4149 {
4150 if (!radv_pipeline_has_tess(pipeline))
4151 return;
4152
4153 struct radv_shader_variant *tes, *tcs;
4154
4155 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
4156 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
4157
4158 if (tes) {
4159 if (tes->info.is_ngg) {
4160 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, tes);
4161 } else if (tes->info.tes.as_es)
4162 radv_pipeline_generate_hw_es(cs, pipeline, tes);
4163 else
4164 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, tes);
4165 }
4166
4167 radv_pipeline_generate_hw_hs(cs, pipeline, tcs, tess);
4168
4169 radeon_set_context_reg(ctx_cs, R_028B6C_VGT_TF_PARAM,
4170 tess->tf_param);
4171
4172 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7)
4173 radeon_set_context_reg_idx(ctx_cs, R_028B58_VGT_LS_HS_CONFIG, 2,
4174 tess->ls_hs_config);
4175 else
4176 radeon_set_context_reg(ctx_cs, R_028B58_VGT_LS_HS_CONFIG,
4177 tess->ls_hs_config);
4178
4179 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 &&
4180 !radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) {
4181 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
4182 S_028A44_ES_VERTS_PER_SUBGRP(250) |
4183 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
4184 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
4185 }
4186 }
4187
4188 static void
4189 radv_pipeline_generate_hw_gs(struct radeon_cmdbuf *ctx_cs,
4190 struct radeon_cmdbuf *cs,
4191 struct radv_pipeline *pipeline,
4192 struct radv_shader_variant *gs)
4193 {
4194 const struct gfx9_gs_info *gs_state = &gs->info.gs_ring_info;
4195 unsigned gs_max_out_vertices;
4196 uint8_t *num_components;
4197 uint8_t max_stream;
4198 unsigned offset;
4199 uint64_t va;
4200
4201 gs_max_out_vertices = gs->info.gs.vertices_out;
4202 max_stream = gs->info.gs.max_stream;
4203 num_components = gs->info.gs.num_stream_output_components;
4204
4205 offset = num_components[0] * gs_max_out_vertices;
4206
4207 radeon_set_context_reg_seq(ctx_cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
4208 radeon_emit(ctx_cs, offset);
4209 if (max_stream >= 1)
4210 offset += num_components[1] * gs_max_out_vertices;
4211 radeon_emit(ctx_cs, offset);
4212 if (max_stream >= 2)
4213 offset += num_components[2] * gs_max_out_vertices;
4214 radeon_emit(ctx_cs, offset);
4215 if (max_stream >= 3)
4216 offset += num_components[3] * gs_max_out_vertices;
4217 radeon_set_context_reg(ctx_cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
4218
4219 radeon_set_context_reg_seq(ctx_cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
4220 radeon_emit(ctx_cs, num_components[0]);
4221 radeon_emit(ctx_cs, (max_stream >= 1) ? num_components[1] : 0);
4222 radeon_emit(ctx_cs, (max_stream >= 2) ? num_components[2] : 0);
4223 radeon_emit(ctx_cs, (max_stream >= 3) ? num_components[3] : 0);
4224
4225 uint32_t gs_num_invocations = gs->info.gs.invocations;
4226 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
4227 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
4228 S_028B90_ENABLE(gs_num_invocations > 0));
4229
4230 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
4231 gs_state->vgt_esgs_ring_itemsize);
4232
4233 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
4234
4235 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
4236 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4237 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
4238 radeon_emit(cs, va >> 8);
4239 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
4240 } else {
4241 radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
4242 radeon_emit(cs, va >> 8);
4243 radeon_emit(cs, S_00B214_MEM_BASE(va >> 40));
4244 }
4245
4246 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
4247 radeon_emit(cs, gs->config.rsrc1);
4248 radeon_emit(cs, gs->config.rsrc2 | S_00B22C_LDS_SIZE(gs_state->lds_size));
4249
4250 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL, gs_state->vgt_gs_onchip_cntl);
4251 radeon_set_context_reg(ctx_cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, gs_state->vgt_gs_max_prims_per_subgroup);
4252 } else {
4253 radeon_set_sh_reg_seq(cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
4254 radeon_emit(cs, va >> 8);
4255 radeon_emit(cs, S_00B224_MEM_BASE(va >> 40));
4256 radeon_emit(cs, gs->config.rsrc1);
4257 radeon_emit(cs, gs->config.rsrc2);
4258 }
4259
4260 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, pipeline->gs_copy_shader);
4261 }
4262
4263 static void
4264 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf *ctx_cs,
4265 struct radeon_cmdbuf *cs,
4266 struct radv_pipeline *pipeline)
4267 {
4268 struct radv_shader_variant *gs;
4269
4270 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
4271 if (!gs)
4272 return;
4273
4274 if (gs->info.is_ngg)
4275 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, gs);
4276 else
4277 radv_pipeline_generate_hw_gs(ctx_cs, cs, pipeline, gs);
4278
4279 radeon_set_context_reg(ctx_cs, R_028B38_VGT_GS_MAX_VERT_OUT,
4280 gs->info.gs.vertices_out);
4281 }
4282
4283 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade,
4284 bool explicit, bool float16)
4285 {
4286 uint32_t ps_input_cntl;
4287 if (offset <= AC_EXP_PARAM_OFFSET_31) {
4288 ps_input_cntl = S_028644_OFFSET(offset);
4289 if (flat_shade || explicit)
4290 ps_input_cntl |= S_028644_FLAT_SHADE(1);
4291 if (explicit) {
4292 /* Force parameter cache to be read in passthrough
4293 * mode.
4294 */
4295 ps_input_cntl |= S_028644_OFFSET(1 << 5);
4296 }
4297 if (float16) {
4298 ps_input_cntl |= S_028644_FP16_INTERP_MODE(1) |
4299 S_028644_ATTR0_VALID(1);
4300 }
4301 } else {
4302 /* The input is a DEFAULT_VAL constant. */
4303 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
4304 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
4305 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
4306 ps_input_cntl = S_028644_OFFSET(0x20) |
4307 S_028644_DEFAULT_VAL(offset);
4308 }
4309 return ps_input_cntl;
4310 }
4311
4312 static void
4313 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf *ctx_cs,
4314 struct radv_pipeline *pipeline)
4315 {
4316 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4317 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
4318 uint32_t ps_input_cntl[32];
4319
4320 unsigned ps_offset = 0;
4321
4322 if (ps->info.ps.prim_id_input) {
4323 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
4324 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
4325 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false, false);
4326 ++ps_offset;
4327 }
4328 }
4329
4330 if (ps->info.ps.layer_input ||
4331 ps->info.needs_multiview_view_index) {
4332 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
4333 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
4334 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false, false);
4335 else
4336 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true, false, false);
4337 ++ps_offset;
4338 }
4339
4340 if (ps->info.ps.viewport_index_input) {
4341 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VIEWPORT];
4342 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
4343 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false, false);
4344 else
4345 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true, false, false);
4346 ++ps_offset;
4347 }
4348
4349 if (ps->info.ps.has_pcoord) {
4350 unsigned val;
4351 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
4352 ps_input_cntl[ps_offset] = val;
4353 ps_offset++;
4354 }
4355
4356 if (ps->info.ps.num_input_clips_culls) {
4357 unsigned vs_offset;
4358
4359 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST0];
4360 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
4361 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false, false);
4362 ++ps_offset;
4363 }
4364
4365 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST1];
4366 if (vs_offset != AC_EXP_PARAM_UNDEFINED &&
4367 ps->info.ps.num_input_clips_culls > 4) {
4368 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false, false);
4369 ++ps_offset;
4370 }
4371 }
4372
4373 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.ps.input_mask; ++i) {
4374 unsigned vs_offset;
4375 bool flat_shade;
4376 bool explicit;
4377 bool float16;
4378 if (!(ps->info.ps.input_mask & (1u << i)))
4379 continue;
4380
4381 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
4382 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
4383 ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
4384 ++ps_offset;
4385 continue;
4386 }
4387
4388 flat_shade = !!(ps->info.ps.flat_shaded_mask & (1u << ps_offset));
4389 explicit = !!(ps->info.ps.explicit_shaded_mask & (1u << ps_offset));
4390 float16 = !!(ps->info.ps.float16_shaded_mask & (1u << ps_offset));
4391
4392 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade, explicit, float16);
4393 ++ps_offset;
4394 }
4395
4396 if (ps_offset) {
4397 radeon_set_context_reg_seq(ctx_cs, R_028644_SPI_PS_INPUT_CNTL_0, ps_offset);
4398 for (unsigned i = 0; i < ps_offset; i++) {
4399 radeon_emit(ctx_cs, ps_input_cntl[i]);
4400 }
4401 }
4402 }
4403
4404 static uint32_t
4405 radv_compute_db_shader_control(const struct radv_device *device,
4406 const struct radv_pipeline *pipeline,
4407 const struct radv_shader_variant *ps)
4408 {
4409 unsigned conservative_z_export = V_02880C_EXPORT_ANY_Z;
4410 unsigned z_order;
4411 if (ps->info.ps.early_fragment_test || !ps->info.ps.writes_memory)
4412 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
4413 else
4414 z_order = V_02880C_LATE_Z;
4415
4416 if (ps->info.ps.depth_layout == FRAG_DEPTH_LAYOUT_GREATER)
4417 conservative_z_export = V_02880C_EXPORT_GREATER_THAN_Z;
4418 else if (ps->info.ps.depth_layout == FRAG_DEPTH_LAYOUT_LESS)
4419 conservative_z_export = V_02880C_EXPORT_LESS_THAN_Z;
4420
4421 bool disable_rbplus = device->physical_device->rad_info.has_rbplus &&
4422 !device->physical_device->rad_info.rbplus_allowed;
4423
4424 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
4425 * but this appears to break Project Cars (DXVK). See
4426 * https://bugs.freedesktop.org/show_bug.cgi?id=109401
4427 */
4428 bool mask_export_enable = ps->info.ps.writes_sample_mask;
4429
4430 return S_02880C_Z_EXPORT_ENABLE(ps->info.ps.writes_z) |
4431 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.ps.writes_stencil) |
4432 S_02880C_KILL_ENABLE(!!ps->info.ps.can_discard) |
4433 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable) |
4434 S_02880C_CONSERVATIVE_Z_EXPORT(conservative_z_export) |
4435 S_02880C_Z_ORDER(z_order) |
4436 S_02880C_DEPTH_BEFORE_SHADER(ps->info.ps.early_fragment_test) |
4437 S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps->info.ps.post_depth_coverage) |
4438 S_02880C_EXEC_ON_HIER_FAIL(ps->info.ps.writes_memory) |
4439 S_02880C_EXEC_ON_NOOP(ps->info.ps.writes_memory) |
4440 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus);
4441 }
4442
4443 static void
4444 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf *ctx_cs,
4445 struct radeon_cmdbuf *cs,
4446 struct radv_pipeline *pipeline)
4447 {
4448 struct radv_shader_variant *ps;
4449 uint64_t va;
4450 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
4451
4452 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4453 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
4454
4455 radeon_set_sh_reg_seq(cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
4456 radeon_emit(cs, va >> 8);
4457 radeon_emit(cs, S_00B024_MEM_BASE(va >> 40));
4458 radeon_emit(cs, ps->config.rsrc1);
4459 radeon_emit(cs, ps->config.rsrc2);
4460
4461 radeon_set_context_reg(ctx_cs, R_02880C_DB_SHADER_CONTROL,
4462 radv_compute_db_shader_control(pipeline->device,
4463 pipeline, ps));
4464
4465 radeon_set_context_reg(ctx_cs, R_0286CC_SPI_PS_INPUT_ENA,
4466 ps->config.spi_ps_input_ena);
4467
4468 radeon_set_context_reg(ctx_cs, R_0286D0_SPI_PS_INPUT_ADDR,
4469 ps->config.spi_ps_input_addr);
4470
4471 radeon_set_context_reg(ctx_cs, R_0286D8_SPI_PS_IN_CONTROL,
4472 S_0286D8_NUM_INTERP(ps->info.ps.num_interp) |
4473 S_0286D8_PS_W32_EN(ps->info.wave_size == 32));
4474
4475 radeon_set_context_reg(ctx_cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl);
4476
4477 radeon_set_context_reg(ctx_cs, R_028710_SPI_SHADER_Z_FORMAT,
4478 ac_get_spi_shader_z_format(ps->info.ps.writes_z,
4479 ps->info.ps.writes_stencil,
4480 ps->info.ps.writes_sample_mask));
4481
4482 if (pipeline->device->dfsm_allowed) {
4483 /* optimise this? */
4484 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
4485 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
4486 }
4487 }
4488
4489 static void
4490 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf *ctx_cs,
4491 struct radv_pipeline *pipeline)
4492 {
4493 if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10 ||
4494 pipeline->device->physical_device->rad_info.chip_class >= GFX10)
4495 return;
4496
4497 unsigned vtx_reuse_depth = 30;
4498 if (radv_pipeline_has_tess(pipeline) &&
4499 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
4500 vtx_reuse_depth = 14;
4501 }
4502 radeon_set_context_reg(ctx_cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
4503 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth));
4504 }
4505
4506 static void
4507 radv_pipeline_generate_vgt_shader_config(struct radeon_cmdbuf *ctx_cs,
4508 const struct radv_pipeline *pipeline)
4509 {
4510 uint32_t stages = 0;
4511 if (radv_pipeline_has_tess(pipeline)) {
4512 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
4513 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
4514
4515 if (radv_pipeline_has_gs(pipeline))
4516 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
4517 S_028B54_GS_EN(1);
4518 else if (radv_pipeline_has_ngg(pipeline))
4519 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
4520 else
4521 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
4522 } else if (radv_pipeline_has_gs(pipeline)) {
4523 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
4524 S_028B54_GS_EN(1);
4525 } else if (radv_pipeline_has_ngg(pipeline)) {
4526 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
4527 }
4528
4529 if (radv_pipeline_has_ngg(pipeline)) {
4530 stages |= S_028B54_PRIMGEN_EN(1);
4531 if (pipeline->streamout_shader)
4532 stages |= S_028B54_NGG_WAVE_ID_EN(1);
4533 if (radv_pipeline_has_ngg_passthrough(pipeline))
4534 stages |= S_028B54_PRIMGEN_PASSTHRU_EN(1);
4535 } else if (radv_pipeline_has_gs(pipeline)) {
4536 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
4537 }
4538
4539 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
4540 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
4541
4542 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4543 uint8_t hs_size = 64, gs_size = 64, vs_size = 64;
4544
4545 if (radv_pipeline_has_tess(pipeline))
4546 hs_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.wave_size;
4547
4548 if (pipeline->shaders[MESA_SHADER_GEOMETRY]) {
4549 vs_size = gs_size = pipeline->shaders[MESA_SHADER_GEOMETRY]->info.wave_size;
4550 if (pipeline->gs_copy_shader)
4551 vs_size = pipeline->gs_copy_shader->info.wave_size;
4552 } else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
4553 vs_size = pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.wave_size;
4554 else if (pipeline->shaders[MESA_SHADER_VERTEX])
4555 vs_size = pipeline->shaders[MESA_SHADER_VERTEX]->info.wave_size;
4556
4557 if (radv_pipeline_has_ngg(pipeline))
4558 gs_size = vs_size;
4559
4560 /* legacy GS only supports Wave64 */
4561 stages |= S_028B54_HS_W32_EN(hs_size == 32 ? 1 : 0) |
4562 S_028B54_GS_W32_EN(gs_size == 32 ? 1 : 0) |
4563 S_028B54_VS_W32_EN(vs_size == 32 ? 1 : 0);
4564 }
4565
4566 radeon_set_context_reg(ctx_cs, R_028B54_VGT_SHADER_STAGES_EN, stages);
4567 }
4568
4569 static void
4570 radv_pipeline_generate_cliprect_rule(struct radeon_cmdbuf *ctx_cs,
4571 const VkGraphicsPipelineCreateInfo *pCreateInfo)
4572 {
4573 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
4574 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
4575 uint32_t cliprect_rule = 0;
4576
4577 if (!discard_rectangle_info) {
4578 cliprect_rule = 0xffff;
4579 } else {
4580 for (unsigned i = 0; i < (1u << MAX_DISCARD_RECTANGLES); ++i) {
4581 /* Interpret i as a bitmask, and then set the bit in
4582 * the mask if that combination of rectangles in which
4583 * the pixel is contained should pass the cliprect
4584 * test.
4585 */
4586 unsigned relevant_subset = i & ((1u << discard_rectangle_info->discardRectangleCount) - 1);
4587
4588 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT &&
4589 !relevant_subset)
4590 continue;
4591
4592 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT &&
4593 relevant_subset)
4594 continue;
4595
4596 cliprect_rule |= 1u << i;
4597 }
4598 }
4599
4600 radeon_set_context_reg(ctx_cs, R_02820C_PA_SC_CLIPRECT_RULE, cliprect_rule);
4601 }
4602
4603 static void
4604 gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf *ctx_cs,
4605 struct radv_pipeline *pipeline)
4606 {
4607 bool break_wave_at_eoi = false;
4608 unsigned primgroup_size;
4609 unsigned vertgroup_size = 256; /* 256 = disable vertex grouping */
4610
4611 if (radv_pipeline_has_tess(pipeline)) {
4612 primgroup_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
4613 } else if (radv_pipeline_has_gs(pipeline)) {
4614 const struct gfx9_gs_info *gs_state =
4615 &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs_ring_info;
4616 unsigned vgt_gs_onchip_cntl = gs_state->vgt_gs_onchip_cntl;
4617 primgroup_size = G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl);
4618 } else {
4619 primgroup_size = 128; /* recommended without a GS and tess */
4620 }
4621
4622 if (radv_pipeline_has_tess(pipeline)) {
4623 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
4624 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.uses_prim_id)
4625 break_wave_at_eoi = true;
4626 }
4627
4628 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL,
4629 S_03096C_PRIM_GRP_SIZE(primgroup_size) |
4630 S_03096C_VERT_GRP_SIZE(vertgroup_size) |
4631 S_03096C_PACKET_TO_ONE_PA(0) /* line stipple */ |
4632 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi));
4633 }
4634
4635 static void
4636 radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
4637 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4638 const struct radv_graphics_pipeline_create_info *extra,
4639 const struct radv_blend_state *blend,
4640 const struct radv_tessellation_state *tess,
4641 unsigned gs_out)
4642 {
4643 struct radeon_cmdbuf *ctx_cs = &pipeline->ctx_cs;
4644 struct radeon_cmdbuf *cs = &pipeline->cs;
4645
4646 cs->max_dw = 64;
4647 ctx_cs->max_dw = 256;
4648 cs->buf = malloc(4 * (cs->max_dw + ctx_cs->max_dw));
4649 ctx_cs->buf = cs->buf + cs->max_dw;
4650
4651 radv_pipeline_generate_depth_stencil_state(ctx_cs, pipeline, pCreateInfo, extra);
4652 radv_pipeline_generate_blend_state(ctx_cs, pipeline, blend);
4653 radv_pipeline_generate_raster_state(ctx_cs, pipeline, pCreateInfo);
4654 radv_pipeline_generate_multisample_state(ctx_cs, pipeline);
4655 radv_pipeline_generate_vgt_gs_mode(ctx_cs, pipeline);
4656 radv_pipeline_generate_vertex_shader(ctx_cs, cs, pipeline, tess);
4657 radv_pipeline_generate_tess_shaders(ctx_cs, cs, pipeline, tess);
4658 radv_pipeline_generate_geometry_shader(ctx_cs, cs, pipeline);
4659 radv_pipeline_generate_fragment_shader(ctx_cs, cs, pipeline);
4660 radv_pipeline_generate_ps_inputs(ctx_cs, pipeline);
4661 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs, pipeline);
4662 radv_pipeline_generate_binning_state(ctx_cs, pipeline, pCreateInfo, blend);
4663 radv_pipeline_generate_vgt_shader_config(ctx_cs, pipeline);
4664 radv_pipeline_generate_cliprect_rule(ctx_cs, pCreateInfo);
4665
4666 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 && !radv_pipeline_has_ngg(pipeline))
4667 gfx10_pipeline_generate_ge_cntl(ctx_cs, pipeline);
4668
4669 radeon_set_context_reg(ctx_cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out);
4670
4671 pipeline->ctx_cs_hash = _mesa_hash_data(ctx_cs->buf, ctx_cs->cdw * 4);
4672
4673 assert(ctx_cs->cdw <= ctx_cs->max_dw);
4674 assert(cs->cdw <= cs->max_dw);
4675 }
4676
4677 static struct radv_ia_multi_vgt_param_helpers
4678 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline)
4679 {
4680 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param = {0};
4681 const struct radv_device *device = pipeline->device;
4682
4683 if (radv_pipeline_has_tess(pipeline))
4684 ia_multi_vgt_param.primgroup_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
4685 else if (radv_pipeline_has_gs(pipeline))
4686 ia_multi_vgt_param.primgroup_size = 64;
4687 else
4688 ia_multi_vgt_param.primgroup_size = 128; /* recommended without a GS */
4689
4690 /* GS requirement. */
4691 ia_multi_vgt_param.partial_es_wave = false;
4692 if (radv_pipeline_has_gs(pipeline) && device->physical_device->rad_info.chip_class <= GFX8)
4693 if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3)
4694 ia_multi_vgt_param.partial_es_wave = true;
4695
4696 ia_multi_vgt_param.ia_switch_on_eoi = false;
4697 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.prim_id_input)
4698 ia_multi_vgt_param.ia_switch_on_eoi = true;
4699 if (radv_pipeline_has_gs(pipeline) &&
4700 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.uses_prim_id)
4701 ia_multi_vgt_param.ia_switch_on_eoi = true;
4702 if (radv_pipeline_has_tess(pipeline)) {
4703 /* SWITCH_ON_EOI must be set if PrimID is used. */
4704 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
4705 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.uses_prim_id)
4706 ia_multi_vgt_param.ia_switch_on_eoi = true;
4707 }
4708
4709 ia_multi_vgt_param.partial_vs_wave = false;
4710 if (radv_pipeline_has_tess(pipeline)) {
4711 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
4712 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
4713 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
4714 device->physical_device->rad_info.family == CHIP_BONAIRE) &&
4715 radv_pipeline_has_gs(pipeline))
4716 ia_multi_vgt_param.partial_vs_wave = true;
4717 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
4718 if (device->physical_device->rad_info.has_distributed_tess) {
4719 if (radv_pipeline_has_gs(pipeline)) {
4720 if (device->physical_device->rad_info.chip_class <= GFX8)
4721 ia_multi_vgt_param.partial_es_wave = true;
4722 } else {
4723 ia_multi_vgt_param.partial_vs_wave = true;
4724 }
4725 }
4726 }
4727
4728 if (radv_pipeline_has_gs(pipeline)) {
4729 /* On these chips there is the possibility of a hang if the
4730 * pipeline uses a GS and partial_vs_wave is not set.
4731 *
4732 * This mostly does not hit 4-SE chips, as those typically set
4733 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
4734 * with GS due to another workaround.
4735 *
4736 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
4737 */
4738 if (device->physical_device->rad_info.family == CHIP_TONGA ||
4739 device->physical_device->rad_info.family == CHIP_FIJI ||
4740 device->physical_device->rad_info.family == CHIP_POLARIS10 ||
4741 device->physical_device->rad_info.family == CHIP_POLARIS11 ||
4742 device->physical_device->rad_info.family == CHIP_POLARIS12 ||
4743 device->physical_device->rad_info.family == CHIP_VEGAM) {
4744 ia_multi_vgt_param.partial_vs_wave = true;
4745 }
4746 }
4747
4748 ia_multi_vgt_param.base =
4749 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param.primgroup_size - 1) |
4750 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
4751 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == GFX8 ? 2 : 0) |
4752 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
4753 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
4754
4755 return ia_multi_vgt_param;
4756 }
4757
4758
4759 static void
4760 radv_compute_vertex_input_state(struct radv_pipeline *pipeline,
4761 const VkGraphicsPipelineCreateInfo *pCreateInfo)
4762 {
4763 const VkPipelineVertexInputStateCreateInfo *vi_info =
4764 pCreateInfo->pVertexInputState;
4765
4766 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
4767 const VkVertexInputBindingDescription *desc =
4768 &vi_info->pVertexBindingDescriptions[i];
4769
4770 pipeline->binding_stride[desc->binding] = desc->stride;
4771 pipeline->num_vertex_bindings =
4772 MAX2(pipeline->num_vertex_bindings, desc->binding + 1);
4773 }
4774 }
4775
4776 static struct radv_shader_variant *
4777 radv_pipeline_get_streamout_shader(struct radv_pipeline *pipeline)
4778 {
4779 int i;
4780
4781 for (i = MESA_SHADER_GEOMETRY; i >= MESA_SHADER_VERTEX; i--) {
4782 struct radv_shader_variant *shader =
4783 radv_get_shader(pipeline, i);
4784
4785 if (shader && shader->info.so.num_outputs > 0)
4786 return shader;
4787 }
4788
4789 return NULL;
4790 }
4791
4792 static VkResult
4793 radv_pipeline_init(struct radv_pipeline *pipeline,
4794 struct radv_device *device,
4795 struct radv_pipeline_cache *cache,
4796 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4797 const struct radv_graphics_pipeline_create_info *extra)
4798 {
4799 VkResult result;
4800 bool has_view_index = false;
4801
4802 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
4803 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
4804 if (subpass->view_mask)
4805 has_view_index = true;
4806
4807 pipeline->device = device;
4808 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
4809 assert(pipeline->layout);
4810
4811 struct radv_blend_state blend = radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
4812
4813 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
4814 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
4815 radv_init_feedback(creation_feedback);
4816
4817 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
4818
4819 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
4820 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
4821 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
4822 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
4823 pStages[stage] = &pCreateInfo->pStages[i];
4824 if(creation_feedback)
4825 stage_feedbacks[stage] = &creation_feedback->pPipelineStageCreationFeedbacks[i];
4826 }
4827
4828 struct radv_pipeline_key key = radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &blend, has_view_index);
4829
4830 result = radv_create_shaders(pipeline, device, cache, &key, pStages,
4831 pCreateInfo->flags, pipeline_feedback,
4832 stage_feedbacks);
4833 if (result != VK_SUCCESS)
4834 return result;
4835
4836 pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
4837 radv_pipeline_init_multisample_state(pipeline, &blend, pCreateInfo);
4838 uint32_t gs_out;
4839
4840 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
4841
4842 if (radv_pipeline_has_gs(pipeline)) {
4843 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
4844 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
4845 } else if (radv_pipeline_has_tess(pipeline)) {
4846 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.point_mode)
4847 gs_out = V_028A6C_OUTPRIM_TYPE_POINTLIST;
4848 else
4849 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.primitive_mode);
4850 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
4851 } else {
4852 gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
4853 }
4854 if (extra && extra->use_rectlist) {
4855 gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
4856 pipeline->graphics.can_use_guardband = true;
4857 if (radv_pipeline_has_ngg(pipeline))
4858 gs_out = V_028A6C_VGT_OUT_RECT_V0;
4859 }
4860 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
4861
4862 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo, extra);
4863
4864 /* Ensure that some export memory is always allocated, for two reasons:
4865 *
4866 * 1) Correctness: The hardware ignores the EXEC mask if no export
4867 * memory is allocated, so KILL and alpha test do not work correctly
4868 * without this.
4869 * 2) Performance: Every shader needs at least a NULL export, even when
4870 * it writes no color/depth output. The NULL export instruction
4871 * stalls without this setting.
4872 *
4873 * Don't add this to CB_SHADER_MASK.
4874 *
4875 * GFX10 supports pixel shaders without exports by setting both the
4876 * color and Z formats to SPI_SHADER_ZERO. The hw will skip export
4877 * instructions if any are present.
4878 */
4879 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4880 if ((pipeline->device->physical_device->rad_info.chip_class <= GFX9 ||
4881 ps->info.ps.can_discard) &&
4882 !blend.spi_shader_col_format) {
4883 if (!ps->info.ps.writes_z &&
4884 !ps->info.ps.writes_stencil &&
4885 !ps->info.ps.writes_sample_mask)
4886 blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
4887 }
4888
4889 blend.cb_shader_mask = ps->info.ps.cb_shader_mask;
4890
4891 if (extra &&
4892 (extra->custom_blend_mode == V_028808_CB_ELIMINATE_FAST_CLEAR ||
4893 extra->custom_blend_mode == V_028808_CB_FMASK_DECOMPRESS ||
4894 extra->custom_blend_mode == V_028808_CB_DCC_DECOMPRESS ||
4895 extra->custom_blend_mode == V_028808_CB_RESOLVE)) {
4896 /* According to the CB spec states, CB_SHADER_MASK should be
4897 * set to enable writes to all four channels of MRT0.
4898 */
4899 blend.cb_shader_mask = 0xf;
4900 }
4901
4902 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
4903 if (pipeline->shaders[i]) {
4904 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
4905 }
4906 }
4907
4908 if (radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) {
4909 struct radv_shader_variant *gs =
4910 pipeline->shaders[MESA_SHADER_GEOMETRY];
4911
4912 calculate_gs_ring_sizes(pipeline, &gs->info.gs_ring_info);
4913 }
4914
4915 struct radv_tessellation_state tess = {0};
4916 if (radv_pipeline_has_tess(pipeline)) {
4917 pipeline->graphics.tess_patch_control_points =
4918 pCreateInfo->pTessellationState->patchControlPoints;
4919 tess = calculate_tess_state(pipeline, pCreateInfo);
4920 }
4921
4922 pipeline->graphics.ia_multi_vgt_param = radv_compute_ia_multi_vgt_param_helpers(pipeline);
4923
4924 radv_compute_vertex_input_state(pipeline, pCreateInfo);
4925
4926 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
4927 pipeline->user_data_0[i] = radv_pipeline_stage_to_user_data_0(pipeline, i, device->physical_device->rad_info.chip_class);
4928
4929 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
4930 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
4931 if (loc->sgpr_idx != -1) {
4932 pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX];
4933 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
4934 if (radv_get_shader(pipeline, MESA_SHADER_VERTEX)->info.vs.needs_draw_id)
4935 pipeline->graphics.vtx_emit_num = 3;
4936 else
4937 pipeline->graphics.vtx_emit_num = 2;
4938 }
4939
4940 /* Find the last vertex shader stage that eventually uses streamout. */
4941 pipeline->streamout_shader = radv_pipeline_get_streamout_shader(pipeline);
4942
4943 result = radv_pipeline_scratch_init(device, pipeline);
4944 radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend, &tess, gs_out);
4945
4946 return result;
4947 }
4948
4949 VkResult
4950 radv_graphics_pipeline_create(
4951 VkDevice _device,
4952 VkPipelineCache _cache,
4953 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4954 const struct radv_graphics_pipeline_create_info *extra,
4955 const VkAllocationCallbacks *pAllocator,
4956 VkPipeline *pPipeline)
4957 {
4958 RADV_FROM_HANDLE(radv_device, device, _device);
4959 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
4960 struct radv_pipeline *pipeline;
4961 VkResult result;
4962
4963 pipeline = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*pipeline), 8,
4964 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4965 if (pipeline == NULL)
4966 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4967
4968 vk_object_base_init(&device->vk, &pipeline->base,
4969 VK_OBJECT_TYPE_PIPELINE);
4970
4971 result = radv_pipeline_init(pipeline, device, cache,
4972 pCreateInfo, extra);
4973 if (result != VK_SUCCESS) {
4974 radv_pipeline_destroy(device, pipeline, pAllocator);
4975 return result;
4976 }
4977
4978 *pPipeline = radv_pipeline_to_handle(pipeline);
4979
4980 return VK_SUCCESS;
4981 }
4982
4983 VkResult radv_CreateGraphicsPipelines(
4984 VkDevice _device,
4985 VkPipelineCache pipelineCache,
4986 uint32_t count,
4987 const VkGraphicsPipelineCreateInfo* pCreateInfos,
4988 const VkAllocationCallbacks* pAllocator,
4989 VkPipeline* pPipelines)
4990 {
4991 VkResult result = VK_SUCCESS;
4992 unsigned i = 0;
4993
4994 for (; i < count; i++) {
4995 VkResult r;
4996 r = radv_graphics_pipeline_create(_device,
4997 pipelineCache,
4998 &pCreateInfos[i],
4999 NULL, pAllocator, &pPipelines[i]);
5000 if (r != VK_SUCCESS) {
5001 result = r;
5002 pPipelines[i] = VK_NULL_HANDLE;
5003
5004 if (pCreateInfos[i].flags & VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT)
5005 break;
5006 }
5007 }
5008
5009 for (; i < count; ++i)
5010 pPipelines[i] = VK_NULL_HANDLE;
5011
5012 return result;
5013 }
5014
5015 static void
5016 radv_pipeline_generate_hw_cs(struct radeon_cmdbuf *cs,
5017 struct radv_pipeline *pipeline)
5018 {
5019 struct radv_shader_variant *shader = pipeline->shaders[MESA_SHADER_COMPUTE];
5020 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
5021 struct radv_device *device = pipeline->device;
5022
5023 radeon_set_sh_reg_seq(cs, R_00B830_COMPUTE_PGM_LO, 2);
5024 radeon_emit(cs, va >> 8);
5025 radeon_emit(cs, S_00B834_DATA(va >> 40));
5026
5027 radeon_set_sh_reg_seq(cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
5028 radeon_emit(cs, shader->config.rsrc1);
5029 radeon_emit(cs, shader->config.rsrc2);
5030 if (device->physical_device->rad_info.chip_class >= GFX10) {
5031 radeon_set_sh_reg(cs, R_00B8A0_COMPUTE_PGM_RSRC3, shader->config.rsrc3);
5032 }
5033 }
5034
5035 static void
5036 radv_pipeline_generate_compute_state(struct radeon_cmdbuf *cs,
5037 struct radv_pipeline *pipeline)
5038 {
5039 struct radv_shader_variant *shader = pipeline->shaders[MESA_SHADER_COMPUTE];
5040 struct radv_device *device = pipeline->device;
5041 unsigned threads_per_threadgroup;
5042 unsigned threadgroups_per_cu = 1;
5043 unsigned waves_per_threadgroup;
5044 unsigned max_waves_per_sh = 0;
5045
5046 /* Calculate best compute resource limits. */
5047 threads_per_threadgroup = shader->info.cs.block_size[0] *
5048 shader->info.cs.block_size[1] *
5049 shader->info.cs.block_size[2];
5050 waves_per_threadgroup = DIV_ROUND_UP(threads_per_threadgroup,
5051 shader->info.wave_size);
5052
5053 if (device->physical_device->rad_info.chip_class >= GFX10 &&
5054 waves_per_threadgroup == 1)
5055 threadgroups_per_cu = 2;
5056
5057 radeon_set_sh_reg(cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
5058 ac_get_compute_resource_limits(&device->physical_device->rad_info,
5059 waves_per_threadgroup,
5060 max_waves_per_sh,
5061 threadgroups_per_cu));
5062
5063 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
5064 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(shader->info.cs.block_size[0]));
5065 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(shader->info.cs.block_size[1]));
5066 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(shader->info.cs.block_size[2]));
5067 }
5068
5069 static void
5070 radv_compute_generate_pm4(struct radv_pipeline *pipeline)
5071 {
5072 struct radv_device *device = pipeline->device;
5073 struct radeon_cmdbuf *cs = &pipeline->cs;
5074
5075 cs->max_dw = device->physical_device->rad_info.chip_class >= GFX10 ? 19 : 16;
5076 cs->buf = malloc(cs->max_dw * 4);
5077
5078 radv_pipeline_generate_hw_cs(cs, pipeline);
5079 radv_pipeline_generate_compute_state(cs, pipeline);
5080
5081 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
5082 }
5083
5084 static struct radv_pipeline_key
5085 radv_generate_compute_pipeline_key(struct radv_pipeline *pipeline,
5086 const VkComputePipelineCreateInfo *pCreateInfo)
5087 {
5088 const VkPipelineShaderStageCreateInfo *stage = &pCreateInfo->stage;
5089 struct radv_pipeline_key key;
5090 memset(&key, 0, sizeof(key));
5091
5092 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
5093 key.optimisations_disabled = 1;
5094
5095 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT *subgroup_size =
5096 vk_find_struct_const(stage->pNext,
5097 PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT);
5098
5099 if (subgroup_size) {
5100 assert(subgroup_size->requiredSubgroupSize == 32 ||
5101 subgroup_size->requiredSubgroupSize == 64);
5102 key.compute_subgroup_size = subgroup_size->requiredSubgroupSize;
5103 }
5104
5105 return key;
5106 }
5107
5108 static VkResult radv_compute_pipeline_create(
5109 VkDevice _device,
5110 VkPipelineCache _cache,
5111 const VkComputePipelineCreateInfo* pCreateInfo,
5112 const VkAllocationCallbacks* pAllocator,
5113 VkPipeline* pPipeline)
5114 {
5115 RADV_FROM_HANDLE(radv_device, device, _device);
5116 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
5117 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
5118 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
5119 struct radv_pipeline *pipeline;
5120 VkResult result;
5121
5122 pipeline = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*pipeline), 8,
5123 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5124 if (pipeline == NULL)
5125 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5126
5127 vk_object_base_init(&device->vk, &pipeline->base,
5128 VK_OBJECT_TYPE_PIPELINE);
5129
5130 pipeline->device = device;
5131 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
5132 assert(pipeline->layout);
5133
5134 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
5135 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
5136 radv_init_feedback(creation_feedback);
5137
5138 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
5139 if (creation_feedback)
5140 stage_feedbacks[MESA_SHADER_COMPUTE] = &creation_feedback->pPipelineStageCreationFeedbacks[0];
5141
5142 pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
5143
5144 struct radv_pipeline_key key =
5145 radv_generate_compute_pipeline_key(pipeline, pCreateInfo);
5146
5147 result = radv_create_shaders(pipeline, device, cache, &key, pStages,
5148 pCreateInfo->flags, pipeline_feedback,
5149 stage_feedbacks);
5150 if (result != VK_SUCCESS) {
5151 radv_pipeline_destroy(device, pipeline, pAllocator);
5152 return result;
5153 }
5154
5155 pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
5156 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
5157 result = radv_pipeline_scratch_init(device, pipeline);
5158 if (result != VK_SUCCESS) {
5159 radv_pipeline_destroy(device, pipeline, pAllocator);
5160 return result;
5161 }
5162
5163 radv_compute_generate_pm4(pipeline);
5164
5165 *pPipeline = radv_pipeline_to_handle(pipeline);
5166
5167 return VK_SUCCESS;
5168 }
5169
5170 VkResult radv_CreateComputePipelines(
5171 VkDevice _device,
5172 VkPipelineCache pipelineCache,
5173 uint32_t count,
5174 const VkComputePipelineCreateInfo* pCreateInfos,
5175 const VkAllocationCallbacks* pAllocator,
5176 VkPipeline* pPipelines)
5177 {
5178 VkResult result = VK_SUCCESS;
5179
5180 unsigned i = 0;
5181 for (; i < count; i++) {
5182 VkResult r;
5183 r = radv_compute_pipeline_create(_device, pipelineCache,
5184 &pCreateInfos[i],
5185 pAllocator, &pPipelines[i]);
5186 if (r != VK_SUCCESS) {
5187 result = r;
5188 pPipelines[i] = VK_NULL_HANDLE;
5189
5190 if (pCreateInfos[i].flags & VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT)
5191 break;
5192 }
5193 }
5194
5195 for (; i < count; ++i)
5196 pPipelines[i] = VK_NULL_HANDLE;
5197
5198 return result;
5199 }
5200
5201
5202 static uint32_t radv_get_executable_count(const struct radv_pipeline *pipeline)
5203 {
5204 uint32_t ret = 0;
5205 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
5206 if (!pipeline->shaders[i])
5207 continue;
5208
5209 if (i == MESA_SHADER_GEOMETRY &&
5210 !radv_pipeline_has_ngg(pipeline)) {
5211 ret += 2u;
5212 } else {
5213 ret += 1u;
5214 }
5215
5216 }
5217 return ret;
5218 }
5219
5220 static struct radv_shader_variant *
5221 radv_get_shader_from_executable_index(const struct radv_pipeline *pipeline, int index, gl_shader_stage *stage)
5222 {
5223 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
5224 if (!pipeline->shaders[i])
5225 continue;
5226 if (!index) {
5227 *stage = i;
5228 return pipeline->shaders[i];
5229 }
5230
5231 --index;
5232
5233 if (i == MESA_SHADER_GEOMETRY &&
5234 !radv_pipeline_has_ngg(pipeline)) {
5235 if (!index) {
5236 *stage = i;
5237 return pipeline->gs_copy_shader;
5238 }
5239 --index;
5240 }
5241 }
5242
5243 *stage = -1;
5244 return NULL;
5245 }
5246
5247 /* Basically strlcpy (which does not exist on linux) specialized for
5248 * descriptions. */
5249 static void desc_copy(char *desc, const char *src) {
5250 int len = strlen(src);
5251 assert(len < VK_MAX_DESCRIPTION_SIZE);
5252 memcpy(desc, src, len);
5253 memset(desc + len, 0, VK_MAX_DESCRIPTION_SIZE - len);
5254 }
5255
5256 VkResult radv_GetPipelineExecutablePropertiesKHR(
5257 VkDevice _device,
5258 const VkPipelineInfoKHR* pPipelineInfo,
5259 uint32_t* pExecutableCount,
5260 VkPipelineExecutablePropertiesKHR* pProperties)
5261 {
5262 RADV_FROM_HANDLE(radv_pipeline, pipeline, pPipelineInfo->pipeline);
5263 const uint32_t total_count = radv_get_executable_count(pipeline);
5264
5265 if (!pProperties) {
5266 *pExecutableCount = total_count;
5267 return VK_SUCCESS;
5268 }
5269
5270 const uint32_t count = MIN2(total_count, *pExecutableCount);
5271 for (unsigned i = 0, executable_idx = 0;
5272 i < MESA_SHADER_STAGES && executable_idx < count; ++i) {
5273 if (!pipeline->shaders[i])
5274 continue;
5275 pProperties[executable_idx].stages = mesa_to_vk_shader_stage(i);
5276 const char *name = NULL;
5277 const char *description = NULL;
5278 switch(i) {
5279 case MESA_SHADER_VERTEX:
5280 name = "Vertex Shader";
5281 description = "Vulkan Vertex Shader";
5282 break;
5283 case MESA_SHADER_TESS_CTRL:
5284 if (!pipeline->shaders[MESA_SHADER_VERTEX]) {
5285 pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT;
5286 name = "Vertex + Tessellation Control Shaders";
5287 description = "Combined Vulkan Vertex and Tessellation Control Shaders";
5288 } else {
5289 name = "Tessellation Control Shader";
5290 description = "Vulkan Tessellation Control Shader";
5291 }
5292 break;
5293 case MESA_SHADER_TESS_EVAL:
5294 name = "Tessellation Evaluation Shader";
5295 description = "Vulkan Tessellation Evaluation Shader";
5296 break;
5297 case MESA_SHADER_GEOMETRY:
5298 if (radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_TESS_EVAL]) {
5299 pProperties[executable_idx].stages |= VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT;
5300 name = "Tessellation Evaluation + Geometry Shaders";
5301 description = "Combined Vulkan Tessellation Evaluation and Geometry Shaders";
5302 } else if (!radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_VERTEX]) {
5303 pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT;
5304 name = "Vertex + Geometry Shader";
5305 description = "Combined Vulkan Vertex and Geometry Shaders";
5306 } else {
5307 name = "Geometry Shader";
5308 description = "Vulkan Geometry Shader";
5309 }
5310 break;
5311 case MESA_SHADER_FRAGMENT:
5312 name = "Fragment Shader";
5313 description = "Vulkan Fragment Shader";
5314 break;
5315 case MESA_SHADER_COMPUTE:
5316 name = "Compute Shader";
5317 description = "Vulkan Compute Shader";
5318 break;
5319 }
5320
5321 pProperties[executable_idx].subgroupSize = pipeline->shaders[i]->info.wave_size;
5322 desc_copy(pProperties[executable_idx].name, name);
5323 desc_copy(pProperties[executable_idx].description, description);
5324
5325 ++executable_idx;
5326 if (i == MESA_SHADER_GEOMETRY &&
5327 !radv_pipeline_has_ngg(pipeline)) {
5328 assert(pipeline->gs_copy_shader);
5329 if (executable_idx >= count)
5330 break;
5331
5332 pProperties[executable_idx].stages = VK_SHADER_STAGE_GEOMETRY_BIT;
5333 pProperties[executable_idx].subgroupSize = 64;
5334 desc_copy(pProperties[executable_idx].name, "GS Copy Shader");
5335 desc_copy(pProperties[executable_idx].description,
5336 "Extra shader stage that loads the GS output ringbuffer into the rasterizer");
5337
5338 ++executable_idx;
5339 }
5340 }
5341
5342 VkResult result = *pExecutableCount < total_count ? VK_INCOMPLETE : VK_SUCCESS;
5343 *pExecutableCount = count;
5344 return result;
5345 }
5346
5347 VkResult radv_GetPipelineExecutableStatisticsKHR(
5348 VkDevice _device,
5349 const VkPipelineExecutableInfoKHR* pExecutableInfo,
5350 uint32_t* pStatisticCount,
5351 VkPipelineExecutableStatisticKHR* pStatistics)
5352 {
5353 RADV_FROM_HANDLE(radv_device, device, _device);
5354 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
5355 gl_shader_stage stage;
5356 struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
5357
5358 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
5359 unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
5360 unsigned max_waves = radv_get_max_waves(device, shader, stage);
5361
5362 VkPipelineExecutableStatisticKHR *s = pStatistics;
5363 VkPipelineExecutableStatisticKHR *end = s + (pStatistics ? *pStatisticCount : 0);
5364 VkResult result = VK_SUCCESS;
5365
5366 if (s < end) {
5367 desc_copy(s->name, "SGPRs");
5368 desc_copy(s->description, "Number of SGPR registers allocated per subgroup");
5369 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5370 s->value.u64 = shader->config.num_sgprs;
5371 }
5372 ++s;
5373
5374 if (s < end) {
5375 desc_copy(s->name, "VGPRs");
5376 desc_copy(s->description, "Number of VGPR registers allocated per subgroup");
5377 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5378 s->value.u64 = shader->config.num_vgprs;
5379 }
5380 ++s;
5381
5382 if (s < end) {
5383 desc_copy(s->name, "Spilled SGPRs");
5384 desc_copy(s->description, "Number of SGPR registers spilled per subgroup");
5385 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5386 s->value.u64 = shader->config.spilled_sgprs;
5387 }
5388 ++s;
5389
5390 if (s < end) {
5391 desc_copy(s->name, "Spilled VGPRs");
5392 desc_copy(s->description, "Number of VGPR registers spilled per subgroup");
5393 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5394 s->value.u64 = shader->config.spilled_vgprs;
5395 }
5396 ++s;
5397
5398 if (s < end) {
5399 desc_copy(s->name, "PrivMem VGPRs");
5400 desc_copy(s->description, "Number of VGPRs stored in private memory per subgroup");
5401 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5402 s->value.u64 = shader->info.private_mem_vgprs;
5403 }
5404 ++s;
5405
5406 if (s < end) {
5407 desc_copy(s->name, "Code size");
5408 desc_copy(s->description, "Code size in bytes");
5409 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5410 s->value.u64 = shader->exec_size;
5411 }
5412 ++s;
5413
5414 if (s < end) {
5415 desc_copy(s->name, "LDS size");
5416 desc_copy(s->description, "LDS size in bytes per workgroup");
5417 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5418 s->value.u64 = shader->config.lds_size * lds_increment;
5419 }
5420 ++s;
5421
5422 if (s < end) {
5423 desc_copy(s->name, "Scratch size");
5424 desc_copy(s->description, "Private memory in bytes per subgroup");
5425 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5426 s->value.u64 = shader->config.scratch_bytes_per_wave;
5427 }
5428 ++s;
5429
5430 if (s < end) {
5431 desc_copy(s->name, "Subgroups per SIMD");
5432 desc_copy(s->description, "The maximum number of subgroups in flight on a SIMD unit");
5433 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5434 s->value.u64 = max_waves;
5435 }
5436 ++s;
5437
5438 if (shader->statistics) {
5439 for (unsigned i = 0; i < shader->statistics->count; i++) {
5440 struct radv_compiler_statistic_info *info = &shader->statistics->infos[i];
5441 uint32_t value = shader->statistics->values[i];
5442 if (s < end) {
5443 desc_copy(s->name, info->name);
5444 desc_copy(s->description, info->desc);
5445 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5446 s->value.u64 = value;
5447 }
5448 ++s;
5449 }
5450 }
5451
5452 if (!pStatistics)
5453 *pStatisticCount = s - pStatistics;
5454 else if (s > end) {
5455 *pStatisticCount = end - pStatistics;
5456 result = VK_INCOMPLETE;
5457 } else {
5458 *pStatisticCount = s - pStatistics;
5459 }
5460
5461 return result;
5462 }
5463
5464 static VkResult radv_copy_representation(void *data, size_t *data_size, const char *src)
5465 {
5466 size_t total_size = strlen(src) + 1;
5467
5468 if (!data) {
5469 *data_size = total_size;
5470 return VK_SUCCESS;
5471 }
5472
5473 size_t size = MIN2(total_size, *data_size);
5474
5475 memcpy(data, src, size);
5476 if (size)
5477 *((char*)data + size - 1) = 0;
5478 return size < total_size ? VK_INCOMPLETE : VK_SUCCESS;
5479 }
5480
5481 VkResult radv_GetPipelineExecutableInternalRepresentationsKHR(
5482 VkDevice device,
5483 const VkPipelineExecutableInfoKHR* pExecutableInfo,
5484 uint32_t* pInternalRepresentationCount,
5485 VkPipelineExecutableInternalRepresentationKHR* pInternalRepresentations)
5486 {
5487 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
5488 gl_shader_stage stage;
5489 struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
5490
5491 VkPipelineExecutableInternalRepresentationKHR *p = pInternalRepresentations;
5492 VkPipelineExecutableInternalRepresentationKHR *end = p + (pInternalRepresentations ? *pInternalRepresentationCount : 0);
5493 VkResult result = VK_SUCCESS;
5494 /* optimized NIR */
5495 if (p < end) {
5496 p->isText = true;
5497 desc_copy(p->name, "NIR Shader(s)");
5498 desc_copy(p->description, "The optimized NIR shader(s)");
5499 if (radv_copy_representation(p->pData, &p->dataSize, shader->nir_string) != VK_SUCCESS)
5500 result = VK_INCOMPLETE;
5501 }
5502 ++p;
5503
5504 /* backend IR */
5505 if (p < end) {
5506 p->isText = true;
5507 if (pipeline->device->physical_device->use_llvm) {
5508 desc_copy(p->name, "LLVM IR");
5509 desc_copy(p->description, "The LLVM IR after some optimizations");
5510 } else {
5511 desc_copy(p->name, "ACO IR");
5512 desc_copy(p->description, "The ACO IR after some optimizations");
5513 }
5514 if (radv_copy_representation(p->pData, &p->dataSize, shader->ir_string) != VK_SUCCESS)
5515 result = VK_INCOMPLETE;
5516 }
5517 ++p;
5518
5519 /* Disassembler */
5520 if (p < end) {
5521 p->isText = true;
5522 desc_copy(p->name, "Assembly");
5523 desc_copy(p->description, "Final Assembly");
5524 if (radv_copy_representation(p->pData, &p->dataSize, shader->disasm_string) != VK_SUCCESS)
5525 result = VK_INCOMPLETE;
5526 }
5527 ++p;
5528
5529 if (!pInternalRepresentations)
5530 *pInternalRepresentationCount = p - pInternalRepresentations;
5531 else if(p > end) {
5532 result = VK_INCOMPLETE;
5533 *pInternalRepresentationCount = end - pInternalRepresentations;
5534 } else {
5535 *pInternalRepresentationCount = p - pInternalRepresentations;
5536 }
5537
5538 return result;
5539 }