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radv: add tessellation support to variant code.
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "radv_private.h"
30 #include "nir/nir.h"
31 #include "nir/nir_builder.h"
32 #include "spirv/nir_spirv.h"
33
34 #include <llvm-c/Core.h>
35 #include <llvm-c/TargetMachine.h>
36
37 #include "sid.h"
38 #include "r600d_common.h"
39 #include "ac_binary.h"
40 #include "ac_llvm_util.h"
41 #include "ac_nir_to_llvm.h"
42 #include "vk_format.h"
43 #include "util/debug.h"
44
45 void radv_shader_variant_destroy(struct radv_device *device,
46 struct radv_shader_variant *variant);
47
48 static const struct nir_shader_compiler_options nir_options = {
49 .vertex_id_zero_based = true,
50 .lower_scmp = true,
51 .lower_flrp32 = true,
52 .lower_fsat = true,
53 .lower_pack_snorm_2x16 = true,
54 .lower_pack_snorm_4x8 = true,
55 .lower_pack_unorm_2x16 = true,
56 .lower_pack_unorm_4x8 = true,
57 .lower_unpack_snorm_2x16 = true,
58 .lower_unpack_snorm_4x8 = true,
59 .lower_unpack_unorm_2x16 = true,
60 .lower_unpack_unorm_4x8 = true,
61 .lower_extract_byte = true,
62 .lower_extract_word = true,
63 };
64
65 VkResult radv_CreateShaderModule(
66 VkDevice _device,
67 const VkShaderModuleCreateInfo* pCreateInfo,
68 const VkAllocationCallbacks* pAllocator,
69 VkShaderModule* pShaderModule)
70 {
71 RADV_FROM_HANDLE(radv_device, device, _device);
72 struct radv_shader_module *module;
73
74 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
75 assert(pCreateInfo->flags == 0);
76
77 module = vk_alloc2(&device->alloc, pAllocator,
78 sizeof(*module) + pCreateInfo->codeSize, 8,
79 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
80 if (module == NULL)
81 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
82
83 module->nir = NULL;
84 module->size = pCreateInfo->codeSize;
85 memcpy(module->data, pCreateInfo->pCode, module->size);
86
87 _mesa_sha1_compute(module->data, module->size, module->sha1);
88
89 *pShaderModule = radv_shader_module_to_handle(module);
90
91 return VK_SUCCESS;
92 }
93
94 void radv_DestroyShaderModule(
95 VkDevice _device,
96 VkShaderModule _module,
97 const VkAllocationCallbacks* pAllocator)
98 {
99 RADV_FROM_HANDLE(radv_device, device, _device);
100 RADV_FROM_HANDLE(radv_shader_module, module, _module);
101
102 if (!module)
103 return;
104
105 vk_free2(&device->alloc, pAllocator, module);
106 }
107
108
109 static void
110 radv_pipeline_destroy(struct radv_device *device,
111 struct radv_pipeline *pipeline,
112 const VkAllocationCallbacks* allocator)
113 {
114 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
115 if (pipeline->shaders[i])
116 radv_shader_variant_destroy(device, pipeline->shaders[i]);
117
118 if (pipeline->gs_copy_shader)
119 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
120
121 vk_free2(&device->alloc, allocator, pipeline);
122 }
123
124 void radv_DestroyPipeline(
125 VkDevice _device,
126 VkPipeline _pipeline,
127 const VkAllocationCallbacks* pAllocator)
128 {
129 RADV_FROM_HANDLE(radv_device, device, _device);
130 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
131
132 if (!_pipeline)
133 return;
134
135 radv_pipeline_destroy(device, pipeline, pAllocator);
136 }
137
138
139 static void
140 radv_optimize_nir(struct nir_shader *shader)
141 {
142 bool progress;
143
144 do {
145 progress = false;
146
147 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
148 NIR_PASS_V(shader, nir_lower_alu_to_scalar);
149 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
150
151 NIR_PASS(progress, shader, nir_copy_prop);
152 NIR_PASS(progress, shader, nir_opt_remove_phis);
153 NIR_PASS(progress, shader, nir_opt_dce);
154 NIR_PASS(progress, shader, nir_opt_dead_cf);
155 NIR_PASS(progress, shader, nir_opt_cse);
156 NIR_PASS(progress, shader, nir_opt_peephole_select, 8);
157 NIR_PASS(progress, shader, nir_opt_algebraic);
158 NIR_PASS(progress, shader, nir_opt_constant_folding);
159 NIR_PASS(progress, shader, nir_opt_undef);
160 NIR_PASS(progress, shader, nir_opt_conditional_discard);
161 } while (progress);
162 }
163
164 static nir_shader *
165 radv_shader_compile_to_nir(struct radv_device *device,
166 struct radv_shader_module *module,
167 const char *entrypoint_name,
168 gl_shader_stage stage,
169 const VkSpecializationInfo *spec_info,
170 bool dump)
171 {
172 if (strcmp(entrypoint_name, "main") != 0) {
173 radv_finishme("Multiple shaders per module not really supported");
174 }
175
176 nir_shader *nir;
177 nir_function *entry_point;
178 if (module->nir) {
179 /* Some things such as our meta clear/blit code will give us a NIR
180 * shader directly. In that case, we just ignore the SPIR-V entirely
181 * and just use the NIR shader */
182 nir = module->nir;
183 nir->options = &nir_options;
184 nir_validate_shader(nir);
185
186 assert(exec_list_length(&nir->functions) == 1);
187 struct exec_node *node = exec_list_get_head(&nir->functions);
188 entry_point = exec_node_data(nir_function, node, node);
189 } else {
190 uint32_t *spirv = (uint32_t *) module->data;
191 assert(module->size % 4 == 0);
192
193 uint32_t num_spec_entries = 0;
194 struct nir_spirv_specialization *spec_entries = NULL;
195 if (spec_info && spec_info->mapEntryCount > 0) {
196 num_spec_entries = spec_info->mapEntryCount;
197 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
198 for (uint32_t i = 0; i < num_spec_entries; i++) {
199 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
200 const void *data = spec_info->pData + entry.offset;
201 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
202
203 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
204 if (spec_info->dataSize == 8)
205 spec_entries[i].data64 = *(const uint64_t *)data;
206 else
207 spec_entries[i].data32 = *(const uint32_t *)data;
208 }
209 }
210 const struct nir_spirv_supported_extensions supported_ext = {
211 .draw_parameters = true,
212 .float64 = true,
213 .image_read_without_format = true,
214 .image_write_without_format = true,
215 };
216 entry_point = spirv_to_nir(spirv, module->size / 4,
217 spec_entries, num_spec_entries,
218 stage, entrypoint_name, &supported_ext, &nir_options);
219 nir = entry_point->shader;
220 assert(nir->stage == stage);
221 nir_validate_shader(nir);
222
223 free(spec_entries);
224
225 /* We have to lower away local constant initializers right before we
226 * inline functions. That way they get properly initialized at the top
227 * of the function and not at the top of its caller.
228 */
229 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_local);
230 NIR_PASS_V(nir, nir_lower_returns);
231 NIR_PASS_V(nir, nir_inline_functions);
232
233 /* Pick off the single entrypoint that we want */
234 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
235 if (func != entry_point)
236 exec_node_remove(&func->node);
237 }
238 assert(exec_list_length(&nir->functions) == 1);
239 entry_point->name = ralloc_strdup(entry_point, "main");
240
241 NIR_PASS_V(nir, nir_remove_dead_variables,
242 nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
243
244 /* Now that we've deleted all but the main function, we can go ahead and
245 * lower the rest of the constant initializers.
246 */
247 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
248 NIR_PASS_V(nir, nir_lower_system_values);
249 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
250 }
251
252 /* Vulkan uses the separate-shader linking model */
253 nir->info->separate_shader = true;
254
255 nir_shader_gather_info(nir, entry_point->impl);
256
257 nir_variable_mode indirect_mask = 0;
258 indirect_mask |= nir_var_shader_in;
259 indirect_mask |= nir_var_local;
260
261 nir_lower_indirect_derefs(nir, indirect_mask);
262
263 static const nir_lower_tex_options tex_options = {
264 .lower_txp = ~0,
265 };
266
267 nir_lower_tex(nir, &tex_options);
268
269 nir_lower_vars_to_ssa(nir);
270 nir_lower_var_copies(nir);
271 nir_lower_global_vars_to_local(nir);
272 nir_remove_dead_variables(nir, nir_var_local);
273 radv_optimize_nir(nir);
274
275 if (dump)
276 nir_print_shader(nir, stderr);
277
278 return nir;
279 }
280
281 static const char *radv_get_shader_name(struct radv_shader_variant *var,
282 gl_shader_stage stage)
283 {
284 switch (stage) {
285 case MESA_SHADER_VERTEX: return var->info.vs.as_ls ? "Vertex Shader as LS" : var->info.vs.as_es ? "Vertex Shader as ES" : "Vertex Shader as VS";
286 case MESA_SHADER_GEOMETRY: return "Geometry Shader";
287 case MESA_SHADER_FRAGMENT: return "Pixel Shader";
288 case MESA_SHADER_COMPUTE: return "Compute Shader";
289 case MESA_SHADER_TESS_CTRL: return "Tessellation Control Shader";
290 case MESA_SHADER_TESS_EVAL: return var->info.tes.as_es ? "Tessellation Evaluation Shader as ES" : "Tessellation Evaluation Shader as VS";
291 default:
292 return "Unknown shader";
293 };
294
295 }
296 static void radv_dump_pipeline_stats(struct radv_device *device, struct radv_pipeline *pipeline)
297 {
298 unsigned lds_increment = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
299 struct radv_shader_variant *var;
300 struct ac_shader_config *conf;
301 int i;
302 FILE *file = stderr;
303 unsigned max_simd_waves = 10;
304 unsigned lds_per_wave = 0;
305
306 for (i = 0; i < MESA_SHADER_STAGES; i++) {
307 if (!pipeline->shaders[i])
308 continue;
309 var = pipeline->shaders[i];
310
311 conf = &var->config;
312
313 if (i == MESA_SHADER_FRAGMENT) {
314 lds_per_wave = conf->lds_size * lds_increment +
315 align(var->info.fs.num_interp * 48, lds_increment);
316 }
317
318 if (conf->num_sgprs) {
319 if (device->physical_device->rad_info.chip_class >= VI)
320 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
321 else
322 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
323 }
324
325 if (conf->num_vgprs)
326 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
327
328 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
329 * that PS can use.
330 */
331 if (lds_per_wave)
332 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
333
334 fprintf(file, "\n%s:\n",
335 radv_get_shader_name(var, i));
336 if (i == MESA_SHADER_FRAGMENT) {
337 fprintf(file, "*** SHADER CONFIG ***\n"
338 "SPI_PS_INPUT_ADDR = 0x%04x\n"
339 "SPI_PS_INPUT_ENA = 0x%04x\n",
340 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
341 }
342 fprintf(file, "*** SHADER STATS ***\n"
343 "SGPRS: %d\n"
344 "VGPRS: %d\n"
345 "Spilled SGPRs: %d\n"
346 "Spilled VGPRs: %d\n"
347 "Code Size: %d bytes\n"
348 "LDS: %d blocks\n"
349 "Scratch: %d bytes per wave\n"
350 "Max Waves: %d\n"
351 "********************\n\n\n",
352 conf->num_sgprs, conf->num_vgprs,
353 conf->spilled_sgprs, conf->spilled_vgprs, var->code_size,
354 conf->lds_size, conf->scratch_bytes_per_wave,
355 max_simd_waves);
356 }
357 }
358
359 void radv_shader_variant_destroy(struct radv_device *device,
360 struct radv_shader_variant *variant)
361 {
362 if (__sync_fetch_and_sub(&variant->ref_count, 1) != 1)
363 return;
364
365 device->ws->buffer_destroy(variant->bo);
366 free(variant);
367 }
368
369 static void radv_fill_shader_variant(struct radv_device *device,
370 struct radv_shader_variant *variant,
371 struct ac_shader_binary *binary,
372 gl_shader_stage stage)
373 {
374 bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0;
375 unsigned vgpr_comp_cnt = 0;
376
377 if (scratch_enabled && !device->llvm_supports_spill)
378 radv_finishme("shader scratch support only available with LLVM 4.0");
379
380 variant->code_size = binary->code_size;
381 variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
382 S_00B12C_SCRATCH_EN(scratch_enabled);
383
384 switch (stage) {
385 case MESA_SHADER_TESS_EVAL:
386 vgpr_comp_cnt = 3;
387 /* fallthrough */
388 case MESA_SHADER_TESS_CTRL:
389 variant->rsrc2 |= S_00B42C_OC_LDS_EN(1);
390 break;
391 case MESA_SHADER_VERTEX:
392 case MESA_SHADER_GEOMETRY:
393 vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
394 break;
395 case MESA_SHADER_FRAGMENT:
396 break;
397 case MESA_SHADER_COMPUTE:
398 variant->rsrc2 |=
399 S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) |
400 S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) |
401 S_00B84C_TG_SIZE_EN(1) |
402 S_00B84C_LDS_SIZE(variant->config.lds_size);
403 break;
404 default:
405 unreachable("unsupported shader type");
406 break;
407 }
408
409 variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
410 S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) |
411 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
412 S_00B848_DX10_CLAMP(1) |
413 S_00B848_FLOAT_MODE(variant->config.float_mode);
414
415 variant->bo = device->ws->buffer_create(device->ws, binary->code_size, 256,
416 RADEON_DOMAIN_VRAM, RADEON_FLAG_CPU_ACCESS);
417
418 void *ptr = device->ws->buffer_map(variant->bo);
419 memcpy(ptr, binary->code, binary->code_size);
420 device->ws->buffer_unmap(variant->bo);
421
422
423 }
424
425 static struct radv_shader_variant *radv_shader_variant_create(struct radv_device *device,
426 struct nir_shader *shader,
427 struct radv_pipeline_layout *layout,
428 const union ac_shader_variant_key *key,
429 void** code_out,
430 unsigned *code_size_out,
431 bool dump)
432 {
433 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
434 enum radeon_family chip_family = device->physical_device->rad_info.family;
435 LLVMTargetMachineRef tm;
436 if (!variant)
437 return NULL;
438
439 struct ac_nir_compiler_options options = {0};
440 options.layout = layout;
441 if (key)
442 options.key = *key;
443
444 struct ac_shader_binary binary;
445
446 options.unsafe_math = !!(device->debug_flags & RADV_DEBUG_UNSAFE_MATH);
447 options.family = chip_family;
448 options.chip_class = device->physical_device->rad_info.chip_class;
449 options.supports_spill = device->llvm_supports_spill;
450 tm = ac_create_target_machine(chip_family, options.supports_spill);
451 ac_compile_nir_shader(tm, &binary, &variant->config,
452 &variant->info, shader, &options, dump);
453 LLVMDisposeTargetMachine(tm);
454
455 radv_fill_shader_variant(device, variant, &binary, shader->stage);
456
457 if (code_out) {
458 *code_out = binary.code;
459 *code_size_out = binary.code_size;
460 } else
461 free(binary.code);
462 free(binary.config);
463 free(binary.rodata);
464 free(binary.global_symbol_offsets);
465 free(binary.relocs);
466 free(binary.disasm_string);
467 variant->ref_count = 1;
468 return variant;
469 }
470
471 static struct radv_shader_variant *
472 radv_pipeline_create_gs_copy_shader(struct radv_pipeline *pipeline,
473 struct nir_shader *nir,
474 void** code_out,
475 unsigned *code_size_out,
476 bool dump_shader)
477 {
478 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
479 enum radeon_family chip_family = pipeline->device->physical_device->rad_info.family;
480 LLVMTargetMachineRef tm;
481 if (!variant)
482 return NULL;
483
484 struct ac_nir_compiler_options options = {0};
485 struct ac_shader_binary binary;
486 options.family = chip_family;
487 options.chip_class = pipeline->device->physical_device->rad_info.chip_class;
488 options.supports_spill = pipeline->device->llvm_supports_spill;
489 tm = ac_create_target_machine(chip_family, options.supports_spill);
490 ac_create_gs_copy_shader(tm, nir, &binary, &variant->config, &variant->info, &options, dump_shader);
491 LLVMDisposeTargetMachine(tm);
492
493 radv_fill_shader_variant(pipeline->device, variant, &binary, MESA_SHADER_VERTEX);
494
495 if (code_out) {
496 *code_out = binary.code;
497 *code_size_out = binary.code_size;
498 } else
499 free(binary.code);
500 free(binary.config);
501 free(binary.rodata);
502 free(binary.global_symbol_offsets);
503 free(binary.relocs);
504 free(binary.disasm_string);
505 variant->ref_count = 1;
506 return variant;
507 }
508
509 static struct radv_shader_variant *
510 radv_pipeline_compile(struct radv_pipeline *pipeline,
511 struct radv_pipeline_cache *cache,
512 struct radv_shader_module *module,
513 const char *entrypoint,
514 gl_shader_stage stage,
515 const VkSpecializationInfo *spec_info,
516 struct radv_pipeline_layout *layout,
517 const union ac_shader_variant_key *key)
518 {
519 unsigned char sha1[20];
520 unsigned char gs_copy_sha1[20];
521 struct radv_shader_variant *variant;
522 nir_shader *nir;
523 void *code = NULL;
524 unsigned code_size = 0;
525 bool dump = (pipeline->device->debug_flags & RADV_DEBUG_DUMP_SHADERS);
526
527 if (module->nir)
528 _mesa_sha1_compute(module->nir->info->name,
529 strlen(module->nir->info->name),
530 module->sha1);
531
532 radv_hash_shader(sha1, module, entrypoint, spec_info, layout, key, 0);
533 if (stage == MESA_SHADER_GEOMETRY)
534 radv_hash_shader(gs_copy_sha1, module, entrypoint, spec_info,
535 layout, key, 1);
536
537 variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
538 cache,
539 sha1);
540
541 if (stage == MESA_SHADER_GEOMETRY) {
542 pipeline->gs_copy_shader =
543 radv_create_shader_variant_from_pipeline_cache(
544 pipeline->device,
545 cache,
546 gs_copy_sha1);
547 }
548
549 if (variant &&
550 (stage != MESA_SHADER_GEOMETRY || pipeline->gs_copy_shader))
551 return variant;
552
553 nir = radv_shader_compile_to_nir(pipeline->device,
554 module, entrypoint, stage,
555 spec_info, dump);
556 if (nir == NULL)
557 return NULL;
558
559 if (!variant) {
560 variant = radv_shader_variant_create(pipeline->device, nir,
561 layout, key, &code,
562 &code_size, dump);
563 }
564
565 if (stage == MESA_SHADER_GEOMETRY && !pipeline->gs_copy_shader) {
566 void *gs_copy_code = NULL;
567 unsigned gs_copy_code_size = 0;
568 pipeline->gs_copy_shader = radv_pipeline_create_gs_copy_shader(
569 pipeline, nir, &gs_copy_code, &gs_copy_code_size, dump);
570
571 if (pipeline->gs_copy_shader) {
572 pipeline->gs_copy_shader =
573 radv_pipeline_cache_insert_shader(cache,
574 gs_copy_sha1,
575 pipeline->gs_copy_shader,
576 gs_copy_code,
577 gs_copy_code_size);
578 }
579 }
580 if (!module->nir)
581 ralloc_free(nir);
582
583 if (variant)
584 variant = radv_pipeline_cache_insert_shader(cache, sha1, variant,
585 code, code_size);
586
587 if (code)
588 free(code);
589 return variant;
590 }
591
592 static VkResult
593 radv_pipeline_scratch_init(struct radv_device *device,
594 struct radv_pipeline *pipeline)
595 {
596 unsigned scratch_bytes_per_wave = 0;
597 unsigned max_waves = 0;
598 unsigned min_waves = 1;
599
600 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
601 if (pipeline->shaders[i]) {
602 unsigned max_stage_waves = device->scratch_waves;
603
604 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
605 pipeline->shaders[i]->config.scratch_bytes_per_wave);
606
607 max_stage_waves = MIN2(max_stage_waves,
608 4 * device->physical_device->rad_info.num_good_compute_units *
609 (256 / pipeline->shaders[i]->config.num_vgprs));
610 max_waves = MAX2(max_waves, max_stage_waves);
611 }
612 }
613
614 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
615 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
616 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
617 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
618 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
619 }
620
621 if (scratch_bytes_per_wave)
622 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
623
624 if (scratch_bytes_per_wave && max_waves < min_waves) {
625 /* Not really true at this moment, but will be true on first
626 * execution. Avoid having hanging shaders. */
627 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
628 }
629 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
630 pipeline->max_waves = max_waves;
631 return VK_SUCCESS;
632 }
633
634 static uint32_t si_translate_blend_function(VkBlendOp op)
635 {
636 switch (op) {
637 case VK_BLEND_OP_ADD:
638 return V_028780_COMB_DST_PLUS_SRC;
639 case VK_BLEND_OP_SUBTRACT:
640 return V_028780_COMB_SRC_MINUS_DST;
641 case VK_BLEND_OP_REVERSE_SUBTRACT:
642 return V_028780_COMB_DST_MINUS_SRC;
643 case VK_BLEND_OP_MIN:
644 return V_028780_COMB_MIN_DST_SRC;
645 case VK_BLEND_OP_MAX:
646 return V_028780_COMB_MAX_DST_SRC;
647 default:
648 return 0;
649 }
650 }
651
652 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
653 {
654 switch (factor) {
655 case VK_BLEND_FACTOR_ZERO:
656 return V_028780_BLEND_ZERO;
657 case VK_BLEND_FACTOR_ONE:
658 return V_028780_BLEND_ONE;
659 case VK_BLEND_FACTOR_SRC_COLOR:
660 return V_028780_BLEND_SRC_COLOR;
661 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
662 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
663 case VK_BLEND_FACTOR_DST_COLOR:
664 return V_028780_BLEND_DST_COLOR;
665 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
666 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
667 case VK_BLEND_FACTOR_SRC_ALPHA:
668 return V_028780_BLEND_SRC_ALPHA;
669 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
670 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
671 case VK_BLEND_FACTOR_DST_ALPHA:
672 return V_028780_BLEND_DST_ALPHA;
673 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
674 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
675 case VK_BLEND_FACTOR_CONSTANT_COLOR:
676 return V_028780_BLEND_CONSTANT_COLOR;
677 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
678 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
679 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
680 return V_028780_BLEND_CONSTANT_ALPHA;
681 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
682 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
683 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
684 return V_028780_BLEND_SRC_ALPHA_SATURATE;
685 case VK_BLEND_FACTOR_SRC1_COLOR:
686 return V_028780_BLEND_SRC1_COLOR;
687 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
688 return V_028780_BLEND_INV_SRC1_COLOR;
689 case VK_BLEND_FACTOR_SRC1_ALPHA:
690 return V_028780_BLEND_SRC1_ALPHA;
691 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
692 return V_028780_BLEND_INV_SRC1_ALPHA;
693 default:
694 return 0;
695 }
696 }
697
698 static bool is_dual_src(VkBlendFactor factor)
699 {
700 switch (factor) {
701 case VK_BLEND_FACTOR_SRC1_COLOR:
702 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
703 case VK_BLEND_FACTOR_SRC1_ALPHA:
704 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
705 return true;
706 default:
707 return false;
708 }
709 }
710
711 static unsigned si_choose_spi_color_format(VkFormat vk_format,
712 bool blend_enable,
713 bool blend_need_alpha)
714 {
715 const struct vk_format_description *desc = vk_format_description(vk_format);
716 unsigned format, ntype, swap;
717
718 /* Alpha is needed for alpha-to-coverage.
719 * Blending may be with or without alpha.
720 */
721 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
722 unsigned alpha = 0; /* exports alpha, but may not support blending */
723 unsigned blend = 0; /* supports blending, but may not export alpha */
724 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
725
726 format = radv_translate_colorformat(vk_format);
727 ntype = radv_translate_color_numformat(vk_format, desc,
728 vk_format_get_first_non_void_channel(vk_format));
729 swap = radv_translate_colorswap(vk_format, false);
730
731 /* Choose the SPI color formats. These are required values for Stoney/RB+.
732 * Other chips have multiple choices, though they are not necessarily better.
733 */
734 switch (format) {
735 case V_028C70_COLOR_5_6_5:
736 case V_028C70_COLOR_1_5_5_5:
737 case V_028C70_COLOR_5_5_5_1:
738 case V_028C70_COLOR_4_4_4_4:
739 case V_028C70_COLOR_10_11_11:
740 case V_028C70_COLOR_11_11_10:
741 case V_028C70_COLOR_8:
742 case V_028C70_COLOR_8_8:
743 case V_028C70_COLOR_8_8_8_8:
744 case V_028C70_COLOR_10_10_10_2:
745 case V_028C70_COLOR_2_10_10_10:
746 if (ntype == V_028C70_NUMBER_UINT)
747 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
748 else if (ntype == V_028C70_NUMBER_SINT)
749 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
750 else
751 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
752 break;
753
754 case V_028C70_COLOR_16:
755 case V_028C70_COLOR_16_16:
756 case V_028C70_COLOR_16_16_16_16:
757 if (ntype == V_028C70_NUMBER_UNORM ||
758 ntype == V_028C70_NUMBER_SNORM) {
759 /* UNORM16 and SNORM16 don't support blending */
760 if (ntype == V_028C70_NUMBER_UNORM)
761 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
762 else
763 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
764
765 /* Use 32 bits per channel for blending. */
766 if (format == V_028C70_COLOR_16) {
767 if (swap == V_028C70_SWAP_STD) { /* R */
768 blend = V_028714_SPI_SHADER_32_R;
769 blend_alpha = V_028714_SPI_SHADER_32_AR;
770 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
771 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
772 else
773 assert(0);
774 } else if (format == V_028C70_COLOR_16_16) {
775 if (swap == V_028C70_SWAP_STD) { /* RG */
776 blend = V_028714_SPI_SHADER_32_GR;
777 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
778 } else if (swap == V_028C70_SWAP_ALT) /* RA */
779 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
780 else
781 assert(0);
782 } else /* 16_16_16_16 */
783 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
784 } else if (ntype == V_028C70_NUMBER_UINT)
785 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
786 else if (ntype == V_028C70_NUMBER_SINT)
787 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
788 else if (ntype == V_028C70_NUMBER_FLOAT)
789 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
790 else
791 assert(0);
792 break;
793
794 case V_028C70_COLOR_32:
795 if (swap == V_028C70_SWAP_STD) { /* R */
796 blend = normal = V_028714_SPI_SHADER_32_R;
797 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
798 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
799 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
800 else
801 assert(0);
802 break;
803
804 case V_028C70_COLOR_32_32:
805 if (swap == V_028C70_SWAP_STD) { /* RG */
806 blend = normal = V_028714_SPI_SHADER_32_GR;
807 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
808 } else if (swap == V_028C70_SWAP_ALT) /* RA */
809 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
810 else
811 assert(0);
812 break;
813
814 case V_028C70_COLOR_32_32_32_32:
815 case V_028C70_COLOR_8_24:
816 case V_028C70_COLOR_24_8:
817 case V_028C70_COLOR_X24_8_32_FLOAT:
818 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
819 break;
820
821 default:
822 unreachable("unhandled blend format");
823 }
824
825 if (blend_enable && blend_need_alpha)
826 return blend_alpha;
827 else if(blend_need_alpha)
828 return alpha;
829 else if(blend_enable)
830 return blend;
831 else
832 return normal;
833 }
834
835 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
836 {
837 unsigned i, cb_shader_mask = 0;
838
839 for (i = 0; i < 8; i++) {
840 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
841 case V_028714_SPI_SHADER_ZERO:
842 break;
843 case V_028714_SPI_SHADER_32_R:
844 cb_shader_mask |= 0x1 << (i * 4);
845 break;
846 case V_028714_SPI_SHADER_32_GR:
847 cb_shader_mask |= 0x3 << (i * 4);
848 break;
849 case V_028714_SPI_SHADER_32_AR:
850 cb_shader_mask |= 0x9 << (i * 4);
851 break;
852 case V_028714_SPI_SHADER_FP16_ABGR:
853 case V_028714_SPI_SHADER_UNORM16_ABGR:
854 case V_028714_SPI_SHADER_SNORM16_ABGR:
855 case V_028714_SPI_SHADER_UINT16_ABGR:
856 case V_028714_SPI_SHADER_SINT16_ABGR:
857 case V_028714_SPI_SHADER_32_ABGR:
858 cb_shader_mask |= 0xf << (i * 4);
859 break;
860 default:
861 assert(0);
862 }
863 }
864 return cb_shader_mask;
865 }
866
867 static void
868 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
869 const VkGraphicsPipelineCreateInfo *pCreateInfo,
870 uint32_t blend_enable,
871 uint32_t blend_need_alpha,
872 bool single_cb_enable,
873 bool blend_mrt0_is_dual_src)
874 {
875 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
876 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
877 struct radv_blend_state *blend = &pipeline->graphics.blend;
878 unsigned col_format = 0;
879
880 for (unsigned i = 0; i < (single_cb_enable ? 1 : subpass->color_count); ++i) {
881 struct radv_render_pass_attachment *attachment;
882 unsigned cf;
883
884 attachment = pass->attachments + subpass->color_attachments[i].attachment;
885
886 cf = si_choose_spi_color_format(attachment->format,
887 blend_enable & (1 << i),
888 blend_need_alpha & (1 << i));
889
890 col_format |= cf << (4 * i);
891 }
892
893 blend->cb_shader_mask = si_get_cb_shader_mask(col_format);
894
895 if (blend_mrt0_is_dual_src)
896 col_format |= (col_format & 0xf) << 4;
897 blend->spi_shader_col_format = col_format;
898 }
899
900 static bool
901 format_is_int8(VkFormat format)
902 {
903 const struct vk_format_description *desc = vk_format_description(format);
904 int channel = vk_format_get_first_non_void_channel(format);
905
906 return channel >= 0 && desc->channel[channel].pure_integer &&
907 desc->channel[channel].size == 8;
908 }
909
910 unsigned radv_format_meta_fs_key(VkFormat format)
911 {
912 unsigned col_format = si_choose_spi_color_format(format, false, false) - 1;
913 bool is_int8 = format_is_int8(format);
914
915 return col_format + (is_int8 ? 3 : 0);
916 }
917
918 static unsigned
919 radv_pipeline_compute_is_int8(const VkGraphicsPipelineCreateInfo *pCreateInfo)
920 {
921 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
922 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
923 unsigned is_int8 = 0;
924
925 for (unsigned i = 0; i < subpass->color_count; ++i) {
926 struct radv_render_pass_attachment *attachment;
927
928 attachment = pass->attachments + subpass->color_attachments[i].attachment;
929
930 if (format_is_int8(attachment->format))
931 is_int8 |= 1 << i;
932 }
933
934 return is_int8;
935 }
936
937 static void
938 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
939 const VkGraphicsPipelineCreateInfo *pCreateInfo,
940 const struct radv_graphics_pipeline_create_info *extra)
941 {
942 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
943 struct radv_blend_state *blend = &pipeline->graphics.blend;
944 unsigned mode = V_028808_CB_NORMAL;
945 uint32_t blend_enable = 0, blend_need_alpha = 0;
946 bool blend_mrt0_is_dual_src = false;
947 int i;
948 bool single_cb_enable = false;
949
950 if (!vkblend)
951 return;
952
953 if (extra && extra->custom_blend_mode) {
954 single_cb_enable = true;
955 mode = extra->custom_blend_mode;
956 }
957 blend->cb_color_control = 0;
958 if (vkblend->logicOpEnable)
959 blend->cb_color_control |= S_028808_ROP3(vkblend->logicOp | (vkblend->logicOp << 4));
960 else
961 blend->cb_color_control |= S_028808_ROP3(0xcc);
962
963 blend->db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
964 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
965 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
966 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
967
968 blend->cb_target_mask = 0;
969 for (i = 0; i < vkblend->attachmentCount; i++) {
970 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
971 unsigned blend_cntl = 0;
972 VkBlendOp eqRGB = att->colorBlendOp;
973 VkBlendFactor srcRGB = att->srcColorBlendFactor;
974 VkBlendFactor dstRGB = att->dstColorBlendFactor;
975 VkBlendOp eqA = att->alphaBlendOp;
976 VkBlendFactor srcA = att->srcAlphaBlendFactor;
977 VkBlendFactor dstA = att->dstAlphaBlendFactor;
978
979 blend->sx_mrt0_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
980
981 if (!att->colorWriteMask)
982 continue;
983
984 blend->cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
985 if (!att->blendEnable) {
986 blend->cb_blend_control[i] = blend_cntl;
987 continue;
988 }
989
990 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
991 if (i == 0)
992 blend_mrt0_is_dual_src = true;
993
994 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
995 srcRGB = VK_BLEND_FACTOR_ONE;
996 dstRGB = VK_BLEND_FACTOR_ONE;
997 }
998 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
999 srcA = VK_BLEND_FACTOR_ONE;
1000 dstA = VK_BLEND_FACTOR_ONE;
1001 }
1002
1003 blend_cntl |= S_028780_ENABLE(1);
1004
1005 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
1006 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
1007 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
1008 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
1009 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
1010 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
1011 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
1012 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
1013 }
1014 blend->cb_blend_control[i] = blend_cntl;
1015
1016 blend_enable |= 1 << i;
1017
1018 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
1019 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
1020 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
1021 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
1022 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
1023 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
1024 blend_need_alpha |= 1 << i;
1025 }
1026 for (i = vkblend->attachmentCount; i < 8; i++)
1027 blend->cb_blend_control[i] = 0;
1028
1029 if (blend->cb_target_mask)
1030 blend->cb_color_control |= S_028808_MODE(mode);
1031 else
1032 blend->cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
1033
1034 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo,
1035 blend_enable, blend_need_alpha, single_cb_enable, blend_mrt0_is_dual_src);
1036 }
1037
1038 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
1039 {
1040 switch (op) {
1041 case VK_STENCIL_OP_KEEP:
1042 return V_02842C_STENCIL_KEEP;
1043 case VK_STENCIL_OP_ZERO:
1044 return V_02842C_STENCIL_ZERO;
1045 case VK_STENCIL_OP_REPLACE:
1046 return V_02842C_STENCIL_REPLACE_TEST;
1047 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
1048 return V_02842C_STENCIL_ADD_CLAMP;
1049 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
1050 return V_02842C_STENCIL_SUB_CLAMP;
1051 case VK_STENCIL_OP_INVERT:
1052 return V_02842C_STENCIL_INVERT;
1053 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
1054 return V_02842C_STENCIL_ADD_WRAP;
1055 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
1056 return V_02842C_STENCIL_SUB_WRAP;
1057 default:
1058 return 0;
1059 }
1060 }
1061 static void
1062 radv_pipeline_init_depth_stencil_state(struct radv_pipeline *pipeline,
1063 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1064 const struct radv_graphics_pipeline_create_info *extra)
1065 {
1066 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
1067 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
1068
1069 memset(ds, 0, sizeof(*ds));
1070 if (!vkds)
1071 return;
1072 ds->db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
1073 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
1074 S_028800_ZFUNC(vkds->depthCompareOp) |
1075 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
1076
1077 if (vkds->stencilTestEnable) {
1078 ds->db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
1079 ds->db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
1080 ds->db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
1081 ds->db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
1082 ds->db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
1083
1084 ds->db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
1085 ds->db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
1086 ds->db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
1087 ds->db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
1088 }
1089
1090 if (extra) {
1091
1092 ds->db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
1093 ds->db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
1094
1095 ds->db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
1096 ds->db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
1097 ds->db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
1098 ds->db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
1099 ds->db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
1100 }
1101 }
1102
1103 static uint32_t si_translate_fill(VkPolygonMode func)
1104 {
1105 switch(func) {
1106 case VK_POLYGON_MODE_FILL:
1107 return V_028814_X_DRAW_TRIANGLES;
1108 case VK_POLYGON_MODE_LINE:
1109 return V_028814_X_DRAW_LINES;
1110 case VK_POLYGON_MODE_POINT:
1111 return V_028814_X_DRAW_POINTS;
1112 default:
1113 assert(0);
1114 return V_028814_X_DRAW_POINTS;
1115 }
1116 }
1117 static void
1118 radv_pipeline_init_raster_state(struct radv_pipeline *pipeline,
1119 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1120 {
1121 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
1122 struct radv_raster_state *raster = &pipeline->graphics.raster;
1123
1124 memset(raster, 0, sizeof(*raster));
1125
1126 raster->spi_interp_control =
1127 S_0286D4_FLAT_SHADE_ENA(1) |
1128 S_0286D4_PNT_SPRITE_ENA(1) |
1129 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
1130 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
1131 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
1132 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
1133 S_0286D4_PNT_SPRITE_TOP_1(0); // vulkan is top to bottom - 1.0 at bottom
1134
1135
1136 raster->pa_cl_clip_cntl = S_028810_PS_UCP_MODE(3) |
1137 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
1138 S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1139 S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1140 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
1141 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
1142
1143 raster->pa_su_vtx_cntl =
1144 S_028BE4_PIX_CENTER(1) | // TODO verify
1145 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
1146 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH);
1147
1148 raster->pa_su_sc_mode_cntl =
1149 S_028814_FACE(vkraster->frontFace) |
1150 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
1151 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
1152 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
1153 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1154 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1155 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1156 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1157 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0);
1158
1159 }
1160
1161 static void
1162 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1163 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1164 {
1165 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
1166 struct radv_blend_state *blend = &pipeline->graphics.blend;
1167 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1168 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1169 int ps_iter_samples = 1;
1170 uint32_t mask = 0xffff;
1171
1172 if (vkms)
1173 ms->num_samples = vkms->rasterizationSamples;
1174 else
1175 ms->num_samples = 1;
1176
1177 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.force_persample) {
1178 ps_iter_samples = ms->num_samples;
1179 }
1180
1181 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1182 ms->pa_sc_aa_config = 0;
1183 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1184 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1185 ms->pa_sc_mode_cntl_1 =
1186 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1187 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1188 /* always 1: */
1189 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1190 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1191 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1192 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1193 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1194 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1195
1196 if (ms->num_samples > 1) {
1197 unsigned log_samples = util_logbase2(ms->num_samples);
1198 unsigned log_ps_iter_samples = util_logbase2(util_next_power_of_two(ps_iter_samples));
1199 ms->pa_sc_mode_cntl_0 = S_028A48_MSAA_ENABLE(1);
1200 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1201 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1202 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1203 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1204 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1205 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1206 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
1207 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1208 ms->pa_sc_mode_cntl_1 |= EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1209 }
1210
1211 if (vkms) {
1212 if (vkms->alphaToCoverageEnable)
1213 blend->db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
1214
1215 if (vkms->pSampleMask)
1216 mask = vkms->pSampleMask[0] & 0xffff;
1217 }
1218
1219 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1220 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1221 }
1222
1223 static bool
1224 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1225 {
1226 switch (topology) {
1227 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1228 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1229 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1230 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1231 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1232 return false;
1233 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1234 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1235 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1236 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1237 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1238 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1239 return true;
1240 default:
1241 unreachable("unhandled primitive type");
1242 }
1243 }
1244
1245 static uint32_t
1246 si_translate_prim(enum VkPrimitiveTopology topology)
1247 {
1248 switch (topology) {
1249 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1250 return V_008958_DI_PT_POINTLIST;
1251 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1252 return V_008958_DI_PT_LINELIST;
1253 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1254 return V_008958_DI_PT_LINESTRIP;
1255 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1256 return V_008958_DI_PT_TRILIST;
1257 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1258 return V_008958_DI_PT_TRISTRIP;
1259 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1260 return V_008958_DI_PT_TRIFAN;
1261 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1262 return V_008958_DI_PT_LINELIST_ADJ;
1263 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1264 return V_008958_DI_PT_LINESTRIP_ADJ;
1265 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1266 return V_008958_DI_PT_TRILIST_ADJ;
1267 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1268 return V_008958_DI_PT_TRISTRIP_ADJ;
1269 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1270 return V_008958_DI_PT_PATCH;
1271 default:
1272 assert(0);
1273 return 0;
1274 }
1275 }
1276
1277 static uint32_t
1278 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1279 {
1280 switch (gl_prim) {
1281 case 0: /* GL_POINTS */
1282 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1283 case 1: /* GL_LINES */
1284 case 3: /* GL_LINE_STRIP */
1285 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1286 case 0x8E7A: /* GL_ISOLINES */
1287 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1288
1289 case 4: /* GL_TRIANGLES */
1290 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1291 case 5: /* GL_TRIANGLE_STRIP */
1292 case 7: /* GL_QUADS */
1293 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1294 default:
1295 assert(0);
1296 return 0;
1297 }
1298 }
1299
1300 static uint32_t
1301 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1302 {
1303 switch (topology) {
1304 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1305 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1306 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1307 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1308 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1309 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1310 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1311 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1312 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1313 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1314 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1315 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1316 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1317 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1318 default:
1319 assert(0);
1320 return 0;
1321 }
1322 }
1323
1324 static unsigned si_map_swizzle(unsigned swizzle)
1325 {
1326 switch (swizzle) {
1327 case VK_SWIZZLE_Y:
1328 return V_008F0C_SQ_SEL_Y;
1329 case VK_SWIZZLE_Z:
1330 return V_008F0C_SQ_SEL_Z;
1331 case VK_SWIZZLE_W:
1332 return V_008F0C_SQ_SEL_W;
1333 case VK_SWIZZLE_0:
1334 return V_008F0C_SQ_SEL_0;
1335 case VK_SWIZZLE_1:
1336 return V_008F0C_SQ_SEL_1;
1337 default: /* VK_SWIZZLE_X */
1338 return V_008F0C_SQ_SEL_X;
1339 }
1340 }
1341
1342 static void
1343 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1344 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1345 {
1346 radv_cmd_dirty_mask_t states = RADV_CMD_DIRTY_DYNAMIC_ALL;
1347 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1348 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1349
1350 pipeline->dynamic_state = default_dynamic_state;
1351
1352 if (pCreateInfo->pDynamicState) {
1353 /* Remove all of the states that are marked as dynamic */
1354 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1355 for (uint32_t s = 0; s < count; s++)
1356 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
1357 }
1358
1359 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1360
1361 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1362 *
1363 * pViewportState is [...] NULL if the pipeline
1364 * has rasterization disabled.
1365 */
1366 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1367 assert(pCreateInfo->pViewportState);
1368
1369 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1370 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
1371 typed_memcpy(dynamic->viewport.viewports,
1372 pCreateInfo->pViewportState->pViewports,
1373 pCreateInfo->pViewportState->viewportCount);
1374 }
1375
1376 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1377 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
1378 typed_memcpy(dynamic->scissor.scissors,
1379 pCreateInfo->pViewportState->pScissors,
1380 pCreateInfo->pViewportState->scissorCount);
1381 }
1382 }
1383
1384 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
1385 assert(pCreateInfo->pRasterizationState);
1386 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1387 }
1388
1389 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
1390 assert(pCreateInfo->pRasterizationState);
1391 dynamic->depth_bias.bias =
1392 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1393 dynamic->depth_bias.clamp =
1394 pCreateInfo->pRasterizationState->depthBiasClamp;
1395 dynamic->depth_bias.slope =
1396 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1397 }
1398
1399 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1400 *
1401 * pColorBlendState is [...] NULL if the pipeline has rasterization
1402 * disabled or if the subpass of the render pass the pipeline is
1403 * created against does not use any color attachments.
1404 */
1405 bool uses_color_att = false;
1406 for (unsigned i = 0; i < subpass->color_count; ++i) {
1407 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1408 uses_color_att = true;
1409 break;
1410 }
1411 }
1412
1413 if (uses_color_att && states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
1414 assert(pCreateInfo->pColorBlendState);
1415 typed_memcpy(dynamic->blend_constants,
1416 pCreateInfo->pColorBlendState->blendConstants, 4);
1417 }
1418
1419 /* If there is no depthstencil attachment, then don't read
1420 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1421 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1422 * no need to override the depthstencil defaults in
1423 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1424 *
1425 * Section 9.2 of the Vulkan 1.0.15 spec says:
1426 *
1427 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1428 * disabled or if the subpass of the render pass the pipeline is created
1429 * against does not use a depth/stencil attachment.
1430 */
1431 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
1432 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1433 assert(pCreateInfo->pDepthStencilState);
1434
1435 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
1436 dynamic->depth_bounds.min =
1437 pCreateInfo->pDepthStencilState->minDepthBounds;
1438 dynamic->depth_bounds.max =
1439 pCreateInfo->pDepthStencilState->maxDepthBounds;
1440 }
1441
1442 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
1443 dynamic->stencil_compare_mask.front =
1444 pCreateInfo->pDepthStencilState->front.compareMask;
1445 dynamic->stencil_compare_mask.back =
1446 pCreateInfo->pDepthStencilState->back.compareMask;
1447 }
1448
1449 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
1450 dynamic->stencil_write_mask.front =
1451 pCreateInfo->pDepthStencilState->front.writeMask;
1452 dynamic->stencil_write_mask.back =
1453 pCreateInfo->pDepthStencilState->back.writeMask;
1454 }
1455
1456 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
1457 dynamic->stencil_reference.front =
1458 pCreateInfo->pDepthStencilState->front.reference;
1459 dynamic->stencil_reference.back =
1460 pCreateInfo->pDepthStencilState->back.reference;
1461 }
1462 }
1463
1464 pipeline->dynamic_state_mask = states;
1465 }
1466
1467 static union ac_shader_variant_key
1468 radv_compute_vs_key(const VkGraphicsPipelineCreateInfo *pCreateInfo, bool as_es)
1469 {
1470 union ac_shader_variant_key key;
1471 const VkPipelineVertexInputStateCreateInfo *input_state =
1472 pCreateInfo->pVertexInputState;
1473
1474 memset(&key, 0, sizeof(key));
1475 key.vs.instance_rate_inputs = 0;
1476 key.vs.as_es = as_es;
1477
1478 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
1479 unsigned binding;
1480 binding = input_state->pVertexAttributeDescriptions[i].binding;
1481 if (input_state->pVertexBindingDescriptions[binding].inputRate)
1482 key.vs.instance_rate_inputs |= 1u << input_state->pVertexAttributeDescriptions[i].location;
1483 }
1484 return key;
1485 }
1486
1487 static void
1488 calculate_gs_ring_sizes(struct radv_pipeline *pipeline)
1489 {
1490 struct radv_device *device = pipeline->device;
1491 unsigned num_se = device->physical_device->rad_info.max_se;
1492 unsigned wave_size = 64;
1493 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1494 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1495 unsigned alignment = 256 * num_se;
1496 /* The maximum size is 63.999 MB per SE. */
1497 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1498 struct ac_es_output_info *es_info = &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info;
1499 struct ac_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1500
1501 /* Calculate the minimum size. */
1502 unsigned min_esgs_ring_size = align(es_info->esgs_itemsize * gs_vertex_reuse *
1503 wave_size, alignment);
1504 /* These are recommended sizes, not minimum sizes. */
1505 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1506 es_info->esgs_itemsize * gs_info->gs.vertices_in;
1507 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1508 gs_info->gs.max_gsvs_emit_size * 1; // no streams in VK (gs->max_gs_stream + 1);
1509
1510 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1511 esgs_ring_size = align(esgs_ring_size, alignment);
1512 gsvs_ring_size = align(gsvs_ring_size, alignment);
1513
1514 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1515 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1516 }
1517
1518 static const struct radv_prim_vertex_count prim_size_table[] = {
1519 [V_008958_DI_PT_NONE] = {0, 0},
1520 [V_008958_DI_PT_POINTLIST] = {1, 1},
1521 [V_008958_DI_PT_LINELIST] = {2, 2},
1522 [V_008958_DI_PT_LINESTRIP] = {2, 1},
1523 [V_008958_DI_PT_TRILIST] = {3, 3},
1524 [V_008958_DI_PT_TRIFAN] = {3, 1},
1525 [V_008958_DI_PT_TRISTRIP] = {3, 1},
1526 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
1527 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
1528 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
1529 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
1530 [V_008958_DI_PT_RECTLIST] = {3, 3},
1531 [V_008958_DI_PT_LINELOOP] = {2, 1},
1532 [V_008958_DI_PT_POLYGON] = {3, 1},
1533 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
1534 };
1535
1536 static uint32_t si_vgt_gs_mode(struct radv_shader_variant *gs)
1537 {
1538 unsigned gs_max_vert_out = gs->info.gs.vertices_out;
1539 unsigned cut_mode;
1540
1541 if (gs_max_vert_out <= 128) {
1542 cut_mode = V_028A40_GS_CUT_128;
1543 } else if (gs_max_vert_out <= 256) {
1544 cut_mode = V_028A40_GS_CUT_256;
1545 } else if (gs_max_vert_out <= 512) {
1546 cut_mode = V_028A40_GS_CUT_512;
1547 } else {
1548 assert(gs_max_vert_out <= 1024);
1549 cut_mode = V_028A40_GS_CUT_1024;
1550 }
1551
1552 return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
1553 S_028A40_CUT_MODE(cut_mode)|
1554 S_028A40_ES_WRITE_OPTIMIZE(1) |
1555 S_028A40_GS_WRITE_OPTIMIZE(1);
1556 }
1557
1558 static void calculate_pa_cl_vs_out_cntl(struct radv_pipeline *pipeline)
1559 {
1560 struct radv_shader_variant *vs;
1561 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : pipeline->shaders[MESA_SHADER_VERTEX];
1562
1563 struct ac_vs_output_info *outinfo = &vs->info.vs.outinfo;
1564
1565 unsigned clip_dist_mask, cull_dist_mask, total_mask;
1566 clip_dist_mask = outinfo->clip_dist_mask;
1567 cull_dist_mask = outinfo->cull_dist_mask;
1568 total_mask = clip_dist_mask | cull_dist_mask;
1569
1570 bool misc_vec_ena = outinfo->writes_pointsize ||
1571 outinfo->writes_layer ||
1572 outinfo->writes_viewport_index;
1573 pipeline->graphics.pa_cl_vs_out_cntl =
1574 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
1575 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
1576 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
1577 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
1578 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
1579 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
1580 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
1581 cull_dist_mask << 8 |
1582 clip_dist_mask;
1583
1584 }
1585 static void calculate_ps_inputs(struct radv_pipeline *pipeline)
1586 {
1587 struct radv_shader_variant *ps, *vs;
1588 struct ac_vs_output_info *outinfo;
1589
1590 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
1591 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : pipeline->shaders[MESA_SHADER_VERTEX];
1592
1593 outinfo = &vs->info.vs.outinfo;
1594
1595 unsigned ps_offset = 0;
1596 if (ps->info.fs.has_pcoord) {
1597 unsigned val;
1598 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
1599 pipeline->graphics.ps_input_cntl[ps_offset] = val;
1600 ps_offset++;
1601 }
1602
1603 if (ps->info.fs.prim_id_input && (outinfo->prim_id_output != 0xffffffff)) {
1604 unsigned vs_offset, flat_shade;
1605 unsigned val;
1606 vs_offset = outinfo->prim_id_output;
1607 flat_shade = true;
1608 val = S_028644_OFFSET(vs_offset) | S_028644_FLAT_SHADE(flat_shade);
1609 pipeline->graphics.ps_input_cntl[ps_offset] = val;
1610 ++ps_offset;
1611 }
1612
1613 if (ps->info.fs.layer_input && (outinfo->layer_output != 0xffffffff)) {
1614 unsigned vs_offset, flat_shade;
1615 unsigned val;
1616 vs_offset = outinfo->layer_output;
1617 flat_shade = true;
1618 val = S_028644_OFFSET(vs_offset) | S_028644_FLAT_SHADE(flat_shade);
1619 pipeline->graphics.ps_input_cntl[ps_offset] = val;
1620 ++ps_offset;
1621 }
1622
1623 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
1624 unsigned vs_offset, flat_shade;
1625 unsigned val;
1626
1627 if (!(ps->info.fs.input_mask & (1u << i)))
1628 continue;
1629
1630 if (!(outinfo->export_mask & (1u << i))) {
1631 pipeline->graphics.ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
1632 ++ps_offset;
1633 continue;
1634 }
1635
1636 vs_offset = util_bitcount(outinfo->export_mask & ((1u << i) - 1));
1637 if (outinfo->prim_id_output != 0xffffffff) {
1638 if (vs_offset >= outinfo->prim_id_output)
1639 vs_offset++;
1640 }
1641 if (outinfo->layer_output != 0xffffffff) {
1642 if (vs_offset >= outinfo->layer_output)
1643 vs_offset++;
1644 }
1645 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
1646
1647 val = S_028644_OFFSET(vs_offset) | S_028644_FLAT_SHADE(flat_shade);
1648 pipeline->graphics.ps_input_cntl[ps_offset] = val;
1649 ++ps_offset;
1650 }
1651
1652 pipeline->graphics.ps_input_cntl_num = ps_offset;
1653 }
1654
1655 VkResult
1656 radv_pipeline_init(struct radv_pipeline *pipeline,
1657 struct radv_device *device,
1658 struct radv_pipeline_cache *cache,
1659 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1660 const struct radv_graphics_pipeline_create_info *extra,
1661 const VkAllocationCallbacks *alloc)
1662 {
1663 struct radv_shader_module fs_m = {0};
1664 VkResult result;
1665
1666 if (alloc == NULL)
1667 alloc = &device->alloc;
1668
1669 pipeline->device = device;
1670 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
1671
1672 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
1673 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
1674 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
1675 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
1676 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
1677 pStages[stage] = &pCreateInfo->pStages[i];
1678 modules[stage] = radv_shader_module_from_handle(pStages[stage]->module);
1679 }
1680
1681 radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
1682
1683 if (modules[MESA_SHADER_VERTEX]) {
1684 bool as_es = modules[MESA_SHADER_GEOMETRY] != NULL;
1685 union ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo, as_es);
1686
1687 pipeline->shaders[MESA_SHADER_VERTEX] =
1688 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_VERTEX],
1689 pStages[MESA_SHADER_VERTEX]->pName,
1690 MESA_SHADER_VERTEX,
1691 pStages[MESA_SHADER_VERTEX]->pSpecializationInfo,
1692 pipeline->layout, &key);
1693
1694 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_VERTEX);
1695 }
1696
1697 if (modules[MESA_SHADER_GEOMETRY]) {
1698 union ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo, false);
1699
1700 pipeline->shaders[MESA_SHADER_GEOMETRY] =
1701 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_GEOMETRY],
1702 pStages[MESA_SHADER_GEOMETRY]->pName,
1703 MESA_SHADER_GEOMETRY,
1704 pStages[MESA_SHADER_GEOMETRY]->pSpecializationInfo,
1705 pipeline->layout, &key);
1706
1707 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_GEOMETRY);
1708 calculate_gs_ring_sizes(pipeline);
1709
1710 pipeline->graphics.vgt_gs_mode = si_vgt_gs_mode(pipeline->shaders[MESA_SHADER_GEOMETRY]);
1711 } else
1712 pipeline->graphics.vgt_gs_mode = 0;
1713
1714 if (!modules[MESA_SHADER_FRAGMENT]) {
1715 nir_builder fs_b;
1716 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
1717 fs_b.shader->info->name = ralloc_strdup(fs_b.shader, "noop_fs");
1718 fs_m.nir = fs_b.shader;
1719 modules[MESA_SHADER_FRAGMENT] = &fs_m;
1720 }
1721
1722 if (modules[MESA_SHADER_FRAGMENT]) {
1723 union ac_shader_variant_key key;
1724 key.fs.col_format = pipeline->graphics.blend.spi_shader_col_format;
1725 key.fs.is_int8 = radv_pipeline_compute_is_int8(pCreateInfo);
1726
1727 const VkPipelineShaderStageCreateInfo *stage = pStages[MESA_SHADER_FRAGMENT];
1728
1729 pipeline->shaders[MESA_SHADER_FRAGMENT] =
1730 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_FRAGMENT],
1731 stage ? stage->pName : "main",
1732 MESA_SHADER_FRAGMENT,
1733 stage ? stage->pSpecializationInfo : NULL,
1734 pipeline->layout, &key);
1735 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_FRAGMENT);
1736 }
1737
1738 if (fs_m.nir)
1739 ralloc_free(fs_m.nir);
1740
1741 radv_pipeline_init_depth_stencil_state(pipeline, pCreateInfo, extra);
1742 radv_pipeline_init_raster_state(pipeline, pCreateInfo);
1743 radv_pipeline_init_multisample_state(pipeline, pCreateInfo);
1744 pipeline->graphics.prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
1745 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
1746
1747 if (radv_pipeline_has_gs(pipeline)) {
1748 pipeline->graphics.gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
1749 pipeline->graphics.can_use_guardband = pipeline->graphics.gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1750 } else {
1751 pipeline->graphics.gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
1752 }
1753 if (extra && extra->use_rectlist) {
1754 pipeline->graphics.prim = V_008958_DI_PT_RECTLIST;
1755 pipeline->graphics.gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1756 pipeline->graphics.can_use_guardband = true;
1757 }
1758 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
1759 /* prim vertex count will need TESS changes */
1760 pipeline->graphics.prim_vertex_count = prim_size_table[pipeline->graphics.prim];
1761
1762 /* Ensure that some export memory is always allocated, for two reasons:
1763 *
1764 * 1) Correctness: The hardware ignores the EXEC mask if no export
1765 * memory is allocated, so KILL and alpha test do not work correctly
1766 * without this.
1767 * 2) Performance: Every shader needs at least a NULL export, even when
1768 * it writes no color/depth output. The NULL export instruction
1769 * stalls without this setting.
1770 *
1771 * Don't add this to CB_SHADER_MASK.
1772 */
1773 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
1774 if (!pipeline->graphics.blend.spi_shader_col_format) {
1775 if (!ps->info.fs.writes_z &&
1776 !ps->info.fs.writes_stencil &&
1777 !ps->info.fs.writes_sample_mask)
1778 pipeline->graphics.blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1779 }
1780
1781 unsigned z_order;
1782 pipeline->graphics.db_shader_control = 0;
1783 if (ps->info.fs.early_fragment_test || !ps->info.fs.writes_memory)
1784 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
1785 else
1786 z_order = V_02880C_LATE_Z;
1787
1788 pipeline->graphics.db_shader_control =
1789 S_02880C_Z_EXPORT_ENABLE(ps->info.fs.writes_z) |
1790 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.fs.writes_stencil) |
1791 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
1792 S_02880C_MASK_EXPORT_ENABLE(ps->info.fs.writes_sample_mask) |
1793 S_02880C_Z_ORDER(z_order) |
1794 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
1795 S_02880C_EXEC_ON_HIER_FAIL(ps->info.fs.writes_memory) |
1796 S_02880C_EXEC_ON_NOOP(ps->info.fs.writes_memory);
1797
1798 pipeline->graphics.shader_z_format =
1799 ps->info.fs.writes_sample_mask ? V_028710_SPI_SHADER_32_ABGR :
1800 ps->info.fs.writes_stencil ? V_028710_SPI_SHADER_32_GR :
1801 ps->info.fs.writes_z ? V_028710_SPI_SHADER_32_R :
1802 V_028710_SPI_SHADER_ZERO;
1803
1804 calculate_pa_cl_vs_out_cntl(pipeline);
1805 calculate_ps_inputs(pipeline);
1806
1807 uint32_t stages = 0;
1808 if (radv_pipeline_has_gs(pipeline))
1809 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
1810 S_028B54_GS_EN(1) |
1811 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1812 pipeline->graphics.vgt_shader_stages_en = stages;
1813
1814 const VkPipelineVertexInputStateCreateInfo *vi_info =
1815 pCreateInfo->pVertexInputState;
1816 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
1817 const VkVertexInputAttributeDescription *desc =
1818 &vi_info->pVertexAttributeDescriptions[i];
1819 unsigned loc = desc->location;
1820 const struct vk_format_description *format_desc;
1821 int first_non_void;
1822 uint32_t num_format, data_format;
1823 format_desc = vk_format_description(desc->format);
1824 first_non_void = vk_format_get_first_non_void_channel(desc->format);
1825
1826 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
1827 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
1828
1829 pipeline->va_rsrc_word3[loc] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc->swizzle[0])) |
1830 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc->swizzle[1])) |
1831 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc->swizzle[2])) |
1832 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc->swizzle[3])) |
1833 S_008F0C_NUM_FORMAT(num_format) |
1834 S_008F0C_DATA_FORMAT(data_format);
1835 pipeline->va_format_size[loc] = format_desc->block.bits / 8;
1836 pipeline->va_offset[loc] = desc->offset;
1837 pipeline->va_binding[loc] = desc->binding;
1838 pipeline->num_vertex_attribs = MAX2(pipeline->num_vertex_attribs, loc + 1);
1839 }
1840
1841 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
1842 const VkVertexInputBindingDescription *desc =
1843 &vi_info->pVertexBindingDescriptions[i];
1844
1845 pipeline->binding_stride[desc->binding] = desc->stride;
1846 }
1847
1848 if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
1849 radv_dump_pipeline_stats(device, pipeline);
1850 }
1851
1852 result = radv_pipeline_scratch_init(device, pipeline);
1853 return result;
1854 }
1855
1856 VkResult
1857 radv_graphics_pipeline_create(
1858 VkDevice _device,
1859 VkPipelineCache _cache,
1860 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1861 const struct radv_graphics_pipeline_create_info *extra,
1862 const VkAllocationCallbacks *pAllocator,
1863 VkPipeline *pPipeline)
1864 {
1865 RADV_FROM_HANDLE(radv_device, device, _device);
1866 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
1867 struct radv_pipeline *pipeline;
1868 VkResult result;
1869
1870 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
1871 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1872 if (pipeline == NULL)
1873 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1874
1875 memset(pipeline, 0, sizeof(*pipeline));
1876 result = radv_pipeline_init(pipeline, device, cache,
1877 pCreateInfo, extra, pAllocator);
1878 if (result != VK_SUCCESS) {
1879 radv_pipeline_destroy(device, pipeline, pAllocator);
1880 return result;
1881 }
1882
1883 *pPipeline = radv_pipeline_to_handle(pipeline);
1884
1885 return VK_SUCCESS;
1886 }
1887
1888 VkResult radv_CreateGraphicsPipelines(
1889 VkDevice _device,
1890 VkPipelineCache pipelineCache,
1891 uint32_t count,
1892 const VkGraphicsPipelineCreateInfo* pCreateInfos,
1893 const VkAllocationCallbacks* pAllocator,
1894 VkPipeline* pPipelines)
1895 {
1896 VkResult result = VK_SUCCESS;
1897 unsigned i = 0;
1898
1899 for (; i < count; i++) {
1900 VkResult r;
1901 r = radv_graphics_pipeline_create(_device,
1902 pipelineCache,
1903 &pCreateInfos[i],
1904 NULL, pAllocator, &pPipelines[i]);
1905 if (r != VK_SUCCESS) {
1906 result = r;
1907 pPipelines[i] = VK_NULL_HANDLE;
1908 }
1909 }
1910
1911 return result;
1912 }
1913
1914 static VkResult radv_compute_pipeline_create(
1915 VkDevice _device,
1916 VkPipelineCache _cache,
1917 const VkComputePipelineCreateInfo* pCreateInfo,
1918 const VkAllocationCallbacks* pAllocator,
1919 VkPipeline* pPipeline)
1920 {
1921 RADV_FROM_HANDLE(radv_device, device, _device);
1922 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
1923 RADV_FROM_HANDLE(radv_shader_module, module, pCreateInfo->stage.module);
1924 struct radv_pipeline *pipeline;
1925 VkResult result;
1926
1927 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
1928 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1929 if (pipeline == NULL)
1930 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1931
1932 memset(pipeline, 0, sizeof(*pipeline));
1933 pipeline->device = device;
1934 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
1935
1936 pipeline->shaders[MESA_SHADER_COMPUTE] =
1937 radv_pipeline_compile(pipeline, cache, module,
1938 pCreateInfo->stage.pName,
1939 MESA_SHADER_COMPUTE,
1940 pCreateInfo->stage.pSpecializationInfo,
1941 pipeline->layout, NULL);
1942
1943
1944 result = radv_pipeline_scratch_init(device, pipeline);
1945 if (result != VK_SUCCESS) {
1946 radv_pipeline_destroy(device, pipeline, pAllocator);
1947 return result;
1948 }
1949
1950 *pPipeline = radv_pipeline_to_handle(pipeline);
1951
1952 if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
1953 radv_dump_pipeline_stats(device, pipeline);
1954 }
1955 return VK_SUCCESS;
1956 }
1957 VkResult radv_CreateComputePipelines(
1958 VkDevice _device,
1959 VkPipelineCache pipelineCache,
1960 uint32_t count,
1961 const VkComputePipelineCreateInfo* pCreateInfos,
1962 const VkAllocationCallbacks* pAllocator,
1963 VkPipeline* pPipelines)
1964 {
1965 VkResult result = VK_SUCCESS;
1966
1967 unsigned i = 0;
1968 for (; i < count; i++) {
1969 VkResult r;
1970 r = radv_compute_pipeline_create(_device, pipelineCache,
1971 &pCreateInfos[i],
1972 pAllocator, &pPipelines[i]);
1973 if (r != VK_SUCCESS) {
1974 result = r;
1975 pPipelines[i] = VK_NULL_HANDLE;
1976 }
1977 }
1978
1979 return result;
1980 }