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radv: move db_shader_control calculation to pipeline.
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "radv_private.h"
30 #include "nir/nir.h"
31 #include "nir/nir_builder.h"
32 #include "spirv/nir_spirv.h"
33
34 #include <llvm-c/Core.h>
35 #include <llvm-c/TargetMachine.h>
36
37 #include "sid.h"
38 #include "r600d_common.h"
39 #include "ac_binary.h"
40 #include "ac_llvm_util.h"
41 #include "ac_nir_to_llvm.h"
42 #include "vk_format.h"
43 #include "util/debug.h"
44
45 void radv_shader_variant_destroy(struct radv_device *device,
46 struct radv_shader_variant *variant);
47
48 static const struct nir_shader_compiler_options nir_options = {
49 .vertex_id_zero_based = true,
50 .lower_scmp = true,
51 .lower_flrp32 = true,
52 .lower_fsat = true,
53 .lower_pack_snorm_2x16 = true,
54 .lower_pack_snorm_4x8 = true,
55 .lower_pack_unorm_2x16 = true,
56 .lower_pack_unorm_4x8 = true,
57 .lower_unpack_snorm_2x16 = true,
58 .lower_unpack_snorm_4x8 = true,
59 .lower_unpack_unorm_2x16 = true,
60 .lower_unpack_unorm_4x8 = true,
61 .lower_extract_byte = true,
62 .lower_extract_word = true,
63 };
64
65 VkResult radv_CreateShaderModule(
66 VkDevice _device,
67 const VkShaderModuleCreateInfo* pCreateInfo,
68 const VkAllocationCallbacks* pAllocator,
69 VkShaderModule* pShaderModule)
70 {
71 RADV_FROM_HANDLE(radv_device, device, _device);
72 struct radv_shader_module *module;
73
74 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
75 assert(pCreateInfo->flags == 0);
76
77 module = vk_alloc2(&device->alloc, pAllocator,
78 sizeof(*module) + pCreateInfo->codeSize, 8,
79 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
80 if (module == NULL)
81 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
82
83 module->nir = NULL;
84 module->size = pCreateInfo->codeSize;
85 memcpy(module->data, pCreateInfo->pCode, module->size);
86
87 _mesa_sha1_compute(module->data, module->size, module->sha1);
88
89 *pShaderModule = radv_shader_module_to_handle(module);
90
91 return VK_SUCCESS;
92 }
93
94 void radv_DestroyShaderModule(
95 VkDevice _device,
96 VkShaderModule _module,
97 const VkAllocationCallbacks* pAllocator)
98 {
99 RADV_FROM_HANDLE(radv_device, device, _device);
100 RADV_FROM_HANDLE(radv_shader_module, module, _module);
101
102 if (!module)
103 return;
104
105 vk_free2(&device->alloc, pAllocator, module);
106 }
107
108
109 static void
110 radv_pipeline_destroy(struct radv_device *device,
111 struct radv_pipeline *pipeline,
112 const VkAllocationCallbacks* allocator)
113 {
114 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
115 if (pipeline->shaders[i])
116 radv_shader_variant_destroy(device, pipeline->shaders[i]);
117
118 if (pipeline->gs_copy_shader)
119 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
120
121 vk_free2(&device->alloc, allocator, pipeline);
122 }
123
124 void radv_DestroyPipeline(
125 VkDevice _device,
126 VkPipeline _pipeline,
127 const VkAllocationCallbacks* pAllocator)
128 {
129 RADV_FROM_HANDLE(radv_device, device, _device);
130 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
131
132 if (!_pipeline)
133 return;
134
135 radv_pipeline_destroy(device, pipeline, pAllocator);
136 }
137
138
139 static void
140 radv_optimize_nir(struct nir_shader *shader)
141 {
142 bool progress;
143
144 do {
145 progress = false;
146
147 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
148 NIR_PASS_V(shader, nir_lower_alu_to_scalar);
149 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
150
151 NIR_PASS(progress, shader, nir_copy_prop);
152 NIR_PASS(progress, shader, nir_opt_remove_phis);
153 NIR_PASS(progress, shader, nir_opt_dce);
154 NIR_PASS(progress, shader, nir_opt_dead_cf);
155 NIR_PASS(progress, shader, nir_opt_cse);
156 NIR_PASS(progress, shader, nir_opt_peephole_select, 8);
157 NIR_PASS(progress, shader, nir_opt_algebraic);
158 NIR_PASS(progress, shader, nir_opt_constant_folding);
159 NIR_PASS(progress, shader, nir_opt_undef);
160 NIR_PASS(progress, shader, nir_opt_conditional_discard);
161 } while (progress);
162 }
163
164 static nir_shader *
165 radv_shader_compile_to_nir(struct radv_device *device,
166 struct radv_shader_module *module,
167 const char *entrypoint_name,
168 gl_shader_stage stage,
169 const VkSpecializationInfo *spec_info,
170 bool dump)
171 {
172 if (strcmp(entrypoint_name, "main") != 0) {
173 radv_finishme("Multiple shaders per module not really supported");
174 }
175
176 nir_shader *nir;
177 nir_function *entry_point;
178 if (module->nir) {
179 /* Some things such as our meta clear/blit code will give us a NIR
180 * shader directly. In that case, we just ignore the SPIR-V entirely
181 * and just use the NIR shader */
182 nir = module->nir;
183 nir->options = &nir_options;
184 nir_validate_shader(nir);
185
186 assert(exec_list_length(&nir->functions) == 1);
187 struct exec_node *node = exec_list_get_head(&nir->functions);
188 entry_point = exec_node_data(nir_function, node, node);
189 } else {
190 uint32_t *spirv = (uint32_t *) module->data;
191 assert(module->size % 4 == 0);
192
193 uint32_t num_spec_entries = 0;
194 struct nir_spirv_specialization *spec_entries = NULL;
195 if (spec_info && spec_info->mapEntryCount > 0) {
196 num_spec_entries = spec_info->mapEntryCount;
197 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
198 for (uint32_t i = 0; i < num_spec_entries; i++) {
199 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
200 const void *data = spec_info->pData + entry.offset;
201 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
202
203 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
204 if (spec_info->dataSize == 8)
205 spec_entries[i].data64 = *(const uint64_t *)data;
206 else
207 spec_entries[i].data32 = *(const uint32_t *)data;
208 }
209 }
210 const struct nir_spirv_supported_extensions supported_ext = {
211 .draw_parameters = true,
212 .float64 = true,
213 .image_read_without_format = true,
214 .image_write_without_format = true,
215 };
216 entry_point = spirv_to_nir(spirv, module->size / 4,
217 spec_entries, num_spec_entries,
218 stage, entrypoint_name, &supported_ext, &nir_options);
219 nir = entry_point->shader;
220 assert(nir->stage == stage);
221 nir_validate_shader(nir);
222
223 free(spec_entries);
224
225 /* We have to lower away local constant initializers right before we
226 * inline functions. That way they get properly initialized at the top
227 * of the function and not at the top of its caller.
228 */
229 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_local);
230 NIR_PASS_V(nir, nir_lower_returns);
231 NIR_PASS_V(nir, nir_inline_functions);
232
233 /* Pick off the single entrypoint that we want */
234 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
235 if (func != entry_point)
236 exec_node_remove(&func->node);
237 }
238 assert(exec_list_length(&nir->functions) == 1);
239 entry_point->name = ralloc_strdup(entry_point, "main");
240
241 NIR_PASS_V(nir, nir_remove_dead_variables,
242 nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
243
244 /* Now that we've deleted all but the main function, we can go ahead and
245 * lower the rest of the constant initializers.
246 */
247 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
248 NIR_PASS_V(nir, nir_lower_system_values);
249 }
250
251 /* Vulkan uses the separate-shader linking model */
252 nir->info->separate_shader = true;
253
254 nir_shader_gather_info(nir, entry_point->impl);
255
256 nir_variable_mode indirect_mask = 0;
257 indirect_mask |= nir_var_shader_in;
258 indirect_mask |= nir_var_local;
259
260 nir_lower_indirect_derefs(nir, indirect_mask);
261
262 static const nir_lower_tex_options tex_options = {
263 .lower_txp = ~0,
264 };
265
266 nir_lower_tex(nir, &tex_options);
267
268 nir_lower_vars_to_ssa(nir);
269 nir_lower_var_copies(nir);
270 nir_lower_global_vars_to_local(nir);
271 nir_remove_dead_variables(nir, nir_var_local);
272 radv_optimize_nir(nir);
273
274 if (dump)
275 nir_print_shader(nir, stderr);
276
277 return nir;
278 }
279
280 static const char *radv_get_shader_name(struct radv_shader_variant *var,
281 gl_shader_stage stage)
282 {
283 switch (stage) {
284 case MESA_SHADER_VERTEX: return var->info.vs.as_es ? "Vertex Shader as ES" : "Vertex Shader as VS";
285 case MESA_SHADER_GEOMETRY: return "Geometry Shader";
286 case MESA_SHADER_FRAGMENT: return "Pixel Shader";
287 case MESA_SHADER_COMPUTE: return "Compute Shader";
288 default:
289 return "Unknown shader";
290 };
291
292 }
293 static void radv_dump_pipeline_stats(struct radv_device *device, struct radv_pipeline *pipeline)
294 {
295 unsigned lds_increment = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
296 struct radv_shader_variant *var;
297 struct ac_shader_config *conf;
298 int i;
299 FILE *file = stderr;
300 unsigned max_simd_waves = 10;
301 unsigned lds_per_wave = 0;
302
303 for (i = 0; i < MESA_SHADER_STAGES; i++) {
304 if (!pipeline->shaders[i])
305 continue;
306 var = pipeline->shaders[i];
307
308 conf = &var->config;
309
310 if (i == MESA_SHADER_FRAGMENT) {
311 lds_per_wave = conf->lds_size * lds_increment +
312 align(var->info.fs.num_interp * 48, lds_increment);
313 }
314
315 if (conf->num_sgprs) {
316 if (device->physical_device->rad_info.chip_class >= VI)
317 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
318 else
319 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
320 }
321
322 if (conf->num_vgprs)
323 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
324
325 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
326 * that PS can use.
327 */
328 if (lds_per_wave)
329 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
330
331 fprintf(file, "\n%s:\n",
332 radv_get_shader_name(var, i));
333 if (i == MESA_SHADER_FRAGMENT) {
334 fprintf(file, "*** SHADER CONFIG ***\n"
335 "SPI_PS_INPUT_ADDR = 0x%04x\n"
336 "SPI_PS_INPUT_ENA = 0x%04x\n",
337 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
338 }
339 fprintf(file, "*** SHADER STATS ***\n"
340 "SGPRS: %d\n"
341 "VGPRS: %d\n"
342 "Spilled SGPRs: %d\n"
343 "Spilled VGPRs: %d\n"
344 "Code Size: %d bytes\n"
345 "LDS: %d blocks\n"
346 "Scratch: %d bytes per wave\n"
347 "Max Waves: %d\n"
348 "********************\n\n\n",
349 conf->num_sgprs, conf->num_vgprs,
350 conf->spilled_sgprs, conf->spilled_vgprs, var->code_size,
351 conf->lds_size, conf->scratch_bytes_per_wave,
352 max_simd_waves);
353 }
354 }
355
356 void radv_shader_variant_destroy(struct radv_device *device,
357 struct radv_shader_variant *variant)
358 {
359 if (__sync_fetch_and_sub(&variant->ref_count, 1) != 1)
360 return;
361
362 device->ws->buffer_destroy(variant->bo);
363 free(variant);
364 }
365
366 static void radv_fill_shader_variant(struct radv_device *device,
367 struct radv_shader_variant *variant,
368 struct ac_shader_binary *binary,
369 gl_shader_stage stage)
370 {
371 bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0;
372 unsigned vgpr_comp_cnt = 0;
373
374 if (scratch_enabled && !device->llvm_supports_spill)
375 radv_finishme("shader scratch support only available with LLVM 4.0");
376
377 variant->code_size = binary->code_size;
378
379 switch (stage) {
380 case MESA_SHADER_VERTEX:
381 case MESA_SHADER_GEOMETRY:
382 variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
383 S_00B12C_SCRATCH_EN(scratch_enabled);
384 vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
385 break;
386 case MESA_SHADER_FRAGMENT:
387 variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
388 S_00B12C_SCRATCH_EN(scratch_enabled);
389 break;
390 case MESA_SHADER_COMPUTE:
391 variant->rsrc2 = S_00B84C_USER_SGPR(variant->info.num_user_sgprs) |
392 S_00B84C_SCRATCH_EN(scratch_enabled) |
393 S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) |
394 S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) |
395 S_00B84C_TG_SIZE_EN(1) |
396 S_00B84C_LDS_SIZE(variant->config.lds_size);
397 break;
398 default:
399 unreachable("unsupported shader type");
400 break;
401 }
402
403 variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
404 S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) |
405 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
406 S_00B848_DX10_CLAMP(1) |
407 S_00B848_FLOAT_MODE(variant->config.float_mode);
408
409 variant->bo = device->ws->buffer_create(device->ws, binary->code_size, 256,
410 RADEON_DOMAIN_VRAM, RADEON_FLAG_CPU_ACCESS);
411
412 void *ptr = device->ws->buffer_map(variant->bo);
413 memcpy(ptr, binary->code, binary->code_size);
414 device->ws->buffer_unmap(variant->bo);
415
416
417 }
418
419 static struct radv_shader_variant *radv_shader_variant_create(struct radv_device *device,
420 struct nir_shader *shader,
421 struct radv_pipeline_layout *layout,
422 const union ac_shader_variant_key *key,
423 void** code_out,
424 unsigned *code_size_out,
425 bool dump)
426 {
427 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
428 enum radeon_family chip_family = device->physical_device->rad_info.family;
429 LLVMTargetMachineRef tm;
430 if (!variant)
431 return NULL;
432
433 struct ac_nir_compiler_options options = {0};
434 options.layout = layout;
435 if (key)
436 options.key = *key;
437
438 struct ac_shader_binary binary;
439
440 options.unsafe_math = !!(device->debug_flags & RADV_DEBUG_UNSAFE_MATH);
441 options.family = chip_family;
442 options.chip_class = device->physical_device->rad_info.chip_class;
443 options.supports_spill = device->llvm_supports_spill;
444 tm = ac_create_target_machine(chip_family, options.supports_spill);
445 ac_compile_nir_shader(tm, &binary, &variant->config,
446 &variant->info, shader, &options, dump);
447 LLVMDisposeTargetMachine(tm);
448
449 radv_fill_shader_variant(device, variant, &binary, shader->stage);
450
451 if (code_out) {
452 *code_out = binary.code;
453 *code_size_out = binary.code_size;
454 } else
455 free(binary.code);
456 free(binary.config);
457 free(binary.rodata);
458 free(binary.global_symbol_offsets);
459 free(binary.relocs);
460 free(binary.disasm_string);
461 variant->ref_count = 1;
462 return variant;
463 }
464
465 static struct radv_shader_variant *
466 radv_pipeline_create_gs_copy_shader(struct radv_pipeline *pipeline,
467 struct nir_shader *nir,
468 void** code_out,
469 unsigned *code_size_out,
470 bool dump_shader)
471 {
472 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
473 enum radeon_family chip_family = pipeline->device->physical_device->rad_info.family;
474 LLVMTargetMachineRef tm;
475 if (!variant)
476 return NULL;
477
478 struct ac_nir_compiler_options options = {0};
479 struct ac_shader_binary binary;
480 options.family = chip_family;
481 options.chip_class = pipeline->device->physical_device->rad_info.chip_class;
482 options.supports_spill = pipeline->device->llvm_supports_spill;
483 tm = ac_create_target_machine(chip_family, options.supports_spill);
484 ac_create_gs_copy_shader(tm, nir, &binary, &variant->config, &variant->info, &options, dump_shader);
485 LLVMDisposeTargetMachine(tm);
486
487 radv_fill_shader_variant(pipeline->device, variant, &binary, MESA_SHADER_VERTEX);
488
489 if (code_out) {
490 *code_out = binary.code;
491 *code_size_out = binary.code_size;
492 } else
493 free(binary.code);
494 free(binary.config);
495 free(binary.rodata);
496 free(binary.global_symbol_offsets);
497 free(binary.relocs);
498 free(binary.disasm_string);
499 variant->ref_count = 1;
500 return variant;
501 }
502
503 static struct radv_shader_variant *
504 radv_pipeline_compile(struct radv_pipeline *pipeline,
505 struct radv_pipeline_cache *cache,
506 struct radv_shader_module *module,
507 const char *entrypoint,
508 gl_shader_stage stage,
509 const VkSpecializationInfo *spec_info,
510 struct radv_pipeline_layout *layout,
511 const union ac_shader_variant_key *key)
512 {
513 unsigned char sha1[20];
514 unsigned char gs_copy_sha1[20];
515 struct radv_shader_variant *variant;
516 nir_shader *nir;
517 void *code = NULL;
518 unsigned code_size = 0;
519 bool dump = (pipeline->device->debug_flags & RADV_DEBUG_DUMP_SHADERS);
520
521 if (module->nir)
522 _mesa_sha1_compute(module->nir->info->name,
523 strlen(module->nir->info->name),
524 module->sha1);
525
526 radv_hash_shader(sha1, module, entrypoint, spec_info, layout, key, 0);
527 if (stage == MESA_SHADER_GEOMETRY)
528 radv_hash_shader(gs_copy_sha1, module, entrypoint, spec_info,
529 layout, key, 1);
530
531 variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
532 cache,
533 sha1);
534
535 if (stage == MESA_SHADER_GEOMETRY) {
536 pipeline->gs_copy_shader =
537 radv_create_shader_variant_from_pipeline_cache(
538 pipeline->device,
539 cache,
540 gs_copy_sha1);
541 }
542
543 if (variant &&
544 (stage != MESA_SHADER_GEOMETRY || pipeline->gs_copy_shader))
545 return variant;
546
547 nir = radv_shader_compile_to_nir(pipeline->device,
548 module, entrypoint, stage,
549 spec_info, dump);
550 if (nir == NULL)
551 return NULL;
552
553 if (!variant) {
554 variant = radv_shader_variant_create(pipeline->device, nir,
555 layout, key, &code,
556 &code_size, dump);
557 }
558
559 if (stage == MESA_SHADER_GEOMETRY && !pipeline->gs_copy_shader) {
560 void *gs_copy_code = NULL;
561 unsigned gs_copy_code_size = 0;
562 pipeline->gs_copy_shader = radv_pipeline_create_gs_copy_shader(
563 pipeline, nir, &gs_copy_code, &gs_copy_code_size, dump);
564
565 if (pipeline->gs_copy_shader) {
566 pipeline->gs_copy_shader =
567 radv_pipeline_cache_insert_shader(cache,
568 gs_copy_sha1,
569 pipeline->gs_copy_shader,
570 gs_copy_code,
571 gs_copy_code_size);
572 }
573 }
574 if (!module->nir)
575 ralloc_free(nir);
576
577 if (variant)
578 variant = radv_pipeline_cache_insert_shader(cache, sha1, variant,
579 code, code_size);
580
581 if (code)
582 free(code);
583 return variant;
584 }
585
586 static VkResult
587 radv_pipeline_scratch_init(struct radv_device *device,
588 struct radv_pipeline *pipeline)
589 {
590 unsigned scratch_bytes_per_wave = 0;
591 unsigned max_waves = 0;
592 unsigned min_waves = 1;
593
594 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
595 if (pipeline->shaders[i]) {
596 unsigned max_stage_waves = device->scratch_waves;
597
598 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
599 pipeline->shaders[i]->config.scratch_bytes_per_wave);
600
601 max_stage_waves = MIN2(max_stage_waves,
602 4 * device->physical_device->rad_info.num_good_compute_units *
603 (256 / pipeline->shaders[i]->config.num_vgprs));
604 max_waves = MAX2(max_waves, max_stage_waves);
605 }
606 }
607
608 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
609 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
610 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
611 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
612 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
613 }
614
615 if (scratch_bytes_per_wave)
616 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
617
618 if (scratch_bytes_per_wave && max_waves < min_waves) {
619 /* Not really true at this moment, but will be true on first
620 * execution. Avoid having hanging shaders. */
621 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
622 }
623 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
624 pipeline->max_waves = max_waves;
625 return VK_SUCCESS;
626 }
627
628 static uint32_t si_translate_blend_function(VkBlendOp op)
629 {
630 switch (op) {
631 case VK_BLEND_OP_ADD:
632 return V_028780_COMB_DST_PLUS_SRC;
633 case VK_BLEND_OP_SUBTRACT:
634 return V_028780_COMB_SRC_MINUS_DST;
635 case VK_BLEND_OP_REVERSE_SUBTRACT:
636 return V_028780_COMB_DST_MINUS_SRC;
637 case VK_BLEND_OP_MIN:
638 return V_028780_COMB_MIN_DST_SRC;
639 case VK_BLEND_OP_MAX:
640 return V_028780_COMB_MAX_DST_SRC;
641 default:
642 return 0;
643 }
644 }
645
646 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
647 {
648 switch (factor) {
649 case VK_BLEND_FACTOR_ZERO:
650 return V_028780_BLEND_ZERO;
651 case VK_BLEND_FACTOR_ONE:
652 return V_028780_BLEND_ONE;
653 case VK_BLEND_FACTOR_SRC_COLOR:
654 return V_028780_BLEND_SRC_COLOR;
655 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
656 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
657 case VK_BLEND_FACTOR_DST_COLOR:
658 return V_028780_BLEND_DST_COLOR;
659 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
660 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
661 case VK_BLEND_FACTOR_SRC_ALPHA:
662 return V_028780_BLEND_SRC_ALPHA;
663 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
664 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
665 case VK_BLEND_FACTOR_DST_ALPHA:
666 return V_028780_BLEND_DST_ALPHA;
667 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
668 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
669 case VK_BLEND_FACTOR_CONSTANT_COLOR:
670 return V_028780_BLEND_CONSTANT_COLOR;
671 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
672 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
673 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
674 return V_028780_BLEND_CONSTANT_ALPHA;
675 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
676 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
677 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
678 return V_028780_BLEND_SRC_ALPHA_SATURATE;
679 case VK_BLEND_FACTOR_SRC1_COLOR:
680 return V_028780_BLEND_SRC1_COLOR;
681 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
682 return V_028780_BLEND_INV_SRC1_COLOR;
683 case VK_BLEND_FACTOR_SRC1_ALPHA:
684 return V_028780_BLEND_SRC1_ALPHA;
685 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
686 return V_028780_BLEND_INV_SRC1_ALPHA;
687 default:
688 return 0;
689 }
690 }
691
692 static bool is_dual_src(VkBlendFactor factor)
693 {
694 switch (factor) {
695 case VK_BLEND_FACTOR_SRC1_COLOR:
696 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
697 case VK_BLEND_FACTOR_SRC1_ALPHA:
698 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
699 return true;
700 default:
701 return false;
702 }
703 }
704
705 static unsigned si_choose_spi_color_format(VkFormat vk_format,
706 bool blend_enable,
707 bool blend_need_alpha)
708 {
709 const struct vk_format_description *desc = vk_format_description(vk_format);
710 unsigned format, ntype, swap;
711
712 /* Alpha is needed for alpha-to-coverage.
713 * Blending may be with or without alpha.
714 */
715 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
716 unsigned alpha = 0; /* exports alpha, but may not support blending */
717 unsigned blend = 0; /* supports blending, but may not export alpha */
718 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
719
720 format = radv_translate_colorformat(vk_format);
721 ntype = radv_translate_color_numformat(vk_format, desc,
722 vk_format_get_first_non_void_channel(vk_format));
723 swap = radv_translate_colorswap(vk_format, false);
724
725 /* Choose the SPI color formats. These are required values for Stoney/RB+.
726 * Other chips have multiple choices, though they are not necessarily better.
727 */
728 switch (format) {
729 case V_028C70_COLOR_5_6_5:
730 case V_028C70_COLOR_1_5_5_5:
731 case V_028C70_COLOR_5_5_5_1:
732 case V_028C70_COLOR_4_4_4_4:
733 case V_028C70_COLOR_10_11_11:
734 case V_028C70_COLOR_11_11_10:
735 case V_028C70_COLOR_8:
736 case V_028C70_COLOR_8_8:
737 case V_028C70_COLOR_8_8_8_8:
738 case V_028C70_COLOR_10_10_10_2:
739 case V_028C70_COLOR_2_10_10_10:
740 if (ntype == V_028C70_NUMBER_UINT)
741 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
742 else if (ntype == V_028C70_NUMBER_SINT)
743 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
744 else
745 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
746 break;
747
748 case V_028C70_COLOR_16:
749 case V_028C70_COLOR_16_16:
750 case V_028C70_COLOR_16_16_16_16:
751 if (ntype == V_028C70_NUMBER_UNORM ||
752 ntype == V_028C70_NUMBER_SNORM) {
753 /* UNORM16 and SNORM16 don't support blending */
754 if (ntype == V_028C70_NUMBER_UNORM)
755 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
756 else
757 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
758
759 /* Use 32 bits per channel for blending. */
760 if (format == V_028C70_COLOR_16) {
761 if (swap == V_028C70_SWAP_STD) { /* R */
762 blend = V_028714_SPI_SHADER_32_R;
763 blend_alpha = V_028714_SPI_SHADER_32_AR;
764 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
765 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
766 else
767 assert(0);
768 } else if (format == V_028C70_COLOR_16_16) {
769 if (swap == V_028C70_SWAP_STD) { /* RG */
770 blend = V_028714_SPI_SHADER_32_GR;
771 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
772 } else if (swap == V_028C70_SWAP_ALT) /* RA */
773 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
774 else
775 assert(0);
776 } else /* 16_16_16_16 */
777 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
778 } else if (ntype == V_028C70_NUMBER_UINT)
779 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
780 else if (ntype == V_028C70_NUMBER_SINT)
781 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
782 else if (ntype == V_028C70_NUMBER_FLOAT)
783 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
784 else
785 assert(0);
786 break;
787
788 case V_028C70_COLOR_32:
789 if (swap == V_028C70_SWAP_STD) { /* R */
790 blend = normal = V_028714_SPI_SHADER_32_R;
791 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
792 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
793 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
794 else
795 assert(0);
796 break;
797
798 case V_028C70_COLOR_32_32:
799 if (swap == V_028C70_SWAP_STD) { /* RG */
800 blend = normal = V_028714_SPI_SHADER_32_GR;
801 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
802 } else if (swap == V_028C70_SWAP_ALT) /* RA */
803 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
804 else
805 assert(0);
806 break;
807
808 case V_028C70_COLOR_32_32_32_32:
809 case V_028C70_COLOR_8_24:
810 case V_028C70_COLOR_24_8:
811 case V_028C70_COLOR_X24_8_32_FLOAT:
812 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
813 break;
814
815 default:
816 unreachable("unhandled blend format");
817 }
818
819 if (blend_enable && blend_need_alpha)
820 return blend_alpha;
821 else if(blend_need_alpha)
822 return alpha;
823 else if(blend_enable)
824 return blend;
825 else
826 return normal;
827 }
828
829 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
830 {
831 unsigned i, cb_shader_mask = 0;
832
833 for (i = 0; i < 8; i++) {
834 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
835 case V_028714_SPI_SHADER_ZERO:
836 break;
837 case V_028714_SPI_SHADER_32_R:
838 cb_shader_mask |= 0x1 << (i * 4);
839 break;
840 case V_028714_SPI_SHADER_32_GR:
841 cb_shader_mask |= 0x3 << (i * 4);
842 break;
843 case V_028714_SPI_SHADER_32_AR:
844 cb_shader_mask |= 0x9 << (i * 4);
845 break;
846 case V_028714_SPI_SHADER_FP16_ABGR:
847 case V_028714_SPI_SHADER_UNORM16_ABGR:
848 case V_028714_SPI_SHADER_SNORM16_ABGR:
849 case V_028714_SPI_SHADER_UINT16_ABGR:
850 case V_028714_SPI_SHADER_SINT16_ABGR:
851 case V_028714_SPI_SHADER_32_ABGR:
852 cb_shader_mask |= 0xf << (i * 4);
853 break;
854 default:
855 assert(0);
856 }
857 }
858 return cb_shader_mask;
859 }
860
861 static void
862 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
863 const VkGraphicsPipelineCreateInfo *pCreateInfo,
864 uint32_t blend_enable,
865 uint32_t blend_need_alpha,
866 bool single_cb_enable,
867 bool blend_mrt0_is_dual_src)
868 {
869 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
870 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
871 struct radv_blend_state *blend = &pipeline->graphics.blend;
872 unsigned col_format = 0;
873
874 for (unsigned i = 0; i < (single_cb_enable ? 1 : subpass->color_count); ++i) {
875 struct radv_render_pass_attachment *attachment;
876 unsigned cf;
877
878 attachment = pass->attachments + subpass->color_attachments[i].attachment;
879
880 cf = si_choose_spi_color_format(attachment->format,
881 blend_enable & (1 << i),
882 blend_need_alpha & (1 << i));
883
884 col_format |= cf << (4 * i);
885 }
886
887 blend->cb_shader_mask = si_get_cb_shader_mask(col_format);
888
889 if (blend_mrt0_is_dual_src)
890 col_format |= (col_format & 0xf) << 4;
891 blend->spi_shader_col_format = col_format;
892 }
893
894 static bool
895 format_is_int8(VkFormat format)
896 {
897 const struct vk_format_description *desc = vk_format_description(format);
898 int channel = vk_format_get_first_non_void_channel(format);
899
900 return channel >= 0 && desc->channel[channel].pure_integer &&
901 desc->channel[channel].size == 8;
902 }
903
904 unsigned radv_format_meta_fs_key(VkFormat format)
905 {
906 unsigned col_format = si_choose_spi_color_format(format, false, false) - 1;
907 bool is_int8 = format_is_int8(format);
908
909 return col_format + (is_int8 ? 3 : 0);
910 }
911
912 static unsigned
913 radv_pipeline_compute_is_int8(const VkGraphicsPipelineCreateInfo *pCreateInfo)
914 {
915 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
916 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
917 unsigned is_int8 = 0;
918
919 for (unsigned i = 0; i < subpass->color_count; ++i) {
920 struct radv_render_pass_attachment *attachment;
921
922 attachment = pass->attachments + subpass->color_attachments[i].attachment;
923
924 if (format_is_int8(attachment->format))
925 is_int8 |= 1 << i;
926 }
927
928 return is_int8;
929 }
930
931 static void
932 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
933 const VkGraphicsPipelineCreateInfo *pCreateInfo,
934 const struct radv_graphics_pipeline_create_info *extra)
935 {
936 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
937 struct radv_blend_state *blend = &pipeline->graphics.blend;
938 unsigned mode = V_028808_CB_NORMAL;
939 uint32_t blend_enable = 0, blend_need_alpha = 0;
940 bool blend_mrt0_is_dual_src = false;
941 int i;
942 bool single_cb_enable = false;
943
944 if (!vkblend)
945 return;
946
947 if (extra && extra->custom_blend_mode) {
948 single_cb_enable = true;
949 mode = extra->custom_blend_mode;
950 }
951 blend->cb_color_control = 0;
952 if (vkblend->logicOpEnable)
953 blend->cb_color_control |= S_028808_ROP3(vkblend->logicOp | (vkblend->logicOp << 4));
954 else
955 blend->cb_color_control |= S_028808_ROP3(0xcc);
956
957 blend->db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
958 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
959 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
960 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
961
962 blend->cb_target_mask = 0;
963 for (i = 0; i < vkblend->attachmentCount; i++) {
964 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
965 unsigned blend_cntl = 0;
966 VkBlendOp eqRGB = att->colorBlendOp;
967 VkBlendFactor srcRGB = att->srcColorBlendFactor;
968 VkBlendFactor dstRGB = att->dstColorBlendFactor;
969 VkBlendOp eqA = att->alphaBlendOp;
970 VkBlendFactor srcA = att->srcAlphaBlendFactor;
971 VkBlendFactor dstA = att->dstAlphaBlendFactor;
972
973 blend->sx_mrt0_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
974
975 if (!att->colorWriteMask)
976 continue;
977
978 blend->cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
979 if (!att->blendEnable) {
980 blend->cb_blend_control[i] = blend_cntl;
981 continue;
982 }
983
984 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
985 if (i == 0)
986 blend_mrt0_is_dual_src = true;
987
988 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
989 srcRGB = VK_BLEND_FACTOR_ONE;
990 dstRGB = VK_BLEND_FACTOR_ONE;
991 }
992 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
993 srcA = VK_BLEND_FACTOR_ONE;
994 dstA = VK_BLEND_FACTOR_ONE;
995 }
996
997 blend_cntl |= S_028780_ENABLE(1);
998
999 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
1000 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
1001 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
1002 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
1003 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
1004 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
1005 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
1006 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
1007 }
1008 blend->cb_blend_control[i] = blend_cntl;
1009
1010 blend_enable |= 1 << i;
1011
1012 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
1013 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
1014 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
1015 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
1016 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
1017 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
1018 blend_need_alpha |= 1 << i;
1019 }
1020 for (i = vkblend->attachmentCount; i < 8; i++)
1021 blend->cb_blend_control[i] = 0;
1022
1023 if (blend->cb_target_mask)
1024 blend->cb_color_control |= S_028808_MODE(mode);
1025 else
1026 blend->cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
1027
1028 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo,
1029 blend_enable, blend_need_alpha, single_cb_enable, blend_mrt0_is_dual_src);
1030 }
1031
1032 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
1033 {
1034 switch (op) {
1035 case VK_STENCIL_OP_KEEP:
1036 return V_02842C_STENCIL_KEEP;
1037 case VK_STENCIL_OP_ZERO:
1038 return V_02842C_STENCIL_ZERO;
1039 case VK_STENCIL_OP_REPLACE:
1040 return V_02842C_STENCIL_REPLACE_TEST;
1041 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
1042 return V_02842C_STENCIL_ADD_CLAMP;
1043 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
1044 return V_02842C_STENCIL_SUB_CLAMP;
1045 case VK_STENCIL_OP_INVERT:
1046 return V_02842C_STENCIL_INVERT;
1047 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
1048 return V_02842C_STENCIL_ADD_WRAP;
1049 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
1050 return V_02842C_STENCIL_SUB_WRAP;
1051 default:
1052 return 0;
1053 }
1054 }
1055 static void
1056 radv_pipeline_init_depth_stencil_state(struct radv_pipeline *pipeline,
1057 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1058 const struct radv_graphics_pipeline_create_info *extra)
1059 {
1060 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
1061 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
1062
1063 memset(ds, 0, sizeof(*ds));
1064 if (!vkds)
1065 return;
1066 ds->db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
1067 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
1068 S_028800_ZFUNC(vkds->depthCompareOp) |
1069 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
1070
1071 if (vkds->stencilTestEnable) {
1072 ds->db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
1073 ds->db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
1074 ds->db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
1075 ds->db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
1076 ds->db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
1077
1078 ds->db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
1079 ds->db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
1080 ds->db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
1081 ds->db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
1082 }
1083
1084 if (extra) {
1085
1086 ds->db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
1087 ds->db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
1088
1089 ds->db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
1090 ds->db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
1091 ds->db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
1092 ds->db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
1093 ds->db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
1094 }
1095 }
1096
1097 static uint32_t si_translate_fill(VkPolygonMode func)
1098 {
1099 switch(func) {
1100 case VK_POLYGON_MODE_FILL:
1101 return V_028814_X_DRAW_TRIANGLES;
1102 case VK_POLYGON_MODE_LINE:
1103 return V_028814_X_DRAW_LINES;
1104 case VK_POLYGON_MODE_POINT:
1105 return V_028814_X_DRAW_POINTS;
1106 default:
1107 assert(0);
1108 return V_028814_X_DRAW_POINTS;
1109 }
1110 }
1111 static void
1112 radv_pipeline_init_raster_state(struct radv_pipeline *pipeline,
1113 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1114 {
1115 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
1116 struct radv_raster_state *raster = &pipeline->graphics.raster;
1117
1118 memset(raster, 0, sizeof(*raster));
1119
1120 raster->spi_interp_control =
1121 S_0286D4_FLAT_SHADE_ENA(1) |
1122 S_0286D4_PNT_SPRITE_ENA(1) |
1123 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
1124 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
1125 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
1126 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
1127 S_0286D4_PNT_SPRITE_TOP_1(0); // vulkan is top to bottom - 1.0 at bottom
1128
1129 raster->pa_cl_vs_out_cntl = S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1);
1130 raster->pa_cl_clip_cntl = S_028810_PS_UCP_MODE(3) |
1131 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
1132 S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1133 S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1134 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
1135 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
1136
1137 raster->pa_su_vtx_cntl =
1138 S_028BE4_PIX_CENTER(1) | // TODO verify
1139 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
1140 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH);
1141
1142 raster->pa_su_sc_mode_cntl =
1143 S_028814_FACE(vkraster->frontFace) |
1144 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
1145 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
1146 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
1147 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1148 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1149 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1150 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1151 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0);
1152
1153 }
1154
1155 static void
1156 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1157 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1158 {
1159 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
1160 struct radv_blend_state *blend = &pipeline->graphics.blend;
1161 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1162 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1163 int ps_iter_samples = 1;
1164 uint32_t mask = 0xffff;
1165
1166 if (vkms)
1167 ms->num_samples = vkms->rasterizationSamples;
1168 else
1169 ms->num_samples = 1;
1170
1171 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.force_persample) {
1172 ps_iter_samples = ms->num_samples;
1173 }
1174
1175 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1176 ms->pa_sc_aa_config = 0;
1177 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1178 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1179 ms->pa_sc_mode_cntl_1 =
1180 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1181 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1182 /* always 1: */
1183 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1184 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1185 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1186 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1187 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1188 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1189
1190 if (ms->num_samples > 1) {
1191 unsigned log_samples = util_logbase2(ms->num_samples);
1192 unsigned log_ps_iter_samples = util_logbase2(util_next_power_of_two(ps_iter_samples));
1193 ms->pa_sc_mode_cntl_0 = S_028A48_MSAA_ENABLE(1);
1194 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1195 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1196 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1197 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1198 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1199 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1200 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
1201 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1202 ms->pa_sc_mode_cntl_1 |= EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1203 }
1204
1205 if (vkms) {
1206 if (vkms->alphaToCoverageEnable)
1207 blend->db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
1208
1209 if (vkms->pSampleMask)
1210 mask = vkms->pSampleMask[0] & 0xffff;
1211 }
1212
1213 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1214 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1215 }
1216
1217 static uint32_t
1218 si_translate_prim(enum VkPrimitiveTopology topology)
1219 {
1220 switch (topology) {
1221 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1222 return V_008958_DI_PT_POINTLIST;
1223 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1224 return V_008958_DI_PT_LINELIST;
1225 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1226 return V_008958_DI_PT_LINESTRIP;
1227 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1228 return V_008958_DI_PT_TRILIST;
1229 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1230 return V_008958_DI_PT_TRISTRIP;
1231 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1232 return V_008958_DI_PT_TRIFAN;
1233 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1234 return V_008958_DI_PT_LINELIST_ADJ;
1235 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1236 return V_008958_DI_PT_LINESTRIP_ADJ;
1237 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1238 return V_008958_DI_PT_TRILIST_ADJ;
1239 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1240 return V_008958_DI_PT_TRISTRIP_ADJ;
1241 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1242 return V_008958_DI_PT_PATCH;
1243 default:
1244 assert(0);
1245 return 0;
1246 }
1247 }
1248
1249 static uint32_t
1250 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1251 {
1252 switch (gl_prim) {
1253 case 0: /* GL_POINTS */
1254 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1255 case 1: /* GL_LINES */
1256 case 3: /* GL_LINE_STRIP */
1257 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1258 case 0x8E7A: /* GL_ISOLINES */
1259 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1260
1261 case 4: /* GL_TRIANGLES */
1262 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1263 case 5: /* GL_TRIANGLE_STRIP */
1264 case 7: /* GL_QUADS */
1265 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1266 default:
1267 assert(0);
1268 return 0;
1269 }
1270 }
1271
1272 static uint32_t
1273 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1274 {
1275 switch (topology) {
1276 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1277 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1278 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1279 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1280 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1281 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1282 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1283 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1284 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1285 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1286 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1287 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1288 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1289 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1290 default:
1291 assert(0);
1292 return 0;
1293 }
1294 }
1295
1296 static unsigned si_map_swizzle(unsigned swizzle)
1297 {
1298 switch (swizzle) {
1299 case VK_SWIZZLE_Y:
1300 return V_008F0C_SQ_SEL_Y;
1301 case VK_SWIZZLE_Z:
1302 return V_008F0C_SQ_SEL_Z;
1303 case VK_SWIZZLE_W:
1304 return V_008F0C_SQ_SEL_W;
1305 case VK_SWIZZLE_0:
1306 return V_008F0C_SQ_SEL_0;
1307 case VK_SWIZZLE_1:
1308 return V_008F0C_SQ_SEL_1;
1309 default: /* VK_SWIZZLE_X */
1310 return V_008F0C_SQ_SEL_X;
1311 }
1312 }
1313
1314 static void
1315 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1316 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1317 {
1318 radv_cmd_dirty_mask_t states = RADV_CMD_DIRTY_DYNAMIC_ALL;
1319 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1320 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1321
1322 pipeline->dynamic_state = default_dynamic_state;
1323
1324 if (pCreateInfo->pDynamicState) {
1325 /* Remove all of the states that are marked as dynamic */
1326 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1327 for (uint32_t s = 0; s < count; s++)
1328 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
1329 }
1330
1331 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1332
1333 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1334 *
1335 * pViewportState is [...] NULL if the pipeline
1336 * has rasterization disabled.
1337 */
1338 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1339 assert(pCreateInfo->pViewportState);
1340
1341 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1342 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
1343 typed_memcpy(dynamic->viewport.viewports,
1344 pCreateInfo->pViewportState->pViewports,
1345 pCreateInfo->pViewportState->viewportCount);
1346 }
1347
1348 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1349 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
1350 typed_memcpy(dynamic->scissor.scissors,
1351 pCreateInfo->pViewportState->pScissors,
1352 pCreateInfo->pViewportState->scissorCount);
1353 }
1354 }
1355
1356 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
1357 assert(pCreateInfo->pRasterizationState);
1358 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1359 }
1360
1361 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
1362 assert(pCreateInfo->pRasterizationState);
1363 dynamic->depth_bias.bias =
1364 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1365 dynamic->depth_bias.clamp =
1366 pCreateInfo->pRasterizationState->depthBiasClamp;
1367 dynamic->depth_bias.slope =
1368 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1369 }
1370
1371 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1372 *
1373 * pColorBlendState is [...] NULL if the pipeline has rasterization
1374 * disabled or if the subpass of the render pass the pipeline is
1375 * created against does not use any color attachments.
1376 */
1377 bool uses_color_att = false;
1378 for (unsigned i = 0; i < subpass->color_count; ++i) {
1379 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1380 uses_color_att = true;
1381 break;
1382 }
1383 }
1384
1385 if (uses_color_att && states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
1386 assert(pCreateInfo->pColorBlendState);
1387 typed_memcpy(dynamic->blend_constants,
1388 pCreateInfo->pColorBlendState->blendConstants, 4);
1389 }
1390
1391 /* If there is no depthstencil attachment, then don't read
1392 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1393 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1394 * no need to override the depthstencil defaults in
1395 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1396 *
1397 * Section 9.2 of the Vulkan 1.0.15 spec says:
1398 *
1399 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1400 * disabled or if the subpass of the render pass the pipeline is created
1401 * against does not use a depth/stencil attachment.
1402 */
1403 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
1404 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1405 assert(pCreateInfo->pDepthStencilState);
1406
1407 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
1408 dynamic->depth_bounds.min =
1409 pCreateInfo->pDepthStencilState->minDepthBounds;
1410 dynamic->depth_bounds.max =
1411 pCreateInfo->pDepthStencilState->maxDepthBounds;
1412 }
1413
1414 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
1415 dynamic->stencil_compare_mask.front =
1416 pCreateInfo->pDepthStencilState->front.compareMask;
1417 dynamic->stencil_compare_mask.back =
1418 pCreateInfo->pDepthStencilState->back.compareMask;
1419 }
1420
1421 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
1422 dynamic->stencil_write_mask.front =
1423 pCreateInfo->pDepthStencilState->front.writeMask;
1424 dynamic->stencil_write_mask.back =
1425 pCreateInfo->pDepthStencilState->back.writeMask;
1426 }
1427
1428 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
1429 dynamic->stencil_reference.front =
1430 pCreateInfo->pDepthStencilState->front.reference;
1431 dynamic->stencil_reference.back =
1432 pCreateInfo->pDepthStencilState->back.reference;
1433 }
1434 }
1435
1436 pipeline->dynamic_state_mask = states;
1437 }
1438
1439 static union ac_shader_variant_key
1440 radv_compute_vs_key(const VkGraphicsPipelineCreateInfo *pCreateInfo, bool as_es)
1441 {
1442 union ac_shader_variant_key key;
1443 const VkPipelineVertexInputStateCreateInfo *input_state =
1444 pCreateInfo->pVertexInputState;
1445
1446 memset(&key, 0, sizeof(key));
1447 key.vs.instance_rate_inputs = 0;
1448 key.vs.as_es = as_es;
1449
1450 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
1451 unsigned binding;
1452 binding = input_state->pVertexAttributeDescriptions[i].binding;
1453 if (input_state->pVertexBindingDescriptions[binding].inputRate)
1454 key.vs.instance_rate_inputs |= 1u << input_state->pVertexAttributeDescriptions[i].location;
1455 }
1456 return key;
1457 }
1458
1459 static void
1460 calculate_gs_ring_sizes(struct radv_pipeline *pipeline)
1461 {
1462 struct radv_device *device = pipeline->device;
1463 unsigned num_se = device->physical_device->rad_info.max_se;
1464 unsigned wave_size = 64;
1465 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1466 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1467 unsigned alignment = 256 * num_se;
1468 /* The maximum size is 63.999 MB per SE. */
1469 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1470 struct ac_es_output_info *es_info = &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info;
1471 struct ac_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1472
1473 /* Calculate the minimum size. */
1474 unsigned min_esgs_ring_size = align(es_info->esgs_itemsize * gs_vertex_reuse *
1475 wave_size, alignment);
1476 /* These are recommended sizes, not minimum sizes. */
1477 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1478 es_info->esgs_itemsize * gs_info->gs.vertices_in;
1479 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1480 gs_info->gs.max_gsvs_emit_size * 1; // no streams in VK (gs->max_gs_stream + 1);
1481
1482 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1483 esgs_ring_size = align(esgs_ring_size, alignment);
1484 gsvs_ring_size = align(gsvs_ring_size, alignment);
1485
1486 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1487 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1488 }
1489
1490 static const struct radv_prim_vertex_count prim_size_table[] = {
1491 [V_008958_DI_PT_NONE] = {0, 0},
1492 [V_008958_DI_PT_POINTLIST] = {1, 1},
1493 [V_008958_DI_PT_LINELIST] = {2, 2},
1494 [V_008958_DI_PT_LINESTRIP] = {2, 1},
1495 [V_008958_DI_PT_TRILIST] = {3, 3},
1496 [V_008958_DI_PT_TRIFAN] = {3, 1},
1497 [V_008958_DI_PT_TRISTRIP] = {3, 1},
1498 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
1499 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
1500 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
1501 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
1502 [V_008958_DI_PT_RECTLIST] = {3, 3},
1503 [V_008958_DI_PT_LINELOOP] = {2, 1},
1504 [V_008958_DI_PT_POLYGON] = {3, 1},
1505 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
1506 };
1507
1508 static uint32_t si_vgt_gs_mode(struct radv_shader_variant *gs)
1509 {
1510 unsigned gs_max_vert_out = gs->info.gs.vertices_out;
1511 unsigned cut_mode;
1512
1513 if (gs_max_vert_out <= 128) {
1514 cut_mode = V_028A40_GS_CUT_128;
1515 } else if (gs_max_vert_out <= 256) {
1516 cut_mode = V_028A40_GS_CUT_256;
1517 } else if (gs_max_vert_out <= 512) {
1518 cut_mode = V_028A40_GS_CUT_512;
1519 } else {
1520 assert(gs_max_vert_out <= 1024);
1521 cut_mode = V_028A40_GS_CUT_1024;
1522 }
1523
1524 return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
1525 S_028A40_CUT_MODE(cut_mode)|
1526 S_028A40_ES_WRITE_OPTIMIZE(1) |
1527 S_028A40_GS_WRITE_OPTIMIZE(1);
1528 }
1529
1530 VkResult
1531 radv_pipeline_init(struct radv_pipeline *pipeline,
1532 struct radv_device *device,
1533 struct radv_pipeline_cache *cache,
1534 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1535 const struct radv_graphics_pipeline_create_info *extra,
1536 const VkAllocationCallbacks *alloc)
1537 {
1538 struct radv_shader_module fs_m = {0};
1539 VkResult result;
1540
1541 if (alloc == NULL)
1542 alloc = &device->alloc;
1543
1544 pipeline->device = device;
1545 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
1546
1547 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
1548 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
1549 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
1550 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
1551 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
1552 pStages[stage] = &pCreateInfo->pStages[i];
1553 modules[stage] = radv_shader_module_from_handle(pStages[stage]->module);
1554 }
1555
1556 radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
1557
1558 if (modules[MESA_SHADER_VERTEX]) {
1559 bool as_es = modules[MESA_SHADER_GEOMETRY] != NULL;
1560 union ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo, as_es);
1561
1562 pipeline->shaders[MESA_SHADER_VERTEX] =
1563 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_VERTEX],
1564 pStages[MESA_SHADER_VERTEX]->pName,
1565 MESA_SHADER_VERTEX,
1566 pStages[MESA_SHADER_VERTEX]->pSpecializationInfo,
1567 pipeline->layout, &key);
1568
1569 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_VERTEX);
1570 }
1571
1572 if (modules[MESA_SHADER_GEOMETRY]) {
1573 union ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo, false);
1574
1575 pipeline->shaders[MESA_SHADER_GEOMETRY] =
1576 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_GEOMETRY],
1577 pStages[MESA_SHADER_GEOMETRY]->pName,
1578 MESA_SHADER_GEOMETRY,
1579 pStages[MESA_SHADER_GEOMETRY]->pSpecializationInfo,
1580 pipeline->layout, &key);
1581
1582 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_GEOMETRY);
1583 calculate_gs_ring_sizes(pipeline);
1584
1585 pipeline->graphics.vgt_gs_mode = si_vgt_gs_mode(pipeline->shaders[MESA_SHADER_GEOMETRY]);
1586 } else
1587 pipeline->graphics.vgt_gs_mode = 0;
1588
1589 if (!modules[MESA_SHADER_FRAGMENT]) {
1590 nir_builder fs_b;
1591 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
1592 fs_b.shader->info->name = ralloc_strdup(fs_b.shader, "noop_fs");
1593 fs_m.nir = fs_b.shader;
1594 modules[MESA_SHADER_FRAGMENT] = &fs_m;
1595 }
1596
1597 if (modules[MESA_SHADER_FRAGMENT]) {
1598 union ac_shader_variant_key key;
1599 key.fs.col_format = pipeline->graphics.blend.spi_shader_col_format;
1600 key.fs.is_int8 = radv_pipeline_compute_is_int8(pCreateInfo);
1601
1602 const VkPipelineShaderStageCreateInfo *stage = pStages[MESA_SHADER_FRAGMENT];
1603
1604 pipeline->shaders[MESA_SHADER_FRAGMENT] =
1605 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_FRAGMENT],
1606 stage ? stage->pName : "main",
1607 MESA_SHADER_FRAGMENT,
1608 stage ? stage->pSpecializationInfo : NULL,
1609 pipeline->layout, &key);
1610 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_FRAGMENT);
1611 }
1612
1613 if (fs_m.nir)
1614 ralloc_free(fs_m.nir);
1615
1616 radv_pipeline_init_depth_stencil_state(pipeline, pCreateInfo, extra);
1617 radv_pipeline_init_raster_state(pipeline, pCreateInfo);
1618 radv_pipeline_init_multisample_state(pipeline, pCreateInfo);
1619 pipeline->graphics.prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
1620 if (radv_pipeline_has_gs(pipeline)) {
1621 pipeline->graphics.gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
1622 } else {
1623 pipeline->graphics.gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
1624 }
1625 if (extra && extra->use_rectlist) {
1626 pipeline->graphics.prim = V_008958_DI_PT_RECTLIST;
1627 pipeline->graphics.gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1628 }
1629 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
1630 /* prim vertex count will need TESS changes */
1631 pipeline->graphics.prim_vertex_count = prim_size_table[pipeline->graphics.prim];
1632
1633 /* Ensure that some export memory is always allocated, for two reasons:
1634 *
1635 * 1) Correctness: The hardware ignores the EXEC mask if no export
1636 * memory is allocated, so KILL and alpha test do not work correctly
1637 * without this.
1638 * 2) Performance: Every shader needs at least a NULL export, even when
1639 * it writes no color/depth output. The NULL export instruction
1640 * stalls without this setting.
1641 *
1642 * Don't add this to CB_SHADER_MASK.
1643 */
1644 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
1645 if (!pipeline->graphics.blend.spi_shader_col_format) {
1646 if (!ps->info.fs.writes_z &&
1647 !ps->info.fs.writes_stencil &&
1648 !ps->info.fs.writes_sample_mask)
1649 pipeline->graphics.blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1650 }
1651
1652 unsigned z_order;
1653 pipeline->graphics.db_shader_control = 0;
1654 if (ps->info.fs.early_fragment_test || !ps->info.fs.writes_memory)
1655 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
1656 else
1657 z_order = V_02880C_LATE_Z;
1658
1659 pipeline->graphics.db_shader_control =
1660 S_02880C_Z_EXPORT_ENABLE(ps->info.fs.writes_z) |
1661 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.fs.writes_stencil) |
1662 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
1663 S_02880C_MASK_EXPORT_ENABLE(ps->info.fs.writes_sample_mask) |
1664 S_02880C_Z_ORDER(z_order) |
1665 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
1666 S_02880C_EXEC_ON_HIER_FAIL(ps->info.fs.writes_memory) |
1667 S_02880C_EXEC_ON_NOOP(ps->info.fs.writes_memory);
1668
1669 const VkPipelineVertexInputStateCreateInfo *vi_info =
1670 pCreateInfo->pVertexInputState;
1671 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
1672 const VkVertexInputAttributeDescription *desc =
1673 &vi_info->pVertexAttributeDescriptions[i];
1674 unsigned loc = desc->location;
1675 const struct vk_format_description *format_desc;
1676 int first_non_void;
1677 uint32_t num_format, data_format;
1678 format_desc = vk_format_description(desc->format);
1679 first_non_void = vk_format_get_first_non_void_channel(desc->format);
1680
1681 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
1682 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
1683
1684 pipeline->va_rsrc_word3[loc] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc->swizzle[0])) |
1685 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc->swizzle[1])) |
1686 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc->swizzle[2])) |
1687 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc->swizzle[3])) |
1688 S_008F0C_NUM_FORMAT(num_format) |
1689 S_008F0C_DATA_FORMAT(data_format);
1690 pipeline->va_format_size[loc] = format_desc->block.bits / 8;
1691 pipeline->va_offset[loc] = desc->offset;
1692 pipeline->va_binding[loc] = desc->binding;
1693 pipeline->num_vertex_attribs = MAX2(pipeline->num_vertex_attribs, loc + 1);
1694 }
1695
1696 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
1697 const VkVertexInputBindingDescription *desc =
1698 &vi_info->pVertexBindingDescriptions[i];
1699
1700 pipeline->binding_stride[desc->binding] = desc->stride;
1701 }
1702
1703 if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
1704 radv_dump_pipeline_stats(device, pipeline);
1705 }
1706
1707 result = radv_pipeline_scratch_init(device, pipeline);
1708 return result;
1709 }
1710
1711 VkResult
1712 radv_graphics_pipeline_create(
1713 VkDevice _device,
1714 VkPipelineCache _cache,
1715 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1716 const struct radv_graphics_pipeline_create_info *extra,
1717 const VkAllocationCallbacks *pAllocator,
1718 VkPipeline *pPipeline)
1719 {
1720 RADV_FROM_HANDLE(radv_device, device, _device);
1721 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
1722 struct radv_pipeline *pipeline;
1723 VkResult result;
1724
1725 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
1726 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1727 if (pipeline == NULL)
1728 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1729
1730 memset(pipeline, 0, sizeof(*pipeline));
1731 result = radv_pipeline_init(pipeline, device, cache,
1732 pCreateInfo, extra, pAllocator);
1733 if (result != VK_SUCCESS) {
1734 radv_pipeline_destroy(device, pipeline, pAllocator);
1735 return result;
1736 }
1737
1738 *pPipeline = radv_pipeline_to_handle(pipeline);
1739
1740 return VK_SUCCESS;
1741 }
1742
1743 VkResult radv_CreateGraphicsPipelines(
1744 VkDevice _device,
1745 VkPipelineCache pipelineCache,
1746 uint32_t count,
1747 const VkGraphicsPipelineCreateInfo* pCreateInfos,
1748 const VkAllocationCallbacks* pAllocator,
1749 VkPipeline* pPipelines)
1750 {
1751 VkResult result = VK_SUCCESS;
1752 unsigned i = 0;
1753
1754 for (; i < count; i++) {
1755 VkResult r;
1756 r = radv_graphics_pipeline_create(_device,
1757 pipelineCache,
1758 &pCreateInfos[i],
1759 NULL, pAllocator, &pPipelines[i]);
1760 if (r != VK_SUCCESS) {
1761 result = r;
1762 pPipelines[i] = VK_NULL_HANDLE;
1763 }
1764 }
1765
1766 return result;
1767 }
1768
1769 static VkResult radv_compute_pipeline_create(
1770 VkDevice _device,
1771 VkPipelineCache _cache,
1772 const VkComputePipelineCreateInfo* pCreateInfo,
1773 const VkAllocationCallbacks* pAllocator,
1774 VkPipeline* pPipeline)
1775 {
1776 RADV_FROM_HANDLE(radv_device, device, _device);
1777 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
1778 RADV_FROM_HANDLE(radv_shader_module, module, pCreateInfo->stage.module);
1779 struct radv_pipeline *pipeline;
1780 VkResult result;
1781
1782 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
1783 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1784 if (pipeline == NULL)
1785 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1786
1787 memset(pipeline, 0, sizeof(*pipeline));
1788 pipeline->device = device;
1789 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
1790
1791 pipeline->shaders[MESA_SHADER_COMPUTE] =
1792 radv_pipeline_compile(pipeline, cache, module,
1793 pCreateInfo->stage.pName,
1794 MESA_SHADER_COMPUTE,
1795 pCreateInfo->stage.pSpecializationInfo,
1796 pipeline->layout, NULL);
1797
1798
1799 result = radv_pipeline_scratch_init(device, pipeline);
1800 if (result != VK_SUCCESS) {
1801 radv_pipeline_destroy(device, pipeline, pAllocator);
1802 return result;
1803 }
1804
1805 *pPipeline = radv_pipeline_to_handle(pipeline);
1806
1807 if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
1808 radv_dump_pipeline_stats(device, pipeline);
1809 }
1810 return VK_SUCCESS;
1811 }
1812 VkResult radv_CreateComputePipelines(
1813 VkDevice _device,
1814 VkPipelineCache pipelineCache,
1815 uint32_t count,
1816 const VkComputePipelineCreateInfo* pCreateInfos,
1817 const VkAllocationCallbacks* pAllocator,
1818 VkPipeline* pPipelines)
1819 {
1820 VkResult result = VK_SUCCESS;
1821
1822 unsigned i = 0;
1823 for (; i < count; i++) {
1824 VkResult r;
1825 r = radv_compute_pipeline_create(_device, pipelineCache,
1826 &pCreateInfos[i],
1827 pAllocator, &pPipelines[i]);
1828 if (r != VK_SUCCESS) {
1829 result = r;
1830 pPipelines[i] = VK_NULL_HANDLE;
1831 }
1832 }
1833
1834 return result;
1835 }