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ac/radv: change api to create target machine
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_private.h"
31 #include "nir/nir.h"
32 #include "nir/nir_builder.h"
33 #include "spirv/nir_spirv.h"
34
35 #include <llvm-c/Core.h>
36 #include <llvm-c/TargetMachine.h>
37
38 #include "sid.h"
39 #include "gfx9d.h"
40 #include "r600d_common.h"
41 #include "ac_binary.h"
42 #include "ac_llvm_util.h"
43 #include "ac_nir_to_llvm.h"
44 #include "vk_format.h"
45 #include "util/debug.h"
46 #include "ac_exp_param.h"
47
48 void radv_shader_variant_destroy(struct radv_device *device,
49 struct radv_shader_variant *variant);
50
51 static const struct nir_shader_compiler_options nir_options = {
52 .vertex_id_zero_based = true,
53 .lower_scmp = true,
54 .lower_flrp32 = true,
55 .lower_fsat = true,
56 .lower_fdiv = true,
57 .lower_sub = true,
58 .lower_pack_snorm_2x16 = true,
59 .lower_pack_snorm_4x8 = true,
60 .lower_pack_unorm_2x16 = true,
61 .lower_pack_unorm_4x8 = true,
62 .lower_unpack_snorm_2x16 = true,
63 .lower_unpack_snorm_4x8 = true,
64 .lower_unpack_unorm_2x16 = true,
65 .lower_unpack_unorm_4x8 = true,
66 .lower_extract_byte = true,
67 .lower_extract_word = true,
68 .max_unroll_iterations = 32
69 };
70
71 VkResult radv_CreateShaderModule(
72 VkDevice _device,
73 const VkShaderModuleCreateInfo* pCreateInfo,
74 const VkAllocationCallbacks* pAllocator,
75 VkShaderModule* pShaderModule)
76 {
77 RADV_FROM_HANDLE(radv_device, device, _device);
78 struct radv_shader_module *module;
79
80 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
81 assert(pCreateInfo->flags == 0);
82
83 module = vk_alloc2(&device->alloc, pAllocator,
84 sizeof(*module) + pCreateInfo->codeSize, 8,
85 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
86 if (module == NULL)
87 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
88
89 module->nir = NULL;
90 module->size = pCreateInfo->codeSize;
91 memcpy(module->data, pCreateInfo->pCode, module->size);
92
93 _mesa_sha1_compute(module->data, module->size, module->sha1);
94
95 *pShaderModule = radv_shader_module_to_handle(module);
96
97 return VK_SUCCESS;
98 }
99
100 void radv_DestroyShaderModule(
101 VkDevice _device,
102 VkShaderModule _module,
103 const VkAllocationCallbacks* pAllocator)
104 {
105 RADV_FROM_HANDLE(radv_device, device, _device);
106 RADV_FROM_HANDLE(radv_shader_module, module, _module);
107
108 if (!module)
109 return;
110
111 vk_free2(&device->alloc, pAllocator, module);
112 }
113
114
115 static void
116 radv_pipeline_destroy(struct radv_device *device,
117 struct radv_pipeline *pipeline,
118 const VkAllocationCallbacks* allocator)
119 {
120 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
121 if (pipeline->shaders[i])
122 radv_shader_variant_destroy(device, pipeline->shaders[i]);
123
124 if (pipeline->gs_copy_shader)
125 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
126
127 vk_free2(&device->alloc, allocator, pipeline);
128 }
129
130 void radv_DestroyPipeline(
131 VkDevice _device,
132 VkPipeline _pipeline,
133 const VkAllocationCallbacks* pAllocator)
134 {
135 RADV_FROM_HANDLE(radv_device, device, _device);
136 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
137
138 if (!_pipeline)
139 return;
140
141 radv_pipeline_destroy(device, pipeline, pAllocator);
142 }
143
144
145 static void
146 radv_optimize_nir(struct nir_shader *shader)
147 {
148 bool progress;
149
150 do {
151 progress = false;
152
153 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
154 NIR_PASS_V(shader, nir_lower_64bit_pack);
155 NIR_PASS_V(shader, nir_lower_alu_to_scalar);
156 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
157
158 NIR_PASS(progress, shader, nir_copy_prop);
159 NIR_PASS(progress, shader, nir_opt_remove_phis);
160 NIR_PASS(progress, shader, nir_opt_dce);
161 if (nir_opt_trivial_continues(shader)) {
162 progress = true;
163 NIR_PASS(progress, shader, nir_copy_prop);
164 NIR_PASS(progress, shader, nir_opt_dce);
165 }
166 NIR_PASS(progress, shader, nir_opt_if);
167 NIR_PASS(progress, shader, nir_opt_dead_cf);
168 NIR_PASS(progress, shader, nir_opt_cse);
169 NIR_PASS(progress, shader, nir_opt_peephole_select, 8);
170 NIR_PASS(progress, shader, nir_opt_algebraic);
171 NIR_PASS(progress, shader, nir_opt_constant_folding);
172 NIR_PASS(progress, shader, nir_opt_undef);
173 NIR_PASS(progress, shader, nir_opt_conditional_discard);
174 if (shader->options->max_unroll_iterations) {
175 NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
176 }
177 } while (progress);
178 }
179
180 static nir_shader *
181 radv_shader_compile_to_nir(struct radv_device *device,
182 struct radv_shader_module *module,
183 const char *entrypoint_name,
184 gl_shader_stage stage,
185 const VkSpecializationInfo *spec_info,
186 bool dump)
187 {
188 if (strcmp(entrypoint_name, "main") != 0) {
189 radv_finishme("Multiple shaders per module not really supported");
190 }
191
192 nir_shader *nir;
193 nir_function *entry_point;
194 if (module->nir) {
195 /* Some things such as our meta clear/blit code will give us a NIR
196 * shader directly. In that case, we just ignore the SPIR-V entirely
197 * and just use the NIR shader */
198 nir = module->nir;
199 nir->options = &nir_options;
200 nir_validate_shader(nir);
201
202 assert(exec_list_length(&nir->functions) == 1);
203 struct exec_node *node = exec_list_get_head(&nir->functions);
204 entry_point = exec_node_data(nir_function, node, node);
205 } else {
206 uint32_t *spirv = (uint32_t *) module->data;
207 assert(module->size % 4 == 0);
208
209 uint32_t num_spec_entries = 0;
210 struct nir_spirv_specialization *spec_entries = NULL;
211 if (spec_info && spec_info->mapEntryCount > 0) {
212 num_spec_entries = spec_info->mapEntryCount;
213 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
214 for (uint32_t i = 0; i < num_spec_entries; i++) {
215 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
216 const void *data = spec_info->pData + entry.offset;
217 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
218
219 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
220 if (spec_info->dataSize == 8)
221 spec_entries[i].data64 = *(const uint64_t *)data;
222 else
223 spec_entries[i].data32 = *(const uint32_t *)data;
224 }
225 }
226 const struct nir_spirv_supported_extensions supported_ext = {
227 .draw_parameters = true,
228 .float64 = true,
229 .image_read_without_format = true,
230 .image_write_without_format = true,
231 .tessellation = true,
232 .int64 = true,
233 };
234 entry_point = spirv_to_nir(spirv, module->size / 4,
235 spec_entries, num_spec_entries,
236 stage, entrypoint_name, &supported_ext, &nir_options);
237 nir = entry_point->shader;
238 assert(nir->stage == stage);
239 nir_validate_shader(nir);
240
241 free(spec_entries);
242
243 /* We have to lower away local constant initializers right before we
244 * inline functions. That way they get properly initialized at the top
245 * of the function and not at the top of its caller.
246 */
247 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_local);
248 NIR_PASS_V(nir, nir_lower_returns);
249 NIR_PASS_V(nir, nir_inline_functions);
250
251 /* Pick off the single entrypoint that we want */
252 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
253 if (func != entry_point)
254 exec_node_remove(&func->node);
255 }
256 assert(exec_list_length(&nir->functions) == 1);
257 entry_point->name = ralloc_strdup(entry_point, "main");
258
259 NIR_PASS_V(nir, nir_remove_dead_variables,
260 nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
261
262 /* Now that we've deleted all but the main function, we can go ahead and
263 * lower the rest of the constant initializers.
264 */
265 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
266 NIR_PASS_V(nir, nir_lower_system_values);
267 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
268 }
269
270 /* Vulkan uses the separate-shader linking model */
271 nir->info.separate_shader = true;
272
273 nir_shader_gather_info(nir, entry_point->impl);
274
275 nir_variable_mode indirect_mask = 0;
276 indirect_mask |= nir_var_shader_in;
277 indirect_mask |= nir_var_local;
278
279 nir_lower_indirect_derefs(nir, indirect_mask);
280
281 static const nir_lower_tex_options tex_options = {
282 .lower_txp = ~0,
283 };
284
285 nir_lower_tex(nir, &tex_options);
286
287 nir_lower_vars_to_ssa(nir);
288 nir_lower_var_copies(nir);
289 nir_lower_global_vars_to_local(nir);
290 nir_remove_dead_variables(nir, nir_var_local);
291 radv_optimize_nir(nir);
292
293 if (dump)
294 nir_print_shader(nir, stderr);
295
296 return nir;
297 }
298
299 static const char *radv_get_shader_name(struct radv_shader_variant *var,
300 gl_shader_stage stage)
301 {
302 switch (stage) {
303 case MESA_SHADER_VERTEX: return var->info.vs.as_ls ? "Vertex Shader as LS" : var->info.vs.as_es ? "Vertex Shader as ES" : "Vertex Shader as VS";
304 case MESA_SHADER_GEOMETRY: return "Geometry Shader";
305 case MESA_SHADER_FRAGMENT: return "Pixel Shader";
306 case MESA_SHADER_COMPUTE: return "Compute Shader";
307 case MESA_SHADER_TESS_CTRL: return "Tessellation Control Shader";
308 case MESA_SHADER_TESS_EVAL: return var->info.tes.as_es ? "Tessellation Evaluation Shader as ES" : "Tessellation Evaluation Shader as VS";
309 default:
310 return "Unknown shader";
311 };
312
313 }
314 static void radv_dump_pipeline_stats(struct radv_device *device, struct radv_pipeline *pipeline)
315 {
316 unsigned lds_increment = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
317 struct radv_shader_variant *var;
318 struct ac_shader_config *conf;
319 int i;
320 FILE *file = stderr;
321 unsigned max_simd_waves = 10;
322 unsigned lds_per_wave = 0;
323
324 for (i = 0; i < MESA_SHADER_STAGES; i++) {
325 if (!pipeline->shaders[i])
326 continue;
327 var = pipeline->shaders[i];
328
329 conf = &var->config;
330
331 if (i == MESA_SHADER_FRAGMENT) {
332 lds_per_wave = conf->lds_size * lds_increment +
333 align(var->info.fs.num_interp * 48, lds_increment);
334 }
335
336 if (conf->num_sgprs) {
337 if (device->physical_device->rad_info.chip_class >= VI)
338 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
339 else
340 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
341 }
342
343 if (conf->num_vgprs)
344 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
345
346 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
347 * that PS can use.
348 */
349 if (lds_per_wave)
350 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
351
352 fprintf(file, "\n%s:\n",
353 radv_get_shader_name(var, i));
354 if (i == MESA_SHADER_FRAGMENT) {
355 fprintf(file, "*** SHADER CONFIG ***\n"
356 "SPI_PS_INPUT_ADDR = 0x%04x\n"
357 "SPI_PS_INPUT_ENA = 0x%04x\n",
358 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
359 }
360 fprintf(file, "*** SHADER STATS ***\n"
361 "SGPRS: %d\n"
362 "VGPRS: %d\n"
363 "Spilled SGPRs: %d\n"
364 "Spilled VGPRs: %d\n"
365 "Code Size: %d bytes\n"
366 "LDS: %d blocks\n"
367 "Scratch: %d bytes per wave\n"
368 "Max Waves: %d\n"
369 "********************\n\n\n",
370 conf->num_sgprs, conf->num_vgprs,
371 conf->spilled_sgprs, conf->spilled_vgprs, var->code_size,
372 conf->lds_size, conf->scratch_bytes_per_wave,
373 max_simd_waves);
374 }
375 }
376
377 void radv_shader_variant_destroy(struct radv_device *device,
378 struct radv_shader_variant *variant)
379 {
380 if (!p_atomic_dec_zero(&variant->ref_count))
381 return;
382
383 device->ws->buffer_destroy(variant->bo);
384 free(variant);
385 }
386
387 static void radv_fill_shader_variant(struct radv_device *device,
388 struct radv_shader_variant *variant,
389 struct ac_shader_binary *binary,
390 gl_shader_stage stage)
391 {
392 bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0;
393 unsigned vgpr_comp_cnt = 0;
394
395 if (scratch_enabled && !device->llvm_supports_spill)
396 radv_finishme("shader scratch support only available with LLVM 4.0");
397
398 variant->code_size = binary->code_size;
399 variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
400 S_00B12C_SCRATCH_EN(scratch_enabled);
401
402 switch (stage) {
403 case MESA_SHADER_TESS_EVAL:
404 vgpr_comp_cnt = 3;
405 /* fallthrough */
406 case MESA_SHADER_TESS_CTRL:
407 variant->rsrc2 |= S_00B42C_OC_LDS_EN(1);
408 break;
409 case MESA_SHADER_VERTEX:
410 case MESA_SHADER_GEOMETRY:
411 vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
412 break;
413 case MESA_SHADER_FRAGMENT:
414 break;
415 case MESA_SHADER_COMPUTE:
416 variant->rsrc2 |=
417 S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) |
418 S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) |
419 S_00B84C_TG_SIZE_EN(1) |
420 S_00B84C_LDS_SIZE(variant->config.lds_size);
421 break;
422 default:
423 unreachable("unsupported shader type");
424 break;
425 }
426
427 variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
428 S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) |
429 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
430 S_00B848_DX10_CLAMP(1) |
431 S_00B848_FLOAT_MODE(variant->config.float_mode);
432
433 variant->bo = device->ws->buffer_create(device->ws, binary->code_size, 256,
434 RADEON_DOMAIN_VRAM, RADEON_FLAG_CPU_ACCESS);
435
436 void *ptr = device->ws->buffer_map(variant->bo);
437 memcpy(ptr, binary->code, binary->code_size);
438 device->ws->buffer_unmap(variant->bo);
439
440
441 }
442
443 static struct radv_shader_variant *radv_shader_variant_create(struct radv_device *device,
444 struct nir_shader *shader,
445 struct radv_pipeline_layout *layout,
446 const union ac_shader_variant_key *key,
447 void** code_out,
448 unsigned *code_size_out,
449 bool dump)
450 {
451 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
452 enum radeon_family chip_family = device->physical_device->rad_info.family;
453 LLVMTargetMachineRef tm;
454 if (!variant)
455 return NULL;
456
457 struct ac_nir_compiler_options options = {0};
458 options.layout = layout;
459 if (key)
460 options.key = *key;
461
462 struct ac_shader_binary binary;
463 enum ac_target_machine_options tm_options = 0;
464 options.unsafe_math = !!(device->debug_flags & RADV_DEBUG_UNSAFE_MATH);
465 options.family = chip_family;
466 options.chip_class = device->physical_device->rad_info.chip_class;
467 options.supports_spill = device->llvm_supports_spill;
468 if (options.supports_spill)
469 tm_options |= AC_TM_SUPPORTS_SPILL;
470 tm = ac_create_target_machine(chip_family, tm_options);
471 ac_compile_nir_shader(tm, &binary, &variant->config,
472 &variant->info, shader, &options, dump);
473 LLVMDisposeTargetMachine(tm);
474
475 radv_fill_shader_variant(device, variant, &binary, shader->stage);
476
477 if (code_out) {
478 *code_out = binary.code;
479 *code_size_out = binary.code_size;
480 } else
481 free(binary.code);
482 free(binary.config);
483 free(binary.rodata);
484 free(binary.global_symbol_offsets);
485 free(binary.relocs);
486 free(binary.disasm_string);
487 variant->ref_count = 1;
488 return variant;
489 }
490
491 static struct radv_shader_variant *
492 radv_pipeline_create_gs_copy_shader(struct radv_pipeline *pipeline,
493 struct nir_shader *nir,
494 void** code_out,
495 unsigned *code_size_out,
496 bool dump_shader)
497 {
498 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
499 enum radeon_family chip_family = pipeline->device->physical_device->rad_info.family;
500 LLVMTargetMachineRef tm;
501 if (!variant)
502 return NULL;
503
504 struct ac_nir_compiler_options options = {0};
505 struct ac_shader_binary binary;
506 enum ac_target_machine_options tm_options = 0;
507 options.family = chip_family;
508 options.chip_class = pipeline->device->physical_device->rad_info.chip_class;
509 if (options.supports_spill)
510 tm_options |= AC_TM_SUPPORTS_SPILL;
511 tm = ac_create_target_machine(chip_family, tm_options);
512 ac_create_gs_copy_shader(tm, nir, &binary, &variant->config, &variant->info, &options, dump_shader);
513 LLVMDisposeTargetMachine(tm);
514
515 radv_fill_shader_variant(pipeline->device, variant, &binary, MESA_SHADER_VERTEX);
516
517 if (code_out) {
518 *code_out = binary.code;
519 *code_size_out = binary.code_size;
520 } else
521 free(binary.code);
522 free(binary.config);
523 free(binary.rodata);
524 free(binary.global_symbol_offsets);
525 free(binary.relocs);
526 free(binary.disasm_string);
527 variant->ref_count = 1;
528 return variant;
529 }
530
531 static struct radv_shader_variant *
532 radv_pipeline_compile(struct radv_pipeline *pipeline,
533 struct radv_pipeline_cache *cache,
534 struct radv_shader_module *module,
535 const char *entrypoint,
536 gl_shader_stage stage,
537 const VkSpecializationInfo *spec_info,
538 struct radv_pipeline_layout *layout,
539 const union ac_shader_variant_key *key)
540 {
541 unsigned char sha1[20];
542 unsigned char gs_copy_sha1[20];
543 struct radv_shader_variant *variant;
544 nir_shader *nir;
545 void *code = NULL;
546 unsigned code_size = 0;
547 bool dump = (pipeline->device->debug_flags & RADV_DEBUG_DUMP_SHADERS);
548
549 if (module->nir)
550 _mesa_sha1_compute(module->nir->info.name,
551 strlen(module->nir->info.name),
552 module->sha1);
553
554 radv_hash_shader(sha1, module, entrypoint, spec_info, layout, key, 0);
555 if (stage == MESA_SHADER_GEOMETRY)
556 radv_hash_shader(gs_copy_sha1, module, entrypoint, spec_info,
557 layout, key, 1);
558
559 variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
560 cache,
561 sha1);
562
563 if (stage == MESA_SHADER_GEOMETRY) {
564 pipeline->gs_copy_shader =
565 radv_create_shader_variant_from_pipeline_cache(
566 pipeline->device,
567 cache,
568 gs_copy_sha1);
569 }
570
571 if (variant &&
572 (stage != MESA_SHADER_GEOMETRY || pipeline->gs_copy_shader))
573 return variant;
574
575 nir = radv_shader_compile_to_nir(pipeline->device,
576 module, entrypoint, stage,
577 spec_info, dump);
578 if (nir == NULL)
579 return NULL;
580
581 if (!variant) {
582 variant = radv_shader_variant_create(pipeline->device, nir,
583 layout, key, &code,
584 &code_size, dump);
585 }
586
587 if (stage == MESA_SHADER_GEOMETRY && !pipeline->gs_copy_shader) {
588 void *gs_copy_code = NULL;
589 unsigned gs_copy_code_size = 0;
590 pipeline->gs_copy_shader = radv_pipeline_create_gs_copy_shader(
591 pipeline, nir, &gs_copy_code, &gs_copy_code_size, dump);
592
593 if (pipeline->gs_copy_shader) {
594 pipeline->gs_copy_shader =
595 radv_pipeline_cache_insert_shader(cache,
596 gs_copy_sha1,
597 pipeline->gs_copy_shader,
598 gs_copy_code,
599 gs_copy_code_size);
600 }
601 }
602 if (!module->nir)
603 ralloc_free(nir);
604
605 if (variant)
606 variant = radv_pipeline_cache_insert_shader(cache, sha1, variant,
607 code, code_size);
608
609 if (code)
610 free(code);
611 return variant;
612 }
613
614 static union ac_shader_variant_key
615 radv_compute_tes_key(bool as_es, bool export_prim_id)
616 {
617 union ac_shader_variant_key key;
618 memset(&key, 0, sizeof(key));
619 key.tes.as_es = as_es;
620 /* export prim id only happens when no geom shader */
621 if (!as_es)
622 key.tes.export_prim_id = export_prim_id;
623 return key;
624 }
625
626 static union ac_shader_variant_key
627 radv_compute_tcs_key(unsigned primitive_mode, unsigned input_vertices)
628 {
629 union ac_shader_variant_key key;
630 memset(&key, 0, sizeof(key));
631 key.tcs.primitive_mode = primitive_mode;
632 key.tcs.input_vertices = input_vertices;
633 return key;
634 }
635
636 static void
637 radv_tess_pipeline_compile(struct radv_pipeline *pipeline,
638 struct radv_pipeline_cache *cache,
639 struct radv_shader_module *tcs_module,
640 struct radv_shader_module *tes_module,
641 const char *tcs_entrypoint,
642 const char *tes_entrypoint,
643 const VkSpecializationInfo *tcs_spec_info,
644 const VkSpecializationInfo *tes_spec_info,
645 struct radv_pipeline_layout *layout,
646 unsigned input_vertices)
647 {
648 unsigned char tcs_sha1[20], tes_sha1[20];
649 struct radv_shader_variant *tes_variant = NULL, *tcs_variant = NULL;
650 nir_shader *tes_nir, *tcs_nir;
651 void *tes_code = NULL, *tcs_code = NULL;
652 unsigned tes_code_size = 0, tcs_code_size = 0;
653 union ac_shader_variant_key tes_key;
654 union ac_shader_variant_key tcs_key;
655 bool dump = (pipeline->device->debug_flags & RADV_DEBUG_DUMP_SHADERS);
656
657 tes_key = radv_compute_tes_key(radv_pipeline_has_gs(pipeline),
658 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input);
659 if (tes_module->nir)
660 _mesa_sha1_compute(tes_module->nir->info.name,
661 strlen(tes_module->nir->info.name),
662 tes_module->sha1);
663 radv_hash_shader(tes_sha1, tes_module, tes_entrypoint, tes_spec_info, layout, &tes_key, 0);
664
665 tes_variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
666 cache,
667 tes_sha1);
668
669 if (tes_variant) {
670 tcs_key = radv_compute_tcs_key(tes_variant->info.tes.primitive_mode, input_vertices);
671
672 if (tcs_module->nir)
673 _mesa_sha1_compute(tcs_module->nir->info.name,
674 strlen(tcs_module->nir->info.name),
675 tcs_module->sha1);
676
677 radv_hash_shader(tcs_sha1, tcs_module, tcs_entrypoint, tcs_spec_info, layout, &tcs_key, 0);
678
679 tcs_variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
680 cache,
681 tcs_sha1);
682 }
683
684 if (tcs_variant && tes_variant) {
685 pipeline->shaders[MESA_SHADER_TESS_CTRL] = tcs_variant;
686 pipeline->shaders[MESA_SHADER_TESS_EVAL] = tes_variant;
687 return;
688 }
689
690 tes_nir = radv_shader_compile_to_nir(pipeline->device,
691 tes_module, tes_entrypoint, MESA_SHADER_TESS_EVAL,
692 tes_spec_info, dump);
693 if (tes_nir == NULL)
694 return;
695
696 tcs_nir = radv_shader_compile_to_nir(pipeline->device,
697 tcs_module, tcs_entrypoint, MESA_SHADER_TESS_CTRL,
698 tcs_spec_info, dump);
699 if (tcs_nir == NULL)
700 return;
701
702 nir_lower_tes_patch_vertices(tes_nir,
703 tcs_nir->info.tess.tcs_vertices_out);
704
705 tes_variant = radv_shader_variant_create(pipeline->device, tes_nir,
706 layout, &tes_key, &tes_code,
707 &tes_code_size, dump);
708
709 tcs_key = radv_compute_tcs_key(tes_nir->info.tess.primitive_mode, input_vertices);
710 if (tcs_module->nir)
711 _mesa_sha1_compute(tcs_module->nir->info.name,
712 strlen(tcs_module->nir->info.name),
713 tcs_module->sha1);
714
715 radv_hash_shader(tcs_sha1, tcs_module, tcs_entrypoint, tcs_spec_info, layout, &tcs_key, 0);
716
717 tcs_variant = radv_shader_variant_create(pipeline->device, tcs_nir,
718 layout, &tcs_key, &tcs_code,
719 &tcs_code_size, dump);
720
721 if (!tes_module->nir)
722 ralloc_free(tes_nir);
723
724 if (!tcs_module->nir)
725 ralloc_free(tcs_nir);
726
727 if (tes_variant)
728 tes_variant = radv_pipeline_cache_insert_shader(cache, tes_sha1, tes_variant,
729 tes_code, tes_code_size);
730
731 if (tcs_variant)
732 tcs_variant = radv_pipeline_cache_insert_shader(cache, tcs_sha1, tcs_variant,
733 tcs_code, tcs_code_size);
734
735 if (tes_code)
736 free(tes_code);
737 if (tcs_code)
738 free(tcs_code);
739 pipeline->shaders[MESA_SHADER_TESS_CTRL] = tcs_variant;
740 pipeline->shaders[MESA_SHADER_TESS_EVAL] = tes_variant;
741 return;
742 }
743
744 static VkResult
745 radv_pipeline_scratch_init(struct radv_device *device,
746 struct radv_pipeline *pipeline)
747 {
748 unsigned scratch_bytes_per_wave = 0;
749 unsigned max_waves = 0;
750 unsigned min_waves = 1;
751
752 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
753 if (pipeline->shaders[i]) {
754 unsigned max_stage_waves = device->scratch_waves;
755
756 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
757 pipeline->shaders[i]->config.scratch_bytes_per_wave);
758
759 max_stage_waves = MIN2(max_stage_waves,
760 4 * device->physical_device->rad_info.num_good_compute_units *
761 (256 / pipeline->shaders[i]->config.num_vgprs));
762 max_waves = MAX2(max_waves, max_stage_waves);
763 }
764 }
765
766 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
767 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
768 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
769 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
770 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
771 }
772
773 if (scratch_bytes_per_wave)
774 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
775
776 if (scratch_bytes_per_wave && max_waves < min_waves) {
777 /* Not really true at this moment, but will be true on first
778 * execution. Avoid having hanging shaders. */
779 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
780 }
781 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
782 pipeline->max_waves = max_waves;
783 return VK_SUCCESS;
784 }
785
786 static uint32_t si_translate_blend_function(VkBlendOp op)
787 {
788 switch (op) {
789 case VK_BLEND_OP_ADD:
790 return V_028780_COMB_DST_PLUS_SRC;
791 case VK_BLEND_OP_SUBTRACT:
792 return V_028780_COMB_SRC_MINUS_DST;
793 case VK_BLEND_OP_REVERSE_SUBTRACT:
794 return V_028780_COMB_DST_MINUS_SRC;
795 case VK_BLEND_OP_MIN:
796 return V_028780_COMB_MIN_DST_SRC;
797 case VK_BLEND_OP_MAX:
798 return V_028780_COMB_MAX_DST_SRC;
799 default:
800 return 0;
801 }
802 }
803
804 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
805 {
806 switch (factor) {
807 case VK_BLEND_FACTOR_ZERO:
808 return V_028780_BLEND_ZERO;
809 case VK_BLEND_FACTOR_ONE:
810 return V_028780_BLEND_ONE;
811 case VK_BLEND_FACTOR_SRC_COLOR:
812 return V_028780_BLEND_SRC_COLOR;
813 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
814 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
815 case VK_BLEND_FACTOR_DST_COLOR:
816 return V_028780_BLEND_DST_COLOR;
817 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
818 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
819 case VK_BLEND_FACTOR_SRC_ALPHA:
820 return V_028780_BLEND_SRC_ALPHA;
821 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
822 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
823 case VK_BLEND_FACTOR_DST_ALPHA:
824 return V_028780_BLEND_DST_ALPHA;
825 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
826 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
827 case VK_BLEND_FACTOR_CONSTANT_COLOR:
828 return V_028780_BLEND_CONSTANT_COLOR;
829 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
830 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
831 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
832 return V_028780_BLEND_CONSTANT_ALPHA;
833 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
834 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
835 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
836 return V_028780_BLEND_SRC_ALPHA_SATURATE;
837 case VK_BLEND_FACTOR_SRC1_COLOR:
838 return V_028780_BLEND_SRC1_COLOR;
839 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
840 return V_028780_BLEND_INV_SRC1_COLOR;
841 case VK_BLEND_FACTOR_SRC1_ALPHA:
842 return V_028780_BLEND_SRC1_ALPHA;
843 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
844 return V_028780_BLEND_INV_SRC1_ALPHA;
845 default:
846 return 0;
847 }
848 }
849
850 static bool is_dual_src(VkBlendFactor factor)
851 {
852 switch (factor) {
853 case VK_BLEND_FACTOR_SRC1_COLOR:
854 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
855 case VK_BLEND_FACTOR_SRC1_ALPHA:
856 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
857 return true;
858 default:
859 return false;
860 }
861 }
862
863 static unsigned si_choose_spi_color_format(VkFormat vk_format,
864 bool blend_enable,
865 bool blend_need_alpha)
866 {
867 const struct vk_format_description *desc = vk_format_description(vk_format);
868 unsigned format, ntype, swap;
869
870 /* Alpha is needed for alpha-to-coverage.
871 * Blending may be with or without alpha.
872 */
873 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
874 unsigned alpha = 0; /* exports alpha, but may not support blending */
875 unsigned blend = 0; /* supports blending, but may not export alpha */
876 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
877
878 format = radv_translate_colorformat(vk_format);
879 ntype = radv_translate_color_numformat(vk_format, desc,
880 vk_format_get_first_non_void_channel(vk_format));
881 swap = radv_translate_colorswap(vk_format, false);
882
883 /* Choose the SPI color formats. These are required values for Stoney/RB+.
884 * Other chips have multiple choices, though they are not necessarily better.
885 */
886 switch (format) {
887 case V_028C70_COLOR_5_6_5:
888 case V_028C70_COLOR_1_5_5_5:
889 case V_028C70_COLOR_5_5_5_1:
890 case V_028C70_COLOR_4_4_4_4:
891 case V_028C70_COLOR_10_11_11:
892 case V_028C70_COLOR_11_11_10:
893 case V_028C70_COLOR_8:
894 case V_028C70_COLOR_8_8:
895 case V_028C70_COLOR_8_8_8_8:
896 case V_028C70_COLOR_10_10_10_2:
897 case V_028C70_COLOR_2_10_10_10:
898 if (ntype == V_028C70_NUMBER_UINT)
899 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
900 else if (ntype == V_028C70_NUMBER_SINT)
901 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
902 else
903 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
904 break;
905
906 case V_028C70_COLOR_16:
907 case V_028C70_COLOR_16_16:
908 case V_028C70_COLOR_16_16_16_16:
909 if (ntype == V_028C70_NUMBER_UNORM ||
910 ntype == V_028C70_NUMBER_SNORM) {
911 /* UNORM16 and SNORM16 don't support blending */
912 if (ntype == V_028C70_NUMBER_UNORM)
913 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
914 else
915 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
916
917 /* Use 32 bits per channel for blending. */
918 if (format == V_028C70_COLOR_16) {
919 if (swap == V_028C70_SWAP_STD) { /* R */
920 blend = V_028714_SPI_SHADER_32_R;
921 blend_alpha = V_028714_SPI_SHADER_32_AR;
922 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
923 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
924 else
925 assert(0);
926 } else if (format == V_028C70_COLOR_16_16) {
927 if (swap == V_028C70_SWAP_STD) { /* RG */
928 blend = V_028714_SPI_SHADER_32_GR;
929 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
930 } else if (swap == V_028C70_SWAP_ALT) /* RA */
931 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
932 else
933 assert(0);
934 } else /* 16_16_16_16 */
935 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
936 } else if (ntype == V_028C70_NUMBER_UINT)
937 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
938 else if (ntype == V_028C70_NUMBER_SINT)
939 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
940 else if (ntype == V_028C70_NUMBER_FLOAT)
941 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
942 else
943 assert(0);
944 break;
945
946 case V_028C70_COLOR_32:
947 if (swap == V_028C70_SWAP_STD) { /* R */
948 blend = normal = V_028714_SPI_SHADER_32_R;
949 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
950 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
951 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
952 else
953 assert(0);
954 break;
955
956 case V_028C70_COLOR_32_32:
957 if (swap == V_028C70_SWAP_STD) { /* RG */
958 blend = normal = V_028714_SPI_SHADER_32_GR;
959 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
960 } else if (swap == V_028C70_SWAP_ALT) /* RA */
961 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
962 else
963 assert(0);
964 break;
965
966 case V_028C70_COLOR_32_32_32_32:
967 case V_028C70_COLOR_8_24:
968 case V_028C70_COLOR_24_8:
969 case V_028C70_COLOR_X24_8_32_FLOAT:
970 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
971 break;
972
973 default:
974 unreachable("unhandled blend format");
975 }
976
977 if (blend_enable && blend_need_alpha)
978 return blend_alpha;
979 else if(blend_need_alpha)
980 return alpha;
981 else if(blend_enable)
982 return blend;
983 else
984 return normal;
985 }
986
987 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
988 {
989 unsigned i, cb_shader_mask = 0;
990
991 for (i = 0; i < 8; i++) {
992 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
993 case V_028714_SPI_SHADER_ZERO:
994 break;
995 case V_028714_SPI_SHADER_32_R:
996 cb_shader_mask |= 0x1 << (i * 4);
997 break;
998 case V_028714_SPI_SHADER_32_GR:
999 cb_shader_mask |= 0x3 << (i * 4);
1000 break;
1001 case V_028714_SPI_SHADER_32_AR:
1002 cb_shader_mask |= 0x9 << (i * 4);
1003 break;
1004 case V_028714_SPI_SHADER_FP16_ABGR:
1005 case V_028714_SPI_SHADER_UNORM16_ABGR:
1006 case V_028714_SPI_SHADER_SNORM16_ABGR:
1007 case V_028714_SPI_SHADER_UINT16_ABGR:
1008 case V_028714_SPI_SHADER_SINT16_ABGR:
1009 case V_028714_SPI_SHADER_32_ABGR:
1010 cb_shader_mask |= 0xf << (i * 4);
1011 break;
1012 default:
1013 assert(0);
1014 }
1015 }
1016 return cb_shader_mask;
1017 }
1018
1019 static void
1020 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
1021 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1022 uint32_t blend_enable,
1023 uint32_t blend_need_alpha,
1024 bool single_cb_enable,
1025 bool blend_mrt0_is_dual_src)
1026 {
1027 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1028 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
1029 struct radv_blend_state *blend = &pipeline->graphics.blend;
1030 unsigned col_format = 0;
1031
1032 for (unsigned i = 0; i < (single_cb_enable ? 1 : subpass->color_count); ++i) {
1033 struct radv_render_pass_attachment *attachment;
1034 unsigned cf;
1035
1036 attachment = pass->attachments + subpass->color_attachments[i].attachment;
1037
1038 cf = si_choose_spi_color_format(attachment->format,
1039 blend_enable & (1 << i),
1040 blend_need_alpha & (1 << i));
1041
1042 col_format |= cf << (4 * i);
1043 }
1044
1045 blend->cb_shader_mask = si_get_cb_shader_mask(col_format);
1046
1047 if (blend_mrt0_is_dual_src)
1048 col_format |= (col_format & 0xf) << 4;
1049 blend->spi_shader_col_format = col_format;
1050 }
1051
1052 static bool
1053 format_is_int8(VkFormat format)
1054 {
1055 const struct vk_format_description *desc = vk_format_description(format);
1056 int channel = vk_format_get_first_non_void_channel(format);
1057
1058 return channel >= 0 && desc->channel[channel].pure_integer &&
1059 desc->channel[channel].size == 8;
1060 }
1061
1062 unsigned radv_format_meta_fs_key(VkFormat format)
1063 {
1064 unsigned col_format = si_choose_spi_color_format(format, false, false) - 1;
1065 bool is_int8 = format_is_int8(format);
1066
1067 return col_format + (is_int8 ? 3 : 0);
1068 }
1069
1070 static unsigned
1071 radv_pipeline_compute_is_int8(const VkGraphicsPipelineCreateInfo *pCreateInfo)
1072 {
1073 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1074 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
1075 unsigned is_int8 = 0;
1076
1077 for (unsigned i = 0; i < subpass->color_count; ++i) {
1078 struct radv_render_pass_attachment *attachment;
1079
1080 attachment = pass->attachments + subpass->color_attachments[i].attachment;
1081
1082 if (format_is_int8(attachment->format))
1083 is_int8 |= 1 << i;
1084 }
1085
1086 return is_int8;
1087 }
1088
1089 static void
1090 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
1091 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1092 const struct radv_graphics_pipeline_create_info *extra)
1093 {
1094 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
1095 struct radv_blend_state *blend = &pipeline->graphics.blend;
1096 unsigned mode = V_028808_CB_NORMAL;
1097 uint32_t blend_enable = 0, blend_need_alpha = 0;
1098 bool blend_mrt0_is_dual_src = false;
1099 int i;
1100 bool single_cb_enable = false;
1101
1102 if (!vkblend)
1103 return;
1104
1105 if (extra && extra->custom_blend_mode) {
1106 single_cb_enable = true;
1107 mode = extra->custom_blend_mode;
1108 }
1109 blend->cb_color_control = 0;
1110 if (vkblend->logicOpEnable)
1111 blend->cb_color_control |= S_028808_ROP3(vkblend->logicOp | (vkblend->logicOp << 4));
1112 else
1113 blend->cb_color_control |= S_028808_ROP3(0xcc);
1114
1115 blend->db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
1116 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
1117 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
1118 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
1119
1120 blend->cb_target_mask = 0;
1121 for (i = 0; i < vkblend->attachmentCount; i++) {
1122 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
1123 unsigned blend_cntl = 0;
1124 VkBlendOp eqRGB = att->colorBlendOp;
1125 VkBlendFactor srcRGB = att->srcColorBlendFactor;
1126 VkBlendFactor dstRGB = att->dstColorBlendFactor;
1127 VkBlendOp eqA = att->alphaBlendOp;
1128 VkBlendFactor srcA = att->srcAlphaBlendFactor;
1129 VkBlendFactor dstA = att->dstAlphaBlendFactor;
1130
1131 blend->sx_mrt0_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
1132
1133 if (!att->colorWriteMask)
1134 continue;
1135
1136 blend->cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
1137 if (!att->blendEnable) {
1138 blend->cb_blend_control[i] = blend_cntl;
1139 continue;
1140 }
1141
1142 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
1143 if (i == 0)
1144 blend_mrt0_is_dual_src = true;
1145
1146 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
1147 srcRGB = VK_BLEND_FACTOR_ONE;
1148 dstRGB = VK_BLEND_FACTOR_ONE;
1149 }
1150 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
1151 srcA = VK_BLEND_FACTOR_ONE;
1152 dstA = VK_BLEND_FACTOR_ONE;
1153 }
1154
1155 blend_cntl |= S_028780_ENABLE(1);
1156
1157 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
1158 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
1159 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
1160 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
1161 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
1162 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
1163 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
1164 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
1165 }
1166 blend->cb_blend_control[i] = blend_cntl;
1167
1168 blend_enable |= 1 << i;
1169
1170 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
1171 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
1172 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
1173 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
1174 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
1175 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
1176 blend_need_alpha |= 1 << i;
1177 }
1178 for (i = vkblend->attachmentCount; i < 8; i++)
1179 blend->cb_blend_control[i] = 0;
1180
1181 if (blend->cb_target_mask)
1182 blend->cb_color_control |= S_028808_MODE(mode);
1183 else
1184 blend->cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
1185
1186 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo,
1187 blend_enable, blend_need_alpha, single_cb_enable, blend_mrt0_is_dual_src);
1188 }
1189
1190 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
1191 {
1192 switch (op) {
1193 case VK_STENCIL_OP_KEEP:
1194 return V_02842C_STENCIL_KEEP;
1195 case VK_STENCIL_OP_ZERO:
1196 return V_02842C_STENCIL_ZERO;
1197 case VK_STENCIL_OP_REPLACE:
1198 return V_02842C_STENCIL_REPLACE_TEST;
1199 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
1200 return V_02842C_STENCIL_ADD_CLAMP;
1201 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
1202 return V_02842C_STENCIL_SUB_CLAMP;
1203 case VK_STENCIL_OP_INVERT:
1204 return V_02842C_STENCIL_INVERT;
1205 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
1206 return V_02842C_STENCIL_ADD_WRAP;
1207 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
1208 return V_02842C_STENCIL_SUB_WRAP;
1209 default:
1210 return 0;
1211 }
1212 }
1213 static void
1214 radv_pipeline_init_depth_stencil_state(struct radv_pipeline *pipeline,
1215 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1216 const struct radv_graphics_pipeline_create_info *extra)
1217 {
1218 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
1219 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
1220
1221 memset(ds, 0, sizeof(*ds));
1222 if (!vkds)
1223 return;
1224
1225 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1226 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
1227 if (subpass->depth_stencil_attachment.attachment == VK_ATTACHMENT_UNUSED)
1228 return;
1229
1230 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment.attachment;
1231 bool has_depth_attachment = vk_format_is_depth(attachment->format);
1232 bool has_stencil_attachment = vk_format_is_stencil(attachment->format);
1233
1234 if (has_depth_attachment) {
1235 ds->db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
1236 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
1237 S_028800_ZFUNC(vkds->depthCompareOp) |
1238 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
1239 }
1240
1241 if (has_stencil_attachment && vkds->stencilTestEnable) {
1242 ds->db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
1243 ds->db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
1244 ds->db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
1245 ds->db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
1246 ds->db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
1247
1248 ds->db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
1249 ds->db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
1250 ds->db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
1251 ds->db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
1252 }
1253
1254 if (extra) {
1255
1256 ds->db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
1257 ds->db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
1258
1259 ds->db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
1260 ds->db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
1261 ds->db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
1262 ds->db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
1263 ds->db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
1264 }
1265 }
1266
1267 static uint32_t si_translate_fill(VkPolygonMode func)
1268 {
1269 switch(func) {
1270 case VK_POLYGON_MODE_FILL:
1271 return V_028814_X_DRAW_TRIANGLES;
1272 case VK_POLYGON_MODE_LINE:
1273 return V_028814_X_DRAW_LINES;
1274 case VK_POLYGON_MODE_POINT:
1275 return V_028814_X_DRAW_POINTS;
1276 default:
1277 assert(0);
1278 return V_028814_X_DRAW_POINTS;
1279 }
1280 }
1281 static void
1282 radv_pipeline_init_raster_state(struct radv_pipeline *pipeline,
1283 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1284 {
1285 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
1286 struct radv_raster_state *raster = &pipeline->graphics.raster;
1287
1288 memset(raster, 0, sizeof(*raster));
1289
1290 raster->spi_interp_control =
1291 S_0286D4_FLAT_SHADE_ENA(1) |
1292 S_0286D4_PNT_SPRITE_ENA(1) |
1293 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
1294 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
1295 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
1296 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
1297 S_0286D4_PNT_SPRITE_TOP_1(0); // vulkan is top to bottom - 1.0 at bottom
1298
1299
1300 raster->pa_cl_clip_cntl = S_028810_PS_UCP_MODE(3) |
1301 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
1302 S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1303 S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1304 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
1305 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
1306
1307 raster->pa_su_vtx_cntl =
1308 S_028BE4_PIX_CENTER(1) | // TODO verify
1309 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
1310 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH);
1311
1312 raster->pa_su_sc_mode_cntl =
1313 S_028814_FACE(vkraster->frontFace) |
1314 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
1315 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
1316 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
1317 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1318 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1319 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1320 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1321 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0);
1322
1323 }
1324
1325 static void
1326 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1327 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1328 {
1329 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
1330 struct radv_blend_state *blend = &pipeline->graphics.blend;
1331 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1332 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1333 int ps_iter_samples = 1;
1334 uint32_t mask = 0xffff;
1335
1336 if (vkms)
1337 ms->num_samples = vkms->rasterizationSamples;
1338 else
1339 ms->num_samples = 1;
1340
1341 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.force_persample) {
1342 ps_iter_samples = ms->num_samples;
1343 }
1344
1345 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1346 ms->pa_sc_aa_config = 0;
1347 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1348 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1349 ms->pa_sc_mode_cntl_1 =
1350 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1351 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1352 /* always 1: */
1353 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1354 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1355 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1356 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1357 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1358 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1359 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9);
1360
1361 if (ms->num_samples > 1) {
1362 unsigned log_samples = util_logbase2(ms->num_samples);
1363 unsigned log_ps_iter_samples = util_logbase2(util_next_power_of_two(ps_iter_samples));
1364 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
1365 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1366 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1367 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1368 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1369 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1370 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1371 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
1372 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1373 ms->pa_sc_mode_cntl_1 |= EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1374 }
1375
1376 if (vkms) {
1377 if (vkms->alphaToCoverageEnable)
1378 blend->db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
1379
1380 if (vkms->pSampleMask)
1381 mask = vkms->pSampleMask[0] & 0xffff;
1382 }
1383
1384 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1385 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1386 }
1387
1388 static bool
1389 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1390 {
1391 switch (topology) {
1392 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1393 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1394 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1395 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1396 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1397 return false;
1398 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1399 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1400 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1401 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1402 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1403 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1404 return true;
1405 default:
1406 unreachable("unhandled primitive type");
1407 }
1408 }
1409
1410 static uint32_t
1411 si_translate_prim(enum VkPrimitiveTopology topology)
1412 {
1413 switch (topology) {
1414 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1415 return V_008958_DI_PT_POINTLIST;
1416 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1417 return V_008958_DI_PT_LINELIST;
1418 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1419 return V_008958_DI_PT_LINESTRIP;
1420 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1421 return V_008958_DI_PT_TRILIST;
1422 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1423 return V_008958_DI_PT_TRISTRIP;
1424 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1425 return V_008958_DI_PT_TRIFAN;
1426 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1427 return V_008958_DI_PT_LINELIST_ADJ;
1428 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1429 return V_008958_DI_PT_LINESTRIP_ADJ;
1430 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1431 return V_008958_DI_PT_TRILIST_ADJ;
1432 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1433 return V_008958_DI_PT_TRISTRIP_ADJ;
1434 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1435 return V_008958_DI_PT_PATCH;
1436 default:
1437 assert(0);
1438 return 0;
1439 }
1440 }
1441
1442 static uint32_t
1443 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1444 {
1445 switch (gl_prim) {
1446 case 0: /* GL_POINTS */
1447 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1448 case 1: /* GL_LINES */
1449 case 3: /* GL_LINE_STRIP */
1450 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1451 case 0x8E7A: /* GL_ISOLINES */
1452 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1453
1454 case 4: /* GL_TRIANGLES */
1455 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1456 case 5: /* GL_TRIANGLE_STRIP */
1457 case 7: /* GL_QUADS */
1458 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1459 default:
1460 assert(0);
1461 return 0;
1462 }
1463 }
1464
1465 static uint32_t
1466 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1467 {
1468 switch (topology) {
1469 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1470 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1471 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1472 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1473 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1474 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1475 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1476 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1477 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1478 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1479 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1480 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1481 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1482 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1483 default:
1484 assert(0);
1485 return 0;
1486 }
1487 }
1488
1489 static unsigned si_map_swizzle(unsigned swizzle)
1490 {
1491 switch (swizzle) {
1492 case VK_SWIZZLE_Y:
1493 return V_008F0C_SQ_SEL_Y;
1494 case VK_SWIZZLE_Z:
1495 return V_008F0C_SQ_SEL_Z;
1496 case VK_SWIZZLE_W:
1497 return V_008F0C_SQ_SEL_W;
1498 case VK_SWIZZLE_0:
1499 return V_008F0C_SQ_SEL_0;
1500 case VK_SWIZZLE_1:
1501 return V_008F0C_SQ_SEL_1;
1502 default: /* VK_SWIZZLE_X */
1503 return V_008F0C_SQ_SEL_X;
1504 }
1505 }
1506
1507 static void
1508 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1509 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1510 {
1511 radv_cmd_dirty_mask_t states = RADV_CMD_DIRTY_DYNAMIC_ALL;
1512 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1513 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1514
1515 pipeline->dynamic_state = default_dynamic_state;
1516
1517 if (pCreateInfo->pDynamicState) {
1518 /* Remove all of the states that are marked as dynamic */
1519 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1520 for (uint32_t s = 0; s < count; s++)
1521 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
1522 }
1523
1524 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1525
1526 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1527 *
1528 * pViewportState is [...] NULL if the pipeline
1529 * has rasterization disabled.
1530 */
1531 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1532 assert(pCreateInfo->pViewportState);
1533
1534 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1535 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
1536 typed_memcpy(dynamic->viewport.viewports,
1537 pCreateInfo->pViewportState->pViewports,
1538 pCreateInfo->pViewportState->viewportCount);
1539 }
1540
1541 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1542 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
1543 typed_memcpy(dynamic->scissor.scissors,
1544 pCreateInfo->pViewportState->pScissors,
1545 pCreateInfo->pViewportState->scissorCount);
1546 }
1547 }
1548
1549 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
1550 assert(pCreateInfo->pRasterizationState);
1551 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1552 }
1553
1554 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
1555 assert(pCreateInfo->pRasterizationState);
1556 dynamic->depth_bias.bias =
1557 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1558 dynamic->depth_bias.clamp =
1559 pCreateInfo->pRasterizationState->depthBiasClamp;
1560 dynamic->depth_bias.slope =
1561 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1562 }
1563
1564 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1565 *
1566 * pColorBlendState is [...] NULL if the pipeline has rasterization
1567 * disabled or if the subpass of the render pass the pipeline is
1568 * created against does not use any color attachments.
1569 */
1570 bool uses_color_att = false;
1571 for (unsigned i = 0; i < subpass->color_count; ++i) {
1572 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1573 uses_color_att = true;
1574 break;
1575 }
1576 }
1577
1578 if (uses_color_att && states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
1579 assert(pCreateInfo->pColorBlendState);
1580 typed_memcpy(dynamic->blend_constants,
1581 pCreateInfo->pColorBlendState->blendConstants, 4);
1582 }
1583
1584 /* If there is no depthstencil attachment, then don't read
1585 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1586 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1587 * no need to override the depthstencil defaults in
1588 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1589 *
1590 * Section 9.2 of the Vulkan 1.0.15 spec says:
1591 *
1592 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1593 * disabled or if the subpass of the render pass the pipeline is created
1594 * against does not use a depth/stencil attachment.
1595 */
1596 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
1597 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1598 assert(pCreateInfo->pDepthStencilState);
1599
1600 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
1601 dynamic->depth_bounds.min =
1602 pCreateInfo->pDepthStencilState->minDepthBounds;
1603 dynamic->depth_bounds.max =
1604 pCreateInfo->pDepthStencilState->maxDepthBounds;
1605 }
1606
1607 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
1608 dynamic->stencil_compare_mask.front =
1609 pCreateInfo->pDepthStencilState->front.compareMask;
1610 dynamic->stencil_compare_mask.back =
1611 pCreateInfo->pDepthStencilState->back.compareMask;
1612 }
1613
1614 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
1615 dynamic->stencil_write_mask.front =
1616 pCreateInfo->pDepthStencilState->front.writeMask;
1617 dynamic->stencil_write_mask.back =
1618 pCreateInfo->pDepthStencilState->back.writeMask;
1619 }
1620
1621 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
1622 dynamic->stencil_reference.front =
1623 pCreateInfo->pDepthStencilState->front.reference;
1624 dynamic->stencil_reference.back =
1625 pCreateInfo->pDepthStencilState->back.reference;
1626 }
1627 }
1628
1629 pipeline->dynamic_state_mask = states;
1630 }
1631
1632 static union ac_shader_variant_key
1633 radv_compute_vs_key(const VkGraphicsPipelineCreateInfo *pCreateInfo, bool as_es, bool as_ls, bool export_prim_id)
1634 {
1635 union ac_shader_variant_key key;
1636 const VkPipelineVertexInputStateCreateInfo *input_state =
1637 pCreateInfo->pVertexInputState;
1638
1639 memset(&key, 0, sizeof(key));
1640 key.vs.instance_rate_inputs = 0;
1641 key.vs.as_es = as_es;
1642 key.vs.as_ls = as_ls;
1643 key.vs.export_prim_id = export_prim_id;
1644
1645 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
1646 unsigned binding;
1647 binding = input_state->pVertexAttributeDescriptions[i].binding;
1648 if (input_state->pVertexBindingDescriptions[binding].inputRate)
1649 key.vs.instance_rate_inputs |= 1u << input_state->pVertexAttributeDescriptions[i].location;
1650 }
1651 return key;
1652 }
1653
1654 static void
1655 calculate_gs_ring_sizes(struct radv_pipeline *pipeline)
1656 {
1657 struct radv_device *device = pipeline->device;
1658 unsigned num_se = device->physical_device->rad_info.max_se;
1659 unsigned wave_size = 64;
1660 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1661 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1662 unsigned alignment = 256 * num_se;
1663 /* The maximum size is 63.999 MB per SE. */
1664 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1665 struct ac_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1666 struct ac_es_output_info *es_info = radv_pipeline_has_tess(pipeline) ?
1667 &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.es_info :
1668 &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info;
1669
1670 /* Calculate the minimum size. */
1671 unsigned min_esgs_ring_size = align(es_info->esgs_itemsize * gs_vertex_reuse *
1672 wave_size, alignment);
1673 /* These are recommended sizes, not minimum sizes. */
1674 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1675 es_info->esgs_itemsize * gs_info->gs.vertices_in;
1676 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1677 gs_info->gs.max_gsvs_emit_size * 1; // no streams in VK (gs->max_gs_stream + 1);
1678
1679 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1680 esgs_ring_size = align(esgs_ring_size, alignment);
1681 gsvs_ring_size = align(gsvs_ring_size, alignment);
1682
1683 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1684 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1685 }
1686
1687 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1688 unsigned *lds_size)
1689 {
1690 /* SPI barrier management bug:
1691 * Make sure we have at least 4k of LDS in use to avoid the bug.
1692 * It applies to workgroup sizes of more than one wavefront.
1693 */
1694 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1695 device->physical_device->rad_info.family == CHIP_KABINI ||
1696 device->physical_device->rad_info.family == CHIP_MULLINS)
1697 *lds_size = MAX2(*lds_size, 8);
1698 }
1699
1700 static void
1701 calculate_tess_state(struct radv_pipeline *pipeline,
1702 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1703 {
1704 unsigned num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1705 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
1706 unsigned num_tcs_patch_outputs;
1707 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
1708 unsigned input_patch_size, output_patch_size, output_patch0_offset;
1709 unsigned lds_size, hardware_lds_size;
1710 unsigned perpatch_output_offset;
1711 unsigned num_patches;
1712 struct radv_tessellation_state *tess = &pipeline->graphics.tess;
1713
1714 /* This calculates how shader inputs and outputs among VS, TCS, and TES
1715 * are laid out in LDS. */
1716 num_tcs_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outputs_written);
1717
1718 num_tcs_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written); //tcs->outputs_written
1719 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1720 num_tcs_patch_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.patch_outputs_written);
1721
1722 /* Ensure that we only need one wave per SIMD so we don't need to check
1723 * resource usage. Also ensures that the number of tcs in and out
1724 * vertices per threadgroup are at most 256.
1725 */
1726 input_vertex_size = num_tcs_inputs * 16;
1727 output_vertex_size = num_tcs_outputs * 16;
1728
1729 input_patch_size = num_tcs_input_cp * input_vertex_size;
1730
1731 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
1732 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
1733 /* Ensure that we only need one wave per SIMD so we don't need to check
1734 * resource usage. Also ensures that the number of tcs in and out
1735 * vertices per threadgroup are at most 256.
1736 */
1737 num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
1738
1739 /* Make sure that the data fits in LDS. This assumes the shaders only
1740 * use LDS for the inputs and outputs.
1741 */
1742 hardware_lds_size = pipeline->device->physical_device->rad_info.chip_class >= CIK ? 65536 : 32768;
1743 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
1744
1745 /* Make sure the output data fits in the offchip buffer */
1746 num_patches = MIN2(num_patches,
1747 (pipeline->device->tess_offchip_block_dw_size * 4) /
1748 output_patch_size);
1749
1750 /* Not necessary for correctness, but improves performance. The
1751 * specific value is taken from the proprietary driver.
1752 */
1753 num_patches = MIN2(num_patches, 40);
1754
1755 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
1756 if (pipeline->device->physical_device->rad_info.chip_class == SI) {
1757 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
1758 num_patches = MIN2(num_patches, one_wave);
1759 }
1760
1761 output_patch0_offset = input_patch_size * num_patches;
1762 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
1763
1764 lds_size = output_patch0_offset + output_patch_size * num_patches;
1765
1766 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
1767 assert(lds_size <= 65536);
1768 lds_size = align(lds_size, 512) / 512;
1769 } else {
1770 assert(lds_size <= 32768);
1771 lds_size = align(lds_size, 256) / 256;
1772 }
1773 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1774
1775 tess->lds_size = lds_size;
1776
1777 tess->tcs_in_layout = (input_patch_size / 4) |
1778 ((input_vertex_size / 4) << 13);
1779 tess->tcs_out_layout = (output_patch_size / 4) |
1780 ((output_vertex_size / 4) << 13);
1781 tess->tcs_out_offsets = (output_patch0_offset / 16) |
1782 ((perpatch_output_offset / 16) << 16);
1783 tess->offchip_layout = (pervertex_output_patch_size * num_patches << 16) |
1784 (num_tcs_output_cp << 9) | num_patches;
1785
1786 tess->ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1787 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1788 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1789 tess->num_patches = num_patches;
1790 tess->num_tcs_input_cp = num_tcs_input_cp;
1791
1792 struct radv_shader_variant *tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
1793 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1794
1795 switch (tes->info.tes.primitive_mode) {
1796 case GL_TRIANGLES:
1797 type = V_028B6C_TESS_TRIANGLE;
1798 break;
1799 case GL_QUADS:
1800 type = V_028B6C_TESS_QUAD;
1801 break;
1802 case GL_ISOLINES:
1803 type = V_028B6C_TESS_ISOLINE;
1804 break;
1805 }
1806
1807 switch (tes->info.tes.spacing) {
1808 case TESS_SPACING_EQUAL:
1809 partitioning = V_028B6C_PART_INTEGER;
1810 break;
1811 case TESS_SPACING_FRACTIONAL_ODD:
1812 partitioning = V_028B6C_PART_FRAC_ODD;
1813 break;
1814 case TESS_SPACING_FRACTIONAL_EVEN:
1815 partitioning = V_028B6C_PART_FRAC_EVEN;
1816 break;
1817 default:
1818 break;
1819 }
1820
1821 if (tes->info.tes.point_mode)
1822 topology = V_028B6C_OUTPUT_POINT;
1823 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
1824 topology = V_028B6C_OUTPUT_LINE;
1825 else if (tes->info.tes.ccw)
1826 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
1827 else
1828 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
1829
1830 if (pipeline->device->has_distributed_tess) {
1831 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
1832 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
1833 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
1834 else
1835 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
1836 } else
1837 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
1838
1839 tess->tf_param = S_028B6C_TYPE(type) |
1840 S_028B6C_PARTITIONING(partitioning) |
1841 S_028B6C_TOPOLOGY(topology) |
1842 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
1843 }
1844
1845 static const struct radv_prim_vertex_count prim_size_table[] = {
1846 [V_008958_DI_PT_NONE] = {0, 0},
1847 [V_008958_DI_PT_POINTLIST] = {1, 1},
1848 [V_008958_DI_PT_LINELIST] = {2, 2},
1849 [V_008958_DI_PT_LINESTRIP] = {2, 1},
1850 [V_008958_DI_PT_TRILIST] = {3, 3},
1851 [V_008958_DI_PT_TRIFAN] = {3, 1},
1852 [V_008958_DI_PT_TRISTRIP] = {3, 1},
1853 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
1854 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
1855 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
1856 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
1857 [V_008958_DI_PT_RECTLIST] = {3, 3},
1858 [V_008958_DI_PT_LINELOOP] = {2, 1},
1859 [V_008958_DI_PT_POLYGON] = {3, 1},
1860 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
1861 };
1862
1863 static uint32_t si_vgt_gs_mode(struct radv_shader_variant *gs)
1864 {
1865 unsigned gs_max_vert_out = gs->info.gs.vertices_out;
1866 unsigned cut_mode;
1867
1868 if (gs_max_vert_out <= 128) {
1869 cut_mode = V_028A40_GS_CUT_128;
1870 } else if (gs_max_vert_out <= 256) {
1871 cut_mode = V_028A40_GS_CUT_256;
1872 } else if (gs_max_vert_out <= 512) {
1873 cut_mode = V_028A40_GS_CUT_512;
1874 } else {
1875 assert(gs_max_vert_out <= 1024);
1876 cut_mode = V_028A40_GS_CUT_1024;
1877 }
1878
1879 return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
1880 S_028A40_CUT_MODE(cut_mode)|
1881 S_028A40_ES_WRITE_OPTIMIZE(1) |
1882 S_028A40_GS_WRITE_OPTIMIZE(1);
1883 }
1884
1885 static void calculate_vgt_gs_mode(struct radv_pipeline *pipeline)
1886 {
1887 struct radv_shader_variant *vs;
1888 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : (radv_pipeline_has_tess(pipeline) ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX]);
1889
1890 struct ac_vs_output_info *outinfo = &vs->info.vs.outinfo;
1891
1892 pipeline->graphics.vgt_primitiveid_en = false;
1893 pipeline->graphics.vgt_gs_mode = 0;
1894
1895 if (radv_pipeline_has_gs(pipeline)) {
1896 pipeline->graphics.vgt_gs_mode = si_vgt_gs_mode(pipeline->shaders[MESA_SHADER_GEOMETRY]);
1897 } else if (outinfo->export_prim_id) {
1898 pipeline->graphics.vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
1899 pipeline->graphics.vgt_primitiveid_en = true;
1900 }
1901 }
1902
1903 static void calculate_pa_cl_vs_out_cntl(struct radv_pipeline *pipeline)
1904 {
1905 struct radv_shader_variant *vs;
1906 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : (radv_pipeline_has_tess(pipeline) ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX]);
1907
1908 struct ac_vs_output_info *outinfo = &vs->info.vs.outinfo;
1909
1910 unsigned clip_dist_mask, cull_dist_mask, total_mask;
1911 clip_dist_mask = outinfo->clip_dist_mask;
1912 cull_dist_mask = outinfo->cull_dist_mask;
1913 total_mask = clip_dist_mask | cull_dist_mask;
1914
1915 bool misc_vec_ena = outinfo->writes_pointsize ||
1916 outinfo->writes_layer ||
1917 outinfo->writes_viewport_index;
1918 pipeline->graphics.pa_cl_vs_out_cntl =
1919 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
1920 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
1921 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
1922 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
1923 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
1924 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
1925 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
1926 cull_dist_mask << 8 |
1927 clip_dist_mask;
1928
1929 }
1930
1931 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade)
1932 {
1933 uint32_t ps_input_cntl;
1934 if (offset <= AC_EXP_PARAM_OFFSET_31) {
1935 ps_input_cntl = S_028644_OFFSET(offset);
1936 if (flat_shade)
1937 ps_input_cntl |= S_028644_FLAT_SHADE(1);
1938 } else {
1939 /* The input is a DEFAULT_VAL constant. */
1940 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
1941 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
1942 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
1943 ps_input_cntl = S_028644_OFFSET(0x20) |
1944 S_028644_DEFAULT_VAL(offset);
1945 }
1946 return ps_input_cntl;
1947 }
1948
1949 static void calculate_ps_inputs(struct radv_pipeline *pipeline)
1950 {
1951 struct radv_shader_variant *ps, *vs;
1952 struct ac_vs_output_info *outinfo;
1953
1954 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
1955 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : (radv_pipeline_has_tess(pipeline) ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX]);
1956
1957 outinfo = &vs->info.vs.outinfo;
1958
1959 unsigned ps_offset = 0;
1960
1961 if (ps->info.fs.prim_id_input) {
1962 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
1963 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
1964 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
1965 ++ps_offset;
1966 }
1967 }
1968
1969 if (ps->info.fs.layer_input) {
1970 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
1971 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
1972 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
1973 ++ps_offset;
1974 }
1975 }
1976
1977 if (ps->info.fs.has_pcoord) {
1978 unsigned val;
1979 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
1980 pipeline->graphics.ps_input_cntl[ps_offset] = val;
1981 ps_offset++;
1982 }
1983
1984 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
1985 unsigned vs_offset;
1986 bool flat_shade;
1987 if (!(ps->info.fs.input_mask & (1u << i)))
1988 continue;
1989
1990 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
1991 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
1992 pipeline->graphics.ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
1993 ++ps_offset;
1994 continue;
1995 }
1996
1997 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
1998
1999 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade);
2000 ++ps_offset;
2001 }
2002
2003 pipeline->graphics.ps_input_cntl_num = ps_offset;
2004 }
2005
2006 VkResult
2007 radv_pipeline_init(struct radv_pipeline *pipeline,
2008 struct radv_device *device,
2009 struct radv_pipeline_cache *cache,
2010 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2011 const struct radv_graphics_pipeline_create_info *extra,
2012 const VkAllocationCallbacks *alloc)
2013 {
2014 struct radv_shader_module fs_m = {0};
2015 VkResult result;
2016
2017 if (alloc == NULL)
2018 alloc = &device->alloc;
2019
2020 pipeline->device = device;
2021 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
2022
2023 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
2024 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
2025 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
2026 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
2027 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
2028 pStages[stage] = &pCreateInfo->pStages[i];
2029 modules[stage] = radv_shader_module_from_handle(pStages[stage]->module);
2030 }
2031
2032 radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
2033
2034 if (!modules[MESA_SHADER_FRAGMENT]) {
2035 nir_builder fs_b;
2036 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
2037 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
2038 fs_m.nir = fs_b.shader;
2039 modules[MESA_SHADER_FRAGMENT] = &fs_m;
2040 }
2041
2042 if (modules[MESA_SHADER_FRAGMENT]) {
2043 union ac_shader_variant_key key;
2044 key.fs.col_format = pipeline->graphics.blend.spi_shader_col_format;
2045 key.fs.is_int8 = radv_pipeline_compute_is_int8(pCreateInfo);
2046
2047 const VkPipelineShaderStageCreateInfo *stage = pStages[MESA_SHADER_FRAGMENT];
2048
2049 pipeline->shaders[MESA_SHADER_FRAGMENT] =
2050 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_FRAGMENT],
2051 stage ? stage->pName : "main",
2052 MESA_SHADER_FRAGMENT,
2053 stage ? stage->pSpecializationInfo : NULL,
2054 pipeline->layout, &key);
2055 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_FRAGMENT);
2056 }
2057
2058 if (fs_m.nir)
2059 ralloc_free(fs_m.nir);
2060
2061 if (modules[MESA_SHADER_VERTEX]) {
2062 bool as_es = false;
2063 bool as_ls = false;
2064 bool export_prim_id = false;
2065 if (modules[MESA_SHADER_TESS_CTRL])
2066 as_ls = true;
2067 else if (modules[MESA_SHADER_GEOMETRY])
2068 as_es = true;
2069 else if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input)
2070 export_prim_id = true;
2071 union ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo, as_es, as_ls, export_prim_id);
2072
2073 pipeline->shaders[MESA_SHADER_VERTEX] =
2074 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_VERTEX],
2075 pStages[MESA_SHADER_VERTEX]->pName,
2076 MESA_SHADER_VERTEX,
2077 pStages[MESA_SHADER_VERTEX]->pSpecializationInfo,
2078 pipeline->layout, &key);
2079
2080 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_VERTEX);
2081 }
2082
2083 if (modules[MESA_SHADER_GEOMETRY]) {
2084 union ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo, false, false, false);
2085
2086 pipeline->shaders[MESA_SHADER_GEOMETRY] =
2087 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_GEOMETRY],
2088 pStages[MESA_SHADER_GEOMETRY]->pName,
2089 MESA_SHADER_GEOMETRY,
2090 pStages[MESA_SHADER_GEOMETRY]->pSpecializationInfo,
2091 pipeline->layout, &key);
2092
2093 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_GEOMETRY);
2094 }
2095
2096 if (modules[MESA_SHADER_TESS_EVAL]) {
2097 assert(modules[MESA_SHADER_TESS_CTRL]);
2098
2099 radv_tess_pipeline_compile(pipeline,
2100 cache,
2101 modules[MESA_SHADER_TESS_CTRL],
2102 modules[MESA_SHADER_TESS_EVAL],
2103 pStages[MESA_SHADER_TESS_CTRL]->pName,
2104 pStages[MESA_SHADER_TESS_EVAL]->pName,
2105 pStages[MESA_SHADER_TESS_CTRL]->pSpecializationInfo,
2106 pStages[MESA_SHADER_TESS_EVAL]->pSpecializationInfo,
2107 pipeline->layout,
2108 pCreateInfo->pTessellationState->patchControlPoints);
2109 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_TESS_EVAL) |
2110 mesa_to_vk_shader_stage(MESA_SHADER_TESS_CTRL);
2111 }
2112
2113 radv_pipeline_init_depth_stencil_state(pipeline, pCreateInfo, extra);
2114 radv_pipeline_init_raster_state(pipeline, pCreateInfo);
2115 radv_pipeline_init_multisample_state(pipeline, pCreateInfo);
2116 pipeline->graphics.prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
2117 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
2118
2119 if (radv_pipeline_has_gs(pipeline)) {
2120 pipeline->graphics.gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
2121 pipeline->graphics.can_use_guardband = pipeline->graphics.gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
2122 } else {
2123 pipeline->graphics.gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
2124 }
2125 if (extra && extra->use_rectlist) {
2126 pipeline->graphics.prim = V_008958_DI_PT_RECTLIST;
2127 pipeline->graphics.gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
2128 pipeline->graphics.can_use_guardband = true;
2129 }
2130 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
2131 /* prim vertex count will need TESS changes */
2132 pipeline->graphics.prim_vertex_count = prim_size_table[pipeline->graphics.prim];
2133
2134 /* Ensure that some export memory is always allocated, for two reasons:
2135 *
2136 * 1) Correctness: The hardware ignores the EXEC mask if no export
2137 * memory is allocated, so KILL and alpha test do not work correctly
2138 * without this.
2139 * 2) Performance: Every shader needs at least a NULL export, even when
2140 * it writes no color/depth output. The NULL export instruction
2141 * stalls without this setting.
2142 *
2143 * Don't add this to CB_SHADER_MASK.
2144 */
2145 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
2146 if (!pipeline->graphics.blend.spi_shader_col_format) {
2147 if (!ps->info.fs.writes_z &&
2148 !ps->info.fs.writes_stencil &&
2149 !ps->info.fs.writes_sample_mask)
2150 pipeline->graphics.blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
2151 }
2152
2153 unsigned z_order;
2154 pipeline->graphics.db_shader_control = 0;
2155 if (ps->info.fs.early_fragment_test || !ps->info.fs.writes_memory)
2156 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
2157 else
2158 z_order = V_02880C_LATE_Z;
2159
2160 pipeline->graphics.db_shader_control =
2161 S_02880C_Z_EXPORT_ENABLE(ps->info.fs.writes_z) |
2162 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.fs.writes_stencil) |
2163 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
2164 S_02880C_MASK_EXPORT_ENABLE(ps->info.fs.writes_sample_mask) |
2165 S_02880C_Z_ORDER(z_order) |
2166 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
2167 S_02880C_EXEC_ON_HIER_FAIL(ps->info.fs.writes_memory) |
2168 S_02880C_EXEC_ON_NOOP(ps->info.fs.writes_memory);
2169
2170 pipeline->graphics.shader_z_format =
2171 ps->info.fs.writes_sample_mask ? V_028710_SPI_SHADER_32_ABGR :
2172 ps->info.fs.writes_stencil ? V_028710_SPI_SHADER_32_GR :
2173 ps->info.fs.writes_z ? V_028710_SPI_SHADER_32_R :
2174 V_028710_SPI_SHADER_ZERO;
2175
2176 calculate_vgt_gs_mode(pipeline);
2177 calculate_pa_cl_vs_out_cntl(pipeline);
2178 calculate_ps_inputs(pipeline);
2179
2180 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
2181 if (pipeline->shaders[i]) {
2182 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
2183 }
2184 }
2185
2186 uint32_t stages = 0;
2187 if (radv_pipeline_has_tess(pipeline)) {
2188 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2189 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
2190
2191 if (radv_pipeline_has_gs(pipeline))
2192 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
2193 S_028B54_GS_EN(1) |
2194 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2195 else
2196 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2197
2198 } else if (radv_pipeline_has_gs(pipeline))
2199 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
2200 S_028B54_GS_EN(1) |
2201 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2202
2203 if (device->physical_device->rad_info.chip_class >= GFX9)
2204 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
2205
2206 pipeline->graphics.vgt_shader_stages_en = stages;
2207
2208 if (radv_pipeline_has_gs(pipeline))
2209 calculate_gs_ring_sizes(pipeline);
2210
2211 if (radv_pipeline_has_tess(pipeline)) {
2212 if (pipeline->graphics.prim == V_008958_DI_PT_PATCH) {
2213 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
2214 pipeline->graphics.prim_vertex_count.incr = 1;
2215 }
2216 calculate_tess_state(pipeline, pCreateInfo);
2217 }
2218
2219 const VkPipelineVertexInputStateCreateInfo *vi_info =
2220 pCreateInfo->pVertexInputState;
2221 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
2222 const VkVertexInputAttributeDescription *desc =
2223 &vi_info->pVertexAttributeDescriptions[i];
2224 unsigned loc = desc->location;
2225 const struct vk_format_description *format_desc;
2226 int first_non_void;
2227 uint32_t num_format, data_format;
2228 format_desc = vk_format_description(desc->format);
2229 first_non_void = vk_format_get_first_non_void_channel(desc->format);
2230
2231 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
2232 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
2233
2234 pipeline->va_rsrc_word3[loc] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc->swizzle[0])) |
2235 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc->swizzle[1])) |
2236 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc->swizzle[2])) |
2237 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc->swizzle[3])) |
2238 S_008F0C_NUM_FORMAT(num_format) |
2239 S_008F0C_DATA_FORMAT(data_format);
2240 pipeline->va_format_size[loc] = format_desc->block.bits / 8;
2241 pipeline->va_offset[loc] = desc->offset;
2242 pipeline->va_binding[loc] = desc->binding;
2243 pipeline->num_vertex_attribs = MAX2(pipeline->num_vertex_attribs, loc + 1);
2244 }
2245
2246 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
2247 const VkVertexInputBindingDescription *desc =
2248 &vi_info->pVertexBindingDescriptions[i];
2249
2250 pipeline->binding_stride[desc->binding] = desc->stride;
2251 }
2252
2253 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
2254 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2255 if (loc->sgpr_idx != -1) {
2256 pipeline->graphics.vtx_base_sgpr = radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
2257 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
2258 if (pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id)
2259 pipeline->graphics.vtx_emit_num = 3;
2260 else
2261 pipeline->graphics.vtx_emit_num = 2;
2262 }
2263 if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
2264 radv_dump_pipeline_stats(device, pipeline);
2265 }
2266
2267 result = radv_pipeline_scratch_init(device, pipeline);
2268 return result;
2269 }
2270
2271 VkResult
2272 radv_graphics_pipeline_create(
2273 VkDevice _device,
2274 VkPipelineCache _cache,
2275 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2276 const struct radv_graphics_pipeline_create_info *extra,
2277 const VkAllocationCallbacks *pAllocator,
2278 VkPipeline *pPipeline)
2279 {
2280 RADV_FROM_HANDLE(radv_device, device, _device);
2281 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
2282 struct radv_pipeline *pipeline;
2283 VkResult result;
2284
2285 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
2286 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2287 if (pipeline == NULL)
2288 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2289
2290 memset(pipeline, 0, sizeof(*pipeline));
2291 result = radv_pipeline_init(pipeline, device, cache,
2292 pCreateInfo, extra, pAllocator);
2293 if (result != VK_SUCCESS) {
2294 radv_pipeline_destroy(device, pipeline, pAllocator);
2295 return result;
2296 }
2297
2298 *pPipeline = radv_pipeline_to_handle(pipeline);
2299
2300 return VK_SUCCESS;
2301 }
2302
2303 VkResult radv_CreateGraphicsPipelines(
2304 VkDevice _device,
2305 VkPipelineCache pipelineCache,
2306 uint32_t count,
2307 const VkGraphicsPipelineCreateInfo* pCreateInfos,
2308 const VkAllocationCallbacks* pAllocator,
2309 VkPipeline* pPipelines)
2310 {
2311 VkResult result = VK_SUCCESS;
2312 unsigned i = 0;
2313
2314 for (; i < count; i++) {
2315 VkResult r;
2316 r = radv_graphics_pipeline_create(_device,
2317 pipelineCache,
2318 &pCreateInfos[i],
2319 NULL, pAllocator, &pPipelines[i]);
2320 if (r != VK_SUCCESS) {
2321 result = r;
2322 pPipelines[i] = VK_NULL_HANDLE;
2323 }
2324 }
2325
2326 return result;
2327 }
2328
2329 static VkResult radv_compute_pipeline_create(
2330 VkDevice _device,
2331 VkPipelineCache _cache,
2332 const VkComputePipelineCreateInfo* pCreateInfo,
2333 const VkAllocationCallbacks* pAllocator,
2334 VkPipeline* pPipeline)
2335 {
2336 RADV_FROM_HANDLE(radv_device, device, _device);
2337 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
2338 RADV_FROM_HANDLE(radv_shader_module, module, pCreateInfo->stage.module);
2339 struct radv_pipeline *pipeline;
2340 VkResult result;
2341
2342 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
2343 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2344 if (pipeline == NULL)
2345 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2346
2347 memset(pipeline, 0, sizeof(*pipeline));
2348 pipeline->device = device;
2349 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
2350
2351 pipeline->shaders[MESA_SHADER_COMPUTE] =
2352 radv_pipeline_compile(pipeline, cache, module,
2353 pCreateInfo->stage.pName,
2354 MESA_SHADER_COMPUTE,
2355 pCreateInfo->stage.pSpecializationInfo,
2356 pipeline->layout, NULL);
2357
2358
2359 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
2360 result = radv_pipeline_scratch_init(device, pipeline);
2361 if (result != VK_SUCCESS) {
2362 radv_pipeline_destroy(device, pipeline, pAllocator);
2363 return result;
2364 }
2365
2366 *pPipeline = radv_pipeline_to_handle(pipeline);
2367
2368 if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
2369 radv_dump_pipeline_stats(device, pipeline);
2370 }
2371 return VK_SUCCESS;
2372 }
2373 VkResult radv_CreateComputePipelines(
2374 VkDevice _device,
2375 VkPipelineCache pipelineCache,
2376 uint32_t count,
2377 const VkComputePipelineCreateInfo* pCreateInfos,
2378 const VkAllocationCallbacks* pAllocator,
2379 VkPipeline* pPipelines)
2380 {
2381 VkResult result = VK_SUCCESS;
2382
2383 unsigned i = 0;
2384 for (; i < count; i++) {
2385 VkResult r;
2386 r = radv_compute_pipeline_create(_device, pipelineCache,
2387 &pCreateInfos[i],
2388 pAllocator, &pPipelines[i]);
2389 if (r != VK_SUCCESS) {
2390 result = r;
2391 pPipelines[i] = VK_NULL_HANDLE;
2392 }
2393 }
2394
2395 return result;
2396 }