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radv: put more fields in radv_blend_state
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_cs.h"
33 #include "radv_shader.h"
34 #include "nir/nir.h"
35 #include "nir/nir_builder.h"
36 #include "spirv/nir_spirv.h"
37 #include "vk_util.h"
38
39 #include <llvm-c/Core.h>
40 #include <llvm-c/TargetMachine.h>
41
42 #include "sid.h"
43 #include "gfx9d.h"
44 #include "ac_binary.h"
45 #include "ac_llvm_util.h"
46 #include "ac_nir_to_llvm.h"
47 #include "vk_format.h"
48 #include "util/debug.h"
49 #include "ac_exp_param.h"
50 #include "ac_shader_util.h"
51
52 struct radv_blend_state {
53 uint32_t blend_enable;
54 uint32_t need_src_alpha;
55
56 uint32_t cb_color_control;
57 uint32_t cb_target_mask;
58 uint32_t sx_mrt_blend_opt[8];
59 uint32_t cb_blend_control[8];
60
61 uint32_t spi_shader_col_format;
62 uint32_t cb_shader_mask;
63 uint32_t db_alpha_to_mask;
64
65 bool single_cb_enable;
66 bool mrt0_is_dual_src;
67 };
68
69 struct radv_tessellation_state {
70 uint32_t ls_hs_config;
71 unsigned num_patches;
72 unsigned lds_size;
73 uint32_t tf_param;
74 };
75
76 struct radv_gs_state {
77 uint32_t vgt_gs_onchip_cntl;
78 uint32_t vgt_gs_max_prims_per_subgroup;
79 uint32_t vgt_esgs_ring_itemsize;
80 uint32_t lds_size;
81 };
82
83 static void
84 radv_pipeline_destroy(struct radv_device *device,
85 struct radv_pipeline *pipeline,
86 const VkAllocationCallbacks* allocator)
87 {
88 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
89 if (pipeline->shaders[i])
90 radv_shader_variant_destroy(device, pipeline->shaders[i]);
91
92 if (pipeline->gs_copy_shader)
93 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
94
95 if(pipeline->cs.buf)
96 free(pipeline->cs.buf);
97 vk_free2(&device->alloc, allocator, pipeline);
98 }
99
100 void radv_DestroyPipeline(
101 VkDevice _device,
102 VkPipeline _pipeline,
103 const VkAllocationCallbacks* pAllocator)
104 {
105 RADV_FROM_HANDLE(radv_device, device, _device);
106 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
107
108 if (!_pipeline)
109 return;
110
111 radv_pipeline_destroy(device, pipeline, pAllocator);
112 }
113
114 static uint32_t get_hash_flags(struct radv_device *device)
115 {
116 uint32_t hash_flags = 0;
117
118 if (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH)
119 hash_flags |= RADV_HASH_SHADER_UNSAFE_MATH;
120 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
121 hash_flags |= RADV_HASH_SHADER_SISCHED;
122 return hash_flags;
123 }
124
125 static VkResult
126 radv_pipeline_scratch_init(struct radv_device *device,
127 struct radv_pipeline *pipeline)
128 {
129 unsigned scratch_bytes_per_wave = 0;
130 unsigned max_waves = 0;
131 unsigned min_waves = 1;
132
133 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
134 if (pipeline->shaders[i]) {
135 unsigned max_stage_waves = device->scratch_waves;
136
137 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
138 pipeline->shaders[i]->config.scratch_bytes_per_wave);
139
140 max_stage_waves = MIN2(max_stage_waves,
141 4 * device->physical_device->rad_info.num_good_compute_units *
142 (256 / pipeline->shaders[i]->config.num_vgprs));
143 max_waves = MAX2(max_waves, max_stage_waves);
144 }
145 }
146
147 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
148 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
149 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
150 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
151 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
152 }
153
154 if (scratch_bytes_per_wave)
155 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
156
157 if (scratch_bytes_per_wave && max_waves < min_waves) {
158 /* Not really true at this moment, but will be true on first
159 * execution. Avoid having hanging shaders. */
160 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
161 }
162 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
163 pipeline->max_waves = max_waves;
164 return VK_SUCCESS;
165 }
166
167 static uint32_t si_translate_blend_function(VkBlendOp op)
168 {
169 switch (op) {
170 case VK_BLEND_OP_ADD:
171 return V_028780_COMB_DST_PLUS_SRC;
172 case VK_BLEND_OP_SUBTRACT:
173 return V_028780_COMB_SRC_MINUS_DST;
174 case VK_BLEND_OP_REVERSE_SUBTRACT:
175 return V_028780_COMB_DST_MINUS_SRC;
176 case VK_BLEND_OP_MIN:
177 return V_028780_COMB_MIN_DST_SRC;
178 case VK_BLEND_OP_MAX:
179 return V_028780_COMB_MAX_DST_SRC;
180 default:
181 return 0;
182 }
183 }
184
185 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
186 {
187 switch (factor) {
188 case VK_BLEND_FACTOR_ZERO:
189 return V_028780_BLEND_ZERO;
190 case VK_BLEND_FACTOR_ONE:
191 return V_028780_BLEND_ONE;
192 case VK_BLEND_FACTOR_SRC_COLOR:
193 return V_028780_BLEND_SRC_COLOR;
194 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
195 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
196 case VK_BLEND_FACTOR_DST_COLOR:
197 return V_028780_BLEND_DST_COLOR;
198 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
199 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
200 case VK_BLEND_FACTOR_SRC_ALPHA:
201 return V_028780_BLEND_SRC_ALPHA;
202 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
203 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
204 case VK_BLEND_FACTOR_DST_ALPHA:
205 return V_028780_BLEND_DST_ALPHA;
206 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
207 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
208 case VK_BLEND_FACTOR_CONSTANT_COLOR:
209 return V_028780_BLEND_CONSTANT_COLOR;
210 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
211 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
212 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
213 return V_028780_BLEND_CONSTANT_ALPHA;
214 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
215 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
216 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
217 return V_028780_BLEND_SRC_ALPHA_SATURATE;
218 case VK_BLEND_FACTOR_SRC1_COLOR:
219 return V_028780_BLEND_SRC1_COLOR;
220 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
221 return V_028780_BLEND_INV_SRC1_COLOR;
222 case VK_BLEND_FACTOR_SRC1_ALPHA:
223 return V_028780_BLEND_SRC1_ALPHA;
224 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
225 return V_028780_BLEND_INV_SRC1_ALPHA;
226 default:
227 return 0;
228 }
229 }
230
231 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
232 {
233 switch (op) {
234 case VK_BLEND_OP_ADD:
235 return V_028760_OPT_COMB_ADD;
236 case VK_BLEND_OP_SUBTRACT:
237 return V_028760_OPT_COMB_SUBTRACT;
238 case VK_BLEND_OP_REVERSE_SUBTRACT:
239 return V_028760_OPT_COMB_REVSUBTRACT;
240 case VK_BLEND_OP_MIN:
241 return V_028760_OPT_COMB_MIN;
242 case VK_BLEND_OP_MAX:
243 return V_028760_OPT_COMB_MAX;
244 default:
245 return V_028760_OPT_COMB_BLEND_DISABLED;
246 }
247 }
248
249 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
250 {
251 switch (factor) {
252 case VK_BLEND_FACTOR_ZERO:
253 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
254 case VK_BLEND_FACTOR_ONE:
255 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
256 case VK_BLEND_FACTOR_SRC_COLOR:
257 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
258 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
259 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
260 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
261 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
262 case VK_BLEND_FACTOR_SRC_ALPHA:
263 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
264 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
265 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
266 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
267 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
268 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
269 default:
270 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
271 }
272 }
273
274 /**
275 * Get rid of DST in the blend factors by commuting the operands:
276 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
277 */
278 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
279 unsigned *dst_factor, unsigned expected_dst,
280 unsigned replacement_src)
281 {
282 if (*src_factor == expected_dst &&
283 *dst_factor == VK_BLEND_FACTOR_ZERO) {
284 *src_factor = VK_BLEND_FACTOR_ZERO;
285 *dst_factor = replacement_src;
286
287 /* Commuting the operands requires reversing subtractions. */
288 if (*func == VK_BLEND_OP_SUBTRACT)
289 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
290 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
291 *func = VK_BLEND_OP_SUBTRACT;
292 }
293 }
294
295 static bool si_blend_factor_uses_dst(unsigned factor)
296 {
297 return factor == VK_BLEND_FACTOR_DST_COLOR ||
298 factor == VK_BLEND_FACTOR_DST_ALPHA ||
299 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
300 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
301 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
302 }
303
304 static bool is_dual_src(VkBlendFactor factor)
305 {
306 switch (factor) {
307 case VK_BLEND_FACTOR_SRC1_COLOR:
308 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
309 case VK_BLEND_FACTOR_SRC1_ALPHA:
310 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
311 return true;
312 default:
313 return false;
314 }
315 }
316
317 static unsigned si_choose_spi_color_format(VkFormat vk_format,
318 bool blend_enable,
319 bool blend_need_alpha)
320 {
321 const struct vk_format_description *desc = vk_format_description(vk_format);
322 unsigned format, ntype, swap;
323
324 /* Alpha is needed for alpha-to-coverage.
325 * Blending may be with or without alpha.
326 */
327 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
328 unsigned alpha = 0; /* exports alpha, but may not support blending */
329 unsigned blend = 0; /* supports blending, but may not export alpha */
330 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
331
332 format = radv_translate_colorformat(vk_format);
333 ntype = radv_translate_color_numformat(vk_format, desc,
334 vk_format_get_first_non_void_channel(vk_format));
335 swap = radv_translate_colorswap(vk_format, false);
336
337 /* Choose the SPI color formats. These are required values for Stoney/RB+.
338 * Other chips have multiple choices, though they are not necessarily better.
339 */
340 switch (format) {
341 case V_028C70_COLOR_5_6_5:
342 case V_028C70_COLOR_1_5_5_5:
343 case V_028C70_COLOR_5_5_5_1:
344 case V_028C70_COLOR_4_4_4_4:
345 case V_028C70_COLOR_10_11_11:
346 case V_028C70_COLOR_11_11_10:
347 case V_028C70_COLOR_8:
348 case V_028C70_COLOR_8_8:
349 case V_028C70_COLOR_8_8_8_8:
350 case V_028C70_COLOR_10_10_10_2:
351 case V_028C70_COLOR_2_10_10_10:
352 if (ntype == V_028C70_NUMBER_UINT)
353 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
354 else if (ntype == V_028C70_NUMBER_SINT)
355 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
356 else
357 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
358 break;
359
360 case V_028C70_COLOR_16:
361 case V_028C70_COLOR_16_16:
362 case V_028C70_COLOR_16_16_16_16:
363 if (ntype == V_028C70_NUMBER_UNORM ||
364 ntype == V_028C70_NUMBER_SNORM) {
365 /* UNORM16 and SNORM16 don't support blending */
366 if (ntype == V_028C70_NUMBER_UNORM)
367 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
368 else
369 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
370
371 /* Use 32 bits per channel for blending. */
372 if (format == V_028C70_COLOR_16) {
373 if (swap == V_028C70_SWAP_STD) { /* R */
374 blend = V_028714_SPI_SHADER_32_R;
375 blend_alpha = V_028714_SPI_SHADER_32_AR;
376 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
377 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
378 else
379 assert(0);
380 } else if (format == V_028C70_COLOR_16_16) {
381 if (swap == V_028C70_SWAP_STD) { /* RG */
382 blend = V_028714_SPI_SHADER_32_GR;
383 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
384 } else if (swap == V_028C70_SWAP_ALT) /* RA */
385 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
386 else
387 assert(0);
388 } else /* 16_16_16_16 */
389 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
390 } else if (ntype == V_028C70_NUMBER_UINT)
391 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
392 else if (ntype == V_028C70_NUMBER_SINT)
393 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
394 else if (ntype == V_028C70_NUMBER_FLOAT)
395 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
396 else
397 assert(0);
398 break;
399
400 case V_028C70_COLOR_32:
401 if (swap == V_028C70_SWAP_STD) { /* R */
402 blend = normal = V_028714_SPI_SHADER_32_R;
403 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
404 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
405 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
406 else
407 assert(0);
408 break;
409
410 case V_028C70_COLOR_32_32:
411 if (swap == V_028C70_SWAP_STD) { /* RG */
412 blend = normal = V_028714_SPI_SHADER_32_GR;
413 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
414 } else if (swap == V_028C70_SWAP_ALT) /* RA */
415 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
416 else
417 assert(0);
418 break;
419
420 case V_028C70_COLOR_32_32_32_32:
421 case V_028C70_COLOR_8_24:
422 case V_028C70_COLOR_24_8:
423 case V_028C70_COLOR_X24_8_32_FLOAT:
424 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
425 break;
426
427 default:
428 unreachable("unhandled blend format");
429 }
430
431 if (blend_enable && blend_need_alpha)
432 return blend_alpha;
433 else if(blend_need_alpha)
434 return alpha;
435 else if(blend_enable)
436 return blend;
437 else
438 return normal;
439 }
440
441 static void
442 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
443 const VkGraphicsPipelineCreateInfo *pCreateInfo,
444 struct radv_blend_state *blend)
445 {
446 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
447 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
448 unsigned col_format = 0;
449
450 for (unsigned i = 0; i < (blend->single_cb_enable ? 1 : subpass->color_count); ++i) {
451 unsigned cf;
452
453 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
454 cf = V_028714_SPI_SHADER_ZERO;
455 } else {
456 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
457
458 cf = si_choose_spi_color_format(attachment->format,
459 blend->blend_enable & (1 << i),
460 blend->need_src_alpha & (1 << i));
461 }
462
463 col_format |= cf << (4 * i);
464 }
465
466 blend->cb_shader_mask = ac_get_cb_shader_mask(col_format);
467
468 if (blend->mrt0_is_dual_src)
469 col_format |= (col_format & 0xf) << 4;
470 blend->spi_shader_col_format = col_format;
471 }
472
473 static bool
474 format_is_int8(VkFormat format)
475 {
476 const struct vk_format_description *desc = vk_format_description(format);
477 int channel = vk_format_get_first_non_void_channel(format);
478
479 return channel >= 0 && desc->channel[channel].pure_integer &&
480 desc->channel[channel].size == 8;
481 }
482
483 static bool
484 format_is_int10(VkFormat format)
485 {
486 const struct vk_format_description *desc = vk_format_description(format);
487
488 if (desc->nr_channels != 4)
489 return false;
490 for (unsigned i = 0; i < 4; i++) {
491 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
492 return true;
493 }
494 return false;
495 }
496
497 unsigned radv_format_meta_fs_key(VkFormat format)
498 {
499 unsigned col_format = si_choose_spi_color_format(format, false, false) - 1;
500 bool is_int8 = format_is_int8(format);
501 bool is_int10 = format_is_int10(format);
502
503 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
504 }
505
506 static void
507 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo *pCreateInfo,
508 unsigned *is_int8, unsigned *is_int10)
509 {
510 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
511 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
512 *is_int8 = 0;
513 *is_int10 = 0;
514
515 for (unsigned i = 0; i < subpass->color_count; ++i) {
516 struct radv_render_pass_attachment *attachment;
517
518 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
519 continue;
520
521 attachment = pass->attachments + subpass->color_attachments[i].attachment;
522
523 if (format_is_int8(attachment->format))
524 *is_int8 |= 1 << i;
525 if (format_is_int10(attachment->format))
526 *is_int10 |= 1 << i;
527 }
528 }
529
530 static struct radv_blend_state
531 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
532 const VkGraphicsPipelineCreateInfo *pCreateInfo,
533 const struct radv_graphics_pipeline_create_info *extra)
534 {
535 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
536 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
537 struct radv_blend_state blend = {0};
538 unsigned mode = V_028808_CB_NORMAL;
539 int i;
540
541 if (!vkblend)
542 return blend;
543
544 if (extra && extra->custom_blend_mode) {
545 blend.single_cb_enable = true;
546 mode = extra->custom_blend_mode;
547 }
548 blend.cb_color_control = 0;
549 if (vkblend->logicOpEnable)
550 blend.cb_color_control |= S_028808_ROP3(vkblend->logicOp | (vkblend->logicOp << 4));
551 else
552 blend.cb_color_control |= S_028808_ROP3(0xcc);
553
554 blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
555 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
556 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
557 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
558
559 if (vkms && vkms->alphaToCoverageEnable) {
560 blend.db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
561 }
562
563 blend.cb_target_mask = 0;
564 for (i = 0; i < vkblend->attachmentCount; i++) {
565 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
566 unsigned blend_cntl = 0;
567 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
568 VkBlendOp eqRGB = att->colorBlendOp;
569 VkBlendFactor srcRGB = att->srcColorBlendFactor;
570 VkBlendFactor dstRGB = att->dstColorBlendFactor;
571 VkBlendOp eqA = att->alphaBlendOp;
572 VkBlendFactor srcA = att->srcAlphaBlendFactor;
573 VkBlendFactor dstA = att->dstAlphaBlendFactor;
574
575 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
576
577 if (!att->colorWriteMask)
578 continue;
579
580 blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
581 if (!att->blendEnable) {
582 blend.cb_blend_control[i] = blend_cntl;
583 continue;
584 }
585
586 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
587 if (i == 0)
588 blend.mrt0_is_dual_src = true;
589
590 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
591 srcRGB = VK_BLEND_FACTOR_ONE;
592 dstRGB = VK_BLEND_FACTOR_ONE;
593 }
594 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
595 srcA = VK_BLEND_FACTOR_ONE;
596 dstA = VK_BLEND_FACTOR_ONE;
597 }
598
599 /* Blending optimizations for RB+.
600 * These transformations don't change the behavior.
601 *
602 * First, get rid of DST in the blend factors:
603 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
604 */
605 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
606 VK_BLEND_FACTOR_DST_COLOR,
607 VK_BLEND_FACTOR_SRC_COLOR);
608
609 si_blend_remove_dst(&eqA, &srcA, &dstA,
610 VK_BLEND_FACTOR_DST_COLOR,
611 VK_BLEND_FACTOR_SRC_COLOR);
612
613 si_blend_remove_dst(&eqA, &srcA, &dstA,
614 VK_BLEND_FACTOR_DST_ALPHA,
615 VK_BLEND_FACTOR_SRC_ALPHA);
616
617 /* Look up the ideal settings from tables. */
618 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
619 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
620 srcA_opt = si_translate_blend_opt_factor(srcA, true);
621 dstA_opt = si_translate_blend_opt_factor(dstA, true);
622
623 /* Handle interdependencies. */
624 if (si_blend_factor_uses_dst(srcRGB))
625 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
626 if (si_blend_factor_uses_dst(srcA))
627 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
628
629 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
630 (dstRGB == VK_BLEND_FACTOR_ZERO ||
631 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
632 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
633 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
634
635 /* Set the final value. */
636 blend.sx_mrt_blend_opt[i] =
637 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
638 S_028760_COLOR_DST_OPT(dstRGB_opt) |
639 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
640 S_028760_ALPHA_SRC_OPT(srcA_opt) |
641 S_028760_ALPHA_DST_OPT(dstA_opt) |
642 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
643 blend_cntl |= S_028780_ENABLE(1);
644
645 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
646 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
647 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
648 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
649 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
650 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
651 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
652 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
653 }
654 blend.cb_blend_control[i] = blend_cntl;
655
656 blend.blend_enable |= 1 << i;
657
658 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
659 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
660 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
661 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
662 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
663 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
664 blend.need_src_alpha |= 1 << i;
665 }
666 for (i = vkblend->attachmentCount; i < 8; i++) {
667 blend.cb_blend_control[i] = 0;
668 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
669 }
670
671 if (pipeline->device->physical_device->has_rbplus) {
672 /* Disable RB+ blend optimizations for dual source blending. */
673 if (blend.mrt0_is_dual_src) {
674 for (i = 0; i < 8; i++) {
675 blend.sx_mrt_blend_opt[i] =
676 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
677 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
678 }
679 }
680
681 /* RB+ doesn't work with dual source blending, logic op and
682 * RESOLVE.
683 */
684 if (blend.mrt0_is_dual_src || vkblend->logicOpEnable ||
685 mode == V_028808_CB_RESOLVE)
686 blend.cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
687 }
688
689 if (blend.cb_target_mask)
690 blend.cb_color_control |= S_028808_MODE(mode);
691 else
692 blend.cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
693
694 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo, &blend);
695 return blend;
696 }
697
698 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
699 {
700 switch (op) {
701 case VK_STENCIL_OP_KEEP:
702 return V_02842C_STENCIL_KEEP;
703 case VK_STENCIL_OP_ZERO:
704 return V_02842C_STENCIL_ZERO;
705 case VK_STENCIL_OP_REPLACE:
706 return V_02842C_STENCIL_REPLACE_TEST;
707 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
708 return V_02842C_STENCIL_ADD_CLAMP;
709 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
710 return V_02842C_STENCIL_SUB_CLAMP;
711 case VK_STENCIL_OP_INVERT:
712 return V_02842C_STENCIL_INVERT;
713 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
714 return V_02842C_STENCIL_ADD_WRAP;
715 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
716 return V_02842C_STENCIL_SUB_WRAP;
717 default:
718 return 0;
719 }
720 }
721
722 static uint32_t si_translate_fill(VkPolygonMode func)
723 {
724 switch(func) {
725 case VK_POLYGON_MODE_FILL:
726 return V_028814_X_DRAW_TRIANGLES;
727 case VK_POLYGON_MODE_LINE:
728 return V_028814_X_DRAW_LINES;
729 case VK_POLYGON_MODE_POINT:
730 return V_028814_X_DRAW_POINTS;
731 default:
732 assert(0);
733 return V_028814_X_DRAW_POINTS;
734 }
735 }
736
737 static uint8_t radv_pipeline_get_ps_iter_samples(const VkPipelineMultisampleStateCreateInfo *vkms)
738 {
739 uint32_t num_samples = vkms->rasterizationSamples;
740 uint32_t ps_iter_samples = 1;
741
742 if (vkms->sampleShadingEnable) {
743 ps_iter_samples = ceil(vkms->minSampleShading * num_samples);
744 ps_iter_samples = util_next_power_of_two(ps_iter_samples);
745 }
746 return ps_iter_samples;
747 }
748
749 static void
750 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
751 const VkGraphicsPipelineCreateInfo *pCreateInfo)
752 {
753 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
754 struct radv_multisample_state *ms = &pipeline->graphics.ms;
755 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
756 int ps_iter_samples = 1;
757 uint32_t mask = 0xffff;
758
759 if (vkms)
760 ms->num_samples = vkms->rasterizationSamples;
761 else
762 ms->num_samples = 1;
763
764 if (vkms)
765 ps_iter_samples = radv_pipeline_get_ps_iter_samples(vkms);
766 if (vkms && !vkms->sampleShadingEnable && pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.force_persample) {
767 ps_iter_samples = ms->num_samples;
768 }
769
770 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
771 ms->pa_sc_aa_config = 0;
772 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
773 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
774 ms->pa_sc_mode_cntl_1 =
775 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
776 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
777 /* always 1: */
778 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
779 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
780 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
781 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
782 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
783 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
784 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9) |
785 S_028A48_VPORT_SCISSOR_ENABLE(1);
786
787 if (ms->num_samples > 1) {
788 unsigned log_samples = util_logbase2(ms->num_samples);
789 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
790 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
791 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
792 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
793 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
794 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
795 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
796 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
797 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
798 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
799 ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
800 if (ps_iter_samples > 1)
801 pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
802 }
803
804 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
805 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
806 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
807 ms->pa_sc_mode_cntl_1 |= S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(1) |
808 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7);
809 }
810
811 if (vkms && vkms->pSampleMask) {
812 mask = vkms->pSampleMask[0] & 0xffff;
813 }
814
815 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
816 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
817 }
818
819 static bool
820 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
821 {
822 switch (topology) {
823 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
824 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
825 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
826 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
827 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
828 return false;
829 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
830 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
831 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
832 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
833 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
834 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
835 return true;
836 default:
837 unreachable("unhandled primitive type");
838 }
839 }
840
841 static uint32_t
842 si_translate_prim(enum VkPrimitiveTopology topology)
843 {
844 switch (topology) {
845 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
846 return V_008958_DI_PT_POINTLIST;
847 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
848 return V_008958_DI_PT_LINELIST;
849 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
850 return V_008958_DI_PT_LINESTRIP;
851 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
852 return V_008958_DI_PT_TRILIST;
853 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
854 return V_008958_DI_PT_TRISTRIP;
855 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
856 return V_008958_DI_PT_TRIFAN;
857 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
858 return V_008958_DI_PT_LINELIST_ADJ;
859 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
860 return V_008958_DI_PT_LINESTRIP_ADJ;
861 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
862 return V_008958_DI_PT_TRILIST_ADJ;
863 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
864 return V_008958_DI_PT_TRISTRIP_ADJ;
865 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
866 return V_008958_DI_PT_PATCH;
867 default:
868 assert(0);
869 return 0;
870 }
871 }
872
873 static uint32_t
874 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
875 {
876 switch (gl_prim) {
877 case 0: /* GL_POINTS */
878 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
879 case 1: /* GL_LINES */
880 case 3: /* GL_LINE_STRIP */
881 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
882 case 0x8E7A: /* GL_ISOLINES */
883 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
884
885 case 4: /* GL_TRIANGLES */
886 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
887 case 5: /* GL_TRIANGLE_STRIP */
888 case 7: /* GL_QUADS */
889 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
890 default:
891 assert(0);
892 return 0;
893 }
894 }
895
896 static uint32_t
897 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
898 {
899 switch (topology) {
900 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
901 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
902 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
903 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
904 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
905 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
906 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
907 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
908 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
909 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
910 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
911 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
912 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
913 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
914 default:
915 assert(0);
916 return 0;
917 }
918 }
919
920 static unsigned si_map_swizzle(unsigned swizzle)
921 {
922 switch (swizzle) {
923 case VK_SWIZZLE_Y:
924 return V_008F0C_SQ_SEL_Y;
925 case VK_SWIZZLE_Z:
926 return V_008F0C_SQ_SEL_Z;
927 case VK_SWIZZLE_W:
928 return V_008F0C_SQ_SEL_W;
929 case VK_SWIZZLE_0:
930 return V_008F0C_SQ_SEL_0;
931 case VK_SWIZZLE_1:
932 return V_008F0C_SQ_SEL_1;
933 default: /* VK_SWIZZLE_X */
934 return V_008F0C_SQ_SEL_X;
935 }
936 }
937
938
939 static unsigned radv_dynamic_state_mask(VkDynamicState state)
940 {
941 switch(state) {
942 case VK_DYNAMIC_STATE_VIEWPORT:
943 return RADV_DYNAMIC_VIEWPORT;
944 case VK_DYNAMIC_STATE_SCISSOR:
945 return RADV_DYNAMIC_SCISSOR;
946 case VK_DYNAMIC_STATE_LINE_WIDTH:
947 return RADV_DYNAMIC_LINE_WIDTH;
948 case VK_DYNAMIC_STATE_DEPTH_BIAS:
949 return RADV_DYNAMIC_DEPTH_BIAS;
950 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
951 return RADV_DYNAMIC_BLEND_CONSTANTS;
952 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
953 return RADV_DYNAMIC_DEPTH_BOUNDS;
954 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
955 return RADV_DYNAMIC_STENCIL_COMPARE_MASK;
956 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
957 return RADV_DYNAMIC_STENCIL_WRITE_MASK;
958 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
959 return RADV_DYNAMIC_STENCIL_REFERENCE;
960 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT:
961 return RADV_DYNAMIC_DISCARD_RECTANGLE;
962 default:
963 unreachable("Unhandled dynamic state");
964 }
965 }
966
967 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
968 {
969 uint32_t states = RADV_DYNAMIC_ALL;
970
971 /* If rasterization is disabled we do not care about any of the dynamic states,
972 * since they are all rasterization related only. */
973 if (pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
974 return 0;
975
976 if (!pCreateInfo->pRasterizationState->depthBiasEnable)
977 states &= ~RADV_DYNAMIC_DEPTH_BIAS;
978
979 if (!pCreateInfo->pDepthStencilState ||
980 !pCreateInfo->pDepthStencilState->depthBoundsTestEnable)
981 states &= ~RADV_DYNAMIC_DEPTH_BOUNDS;
982
983 if (!pCreateInfo->pDepthStencilState ||
984 !pCreateInfo->pDepthStencilState->stencilTestEnable)
985 states &= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK |
986 RADV_DYNAMIC_STENCIL_WRITE_MASK |
987 RADV_DYNAMIC_STENCIL_REFERENCE);
988
989 if (!vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT))
990 states &= ~RADV_DYNAMIC_DISCARD_RECTANGLE;
991
992 /* TODO: blend constants & line width. */
993
994 return states;
995 }
996
997
998 static void
999 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1000 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1001 {
1002 uint32_t needed_states = radv_pipeline_needed_dynamic_state(pCreateInfo);
1003 uint32_t states = needed_states;
1004 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1005 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1006
1007 pipeline->dynamic_state = default_dynamic_state;
1008 pipeline->graphics.needed_dynamic_state = needed_states;
1009
1010 if (pCreateInfo->pDynamicState) {
1011 /* Remove all of the states that are marked as dynamic */
1012 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1013 for (uint32_t s = 0; s < count; s++)
1014 states &= ~radv_dynamic_state_mask(pCreateInfo->pDynamicState->pDynamicStates[s]);
1015 }
1016
1017 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1018
1019 if (needed_states & RADV_DYNAMIC_VIEWPORT) {
1020 assert(pCreateInfo->pViewportState);
1021
1022 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1023 if (states & RADV_DYNAMIC_VIEWPORT) {
1024 typed_memcpy(dynamic->viewport.viewports,
1025 pCreateInfo->pViewportState->pViewports,
1026 pCreateInfo->pViewportState->viewportCount);
1027 }
1028 }
1029
1030 if (needed_states & RADV_DYNAMIC_SCISSOR) {
1031 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1032 if (states & RADV_DYNAMIC_SCISSOR) {
1033 typed_memcpy(dynamic->scissor.scissors,
1034 pCreateInfo->pViewportState->pScissors,
1035 pCreateInfo->pViewportState->scissorCount);
1036 }
1037 }
1038
1039 if (states & RADV_DYNAMIC_LINE_WIDTH) {
1040 assert(pCreateInfo->pRasterizationState);
1041 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1042 }
1043
1044 if (states & RADV_DYNAMIC_DEPTH_BIAS) {
1045 assert(pCreateInfo->pRasterizationState);
1046 dynamic->depth_bias.bias =
1047 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1048 dynamic->depth_bias.clamp =
1049 pCreateInfo->pRasterizationState->depthBiasClamp;
1050 dynamic->depth_bias.slope =
1051 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1052 }
1053
1054 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1055 *
1056 * pColorBlendState is [...] NULL if the pipeline has rasterization
1057 * disabled or if the subpass of the render pass the pipeline is
1058 * created against does not use any color attachments.
1059 */
1060 bool uses_color_att = false;
1061 for (unsigned i = 0; i < subpass->color_count; ++i) {
1062 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1063 uses_color_att = true;
1064 break;
1065 }
1066 }
1067
1068 if (uses_color_att && states & RADV_DYNAMIC_BLEND_CONSTANTS) {
1069 assert(pCreateInfo->pColorBlendState);
1070 typed_memcpy(dynamic->blend_constants,
1071 pCreateInfo->pColorBlendState->blendConstants, 4);
1072 }
1073
1074 /* If there is no depthstencil attachment, then don't read
1075 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1076 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1077 * no need to override the depthstencil defaults in
1078 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1079 *
1080 * Section 9.2 of the Vulkan 1.0.15 spec says:
1081 *
1082 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1083 * disabled or if the subpass of the render pass the pipeline is created
1084 * against does not use a depth/stencil attachment.
1085 */
1086 if (needed_states &&
1087 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1088 assert(pCreateInfo->pDepthStencilState);
1089
1090 if (states & RADV_DYNAMIC_DEPTH_BOUNDS) {
1091 dynamic->depth_bounds.min =
1092 pCreateInfo->pDepthStencilState->minDepthBounds;
1093 dynamic->depth_bounds.max =
1094 pCreateInfo->pDepthStencilState->maxDepthBounds;
1095 }
1096
1097 if (states & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
1098 dynamic->stencil_compare_mask.front =
1099 pCreateInfo->pDepthStencilState->front.compareMask;
1100 dynamic->stencil_compare_mask.back =
1101 pCreateInfo->pDepthStencilState->back.compareMask;
1102 }
1103
1104 if (states & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
1105 dynamic->stencil_write_mask.front =
1106 pCreateInfo->pDepthStencilState->front.writeMask;
1107 dynamic->stencil_write_mask.back =
1108 pCreateInfo->pDepthStencilState->back.writeMask;
1109 }
1110
1111 if (states & RADV_DYNAMIC_STENCIL_REFERENCE) {
1112 dynamic->stencil_reference.front =
1113 pCreateInfo->pDepthStencilState->front.reference;
1114 dynamic->stencil_reference.back =
1115 pCreateInfo->pDepthStencilState->back.reference;
1116 }
1117 }
1118
1119 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
1120 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
1121 if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1122 dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount;
1123 typed_memcpy(dynamic->discard_rectangle.rectangles,
1124 discard_rectangle_info->pDiscardRectangles,
1125 discard_rectangle_info->discardRectangleCount);
1126 }
1127
1128 pipeline->dynamic_state.mask = states;
1129 }
1130
1131 static struct radv_gs_state
1132 calculate_gs_info(const VkGraphicsPipelineCreateInfo *pCreateInfo,
1133 const struct radv_pipeline *pipeline)
1134 {
1135 struct radv_gs_state gs = {0};
1136 struct radv_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1137 struct radv_es_output_info *es_info;
1138 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
1139 es_info = radv_pipeline_has_tess(pipeline) ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1140 else
1141 es_info = radv_pipeline_has_tess(pipeline) ?
1142 &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.es_info :
1143 &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info;
1144
1145 unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
1146 bool uses_adjacency;
1147 switch(pCreateInfo->pInputAssemblyState->topology) {
1148 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1149 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1150 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1151 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1152 uses_adjacency = true;
1153 break;
1154 default:
1155 uses_adjacency = false;
1156 break;
1157 }
1158
1159 /* All these are in dwords: */
1160 /* We can't allow using the whole LDS, because GS waves compete with
1161 * other shader stages for LDS space. */
1162 const unsigned max_lds_size = 8 * 1024;
1163 const unsigned esgs_itemsize = es_info->esgs_itemsize / 4;
1164 unsigned esgs_lds_size;
1165
1166 /* All these are per subgroup: */
1167 const unsigned max_out_prims = 32 * 1024;
1168 const unsigned max_es_verts = 255;
1169 const unsigned ideal_gs_prims = 64;
1170 unsigned max_gs_prims, gs_prims;
1171 unsigned min_es_verts, es_verts, worst_case_es_verts;
1172
1173 if (uses_adjacency || gs_num_invocations > 1)
1174 max_gs_prims = 127 / gs_num_invocations;
1175 else
1176 max_gs_prims = 255;
1177
1178 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1179 * Make sure we don't go over the maximum value.
1180 */
1181 if (gs_info->gs.vertices_out > 0) {
1182 max_gs_prims = MIN2(max_gs_prims,
1183 max_out_prims /
1184 (gs_info->gs.vertices_out * gs_num_invocations));
1185 }
1186 assert(max_gs_prims > 0);
1187
1188 /* If the primitive has adjacency, halve the number of vertices
1189 * that will be reused in multiple primitives.
1190 */
1191 min_es_verts = gs_info->gs.vertices_in / (uses_adjacency ? 2 : 1);
1192
1193 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
1194 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
1195
1196 /* Compute ESGS LDS size based on the worst case number of ES vertices
1197 * needed to create the target number of GS prims per subgroup.
1198 */
1199 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1200
1201 /* If total LDS usage is too big, refactor partitions based on ratio
1202 * of ESGS item sizes.
1203 */
1204 if (esgs_lds_size > max_lds_size) {
1205 /* Our target GS Prims Per Subgroup was too large. Calculate
1206 * the maximum number of GS Prims Per Subgroup that will fit
1207 * into LDS, capped by the maximum that the hardware can support.
1208 */
1209 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
1210 max_gs_prims);
1211 assert(gs_prims > 0);
1212 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
1213 max_es_verts);
1214
1215 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1216 assert(esgs_lds_size <= max_lds_size);
1217 }
1218
1219 /* Now calculate remaining ESGS information. */
1220 if (esgs_lds_size)
1221 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
1222 else
1223 es_verts = max_es_verts;
1224
1225 /* Vertices for adjacency primitives are not always reused, so restore
1226 * it for ES_VERTS_PER_SUBGRP.
1227 */
1228 min_es_verts = gs_info->gs.vertices_in;
1229
1230 /* For normal primitives, the VGT only checks if they are past the ES
1231 * verts per subgroup after allocating a full GS primitive and if they
1232 * are, kick off a new subgroup. But if those additional ES verts are
1233 * unique (e.g. not reused) we need to make sure there is enough LDS
1234 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1235 */
1236 es_verts -= min_es_verts - 1;
1237
1238 uint32_t es_verts_per_subgroup = es_verts;
1239 uint32_t gs_prims_per_subgroup = gs_prims;
1240 uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
1241 uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out;
1242 gs.lds_size = align(esgs_lds_size, 128) / 128;
1243 gs.vgt_gs_onchip_cntl = S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) |
1244 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) |
1245 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup);
1246 gs.vgt_gs_max_prims_per_subgroup = S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup);
1247 gs.vgt_esgs_ring_itemsize = esgs_itemsize;
1248 assert(max_prims_per_subgroup <= max_out_prims);
1249
1250 return gs;
1251 }
1252
1253 static void
1254 calculate_gs_ring_sizes(struct radv_pipeline *pipeline, const struct radv_gs_state *gs)
1255 {
1256 struct radv_device *device = pipeline->device;
1257 unsigned num_se = device->physical_device->rad_info.max_se;
1258 unsigned wave_size = 64;
1259 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1260 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1261 unsigned alignment = 256 * num_se;
1262 /* The maximum size is 63.999 MB per SE. */
1263 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1264 struct radv_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1265
1266 /* Calculate the minimum size. */
1267 unsigned min_esgs_ring_size = align(gs->vgt_esgs_ring_itemsize * 4 * gs_vertex_reuse *
1268 wave_size, alignment);
1269 /* These are recommended sizes, not minimum sizes. */
1270 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1271 gs->vgt_esgs_ring_itemsize * 4 * gs_info->gs.vertices_in;
1272 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1273 gs_info->gs.max_gsvs_emit_size * 1; // no streams in VK (gs->max_gs_stream + 1);
1274
1275 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1276 esgs_ring_size = align(esgs_ring_size, alignment);
1277 gsvs_ring_size = align(gsvs_ring_size, alignment);
1278
1279 if (pipeline->device->physical_device->rad_info.chip_class <= VI)
1280 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1281
1282 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1283 }
1284
1285 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1286 unsigned *lds_size)
1287 {
1288 /* If tessellation is all offchip and on-chip GS isn't used, this
1289 * workaround is not needed.
1290 */
1291 return;
1292
1293 /* SPI barrier management bug:
1294 * Make sure we have at least 4k of LDS in use to avoid the bug.
1295 * It applies to workgroup sizes of more than one wavefront.
1296 */
1297 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1298 device->physical_device->rad_info.family == CHIP_KABINI ||
1299 device->physical_device->rad_info.family == CHIP_MULLINS)
1300 *lds_size = MAX2(*lds_size, 8);
1301 }
1302
1303 struct radv_shader_variant *
1304 radv_get_vertex_shader(struct radv_pipeline *pipeline)
1305 {
1306 if (pipeline->shaders[MESA_SHADER_VERTEX])
1307 return pipeline->shaders[MESA_SHADER_VERTEX];
1308 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
1309 return pipeline->shaders[MESA_SHADER_TESS_CTRL];
1310 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1311 }
1312
1313 static struct radv_shader_variant *
1314 radv_get_tess_eval_shader(struct radv_pipeline *pipeline)
1315 {
1316 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
1317 return pipeline->shaders[MESA_SHADER_TESS_EVAL];
1318 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1319 }
1320
1321 static struct radv_tessellation_state
1322 calculate_tess_state(struct radv_pipeline *pipeline,
1323 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1324 {
1325 unsigned num_tcs_input_cp;
1326 unsigned num_tcs_output_cp;
1327 unsigned lds_size;
1328 unsigned num_patches;
1329 struct radv_tessellation_state tess = {0};
1330
1331 num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1332 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1333 num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
1334
1335 lds_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.lds_size;
1336
1337 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
1338 assert(lds_size <= 65536);
1339 lds_size = align(lds_size, 512) / 512;
1340 } else {
1341 assert(lds_size <= 32768);
1342 lds_size = align(lds_size, 256) / 256;
1343 }
1344 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1345
1346 tess.lds_size = lds_size;
1347
1348 tess.ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1349 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1350 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1351 tess.num_patches = num_patches;
1352
1353 struct radv_shader_variant *tes = radv_get_tess_eval_shader(pipeline);
1354 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1355
1356 switch (tes->info.tes.primitive_mode) {
1357 case GL_TRIANGLES:
1358 type = V_028B6C_TESS_TRIANGLE;
1359 break;
1360 case GL_QUADS:
1361 type = V_028B6C_TESS_QUAD;
1362 break;
1363 case GL_ISOLINES:
1364 type = V_028B6C_TESS_ISOLINE;
1365 break;
1366 }
1367
1368 switch (tes->info.tes.spacing) {
1369 case TESS_SPACING_EQUAL:
1370 partitioning = V_028B6C_PART_INTEGER;
1371 break;
1372 case TESS_SPACING_FRACTIONAL_ODD:
1373 partitioning = V_028B6C_PART_FRAC_ODD;
1374 break;
1375 case TESS_SPACING_FRACTIONAL_EVEN:
1376 partitioning = V_028B6C_PART_FRAC_EVEN;
1377 break;
1378 default:
1379 break;
1380 }
1381
1382 bool ccw = tes->info.tes.ccw;
1383 const VkPipelineTessellationDomainOriginStateCreateInfoKHR *domain_origin_state =
1384 vk_find_struct_const(pCreateInfo->pTessellationState,
1385 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO_KHR);
1386
1387 if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT_KHR)
1388 ccw = !ccw;
1389
1390 if (tes->info.tes.point_mode)
1391 topology = V_028B6C_OUTPUT_POINT;
1392 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
1393 topology = V_028B6C_OUTPUT_LINE;
1394 else if (ccw)
1395 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
1396 else
1397 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
1398
1399 if (pipeline->device->has_distributed_tess) {
1400 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
1401 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
1402 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
1403 else
1404 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
1405 } else
1406 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
1407
1408 tess.tf_param = S_028B6C_TYPE(type) |
1409 S_028B6C_PARTITIONING(partitioning) |
1410 S_028B6C_TOPOLOGY(topology) |
1411 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
1412
1413 return tess;
1414 }
1415
1416 static const struct radv_prim_vertex_count prim_size_table[] = {
1417 [V_008958_DI_PT_NONE] = {0, 0},
1418 [V_008958_DI_PT_POINTLIST] = {1, 1},
1419 [V_008958_DI_PT_LINELIST] = {2, 2},
1420 [V_008958_DI_PT_LINESTRIP] = {2, 1},
1421 [V_008958_DI_PT_TRILIST] = {3, 3},
1422 [V_008958_DI_PT_TRIFAN] = {3, 1},
1423 [V_008958_DI_PT_TRISTRIP] = {3, 1},
1424 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
1425 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
1426 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
1427 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
1428 [V_008958_DI_PT_RECTLIST] = {3, 3},
1429 [V_008958_DI_PT_LINELOOP] = {2, 1},
1430 [V_008958_DI_PT_POLYGON] = {3, 1},
1431 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
1432 };
1433
1434 static const struct radv_vs_output_info *get_vs_output_info(const struct radv_pipeline *pipeline)
1435 {
1436 if (radv_pipeline_has_gs(pipeline))
1437 return &pipeline->gs_copy_shader->info.vs.outinfo;
1438 else if (radv_pipeline_has_tess(pipeline))
1439 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
1440 else
1441 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
1442 }
1443
1444 static void
1445 radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
1446 {
1447 nir_shader* ordered_shaders[MESA_SHADER_STAGES];
1448 int shader_count = 0;
1449
1450 if(shaders[MESA_SHADER_FRAGMENT]) {
1451 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
1452 }
1453 if(shaders[MESA_SHADER_GEOMETRY]) {
1454 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
1455 }
1456 if(shaders[MESA_SHADER_TESS_EVAL]) {
1457 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
1458 }
1459 if(shaders[MESA_SHADER_TESS_CTRL]) {
1460 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
1461 }
1462 if(shaders[MESA_SHADER_VERTEX]) {
1463 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
1464 }
1465
1466 for (int i = 1; i < shader_count; ++i) {
1467 nir_lower_io_arrays_to_elements(ordered_shaders[i],
1468 ordered_shaders[i - 1]);
1469
1470 nir_remove_dead_variables(ordered_shaders[i],
1471 nir_var_shader_out);
1472 nir_remove_dead_variables(ordered_shaders[i - 1],
1473 nir_var_shader_in);
1474
1475 bool progress = nir_remove_unused_varyings(ordered_shaders[i],
1476 ordered_shaders[i - 1]);
1477
1478 nir_compact_varyings(ordered_shaders[i],
1479 ordered_shaders[i - 1], true);
1480
1481 if (progress) {
1482 if (nir_lower_global_vars_to_local(ordered_shaders[i])) {
1483 ac_lower_indirect_derefs(ordered_shaders[i],
1484 pipeline->device->physical_device->rad_info.chip_class);
1485 }
1486 radv_optimize_nir(ordered_shaders[i]);
1487
1488 if (nir_lower_global_vars_to_local(ordered_shaders[i - 1])) {
1489 ac_lower_indirect_derefs(ordered_shaders[i - 1],
1490 pipeline->device->physical_device->rad_info.chip_class);
1491 }
1492 radv_optimize_nir(ordered_shaders[i - 1]);
1493 }
1494 }
1495 }
1496
1497
1498 static struct radv_pipeline_key
1499 radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
1500 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1501 const struct radv_blend_state *blend,
1502 bool has_view_index)
1503 {
1504 const VkPipelineVertexInputStateCreateInfo *input_state =
1505 pCreateInfo->pVertexInputState;
1506 struct radv_pipeline_key key;
1507 memset(&key, 0, sizeof(key));
1508
1509 key.has_multiview_view_index = has_view_index;
1510
1511 uint32_t binding_input_rate = 0;
1512 for (unsigned i = 0; i < input_state->vertexBindingDescriptionCount; ++i) {
1513 if (input_state->pVertexBindingDescriptions[i].inputRate)
1514 binding_input_rate |= 1u << input_state->pVertexBindingDescriptions[i].binding;
1515 }
1516
1517 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
1518 unsigned binding;
1519 binding = input_state->pVertexAttributeDescriptions[i].binding;
1520 if (binding_input_rate & (1u << binding))
1521 key.instance_rate_inputs |= 1u << input_state->pVertexAttributeDescriptions[i].location;
1522 }
1523
1524 if (pCreateInfo->pTessellationState)
1525 key.tess_input_vertices = pCreateInfo->pTessellationState->patchControlPoints;
1526
1527
1528 if (pCreateInfo->pMultisampleState &&
1529 pCreateInfo->pMultisampleState->rasterizationSamples > 1) {
1530 uint32_t num_samples = pCreateInfo->pMultisampleState->rasterizationSamples;
1531 uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo->pMultisampleState);
1532 key.multisample = true;
1533 key.log2_num_samples = util_logbase2(num_samples);
1534 key.log2_ps_iter_samples = util_logbase2(ps_iter_samples);
1535 }
1536
1537 key.col_format = blend->spi_shader_col_format;
1538 if (pipeline->device->physical_device->rad_info.chip_class < VI)
1539 radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.is_int8, &key.is_int10);
1540
1541 return key;
1542 }
1543
1544 static void
1545 radv_fill_shader_keys(struct radv_shader_variant_key *keys,
1546 const struct radv_pipeline_key *key,
1547 nir_shader **nir)
1548 {
1549 keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
1550
1551 if (nir[MESA_SHADER_TESS_CTRL]) {
1552 keys[MESA_SHADER_VERTEX].vs.as_ls = true;
1553 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = 0;
1554 keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices;
1555 keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
1556
1557 keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
1558 }
1559
1560 if (nir[MESA_SHADER_GEOMETRY]) {
1561 if (nir[MESA_SHADER_TESS_CTRL])
1562 keys[MESA_SHADER_TESS_EVAL].tes.as_es = true;
1563 else
1564 keys[MESA_SHADER_VERTEX].vs.as_es = true;
1565 }
1566
1567 for(int i = 0; i < MESA_SHADER_STAGES; ++i)
1568 keys[i].has_multiview_view_index = key->has_multiview_view_index;
1569
1570 keys[MESA_SHADER_FRAGMENT].fs.multisample = key->multisample;
1571 keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format;
1572 keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8;
1573 keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
1574 keys[MESA_SHADER_FRAGMENT].fs.log2_ps_iter_samples = key->log2_ps_iter_samples;
1575 keys[MESA_SHADER_FRAGMENT].fs.log2_num_samples = key->log2_num_samples;
1576 }
1577
1578 static void
1579 merge_tess_info(struct shader_info *tes_info,
1580 const struct shader_info *tcs_info)
1581 {
1582 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
1583 *
1584 * "PointMode. Controls generation of points rather than triangles
1585 * or lines. This functionality defaults to disabled, and is
1586 * enabled if either shader stage includes the execution mode.
1587 *
1588 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
1589 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
1590 * and OutputVertices, it says:
1591 *
1592 * "One mode must be set in at least one of the tessellation
1593 * shader stages."
1594 *
1595 * So, the fields can be set in either the TCS or TES, but they must
1596 * agree if set in both. Our backend looks at TES, so bitwise-or in
1597 * the values from the TCS.
1598 */
1599 assert(tcs_info->tess.tcs_vertices_out == 0 ||
1600 tes_info->tess.tcs_vertices_out == 0 ||
1601 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
1602 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
1603
1604 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
1605 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
1606 tcs_info->tess.spacing == tes_info->tess.spacing);
1607 tes_info->tess.spacing |= tcs_info->tess.spacing;
1608
1609 assert(tcs_info->tess.primitive_mode == 0 ||
1610 tes_info->tess.primitive_mode == 0 ||
1611 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
1612 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
1613 tes_info->tess.ccw |= tcs_info->tess.ccw;
1614 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
1615 }
1616
1617 static
1618 void radv_create_shaders(struct radv_pipeline *pipeline,
1619 struct radv_device *device,
1620 struct radv_pipeline_cache *cache,
1621 struct radv_pipeline_key key,
1622 const VkPipelineShaderStageCreateInfo **pStages)
1623 {
1624 struct radv_shader_module fs_m = {0};
1625 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
1626 nir_shader *nir[MESA_SHADER_STAGES] = {0};
1627 void *codes[MESA_SHADER_STAGES] = {0};
1628 unsigned code_sizes[MESA_SHADER_STAGES] = {0};
1629 struct radv_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{0}}}};
1630 unsigned char hash[20], gs_copy_hash[20];
1631
1632 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
1633 if (pStages[i]) {
1634 modules[i] = radv_shader_module_from_handle(pStages[i]->module);
1635 if (modules[i]->nir)
1636 _mesa_sha1_compute(modules[i]->nir->info.name,
1637 strlen(modules[i]->nir->info.name),
1638 modules[i]->sha1);
1639 }
1640 }
1641
1642 radv_hash_shaders(hash, pStages, pipeline->layout, &key, get_hash_flags(device));
1643 memcpy(gs_copy_hash, hash, 20);
1644 gs_copy_hash[0] ^= 1;
1645
1646 if (modules[MESA_SHADER_GEOMETRY]) {
1647 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
1648 radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants);
1649 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
1650 }
1651
1652 if (radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders) &&
1653 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
1654 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
1655 if (pipeline->shaders[i])
1656 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
1657 }
1658 return;
1659 }
1660
1661 if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
1662 nir_builder fs_b;
1663 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
1664 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
1665 fs_m.nir = fs_b.shader;
1666 modules[MESA_SHADER_FRAGMENT] = &fs_m;
1667 }
1668
1669 /* Determine first and last stage. */
1670 unsigned first = MESA_SHADER_STAGES;
1671 unsigned last = 0;
1672 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
1673 if (!pStages[i])
1674 continue;
1675 if (first == MESA_SHADER_STAGES)
1676 first = i;
1677 last = i;
1678 }
1679
1680 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
1681 const VkPipelineShaderStageCreateInfo *stage = pStages[i];
1682
1683 if (!modules[i])
1684 continue;
1685
1686 nir[i] = radv_shader_compile_to_nir(device, modules[i],
1687 stage ? stage->pName : "main", i,
1688 stage ? stage->pSpecializationInfo : NULL);
1689 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
1690
1691 /* We don't want to alter meta shaders IR directly so clone it
1692 * first.
1693 */
1694 if (nir[i]->info.name) {
1695 nir[i] = nir_shader_clone(NULL, nir[i]);
1696 }
1697
1698 if (first != last) {
1699 nir_variable_mode mask = 0;
1700
1701 if (i != first)
1702 mask = mask | nir_var_shader_in;
1703
1704 if (i != last)
1705 mask = mask | nir_var_shader_out;
1706
1707 nir_lower_io_to_scalar_early(nir[i], mask);
1708 radv_optimize_nir(nir[i]);
1709 }
1710 }
1711
1712 if (nir[MESA_SHADER_TESS_CTRL]) {
1713 nir_lower_tes_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out);
1714 merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
1715 }
1716
1717 radv_link_shaders(pipeline, nir);
1718
1719 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
1720 if (modules[i] && radv_can_dump_shader(device, modules[i]))
1721 nir_print_shader(nir[i], stderr);
1722 }
1723
1724 radv_fill_shader_keys(keys, &key, nir);
1725
1726 if (nir[MESA_SHADER_FRAGMENT]) {
1727 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
1728 pipeline->shaders[MESA_SHADER_FRAGMENT] =
1729 radv_shader_variant_create(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
1730 pipeline->layout, keys + MESA_SHADER_FRAGMENT,
1731 &codes[MESA_SHADER_FRAGMENT], &code_sizes[MESA_SHADER_FRAGMENT]);
1732 }
1733
1734 /* TODO: These are no longer used as keys we should refactor this */
1735 keys[MESA_SHADER_VERTEX].vs.export_prim_id =
1736 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input;
1737 keys[MESA_SHADER_VERTEX].vs.export_layer_id =
1738 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.layer_input;
1739 keys[MESA_SHADER_TESS_EVAL].tes.export_prim_id =
1740 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input;
1741 keys[MESA_SHADER_TESS_EVAL].tes.export_layer_id =
1742 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.layer_input;
1743 }
1744
1745 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
1746 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
1747 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
1748 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
1749 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
1750 pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_create(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
1751 pipeline->layout,
1752 &key, &codes[MESA_SHADER_TESS_CTRL],
1753 &code_sizes[MESA_SHADER_TESS_CTRL]);
1754 }
1755 modules[MESA_SHADER_VERTEX] = NULL;
1756 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
1757 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.tcs.outputs_written);
1758 }
1759
1760 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
1761 gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
1762 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
1763 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
1764 pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_create(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
1765 pipeline->layout,
1766 &keys[pre_stage] , &codes[MESA_SHADER_GEOMETRY],
1767 &code_sizes[MESA_SHADER_GEOMETRY]);
1768 }
1769 modules[pre_stage] = NULL;
1770 }
1771
1772 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
1773 if(modules[i] && !pipeline->shaders[i]) {
1774 if (i == MESA_SHADER_TESS_CTRL) {
1775 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.ls_outputs_written);
1776 }
1777 if (i == MESA_SHADER_TESS_EVAL) {
1778 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
1779 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.tcs.outputs_written);
1780 }
1781 pipeline->shaders[i] = radv_shader_variant_create(device, modules[i], &nir[i], 1,
1782 pipeline->layout,
1783 keys + i, &codes[i],
1784 &code_sizes[i]);
1785 }
1786 }
1787
1788 if(modules[MESA_SHADER_GEOMETRY]) {
1789 void *gs_copy_code = NULL;
1790 unsigned gs_copy_code_size = 0;
1791 if (!pipeline->gs_copy_shader) {
1792 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
1793 device, nir[MESA_SHADER_GEOMETRY], &gs_copy_code,
1794 &gs_copy_code_size,
1795 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
1796 }
1797
1798 if (pipeline->gs_copy_shader) {
1799 void *code[MESA_SHADER_STAGES] = {0};
1800 unsigned code_size[MESA_SHADER_STAGES] = {0};
1801 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
1802
1803 code[MESA_SHADER_GEOMETRY] = gs_copy_code;
1804 code_size[MESA_SHADER_GEOMETRY] = gs_copy_code_size;
1805 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
1806
1807 radv_pipeline_cache_insert_shaders(device, cache,
1808 gs_copy_hash,
1809 variants,
1810 (const void**)code,
1811 code_size);
1812 }
1813 free(gs_copy_code);
1814 }
1815
1816 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
1817 (const void**)codes, code_sizes);
1818
1819 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
1820 free(codes[i]);
1821 if (modules[i]) {
1822 if (!pipeline->device->keep_shader_info)
1823 ralloc_free(nir[i]);
1824
1825 if (radv_can_dump_shader_stats(device, modules[i]))
1826 radv_shader_dump_stats(device,
1827 pipeline->shaders[i],
1828 i, stderr);
1829 }
1830 }
1831
1832 if (fs_m.nir)
1833 ralloc_free(fs_m.nir);
1834 }
1835
1836 static uint32_t
1837 radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
1838 gl_shader_stage stage, enum chip_class chip_class)
1839 {
1840 bool has_gs = radv_pipeline_has_gs(pipeline);
1841 bool has_tess = radv_pipeline_has_tess(pipeline);
1842 switch (stage) {
1843 case MESA_SHADER_FRAGMENT:
1844 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
1845 case MESA_SHADER_VERTEX:
1846 if (chip_class >= GFX9) {
1847 return has_tess ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
1848 has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
1849 R_00B130_SPI_SHADER_USER_DATA_VS_0;
1850 }
1851 if (has_tess)
1852 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
1853 else
1854 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0;
1855 case MESA_SHADER_GEOMETRY:
1856 return chip_class >= GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
1857 R_00B230_SPI_SHADER_USER_DATA_GS_0;
1858 case MESA_SHADER_COMPUTE:
1859 return R_00B900_COMPUTE_USER_DATA_0;
1860 case MESA_SHADER_TESS_CTRL:
1861 return chip_class >= GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
1862 R_00B430_SPI_SHADER_USER_DATA_HS_0;
1863 case MESA_SHADER_TESS_EVAL:
1864 if (chip_class >= GFX9) {
1865 return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
1866 R_00B130_SPI_SHADER_USER_DATA_VS_0;
1867 }
1868 if (has_gs)
1869 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
1870 else
1871 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
1872 default:
1873 unreachable("unknown shader");
1874 }
1875 }
1876
1877 struct radv_bin_size_entry {
1878 unsigned bpp;
1879 VkExtent2D extent;
1880 };
1881
1882 static VkExtent2D
1883 radv_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
1884 {
1885 static const struct radv_bin_size_entry color_size_table[][3][9] = {
1886 {
1887 /* One RB / SE */
1888 {
1889 /* One shader engine */
1890 { 0, {128, 128}},
1891 { 1, { 64, 128}},
1892 { 2, { 32, 128}},
1893 { 3, { 16, 128}},
1894 { 17, { 0, 0}},
1895 { UINT_MAX, { 0, 0}},
1896 },
1897 {
1898 /* Two shader engines */
1899 { 0, {128, 128}},
1900 { 2, { 64, 128}},
1901 { 3, { 32, 128}},
1902 { 5, { 16, 128}},
1903 { 17, { 0, 0}},
1904 { UINT_MAX, { 0, 0}},
1905 },
1906 {
1907 /* Four shader engines */
1908 { 0, {128, 128}},
1909 { 3, { 64, 128}},
1910 { 5, { 16, 128}},
1911 { 17, { 0, 0}},
1912 { UINT_MAX, { 0, 0}},
1913 },
1914 },
1915 {
1916 /* Two RB / SE */
1917 {
1918 /* One shader engine */
1919 { 0, {128, 128}},
1920 { 2, { 64, 128}},
1921 { 3, { 32, 128}},
1922 { 5, { 16, 128}},
1923 { 33, { 0, 0}},
1924 { UINT_MAX, { 0, 0}},
1925 },
1926 {
1927 /* Two shader engines */
1928 { 0, {128, 128}},
1929 { 3, { 64, 128}},
1930 { 5, { 32, 128}},
1931 { 9, { 16, 128}},
1932 { 33, { 0, 0}},
1933 { UINT_MAX, { 0, 0}},
1934 },
1935 {
1936 /* Four shader engines */
1937 { 0, {256, 256}},
1938 { 2, {128, 256}},
1939 { 3, {128, 128}},
1940 { 5, { 64, 128}},
1941 { 9, { 16, 128}},
1942 { 33, { 0, 0}},
1943 { UINT_MAX, { 0, 0}},
1944 },
1945 },
1946 {
1947 /* Four RB / SE */
1948 {
1949 /* One shader engine */
1950 { 0, {128, 256}},
1951 { 2, {128, 128}},
1952 { 3, { 64, 128}},
1953 { 5, { 32, 128}},
1954 { 9, { 16, 128}},
1955 { 33, { 0, 0}},
1956 { UINT_MAX, { 0, 0}},
1957 },
1958 {
1959 /* Two shader engines */
1960 { 0, {256, 256}},
1961 { 2, {128, 256}},
1962 { 3, {128, 128}},
1963 { 5, { 64, 128}},
1964 { 9, { 32, 128}},
1965 { 17, { 16, 128}},
1966 { 33, { 0, 0}},
1967 { UINT_MAX, { 0, 0}},
1968 },
1969 {
1970 /* Four shader engines */
1971 { 0, {256, 512}},
1972 { 2, {256, 256}},
1973 { 3, {128, 256}},
1974 { 5, {128, 128}},
1975 { 9, { 64, 128}},
1976 { 17, { 16, 128}},
1977 { 33, { 0, 0}},
1978 { UINT_MAX, { 0, 0}},
1979 },
1980 },
1981 };
1982 static const struct radv_bin_size_entry ds_size_table[][3][9] = {
1983 {
1984 // One RB / SE
1985 {
1986 // One shader engine
1987 { 0, {128, 256}},
1988 { 2, {128, 128}},
1989 { 4, { 64, 128}},
1990 { 7, { 32, 128}},
1991 { 13, { 16, 128}},
1992 { 49, { 0, 0}},
1993 { UINT_MAX, { 0, 0}},
1994 },
1995 {
1996 // Two shader engines
1997 { 0, {256, 256}},
1998 { 2, {128, 256}},
1999 { 4, {128, 128}},
2000 { 7, { 64, 128}},
2001 { 13, { 32, 128}},
2002 { 25, { 16, 128}},
2003 { 49, { 0, 0}},
2004 { UINT_MAX, { 0, 0}},
2005 },
2006 {
2007 // Four shader engines
2008 { 0, {256, 512}},
2009 { 2, {256, 256}},
2010 { 4, {128, 256}},
2011 { 7, {128, 128}},
2012 { 13, { 64, 128}},
2013 { 25, { 16, 128}},
2014 { 49, { 0, 0}},
2015 { UINT_MAX, { 0, 0}},
2016 },
2017 },
2018 {
2019 // Two RB / SE
2020 {
2021 // One shader engine
2022 { 0, {256, 256}},
2023 { 2, {128, 256}},
2024 { 4, {128, 128}},
2025 { 7, { 64, 128}},
2026 { 13, { 32, 128}},
2027 { 25, { 16, 128}},
2028 { 97, { 0, 0}},
2029 { UINT_MAX, { 0, 0}},
2030 },
2031 {
2032 // Two shader engines
2033 { 0, {256, 512}},
2034 { 2, {256, 256}},
2035 { 4, {128, 256}},
2036 { 7, {128, 128}},
2037 { 13, { 64, 128}},
2038 { 25, { 32, 128}},
2039 { 49, { 16, 128}},
2040 { 97, { 0, 0}},
2041 { UINT_MAX, { 0, 0}},
2042 },
2043 {
2044 // Four shader engines
2045 { 0, {512, 512}},
2046 { 2, {256, 512}},
2047 { 4, {256, 256}},
2048 { 7, {128, 256}},
2049 { 13, {128, 128}},
2050 { 25, { 64, 128}},
2051 { 49, { 16, 128}},
2052 { 97, { 0, 0}},
2053 { UINT_MAX, { 0, 0}},
2054 },
2055 },
2056 {
2057 // Four RB / SE
2058 {
2059 // One shader engine
2060 { 0, {256, 512}},
2061 { 2, {256, 256}},
2062 { 4, {128, 256}},
2063 { 7, {128, 128}},
2064 { 13, { 64, 128}},
2065 { 25, { 32, 128}},
2066 { 49, { 16, 128}},
2067 { UINT_MAX, { 0, 0}},
2068 },
2069 {
2070 // Two shader engines
2071 { 0, {512, 512}},
2072 { 2, {256, 512}},
2073 { 4, {256, 256}},
2074 { 7, {128, 256}},
2075 { 13, {128, 128}},
2076 { 25, { 64, 128}},
2077 { 49, { 32, 128}},
2078 { 97, { 16, 128}},
2079 { UINT_MAX, { 0, 0}},
2080 },
2081 {
2082 // Four shader engines
2083 { 0, {512, 512}},
2084 { 4, {256, 512}},
2085 { 7, {256, 256}},
2086 { 13, {128, 256}},
2087 { 25, {128, 128}},
2088 { 49, { 64, 128}},
2089 { 97, { 16, 128}},
2090 { UINT_MAX, { 0, 0}},
2091 },
2092 },
2093 };
2094
2095 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2096 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2097 VkExtent2D extent = {512, 512};
2098
2099 unsigned log_num_rb_per_se =
2100 util_logbase2_ceil(pipeline->device->physical_device->rad_info.num_render_backends /
2101 pipeline->device->physical_device->rad_info.max_se);
2102 unsigned log_num_se = util_logbase2_ceil(pipeline->device->physical_device->rad_info.max_se);
2103
2104 unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_mode_cntl_1);
2105 unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->graphics.ms.db_eqaa);
2106 unsigned effective_samples = total_samples;
2107 unsigned color_bytes_per_pixel = 0;
2108
2109 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
2110 if (vkblend) {
2111 for (unsigned i = 0; i < subpass->color_count; i++) {
2112 if (!vkblend->pAttachments[i].colorWriteMask)
2113 continue;
2114
2115 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
2116 continue;
2117
2118 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
2119 color_bytes_per_pixel += vk_format_get_blocksize(format);
2120 }
2121
2122 /* MSAA images typically don't use all samples all the time. */
2123 if (effective_samples >= 2 && ps_iter_samples <= 1)
2124 effective_samples = 2;
2125 color_bytes_per_pixel *= effective_samples;
2126 }
2127
2128 const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se];
2129 while(color_entry->bpp <= color_bytes_per_pixel)
2130 ++color_entry;
2131
2132 extent = color_entry->extent;
2133
2134 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2135 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment.attachment;
2136
2137 /* Coefficients taken from AMDVLK */
2138 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
2139 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
2140 unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples;
2141
2142 const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se];
2143 while(ds_entry->bpp <= ds_bytes_per_pixel)
2144 ++ds_entry;
2145
2146 extent.width = MIN2(extent.width, ds_entry->extent.width);
2147 extent.height = MIN2(extent.height, ds_entry->extent.height);
2148 }
2149
2150 return extent;
2151 }
2152
2153 static void
2154 radv_pipeline_generate_binning_state(struct radeon_winsys_cs *cs,
2155 struct radv_pipeline *pipeline,
2156 const VkGraphicsPipelineCreateInfo *pCreateInfo)
2157 {
2158 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
2159 return;
2160
2161 uint32_t pa_sc_binner_cntl_0 =
2162 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
2163 S_028C44_DISABLE_START_OF_PRIM(1);
2164 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
2165
2166 VkExtent2D bin_size = radv_compute_bin_size(pipeline, pCreateInfo);
2167
2168 unsigned context_states_per_bin; /* allowed range: [1, 6] */
2169 unsigned persistent_states_per_bin; /* allowed range: [1, 32] */
2170 unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */
2171
2172 switch (pipeline->device->physical_device->rad_info.family) {
2173 case CHIP_VEGA10:
2174 case CHIP_VEGA12:
2175 context_states_per_bin = 1;
2176 persistent_states_per_bin = 1;
2177 fpovs_per_batch = 63;
2178 break;
2179 case CHIP_RAVEN:
2180 context_states_per_bin = 6;
2181 persistent_states_per_bin = 32;
2182 fpovs_per_batch = 63;
2183 break;
2184 default:
2185 unreachable("unhandled family while determining binning state.");
2186 }
2187
2188 if (pipeline->device->pbb_allowed && bin_size.width && bin_size.height) {
2189 pa_sc_binner_cntl_0 =
2190 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
2191 S_028C44_BIN_SIZE_X(bin_size.width == 16) |
2192 S_028C44_BIN_SIZE_Y(bin_size.height == 16) |
2193 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size.width, 32)) - 5) |
2194 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size.height, 32)) - 5) |
2195 S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin - 1) |
2196 S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin - 1) |
2197 S_028C44_DISABLE_START_OF_PRIM(1) |
2198 S_028C44_FPOVS_PER_BATCH(fpovs_per_batch) |
2199 S_028C44_OPTIMAL_BIN_SELECTION(1);
2200 }
2201
2202 radeon_set_context_reg(cs, R_028C44_PA_SC_BINNER_CNTL_0,
2203 pa_sc_binner_cntl_0);
2204 radeon_set_context_reg(cs, R_028060_DB_DFSM_CONTROL,
2205 db_dfsm_control);
2206 }
2207
2208
2209 static void
2210 radv_pipeline_generate_depth_stencil_state(struct radeon_winsys_cs *cs,
2211 struct radv_pipeline *pipeline,
2212 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2213 const struct radv_graphics_pipeline_create_info *extra)
2214 {
2215 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
2216 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2217 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2218 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
2219 struct radv_render_pass_attachment *attachment = NULL;
2220 uint32_t db_depth_control = 0, db_stencil_control = 0;
2221 uint32_t db_render_control = 0, db_render_override2 = 0;
2222 uint32_t db_render_override = 0;
2223
2224 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED)
2225 attachment = pass->attachments + subpass->depth_stencil_attachment.attachment;
2226
2227 bool has_depth_attachment = attachment && vk_format_is_depth(attachment->format);
2228 bool has_stencil_attachment = attachment && vk_format_is_stencil(attachment->format);
2229
2230 if (vkds && has_depth_attachment) {
2231 db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
2232 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
2233 S_028800_ZFUNC(vkds->depthCompareOp) |
2234 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
2235
2236 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
2237 db_render_override2 |= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment->samples > 2);
2238 }
2239
2240 if (has_stencil_attachment && vkds && vkds->stencilTestEnable) {
2241 db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
2242 db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
2243 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
2244 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
2245 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
2246
2247 db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
2248 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
2249 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
2250 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
2251 }
2252
2253 if (attachment && extra) {
2254 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
2255 db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
2256
2257 db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
2258 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
2259 db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
2260 db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
2261 db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
2262 }
2263
2264 db_render_override |= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
2265 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
2266
2267 if (pipeline->device->enabled_extensions.EXT_depth_range_unrestricted &&
2268 !pCreateInfo->pRasterizationState->depthClampEnable &&
2269 ps->info.info.ps.writes_z) {
2270 /* From VK_EXT_depth_range_unrestricted spec:
2271 *
2272 * "The behavior described in Primitive Clipping still applies.
2273 * If depth clamping is disabled the depth values are still
2274 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
2275 * depth clamping is enabled the above equation is ignored and
2276 * the depth values are instead clamped to the VkViewport
2277 * minDepth and maxDepth values, which in the case of this
2278 * extension can be outside of the 0.0 to 1.0 range."
2279 */
2280 db_render_override |= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
2281 }
2282
2283 radeon_set_context_reg(cs, R_028800_DB_DEPTH_CONTROL, db_depth_control);
2284 radeon_set_context_reg(cs, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
2285
2286 radeon_set_context_reg(cs, R_028000_DB_RENDER_CONTROL, db_render_control);
2287 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
2288 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2, db_render_override2);
2289 }
2290
2291 static void
2292 radv_pipeline_generate_blend_state(struct radeon_winsys_cs *cs,
2293 struct radv_pipeline *pipeline,
2294 const struct radv_blend_state *blend)
2295 {
2296 radeon_set_context_reg_seq(cs, R_028780_CB_BLEND0_CONTROL, 8);
2297 radeon_emit_array(cs, blend->cb_blend_control,
2298 8);
2299 radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control);
2300 radeon_set_context_reg(cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask);
2301
2302 if (pipeline->device->physical_device->has_rbplus) {
2303
2304 radeon_set_context_reg_seq(cs, R_028760_SX_MRT0_BLEND_OPT, 8);
2305 radeon_emit_array(cs, blend->sx_mrt_blend_opt, 8);
2306
2307 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
2308 radeon_emit(cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
2309 radeon_emit(cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
2310 radeon_emit(cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
2311 }
2312
2313 radeon_set_context_reg(cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
2314
2315 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
2316 radeon_set_context_reg(cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
2317 }
2318
2319
2320 static void
2321 radv_pipeline_generate_raster_state(struct radeon_winsys_cs *cs,
2322 const VkGraphicsPipelineCreateInfo *pCreateInfo)
2323 {
2324 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
2325
2326 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
2327 S_028810_PS_UCP_MODE(3) |
2328 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
2329 S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
2330 S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
2331 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
2332 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
2333
2334 radeon_set_context_reg(cs, R_0286D4_SPI_INTERP_CONTROL_0,
2335 S_0286D4_FLAT_SHADE_ENA(1) |
2336 S_0286D4_PNT_SPRITE_ENA(1) |
2337 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
2338 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
2339 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
2340 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
2341 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
2342
2343 radeon_set_context_reg(cs, R_028BE4_PA_SU_VTX_CNTL,
2344 S_028BE4_PIX_CENTER(1) | // TODO verify
2345 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
2346 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
2347
2348 radeon_set_context_reg(cs, R_028814_PA_SU_SC_MODE_CNTL,
2349 S_028814_FACE(vkraster->frontFace) |
2350 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
2351 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
2352 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
2353 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
2354 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
2355 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
2356 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
2357 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0));
2358 }
2359
2360
2361 static void
2362 radv_pipeline_generate_multisample_state(struct radeon_winsys_cs *cs,
2363 struct radv_pipeline *pipeline)
2364 {
2365 struct radv_multisample_state *ms = &pipeline->graphics.ms;
2366
2367 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2368 radeon_emit(cs, ms->pa_sc_aa_mask[0]);
2369 radeon_emit(cs, ms->pa_sc_aa_mask[1]);
2370
2371 radeon_set_context_reg(cs, R_028804_DB_EQAA, ms->db_eqaa);
2372 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
2373
2374 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
2375 uint32_t offset;
2376 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
2377 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_FRAGMENT];
2378 if (loc->sgpr_idx == -1)
2379 return;
2380 assert(loc->num_sgprs == 1);
2381 assert(!loc->indirect);
2382 switch (pipeline->graphics.ms.num_samples) {
2383 default:
2384 offset = 0;
2385 break;
2386 case 2:
2387 offset = 1;
2388 break;
2389 case 4:
2390 offset = 3;
2391 break;
2392 case 8:
2393 offset = 7;
2394 break;
2395 case 16:
2396 offset = 15;
2397 break;
2398 }
2399
2400 radeon_set_sh_reg(cs, base_reg + loc->sgpr_idx * 4, offset);
2401 }
2402 }
2403
2404 static void
2405 radv_pipeline_generate_vgt_gs_mode(struct radeon_winsys_cs *cs,
2406 const struct radv_pipeline *pipeline)
2407 {
2408 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
2409
2410 uint32_t vgt_primitiveid_en = false;
2411 uint32_t vgt_gs_mode = 0;
2412
2413 if (radv_pipeline_has_gs(pipeline)) {
2414 const struct radv_shader_variant *gs =
2415 pipeline->shaders[MESA_SHADER_GEOMETRY];
2416
2417 vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out,
2418 pipeline->device->physical_device->rad_info.chip_class);
2419 } else if (outinfo->export_prim_id) {
2420 vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
2421 vgt_primitiveid_en = true;
2422 }
2423
2424 radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, vgt_primitiveid_en);
2425 radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, vgt_gs_mode);
2426 }
2427
2428 static void
2429 radv_pipeline_generate_hw_vs(struct radeon_winsys_cs *cs,
2430 struct radv_pipeline *pipeline,
2431 struct radv_shader_variant *shader)
2432 {
2433 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2434
2435 radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
2436 radeon_emit(cs, va >> 8);
2437 radeon_emit(cs, S_00B124_MEM_BASE(va >> 40));
2438 radeon_emit(cs, shader->rsrc1);
2439 radeon_emit(cs, shader->rsrc2);
2440
2441 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
2442 unsigned clip_dist_mask, cull_dist_mask, total_mask;
2443 clip_dist_mask = outinfo->clip_dist_mask;
2444 cull_dist_mask = outinfo->cull_dist_mask;
2445 total_mask = clip_dist_mask | cull_dist_mask;
2446 bool misc_vec_ena = outinfo->writes_pointsize ||
2447 outinfo->writes_layer ||
2448 outinfo->writes_viewport_index;
2449
2450 radeon_set_context_reg(cs, R_0286C4_SPI_VS_OUT_CONFIG,
2451 S_0286C4_VS_EXPORT_COUNT(MAX2(1, outinfo->param_exports) - 1));
2452
2453 radeon_set_context_reg(cs, R_02870C_SPI_SHADER_POS_FORMAT,
2454 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
2455 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
2456 V_02870C_SPI_SHADER_4COMP :
2457 V_02870C_SPI_SHADER_NONE) |
2458 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
2459 V_02870C_SPI_SHADER_4COMP :
2460 V_02870C_SPI_SHADER_NONE) |
2461 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
2462 V_02870C_SPI_SHADER_4COMP :
2463 V_02870C_SPI_SHADER_NONE));
2464
2465 radeon_set_context_reg(cs, R_028818_PA_CL_VTE_CNTL,
2466 S_028818_VTX_W0_FMT(1) |
2467 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
2468 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
2469 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
2470
2471 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
2472 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
2473 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
2474 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
2475 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2476 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
2477 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
2478 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
2479 cull_dist_mask << 8 |
2480 clip_dist_mask);
2481
2482 if (pipeline->device->physical_device->rad_info.chip_class <= VI)
2483 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
2484 outinfo->writes_viewport_index);
2485 }
2486
2487 static void
2488 radv_pipeline_generate_hw_es(struct radeon_winsys_cs *cs,
2489 struct radv_pipeline *pipeline,
2490 struct radv_shader_variant *shader)
2491 {
2492 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2493
2494 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
2495 radeon_emit(cs, va >> 8);
2496 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
2497 radeon_emit(cs, shader->rsrc1);
2498 radeon_emit(cs, shader->rsrc2);
2499 }
2500
2501 static void
2502 radv_pipeline_generate_hw_ls(struct radeon_winsys_cs *cs,
2503 struct radv_pipeline *pipeline,
2504 struct radv_shader_variant *shader,
2505 const struct radv_tessellation_state *tess)
2506 {
2507 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2508 uint32_t rsrc2 = shader->rsrc2;
2509
2510 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
2511 radeon_emit(cs, va >> 8);
2512 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
2513
2514 rsrc2 |= S_00B52C_LDS_SIZE(tess->lds_size);
2515 if (pipeline->device->physical_device->rad_info.chip_class == CIK &&
2516 pipeline->device->physical_device->rad_info.family != CHIP_HAWAII)
2517 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
2518
2519 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
2520 radeon_emit(cs, shader->rsrc1);
2521 radeon_emit(cs, rsrc2);
2522 }
2523
2524 static void
2525 radv_pipeline_generate_hw_hs(struct radeon_winsys_cs *cs,
2526 struct radv_pipeline *pipeline,
2527 struct radv_shader_variant *shader,
2528 const struct radv_tessellation_state *tess)
2529 {
2530 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
2531
2532 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
2533 radeon_set_sh_reg_seq(cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
2534 radeon_emit(cs, va >> 8);
2535 radeon_emit(cs, S_00B414_MEM_BASE(va >> 40));
2536
2537 radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
2538 radeon_emit(cs, shader->rsrc1);
2539 radeon_emit(cs, shader->rsrc2 |
2540 S_00B42C_LDS_SIZE(tess->lds_size));
2541 } else {
2542 radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
2543 radeon_emit(cs, va >> 8);
2544 radeon_emit(cs, S_00B424_MEM_BASE(va >> 40));
2545 radeon_emit(cs, shader->rsrc1);
2546 radeon_emit(cs, shader->rsrc2);
2547 }
2548 }
2549
2550 static void
2551 radv_pipeline_generate_vertex_shader(struct radeon_winsys_cs *cs,
2552 struct radv_pipeline *pipeline,
2553 const struct radv_tessellation_state *tess)
2554 {
2555 struct radv_shader_variant *vs;
2556
2557 /* Skip shaders merged into HS/GS */
2558 vs = pipeline->shaders[MESA_SHADER_VERTEX];
2559 if (!vs)
2560 return;
2561
2562 if (vs->info.vs.as_ls)
2563 radv_pipeline_generate_hw_ls(cs, pipeline, vs, tess);
2564 else if (vs->info.vs.as_es)
2565 radv_pipeline_generate_hw_es(cs, pipeline, vs);
2566 else
2567 radv_pipeline_generate_hw_vs(cs, pipeline, vs);
2568 }
2569
2570 static void
2571 radv_pipeline_generate_tess_shaders(struct radeon_winsys_cs *cs,
2572 struct radv_pipeline *pipeline,
2573 const struct radv_tessellation_state *tess)
2574 {
2575 if (!radv_pipeline_has_tess(pipeline))
2576 return;
2577
2578 struct radv_shader_variant *tes, *tcs;
2579
2580 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
2581 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
2582
2583 if (tes) {
2584 if (tes->info.tes.as_es)
2585 radv_pipeline_generate_hw_es(cs, pipeline, tes);
2586 else
2587 radv_pipeline_generate_hw_vs(cs, pipeline, tes);
2588 }
2589
2590 radv_pipeline_generate_hw_hs(cs, pipeline, tcs, tess);
2591
2592 radeon_set_context_reg(cs, R_028B6C_VGT_TF_PARAM,
2593 tess->tf_param);
2594
2595 if (pipeline->device->physical_device->rad_info.chip_class >= CIK)
2596 radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2,
2597 tess->ls_hs_config);
2598 else
2599 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
2600 tess->ls_hs_config);
2601 }
2602
2603 static void
2604 radv_pipeline_generate_geometry_shader(struct radeon_winsys_cs *cs,
2605 struct radv_pipeline *pipeline,
2606 const struct radv_gs_state *gs_state)
2607 {
2608 struct radv_shader_variant *gs;
2609 uint64_t va;
2610
2611 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
2612 if (!gs)
2613 return;
2614
2615 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
2616
2617 radeon_set_context_reg_seq(cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
2618 radeon_emit(cs, gsvs_itemsize);
2619 radeon_emit(cs, gsvs_itemsize);
2620 radeon_emit(cs, gsvs_itemsize);
2621
2622 radeon_set_context_reg(cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
2623
2624 radeon_set_context_reg(cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
2625
2626 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
2627 radeon_set_context_reg_seq(cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
2628 radeon_emit(cs, gs_vert_itemsize >> 2);
2629 radeon_emit(cs, 0);
2630 radeon_emit(cs, 0);
2631 radeon_emit(cs, 0);
2632
2633 uint32_t gs_num_invocations = gs->info.gs.invocations;
2634 radeon_set_context_reg(cs, R_028B90_VGT_GS_INSTANCE_CNT,
2635 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
2636 S_028B90_ENABLE(gs_num_invocations > 0));
2637
2638 radeon_set_context_reg(cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
2639 gs_state->vgt_esgs_ring_itemsize);
2640
2641 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
2642
2643 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
2644 radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
2645 radeon_emit(cs, va >> 8);
2646 radeon_emit(cs, S_00B214_MEM_BASE(va >> 40));
2647
2648 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
2649 radeon_emit(cs, gs->rsrc1);
2650 radeon_emit(cs, gs->rsrc2 | S_00B22C_LDS_SIZE(gs_state->lds_size));
2651
2652 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL, gs_state->vgt_gs_onchip_cntl);
2653 radeon_set_context_reg(cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, gs_state->vgt_gs_max_prims_per_subgroup);
2654 } else {
2655 radeon_set_sh_reg_seq(cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
2656 radeon_emit(cs, va >> 8);
2657 radeon_emit(cs, S_00B224_MEM_BASE(va >> 40));
2658 radeon_emit(cs, gs->rsrc1);
2659 radeon_emit(cs, gs->rsrc2);
2660 }
2661
2662 radv_pipeline_generate_hw_vs(cs, pipeline, pipeline->gs_copy_shader);
2663 }
2664
2665 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade)
2666 {
2667 uint32_t ps_input_cntl;
2668 if (offset <= AC_EXP_PARAM_OFFSET_31) {
2669 ps_input_cntl = S_028644_OFFSET(offset);
2670 if (flat_shade)
2671 ps_input_cntl |= S_028644_FLAT_SHADE(1);
2672 } else {
2673 /* The input is a DEFAULT_VAL constant. */
2674 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
2675 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
2676 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
2677 ps_input_cntl = S_028644_OFFSET(0x20) |
2678 S_028644_DEFAULT_VAL(offset);
2679 }
2680 return ps_input_cntl;
2681 }
2682
2683 static void
2684 radv_pipeline_generate_ps_inputs(struct radeon_winsys_cs *cs,
2685 struct radv_pipeline *pipeline)
2686 {
2687 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
2688 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
2689 uint32_t ps_input_cntl[32];
2690
2691 unsigned ps_offset = 0;
2692
2693 if (ps->info.info.ps.prim_id_input) {
2694 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
2695 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
2696 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
2697 ++ps_offset;
2698 }
2699 }
2700
2701 if (ps->info.info.ps.layer_input ||
2702 ps->info.info.ps.uses_input_attachments ||
2703 ps->info.info.needs_multiview_view_index) {
2704 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
2705 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
2706 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
2707 else
2708 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true);
2709 ++ps_offset;
2710 }
2711
2712 if (ps->info.info.ps.has_pcoord) {
2713 unsigned val;
2714 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
2715 ps_input_cntl[ps_offset] = val;
2716 ps_offset++;
2717 }
2718
2719 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
2720 unsigned vs_offset;
2721 bool flat_shade;
2722 if (!(ps->info.fs.input_mask & (1u << i)))
2723 continue;
2724
2725 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
2726 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
2727 ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
2728 ++ps_offset;
2729 continue;
2730 }
2731
2732 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
2733
2734 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade);
2735 ++ps_offset;
2736 }
2737
2738 if (ps_offset) {
2739 radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, ps_offset);
2740 for (unsigned i = 0; i < ps_offset; i++) {
2741 radeon_emit(cs, ps_input_cntl[i]);
2742 }
2743 }
2744 }
2745
2746 static uint32_t
2747 radv_compute_db_shader_control(const struct radv_device *device,
2748 const struct radv_shader_variant *ps)
2749 {
2750 unsigned z_order;
2751 if (ps->info.fs.early_fragment_test || !ps->info.info.ps.writes_memory)
2752 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
2753 else
2754 z_order = V_02880C_LATE_Z;
2755
2756 return S_02880C_Z_EXPORT_ENABLE(ps->info.info.ps.writes_z) |
2757 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.info.ps.writes_stencil) |
2758 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
2759 S_02880C_MASK_EXPORT_ENABLE(ps->info.info.ps.writes_sample_mask) |
2760 S_02880C_Z_ORDER(z_order) |
2761 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
2762 S_02880C_EXEC_ON_HIER_FAIL(ps->info.info.ps.writes_memory) |
2763 S_02880C_EXEC_ON_NOOP(ps->info.info.ps.writes_memory) |
2764 S_02880C_DUAL_QUAD_DISABLE(!!device->physical_device->has_rbplus);
2765 }
2766
2767 static void
2768 radv_pipeline_generate_fragment_shader(struct radeon_winsys_cs *cs,
2769 struct radv_pipeline *pipeline)
2770 {
2771 struct radv_shader_variant *ps;
2772 uint64_t va;
2773 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
2774
2775 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
2776 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
2777
2778 radeon_set_sh_reg_seq(cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
2779 radeon_emit(cs, va >> 8);
2780 radeon_emit(cs, S_00B024_MEM_BASE(va >> 40));
2781 radeon_emit(cs, ps->rsrc1);
2782 radeon_emit(cs, ps->rsrc2);
2783
2784 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
2785 radv_compute_db_shader_control(pipeline->device, ps));
2786
2787 radeon_set_context_reg(cs, R_0286CC_SPI_PS_INPUT_ENA,
2788 ps->config.spi_ps_input_ena);
2789
2790 radeon_set_context_reg(cs, R_0286D0_SPI_PS_INPUT_ADDR,
2791 ps->config.spi_ps_input_addr);
2792
2793 radeon_set_context_reg(cs, R_0286D8_SPI_PS_IN_CONTROL,
2794 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
2795
2796 radeon_set_context_reg(cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl);
2797
2798 radeon_set_context_reg(cs, R_028710_SPI_SHADER_Z_FORMAT,
2799 ac_get_spi_shader_z_format(ps->info.info.ps.writes_z,
2800 ps->info.info.ps.writes_stencil,
2801 ps->info.info.ps.writes_sample_mask));
2802
2803 if (pipeline->device->dfsm_allowed) {
2804 /* optimise this? */
2805 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2806 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
2807 }
2808 }
2809
2810 static void
2811 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_winsys_cs *cs,
2812 struct radv_pipeline *pipeline)
2813 {
2814 if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10)
2815 return;
2816
2817 unsigned vtx_reuse_depth = 30;
2818 if (radv_pipeline_has_tess(pipeline) &&
2819 radv_get_tess_eval_shader(pipeline)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
2820 vtx_reuse_depth = 14;
2821 }
2822 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
2823 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth));
2824 }
2825
2826 static uint32_t
2827 radv_compute_vgt_shader_stages_en(const struct radv_pipeline *pipeline)
2828 {
2829 uint32_t stages = 0;
2830 if (radv_pipeline_has_tess(pipeline)) {
2831 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2832 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
2833
2834 if (radv_pipeline_has_gs(pipeline))
2835 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
2836 S_028B54_GS_EN(1) |
2837 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2838 else
2839 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2840
2841 } else if (radv_pipeline_has_gs(pipeline))
2842 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
2843 S_028B54_GS_EN(1) |
2844 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2845
2846 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
2847 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
2848
2849 return stages;
2850 }
2851
2852 static uint32_t
2853 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo *pCreateInfo)
2854 {
2855 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
2856 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
2857
2858 if (!discard_rectangle_info)
2859 return 0xffff;
2860
2861 unsigned mask = 0;
2862
2863 for (unsigned i = 0; i < (1u << MAX_DISCARD_RECTANGLES); ++i) {
2864 /* Interpret i as a bitmask, and then set the bit in the mask if
2865 * that combination of rectangles in which the pixel is contained
2866 * should pass the cliprect test. */
2867 unsigned relevant_subset = i & ((1u << discard_rectangle_info->discardRectangleCount) - 1);
2868
2869 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT &&
2870 !relevant_subset)
2871 continue;
2872
2873 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT &&
2874 relevant_subset)
2875 continue;
2876
2877 mask |= 1u << i;
2878 }
2879
2880 return mask;
2881 }
2882
2883 static void
2884 radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
2885 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2886 const struct radv_graphics_pipeline_create_info *extra,
2887 const struct radv_blend_state *blend,
2888 const struct radv_tessellation_state *tess,
2889 const struct radv_gs_state *gs,
2890 unsigned prim, unsigned gs_out)
2891 {
2892 pipeline->cs.buf = malloc(4 * 256);
2893 pipeline->cs.max_dw = 256;
2894
2895 radv_pipeline_generate_depth_stencil_state(&pipeline->cs, pipeline, pCreateInfo, extra);
2896 radv_pipeline_generate_blend_state(&pipeline->cs, pipeline, blend);
2897 radv_pipeline_generate_raster_state(&pipeline->cs, pCreateInfo);
2898 radv_pipeline_generate_multisample_state(&pipeline->cs, pipeline);
2899 radv_pipeline_generate_vgt_gs_mode(&pipeline->cs, pipeline);
2900 radv_pipeline_generate_vertex_shader(&pipeline->cs, pipeline, tess);
2901 radv_pipeline_generate_tess_shaders(&pipeline->cs, pipeline, tess);
2902 radv_pipeline_generate_geometry_shader(&pipeline->cs, pipeline, gs);
2903 radv_pipeline_generate_fragment_shader(&pipeline->cs, pipeline);
2904 radv_pipeline_generate_ps_inputs(&pipeline->cs, pipeline);
2905 radv_pipeline_generate_vgt_vertex_reuse(&pipeline->cs, pipeline);
2906 radv_pipeline_generate_binning_state(&pipeline->cs, pipeline, pCreateInfo);
2907
2908 radeon_set_context_reg(&pipeline->cs, R_0286E8_SPI_TMPRING_SIZE,
2909 S_0286E8_WAVES(pipeline->max_waves) |
2910 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
2911
2912 radeon_set_context_reg(&pipeline->cs, R_028B54_VGT_SHADER_STAGES_EN, radv_compute_vgt_shader_stages_en(pipeline));
2913
2914 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
2915 radeon_set_uconfig_reg_idx(&pipeline->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
2916 } else {
2917 radeon_set_config_reg(&pipeline->cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
2918 }
2919 radeon_set_context_reg(&pipeline->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out);
2920
2921 radeon_set_context_reg(&pipeline->cs, R_02820C_PA_SC_CLIPRECT_RULE, radv_compute_cliprect_rule(pCreateInfo));
2922
2923 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
2924 }
2925
2926 static struct radv_ia_multi_vgt_param_helpers
2927 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
2928 const struct radv_tessellation_state *tess,
2929 uint32_t prim)
2930 {
2931 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param = {0};
2932 const struct radv_device *device = pipeline->device;
2933
2934 if (radv_pipeline_has_tess(pipeline))
2935 ia_multi_vgt_param.primgroup_size = tess->num_patches;
2936 else if (radv_pipeline_has_gs(pipeline))
2937 ia_multi_vgt_param.primgroup_size = 64;
2938 else
2939 ia_multi_vgt_param.primgroup_size = 128; /* recommended without a GS */
2940
2941 ia_multi_vgt_param.partial_es_wave = false;
2942 if (pipeline->device->has_distributed_tess) {
2943 if (radv_pipeline_has_gs(pipeline)) {
2944 if (device->physical_device->rad_info.chip_class <= VI)
2945 ia_multi_vgt_param.partial_es_wave = true;
2946 }
2947 }
2948 /* GS requirement. */
2949 if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3)
2950 ia_multi_vgt_param.partial_es_wave = true;
2951
2952 ia_multi_vgt_param.wd_switch_on_eop = false;
2953 if (device->physical_device->rad_info.chip_class >= CIK) {
2954 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
2955 * 4 shader engines. Set 1 to pass the assertion below.
2956 * The other cases are hardware requirements. */
2957 if (device->physical_device->rad_info.max_se < 4 ||
2958 prim == V_008958_DI_PT_POLYGON ||
2959 prim == V_008958_DI_PT_LINELOOP ||
2960 prim == V_008958_DI_PT_TRIFAN ||
2961 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
2962 (pipeline->graphics.prim_restart_enable &&
2963 (device->physical_device->rad_info.family < CHIP_POLARIS10 ||
2964 (prim != V_008958_DI_PT_POINTLIST &&
2965 prim != V_008958_DI_PT_LINESTRIP &&
2966 prim != V_008958_DI_PT_TRISTRIP))))
2967 ia_multi_vgt_param.wd_switch_on_eop = true;
2968 }
2969
2970 ia_multi_vgt_param.ia_switch_on_eoi = false;
2971 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input)
2972 ia_multi_vgt_param.ia_switch_on_eoi = true;
2973 if (radv_pipeline_has_gs(pipeline) &&
2974 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.info.uses_prim_id)
2975 ia_multi_vgt_param.ia_switch_on_eoi = true;
2976 if (radv_pipeline_has_tess(pipeline)) {
2977 /* SWITCH_ON_EOI must be set if PrimID is used. */
2978 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.uses_prim_id ||
2979 radv_get_tess_eval_shader(pipeline)->info.info.uses_prim_id)
2980 ia_multi_vgt_param.ia_switch_on_eoi = true;
2981 }
2982
2983 ia_multi_vgt_param.partial_vs_wave = false;
2984 if (radv_pipeline_has_tess(pipeline)) {
2985 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
2986 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
2987 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
2988 device->physical_device->rad_info.family == CHIP_BONAIRE) &&
2989 radv_pipeline_has_gs(pipeline))
2990 ia_multi_vgt_param.partial_vs_wave = true;
2991 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
2992 if (device->has_distributed_tess) {
2993 if (radv_pipeline_has_gs(pipeline)) {
2994 if (device->physical_device->rad_info.family == CHIP_TONGA ||
2995 device->physical_device->rad_info.family == CHIP_FIJI ||
2996 device->physical_device->rad_info.family == CHIP_POLARIS10 ||
2997 device->physical_device->rad_info.family == CHIP_POLARIS11 ||
2998 device->physical_device->rad_info.family == CHIP_POLARIS12)
2999 ia_multi_vgt_param.partial_vs_wave = true;
3000 } else {
3001 ia_multi_vgt_param.partial_vs_wave = true;
3002 }
3003 }
3004 }
3005
3006 ia_multi_vgt_param.base =
3007 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param.primgroup_size - 1) |
3008 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
3009 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == VI ? 2 : 0) |
3010 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
3011 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
3012
3013 return ia_multi_vgt_param;
3014 }
3015
3016
3017 static void
3018 radv_compute_vertex_input_state(struct radv_pipeline *pipeline,
3019 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3020 {
3021 const VkPipelineVertexInputStateCreateInfo *vi_info =
3022 pCreateInfo->pVertexInputState;
3023 struct radv_vertex_elements_info *velems = &pipeline->vertex_elements;
3024
3025 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
3026 const VkVertexInputAttributeDescription *desc =
3027 &vi_info->pVertexAttributeDescriptions[i];
3028 unsigned loc = desc->location;
3029 const struct vk_format_description *format_desc;
3030 int first_non_void;
3031 uint32_t num_format, data_format;
3032 format_desc = vk_format_description(desc->format);
3033 first_non_void = vk_format_get_first_non_void_channel(desc->format);
3034
3035 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
3036 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
3037
3038 velems->rsrc_word3[loc] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc->swizzle[0])) |
3039 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc->swizzle[1])) |
3040 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc->swizzle[2])) |
3041 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc->swizzle[3])) |
3042 S_008F0C_NUM_FORMAT(num_format) |
3043 S_008F0C_DATA_FORMAT(data_format);
3044 velems->format_size[loc] = format_desc->block.bits / 8;
3045 velems->offset[loc] = desc->offset;
3046 velems->binding[loc] = desc->binding;
3047 velems->count = MAX2(velems->count, loc + 1);
3048 }
3049
3050 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
3051 const VkVertexInputBindingDescription *desc =
3052 &vi_info->pVertexBindingDescriptions[i];
3053
3054 pipeline->binding_stride[desc->binding] = desc->stride;
3055 }
3056 }
3057
3058 static VkResult
3059 radv_pipeline_init(struct radv_pipeline *pipeline,
3060 struct radv_device *device,
3061 struct radv_pipeline_cache *cache,
3062 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3063 const struct radv_graphics_pipeline_create_info *extra,
3064 const VkAllocationCallbacks *alloc)
3065 {
3066 VkResult result;
3067 bool has_view_index = false;
3068
3069 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3070 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3071 if (subpass->view_mask)
3072 has_view_index = true;
3073 if (alloc == NULL)
3074 alloc = &device->alloc;
3075
3076 pipeline->device = device;
3077 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
3078 assert(pipeline->layout);
3079
3080 struct radv_blend_state blend = radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
3081
3082 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
3083 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
3084 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
3085 pStages[stage] = &pCreateInfo->pStages[i];
3086 }
3087
3088 radv_create_shaders(pipeline, device, cache,
3089 radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &blend, has_view_index),
3090 pStages);
3091
3092 pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
3093 radv_pipeline_init_multisample_state(pipeline, pCreateInfo);
3094 uint32_t gs_out;
3095 uint32_t prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
3096
3097 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
3098
3099 if (radv_pipeline_has_gs(pipeline)) {
3100 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
3101 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
3102 } else {
3103 gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
3104 }
3105 if (extra && extra->use_rectlist) {
3106 prim = V_008958_DI_PT_RECTLIST;
3107 gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
3108 pipeline->graphics.can_use_guardband = true;
3109 }
3110 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
3111 /* prim vertex count will need TESS changes */
3112 pipeline->graphics.prim_vertex_count = prim_size_table[prim];
3113
3114 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
3115
3116 /* Ensure that some export memory is always allocated, for two reasons:
3117 *
3118 * 1) Correctness: The hardware ignores the EXEC mask if no export
3119 * memory is allocated, so KILL and alpha test do not work correctly
3120 * without this.
3121 * 2) Performance: Every shader needs at least a NULL export, even when
3122 * it writes no color/depth output. The NULL export instruction
3123 * stalls without this setting.
3124 *
3125 * Don't add this to CB_SHADER_MASK.
3126 */
3127 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3128 if (!blend.spi_shader_col_format) {
3129 if (!ps->info.info.ps.writes_z &&
3130 !ps->info.info.ps.writes_stencil &&
3131 !ps->info.info.ps.writes_sample_mask)
3132 blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
3133 }
3134
3135 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
3136 if (pipeline->shaders[i]) {
3137 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
3138 }
3139 }
3140
3141 struct radv_gs_state gs = {0};
3142 if (radv_pipeline_has_gs(pipeline)) {
3143 gs = calculate_gs_info(pCreateInfo, pipeline);
3144 calculate_gs_ring_sizes(pipeline, &gs);
3145 }
3146
3147 struct radv_tessellation_state tess = {0};
3148 if (radv_pipeline_has_tess(pipeline)) {
3149 if (prim == V_008958_DI_PT_PATCH) {
3150 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
3151 pipeline->graphics.prim_vertex_count.incr = 1;
3152 }
3153 tess = calculate_tess_state(pipeline, pCreateInfo);
3154 }
3155
3156 pipeline->graphics.ia_multi_vgt_param = radv_compute_ia_multi_vgt_param_helpers(pipeline, &tess, prim);
3157
3158 radv_compute_vertex_input_state(pipeline, pCreateInfo);
3159
3160 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
3161 pipeline->user_data_0[i] = radv_pipeline_stage_to_user_data_0(pipeline, i, device->physical_device->rad_info.chip_class);
3162
3163 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
3164 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
3165 if (loc->sgpr_idx != -1) {
3166 pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX];
3167 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
3168 if (radv_get_vertex_shader(pipeline)->info.info.vs.needs_draw_id)
3169 pipeline->graphics.vtx_emit_num = 3;
3170 else
3171 pipeline->graphics.vtx_emit_num = 2;
3172 }
3173
3174 result = radv_pipeline_scratch_init(device, pipeline);
3175 radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend, &tess, &gs, prim, gs_out);
3176
3177 return result;
3178 }
3179
3180 VkResult
3181 radv_graphics_pipeline_create(
3182 VkDevice _device,
3183 VkPipelineCache _cache,
3184 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3185 const struct radv_graphics_pipeline_create_info *extra,
3186 const VkAllocationCallbacks *pAllocator,
3187 VkPipeline *pPipeline)
3188 {
3189 RADV_FROM_HANDLE(radv_device, device, _device);
3190 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
3191 struct radv_pipeline *pipeline;
3192 VkResult result;
3193
3194 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
3195 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3196 if (pipeline == NULL)
3197 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3198
3199 result = radv_pipeline_init(pipeline, device, cache,
3200 pCreateInfo, extra, pAllocator);
3201 if (result != VK_SUCCESS) {
3202 radv_pipeline_destroy(device, pipeline, pAllocator);
3203 return result;
3204 }
3205
3206 *pPipeline = radv_pipeline_to_handle(pipeline);
3207
3208 return VK_SUCCESS;
3209 }
3210
3211 VkResult radv_CreateGraphicsPipelines(
3212 VkDevice _device,
3213 VkPipelineCache pipelineCache,
3214 uint32_t count,
3215 const VkGraphicsPipelineCreateInfo* pCreateInfos,
3216 const VkAllocationCallbacks* pAllocator,
3217 VkPipeline* pPipelines)
3218 {
3219 VkResult result = VK_SUCCESS;
3220 unsigned i = 0;
3221
3222 for (; i < count; i++) {
3223 VkResult r;
3224 r = radv_graphics_pipeline_create(_device,
3225 pipelineCache,
3226 &pCreateInfos[i],
3227 NULL, pAllocator, &pPipelines[i]);
3228 if (r != VK_SUCCESS) {
3229 result = r;
3230 pPipelines[i] = VK_NULL_HANDLE;
3231 }
3232 }
3233
3234 return result;
3235 }
3236
3237
3238 static void
3239 radv_compute_generate_pm4(struct radv_pipeline *pipeline)
3240 {
3241 struct radv_shader_variant *compute_shader;
3242 struct radv_device *device = pipeline->device;
3243 unsigned compute_resource_limits;
3244 unsigned waves_per_threadgroup;
3245 uint64_t va;
3246
3247 pipeline->cs.buf = malloc(20 * 4);
3248 pipeline->cs.max_dw = 20;
3249
3250 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3251 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
3252
3253 radeon_set_sh_reg_seq(&pipeline->cs, R_00B830_COMPUTE_PGM_LO, 2);
3254 radeon_emit(&pipeline->cs, va >> 8);
3255 radeon_emit(&pipeline->cs, S_00B834_DATA(va >> 40));
3256
3257 radeon_set_sh_reg_seq(&pipeline->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
3258 radeon_emit(&pipeline->cs, compute_shader->rsrc1);
3259 radeon_emit(&pipeline->cs, compute_shader->rsrc2);
3260
3261 radeon_set_sh_reg(&pipeline->cs, R_00B860_COMPUTE_TMPRING_SIZE,
3262 S_00B860_WAVES(pipeline->max_waves) |
3263 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
3264
3265 /* Calculate best compute resource limits. */
3266 waves_per_threadgroup =
3267 DIV_ROUND_UP(compute_shader->info.cs.block_size[0] *
3268 compute_shader->info.cs.block_size[1] *
3269 compute_shader->info.cs.block_size[2], 64);
3270 compute_resource_limits =
3271 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0);
3272
3273 if (device->physical_device->rad_info.chip_class >= CIK) {
3274 unsigned num_cu_per_se =
3275 device->physical_device->rad_info.num_good_compute_units /
3276 device->physical_device->rad_info.max_se;
3277
3278 /* Force even distribution on all SIMDs in CU if the workgroup
3279 * size is 64. This has shown some good improvements if # of
3280 * CUs per SE is not a multiple of 4.
3281 */
3282 if (num_cu_per_se % 4 && waves_per_threadgroup == 1)
3283 compute_resource_limits |= S_00B854_FORCE_SIMD_DIST(1);
3284 }
3285
3286 radeon_set_sh_reg(&pipeline->cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
3287 compute_resource_limits);
3288
3289 radeon_set_sh_reg_seq(&pipeline->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3290 radeon_emit(&pipeline->cs,
3291 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
3292 radeon_emit(&pipeline->cs,
3293 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
3294 radeon_emit(&pipeline->cs,
3295 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
3296
3297 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
3298 }
3299
3300 static VkResult radv_compute_pipeline_create(
3301 VkDevice _device,
3302 VkPipelineCache _cache,
3303 const VkComputePipelineCreateInfo* pCreateInfo,
3304 const VkAllocationCallbacks* pAllocator,
3305 VkPipeline* pPipeline)
3306 {
3307 RADV_FROM_HANDLE(radv_device, device, _device);
3308 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
3309 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
3310 struct radv_pipeline *pipeline;
3311 VkResult result;
3312
3313 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
3314 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3315 if (pipeline == NULL)
3316 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3317
3318 pipeline->device = device;
3319 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
3320 assert(pipeline->layout);
3321
3322 pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
3323 radv_create_shaders(pipeline, device, cache, (struct radv_pipeline_key) {0}, pStages);
3324
3325 pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
3326 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
3327 result = radv_pipeline_scratch_init(device, pipeline);
3328 if (result != VK_SUCCESS) {
3329 radv_pipeline_destroy(device, pipeline, pAllocator);
3330 return result;
3331 }
3332
3333 radv_compute_generate_pm4(pipeline);
3334
3335 *pPipeline = radv_pipeline_to_handle(pipeline);
3336
3337 return VK_SUCCESS;
3338 }
3339
3340 VkResult radv_CreateComputePipelines(
3341 VkDevice _device,
3342 VkPipelineCache pipelineCache,
3343 uint32_t count,
3344 const VkComputePipelineCreateInfo* pCreateInfos,
3345 const VkAllocationCallbacks* pAllocator,
3346 VkPipeline* pPipelines)
3347 {
3348 VkResult result = VK_SUCCESS;
3349
3350 unsigned i = 0;
3351 for (; i < count; i++) {
3352 VkResult r;
3353 r = radv_compute_pipeline_create(_device, pipelineCache,
3354 &pCreateInfos[i],
3355 pAllocator, &pPipelines[i]);
3356 if (r != VK_SUCCESS) {
3357 result = r;
3358 pPipelines[i] = VK_NULL_HANDLE;
3359 }
3360 }
3361
3362 return result;
3363 }