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radv: Don't bail out on pipeline create failure.
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "radv_private.h"
30 #include "nir/nir.h"
31 #include "nir/nir_builder.h"
32 #include "spirv/nir_spirv.h"
33
34 #include <llvm-c/Core.h>
35 #include <llvm-c/TargetMachine.h>
36
37 #include "sid.h"
38 #include "r600d_common.h"
39 #include "ac_binary.h"
40 #include "ac_llvm_util.h"
41 #include "ac_nir_to_llvm.h"
42 #include "vk_format.h"
43 #include "util/debug.h"
44 void radv_shader_variant_destroy(struct radv_device *device,
45 struct radv_shader_variant *variant);
46
47 static const struct nir_shader_compiler_options nir_options = {
48 .vertex_id_zero_based = true,
49 .lower_scmp = true,
50 .lower_flrp32 = true,
51 .lower_fsat = true,
52 .lower_pack_snorm_2x16 = true,
53 .lower_pack_snorm_4x8 = true,
54 .lower_pack_unorm_2x16 = true,
55 .lower_pack_unorm_4x8 = true,
56 .lower_unpack_snorm_2x16 = true,
57 .lower_unpack_snorm_4x8 = true,
58 .lower_unpack_unorm_2x16 = true,
59 .lower_unpack_unorm_4x8 = true,
60 .lower_extract_byte = true,
61 .lower_extract_word = true,
62 };
63
64 VkResult radv_CreateShaderModule(
65 VkDevice _device,
66 const VkShaderModuleCreateInfo* pCreateInfo,
67 const VkAllocationCallbacks* pAllocator,
68 VkShaderModule* pShaderModule)
69 {
70 RADV_FROM_HANDLE(radv_device, device, _device);
71 struct radv_shader_module *module;
72
73 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
74 assert(pCreateInfo->flags == 0);
75
76 module = vk_alloc2(&device->alloc, pAllocator,
77 sizeof(*module) + pCreateInfo->codeSize, 8,
78 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
79 if (module == NULL)
80 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
81
82 module->nir = NULL;
83 module->size = pCreateInfo->codeSize;
84 memcpy(module->data, pCreateInfo->pCode, module->size);
85
86 _mesa_sha1_compute(module->data, module->size, module->sha1);
87
88 *pShaderModule = radv_shader_module_to_handle(module);
89
90 return VK_SUCCESS;
91 }
92
93 void radv_DestroyShaderModule(
94 VkDevice _device,
95 VkShaderModule _module,
96 const VkAllocationCallbacks* pAllocator)
97 {
98 RADV_FROM_HANDLE(radv_device, device, _device);
99 RADV_FROM_HANDLE(radv_shader_module, module, _module);
100
101 if (!module)
102 return;
103
104 vk_free2(&device->alloc, pAllocator, module);
105 }
106
107 void radv_DestroyPipeline(
108 VkDevice _device,
109 VkPipeline _pipeline,
110 const VkAllocationCallbacks* pAllocator)
111 {
112 RADV_FROM_HANDLE(radv_device, device, _device);
113 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
114
115 if (!_pipeline)
116 return;
117
118 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
119 if (pipeline->shaders[i])
120 radv_shader_variant_destroy(device, pipeline->shaders[i]);
121
122 vk_free2(&device->alloc, pAllocator, pipeline);
123 }
124
125
126 static void
127 radv_optimize_nir(struct nir_shader *shader)
128 {
129 bool progress;
130
131 do {
132 progress = false;
133
134 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
135 NIR_PASS_V(shader, nir_lower_alu_to_scalar);
136 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
137
138 NIR_PASS(progress, shader, nir_copy_prop);
139 NIR_PASS(progress, shader, nir_opt_remove_phis);
140 NIR_PASS(progress, shader, nir_opt_dce);
141 NIR_PASS(progress, shader, nir_opt_dead_cf);
142 NIR_PASS(progress, shader, nir_opt_cse);
143 NIR_PASS(progress, shader, nir_opt_peephole_select, 8);
144 NIR_PASS(progress, shader, nir_opt_algebraic);
145 NIR_PASS(progress, shader, nir_opt_constant_folding);
146 NIR_PASS(progress, shader, nir_opt_undef);
147 NIR_PASS(progress, shader, nir_opt_conditional_discard);
148 } while (progress);
149 }
150
151 static nir_shader *
152 radv_shader_compile_to_nir(struct radv_device *device,
153 struct radv_shader_module *module,
154 const char *entrypoint_name,
155 gl_shader_stage stage,
156 const VkSpecializationInfo *spec_info,
157 bool dump)
158 {
159 if (strcmp(entrypoint_name, "main") != 0) {
160 radv_finishme("Multiple shaders per module not really supported");
161 }
162
163 nir_shader *nir;
164 nir_function *entry_point;
165 if (module->nir) {
166 /* Some things such as our meta clear/blit code will give us a NIR
167 * shader directly. In that case, we just ignore the SPIR-V entirely
168 * and just use the NIR shader */
169 nir = module->nir;
170 nir->options = &nir_options;
171 nir_validate_shader(nir);
172
173 assert(exec_list_length(&nir->functions) == 1);
174 struct exec_node *node = exec_list_get_head(&nir->functions);
175 entry_point = exec_node_data(nir_function, node, node);
176 } else {
177 uint32_t *spirv = (uint32_t *) module->data;
178 assert(module->size % 4 == 0);
179
180 uint32_t num_spec_entries = 0;
181 struct nir_spirv_specialization *spec_entries = NULL;
182 if (spec_info && spec_info->mapEntryCount > 0) {
183 num_spec_entries = spec_info->mapEntryCount;
184 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
185 for (uint32_t i = 0; i < num_spec_entries; i++) {
186 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
187 const void *data = spec_info->pData + entry.offset;
188 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
189
190 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
191 spec_entries[i].data = *(const uint32_t *)data;
192 }
193 }
194
195 entry_point = spirv_to_nir(spirv, module->size / 4,
196 spec_entries, num_spec_entries,
197 stage, entrypoint_name, &nir_options);
198 nir = entry_point->shader;
199 assert(nir->stage == stage);
200 nir_validate_shader(nir);
201
202 free(spec_entries);
203
204 nir_lower_returns(nir);
205 nir_validate_shader(nir);
206
207 nir_inline_functions(nir);
208 nir_validate_shader(nir);
209
210 /* Pick off the single entrypoint that we want */
211 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
212 if (func != entry_point)
213 exec_node_remove(&func->node);
214 }
215 assert(exec_list_length(&nir->functions) == 1);
216 entry_point->name = ralloc_strdup(entry_point, "main");
217
218 nir_remove_dead_variables(nir, nir_var_shader_in);
219 nir_remove_dead_variables(nir, nir_var_shader_out);
220 nir_remove_dead_variables(nir, nir_var_system_value);
221 nir_validate_shader(nir);
222
223 nir_lower_system_values(nir);
224 nir_validate_shader(nir);
225 }
226
227 /* Vulkan uses the separate-shader linking model */
228 nir->info->separate_shader = true;
229
230 // nir = brw_preprocess_nir(compiler, nir);
231
232 nir_shader_gather_info(nir, entry_point->impl);
233
234 nir_variable_mode indirect_mask = 0;
235 // if (compiler->glsl_compiler_options[stage].EmitNoIndirectInput)
236 indirect_mask |= nir_var_shader_in;
237 // if (compiler->glsl_compiler_options[stage].EmitNoIndirectTemp)
238 indirect_mask |= nir_var_local;
239
240 nir_lower_indirect_derefs(nir, indirect_mask);
241
242 static const nir_lower_tex_options tex_options = {
243 .lower_txp = ~0,
244 };
245
246 nir_lower_tex(nir, &tex_options);
247
248 nir_lower_vars_to_ssa(nir);
249 nir_lower_var_copies(nir);
250 nir_lower_global_vars_to_local(nir);
251 nir_remove_dead_variables(nir, nir_var_local);
252 radv_optimize_nir(nir);
253
254 if (dump)
255 nir_print_shader(nir, stderr);
256
257 return nir;
258 }
259
260 static const char *radv_get_shader_name(struct radv_shader_variant *var,
261 gl_shader_stage stage)
262 {
263 switch (stage) {
264 case MESA_SHADER_VERTEX: return "Vertex Shader as VS";
265 case MESA_SHADER_FRAGMENT: return "Pixel Shader";
266 case MESA_SHADER_COMPUTE: return "Compute Shader";
267 default:
268 return "Unknown shader";
269 };
270
271 }
272 static void radv_dump_pipeline_stats(struct radv_device *device, struct radv_pipeline *pipeline)
273 {
274 unsigned lds_increment = device->instance->physicalDevice.rad_info.chip_class >= CIK ? 512 : 256;
275 struct radv_shader_variant *var;
276 struct ac_shader_config *conf;
277 int i;
278 FILE *file = stderr;
279 unsigned max_simd_waves = 10;
280 unsigned lds_per_wave = 0;
281
282 for (i = 0; i < MESA_SHADER_STAGES; i++) {
283 if (!pipeline->shaders[i])
284 continue;
285 var = pipeline->shaders[i];
286
287 conf = &var->config;
288
289 if (i == MESA_SHADER_FRAGMENT) {
290 lds_per_wave = conf->lds_size * lds_increment +
291 align(var->info.fs.num_interp * 48, lds_increment);
292 }
293
294 if (conf->num_sgprs) {
295 if (device->instance->physicalDevice.rad_info.chip_class >= VI)
296 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
297 else
298 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
299 }
300
301 if (conf->num_vgprs)
302 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
303
304 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
305 * that PS can use.
306 */
307 if (lds_per_wave)
308 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
309
310 fprintf(file, "\n%s:\n",
311 radv_get_shader_name(var, i));
312 if (i == MESA_SHADER_FRAGMENT) {
313 fprintf(file, "*** SHADER CONFIG ***\n"
314 "SPI_PS_INPUT_ADDR = 0x%04x\n"
315 "SPI_PS_INPUT_ENA = 0x%04x\n",
316 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
317 }
318 fprintf(file, "*** SHADER STATS ***\n"
319 "SGPRS: %d\n"
320 "VGPRS: %d\n"
321 "Spilled SGPRs: %d\n"
322 "Spilled VGPRs: %d\n"
323 "Code Size: %d bytes\n"
324 "LDS: %d blocks\n"
325 "Scratch: %d bytes per wave\n"
326 "Max Waves: %d\n"
327 "********************\n\n\n",
328 conf->num_sgprs, conf->num_vgprs,
329 conf->spilled_sgprs, conf->spilled_vgprs, var->code_size,
330 conf->lds_size, conf->scratch_bytes_per_wave,
331 max_simd_waves);
332 }
333 }
334
335 void radv_shader_variant_destroy(struct radv_device *device,
336 struct radv_shader_variant *variant)
337 {
338 if (__sync_fetch_and_sub(&variant->ref_count, 1) != 1)
339 return;
340
341 device->ws->buffer_destroy(variant->bo);
342 free(variant);
343 }
344
345 static void radv_fill_shader_variant(struct radv_device *device,
346 struct radv_shader_variant *variant,
347 struct ac_shader_binary *binary,
348 gl_shader_stage stage)
349 {
350 variant->code_size = binary->code_size;
351 bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0;
352 unsigned vgpr_comp_cnt = 0;
353
354 if (scratch_enabled)
355 radv_finishme("shader scratch space");
356
357 switch (stage) {
358 case MESA_SHADER_VERTEX:
359 variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
360 S_00B12C_SCRATCH_EN(scratch_enabled);
361 vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
362 break;
363 case MESA_SHADER_FRAGMENT:
364 variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
365 S_00B12C_SCRATCH_EN(scratch_enabled);
366 break;
367 case MESA_SHADER_COMPUTE:
368 variant->rsrc2 = S_00B84C_USER_SGPR(variant->info.num_user_sgprs) |
369 S_00B84C_SCRATCH_EN(scratch_enabled) |
370 S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) |
371 S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) |
372 S_00B84C_TG_SIZE_EN(1) |
373 S_00B84C_LDS_SIZE(variant->config.lds_size);
374 break;
375 default:
376 unreachable("unsupported shader type");
377 break;
378 }
379
380 variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
381 S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) |
382 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
383 S_00B848_DX10_CLAMP(1) |
384 S_00B848_FLOAT_MODE(variant->config.float_mode);
385
386 variant->bo = device->ws->buffer_create(device->ws, binary->code_size, 256,
387 RADEON_DOMAIN_GTT, RADEON_FLAG_CPU_ACCESS);
388
389 void *ptr = device->ws->buffer_map(variant->bo);
390 memcpy(ptr, binary->code, binary->code_size);
391 device->ws->buffer_unmap(variant->bo);
392
393
394 }
395
396 static struct radv_shader_variant *radv_shader_variant_create(struct radv_device *device,
397 struct nir_shader *shader,
398 struct radv_pipeline_layout *layout,
399 const union ac_shader_variant_key *key,
400 void** code_out,
401 unsigned *code_size_out,
402 bool dump)
403 {
404 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
405 enum radeon_family chip_family = device->instance->physicalDevice.rad_info.family;
406 LLVMTargetMachineRef tm;
407 if (!variant)
408 return NULL;
409
410 struct ac_nir_compiler_options options = {0};
411 options.layout = layout;
412 if (key)
413 options.key = *key;
414
415 struct ac_shader_binary binary;
416
417 options.unsafe_math = env_var_as_boolean("RADV_UNSAFE_MATH", false);
418 options.family = chip_family;
419 options.chip_class = device->instance->physicalDevice.rad_info.chip_class;
420 tm = ac_create_target_machine(chip_family);
421 ac_compile_nir_shader(tm, &binary, &variant->config,
422 &variant->info, shader, &options, dump);
423 LLVMDisposeTargetMachine(tm);
424
425 radv_fill_shader_variant(device, variant, &binary, shader->stage);
426
427 if (code_out) {
428 *code_out = binary.code;
429 *code_size_out = binary.code_size;
430 } else
431 free(binary.code);
432 free(binary.config);
433 free(binary.rodata);
434 free(binary.global_symbol_offsets);
435 free(binary.relocs);
436 free(binary.disasm_string);
437 variant->ref_count = 1;
438 return variant;
439 }
440
441
442 static struct radv_shader_variant *
443 radv_pipeline_compile(struct radv_pipeline *pipeline,
444 struct radv_pipeline_cache *cache,
445 struct radv_shader_module *module,
446 const char *entrypoint,
447 gl_shader_stage stage,
448 const VkSpecializationInfo *spec_info,
449 struct radv_pipeline_layout *layout,
450 const union ac_shader_variant_key *key,
451 bool dump)
452 {
453 unsigned char sha1[20];
454 struct radv_shader_variant *variant;
455 nir_shader *nir;
456 void *code = NULL;
457 unsigned code_size = 0;
458
459 if (module->nir)
460 _mesa_sha1_compute(module->nir->info->name,
461 strlen(module->nir->info->name),
462 module->sha1);
463
464 radv_hash_shader(sha1, module, entrypoint, spec_info, layout, key);
465
466 if (cache) {
467 variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
468 cache,
469 sha1);
470 if (variant)
471 return variant;
472 }
473
474 nir = radv_shader_compile_to_nir(pipeline->device,
475 module, entrypoint, stage,
476 spec_info, dump);
477 if (nir == NULL)
478 return NULL;
479
480 variant = radv_shader_variant_create(pipeline->device, nir, layout, key,
481 &code, &code_size, dump);
482 if (!module->nir)
483 ralloc_free(nir);
484
485 if (variant && cache)
486 variant = radv_pipeline_cache_insert_shader(cache, sha1, variant,
487 code, code_size);
488
489 if (code)
490 free(code);
491 return variant;
492 }
493
494 static uint32_t si_translate_blend_function(VkBlendOp op)
495 {
496 switch (op) {
497 case VK_BLEND_OP_ADD:
498 return V_028780_COMB_DST_PLUS_SRC;
499 case VK_BLEND_OP_SUBTRACT:
500 return V_028780_COMB_SRC_MINUS_DST;
501 case VK_BLEND_OP_REVERSE_SUBTRACT:
502 return V_028780_COMB_DST_MINUS_SRC;
503 case VK_BLEND_OP_MIN:
504 return V_028780_COMB_MIN_DST_SRC;
505 case VK_BLEND_OP_MAX:
506 return V_028780_COMB_MAX_DST_SRC;
507 default:
508 return 0;
509 }
510 }
511
512 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
513 {
514 switch (factor) {
515 case VK_BLEND_FACTOR_ZERO:
516 return V_028780_BLEND_ZERO;
517 case VK_BLEND_FACTOR_ONE:
518 return V_028780_BLEND_ONE;
519 case VK_BLEND_FACTOR_SRC_COLOR:
520 return V_028780_BLEND_SRC_COLOR;
521 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
522 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
523 case VK_BLEND_FACTOR_DST_COLOR:
524 return V_028780_BLEND_DST_COLOR;
525 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
526 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
527 case VK_BLEND_FACTOR_SRC_ALPHA:
528 return V_028780_BLEND_SRC_ALPHA;
529 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
530 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
531 case VK_BLEND_FACTOR_DST_ALPHA:
532 return V_028780_BLEND_DST_ALPHA;
533 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
534 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
535 case VK_BLEND_FACTOR_CONSTANT_COLOR:
536 return V_028780_BLEND_CONSTANT_COLOR;
537 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
538 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
539 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
540 return V_028780_BLEND_CONSTANT_ALPHA;
541 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
542 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
543 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
544 return V_028780_BLEND_SRC_ALPHA_SATURATE;
545 case VK_BLEND_FACTOR_SRC1_COLOR:
546 return V_028780_BLEND_SRC1_COLOR;
547 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
548 return V_028780_BLEND_INV_SRC1_COLOR;
549 case VK_BLEND_FACTOR_SRC1_ALPHA:
550 return V_028780_BLEND_SRC1_ALPHA;
551 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
552 return V_028780_BLEND_INV_SRC1_ALPHA;
553 default:
554 return 0;
555 }
556 }
557
558 static bool is_dual_src(VkBlendFactor factor)
559 {
560 switch (factor) {
561 case VK_BLEND_FACTOR_SRC1_COLOR:
562 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
563 case VK_BLEND_FACTOR_SRC1_ALPHA:
564 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
565 return true;
566 default:
567 return false;
568 }
569 }
570
571 static unsigned si_choose_spi_color_format(VkFormat vk_format,
572 bool blend_enable,
573 bool blend_need_alpha)
574 {
575 const struct vk_format_description *desc = vk_format_description(vk_format);
576 unsigned format, ntype, swap;
577
578 /* Alpha is needed for alpha-to-coverage.
579 * Blending may be with or without alpha.
580 */
581 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
582 unsigned alpha = 0; /* exports alpha, but may not support blending */
583 unsigned blend = 0; /* supports blending, but may not export alpha */
584 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
585
586 format = radv_translate_colorformat(vk_format);
587 ntype = radv_translate_color_numformat(vk_format, desc,
588 vk_format_get_first_non_void_channel(vk_format));
589 swap = radv_translate_colorswap(vk_format, false);
590
591 /* Choose the SPI color formats. These are required values for Stoney/RB+.
592 * Other chips have multiple choices, though they are not necessarily better.
593 */
594 switch (format) {
595 case V_028C70_COLOR_5_6_5:
596 case V_028C70_COLOR_1_5_5_5:
597 case V_028C70_COLOR_5_5_5_1:
598 case V_028C70_COLOR_4_4_4_4:
599 case V_028C70_COLOR_10_11_11:
600 case V_028C70_COLOR_11_11_10:
601 case V_028C70_COLOR_8:
602 case V_028C70_COLOR_8_8:
603 case V_028C70_COLOR_8_8_8_8:
604 case V_028C70_COLOR_10_10_10_2:
605 case V_028C70_COLOR_2_10_10_10:
606 if (ntype == V_028C70_NUMBER_UINT)
607 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
608 else if (ntype == V_028C70_NUMBER_SINT)
609 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
610 else
611 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
612 break;
613
614 case V_028C70_COLOR_16:
615 case V_028C70_COLOR_16_16:
616 case V_028C70_COLOR_16_16_16_16:
617 if (ntype == V_028C70_NUMBER_UNORM ||
618 ntype == V_028C70_NUMBER_SNORM) {
619 /* UNORM16 and SNORM16 don't support blending */
620 if (ntype == V_028C70_NUMBER_UNORM)
621 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
622 else
623 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
624
625 /* Use 32 bits per channel for blending. */
626 if (format == V_028C70_COLOR_16) {
627 if (swap == V_028C70_SWAP_STD) { /* R */
628 blend = V_028714_SPI_SHADER_32_R;
629 blend_alpha = V_028714_SPI_SHADER_32_AR;
630 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
631 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
632 else
633 assert(0);
634 } else if (format == V_028C70_COLOR_16_16) {
635 if (swap == V_028C70_SWAP_STD) { /* RG */
636 blend = V_028714_SPI_SHADER_32_GR;
637 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
638 } else if (swap == V_028C70_SWAP_ALT) /* RA */
639 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
640 else
641 assert(0);
642 } else /* 16_16_16_16 */
643 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
644 } else if (ntype == V_028C70_NUMBER_UINT)
645 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
646 else if (ntype == V_028C70_NUMBER_SINT)
647 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
648 else if (ntype == V_028C70_NUMBER_FLOAT)
649 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
650 else
651 assert(0);
652 break;
653
654 case V_028C70_COLOR_32:
655 if (swap == V_028C70_SWAP_STD) { /* R */
656 blend = normal = V_028714_SPI_SHADER_32_R;
657 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
658 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
659 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
660 else
661 assert(0);
662 break;
663
664 case V_028C70_COLOR_32_32:
665 if (swap == V_028C70_SWAP_STD) { /* RG */
666 blend = normal = V_028714_SPI_SHADER_32_GR;
667 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
668 } else if (swap == V_028C70_SWAP_ALT) /* RA */
669 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
670 else
671 assert(0);
672 break;
673
674 case V_028C70_COLOR_32_32_32_32:
675 case V_028C70_COLOR_8_24:
676 case V_028C70_COLOR_24_8:
677 case V_028C70_COLOR_X24_8_32_FLOAT:
678 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
679 break;
680
681 default:
682 unreachable("unhandled blend format");
683 }
684
685 if (blend_enable && blend_need_alpha)
686 return blend_alpha;
687 else if(blend_need_alpha)
688 return alpha;
689 else if(blend_enable)
690 return blend;
691 else
692 return normal;
693 }
694
695 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
696 {
697 unsigned i, cb_shader_mask = 0;
698
699 for (i = 0; i < 8; i++) {
700 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
701 case V_028714_SPI_SHADER_ZERO:
702 break;
703 case V_028714_SPI_SHADER_32_R:
704 cb_shader_mask |= 0x1 << (i * 4);
705 break;
706 case V_028714_SPI_SHADER_32_GR:
707 cb_shader_mask |= 0x3 << (i * 4);
708 break;
709 case V_028714_SPI_SHADER_32_AR:
710 cb_shader_mask |= 0x9 << (i * 4);
711 break;
712 case V_028714_SPI_SHADER_FP16_ABGR:
713 case V_028714_SPI_SHADER_UNORM16_ABGR:
714 case V_028714_SPI_SHADER_SNORM16_ABGR:
715 case V_028714_SPI_SHADER_UINT16_ABGR:
716 case V_028714_SPI_SHADER_SINT16_ABGR:
717 case V_028714_SPI_SHADER_32_ABGR:
718 cb_shader_mask |= 0xf << (i * 4);
719 break;
720 default:
721 assert(0);
722 }
723 }
724 return cb_shader_mask;
725 }
726
727 static void
728 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
729 const VkGraphicsPipelineCreateInfo *pCreateInfo,
730 uint32_t blend_enable,
731 uint32_t blend_need_alpha,
732 bool single_cb_enable,
733 bool blend_mrt0_is_dual_src)
734 {
735 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
736 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
737 struct radv_blend_state *blend = &pipeline->graphics.blend;
738 unsigned col_format = 0;
739
740 for (unsigned i = 0; i < (single_cb_enable ? 1 : subpass->color_count); ++i) {
741 struct radv_render_pass_attachment *attachment;
742 unsigned cf;
743
744 attachment = pass->attachments + subpass->color_attachments[i].attachment;
745
746 cf = si_choose_spi_color_format(attachment->format,
747 blend_enable & (1 << i),
748 blend_need_alpha & (1 << i));
749
750 col_format |= cf << (4 * i);
751 }
752
753 blend->cb_shader_mask = si_get_cb_shader_mask(col_format);
754
755 if (blend_mrt0_is_dual_src)
756 col_format |= (col_format & 0xf) << 4;
757 if (!col_format)
758 col_format |= V_028714_SPI_SHADER_32_R;
759 blend->spi_shader_col_format = col_format;
760 }
761
762 static bool
763 format_is_int8(VkFormat format)
764 {
765 const struct vk_format_description *desc = vk_format_description(format);
766 int channel = vk_format_get_first_non_void_channel(format);
767
768 return channel >= 0 && desc->channel[channel].pure_integer &&
769 desc->channel[channel].size == 8;
770 }
771
772 unsigned radv_format_meta_fs_key(VkFormat format)
773 {
774 unsigned col_format = si_choose_spi_color_format(format, false, false) - 1;
775 bool is_int8 = format_is_int8(format);
776
777 return col_format + (is_int8 ? 3 : 0);
778 }
779
780 static unsigned
781 radv_pipeline_compute_is_int8(const VkGraphicsPipelineCreateInfo *pCreateInfo)
782 {
783 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
784 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
785 unsigned is_int8 = 0;
786
787 for (unsigned i = 0; i < subpass->color_count; ++i) {
788 struct radv_render_pass_attachment *attachment;
789
790 attachment = pass->attachments + subpass->color_attachments[i].attachment;
791
792 if (format_is_int8(attachment->format))
793 is_int8 |= 1 << i;
794 }
795
796 return is_int8;
797 }
798
799 static void
800 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
801 const VkGraphicsPipelineCreateInfo *pCreateInfo,
802 const struct radv_graphics_pipeline_create_info *extra)
803 {
804 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
805 struct radv_blend_state *blend = &pipeline->graphics.blend;
806 unsigned mode = V_028808_CB_NORMAL;
807 uint32_t blend_enable = 0, blend_need_alpha = 0;
808 bool blend_mrt0_is_dual_src = false;
809 int i;
810 bool single_cb_enable = false;
811
812 if (!vkblend)
813 return;
814
815 if (extra && extra->custom_blend_mode) {
816 single_cb_enable = true;
817 mode = extra->custom_blend_mode;
818 }
819 blend->cb_color_control = 0;
820 if (vkblend->logicOpEnable)
821 blend->cb_color_control |= S_028808_ROP3(vkblend->logicOp | (vkblend->logicOp << 4));
822 else
823 blend->cb_color_control |= S_028808_ROP3(0xcc);
824
825 blend->db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
826 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
827 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
828 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
829
830 blend->cb_target_mask = 0;
831 for (i = 0; i < vkblend->attachmentCount; i++) {
832 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
833 unsigned blend_cntl = 0;
834 VkBlendOp eqRGB = att->colorBlendOp;
835 VkBlendFactor srcRGB = att->srcColorBlendFactor;
836 VkBlendFactor dstRGB = att->dstColorBlendFactor;
837 VkBlendOp eqA = att->alphaBlendOp;
838 VkBlendFactor srcA = att->srcAlphaBlendFactor;
839 VkBlendFactor dstA = att->dstAlphaBlendFactor;
840
841 blend->sx_mrt0_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
842
843 if (!att->colorWriteMask)
844 continue;
845
846 blend->cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
847 if (!att->blendEnable) {
848 blend->cb_blend_control[i] = blend_cntl;
849 continue;
850 }
851
852 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
853 if (i == 0)
854 blend_mrt0_is_dual_src = true;
855
856 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
857 srcRGB = VK_BLEND_FACTOR_ONE;
858 dstRGB = VK_BLEND_FACTOR_ONE;
859 }
860 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
861 srcA = VK_BLEND_FACTOR_ONE;
862 dstA = VK_BLEND_FACTOR_ONE;
863 }
864
865 blend_cntl |= S_028780_ENABLE(1);
866
867 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
868 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
869 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
870 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
871 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
872 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
873 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
874 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
875 }
876 blend->cb_blend_control[i] = blend_cntl;
877
878 blend_enable |= 1 << i;
879
880 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
881 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
882 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
883 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
884 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
885 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
886 blend_need_alpha |= 1 << i;
887 }
888 for (i = vkblend->attachmentCount; i < 8; i++)
889 blend->cb_blend_control[i] = 0;
890
891 if (blend->cb_target_mask)
892 blend->cb_color_control |= S_028808_MODE(mode);
893 else
894 blend->cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
895
896 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo,
897 blend_enable, blend_need_alpha, single_cb_enable, blend_mrt0_is_dual_src);
898 }
899
900 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
901 {
902 switch (op) {
903 case VK_STENCIL_OP_KEEP:
904 return V_02842C_STENCIL_KEEP;
905 case VK_STENCIL_OP_ZERO:
906 return V_02842C_STENCIL_ZERO;
907 case VK_STENCIL_OP_REPLACE:
908 return V_02842C_STENCIL_REPLACE_TEST;
909 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
910 return V_02842C_STENCIL_ADD_CLAMP;
911 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
912 return V_02842C_STENCIL_SUB_CLAMP;
913 case VK_STENCIL_OP_INVERT:
914 return V_02842C_STENCIL_INVERT;
915 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
916 return V_02842C_STENCIL_ADD_WRAP;
917 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
918 return V_02842C_STENCIL_SUB_WRAP;
919 default:
920 return 0;
921 }
922 }
923 static void
924 radv_pipeline_init_depth_stencil_state(struct radv_pipeline *pipeline,
925 const VkGraphicsPipelineCreateInfo *pCreateInfo,
926 const struct radv_graphics_pipeline_create_info *extra)
927 {
928 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
929 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
930
931 memset(ds, 0, sizeof(*ds));
932 if (!vkds)
933 return;
934 ds->db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
935 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
936 S_028800_ZFUNC(vkds->depthCompareOp) |
937 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
938
939 if (vkds->stencilTestEnable) {
940 ds->db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
941 ds->db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
942 ds->db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
943 ds->db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
944 ds->db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
945
946 ds->db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
947 ds->db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
948 ds->db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
949 ds->db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
950 }
951
952 if (extra) {
953
954 ds->db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
955 ds->db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
956
957 ds->db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
958 ds->db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
959 ds->db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
960 ds->db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
961 ds->db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
962 }
963 }
964
965 static uint32_t si_translate_fill(VkPolygonMode func)
966 {
967 switch(func) {
968 case VK_POLYGON_MODE_FILL:
969 return V_028814_X_DRAW_TRIANGLES;
970 case VK_POLYGON_MODE_LINE:
971 return V_028814_X_DRAW_LINES;
972 case VK_POLYGON_MODE_POINT:
973 return V_028814_X_DRAW_POINTS;
974 default:
975 assert(0);
976 return V_028814_X_DRAW_POINTS;
977 }
978 }
979 static void
980 radv_pipeline_init_raster_state(struct radv_pipeline *pipeline,
981 const VkGraphicsPipelineCreateInfo *pCreateInfo)
982 {
983 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
984 struct radv_raster_state *raster = &pipeline->graphics.raster;
985
986 memset(raster, 0, sizeof(*raster));
987
988 raster->spi_interp_control =
989 S_0286D4_FLAT_SHADE_ENA(1) |
990 S_0286D4_PNT_SPRITE_ENA(1) |
991 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
992 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
993 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
994 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
995 S_0286D4_PNT_SPRITE_TOP_1(0); // vulkan is top to bottom - 1.0 at bottom
996
997 raster->pa_cl_vs_out_cntl = S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1);
998 raster->pa_cl_clip_cntl = S_028810_PS_UCP_MODE(3) |
999 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
1000 S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1001 S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1002 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
1003 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
1004
1005 raster->pa_su_vtx_cntl =
1006 S_028BE4_PIX_CENTER(1) | // TODO verify
1007 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
1008 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH);
1009
1010 raster->pa_su_sc_mode_cntl =
1011 S_028814_FACE(vkraster->frontFace) |
1012 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
1013 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
1014 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
1015 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1016 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1017 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1018 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1019 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0);
1020
1021 }
1022
1023 static void
1024 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1025 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1026 {
1027 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
1028 struct radv_blend_state *blend = &pipeline->graphics.blend;
1029 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1030 unsigned num_tile_pipes = pipeline->device->instance->physicalDevice.rad_info.num_tile_pipes;
1031 int ps_iter_samples = 1;
1032 uint32_t mask = 0xffff;
1033
1034 ms->num_samples = vkms->rasterizationSamples;
1035
1036 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.force_persample) {
1037 ps_iter_samples = vkms->rasterizationSamples;
1038 }
1039
1040 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1041 ms->pa_sc_aa_config = 0;
1042 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1043 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1044 ms->pa_sc_mode_cntl_1 =
1045 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1046 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1047 /* always 1: */
1048 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1049 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1050 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1051 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1052 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1053 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1054
1055 if (vkms->rasterizationSamples > 1) {
1056 unsigned log_samples = util_logbase2(vkms->rasterizationSamples);
1057 unsigned log_ps_iter_samples = util_logbase2(util_next_power_of_two(ps_iter_samples));
1058 ms->pa_sc_mode_cntl_0 = S_028A48_MSAA_ENABLE(1);
1059 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1060 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1061 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1062 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1063 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1064 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1065 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
1066 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1067 ms->pa_sc_mode_cntl_1 |= EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1068 }
1069
1070 if (vkms->alphaToCoverageEnable)
1071 blend->db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
1072
1073 if (vkms->pSampleMask) {
1074 mask = vkms->pSampleMask[0] & 0xffff;
1075 }
1076
1077 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1078 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1079 }
1080
1081 static uint32_t
1082 si_translate_prim(enum VkPrimitiveTopology topology)
1083 {
1084 switch (topology) {
1085 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1086 return V_008958_DI_PT_POINTLIST;
1087 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1088 return V_008958_DI_PT_LINELIST;
1089 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1090 return V_008958_DI_PT_LINESTRIP;
1091 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1092 return V_008958_DI_PT_TRILIST;
1093 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1094 return V_008958_DI_PT_TRISTRIP;
1095 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1096 return V_008958_DI_PT_TRIFAN;
1097 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1098 return V_008958_DI_PT_LINELIST_ADJ;
1099 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1100 return V_008958_DI_PT_LINESTRIP_ADJ;
1101 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1102 return V_008958_DI_PT_TRILIST_ADJ;
1103 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1104 return V_008958_DI_PT_TRISTRIP_ADJ;
1105 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1106 return V_008958_DI_PT_PATCH;
1107 default:
1108 assert(0);
1109 return 0;
1110 }
1111 }
1112
1113 static uint32_t
1114 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1115 {
1116 switch (topology) {
1117 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1118 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1119 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1120 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1121 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1122 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1123 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1124 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1125 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1126 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1127 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1128 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1129 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1130 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1131 default:
1132 assert(0);
1133 return 0;
1134 }
1135 }
1136
1137 static unsigned si_map_swizzle(unsigned swizzle)
1138 {
1139 switch (swizzle) {
1140 case VK_SWIZZLE_Y:
1141 return V_008F0C_SQ_SEL_Y;
1142 case VK_SWIZZLE_Z:
1143 return V_008F0C_SQ_SEL_Z;
1144 case VK_SWIZZLE_W:
1145 return V_008F0C_SQ_SEL_W;
1146 case VK_SWIZZLE_0:
1147 return V_008F0C_SQ_SEL_0;
1148 case VK_SWIZZLE_1:
1149 return V_008F0C_SQ_SEL_1;
1150 default: /* VK_SWIZZLE_X */
1151 return V_008F0C_SQ_SEL_X;
1152 }
1153 }
1154
1155 static void
1156 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1157 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1158 {
1159 radv_cmd_dirty_mask_t states = RADV_CMD_DIRTY_DYNAMIC_ALL;
1160 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1161 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1162
1163 pipeline->dynamic_state = default_dynamic_state;
1164
1165 if (pCreateInfo->pDynamicState) {
1166 /* Remove all of the states that are marked as dynamic */
1167 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1168 for (uint32_t s = 0; s < count; s++)
1169 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
1170 }
1171
1172 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1173
1174 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1175 *
1176 * pViewportState is [...] NULL if the pipeline
1177 * has rasterization disabled.
1178 */
1179 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1180 assert(pCreateInfo->pViewportState);
1181
1182 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1183 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
1184 typed_memcpy(dynamic->viewport.viewports,
1185 pCreateInfo->pViewportState->pViewports,
1186 pCreateInfo->pViewportState->viewportCount);
1187 }
1188
1189 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1190 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
1191 typed_memcpy(dynamic->scissor.scissors,
1192 pCreateInfo->pViewportState->pScissors,
1193 pCreateInfo->pViewportState->scissorCount);
1194 }
1195 }
1196
1197 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
1198 assert(pCreateInfo->pRasterizationState);
1199 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1200 }
1201
1202 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
1203 assert(pCreateInfo->pRasterizationState);
1204 dynamic->depth_bias.bias =
1205 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1206 dynamic->depth_bias.clamp =
1207 pCreateInfo->pRasterizationState->depthBiasClamp;
1208 dynamic->depth_bias.slope =
1209 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1210 }
1211
1212 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1213 *
1214 * pColorBlendState is [...] NULL if the pipeline has rasterization
1215 * disabled or if the subpass of the render pass the pipeline is
1216 * created against does not use any color attachments.
1217 */
1218 bool uses_color_att = false;
1219 for (unsigned i = 0; i < subpass->color_count; ++i) {
1220 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1221 uses_color_att = true;
1222 break;
1223 }
1224 }
1225
1226 if (uses_color_att && states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
1227 assert(pCreateInfo->pColorBlendState);
1228 typed_memcpy(dynamic->blend_constants,
1229 pCreateInfo->pColorBlendState->blendConstants, 4);
1230 }
1231
1232 /* If there is no depthstencil attachment, then don't read
1233 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1234 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1235 * no need to override the depthstencil defaults in
1236 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1237 *
1238 * Section 9.2 of the Vulkan 1.0.15 spec says:
1239 *
1240 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1241 * disabled or if the subpass of the render pass the pipeline is created
1242 * against does not use a depth/stencil attachment.
1243 */
1244 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
1245 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1246 assert(pCreateInfo->pDepthStencilState);
1247
1248 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
1249 dynamic->depth_bounds.min =
1250 pCreateInfo->pDepthStencilState->minDepthBounds;
1251 dynamic->depth_bounds.max =
1252 pCreateInfo->pDepthStencilState->maxDepthBounds;
1253 }
1254
1255 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
1256 dynamic->stencil_compare_mask.front =
1257 pCreateInfo->pDepthStencilState->front.compareMask;
1258 dynamic->stencil_compare_mask.back =
1259 pCreateInfo->pDepthStencilState->back.compareMask;
1260 }
1261
1262 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
1263 dynamic->stencil_write_mask.front =
1264 pCreateInfo->pDepthStencilState->front.writeMask;
1265 dynamic->stencil_write_mask.back =
1266 pCreateInfo->pDepthStencilState->back.writeMask;
1267 }
1268
1269 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
1270 dynamic->stencil_reference.front =
1271 pCreateInfo->pDepthStencilState->front.reference;
1272 dynamic->stencil_reference.back =
1273 pCreateInfo->pDepthStencilState->back.reference;
1274 }
1275 }
1276
1277 pipeline->dynamic_state_mask = states;
1278 }
1279
1280 static union ac_shader_variant_key
1281 radv_compute_vs_key(const VkGraphicsPipelineCreateInfo *pCreateInfo)
1282 {
1283 union ac_shader_variant_key key;
1284 const VkPipelineVertexInputStateCreateInfo *input_state =
1285 pCreateInfo->pVertexInputState;
1286
1287 memset(&key, 0, sizeof(key));
1288 key.vs.instance_rate_inputs = 0;
1289
1290 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
1291 unsigned binding;
1292 binding = input_state->pVertexAttributeDescriptions[i].binding;
1293 if (input_state->pVertexBindingDescriptions[binding].inputRate)
1294 key.vs.instance_rate_inputs |= 1u << input_state->pVertexAttributeDescriptions[i].location;
1295 }
1296 return key;
1297 }
1298
1299 VkResult
1300 radv_pipeline_init(struct radv_pipeline *pipeline,
1301 struct radv_device *device,
1302 struct radv_pipeline_cache *cache,
1303 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1304 const struct radv_graphics_pipeline_create_info *extra,
1305 const VkAllocationCallbacks *alloc)
1306 {
1307 struct radv_shader_module fs_m = {0};
1308
1309 bool dump = getenv("RADV_DUMP_SHADERS");
1310 if (alloc == NULL)
1311 alloc = &device->alloc;
1312
1313 pipeline->device = device;
1314 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
1315
1316 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
1317 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
1318 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
1319 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
1320 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
1321 pStages[stage] = &pCreateInfo->pStages[i];
1322 modules[stage] = radv_shader_module_from_handle(pStages[stage]->module);
1323 }
1324
1325 radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
1326
1327 /* */
1328 if (modules[MESA_SHADER_VERTEX]) {
1329 union ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo);
1330
1331 pipeline->shaders[MESA_SHADER_VERTEX] =
1332 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_VERTEX],
1333 pStages[MESA_SHADER_VERTEX]->pName,
1334 MESA_SHADER_VERTEX,
1335 pStages[MESA_SHADER_VERTEX]->pSpecializationInfo,
1336 pipeline->layout, &key, dump);
1337
1338 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_VERTEX);
1339 }
1340
1341 if (!modules[MESA_SHADER_FRAGMENT]) {
1342 nir_builder fs_b;
1343 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
1344 fs_b.shader->info->name = ralloc_strdup(fs_b.shader, "noop_fs");
1345 fs_m.nir = fs_b.shader;
1346 modules[MESA_SHADER_FRAGMENT] = &fs_m;
1347 }
1348
1349 if (modules[MESA_SHADER_FRAGMENT]) {
1350 union ac_shader_variant_key key;
1351 key.fs.col_format = pipeline->graphics.blend.spi_shader_col_format;
1352 key.fs.is_int8 = radv_pipeline_compute_is_int8(pCreateInfo);
1353
1354 const VkPipelineShaderStageCreateInfo *stage = pStages[MESA_SHADER_FRAGMENT];
1355
1356 pipeline->shaders[MESA_SHADER_FRAGMENT] =
1357 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_FRAGMENT],
1358 stage ? stage->pName : "main",
1359 MESA_SHADER_FRAGMENT,
1360 stage ? stage->pSpecializationInfo : NULL,
1361 pipeline->layout, &key, dump);
1362 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_FRAGMENT);
1363 }
1364
1365 if (fs_m.nir)
1366 ralloc_free(fs_m.nir);
1367
1368 radv_pipeline_init_depth_stencil_state(pipeline, pCreateInfo, extra);
1369 radv_pipeline_init_raster_state(pipeline, pCreateInfo);
1370 radv_pipeline_init_multisample_state(pipeline, pCreateInfo);
1371 pipeline->graphics.prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
1372 pipeline->graphics.gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
1373 if (extra && extra->use_rectlist) {
1374 pipeline->graphics.prim = V_008958_DI_PT_RECTLIST;
1375 pipeline->graphics.gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1376 }
1377 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
1378
1379 const VkPipelineVertexInputStateCreateInfo *vi_info =
1380 pCreateInfo->pVertexInputState;
1381 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
1382 const VkVertexInputAttributeDescription *desc =
1383 &vi_info->pVertexAttributeDescriptions[i];
1384 unsigned loc = desc->location;
1385 const struct vk_format_description *format_desc;
1386 int first_non_void;
1387 uint32_t num_format, data_format;
1388 format_desc = vk_format_description(desc->format);
1389 first_non_void = vk_format_get_first_non_void_channel(desc->format);
1390
1391 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
1392 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
1393
1394 pipeline->va_rsrc_word3[loc] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc->swizzle[0])) |
1395 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc->swizzle[1])) |
1396 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc->swizzle[2])) |
1397 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc->swizzle[3])) |
1398 S_008F0C_NUM_FORMAT(num_format) |
1399 S_008F0C_DATA_FORMAT(data_format);
1400 pipeline->va_format_size[loc] = format_desc->block.bits / 8;
1401 pipeline->va_offset[loc] = desc->offset;
1402 pipeline->va_binding[loc] = desc->binding;
1403 pipeline->num_vertex_attribs = MAX2(pipeline->num_vertex_attribs, loc + 1);
1404 }
1405
1406 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
1407 const VkVertexInputBindingDescription *desc =
1408 &vi_info->pVertexBindingDescriptions[i];
1409
1410 pipeline->binding_stride[desc->binding] = desc->stride;
1411 }
1412
1413 if (device->shader_stats_dump) {
1414 radv_dump_pipeline_stats(device, pipeline);
1415 }
1416
1417 return VK_SUCCESS;
1418 }
1419
1420 VkResult
1421 radv_graphics_pipeline_create(
1422 VkDevice _device,
1423 VkPipelineCache _cache,
1424 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1425 const struct radv_graphics_pipeline_create_info *extra,
1426 const VkAllocationCallbacks *pAllocator,
1427 VkPipeline *pPipeline)
1428 {
1429 RADV_FROM_HANDLE(radv_device, device, _device);
1430 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
1431 struct radv_pipeline *pipeline;
1432 VkResult result;
1433
1434 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
1435 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1436 if (pipeline == NULL)
1437 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1438
1439 memset(pipeline, 0, sizeof(*pipeline));
1440 result = radv_pipeline_init(pipeline, device, cache,
1441 pCreateInfo, extra, pAllocator);
1442 if (result != VK_SUCCESS) {
1443 vk_free2(&device->alloc, pAllocator, pipeline);
1444 return result;
1445 }
1446
1447 *pPipeline = radv_pipeline_to_handle(pipeline);
1448
1449 return VK_SUCCESS;
1450 }
1451
1452 VkResult radv_CreateGraphicsPipelines(
1453 VkDevice _device,
1454 VkPipelineCache pipelineCache,
1455 uint32_t count,
1456 const VkGraphicsPipelineCreateInfo* pCreateInfos,
1457 const VkAllocationCallbacks* pAllocator,
1458 VkPipeline* pPipelines)
1459 {
1460 VkResult result = VK_SUCCESS;
1461 unsigned i = 0;
1462
1463 for (; i < count; i++) {
1464 VkResult r;
1465 r = radv_graphics_pipeline_create(_device,
1466 pipelineCache,
1467 &pCreateInfos[i],
1468 NULL, pAllocator, &pPipelines[i]);
1469 if (r != VK_SUCCESS) {
1470 result = r;
1471 pPipelines[i] = VK_NULL_HANDLE;
1472 }
1473 }
1474
1475 return result;
1476 }
1477
1478 static VkResult radv_compute_pipeline_create(
1479 VkDevice _device,
1480 VkPipelineCache _cache,
1481 const VkComputePipelineCreateInfo* pCreateInfo,
1482 const VkAllocationCallbacks* pAllocator,
1483 VkPipeline* pPipeline)
1484 {
1485 RADV_FROM_HANDLE(radv_device, device, _device);
1486 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
1487 RADV_FROM_HANDLE(radv_shader_module, module, pCreateInfo->stage.module);
1488 struct radv_pipeline *pipeline;
1489 bool dump = getenv("RADV_DUMP_SHADERS");
1490
1491 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
1492 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1493 if (pipeline == NULL)
1494 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1495
1496 memset(pipeline, 0, sizeof(*pipeline));
1497 pipeline->device = device;
1498 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
1499
1500 pipeline->shaders[MESA_SHADER_COMPUTE] =
1501 radv_pipeline_compile(pipeline, cache, module,
1502 pCreateInfo->stage.pName,
1503 MESA_SHADER_COMPUTE,
1504 pCreateInfo->stage.pSpecializationInfo,
1505 pipeline->layout, NULL, dump);
1506
1507 *pPipeline = radv_pipeline_to_handle(pipeline);
1508
1509 if (device->shader_stats_dump) {
1510 radv_dump_pipeline_stats(device, pipeline);
1511 }
1512 return VK_SUCCESS;
1513 }
1514 VkResult radv_CreateComputePipelines(
1515 VkDevice _device,
1516 VkPipelineCache pipelineCache,
1517 uint32_t count,
1518 const VkComputePipelineCreateInfo* pCreateInfos,
1519 const VkAllocationCallbacks* pAllocator,
1520 VkPipeline* pPipelines)
1521 {
1522 VkResult result = VK_SUCCESS;
1523
1524 unsigned i = 0;
1525 for (; i < count; i++) {
1526 VkResult r;
1527 r = radv_compute_pipeline_create(_device, pipelineCache,
1528 &pCreateInfos[i],
1529 pAllocator, &pPipelines[i]);
1530 if (r != VK_SUCCESS) {
1531 result = r;
1532 pPipelines[i] = VK_NULL_HANDLE;
1533 }
1534 }
1535
1536 return result;
1537 }