projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv/gfx10: compute the LDS size for exporting PrimID for VS
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_cs.h"
33 #include "radv_shader.h"
34 #include "nir/nir.h"
35 #include "nir/nir_builder.h"
36 #include "nir/nir_xfb_info.h"
37 #include "spirv/nir_spirv.h"
38 #include "vk_util.h"
39
40 #include <llvm-c/Core.h>
41 #include <llvm-c/TargetMachine.h>
42
43 #include "sid.h"
44 #include "ac_binary.h"
45 #include "ac_llvm_util.h"
46 #include "ac_nir_to_llvm.h"
47 #include "vk_format.h"
48 #include "util/debug.h"
49 #include "ac_exp_param.h"
50 #include "ac_shader_util.h"
51 #include "main/menums.h"
52
53 struct radv_blend_state {
54 uint32_t blend_enable_4bit;
55 uint32_t need_src_alpha;
56
57 uint32_t cb_color_control;
58 uint32_t cb_target_mask;
59 uint32_t cb_target_enabled_4bit;
60 uint32_t sx_mrt_blend_opt[8];
61 uint32_t cb_blend_control[8];
62
63 uint32_t spi_shader_col_format;
64 uint32_t cb_shader_mask;
65 uint32_t db_alpha_to_mask;
66
67 uint32_t commutative_4bit;
68
69 bool single_cb_enable;
70 bool mrt0_is_dual_src;
71 };
72
73 struct radv_dsa_order_invariance {
74 /* Whether the final result in Z/S buffers is guaranteed to be
75 * invariant under changes to the order in which fragments arrive.
76 */
77 bool zs;
78
79 /* Whether the set of fragments that pass the combined Z/S test is
80 * guaranteed to be invariant under changes to the order in which
81 * fragments arrive.
82 */
83 bool pass_set;
84 };
85
86 struct radv_tessellation_state {
87 uint32_t ls_hs_config;
88 unsigned num_patches;
89 unsigned lds_size;
90 uint32_t tf_param;
91 };
92
93 struct radv_gs_state {
94 uint32_t vgt_gs_onchip_cntl;
95 uint32_t vgt_gs_max_prims_per_subgroup;
96 uint32_t vgt_esgs_ring_itemsize;
97 uint32_t lds_size;
98 };
99
100 struct radv_ngg_state {
101 uint16_t ngg_emit_size; /* in dwords */
102 uint32_t hw_max_esverts;
103 uint32_t max_gsprims;
104 uint32_t max_out_verts;
105 uint32_t prim_amp_factor;
106 uint32_t vgt_esgs_ring_itemsize;
107 bool max_vert_out_per_gs_instance;
108 };
109
110 bool radv_pipeline_has_ngg(const struct radv_pipeline *pipeline)
111 {
112 struct radv_shader_variant *variant = NULL;
113 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
114 variant = pipeline->shaders[MESA_SHADER_GEOMETRY];
115 else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
116 variant = pipeline->shaders[MESA_SHADER_TESS_EVAL];
117 else if (pipeline->shaders[MESA_SHADER_VERTEX])
118 variant = pipeline->shaders[MESA_SHADER_VERTEX];
119 else
120 return false;
121 return variant->info.is_ngg;
122 }
123
124 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline *pipeline)
125 {
126 if (!radv_pipeline_has_gs(pipeline))
127 return false;
128
129 /* The GS copy shader is required if the pipeline has GS on GFX6-GFX9.
130 * On GFX10, it might be required in rare cases if it's not possible to
131 * enable NGG.
132 */
133 if (radv_pipeline_has_ngg(pipeline))
134 return false;
135
136 assert(pipeline->gs_copy_shader);
137 return true;
138 }
139
140 static void
141 radv_pipeline_destroy(struct radv_device *device,
142 struct radv_pipeline *pipeline,
143 const VkAllocationCallbacks* allocator)
144 {
145 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
146 if (pipeline->shaders[i])
147 radv_shader_variant_destroy(device, pipeline->shaders[i]);
148
149 if (pipeline->gs_copy_shader)
150 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
151
152 if(pipeline->cs.buf)
153 free(pipeline->cs.buf);
154 vk_free2(&device->alloc, allocator, pipeline);
155 }
156
157 void radv_DestroyPipeline(
158 VkDevice _device,
159 VkPipeline _pipeline,
160 const VkAllocationCallbacks* pAllocator)
161 {
162 RADV_FROM_HANDLE(radv_device, device, _device);
163 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
164
165 if (!_pipeline)
166 return;
167
168 radv_pipeline_destroy(device, pipeline, pAllocator);
169 }
170
171 static uint32_t get_hash_flags(struct radv_device *device)
172 {
173 uint32_t hash_flags = 0;
174
175 if (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH)
176 hash_flags |= RADV_HASH_SHADER_UNSAFE_MATH;
177 if (device->instance->debug_flags & RADV_DEBUG_NO_NGG)
178 hash_flags |= RADV_HASH_SHADER_NO_NGG;
179 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
180 hash_flags |= RADV_HASH_SHADER_SISCHED;
181 if (device->physical_device->cs_wave_size == 32)
182 hash_flags |= RADV_HASH_SHADER_CS_WAVE32;
183 if (device->physical_device->ps_wave_size == 32)
184 hash_flags |= RADV_HASH_SHADER_PS_WAVE32;
185 if (device->physical_device->ge_wave_size == 32)
186 hash_flags |= RADV_HASH_SHADER_GE_WAVE32;
187 return hash_flags;
188 }
189
190 static VkResult
191 radv_pipeline_scratch_init(struct radv_device *device,
192 struct radv_pipeline *pipeline)
193 {
194 unsigned scratch_bytes_per_wave = 0;
195 unsigned max_waves = 0;
196 unsigned min_waves = 1;
197
198 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
199 if (pipeline->shaders[i]) {
200 unsigned max_stage_waves = device->scratch_waves;
201
202 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
203 pipeline->shaders[i]->config.scratch_bytes_per_wave);
204
205 max_stage_waves = MIN2(max_stage_waves,
206 4 * device->physical_device->rad_info.num_good_compute_units *
207 (256 / pipeline->shaders[i]->config.num_vgprs));
208 max_waves = MAX2(max_waves, max_stage_waves);
209 }
210 }
211
212 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
213 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
214 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
215 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
216 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
217 }
218
219 if (scratch_bytes_per_wave)
220 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
221
222 if (scratch_bytes_per_wave && max_waves < min_waves) {
223 /* Not really true at this moment, but will be true on first
224 * execution. Avoid having hanging shaders. */
225 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
226 }
227 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
228 pipeline->max_waves = max_waves;
229 return VK_SUCCESS;
230 }
231
232 static uint32_t si_translate_blend_logic_op(VkLogicOp op)
233 {
234 switch (op) {
235 case VK_LOGIC_OP_CLEAR:
236 return V_028808_ROP3_CLEAR;
237 case VK_LOGIC_OP_AND:
238 return V_028808_ROP3_AND;
239 case VK_LOGIC_OP_AND_REVERSE:
240 return V_028808_ROP3_AND_REVERSE;
241 case VK_LOGIC_OP_COPY:
242 return V_028808_ROP3_COPY;
243 case VK_LOGIC_OP_AND_INVERTED:
244 return V_028808_ROP3_AND_INVERTED;
245 case VK_LOGIC_OP_NO_OP:
246 return V_028808_ROP3_NO_OP;
247 case VK_LOGIC_OP_XOR:
248 return V_028808_ROP3_XOR;
249 case VK_LOGIC_OP_OR:
250 return V_028808_ROP3_OR;
251 case VK_LOGIC_OP_NOR:
252 return V_028808_ROP3_NOR;
253 case VK_LOGIC_OP_EQUIVALENT:
254 return V_028808_ROP3_EQUIVALENT;
255 case VK_LOGIC_OP_INVERT:
256 return V_028808_ROP3_INVERT;
257 case VK_LOGIC_OP_OR_REVERSE:
258 return V_028808_ROP3_OR_REVERSE;
259 case VK_LOGIC_OP_COPY_INVERTED:
260 return V_028808_ROP3_COPY_INVERTED;
261 case VK_LOGIC_OP_OR_INVERTED:
262 return V_028808_ROP3_OR_INVERTED;
263 case VK_LOGIC_OP_NAND:
264 return V_028808_ROP3_NAND;
265 case VK_LOGIC_OP_SET:
266 return V_028808_ROP3_SET;
267 default:
268 unreachable("Unhandled logic op");
269 }
270 }
271
272
273 static uint32_t si_translate_blend_function(VkBlendOp op)
274 {
275 switch (op) {
276 case VK_BLEND_OP_ADD:
277 return V_028780_COMB_DST_PLUS_SRC;
278 case VK_BLEND_OP_SUBTRACT:
279 return V_028780_COMB_SRC_MINUS_DST;
280 case VK_BLEND_OP_REVERSE_SUBTRACT:
281 return V_028780_COMB_DST_MINUS_SRC;
282 case VK_BLEND_OP_MIN:
283 return V_028780_COMB_MIN_DST_SRC;
284 case VK_BLEND_OP_MAX:
285 return V_028780_COMB_MAX_DST_SRC;
286 default:
287 return 0;
288 }
289 }
290
291 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
292 {
293 switch (factor) {
294 case VK_BLEND_FACTOR_ZERO:
295 return V_028780_BLEND_ZERO;
296 case VK_BLEND_FACTOR_ONE:
297 return V_028780_BLEND_ONE;
298 case VK_BLEND_FACTOR_SRC_COLOR:
299 return V_028780_BLEND_SRC_COLOR;
300 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
301 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
302 case VK_BLEND_FACTOR_DST_COLOR:
303 return V_028780_BLEND_DST_COLOR;
304 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
305 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
306 case VK_BLEND_FACTOR_SRC_ALPHA:
307 return V_028780_BLEND_SRC_ALPHA;
308 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
309 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
310 case VK_BLEND_FACTOR_DST_ALPHA:
311 return V_028780_BLEND_DST_ALPHA;
312 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
313 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
314 case VK_BLEND_FACTOR_CONSTANT_COLOR:
315 return V_028780_BLEND_CONSTANT_COLOR;
316 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
317 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
318 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
319 return V_028780_BLEND_CONSTANT_ALPHA;
320 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
321 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
322 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
323 return V_028780_BLEND_SRC_ALPHA_SATURATE;
324 case VK_BLEND_FACTOR_SRC1_COLOR:
325 return V_028780_BLEND_SRC1_COLOR;
326 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
327 return V_028780_BLEND_INV_SRC1_COLOR;
328 case VK_BLEND_FACTOR_SRC1_ALPHA:
329 return V_028780_BLEND_SRC1_ALPHA;
330 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
331 return V_028780_BLEND_INV_SRC1_ALPHA;
332 default:
333 return 0;
334 }
335 }
336
337 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
338 {
339 switch (op) {
340 case VK_BLEND_OP_ADD:
341 return V_028760_OPT_COMB_ADD;
342 case VK_BLEND_OP_SUBTRACT:
343 return V_028760_OPT_COMB_SUBTRACT;
344 case VK_BLEND_OP_REVERSE_SUBTRACT:
345 return V_028760_OPT_COMB_REVSUBTRACT;
346 case VK_BLEND_OP_MIN:
347 return V_028760_OPT_COMB_MIN;
348 case VK_BLEND_OP_MAX:
349 return V_028760_OPT_COMB_MAX;
350 default:
351 return V_028760_OPT_COMB_BLEND_DISABLED;
352 }
353 }
354
355 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
356 {
357 switch (factor) {
358 case VK_BLEND_FACTOR_ZERO:
359 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
360 case VK_BLEND_FACTOR_ONE:
361 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
362 case VK_BLEND_FACTOR_SRC_COLOR:
363 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
364 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
365 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
366 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
367 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
368 case VK_BLEND_FACTOR_SRC_ALPHA:
369 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
370 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
371 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
372 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
373 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
374 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
375 default:
376 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
377 }
378 }
379
380 /**
381 * Get rid of DST in the blend factors by commuting the operands:
382 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
383 */
384 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
385 unsigned *dst_factor, unsigned expected_dst,
386 unsigned replacement_src)
387 {
388 if (*src_factor == expected_dst &&
389 *dst_factor == VK_BLEND_FACTOR_ZERO) {
390 *src_factor = VK_BLEND_FACTOR_ZERO;
391 *dst_factor = replacement_src;
392
393 /* Commuting the operands requires reversing subtractions. */
394 if (*func == VK_BLEND_OP_SUBTRACT)
395 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
396 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
397 *func = VK_BLEND_OP_SUBTRACT;
398 }
399 }
400
401 static bool si_blend_factor_uses_dst(unsigned factor)
402 {
403 return factor == VK_BLEND_FACTOR_DST_COLOR ||
404 factor == VK_BLEND_FACTOR_DST_ALPHA ||
405 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
406 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
407 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
408 }
409
410 static bool is_dual_src(VkBlendFactor factor)
411 {
412 switch (factor) {
413 case VK_BLEND_FACTOR_SRC1_COLOR:
414 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
415 case VK_BLEND_FACTOR_SRC1_ALPHA:
416 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
417 return true;
418 default:
419 return false;
420 }
421 }
422
423 static unsigned si_choose_spi_color_format(VkFormat vk_format,
424 bool blend_enable,
425 bool blend_need_alpha)
426 {
427 const struct vk_format_description *desc = vk_format_description(vk_format);
428 unsigned format, ntype, swap;
429
430 /* Alpha is needed for alpha-to-coverage.
431 * Blending may be with or without alpha.
432 */
433 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
434 unsigned alpha = 0; /* exports alpha, but may not support blending */
435 unsigned blend = 0; /* supports blending, but may not export alpha */
436 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
437
438 format = radv_translate_colorformat(vk_format);
439 ntype = radv_translate_color_numformat(vk_format, desc,
440 vk_format_get_first_non_void_channel(vk_format));
441 swap = radv_translate_colorswap(vk_format, false);
442
443 /* Choose the SPI color formats. These are required values for Stoney/RB+.
444 * Other chips have multiple choices, though they are not necessarily better.
445 */
446 switch (format) {
447 case V_028C70_COLOR_5_6_5:
448 case V_028C70_COLOR_1_5_5_5:
449 case V_028C70_COLOR_5_5_5_1:
450 case V_028C70_COLOR_4_4_4_4:
451 case V_028C70_COLOR_10_11_11:
452 case V_028C70_COLOR_11_11_10:
453 case V_028C70_COLOR_8:
454 case V_028C70_COLOR_8_8:
455 case V_028C70_COLOR_8_8_8_8:
456 case V_028C70_COLOR_10_10_10_2:
457 case V_028C70_COLOR_2_10_10_10:
458 if (ntype == V_028C70_NUMBER_UINT)
459 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
460 else if (ntype == V_028C70_NUMBER_SINT)
461 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
462 else
463 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
464 break;
465
466 case V_028C70_COLOR_16:
467 case V_028C70_COLOR_16_16:
468 case V_028C70_COLOR_16_16_16_16:
469 if (ntype == V_028C70_NUMBER_UNORM ||
470 ntype == V_028C70_NUMBER_SNORM) {
471 /* UNORM16 and SNORM16 don't support blending */
472 if (ntype == V_028C70_NUMBER_UNORM)
473 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
474 else
475 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
476
477 /* Use 32 bits per channel for blending. */
478 if (format == V_028C70_COLOR_16) {
479 if (swap == V_028C70_SWAP_STD) { /* R */
480 blend = V_028714_SPI_SHADER_32_R;
481 blend_alpha = V_028714_SPI_SHADER_32_AR;
482 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
483 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
484 else
485 assert(0);
486 } else if (format == V_028C70_COLOR_16_16) {
487 if (swap == V_028C70_SWAP_STD) { /* RG */
488 blend = V_028714_SPI_SHADER_32_GR;
489 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
490 } else if (swap == V_028C70_SWAP_ALT) /* RA */
491 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
492 else
493 assert(0);
494 } else /* 16_16_16_16 */
495 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
496 } else if (ntype == V_028C70_NUMBER_UINT)
497 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
498 else if (ntype == V_028C70_NUMBER_SINT)
499 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
500 else if (ntype == V_028C70_NUMBER_FLOAT)
501 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
502 else
503 assert(0);
504 break;
505
506 case V_028C70_COLOR_32:
507 if (swap == V_028C70_SWAP_STD) { /* R */
508 blend = normal = V_028714_SPI_SHADER_32_R;
509 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
510 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
511 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
512 else
513 assert(0);
514 break;
515
516 case V_028C70_COLOR_32_32:
517 if (swap == V_028C70_SWAP_STD) { /* RG */
518 blend = normal = V_028714_SPI_SHADER_32_GR;
519 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
520 } else if (swap == V_028C70_SWAP_ALT) /* RA */
521 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
522 else
523 assert(0);
524 break;
525
526 case V_028C70_COLOR_32_32_32_32:
527 case V_028C70_COLOR_8_24:
528 case V_028C70_COLOR_24_8:
529 case V_028C70_COLOR_X24_8_32_FLOAT:
530 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
531 break;
532
533 default:
534 unreachable("unhandled blend format");
535 }
536
537 if (blend_enable && blend_need_alpha)
538 return blend_alpha;
539 else if(blend_need_alpha)
540 return alpha;
541 else if(blend_enable)
542 return blend;
543 else
544 return normal;
545 }
546
547 static void
548 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
549 const VkGraphicsPipelineCreateInfo *pCreateInfo,
550 struct radv_blend_state *blend)
551 {
552 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
553 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
554 unsigned col_format = 0;
555 unsigned num_targets;
556
557 for (unsigned i = 0; i < (blend->single_cb_enable ? 1 : subpass->color_count); ++i) {
558 unsigned cf;
559
560 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
561 cf = V_028714_SPI_SHADER_ZERO;
562 } else {
563 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
564 bool blend_enable =
565 blend->blend_enable_4bit & (0xfu << (i * 4));
566
567 cf = si_choose_spi_color_format(attachment->format,
568 blend_enable,
569 blend->need_src_alpha & (1 << i));
570 }
571
572 col_format |= cf << (4 * i);
573 }
574
575 if (!(col_format & 0xf) && blend->need_src_alpha & (1 << 0)) {
576 /* When a subpass doesn't have any color attachments, write the
577 * alpha channel of MRT0 when alpha coverage is enabled because
578 * the depth attachment needs it.
579 */
580 col_format |= V_028714_SPI_SHADER_32_AR;
581 }
582
583 /* If the i-th target format is set, all previous target formats must
584 * be non-zero to avoid hangs.
585 */
586 num_targets = (util_last_bit(col_format) + 3) / 4;
587 for (unsigned i = 0; i < num_targets; i++) {
588 if (!(col_format & (0xf << (i * 4)))) {
589 col_format |= V_028714_SPI_SHADER_32_R << (i * 4);
590 }
591 }
592
593 /* The output for dual source blending should have the same format as
594 * the first output.
595 */
596 if (blend->mrt0_is_dual_src)
597 col_format |= (col_format & 0xf) << 4;
598
599 blend->cb_shader_mask = ac_get_cb_shader_mask(col_format);
600 blend->spi_shader_col_format = col_format;
601 }
602
603 static bool
604 format_is_int8(VkFormat format)
605 {
606 const struct vk_format_description *desc = vk_format_description(format);
607 int channel = vk_format_get_first_non_void_channel(format);
608
609 return channel >= 0 && desc->channel[channel].pure_integer &&
610 desc->channel[channel].size == 8;
611 }
612
613 static bool
614 format_is_int10(VkFormat format)
615 {
616 const struct vk_format_description *desc = vk_format_description(format);
617
618 if (desc->nr_channels != 4)
619 return false;
620 for (unsigned i = 0; i < 4; i++) {
621 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
622 return true;
623 }
624 return false;
625 }
626
627 /*
628 * Ordered so that for each i,
629 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
630 */
631 const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS] = {
632 VK_FORMAT_R32_SFLOAT,
633 VK_FORMAT_R32G32_SFLOAT,
634 VK_FORMAT_R8G8B8A8_UNORM,
635 VK_FORMAT_R16G16B16A16_UNORM,
636 VK_FORMAT_R16G16B16A16_SNORM,
637 VK_FORMAT_R16G16B16A16_UINT,
638 VK_FORMAT_R16G16B16A16_SINT,
639 VK_FORMAT_R32G32B32A32_SFLOAT,
640 VK_FORMAT_R8G8B8A8_UINT,
641 VK_FORMAT_R8G8B8A8_SINT,
642 VK_FORMAT_A2R10G10B10_UINT_PACK32,
643 VK_FORMAT_A2R10G10B10_SINT_PACK32,
644 };
645
646 unsigned radv_format_meta_fs_key(VkFormat format)
647 {
648 unsigned col_format = si_choose_spi_color_format(format, false, false);
649
650 assert(col_format != V_028714_SPI_SHADER_32_AR);
651 if (col_format >= V_028714_SPI_SHADER_32_AR)
652 --col_format; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
653
654 --col_format; /* Skip V_028714_SPI_SHADER_ZERO */
655 bool is_int8 = format_is_int8(format);
656 bool is_int10 = format_is_int10(format);
657
658 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
659 }
660
661 static void
662 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo *pCreateInfo,
663 unsigned *is_int8, unsigned *is_int10)
664 {
665 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
666 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
667 *is_int8 = 0;
668 *is_int10 = 0;
669
670 for (unsigned i = 0; i < subpass->color_count; ++i) {
671 struct radv_render_pass_attachment *attachment;
672
673 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
674 continue;
675
676 attachment = pass->attachments + subpass->color_attachments[i].attachment;
677
678 if (format_is_int8(attachment->format))
679 *is_int8 |= 1 << i;
680 if (format_is_int10(attachment->format))
681 *is_int10 |= 1 << i;
682 }
683 }
684
685 static void
686 radv_blend_check_commutativity(struct radv_blend_state *blend,
687 VkBlendOp op, VkBlendFactor src,
688 VkBlendFactor dst, unsigned chanmask)
689 {
690 /* Src factor is allowed when it does not depend on Dst. */
691 static const uint32_t src_allowed =
692 (1u << VK_BLEND_FACTOR_ONE) |
693 (1u << VK_BLEND_FACTOR_SRC_COLOR) |
694 (1u << VK_BLEND_FACTOR_SRC_ALPHA) |
695 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE) |
696 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR) |
697 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA) |
698 (1u << VK_BLEND_FACTOR_SRC1_COLOR) |
699 (1u << VK_BLEND_FACTOR_SRC1_ALPHA) |
700 (1u << VK_BLEND_FACTOR_ZERO) |
701 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR) |
702 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA) |
703 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR) |
704 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA) |
705 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR) |
706 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA);
707
708 if (dst == VK_BLEND_FACTOR_ONE &&
709 (src_allowed & (1u << src))) {
710 /* Addition is commutative, but floating point addition isn't
711 * associative: subtle changes can be introduced via different
712 * rounding. Be conservative, only enable for min and max.
713 */
714 if (op == VK_BLEND_OP_MAX || op == VK_BLEND_OP_MIN)
715 blend->commutative_4bit |= chanmask;
716 }
717 }
718
719 static struct radv_blend_state
720 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
721 const VkGraphicsPipelineCreateInfo *pCreateInfo,
722 const struct radv_graphics_pipeline_create_info *extra)
723 {
724 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
725 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
726 struct radv_blend_state blend = {0};
727 unsigned mode = V_028808_CB_NORMAL;
728 int i;
729
730 if (!vkblend)
731 return blend;
732
733 if (extra && extra->custom_blend_mode) {
734 blend.single_cb_enable = true;
735 mode = extra->custom_blend_mode;
736 }
737 blend.cb_color_control = 0;
738 if (vkblend->logicOpEnable)
739 blend.cb_color_control |= S_028808_ROP3(si_translate_blend_logic_op(vkblend->logicOp));
740 else
741 blend.cb_color_control |= S_028808_ROP3(V_028808_ROP3_COPY);
742
743 blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
744 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
745 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
746 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
747 S_028B70_OFFSET_ROUND(1);
748
749 if (vkms && vkms->alphaToCoverageEnable) {
750 blend.db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
751 blend.need_src_alpha |= 0x1;
752 }
753
754 blend.cb_target_mask = 0;
755 for (i = 0; i < vkblend->attachmentCount; i++) {
756 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
757 unsigned blend_cntl = 0;
758 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
759 VkBlendOp eqRGB = att->colorBlendOp;
760 VkBlendFactor srcRGB = att->srcColorBlendFactor;
761 VkBlendFactor dstRGB = att->dstColorBlendFactor;
762 VkBlendOp eqA = att->alphaBlendOp;
763 VkBlendFactor srcA = att->srcAlphaBlendFactor;
764 VkBlendFactor dstA = att->dstAlphaBlendFactor;
765
766 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
767
768 if (!att->colorWriteMask)
769 continue;
770
771 blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
772 blend.cb_target_enabled_4bit |= 0xf << (4 * i);
773 if (!att->blendEnable) {
774 blend.cb_blend_control[i] = blend_cntl;
775 continue;
776 }
777
778 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
779 if (i == 0)
780 blend.mrt0_is_dual_src = true;
781
782 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
783 srcRGB = VK_BLEND_FACTOR_ONE;
784 dstRGB = VK_BLEND_FACTOR_ONE;
785 }
786 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
787 srcA = VK_BLEND_FACTOR_ONE;
788 dstA = VK_BLEND_FACTOR_ONE;
789 }
790
791 radv_blend_check_commutativity(&blend, eqRGB, srcRGB, dstRGB,
792 0x7 << (4 * i));
793 radv_blend_check_commutativity(&blend, eqA, srcA, dstA,
794 0x8 << (4 * i));
795
796 /* Blending optimizations for RB+.
797 * These transformations don't change the behavior.
798 *
799 * First, get rid of DST in the blend factors:
800 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
801 */
802 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
803 VK_BLEND_FACTOR_DST_COLOR,
804 VK_BLEND_FACTOR_SRC_COLOR);
805
806 si_blend_remove_dst(&eqA, &srcA, &dstA,
807 VK_BLEND_FACTOR_DST_COLOR,
808 VK_BLEND_FACTOR_SRC_COLOR);
809
810 si_blend_remove_dst(&eqA, &srcA, &dstA,
811 VK_BLEND_FACTOR_DST_ALPHA,
812 VK_BLEND_FACTOR_SRC_ALPHA);
813
814 /* Look up the ideal settings from tables. */
815 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
816 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
817 srcA_opt = si_translate_blend_opt_factor(srcA, true);
818 dstA_opt = si_translate_blend_opt_factor(dstA, true);
819
820 /* Handle interdependencies. */
821 if (si_blend_factor_uses_dst(srcRGB))
822 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
823 if (si_blend_factor_uses_dst(srcA))
824 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
825
826 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
827 (dstRGB == VK_BLEND_FACTOR_ZERO ||
828 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
829 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
830 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
831
832 /* Set the final value. */
833 blend.sx_mrt_blend_opt[i] =
834 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
835 S_028760_COLOR_DST_OPT(dstRGB_opt) |
836 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
837 S_028760_ALPHA_SRC_OPT(srcA_opt) |
838 S_028760_ALPHA_DST_OPT(dstA_opt) |
839 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
840 blend_cntl |= S_028780_ENABLE(1);
841
842 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
843 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
844 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
845 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
846 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
847 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
848 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
849 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
850 }
851 blend.cb_blend_control[i] = blend_cntl;
852
853 blend.blend_enable_4bit |= 0xfu << (i * 4);
854
855 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
856 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
857 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
858 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
859 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
860 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
861 blend.need_src_alpha |= 1 << i;
862 }
863 for (i = vkblend->attachmentCount; i < 8; i++) {
864 blend.cb_blend_control[i] = 0;
865 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
866 }
867
868 if (pipeline->device->physical_device->rad_info.has_rbplus) {
869 /* Disable RB+ blend optimizations for dual source blending. */
870 if (blend.mrt0_is_dual_src) {
871 for (i = 0; i < 8; i++) {
872 blend.sx_mrt_blend_opt[i] =
873 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
874 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
875 }
876 }
877
878 /* RB+ doesn't work with dual source blending, logic op and
879 * RESOLVE.
880 */
881 if (blend.mrt0_is_dual_src || vkblend->logicOpEnable ||
882 mode == V_028808_CB_RESOLVE)
883 blend.cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
884 }
885
886 if (blend.cb_target_mask)
887 blend.cb_color_control |= S_028808_MODE(mode);
888 else
889 blend.cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
890
891 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo, &blend);
892 return blend;
893 }
894
895 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
896 {
897 switch (op) {
898 case VK_STENCIL_OP_KEEP:
899 return V_02842C_STENCIL_KEEP;
900 case VK_STENCIL_OP_ZERO:
901 return V_02842C_STENCIL_ZERO;
902 case VK_STENCIL_OP_REPLACE:
903 return V_02842C_STENCIL_REPLACE_TEST;
904 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
905 return V_02842C_STENCIL_ADD_CLAMP;
906 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
907 return V_02842C_STENCIL_SUB_CLAMP;
908 case VK_STENCIL_OP_INVERT:
909 return V_02842C_STENCIL_INVERT;
910 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
911 return V_02842C_STENCIL_ADD_WRAP;
912 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
913 return V_02842C_STENCIL_SUB_WRAP;
914 default:
915 return 0;
916 }
917 }
918
919 static uint32_t si_translate_fill(VkPolygonMode func)
920 {
921 switch(func) {
922 case VK_POLYGON_MODE_FILL:
923 return V_028814_X_DRAW_TRIANGLES;
924 case VK_POLYGON_MODE_LINE:
925 return V_028814_X_DRAW_LINES;
926 case VK_POLYGON_MODE_POINT:
927 return V_028814_X_DRAW_POINTS;
928 default:
929 assert(0);
930 return V_028814_X_DRAW_POINTS;
931 }
932 }
933
934 static uint8_t radv_pipeline_get_ps_iter_samples(const VkPipelineMultisampleStateCreateInfo *vkms)
935 {
936 uint32_t num_samples = vkms->rasterizationSamples;
937 uint32_t ps_iter_samples = 1;
938
939 if (vkms->sampleShadingEnable) {
940 ps_iter_samples = ceil(vkms->minSampleShading * num_samples);
941 ps_iter_samples = util_next_power_of_two(ps_iter_samples);
942 }
943 return ps_iter_samples;
944 }
945
946 static bool
947 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
948 {
949 return pCreateInfo->depthTestEnable &&
950 pCreateInfo->depthWriteEnable &&
951 pCreateInfo->depthCompareOp != VK_COMPARE_OP_NEVER;
952 }
953
954 static bool
955 radv_writes_stencil(const VkStencilOpState *state)
956 {
957 return state->writeMask &&
958 (state->failOp != VK_STENCIL_OP_KEEP ||
959 state->passOp != VK_STENCIL_OP_KEEP ||
960 state->depthFailOp != VK_STENCIL_OP_KEEP);
961 }
962
963 static bool
964 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
965 {
966 return pCreateInfo->stencilTestEnable &&
967 (radv_writes_stencil(&pCreateInfo->front) ||
968 radv_writes_stencil(&pCreateInfo->back));
969 }
970
971 static bool
972 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
973 {
974 return radv_is_depth_write_enabled(pCreateInfo) ||
975 radv_is_stencil_write_enabled(pCreateInfo);
976 }
977
978 static bool
979 radv_order_invariant_stencil_op(VkStencilOp op)
980 {
981 /* REPLACE is normally order invariant, except when the stencil
982 * reference value is written by the fragment shader. Tracking this
983 * interaction does not seem worth the effort, so be conservative.
984 */
985 return op != VK_STENCIL_OP_INCREMENT_AND_CLAMP &&
986 op != VK_STENCIL_OP_DECREMENT_AND_CLAMP &&
987 op != VK_STENCIL_OP_REPLACE;
988 }
989
990 static bool
991 radv_order_invariant_stencil_state(const VkStencilOpState *state)
992 {
993 /* Compute whether, assuming Z writes are disabled, this stencil state
994 * is order invariant in the sense that the set of passing fragments as
995 * well as the final stencil buffer result does not depend on the order
996 * of fragments.
997 */
998 return !state->writeMask ||
999 /* The following assumes that Z writes are disabled. */
1000 (state->compareOp == VK_COMPARE_OP_ALWAYS &&
1001 radv_order_invariant_stencil_op(state->passOp) &&
1002 radv_order_invariant_stencil_op(state->depthFailOp)) ||
1003 (state->compareOp == VK_COMPARE_OP_NEVER &&
1004 radv_order_invariant_stencil_op(state->failOp));
1005 }
1006
1007 static bool
1008 radv_pipeline_out_of_order_rast(struct radv_pipeline *pipeline,
1009 struct radv_blend_state *blend,
1010 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1011 {
1012 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1013 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
1014 unsigned colormask = blend->cb_target_enabled_4bit;
1015
1016 if (!pipeline->device->physical_device->out_of_order_rast_allowed)
1017 return false;
1018
1019 /* Be conservative if a logic operation is enabled with color buffers. */
1020 if (colormask && pCreateInfo->pColorBlendState->logicOpEnable)
1021 return false;
1022
1023 /* Default depth/stencil invariance when no attachment is bound. */
1024 struct radv_dsa_order_invariance dsa_order_invariant = {
1025 .zs = true, .pass_set = true
1026 };
1027
1028 if (pCreateInfo->pDepthStencilState &&
1029 subpass->depth_stencil_attachment) {
1030 const VkPipelineDepthStencilStateCreateInfo *vkds =
1031 pCreateInfo->pDepthStencilState;
1032 struct radv_render_pass_attachment *attachment =
1033 pass->attachments + subpass->depth_stencil_attachment->attachment;
1034 bool has_stencil = vk_format_is_stencil(attachment->format);
1035 struct radv_dsa_order_invariance order_invariance[2];
1036 struct radv_shader_variant *ps =
1037 pipeline->shaders[MESA_SHADER_FRAGMENT];
1038
1039 /* Compute depth/stencil order invariance in order to know if
1040 * it's safe to enable out-of-order.
1041 */
1042 bool zfunc_is_ordered =
1043 vkds->depthCompareOp == VK_COMPARE_OP_NEVER ||
1044 vkds->depthCompareOp == VK_COMPARE_OP_LESS ||
1045 vkds->depthCompareOp == VK_COMPARE_OP_LESS_OR_EQUAL ||
1046 vkds->depthCompareOp == VK_COMPARE_OP_GREATER ||
1047 vkds->depthCompareOp == VK_COMPARE_OP_GREATER_OR_EQUAL;
1048
1049 bool nozwrite_and_order_invariant_stencil =
1050 !radv_is_ds_write_enabled(vkds) ||
1051 (!radv_is_depth_write_enabled(vkds) &&
1052 radv_order_invariant_stencil_state(&vkds->front) &&
1053 radv_order_invariant_stencil_state(&vkds->back));
1054
1055 order_invariance[1].zs =
1056 nozwrite_and_order_invariant_stencil ||
1057 (!radv_is_stencil_write_enabled(vkds) &&
1058 zfunc_is_ordered);
1059 order_invariance[0].zs =
1060 !radv_is_depth_write_enabled(vkds) || zfunc_is_ordered;
1061
1062 order_invariance[1].pass_set =
1063 nozwrite_and_order_invariant_stencil ||
1064 (!radv_is_stencil_write_enabled(vkds) &&
1065 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1066 vkds->depthCompareOp == VK_COMPARE_OP_NEVER));
1067 order_invariance[0].pass_set =
1068 !radv_is_depth_write_enabled(vkds) ||
1069 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1070 vkds->depthCompareOp == VK_COMPARE_OP_NEVER);
1071
1072 dsa_order_invariant = order_invariance[has_stencil];
1073 if (!dsa_order_invariant.zs)
1074 return false;
1075
1076 /* The set of PS invocations is always order invariant,
1077 * except when early Z/S tests are requested.
1078 */
1079 if (ps &&
1080 ps->info.info.ps.writes_memory &&
1081 ps->info.fs.early_fragment_test &&
1082 !dsa_order_invariant.pass_set)
1083 return false;
1084
1085 /* Determine if out-of-order rasterization should be disabled
1086 * when occlusion queries are used.
1087 */
1088 pipeline->graphics.disable_out_of_order_rast_for_occlusion =
1089 !dsa_order_invariant.pass_set;
1090 }
1091
1092 /* No color buffers are enabled for writing. */
1093 if (!colormask)
1094 return true;
1095
1096 unsigned blendmask = colormask & blend->blend_enable_4bit;
1097
1098 if (blendmask) {
1099 /* Only commutative blending. */
1100 if (blendmask & ~blend->commutative_4bit)
1101 return false;
1102
1103 if (!dsa_order_invariant.pass_set)
1104 return false;
1105 }
1106
1107 if (colormask & ~blendmask)
1108 return false;
1109
1110 return true;
1111 }
1112
1113 static void
1114 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1115 struct radv_blend_state *blend,
1116 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1117 {
1118 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
1119 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1120 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1121 bool out_of_order_rast = false;
1122 int ps_iter_samples = 1;
1123 uint32_t mask = 0xffff;
1124
1125 if (vkms)
1126 ms->num_samples = vkms->rasterizationSamples;
1127 else
1128 ms->num_samples = 1;
1129
1130 if (vkms)
1131 ps_iter_samples = radv_pipeline_get_ps_iter_samples(vkms);
1132 if (vkms && !vkms->sampleShadingEnable && pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.force_persample) {
1133 ps_iter_samples = ms->num_samples;
1134 }
1135
1136 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
1137 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
1138 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
1139 /* Out-of-order rasterization is explicitly enabled by the
1140 * application.
1141 */
1142 out_of_order_rast = true;
1143 } else {
1144 /* Determine if the driver can enable out-of-order
1145 * rasterization internally.
1146 */
1147 out_of_order_rast =
1148 radv_pipeline_out_of_order_rast(pipeline, blend, pCreateInfo);
1149 }
1150
1151 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1152 ms->pa_sc_aa_config = 0;
1153 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1154 S_028804_INCOHERENT_EQAA_READS(1) |
1155 S_028804_INTERPOLATE_COMP_Z(1) |
1156 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1157 ms->pa_sc_mode_cntl_1 =
1158 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1159 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1160 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
1161 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1162 /* always 1: */
1163 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1164 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1165 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1166 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1167 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1168 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1169 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9) |
1170 S_028A48_VPORT_SCISSOR_ENABLE(1);
1171
1172 if (ms->num_samples > 1) {
1173 unsigned log_samples = util_logbase2(ms->num_samples);
1174 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
1175 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
1176 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1177 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1178 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1179 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1180 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1181 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1182 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples)) |
1183 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1184 ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1185 if (ps_iter_samples > 1)
1186 pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1187 }
1188
1189 if (vkms && vkms->pSampleMask) {
1190 mask = vkms->pSampleMask[0] & 0xffff;
1191 }
1192
1193 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1194 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1195 }
1196
1197 static bool
1198 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1199 {
1200 switch (topology) {
1201 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1202 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1203 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1204 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1205 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1206 return false;
1207 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1208 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1209 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1210 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1211 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1212 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1213 return true;
1214 default:
1215 unreachable("unhandled primitive type");
1216 }
1217 }
1218
1219 static uint32_t
1220 si_translate_prim(enum VkPrimitiveTopology topology)
1221 {
1222 switch (topology) {
1223 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1224 return V_008958_DI_PT_POINTLIST;
1225 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1226 return V_008958_DI_PT_LINELIST;
1227 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1228 return V_008958_DI_PT_LINESTRIP;
1229 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1230 return V_008958_DI_PT_TRILIST;
1231 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1232 return V_008958_DI_PT_TRISTRIP;
1233 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1234 return V_008958_DI_PT_TRIFAN;
1235 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1236 return V_008958_DI_PT_LINELIST_ADJ;
1237 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1238 return V_008958_DI_PT_LINESTRIP_ADJ;
1239 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1240 return V_008958_DI_PT_TRILIST_ADJ;
1241 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1242 return V_008958_DI_PT_TRISTRIP_ADJ;
1243 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1244 return V_008958_DI_PT_PATCH;
1245 default:
1246 assert(0);
1247 return 0;
1248 }
1249 }
1250
1251 static uint32_t
1252 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1253 {
1254 switch (gl_prim) {
1255 case 0: /* GL_POINTS */
1256 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1257 case 1: /* GL_LINES */
1258 case 3: /* GL_LINE_STRIP */
1259 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1260 case 0x8E7A: /* GL_ISOLINES */
1261 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1262
1263 case 4: /* GL_TRIANGLES */
1264 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1265 case 5: /* GL_TRIANGLE_STRIP */
1266 case 7: /* GL_QUADS */
1267 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1268 default:
1269 assert(0);
1270 return 0;
1271 }
1272 }
1273
1274 static uint32_t
1275 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1276 {
1277 switch (topology) {
1278 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1279 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1280 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1281 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1282 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1283 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1284 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1285 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1286 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1287 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1288 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1289 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1290 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1291 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1292 default:
1293 assert(0);
1294 return 0;
1295 }
1296 }
1297
1298 static unsigned radv_dynamic_state_mask(VkDynamicState state)
1299 {
1300 switch(state) {
1301 case VK_DYNAMIC_STATE_VIEWPORT:
1302 return RADV_DYNAMIC_VIEWPORT;
1303 case VK_DYNAMIC_STATE_SCISSOR:
1304 return RADV_DYNAMIC_SCISSOR;
1305 case VK_DYNAMIC_STATE_LINE_WIDTH:
1306 return RADV_DYNAMIC_LINE_WIDTH;
1307 case VK_DYNAMIC_STATE_DEPTH_BIAS:
1308 return RADV_DYNAMIC_DEPTH_BIAS;
1309 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
1310 return RADV_DYNAMIC_BLEND_CONSTANTS;
1311 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
1312 return RADV_DYNAMIC_DEPTH_BOUNDS;
1313 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
1314 return RADV_DYNAMIC_STENCIL_COMPARE_MASK;
1315 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
1316 return RADV_DYNAMIC_STENCIL_WRITE_MASK;
1317 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
1318 return RADV_DYNAMIC_STENCIL_REFERENCE;
1319 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT:
1320 return RADV_DYNAMIC_DISCARD_RECTANGLE;
1321 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT:
1322 return RADV_DYNAMIC_SAMPLE_LOCATIONS;
1323 default:
1324 unreachable("Unhandled dynamic state");
1325 }
1326 }
1327
1328 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
1329 {
1330 uint32_t states = RADV_DYNAMIC_ALL;
1331
1332 /* If rasterization is disabled we do not care about any of the dynamic states,
1333 * since they are all rasterization related only. */
1334 if (pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
1335 return 0;
1336
1337 if (!pCreateInfo->pRasterizationState->depthBiasEnable)
1338 states &= ~RADV_DYNAMIC_DEPTH_BIAS;
1339
1340 if (!pCreateInfo->pDepthStencilState ||
1341 !pCreateInfo->pDepthStencilState->depthBoundsTestEnable)
1342 states &= ~RADV_DYNAMIC_DEPTH_BOUNDS;
1343
1344 if (!pCreateInfo->pDepthStencilState ||
1345 !pCreateInfo->pDepthStencilState->stencilTestEnable)
1346 states &= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK |
1347 RADV_DYNAMIC_STENCIL_WRITE_MASK |
1348 RADV_DYNAMIC_STENCIL_REFERENCE);
1349
1350 if (!vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT))
1351 states &= ~RADV_DYNAMIC_DISCARD_RECTANGLE;
1352
1353 if (!pCreateInfo->pMultisampleState ||
1354 !vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1355 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT))
1356 states &= ~RADV_DYNAMIC_SAMPLE_LOCATIONS;
1357
1358 /* TODO: blend constants & line width. */
1359
1360 return states;
1361 }
1362
1363
1364 static void
1365 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1366 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1367 {
1368 uint32_t needed_states = radv_pipeline_needed_dynamic_state(pCreateInfo);
1369 uint32_t states = needed_states;
1370 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1371 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1372
1373 pipeline->dynamic_state = default_dynamic_state;
1374 pipeline->graphics.needed_dynamic_state = needed_states;
1375
1376 if (pCreateInfo->pDynamicState) {
1377 /* Remove all of the states that are marked as dynamic */
1378 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1379 for (uint32_t s = 0; s < count; s++)
1380 states &= ~radv_dynamic_state_mask(pCreateInfo->pDynamicState->pDynamicStates[s]);
1381 }
1382
1383 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1384
1385 if (needed_states & RADV_DYNAMIC_VIEWPORT) {
1386 assert(pCreateInfo->pViewportState);
1387
1388 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1389 if (states & RADV_DYNAMIC_VIEWPORT) {
1390 typed_memcpy(dynamic->viewport.viewports,
1391 pCreateInfo->pViewportState->pViewports,
1392 pCreateInfo->pViewportState->viewportCount);
1393 }
1394 }
1395
1396 if (needed_states & RADV_DYNAMIC_SCISSOR) {
1397 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1398 if (states & RADV_DYNAMIC_SCISSOR) {
1399 typed_memcpy(dynamic->scissor.scissors,
1400 pCreateInfo->pViewportState->pScissors,
1401 pCreateInfo->pViewportState->scissorCount);
1402 }
1403 }
1404
1405 if (states & RADV_DYNAMIC_LINE_WIDTH) {
1406 assert(pCreateInfo->pRasterizationState);
1407 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1408 }
1409
1410 if (states & RADV_DYNAMIC_DEPTH_BIAS) {
1411 assert(pCreateInfo->pRasterizationState);
1412 dynamic->depth_bias.bias =
1413 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1414 dynamic->depth_bias.clamp =
1415 pCreateInfo->pRasterizationState->depthBiasClamp;
1416 dynamic->depth_bias.slope =
1417 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1418 }
1419
1420 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1421 *
1422 * pColorBlendState is [...] NULL if the pipeline has rasterization
1423 * disabled or if the subpass of the render pass the pipeline is
1424 * created against does not use any color attachments.
1425 */
1426 if (subpass->has_color_att && states & RADV_DYNAMIC_BLEND_CONSTANTS) {
1427 assert(pCreateInfo->pColorBlendState);
1428 typed_memcpy(dynamic->blend_constants,
1429 pCreateInfo->pColorBlendState->blendConstants, 4);
1430 }
1431
1432 /* If there is no depthstencil attachment, then don't read
1433 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1434 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1435 * no need to override the depthstencil defaults in
1436 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1437 *
1438 * Section 9.2 of the Vulkan 1.0.15 spec says:
1439 *
1440 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1441 * disabled or if the subpass of the render pass the pipeline is created
1442 * against does not use a depth/stencil attachment.
1443 */
1444 if (needed_states && subpass->depth_stencil_attachment) {
1445 assert(pCreateInfo->pDepthStencilState);
1446
1447 if (states & RADV_DYNAMIC_DEPTH_BOUNDS) {
1448 dynamic->depth_bounds.min =
1449 pCreateInfo->pDepthStencilState->minDepthBounds;
1450 dynamic->depth_bounds.max =
1451 pCreateInfo->pDepthStencilState->maxDepthBounds;
1452 }
1453
1454 if (states & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
1455 dynamic->stencil_compare_mask.front =
1456 pCreateInfo->pDepthStencilState->front.compareMask;
1457 dynamic->stencil_compare_mask.back =
1458 pCreateInfo->pDepthStencilState->back.compareMask;
1459 }
1460
1461 if (states & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
1462 dynamic->stencil_write_mask.front =
1463 pCreateInfo->pDepthStencilState->front.writeMask;
1464 dynamic->stencil_write_mask.back =
1465 pCreateInfo->pDepthStencilState->back.writeMask;
1466 }
1467
1468 if (states & RADV_DYNAMIC_STENCIL_REFERENCE) {
1469 dynamic->stencil_reference.front =
1470 pCreateInfo->pDepthStencilState->front.reference;
1471 dynamic->stencil_reference.back =
1472 pCreateInfo->pDepthStencilState->back.reference;
1473 }
1474 }
1475
1476 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
1477 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
1478 if (needed_states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1479 dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount;
1480 if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1481 typed_memcpy(dynamic->discard_rectangle.rectangles,
1482 discard_rectangle_info->pDiscardRectangles,
1483 discard_rectangle_info->discardRectangleCount);
1484 }
1485 }
1486
1487 if (needed_states & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
1488 const VkPipelineSampleLocationsStateCreateInfoEXT *sample_location_info =
1489 vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1490 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
1491 /* If sampleLocationsEnable is VK_FALSE, the default sample
1492 * locations are used and the values specified in
1493 * sampleLocationsInfo are ignored.
1494 */
1495 if (sample_location_info->sampleLocationsEnable) {
1496 const VkSampleLocationsInfoEXT *pSampleLocationsInfo =
1497 &sample_location_info->sampleLocationsInfo;
1498
1499 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
1500
1501 dynamic->sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
1502 dynamic->sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
1503 dynamic->sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
1504 typed_memcpy(&dynamic->sample_location.locations[0],
1505 pSampleLocationsInfo->pSampleLocations,
1506 pSampleLocationsInfo->sampleLocationsCount);
1507 }
1508 }
1509
1510 pipeline->dynamic_state.mask = states;
1511 }
1512
1513 static struct radv_gs_state
1514 calculate_gs_info(const VkGraphicsPipelineCreateInfo *pCreateInfo,
1515 const struct radv_pipeline *pipeline)
1516 {
1517 struct radv_gs_state gs = {0};
1518 struct radv_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1519 struct radv_es_output_info *es_info;
1520 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
1521 es_info = radv_pipeline_has_tess(pipeline) ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1522 else
1523 es_info = radv_pipeline_has_tess(pipeline) ?
1524 &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.es_info :
1525 &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info;
1526
1527 unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
1528 bool uses_adjacency;
1529 switch(pCreateInfo->pInputAssemblyState->topology) {
1530 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1531 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1532 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1533 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1534 uses_adjacency = true;
1535 break;
1536 default:
1537 uses_adjacency = false;
1538 break;
1539 }
1540
1541 /* All these are in dwords: */
1542 /* We can't allow using the whole LDS, because GS waves compete with
1543 * other shader stages for LDS space. */
1544 const unsigned max_lds_size = 8 * 1024;
1545 const unsigned esgs_itemsize = es_info->esgs_itemsize / 4;
1546 unsigned esgs_lds_size;
1547
1548 /* All these are per subgroup: */
1549 const unsigned max_out_prims = 32 * 1024;
1550 const unsigned max_es_verts = 255;
1551 const unsigned ideal_gs_prims = 64;
1552 unsigned max_gs_prims, gs_prims;
1553 unsigned min_es_verts, es_verts, worst_case_es_verts;
1554
1555 if (uses_adjacency || gs_num_invocations > 1)
1556 max_gs_prims = 127 / gs_num_invocations;
1557 else
1558 max_gs_prims = 255;
1559
1560 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1561 * Make sure we don't go over the maximum value.
1562 */
1563 if (gs_info->gs.vertices_out > 0) {
1564 max_gs_prims = MIN2(max_gs_prims,
1565 max_out_prims /
1566 (gs_info->gs.vertices_out * gs_num_invocations));
1567 }
1568 assert(max_gs_prims > 0);
1569
1570 /* If the primitive has adjacency, halve the number of vertices
1571 * that will be reused in multiple primitives.
1572 */
1573 min_es_verts = gs_info->gs.vertices_in / (uses_adjacency ? 2 : 1);
1574
1575 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
1576 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
1577
1578 /* Compute ESGS LDS size based on the worst case number of ES vertices
1579 * needed to create the target number of GS prims per subgroup.
1580 */
1581 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1582
1583 /* If total LDS usage is too big, refactor partitions based on ratio
1584 * of ESGS item sizes.
1585 */
1586 if (esgs_lds_size > max_lds_size) {
1587 /* Our target GS Prims Per Subgroup was too large. Calculate
1588 * the maximum number of GS Prims Per Subgroup that will fit
1589 * into LDS, capped by the maximum that the hardware can support.
1590 */
1591 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
1592 max_gs_prims);
1593 assert(gs_prims > 0);
1594 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
1595 max_es_verts);
1596
1597 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1598 assert(esgs_lds_size <= max_lds_size);
1599 }
1600
1601 /* Now calculate remaining ESGS information. */
1602 if (esgs_lds_size)
1603 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
1604 else
1605 es_verts = max_es_verts;
1606
1607 /* Vertices for adjacency primitives are not always reused, so restore
1608 * it for ES_VERTS_PER_SUBGRP.
1609 */
1610 min_es_verts = gs_info->gs.vertices_in;
1611
1612 /* For normal primitives, the VGT only checks if they are past the ES
1613 * verts per subgroup after allocating a full GS primitive and if they
1614 * are, kick off a new subgroup. But if those additional ES verts are
1615 * unique (e.g. not reused) we need to make sure there is enough LDS
1616 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1617 */
1618 es_verts -= min_es_verts - 1;
1619
1620 uint32_t es_verts_per_subgroup = es_verts;
1621 uint32_t gs_prims_per_subgroup = gs_prims;
1622 uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
1623 uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out;
1624 gs.lds_size = align(esgs_lds_size, 128) / 128;
1625 gs.vgt_gs_onchip_cntl = S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) |
1626 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) |
1627 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup);
1628 gs.vgt_gs_max_prims_per_subgroup = S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup);
1629 gs.vgt_esgs_ring_itemsize = esgs_itemsize;
1630 assert(max_prims_per_subgroup <= max_out_prims);
1631
1632 return gs;
1633 }
1634
1635 static void clamp_gsprims_to_esverts(unsigned *max_gsprims, unsigned max_esverts,
1636 unsigned min_verts_per_prim, bool use_adjacency)
1637 {
1638 unsigned max_reuse = max_esverts - min_verts_per_prim;
1639 if (use_adjacency)
1640 max_reuse /= 2;
1641 *max_gsprims = MIN2(*max_gsprims, 1 + max_reuse);
1642 }
1643
1644 static unsigned
1645 radv_get_num_input_vertices(struct radv_pipeline *pipeline)
1646 {
1647 if (radv_pipeline_has_gs(pipeline)) {
1648 struct radv_shader_variant *gs =
1649 radv_get_shader(pipeline, MESA_SHADER_GEOMETRY);
1650
1651 return gs->info.gs.vertices_in;
1652 }
1653
1654 if (radv_pipeline_has_tess(pipeline)) {
1655 struct radv_shader_variant *tes = radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL);
1656
1657 if (tes->info.tes.point_mode)
1658 return 1;
1659 if (tes->info.tes.primitive_mode == GL_ISOLINES)
1660 return 2;
1661 return 3;
1662 }
1663
1664 return 3;
1665 }
1666
1667 static struct radv_ngg_state
1668 calculate_ngg_info(const VkGraphicsPipelineCreateInfo *pCreateInfo,
1669 struct radv_pipeline *pipeline)
1670 {
1671 struct radv_ngg_state ngg = {0};
1672 struct radv_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1673 struct radv_es_output_info *es_info =
1674 radv_pipeline_has_tess(pipeline) ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1675 unsigned gs_type = radv_pipeline_has_gs(pipeline) ? MESA_SHADER_GEOMETRY : MESA_SHADER_VERTEX;
1676 unsigned max_verts_per_prim = radv_get_num_input_vertices(pipeline);
1677 unsigned min_verts_per_prim =
1678 gs_type == MESA_SHADER_GEOMETRY ? max_verts_per_prim : 1;
1679 unsigned gs_num_invocations = radv_pipeline_has_gs(pipeline) ? MAX2(gs_info->gs.invocations, 1) : 1;
1680 bool uses_adjacency;
1681 switch(pCreateInfo->pInputAssemblyState->topology) {
1682 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1683 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1684 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1685 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1686 uses_adjacency = true;
1687 break;
1688 default:
1689 uses_adjacency = false;
1690 break;
1691 }
1692
1693 /* All these are in dwords: */
1694 /* We can't allow using the whole LDS, because GS waves compete with
1695 * other shader stages for LDS space.
1696 *
1697 * Streamout can increase the ESGS buffer size later on, so be more
1698 * conservative with streamout and use 4K dwords. This may be suboptimal.
1699 *
1700 * Otherwise, use the limit of 7K dwords. The reason is that we need
1701 * to leave some headroom for the max_esverts increase at the end.
1702 *
1703 * TODO: We should really take the shader's internal LDS use into
1704 * account. The linker will fail if the size is greater than
1705 * 8K dwords.
1706 */
1707 const unsigned max_lds_size = (0 /*gs_info->info.so.num_outputs*/ ? 4 : 7) * 1024 - 128;
1708 const unsigned target_lds_size = max_lds_size;
1709 unsigned esvert_lds_size = 0;
1710 unsigned gsprim_lds_size = 0;
1711
1712 /* All these are per subgroup: */
1713 bool max_vert_out_per_gs_instance = false;
1714 unsigned max_esverts_base = 256;
1715 unsigned max_gsprims_base = 128; /* default prim group size clamp */
1716
1717 /* Hardware has the following non-natural restrictions on the value
1718 * of GE_CNTL.VERT_GRP_SIZE based on based on the primitive type of
1719 * the draw:
1720 * - at most 252 for any line input primitive type
1721 * - at most 251 for any quad input primitive type
1722 * - at most 251 for triangle strips with adjacency (this happens to
1723 * be the natural limit for triangle *lists* with adjacency)
1724 */
1725 max_esverts_base = MIN2(max_esverts_base, 251 + max_verts_per_prim - 1);
1726
1727 if (gs_type == MESA_SHADER_GEOMETRY) {
1728 unsigned max_out_verts_per_gsprim =
1729 gs_info->gs.vertices_out * gs_num_invocations;
1730
1731 if (max_out_verts_per_gsprim <= 256) {
1732 if (max_out_verts_per_gsprim) {
1733 max_gsprims_base = MIN2(max_gsprims_base,
1734 256 / max_out_verts_per_gsprim);
1735 }
1736 } else {
1737 /* Use special multi-cycling mode in which each GS
1738 * instance gets its own subgroup. Does not work with
1739 * tessellation. */
1740 max_vert_out_per_gs_instance = true;
1741 max_gsprims_base = 1;
1742 max_out_verts_per_gsprim = gs_info->gs.vertices_out;
1743 }
1744
1745 esvert_lds_size = es_info->esgs_itemsize / 4;
1746 gsprim_lds_size = (gs_info->gs.gsvs_vertex_size / 4 + 1) * max_out_verts_per_gsprim;
1747 } else {
1748 /* TODO: This needs to be adjusted once LDS use for compaction
1749 * after culling is implemented. */
1750 /*
1751 if (es_info->info.so.num_outputs)
1752 esvert_lds_size = 4 * es_info->info.so.num_outputs + 1;
1753 */
1754
1755 /* LDS size for passing data from GS to ES.
1756 * GS stores Primitive IDs (one DWORD) into LDS at the address
1757 * corresponding to the ES thread of the provoking vertex. All
1758 * ES threads load and export PrimitiveID for their thread.
1759 */
1760 if (!radv_pipeline_has_tess(pipeline) &&
1761 pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.export_prim_id)
1762 esvert_lds_size = MAX2(esvert_lds_size, 1);
1763 }
1764
1765 unsigned max_gsprims = max_gsprims_base;
1766 unsigned max_esverts = max_esverts_base;
1767
1768 if (esvert_lds_size)
1769 max_esverts = MIN2(max_esverts, target_lds_size / esvert_lds_size);
1770 if (gsprim_lds_size)
1771 max_gsprims = MIN2(max_gsprims, target_lds_size / gsprim_lds_size);
1772
1773 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1774 clamp_gsprims_to_esverts(&max_gsprims, max_esverts, min_verts_per_prim, uses_adjacency);
1775 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1776
1777 if (esvert_lds_size || gsprim_lds_size) {
1778 /* Now that we have a rough proportionality between esverts
1779 * and gsprims based on the primitive type, scale both of them
1780 * down simultaneously based on required LDS space.
1781 *
1782 * We could be smarter about this if we knew how much vertex
1783 * reuse to expect.
1784 */
1785 unsigned lds_total = max_esverts * esvert_lds_size +
1786 max_gsprims * gsprim_lds_size;
1787 if (lds_total > target_lds_size) {
1788 max_esverts = max_esverts * target_lds_size / lds_total;
1789 max_gsprims = max_gsprims * target_lds_size / lds_total;
1790
1791 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1792 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1793 min_verts_per_prim, uses_adjacency);
1794 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1795 }
1796 }
1797
1798 /* Round up towards full wave sizes for better ALU utilization. */
1799 if (!max_vert_out_per_gs_instance) {
1800 const unsigned wavesize = pipeline->device->physical_device->ge_wave_size;
1801 unsigned orig_max_esverts;
1802 unsigned orig_max_gsprims;
1803 do {
1804 orig_max_esverts = max_esverts;
1805 orig_max_gsprims = max_gsprims;
1806
1807 max_esverts = align(max_esverts, wavesize);
1808 max_esverts = MIN2(max_esverts, max_esverts_base);
1809 if (esvert_lds_size)
1810 max_esverts = MIN2(max_esverts,
1811 (max_lds_size - max_gsprims * gsprim_lds_size) /
1812 esvert_lds_size);
1813 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1814
1815 max_gsprims = align(max_gsprims, wavesize);
1816 max_gsprims = MIN2(max_gsprims, max_gsprims_base);
1817 if (gsprim_lds_size)
1818 max_gsprims = MIN2(max_gsprims,
1819 (max_lds_size - max_esverts * esvert_lds_size) /
1820 gsprim_lds_size);
1821 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1822 min_verts_per_prim, uses_adjacency);
1823 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1824 } while (orig_max_esverts != max_esverts || orig_max_gsprims != max_gsprims);
1825 }
1826
1827 /* Hardware restriction: minimum value of max_esverts */
1828 max_esverts = MAX2(max_esverts, 23 + max_verts_per_prim);
1829
1830 unsigned max_out_vertices =
1831 max_vert_out_per_gs_instance ? gs_info->gs.vertices_out :
1832 gs_type == MESA_SHADER_GEOMETRY ?
1833 max_gsprims * gs_num_invocations * gs_info->gs.vertices_out :
1834 max_esverts;
1835 assert(max_out_vertices <= 256);
1836
1837 unsigned prim_amp_factor = 1;
1838 if (gs_type == MESA_SHADER_GEOMETRY) {
1839 /* Number of output primitives per GS input primitive after
1840 * GS instancing. */
1841 prim_amp_factor = gs_info->gs.vertices_out;
1842 }
1843
1844 /* The GE only checks against the maximum number of ES verts after
1845 * allocating a full GS primitive. So we need to ensure that whenever
1846 * this check passes, there is enough space for a full primitive without
1847 * vertex reuse.
1848 */
1849 ngg.hw_max_esverts = max_esverts - max_verts_per_prim + 1;
1850 ngg.max_gsprims = max_gsprims;
1851 ngg.max_out_verts = max_out_vertices;
1852 ngg.prim_amp_factor = prim_amp_factor;
1853 ngg.max_vert_out_per_gs_instance = max_vert_out_per_gs_instance;
1854 ngg.ngg_emit_size = max_gsprims * gsprim_lds_size;
1855
1856 if (gs_type == MESA_SHADER_GEOMETRY) {
1857 ngg.vgt_esgs_ring_itemsize = es_info->esgs_itemsize / 4;
1858 } else {
1859 ngg.vgt_esgs_ring_itemsize = 1;
1860 }
1861
1862 pipeline->graphics.esgs_ring_size = 4 * max_esverts * esvert_lds_size;
1863
1864 assert(ngg.hw_max_esverts >= 24); /* HW limitation */
1865
1866 return ngg;
1867 }
1868
1869 static void
1870 calculate_gs_ring_sizes(struct radv_pipeline *pipeline, const struct radv_gs_state *gs)
1871 {
1872 struct radv_device *device = pipeline->device;
1873 unsigned num_se = device->physical_device->rad_info.max_se;
1874 unsigned wave_size = 64;
1875 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1876 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
1877 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
1878 */
1879 unsigned gs_vertex_reuse =
1880 (device->physical_device->rad_info.chip_class >= GFX8 ? 32 : 16) * num_se;
1881 unsigned alignment = 256 * num_se;
1882 /* The maximum size is 63.999 MB per SE. */
1883 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1884 struct radv_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1885
1886 /* Calculate the minimum size. */
1887 unsigned min_esgs_ring_size = align(gs->vgt_esgs_ring_itemsize * 4 * gs_vertex_reuse *
1888 wave_size, alignment);
1889 /* These are recommended sizes, not minimum sizes. */
1890 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1891 gs->vgt_esgs_ring_itemsize * 4 * gs_info->gs.vertices_in;
1892 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1893 gs_info->gs.max_gsvs_emit_size;
1894
1895 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1896 esgs_ring_size = align(esgs_ring_size, alignment);
1897 gsvs_ring_size = align(gsvs_ring_size, alignment);
1898
1899 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
1900 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1901
1902 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1903 }
1904
1905 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1906 unsigned *lds_size)
1907 {
1908 /* If tessellation is all offchip and on-chip GS isn't used, this
1909 * workaround is not needed.
1910 */
1911 return;
1912
1913 /* SPI barrier management bug:
1914 * Make sure we have at least 4k of LDS in use to avoid the bug.
1915 * It applies to workgroup sizes of more than one wavefront.
1916 */
1917 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1918 device->physical_device->rad_info.family == CHIP_KABINI)
1919 *lds_size = MAX2(*lds_size, 8);
1920 }
1921
1922 struct radv_shader_variant *
1923 radv_get_shader(struct radv_pipeline *pipeline,
1924 gl_shader_stage stage)
1925 {
1926 if (stage == MESA_SHADER_VERTEX) {
1927 if (pipeline->shaders[MESA_SHADER_VERTEX])
1928 return pipeline->shaders[MESA_SHADER_VERTEX];
1929 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
1930 return pipeline->shaders[MESA_SHADER_TESS_CTRL];
1931 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1932 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1933 } else if (stage == MESA_SHADER_TESS_EVAL) {
1934 if (!radv_pipeline_has_tess(pipeline))
1935 return NULL;
1936 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
1937 return pipeline->shaders[MESA_SHADER_TESS_EVAL];
1938 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1939 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1940 }
1941 return pipeline->shaders[stage];
1942 }
1943
1944 static struct radv_tessellation_state
1945 calculate_tess_state(struct radv_pipeline *pipeline,
1946 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1947 {
1948 unsigned num_tcs_input_cp;
1949 unsigned num_tcs_output_cp;
1950 unsigned lds_size;
1951 unsigned num_patches;
1952 struct radv_tessellation_state tess = {0};
1953
1954 num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1955 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1956 num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
1957
1958 lds_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.lds_size;
1959
1960 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
1961 assert(lds_size <= 65536);
1962 lds_size = align(lds_size, 512) / 512;
1963 } else {
1964 assert(lds_size <= 32768);
1965 lds_size = align(lds_size, 256) / 256;
1966 }
1967 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1968
1969 tess.lds_size = lds_size;
1970
1971 tess.ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1972 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1973 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1974 tess.num_patches = num_patches;
1975
1976 struct radv_shader_variant *tes = radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL);
1977 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1978
1979 switch (tes->info.tes.primitive_mode) {
1980 case GL_TRIANGLES:
1981 type = V_028B6C_TESS_TRIANGLE;
1982 break;
1983 case GL_QUADS:
1984 type = V_028B6C_TESS_QUAD;
1985 break;
1986 case GL_ISOLINES:
1987 type = V_028B6C_TESS_ISOLINE;
1988 break;
1989 }
1990
1991 switch (tes->info.tes.spacing) {
1992 case TESS_SPACING_EQUAL:
1993 partitioning = V_028B6C_PART_INTEGER;
1994 break;
1995 case TESS_SPACING_FRACTIONAL_ODD:
1996 partitioning = V_028B6C_PART_FRAC_ODD;
1997 break;
1998 case TESS_SPACING_FRACTIONAL_EVEN:
1999 partitioning = V_028B6C_PART_FRAC_EVEN;
2000 break;
2001 default:
2002 break;
2003 }
2004
2005 bool ccw = tes->info.tes.ccw;
2006 const VkPipelineTessellationDomainOriginStateCreateInfo *domain_origin_state =
2007 vk_find_struct_const(pCreateInfo->pTessellationState,
2008 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO);
2009
2010 if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT)
2011 ccw = !ccw;
2012
2013 if (tes->info.tes.point_mode)
2014 topology = V_028B6C_OUTPUT_POINT;
2015 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
2016 topology = V_028B6C_OUTPUT_LINE;
2017 else if (ccw)
2018 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
2019 else
2020 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
2021
2022 if (pipeline->device->physical_device->rad_info.has_distributed_tess) {
2023 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
2024 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
2025 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
2026 else
2027 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
2028 } else
2029 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
2030
2031 tess.tf_param = S_028B6C_TYPE(type) |
2032 S_028B6C_PARTITIONING(partitioning) |
2033 S_028B6C_TOPOLOGY(topology) |
2034 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
2035
2036 return tess;
2037 }
2038
2039 static const struct radv_prim_vertex_count prim_size_table[] = {
2040 [V_008958_DI_PT_NONE] = {0, 0},
2041 [V_008958_DI_PT_POINTLIST] = {1, 1},
2042 [V_008958_DI_PT_LINELIST] = {2, 2},
2043 [V_008958_DI_PT_LINESTRIP] = {2, 1},
2044 [V_008958_DI_PT_TRILIST] = {3, 3},
2045 [V_008958_DI_PT_TRIFAN] = {3, 1},
2046 [V_008958_DI_PT_TRISTRIP] = {3, 1},
2047 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
2048 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
2049 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
2050 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
2051 [V_008958_DI_PT_RECTLIST] = {3, 3},
2052 [V_008958_DI_PT_LINELOOP] = {2, 1},
2053 [V_008958_DI_PT_POLYGON] = {3, 1},
2054 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
2055 };
2056
2057 static const struct radv_vs_output_info *get_vs_output_info(const struct radv_pipeline *pipeline)
2058 {
2059 if (radv_pipeline_has_gs(pipeline))
2060 if (radv_pipeline_has_ngg(pipeline))
2061 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.vs.outinfo;
2062 else
2063 return &pipeline->gs_copy_shader->info.vs.outinfo;
2064 else if (radv_pipeline_has_tess(pipeline))
2065 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
2066 else
2067 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
2068 }
2069
2070 static void
2071 radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
2072 {
2073 nir_shader* ordered_shaders[MESA_SHADER_STAGES];
2074 int shader_count = 0;
2075
2076 if(shaders[MESA_SHADER_FRAGMENT]) {
2077 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
2078 }
2079 if(shaders[MESA_SHADER_GEOMETRY]) {
2080 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
2081 }
2082 if(shaders[MESA_SHADER_TESS_EVAL]) {
2083 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
2084 }
2085 if(shaders[MESA_SHADER_TESS_CTRL]) {
2086 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
2087 }
2088 if(shaders[MESA_SHADER_VERTEX]) {
2089 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
2090 }
2091
2092 if (shader_count > 1) {
2093 unsigned first = ordered_shaders[shader_count - 1]->info.stage;
2094 unsigned last = ordered_shaders[0]->info.stage;
2095
2096 if (ordered_shaders[0]->info.stage == MESA_SHADER_FRAGMENT &&
2097 ordered_shaders[1]->info.has_transform_feedback_varyings)
2098 nir_link_xfb_varyings(ordered_shaders[1], ordered_shaders[0]);
2099
2100 for (int i = 0; i < shader_count; ++i) {
2101 nir_variable_mode mask = 0;
2102
2103 if (ordered_shaders[i]->info.stage != first)
2104 mask = mask | nir_var_shader_in;
2105
2106 if (ordered_shaders[i]->info.stage != last)
2107 mask = mask | nir_var_shader_out;
2108
2109 nir_lower_io_to_scalar_early(ordered_shaders[i], mask);
2110 radv_optimize_nir(ordered_shaders[i], false, false);
2111 }
2112 }
2113
2114 for (int i = 1; i < shader_count; ++i) {
2115 nir_lower_io_arrays_to_elements(ordered_shaders[i],
2116 ordered_shaders[i - 1]);
2117
2118 if (nir_link_opt_varyings(ordered_shaders[i],
2119 ordered_shaders[i - 1]))
2120 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2121
2122 nir_remove_dead_variables(ordered_shaders[i],
2123 nir_var_shader_out);
2124 nir_remove_dead_variables(ordered_shaders[i - 1],
2125 nir_var_shader_in);
2126
2127 bool progress = nir_remove_unused_varyings(ordered_shaders[i],
2128 ordered_shaders[i - 1]);
2129
2130 nir_compact_varyings(ordered_shaders[i],
2131 ordered_shaders[i - 1], true);
2132
2133 if (progress) {
2134 if (nir_lower_global_vars_to_local(ordered_shaders[i])) {
2135 ac_lower_indirect_derefs(ordered_shaders[i],
2136 pipeline->device->physical_device->rad_info.chip_class);
2137 }
2138 radv_optimize_nir(ordered_shaders[i], false, false);
2139
2140 if (nir_lower_global_vars_to_local(ordered_shaders[i - 1])) {
2141 ac_lower_indirect_derefs(ordered_shaders[i - 1],
2142 pipeline->device->physical_device->rad_info.chip_class);
2143 }
2144 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2145 }
2146 }
2147 }
2148
2149 static uint32_t
2150 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo *input_state,
2151 uint32_t attrib_binding)
2152 {
2153 for (uint32_t i = 0; i < input_state->vertexBindingDescriptionCount; i++) {
2154 const VkVertexInputBindingDescription *input_binding =
2155 &input_state->pVertexBindingDescriptions[i];
2156
2157 if (input_binding->binding == attrib_binding)
2158 return input_binding->stride;
2159 }
2160
2161 return 0;
2162 }
2163
2164 static struct radv_pipeline_key
2165 radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
2166 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2167 const struct radv_blend_state *blend,
2168 bool has_view_index)
2169 {
2170 const VkPipelineVertexInputStateCreateInfo *input_state =
2171 pCreateInfo->pVertexInputState;
2172 const VkPipelineVertexInputDivisorStateCreateInfoEXT *divisor_state =
2173 vk_find_struct_const(input_state->pNext, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT);
2174
2175 struct radv_pipeline_key key;
2176 memset(&key, 0, sizeof(key));
2177
2178 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
2179 key.optimisations_disabled = 1;
2180
2181 key.has_multiview_view_index = has_view_index;
2182
2183 uint32_t binding_input_rate = 0;
2184 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
2185 for (unsigned i = 0; i < input_state->vertexBindingDescriptionCount; ++i) {
2186 if (input_state->pVertexBindingDescriptions[i].inputRate) {
2187 unsigned binding = input_state->pVertexBindingDescriptions[i].binding;
2188 binding_input_rate |= 1u << binding;
2189 instance_rate_divisors[binding] = 1;
2190 }
2191 }
2192 if (divisor_state) {
2193 for (unsigned i = 0; i < divisor_state->vertexBindingDivisorCount; ++i) {
2194 instance_rate_divisors[divisor_state->pVertexBindingDivisors[i].binding] =
2195 divisor_state->pVertexBindingDivisors[i].divisor;
2196 }
2197 }
2198
2199 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
2200 const VkVertexInputAttributeDescription *desc =
2201 &input_state->pVertexAttributeDescriptions[i];
2202 const struct vk_format_description *format_desc;
2203 unsigned location = desc->location;
2204 unsigned binding = desc->binding;
2205 unsigned num_format, data_format;
2206 int first_non_void;
2207
2208 if (binding_input_rate & (1u << binding)) {
2209 key.instance_rate_inputs |= 1u << location;
2210 key.instance_rate_divisors[location] = instance_rate_divisors[binding];
2211 }
2212
2213 format_desc = vk_format_description(desc->format);
2214 first_non_void = vk_format_get_first_non_void_channel(desc->format);
2215
2216 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
2217 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
2218
2219 key.vertex_attribute_formats[location] = data_format | (num_format << 4);
2220 key.vertex_attribute_bindings[location] = desc->binding;
2221 key.vertex_attribute_offsets[location] = desc->offset;
2222 key.vertex_attribute_strides[location] = radv_get_attrib_stride(input_state, desc->binding);
2223
2224 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8 &&
2225 pipeline->device->physical_device->rad_info.family != CHIP_STONEY) {
2226 VkFormat format = input_state->pVertexAttributeDescriptions[i].format;
2227 uint64_t adjust;
2228 switch(format) {
2229 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2230 case VK_FORMAT_A2B10G10R10_SNORM_PACK32:
2231 adjust = RADV_ALPHA_ADJUST_SNORM;
2232 break;
2233 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2234 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32:
2235 adjust = RADV_ALPHA_ADJUST_SSCALED;
2236 break;
2237 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2238 case VK_FORMAT_A2B10G10R10_SINT_PACK32:
2239 adjust = RADV_ALPHA_ADJUST_SINT;
2240 break;
2241 default:
2242 adjust = 0;
2243 break;
2244 }
2245 key.vertex_alpha_adjust |= adjust << (2 * location);
2246 }
2247
2248 switch (desc->format) {
2249 case VK_FORMAT_B8G8R8A8_UNORM:
2250 case VK_FORMAT_B8G8R8A8_SNORM:
2251 case VK_FORMAT_B8G8R8A8_USCALED:
2252 case VK_FORMAT_B8G8R8A8_SSCALED:
2253 case VK_FORMAT_B8G8R8A8_UINT:
2254 case VK_FORMAT_B8G8R8A8_SINT:
2255 case VK_FORMAT_B8G8R8A8_SRGB:
2256 case VK_FORMAT_A2R10G10B10_UNORM_PACK32:
2257 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2258 case VK_FORMAT_A2R10G10B10_USCALED_PACK32:
2259 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2260 case VK_FORMAT_A2R10G10B10_UINT_PACK32:
2261 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2262 key.vertex_post_shuffle |= 1 << location;
2263 break;
2264 default:
2265 break;
2266 }
2267 }
2268
2269 if (pCreateInfo->pTessellationState)
2270 key.tess_input_vertices = pCreateInfo->pTessellationState->patchControlPoints;
2271
2272
2273 if (pCreateInfo->pMultisampleState &&
2274 pCreateInfo->pMultisampleState->rasterizationSamples > 1) {
2275 uint32_t num_samples = pCreateInfo->pMultisampleState->rasterizationSamples;
2276 uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo->pMultisampleState);
2277 key.num_samples = num_samples;
2278 key.log2_ps_iter_samples = util_logbase2(ps_iter_samples);
2279 }
2280
2281 key.col_format = blend->spi_shader_col_format;
2282 if (pipeline->device->physical_device->rad_info.chip_class < GFX8)
2283 radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.is_int8, &key.is_int10);
2284
2285 return key;
2286 }
2287
2288 static bool
2289 radv_nir_stage_uses_xfb(const nir_shader *nir)
2290 {
2291 nir_xfb_info *xfb = nir_gather_xfb_info(nir, NULL);
2292 bool uses_xfb = !!xfb;
2293
2294 ralloc_free(xfb);
2295 return uses_xfb;
2296 }
2297
2298 static void
2299 radv_fill_shader_keys(struct radv_device *device,
2300 struct radv_shader_variant_key *keys,
2301 const struct radv_pipeline_key *key,
2302 nir_shader **nir)
2303 {
2304 keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
2305 keys[MESA_SHADER_VERTEX].vs.alpha_adjust = key->vertex_alpha_adjust;
2306 keys[MESA_SHADER_VERTEX].vs.post_shuffle = key->vertex_post_shuffle;
2307 for (unsigned i = 0; i < MAX_VERTEX_ATTRIBS; ++i) {
2308 keys[MESA_SHADER_VERTEX].vs.instance_rate_divisors[i] = key->instance_rate_divisors[i];
2309 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_formats[i] = key->vertex_attribute_formats[i];
2310 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_bindings[i] = key->vertex_attribute_bindings[i];
2311 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_offsets[i] = key->vertex_attribute_offsets[i];
2312 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_strides[i] = key->vertex_attribute_strides[i];
2313 }
2314
2315 if (nir[MESA_SHADER_TESS_CTRL]) {
2316 keys[MESA_SHADER_VERTEX].vs_common_out.as_ls = true;
2317 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = 0;
2318 keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices;
2319 keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
2320
2321 keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
2322 }
2323
2324 if (nir[MESA_SHADER_GEOMETRY]) {
2325 if (nir[MESA_SHADER_TESS_CTRL])
2326 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_es = true;
2327 else
2328 keys[MESA_SHADER_VERTEX].vs_common_out.as_es = true;
2329 }
2330
2331 if (device->physical_device->rad_info.chip_class >= GFX10 &&
2332 device->physical_device->rad_info.family != CHIP_NAVI14 &&
2333 !(device->instance->debug_flags & RADV_DEBUG_NO_NGG)) {
2334 if (nir[MESA_SHADER_TESS_CTRL]) {
2335 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = true;
2336 } else {
2337 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = true;
2338 }
2339
2340 if (nir[MESA_SHADER_TESS_CTRL] &&
2341 nir[MESA_SHADER_GEOMETRY] &&
2342 nir[MESA_SHADER_GEOMETRY]->info.gs.invocations *
2343 nir[MESA_SHADER_GEOMETRY]->info.gs.vertices_out > 256) {
2344 /* Fallback to the legacy path if tessellation is
2345 * enabled with extreme geometry because
2346 * EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it
2347 * might hang.
2348 */
2349 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2350 }
2351
2352 /*
2353 * Disable NGG with geometry shaders. There are a bunch of
2354 * issues still:
2355 * * GS primitives in pipeline statistic queries do not get
2356 * updates. See dEQP-VK.query_pool.statistics_query.geometry_shader_primitives
2357 * * dEQP-VK.clipping.user_defined.clip_cull_distance_dynamic_index.*geom* failures
2358 * * Interactions with tessellation failing:
2359 * dEQP-VK.tessellation.geometry_interaction.passthrough.tessellate_isolines_passthrough_geometry_no_change
2360 * * General issues with the last primitive missing/corrupt:
2361 * https://bugs.freedesktop.org/show_bug.cgi?id=111248
2362 *
2363 * Furthermore, XGL/AMDVLK also disables this as of 9b632ef.
2364 */
2365 if (nir[MESA_SHADER_GEOMETRY]) {
2366 if (nir[MESA_SHADER_TESS_CTRL])
2367 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2368 else
2369 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2370 }
2371
2372 /* TODO: Implement streamout support for NGG. */
2373 gl_shader_stage last_xfb_stage = MESA_SHADER_VERTEX;
2374
2375 for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
2376 if (nir[i])
2377 last_xfb_stage = i;
2378 }
2379
2380 if (nir[last_xfb_stage] &&
2381 radv_nir_stage_uses_xfb(nir[last_xfb_stage])) {
2382 if (nir[MESA_SHADER_TESS_CTRL])
2383 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2384 else
2385 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2386 }
2387 }
2388
2389 for(int i = 0; i < MESA_SHADER_STAGES; ++i)
2390 keys[i].has_multiview_view_index = key->has_multiview_view_index;
2391
2392 keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format;
2393 keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8;
2394 keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
2395 keys[MESA_SHADER_FRAGMENT].fs.log2_ps_iter_samples = key->log2_ps_iter_samples;
2396 keys[MESA_SHADER_FRAGMENT].fs.num_samples = key->num_samples;
2397 }
2398
2399 static void
2400 merge_tess_info(struct shader_info *tes_info,
2401 const struct shader_info *tcs_info)
2402 {
2403 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2404 *
2405 * "PointMode. Controls generation of points rather than triangles
2406 * or lines. This functionality defaults to disabled, and is
2407 * enabled if either shader stage includes the execution mode.
2408 *
2409 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2410 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2411 * and OutputVertices, it says:
2412 *
2413 * "One mode must be set in at least one of the tessellation
2414 * shader stages."
2415 *
2416 * So, the fields can be set in either the TCS or TES, but they must
2417 * agree if set in both. Our backend looks at TES, so bitwise-or in
2418 * the values from the TCS.
2419 */
2420 assert(tcs_info->tess.tcs_vertices_out == 0 ||
2421 tes_info->tess.tcs_vertices_out == 0 ||
2422 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
2423 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
2424
2425 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2426 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2427 tcs_info->tess.spacing == tes_info->tess.spacing);
2428 tes_info->tess.spacing |= tcs_info->tess.spacing;
2429
2430 assert(tcs_info->tess.primitive_mode == 0 ||
2431 tes_info->tess.primitive_mode == 0 ||
2432 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
2433 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
2434 tes_info->tess.ccw |= tcs_info->tess.ccw;
2435 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
2436 }
2437
2438 static
2439 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT *ext)
2440 {
2441 if (!ext)
2442 return;
2443
2444 if (ext->pPipelineCreationFeedback) {
2445 ext->pPipelineCreationFeedback->flags = 0;
2446 ext->pPipelineCreationFeedback->duration = 0;
2447 }
2448
2449 for (unsigned i = 0; i < ext->pipelineStageCreationFeedbackCount; ++i) {
2450 ext->pPipelineStageCreationFeedbacks[i].flags = 0;
2451 ext->pPipelineStageCreationFeedbacks[i].duration = 0;
2452 }
2453 }
2454
2455 static
2456 void radv_start_feedback(VkPipelineCreationFeedbackEXT *feedback)
2457 {
2458 if (!feedback)
2459 return;
2460
2461 feedback->duration -= radv_get_current_time();
2462 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT;
2463 }
2464
2465 static
2466 void radv_stop_feedback(VkPipelineCreationFeedbackEXT *feedback, bool cache_hit)
2467 {
2468 if (!feedback)
2469 return;
2470
2471 feedback->duration += radv_get_current_time();
2472 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT |
2473 (cache_hit ? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT : 0);
2474 }
2475
2476 static
2477 void radv_create_shaders(struct radv_pipeline *pipeline,
2478 struct radv_device *device,
2479 struct radv_pipeline_cache *cache,
2480 const struct radv_pipeline_key *key,
2481 const VkPipelineShaderStageCreateInfo **pStages,
2482 const VkPipelineCreateFlags flags,
2483 VkPipelineCreationFeedbackEXT *pipeline_feedback,
2484 VkPipelineCreationFeedbackEXT **stage_feedbacks)
2485 {
2486 struct radv_shader_module fs_m = {0};
2487 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
2488 nir_shader *nir[MESA_SHADER_STAGES] = {0};
2489 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2490 struct radv_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{{0}}}}};
2491 unsigned char hash[20], gs_copy_hash[20];
2492 bool keep_executable_info = (flags & VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR) || device->keep_shader_info;
2493
2494 radv_start_feedback(pipeline_feedback);
2495
2496 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2497 if (pStages[i]) {
2498 modules[i] = radv_shader_module_from_handle(pStages[i]->module);
2499 if (modules[i]->nir)
2500 _mesa_sha1_compute(modules[i]->nir->info.name,
2501 strlen(modules[i]->nir->info.name),
2502 modules[i]->sha1);
2503
2504 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
2505 }
2506 }
2507
2508 radv_hash_shaders(hash, pStages, pipeline->layout, key, get_hash_flags(device));
2509 memcpy(gs_copy_hash, hash, 20);
2510 gs_copy_hash[0] ^= 1;
2511
2512 bool found_in_application_cache = true;
2513 if (modules[MESA_SHADER_GEOMETRY] && !keep_executable_info) {
2514 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2515 radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants,
2516 &found_in_application_cache);
2517 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
2518 }
2519
2520 if (!keep_executable_info &&
2521 radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders,
2522 &found_in_application_cache) &&
2523 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
2524 radv_stop_feedback(pipeline_feedback, found_in_application_cache);
2525 return;
2526 }
2527
2528 if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
2529 nir_builder fs_b;
2530 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
2531 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
2532 fs_m.nir = fs_b.shader;
2533 modules[MESA_SHADER_FRAGMENT] = &fs_m;
2534 }
2535
2536 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2537 const VkPipelineShaderStageCreateInfo *stage = pStages[i];
2538
2539 if (!modules[i])
2540 continue;
2541
2542 radv_start_feedback(stage_feedbacks[i]);
2543
2544 nir[i] = radv_shader_compile_to_nir(device, modules[i],
2545 stage ? stage->pName : "main", i,
2546 stage ? stage->pSpecializationInfo : NULL,
2547 flags, pipeline->layout);
2548
2549 /* We don't want to alter meta shaders IR directly so clone it
2550 * first.
2551 */
2552 if (nir[i]->info.name) {
2553 nir[i] = nir_shader_clone(NULL, nir[i]);
2554 }
2555
2556 radv_stop_feedback(stage_feedbacks[i], false);
2557 }
2558
2559 if (nir[MESA_SHADER_TESS_CTRL]) {
2560 nir_lower_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out, NULL);
2561 merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
2562 }
2563
2564 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
2565 radv_link_shaders(pipeline, nir);
2566
2567 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2568 if (nir[i]) {
2569 NIR_PASS_V(nir[i], nir_lower_non_uniform_access,
2570 nir_lower_non_uniform_ubo_access |
2571 nir_lower_non_uniform_ssbo_access |
2572 nir_lower_non_uniform_texture_access |
2573 nir_lower_non_uniform_image_access);
2574 NIR_PASS_V(nir[i], nir_lower_bool_to_int32);
2575 }
2576
2577 if (radv_can_dump_shader(device, modules[i], false))
2578 nir_print_shader(nir[i], stderr);
2579 }
2580
2581 radv_fill_shader_keys(device, keys, key, nir);
2582
2583 if (nir[MESA_SHADER_FRAGMENT]) {
2584 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
2585 radv_start_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT]);
2586
2587 pipeline->shaders[MESA_SHADER_FRAGMENT] =
2588 radv_shader_variant_compile(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
2589 pipeline->layout, keys + MESA_SHADER_FRAGMENT,
2590 keep_executable_info, &binaries[MESA_SHADER_FRAGMENT]);
2591
2592 radv_stop_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT], false);
2593 }
2594
2595 /* TODO: These are no longer used as keys we should refactor this */
2596 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id =
2597 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input;
2598 keys[MESA_SHADER_VERTEX].vs_common_out.export_layer_id =
2599 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.layer_input;
2600 keys[MESA_SHADER_VERTEX].vs_common_out.export_clip_dists =
2601 !!pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.num_input_clips_culls;
2602 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_prim_id =
2603 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input;
2604 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_layer_id =
2605 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.layer_input;
2606 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_clip_dists =
2607 !!pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.num_input_clips_culls;
2608 }
2609
2610 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
2611 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
2612 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2613 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2614 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2615
2616 radv_start_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL]);
2617
2618 pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_compile(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
2619 pipeline->layout,
2620 &key, keep_executable_info,
2621 &binaries[MESA_SHADER_TESS_CTRL]);
2622
2623 radv_stop_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL], false);
2624 }
2625 modules[MESA_SHADER_VERTEX] = NULL;
2626 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2627 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.tcs.outputs_written);
2628 }
2629
2630 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
2631 gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2632 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
2633 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2634
2635 radv_start_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY]);
2636
2637 pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_compile(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
2638 pipeline->layout,
2639 &keys[pre_stage], keep_executable_info,
2640 &binaries[MESA_SHADER_GEOMETRY]);
2641
2642 radv_stop_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY], false);
2643 }
2644 modules[pre_stage] = NULL;
2645 }
2646
2647 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2648 if(modules[i] && !pipeline->shaders[i]) {
2649 if (i == MESA_SHADER_TESS_CTRL) {
2650 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.ls_outputs_written);
2651 }
2652 if (i == MESA_SHADER_TESS_EVAL) {
2653 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2654 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.tcs.outputs_written);
2655 }
2656
2657 radv_start_feedback(stage_feedbacks[i]);
2658
2659 pipeline->shaders[i] = radv_shader_variant_compile(device, modules[i], &nir[i], 1,
2660 pipeline->layout,
2661 keys + i, keep_executable_info,
2662 &binaries[i]);
2663
2664 radv_stop_feedback(stage_feedbacks[i], false);
2665 }
2666 }
2667
2668 if(modules[MESA_SHADER_GEOMETRY]) {
2669 struct radv_shader_binary *gs_copy_binary = NULL;
2670 if (!pipeline->gs_copy_shader &&
2671 !radv_pipeline_has_ngg(pipeline)) {
2672 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
2673 device, nir[MESA_SHADER_GEOMETRY], &gs_copy_binary,
2674 keep_executable_info,
2675 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
2676 }
2677
2678 if (!keep_executable_info && pipeline->gs_copy_shader) {
2679 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2680 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2681
2682 binaries[MESA_SHADER_GEOMETRY] = gs_copy_binary;
2683 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
2684
2685 radv_pipeline_cache_insert_shaders(device, cache,
2686 gs_copy_hash,
2687 variants,
2688 binaries);
2689 }
2690 free(gs_copy_binary);
2691 }
2692
2693 if (!keep_executable_info) {
2694 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
2695 binaries);
2696 }
2697
2698 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2699 free(binaries[i]);
2700 if (nir[i]) {
2701 ralloc_free(nir[i]);
2702
2703 if (radv_can_dump_shader_stats(device, modules[i]))
2704 radv_shader_dump_stats(device,
2705 pipeline->shaders[i],
2706 i, stderr);
2707 }
2708 }
2709
2710 if (fs_m.nir)
2711 ralloc_free(fs_m.nir);
2712
2713 radv_stop_feedback(pipeline_feedback, false);
2714 }
2715
2716 static uint32_t
2717 radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
2718 gl_shader_stage stage, enum chip_class chip_class)
2719 {
2720 bool has_gs = radv_pipeline_has_gs(pipeline);
2721 bool has_tess = radv_pipeline_has_tess(pipeline);
2722 bool has_ngg = radv_pipeline_has_ngg(pipeline);
2723
2724 switch (stage) {
2725 case MESA_SHADER_FRAGMENT:
2726 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
2727 case MESA_SHADER_VERTEX:
2728 if (has_tess) {
2729 if (chip_class >= GFX10) {
2730 return R_00B430_SPI_SHADER_USER_DATA_HS_0;
2731 } else if (chip_class == GFX9) {
2732 return R_00B430_SPI_SHADER_USER_DATA_LS_0;
2733 } else {
2734 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
2735 }
2736
2737 }
2738
2739 if (has_gs) {
2740 if (chip_class >= GFX10) {
2741 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
2742 } else {
2743 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
2744 }
2745 }
2746
2747 if (has_ngg)
2748 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
2749
2750 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
2751 case MESA_SHADER_GEOMETRY:
2752 return chip_class == GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
2753 R_00B230_SPI_SHADER_USER_DATA_GS_0;
2754 case MESA_SHADER_COMPUTE:
2755 return R_00B900_COMPUTE_USER_DATA_0;
2756 case MESA_SHADER_TESS_CTRL:
2757 return chip_class == GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
2758 R_00B430_SPI_SHADER_USER_DATA_HS_0;
2759 case MESA_SHADER_TESS_EVAL:
2760 if (has_gs) {
2761 return chip_class >= GFX10 ? R_00B230_SPI_SHADER_USER_DATA_GS_0 :
2762 R_00B330_SPI_SHADER_USER_DATA_ES_0;
2763 } else if (has_ngg) {
2764 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
2765 } else {
2766 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
2767 }
2768 default:
2769 unreachable("unknown shader");
2770 }
2771 }
2772
2773 struct radv_bin_size_entry {
2774 unsigned bpp;
2775 VkExtent2D extent;
2776 };
2777
2778 static VkExtent2D
2779 radv_gfx9_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
2780 {
2781 static const struct radv_bin_size_entry color_size_table[][3][9] = {
2782 {
2783 /* One RB / SE */
2784 {
2785 /* One shader engine */
2786 { 0, {128, 128}},
2787 { 1, { 64, 128}},
2788 { 2, { 32, 128}},
2789 { 3, { 16, 128}},
2790 { 17, { 0, 0}},
2791 { UINT_MAX, { 0, 0}},
2792 },
2793 {
2794 /* Two shader engines */
2795 { 0, {128, 128}},
2796 { 2, { 64, 128}},
2797 { 3, { 32, 128}},
2798 { 5, { 16, 128}},
2799 { 17, { 0, 0}},
2800 { UINT_MAX, { 0, 0}},
2801 },
2802 {
2803 /* Four shader engines */
2804 { 0, {128, 128}},
2805 { 3, { 64, 128}},
2806 { 5, { 16, 128}},
2807 { 17, { 0, 0}},
2808 { UINT_MAX, { 0, 0}},
2809 },
2810 },
2811 {
2812 /* Two RB / SE */
2813 {
2814 /* One shader engine */
2815 { 0, {128, 128}},
2816 { 2, { 64, 128}},
2817 { 3, { 32, 128}},
2818 { 5, { 16, 128}},
2819 { 33, { 0, 0}},
2820 { UINT_MAX, { 0, 0}},
2821 },
2822 {
2823 /* Two shader engines */
2824 { 0, {128, 128}},
2825 { 3, { 64, 128}},
2826 { 5, { 32, 128}},
2827 { 9, { 16, 128}},
2828 { 33, { 0, 0}},
2829 { UINT_MAX, { 0, 0}},
2830 },
2831 {
2832 /* Four shader engines */
2833 { 0, {256, 256}},
2834 { 2, {128, 256}},
2835 { 3, {128, 128}},
2836 { 5, { 64, 128}},
2837 { 9, { 16, 128}},
2838 { 33, { 0, 0}},
2839 { UINT_MAX, { 0, 0}},
2840 },
2841 },
2842 {
2843 /* Four RB / SE */
2844 {
2845 /* One shader engine */
2846 { 0, {128, 256}},
2847 { 2, {128, 128}},
2848 { 3, { 64, 128}},
2849 { 5, { 32, 128}},
2850 { 9, { 16, 128}},
2851 { 33, { 0, 0}},
2852 { UINT_MAX, { 0, 0}},
2853 },
2854 {
2855 /* Two shader engines */
2856 { 0, {256, 256}},
2857 { 2, {128, 256}},
2858 { 3, {128, 128}},
2859 { 5, { 64, 128}},
2860 { 9, { 32, 128}},
2861 { 17, { 16, 128}},
2862 { 33, { 0, 0}},
2863 { UINT_MAX, { 0, 0}},
2864 },
2865 {
2866 /* Four shader engines */
2867 { 0, {256, 512}},
2868 { 2, {256, 256}},
2869 { 3, {128, 256}},
2870 { 5, {128, 128}},
2871 { 9, { 64, 128}},
2872 { 17, { 16, 128}},
2873 { 33, { 0, 0}},
2874 { UINT_MAX, { 0, 0}},
2875 },
2876 },
2877 };
2878 static const struct radv_bin_size_entry ds_size_table[][3][9] = {
2879 {
2880 // One RB / SE
2881 {
2882 // One shader engine
2883 { 0, {128, 256}},
2884 { 2, {128, 128}},
2885 { 4, { 64, 128}},
2886 { 7, { 32, 128}},
2887 { 13, { 16, 128}},
2888 { 49, { 0, 0}},
2889 { UINT_MAX, { 0, 0}},
2890 },
2891 {
2892 // Two shader engines
2893 { 0, {256, 256}},
2894 { 2, {128, 256}},
2895 { 4, {128, 128}},
2896 { 7, { 64, 128}},
2897 { 13, { 32, 128}},
2898 { 25, { 16, 128}},
2899 { 49, { 0, 0}},
2900 { UINT_MAX, { 0, 0}},
2901 },
2902 {
2903 // Four shader engines
2904 { 0, {256, 512}},
2905 { 2, {256, 256}},
2906 { 4, {128, 256}},
2907 { 7, {128, 128}},
2908 { 13, { 64, 128}},
2909 { 25, { 16, 128}},
2910 { 49, { 0, 0}},
2911 { UINT_MAX, { 0, 0}},
2912 },
2913 },
2914 {
2915 // Two RB / SE
2916 {
2917 // One shader engine
2918 { 0, {256, 256}},
2919 { 2, {128, 256}},
2920 { 4, {128, 128}},
2921 { 7, { 64, 128}},
2922 { 13, { 32, 128}},
2923 { 25, { 16, 128}},
2924 { 97, { 0, 0}},
2925 { UINT_MAX, { 0, 0}},
2926 },
2927 {
2928 // Two shader engines
2929 { 0, {256, 512}},
2930 { 2, {256, 256}},
2931 { 4, {128, 256}},
2932 { 7, {128, 128}},
2933 { 13, { 64, 128}},
2934 { 25, { 32, 128}},
2935 { 49, { 16, 128}},
2936 { 97, { 0, 0}},
2937 { UINT_MAX, { 0, 0}},
2938 },
2939 {
2940 // Four shader engines
2941 { 0, {512, 512}},
2942 { 2, {256, 512}},
2943 { 4, {256, 256}},
2944 { 7, {128, 256}},
2945 { 13, {128, 128}},
2946 { 25, { 64, 128}},
2947 { 49, { 16, 128}},
2948 { 97, { 0, 0}},
2949 { UINT_MAX, { 0, 0}},
2950 },
2951 },
2952 {
2953 // Four RB / SE
2954 {
2955 // One shader engine
2956 { 0, {256, 512}},
2957 { 2, {256, 256}},
2958 { 4, {128, 256}},
2959 { 7, {128, 128}},
2960 { 13, { 64, 128}},
2961 { 25, { 32, 128}},
2962 { 49, { 16, 128}},
2963 { UINT_MAX, { 0, 0}},
2964 },
2965 {
2966 // Two shader engines
2967 { 0, {512, 512}},
2968 { 2, {256, 512}},
2969 { 4, {256, 256}},
2970 { 7, {128, 256}},
2971 { 13, {128, 128}},
2972 { 25, { 64, 128}},
2973 { 49, { 32, 128}},
2974 { 97, { 16, 128}},
2975 { UINT_MAX, { 0, 0}},
2976 },
2977 {
2978 // Four shader engines
2979 { 0, {512, 512}},
2980 { 4, {256, 512}},
2981 { 7, {256, 256}},
2982 { 13, {128, 256}},
2983 { 25, {128, 128}},
2984 { 49, { 64, 128}},
2985 { 97, { 16, 128}},
2986 { UINT_MAX, { 0, 0}},
2987 },
2988 },
2989 };
2990
2991 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2992 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2993 VkExtent2D extent = {512, 512};
2994
2995 unsigned log_num_rb_per_se =
2996 util_logbase2_ceil(pipeline->device->physical_device->rad_info.num_render_backends /
2997 pipeline->device->physical_device->rad_info.max_se);
2998 unsigned log_num_se = util_logbase2_ceil(pipeline->device->physical_device->rad_info.max_se);
2999
3000 unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
3001 unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->graphics.ms.db_eqaa);
3002 unsigned effective_samples = total_samples;
3003 unsigned color_bytes_per_pixel = 0;
3004
3005 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
3006 if (vkblend) {
3007 for (unsigned i = 0; i < subpass->color_count; i++) {
3008 if (!vkblend->pAttachments[i].colorWriteMask)
3009 continue;
3010
3011 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3012 continue;
3013
3014 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3015 color_bytes_per_pixel += vk_format_get_blocksize(format);
3016 }
3017
3018 /* MSAA images typically don't use all samples all the time. */
3019 if (effective_samples >= 2 && ps_iter_samples <= 1)
3020 effective_samples = 2;
3021 color_bytes_per_pixel *= effective_samples;
3022 }
3023
3024 const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se];
3025 while(color_entry[1].bpp <= color_bytes_per_pixel)
3026 ++color_entry;
3027
3028 extent = color_entry->extent;
3029
3030 if (subpass->depth_stencil_attachment) {
3031 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3032
3033 /* Coefficients taken from AMDVLK */
3034 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
3035 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
3036 unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples;
3037
3038 const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se];
3039 while(ds_entry[1].bpp <= ds_bytes_per_pixel)
3040 ++ds_entry;
3041
3042 if (ds_entry->extent.width * ds_entry->extent.height < extent.width * extent.height)
3043 extent = ds_entry->extent;
3044 }
3045
3046 return extent;
3047 }
3048
3049 static VkExtent2D
3050 radv_gfx10_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
3051 {
3052 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3053 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3054 VkExtent2D extent = {512, 512};
3055
3056 unsigned sdp_interface_count;
3057
3058 switch(pipeline->device->physical_device->rad_info.family) {
3059 case CHIP_NAVI10:
3060 case CHIP_NAVI12:
3061 sdp_interface_count = 16;
3062 break;
3063 case CHIP_NAVI14:
3064 sdp_interface_count = 8;
3065 break;
3066 default:
3067 unreachable("Unhandled GFX10 chip");
3068 }
3069
3070 const unsigned db_tag_size = 64;
3071 const unsigned db_tag_count = 312;
3072 const unsigned color_tag_size = 1024;
3073 const unsigned color_tag_count = 31;
3074 const unsigned fmask_tag_size = 256;
3075 const unsigned fmask_tag_count = 44;
3076
3077 const unsigned rb_count = pipeline->device->physical_device->rad_info.num_render_backends;
3078 const unsigned pipe_count = MAX2(rb_count, sdp_interface_count);
3079
3080 const unsigned db_tag_part = (db_tag_count * rb_count / pipe_count) * db_tag_size * pipe_count;
3081 const unsigned color_tag_part = (color_tag_count * rb_count / pipe_count) * color_tag_size * pipe_count;
3082 const unsigned fmask_tag_part = (fmask_tag_count * rb_count / pipe_count) * fmask_tag_size * pipe_count;
3083
3084 const unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
3085 const unsigned samples_log = util_logbase2_ceil(total_samples);
3086
3087 unsigned color_bytes_per_pixel = 0;
3088 unsigned fmask_bytes_per_pixel = 0;
3089
3090 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
3091 if (vkblend) {
3092 for (unsigned i = 0; i < subpass->color_count; i++) {
3093 if (!vkblend->pAttachments[i].colorWriteMask)
3094 continue;
3095
3096 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3097 continue;
3098
3099 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3100 color_bytes_per_pixel += vk_format_get_blocksize(format);
3101
3102 if (total_samples > 1) {
3103 const unsigned fmask_array[] = {0, 1, 1, 4};
3104 fmask_bytes_per_pixel += fmask_array[samples_log];
3105 }
3106 }
3107
3108 color_bytes_per_pixel *= total_samples;
3109 }
3110 color_bytes_per_pixel = MAX2(color_bytes_per_pixel, 1);
3111
3112 const unsigned color_pixel_count_log = util_logbase2(color_tag_part / color_bytes_per_pixel);
3113 extent.width = 1ull << ((color_pixel_count_log + 1) / 2);
3114 extent.height = 1ull << (color_pixel_count_log / 2);
3115
3116 if (fmask_bytes_per_pixel) {
3117 const unsigned fmask_pixel_count_log = util_logbase2(fmask_tag_part / fmask_bytes_per_pixel);
3118
3119 const VkExtent2D fmask_extent = (VkExtent2D){
3120 .width = 1ull << ((fmask_pixel_count_log + 1) / 2),
3121 .height = 1ull << (color_pixel_count_log / 2)
3122 };
3123
3124 if (fmask_extent.width * fmask_extent.height < extent.width * extent.height)
3125 extent = fmask_extent;
3126 }
3127
3128 if (subpass->depth_stencil_attachment) {
3129 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3130
3131 /* Coefficients taken from AMDVLK */
3132 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
3133 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
3134 unsigned db_bytes_per_pixel = (depth_coeff + stencil_coeff) * total_samples;
3135
3136 const unsigned db_pixel_count_log = util_logbase2(db_tag_part / db_bytes_per_pixel);
3137
3138 const VkExtent2D db_extent = (VkExtent2D){
3139 .width = 1ull << ((db_pixel_count_log + 1) / 2),
3140 .height = 1ull << (color_pixel_count_log / 2)
3141 };
3142
3143 if (db_extent.width * db_extent.height < extent.width * extent.height)
3144 extent = db_extent;
3145 }
3146
3147 extent.width = MAX2(extent.width, 128);
3148 extent.height = MAX2(extent.width, 64);
3149
3150 return extent;
3151 }
3152
3153 static void
3154 radv_pipeline_generate_disabled_binning_state(struct radeon_cmdbuf *ctx_cs,
3155 struct radv_pipeline *pipeline,
3156 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3157 {
3158 uint32_t pa_sc_binner_cntl_0 =
3159 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
3160 S_028C44_DISABLE_START_OF_PRIM(1);
3161 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
3162
3163 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3164 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3165 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3166 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
3167 unsigned min_bytes_per_pixel = 0;
3168
3169 if (vkblend) {
3170 for (unsigned i = 0; i < subpass->color_count; i++) {
3171 if (!vkblend->pAttachments[i].colorWriteMask)
3172 continue;
3173
3174 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3175 continue;
3176
3177 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3178 unsigned bytes = vk_format_get_blocksize(format);
3179 if (!min_bytes_per_pixel || bytes < min_bytes_per_pixel)
3180 min_bytes_per_pixel = bytes;
3181 }
3182 }
3183
3184 pa_sc_binner_cntl_0 =
3185 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC) |
3186 S_028C44_BIN_SIZE_X(0) |
3187 S_028C44_BIN_SIZE_Y(0) |
3188 S_028C44_BIN_SIZE_X_EXTEND(2) | /* 128 */
3189 S_028C44_BIN_SIZE_Y_EXTEND(min_bytes_per_pixel <= 4 ? 2 : 1) | /* 128 or 64 */
3190 S_028C44_DISABLE_START_OF_PRIM(1);
3191 }
3192
3193 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
3194 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
3195 }
3196
3197 static void
3198 radv_pipeline_generate_binning_state(struct radeon_cmdbuf *ctx_cs,
3199 struct radv_pipeline *pipeline,
3200 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3201 {
3202 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
3203 return;
3204
3205 VkExtent2D bin_size;
3206 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3207 bin_size = radv_gfx10_compute_bin_size(pipeline, pCreateInfo);
3208 } else if (pipeline->device->physical_device->rad_info.chip_class == GFX9) {
3209 bin_size = radv_gfx9_compute_bin_size(pipeline, pCreateInfo);
3210 } else
3211 unreachable("Unhandled generation for binning bin size calculation");
3212
3213 if (pipeline->device->pbb_allowed && bin_size.width && bin_size.height) {
3214 unsigned context_states_per_bin; /* allowed range: [1, 6] */
3215 unsigned persistent_states_per_bin; /* allowed range: [1, 32] */
3216 unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */
3217
3218 if (pipeline->device->physical_device->rad_info.has_dedicated_vram) {
3219 context_states_per_bin = 1;
3220 persistent_states_per_bin = 1;
3221 fpovs_per_batch = 63;
3222 } else {
3223 /* The context states are affected by the scissor bug. */
3224 context_states_per_bin = pipeline->device->physical_device->rad_info.has_gfx9_scissor_bug ? 1 : 6;
3225 /* 32 causes hangs for RAVEN. */
3226 persistent_states_per_bin = 16;
3227 fpovs_per_batch = 63;
3228 }
3229
3230 const uint32_t pa_sc_binner_cntl_0 =
3231 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
3232 S_028C44_BIN_SIZE_X(bin_size.width == 16) |
3233 S_028C44_BIN_SIZE_Y(bin_size.height == 16) |
3234 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size.width, 32)) - 5) |
3235 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size.height, 32)) - 5) |
3236 S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin - 1) |
3237 S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin - 1) |
3238 S_028C44_DISABLE_START_OF_PRIM(1) |
3239 S_028C44_FPOVS_PER_BATCH(fpovs_per_batch) |
3240 S_028C44_OPTIMAL_BIN_SELECTION(1);
3241
3242 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
3243
3244 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
3245 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
3246 } else
3247 radv_pipeline_generate_disabled_binning_state(ctx_cs, pipeline, pCreateInfo);
3248 }
3249
3250
3251 static void
3252 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf *ctx_cs,
3253 struct radv_pipeline *pipeline,
3254 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3255 const struct radv_graphics_pipeline_create_info *extra)
3256 {
3257 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
3258 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3259 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3260 struct radv_render_pass_attachment *attachment = NULL;
3261 uint32_t db_depth_control = 0, db_stencil_control = 0;
3262 uint32_t db_render_control = 0, db_render_override2 = 0;
3263 uint32_t db_render_override = 0;
3264
3265 if (subpass->depth_stencil_attachment)
3266 attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3267
3268 bool has_depth_attachment = attachment && vk_format_is_depth(attachment->format);
3269 bool has_stencil_attachment = attachment && vk_format_is_stencil(attachment->format);
3270
3271 if (vkds && has_depth_attachment) {
3272 db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
3273 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
3274 S_028800_ZFUNC(vkds->depthCompareOp) |
3275 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
3276
3277 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
3278 db_render_override2 |= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment->samples > 2);
3279 }
3280
3281 if (has_stencil_attachment && vkds && vkds->stencilTestEnable) {
3282 db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
3283 db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
3284 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
3285 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
3286 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
3287
3288 db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
3289 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
3290 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
3291 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
3292 }
3293
3294 if (attachment && extra) {
3295 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
3296 db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
3297
3298 db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
3299 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
3300 db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
3301 db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
3302 db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
3303 }
3304
3305 db_render_override |= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3306 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
3307
3308 if (!pCreateInfo->pRasterizationState->depthClampEnable) {
3309 /* From VK_EXT_depth_range_unrestricted spec:
3310 *
3311 * "The behavior described in Primitive Clipping still applies.
3312 * If depth clamping is disabled the depth values are still
3313 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
3314 * depth clamping is enabled the above equation is ignored and
3315 * the depth values are instead clamped to the VkViewport
3316 * minDepth and maxDepth values, which in the case of this
3317 * extension can be outside of the 0.0 to 1.0 range."
3318 */
3319 db_render_override |= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
3320 }
3321
3322 radeon_set_context_reg(ctx_cs, R_028800_DB_DEPTH_CONTROL, db_depth_control);
3323 radeon_set_context_reg(ctx_cs, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
3324
3325 radeon_set_context_reg(ctx_cs, R_028000_DB_RENDER_CONTROL, db_render_control);
3326 radeon_set_context_reg(ctx_cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
3327 radeon_set_context_reg(ctx_cs, R_028010_DB_RENDER_OVERRIDE2, db_render_override2);
3328 }
3329
3330 static void
3331 radv_pipeline_generate_blend_state(struct radeon_cmdbuf *ctx_cs,
3332 struct radv_pipeline *pipeline,
3333 const struct radv_blend_state *blend)
3334 {
3335 radeon_set_context_reg_seq(ctx_cs, R_028780_CB_BLEND0_CONTROL, 8);
3336 radeon_emit_array(ctx_cs, blend->cb_blend_control,
3337 8);
3338 radeon_set_context_reg(ctx_cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control);
3339 radeon_set_context_reg(ctx_cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask);
3340
3341 if (pipeline->device->physical_device->rad_info.has_rbplus) {
3342
3343 radeon_set_context_reg_seq(ctx_cs, R_028760_SX_MRT0_BLEND_OPT, 8);
3344 radeon_emit_array(ctx_cs, blend->sx_mrt_blend_opt, 8);
3345 }
3346
3347 radeon_set_context_reg(ctx_cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
3348
3349 radeon_set_context_reg(ctx_cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
3350 radeon_set_context_reg(ctx_cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
3351
3352 pipeline->graphics.col_format = blend->spi_shader_col_format;
3353 pipeline->graphics.cb_target_mask = blend->cb_target_mask;
3354 }
3355
3356 static const VkConservativeRasterizationModeEXT
3357 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo *pCreateInfo)
3358 {
3359 const VkPipelineRasterizationConservativeStateCreateInfoEXT *conservative_raster =
3360 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT);
3361
3362 if (!conservative_raster)
3363 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT;
3364 return conservative_raster->conservativeRasterizationMode;
3365 }
3366
3367 static void
3368 radv_pipeline_generate_raster_state(struct radeon_cmdbuf *ctx_cs,
3369 struct radv_pipeline *pipeline,
3370 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3371 {
3372 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
3373 const VkConservativeRasterizationModeEXT mode =
3374 radv_get_conservative_raster_mode(vkraster);
3375 uint32_t pa_sc_conservative_rast = S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
3376 bool depth_clip_disable = vkraster->depthClampEnable;
3377
3378 const VkPipelineRasterizationDepthClipStateCreateInfoEXT *depth_clip_state =
3379 vk_find_struct_const(vkraster->pNext, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT);
3380 if (depth_clip_state) {
3381 depth_clip_disable = !depth_clip_state->depthClipEnable;
3382 }
3383
3384 radeon_set_context_reg(ctx_cs, R_028810_PA_CL_CLIP_CNTL,
3385 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
3386 S_028810_ZCLIP_NEAR_DISABLE(depth_clip_disable ? 1 : 0) |
3387 S_028810_ZCLIP_FAR_DISABLE(depth_clip_disable ? 1 : 0) |
3388 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
3389 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
3390
3391 radeon_set_context_reg(ctx_cs, R_0286D4_SPI_INTERP_CONTROL_0,
3392 S_0286D4_FLAT_SHADE_ENA(1) |
3393 S_0286D4_PNT_SPRITE_ENA(1) |
3394 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
3395 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
3396 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
3397 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
3398 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
3399
3400 radeon_set_context_reg(ctx_cs, R_028BE4_PA_SU_VTX_CNTL,
3401 S_028BE4_PIX_CENTER(1) | // TODO verify
3402 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
3403 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
3404
3405 radeon_set_context_reg(ctx_cs, R_028814_PA_SU_SC_MODE_CNTL,
3406 S_028814_FACE(vkraster->frontFace) |
3407 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
3408 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
3409 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
3410 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
3411 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
3412 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
3413 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
3414 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0));
3415
3416 /* Conservative rasterization. */
3417 if (mode != VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT) {
3418 struct radv_multisample_state *ms = &pipeline->graphics.ms;
3419
3420 ms->pa_sc_aa_config |= S_028BE0_AA_MASK_CENTROID_DTMN(1);
3421 ms->db_eqaa |= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
3422 S_028804_OVERRASTERIZATION_AMOUNT(4);
3423
3424 pa_sc_conservative_rast = S_028C4C_PREZ_AA_MASK_ENABLE(1) |
3425 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
3426 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
3427
3428 if (mode == VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT) {
3429 pa_sc_conservative_rast |=
3430 S_028C4C_OVER_RAST_ENABLE(1) |
3431 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
3432 S_028C4C_UNDER_RAST_ENABLE(0) |
3433 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
3434 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
3435 } else {
3436 assert(mode == VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT);
3437 pa_sc_conservative_rast |=
3438 S_028C4C_OVER_RAST_ENABLE(0) |
3439 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
3440 S_028C4C_UNDER_RAST_ENABLE(1) |
3441 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
3442 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
3443 }
3444 }
3445
3446 radeon_set_context_reg(ctx_cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
3447 pa_sc_conservative_rast);
3448 }
3449
3450
3451 static void
3452 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf *ctx_cs,
3453 struct radv_pipeline *pipeline)
3454 {
3455 struct radv_multisample_state *ms = &pipeline->graphics.ms;
3456
3457 radeon_set_context_reg_seq(ctx_cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3458 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[0]);
3459 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[1]);
3460
3461 radeon_set_context_reg(ctx_cs, R_028804_DB_EQAA, ms->db_eqaa);
3462 radeon_set_context_reg(ctx_cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
3463
3464 /* The exclusion bits can be set to improve rasterization efficiency
3465 * if no sample lies on the pixel boundary (-8 sample offset). It's
3466 * currently always TRUE because the driver doesn't support 16 samples.
3467 */
3468 bool exclusion = pipeline->device->physical_device->rad_info.chip_class >= GFX7;
3469 radeon_set_context_reg(ctx_cs, R_02882C_PA_SU_PRIM_FILTER_CNTL,
3470 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
3471 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
3472 }
3473
3474 static void
3475 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf *ctx_cs,
3476 struct radv_pipeline *pipeline)
3477 {
3478 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3479 const struct radv_shader_variant *vs =
3480 pipeline->shaders[MESA_SHADER_TESS_EVAL] ?
3481 pipeline->shaders[MESA_SHADER_TESS_EVAL] :
3482 pipeline->shaders[MESA_SHADER_VERTEX];
3483 unsigned vgt_primitiveid_en = 0;
3484 uint32_t vgt_gs_mode = 0;
3485
3486 if (radv_pipeline_has_ngg(pipeline))
3487 return;
3488
3489 if (radv_pipeline_has_gs(pipeline)) {
3490 const struct radv_shader_variant *gs =
3491 pipeline->shaders[MESA_SHADER_GEOMETRY];
3492
3493 vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out,
3494 pipeline->device->physical_device->rad_info.chip_class);
3495 } else if (outinfo->export_prim_id || vs->info.info.uses_prim_id) {
3496 vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
3497 vgt_primitiveid_en |= S_028A84_PRIMITIVEID_EN(1);
3498 }
3499
3500 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN, vgt_primitiveid_en);
3501 radeon_set_context_reg(ctx_cs, R_028A40_VGT_GS_MODE, vgt_gs_mode);
3502 }
3503
3504 static void
3505 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs,
3506 struct radeon_cmdbuf *cs,
3507 struct radv_pipeline *pipeline,
3508 struct radv_shader_variant *shader)
3509 {
3510 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3511
3512 radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
3513 radeon_emit(cs, va >> 8);
3514 radeon_emit(cs, S_00B124_MEM_BASE(va >> 40));
3515 radeon_emit(cs, shader->config.rsrc1);
3516 radeon_emit(cs, shader->config.rsrc2);
3517
3518 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3519 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3520 clip_dist_mask = outinfo->clip_dist_mask;
3521 cull_dist_mask = outinfo->cull_dist_mask;
3522 total_mask = clip_dist_mask | cull_dist_mask;
3523 bool misc_vec_ena = outinfo->writes_pointsize ||
3524 outinfo->writes_layer ||
3525 outinfo->writes_viewport_index;
3526 unsigned spi_vs_out_config, nparams;
3527
3528 /* VS is required to export at least one param. */
3529 nparams = MAX2(outinfo->param_exports, 1);
3530 spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
3531
3532 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3533 spi_vs_out_config |= S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0);
3534 }
3535
3536 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG, spi_vs_out_config);
3537
3538 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
3539 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
3540 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
3541 V_02870C_SPI_SHADER_4COMP :
3542 V_02870C_SPI_SHADER_NONE) |
3543 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
3544 V_02870C_SPI_SHADER_4COMP :
3545 V_02870C_SPI_SHADER_NONE) |
3546 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
3547 V_02870C_SPI_SHADER_4COMP :
3548 V_02870C_SPI_SHADER_NONE));
3549
3550 radeon_set_context_reg(ctx_cs, R_028818_PA_CL_VTE_CNTL,
3551 S_028818_VTX_W0_FMT(1) |
3552 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3553 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3554 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3555
3556 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
3557 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
3558 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
3559 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
3560 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
3561 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
3562 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
3563 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
3564 cull_dist_mask << 8 |
3565 clip_dist_mask);
3566
3567 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
3568 radeon_set_context_reg(ctx_cs, R_028AB4_VGT_REUSE_OFF,
3569 outinfo->writes_viewport_index);
3570 }
3571
3572 static void
3573 radv_pipeline_generate_hw_es(struct radeon_cmdbuf *cs,
3574 struct radv_pipeline *pipeline,
3575 struct radv_shader_variant *shader)
3576 {
3577 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3578
3579 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
3580 radeon_emit(cs, va >> 8);
3581 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3582 radeon_emit(cs, shader->config.rsrc1);
3583 radeon_emit(cs, shader->config.rsrc2);
3584 }
3585
3586 static void
3587 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf *cs,
3588 struct radv_pipeline *pipeline,
3589 struct radv_shader_variant *shader,
3590 const struct radv_tessellation_state *tess)
3591 {
3592 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3593 uint32_t rsrc2 = shader->config.rsrc2;
3594
3595 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
3596 radeon_emit(cs, va >> 8);
3597 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
3598
3599 rsrc2 |= S_00B52C_LDS_SIZE(tess->lds_size);
3600 if (pipeline->device->physical_device->rad_info.chip_class == GFX7 &&
3601 pipeline->device->physical_device->rad_info.family != CHIP_HAWAII)
3602 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
3603
3604 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
3605 radeon_emit(cs, shader->config.rsrc1);
3606 radeon_emit(cs, rsrc2);
3607 }
3608
3609 static void
3610 radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs,
3611 struct radeon_cmdbuf *cs,
3612 struct radv_pipeline *pipeline,
3613 struct radv_shader_variant *shader,
3614 const struct radv_ngg_state *ngg_state)
3615 {
3616 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3617 gl_shader_stage es_type =
3618 radv_pipeline_has_tess(pipeline) ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
3619 struct radv_shader_variant *es =
3620 es_type == MESA_SHADER_TESS_EVAL ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX];
3621
3622 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
3623 radeon_emit(cs, va >> 8);
3624 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3625 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
3626 radeon_emit(cs, shader->config.rsrc1);
3627 radeon_emit(cs, shader->config.rsrc2);
3628
3629 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3630 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3631 clip_dist_mask = outinfo->clip_dist_mask;
3632 cull_dist_mask = outinfo->cull_dist_mask;
3633 total_mask = clip_dist_mask | cull_dist_mask;
3634 bool misc_vec_ena = outinfo->writes_pointsize ||
3635 outinfo->writes_layer ||
3636 outinfo->writes_viewport_index;
3637 bool es_enable_prim_id = outinfo->export_prim_id ||
3638 (es && es->info.info.uses_prim_id);
3639 bool break_wave_at_eoi = false;
3640 unsigned ge_cntl;
3641 unsigned nparams;
3642
3643 if (es_type == MESA_SHADER_TESS_EVAL) {
3644 struct radv_shader_variant *gs =
3645 pipeline->shaders[MESA_SHADER_GEOMETRY];
3646
3647 if (es_enable_prim_id || (gs && gs->info.info.uses_prim_id))
3648 break_wave_at_eoi = true;
3649 }
3650
3651 nparams = MAX2(outinfo->param_exports, 1);
3652 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG,
3653 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
3654 S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0));
3655
3656 radeon_set_context_reg(ctx_cs, R_028708_SPI_SHADER_IDX_FORMAT,
3657 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP));
3658 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
3659 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
3660 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
3661 V_02870C_SPI_SHADER_4COMP :
3662 V_02870C_SPI_SHADER_NONE) |
3663 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
3664 V_02870C_SPI_SHADER_4COMP :
3665 V_02870C_SPI_SHADER_NONE) |
3666 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
3667 V_02870C_SPI_SHADER_4COMP :
3668 V_02870C_SPI_SHADER_NONE));
3669
3670 radeon_set_context_reg(ctx_cs, R_028818_PA_CL_VTE_CNTL,
3671 S_028818_VTX_W0_FMT(1) |
3672 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3673 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3674 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3675 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
3676 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
3677 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
3678 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
3679 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
3680 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
3681 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
3682 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
3683 cull_dist_mask << 8 |
3684 clip_dist_mask);
3685
3686 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN,
3687 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
3688 S_028A84_NGG_DISABLE_PROVOK_REUSE(es_enable_prim_id));
3689
3690 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
3691 ngg_state->vgt_esgs_ring_itemsize);
3692
3693 /* NGG specific registers. */
3694 struct radv_shader_variant *gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
3695 uint32_t gs_num_invocations = gs ? gs->info.gs.invocations : 1;
3696
3697 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
3698 S_028A44_ES_VERTS_PER_SUBGRP(ngg_state->hw_max_esverts) |
3699 S_028A44_GS_PRIMS_PER_SUBGRP(ngg_state->max_gsprims) |
3700 S_028A44_GS_INST_PRIMS_IN_SUBGRP(ngg_state->max_gsprims * gs_num_invocations));
3701 radeon_set_context_reg(ctx_cs, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
3702 S_0287FC_MAX_VERTS_PER_SUBGROUP(ngg_state->max_out_verts));
3703 radeon_set_context_reg(ctx_cs, R_028B4C_GE_NGG_SUBGRP_CNTL,
3704 S_028B4C_PRIM_AMP_FACTOR(ngg_state->prim_amp_factor) |
3705 S_028B4C_THDS_PER_SUBGRP(0)); /* for fast launch */
3706 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
3707 S_028B90_CNT(gs_num_invocations) |
3708 S_028B90_ENABLE(gs_num_invocations > 1) |
3709 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(ngg_state->max_vert_out_per_gs_instance));
3710
3711 /* User edge flags are set by the pos exports. If user edge flags are
3712 * not used, we must use hw-generated edge flags and pass them via
3713 * the prim export to prevent drawing lines on internal edges of
3714 * decomposed primitives (such as quads) with polygon mode = lines.
3715 *
3716 * TODO: We should combine hw-generated edge flags with user edge
3717 * flags in the shader.
3718 */
3719 radeon_set_context_reg(ctx_cs, R_028838_PA_CL_NGG_CNTL,
3720 S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline) &&
3721 !radv_pipeline_has_gs(pipeline)));
3722
3723 ge_cntl = S_03096C_PRIM_GRP_SIZE(ngg_state->max_gsprims) |
3724 S_03096C_VERT_GRP_SIZE(ngg_state->hw_max_esverts) |
3725 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
3726
3727 /* Bug workaround for a possible hang with non-tessellation cases.
3728 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
3729 *
3730 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
3731 */
3732 if ((pipeline->device->physical_device->rad_info.family == CHIP_NAVI10 ||
3733 pipeline->device->physical_device->rad_info.family == CHIP_NAVI12 ||
3734 pipeline->device->physical_device->rad_info.family == CHIP_NAVI14) &&
3735 !radv_pipeline_has_tess(pipeline) &&
3736 ngg_state->hw_max_esverts != 256) {
3737 ge_cntl &= C_03096C_VERT_GRP_SIZE;
3738
3739 if (ngg_state->hw_max_esverts > 5) {
3740 ge_cntl |= S_03096C_VERT_GRP_SIZE(ngg_state->hw_max_esverts - 5);
3741 }
3742 }
3743
3744 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL, ge_cntl);
3745 }
3746
3747 static void
3748 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf *cs,
3749 struct radv_pipeline *pipeline,
3750 struct radv_shader_variant *shader,
3751 const struct radv_tessellation_state *tess)
3752 {
3753 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3754
3755 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
3756 unsigned hs_rsrc2 = shader->config.rsrc2;
3757
3758 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3759 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX10(tess->lds_size);
3760 } else {
3761 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX9(tess->lds_size);
3762 }
3763
3764 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3765 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
3766 radeon_emit(cs, va >> 8);
3767 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
3768 } else {
3769 radeon_set_sh_reg_seq(cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
3770 radeon_emit(cs, va >> 8);
3771 radeon_emit(cs, S_00B414_MEM_BASE(va >> 40));
3772 }
3773
3774 radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
3775 radeon_emit(cs, shader->config.rsrc1);
3776 radeon_emit(cs, hs_rsrc2);
3777 } else {
3778 radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
3779 radeon_emit(cs, va >> 8);
3780 radeon_emit(cs, S_00B424_MEM_BASE(va >> 40));
3781 radeon_emit(cs, shader->config.rsrc1);
3782 radeon_emit(cs, shader->config.rsrc2);
3783 }
3784 }
3785
3786 static void
3787 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf *ctx_cs,
3788 struct radeon_cmdbuf *cs,
3789 struct radv_pipeline *pipeline,
3790 const struct radv_tessellation_state *tess,
3791 const struct radv_ngg_state *ngg)
3792 {
3793 struct radv_shader_variant *vs;
3794
3795 /* Skip shaders merged into HS/GS */
3796 vs = pipeline->shaders[MESA_SHADER_VERTEX];
3797 if (!vs)
3798 return;
3799
3800 if (vs->info.vs.as_ls)
3801 radv_pipeline_generate_hw_ls(cs, pipeline, vs, tess);
3802 else if (vs->info.vs.as_es)
3803 radv_pipeline_generate_hw_es(cs, pipeline, vs);
3804 else if (vs->info.is_ngg)
3805 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, vs, ngg);
3806 else
3807 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, vs);
3808 }
3809
3810 static void
3811 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf *ctx_cs,
3812 struct radeon_cmdbuf *cs,
3813 struct radv_pipeline *pipeline,
3814 const struct radv_tessellation_state *tess,
3815 const struct radv_ngg_state *ngg)
3816 {
3817 if (!radv_pipeline_has_tess(pipeline))
3818 return;
3819
3820 struct radv_shader_variant *tes, *tcs;
3821
3822 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
3823 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
3824
3825 if (tes) {
3826 if (tes->info.is_ngg) {
3827 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, tes, ngg);
3828 } else if (tes->info.tes.as_es)
3829 radv_pipeline_generate_hw_es(cs, pipeline, tes);
3830 else
3831 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, tes);
3832 }
3833
3834 radv_pipeline_generate_hw_hs(cs, pipeline, tcs, tess);
3835
3836 radeon_set_context_reg(ctx_cs, R_028B6C_VGT_TF_PARAM,
3837 tess->tf_param);
3838
3839 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7)
3840 radeon_set_context_reg_idx(ctx_cs, R_028B58_VGT_LS_HS_CONFIG, 2,
3841 tess->ls_hs_config);
3842 else
3843 radeon_set_context_reg(ctx_cs, R_028B58_VGT_LS_HS_CONFIG,
3844 tess->ls_hs_config);
3845
3846 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 &&
3847 !radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) {
3848 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
3849 S_028A44_ES_VERTS_PER_SUBGRP(250) |
3850 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
3851 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
3852 }
3853 }
3854
3855 static void
3856 radv_pipeline_generate_hw_gs(struct radeon_cmdbuf *ctx_cs,
3857 struct radeon_cmdbuf *cs,
3858 struct radv_pipeline *pipeline,
3859 struct radv_shader_variant *gs,
3860 const struct radv_gs_state *gs_state)
3861 {
3862 unsigned gs_max_out_vertices;
3863 uint8_t *num_components;
3864 uint8_t max_stream;
3865 unsigned offset;
3866 uint64_t va;
3867
3868 gs_max_out_vertices = gs->info.gs.vertices_out;
3869 max_stream = gs->info.info.gs.max_stream;
3870 num_components = gs->info.info.gs.num_stream_output_components;
3871
3872 offset = num_components[0] * gs_max_out_vertices;
3873
3874 radeon_set_context_reg_seq(ctx_cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
3875 radeon_emit(ctx_cs, offset);
3876 if (max_stream >= 1)
3877 offset += num_components[1] * gs_max_out_vertices;
3878 radeon_emit(ctx_cs, offset);
3879 if (max_stream >= 2)
3880 offset += num_components[2] * gs_max_out_vertices;
3881 radeon_emit(ctx_cs, offset);
3882 if (max_stream >= 3)
3883 offset += num_components[3] * gs_max_out_vertices;
3884 radeon_set_context_reg(ctx_cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
3885
3886 radeon_set_context_reg_seq(ctx_cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
3887 radeon_emit(ctx_cs, num_components[0]);
3888 radeon_emit(ctx_cs, (max_stream >= 1) ? num_components[1] : 0);
3889 radeon_emit(ctx_cs, (max_stream >= 2) ? num_components[2] : 0);
3890 radeon_emit(ctx_cs, (max_stream >= 3) ? num_components[3] : 0);
3891
3892 uint32_t gs_num_invocations = gs->info.gs.invocations;
3893 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
3894 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
3895 S_028B90_ENABLE(gs_num_invocations > 0));
3896
3897 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
3898 gs_state->vgt_esgs_ring_itemsize);
3899
3900 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
3901
3902 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
3903 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3904 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
3905 radeon_emit(cs, va >> 8);
3906 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3907 } else {
3908 radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
3909 radeon_emit(cs, va >> 8);
3910 radeon_emit(cs, S_00B214_MEM_BASE(va >> 40));
3911 }
3912
3913 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
3914 radeon_emit(cs, gs->config.rsrc1);
3915 radeon_emit(cs, gs->config.rsrc2 | S_00B22C_LDS_SIZE(gs_state->lds_size));
3916
3917 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL, gs_state->vgt_gs_onchip_cntl);
3918 radeon_set_context_reg(ctx_cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, gs_state->vgt_gs_max_prims_per_subgroup);
3919 } else {
3920 radeon_set_sh_reg_seq(cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
3921 radeon_emit(cs, va >> 8);
3922 radeon_emit(cs, S_00B224_MEM_BASE(va >> 40));
3923 radeon_emit(cs, gs->config.rsrc1);
3924 radeon_emit(cs, gs->config.rsrc2);
3925 }
3926
3927 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, pipeline->gs_copy_shader);
3928 }
3929
3930 static void
3931 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf *ctx_cs,
3932 struct radeon_cmdbuf *cs,
3933 struct radv_pipeline *pipeline,
3934 const struct radv_gs_state *gs_state,
3935 const struct radv_ngg_state *ngg_state)
3936 {
3937 struct radv_shader_variant *gs;
3938
3939 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
3940 if (!gs)
3941 return;
3942
3943 if (gs->info.is_ngg)
3944 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, gs, ngg_state);
3945 else
3946 radv_pipeline_generate_hw_gs(ctx_cs, cs, pipeline, gs, gs_state);
3947
3948 radeon_set_context_reg(ctx_cs, R_028B38_VGT_GS_MAX_VERT_OUT,
3949 gs->info.gs.vertices_out);
3950 }
3951
3952 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade, bool float16)
3953 {
3954 uint32_t ps_input_cntl;
3955 if (offset <= AC_EXP_PARAM_OFFSET_31) {
3956 ps_input_cntl = S_028644_OFFSET(offset);
3957 if (flat_shade)
3958 ps_input_cntl |= S_028644_FLAT_SHADE(1);
3959 if (float16) {
3960 ps_input_cntl |= S_028644_FP16_INTERP_MODE(1) |
3961 S_028644_ATTR0_VALID(1);
3962 }
3963 } else {
3964 /* The input is a DEFAULT_VAL constant. */
3965 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
3966 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
3967 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
3968 ps_input_cntl = S_028644_OFFSET(0x20) |
3969 S_028644_DEFAULT_VAL(offset);
3970 }
3971 return ps_input_cntl;
3972 }
3973
3974 static void
3975 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf *ctx_cs,
3976 struct radv_pipeline *pipeline)
3977 {
3978 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3979 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3980 uint32_t ps_input_cntl[32];
3981
3982 unsigned ps_offset = 0;
3983
3984 if (ps->info.info.ps.prim_id_input) {
3985 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
3986 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
3987 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false);
3988 ++ps_offset;
3989 }
3990 }
3991
3992 if (ps->info.info.ps.layer_input ||
3993 ps->info.info.needs_multiview_view_index) {
3994 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
3995 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
3996 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false);
3997 else
3998 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true, false);
3999 ++ps_offset;
4000 }
4001
4002 if (ps->info.info.ps.has_pcoord) {
4003 unsigned val;
4004 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
4005 ps_input_cntl[ps_offset] = val;
4006 ps_offset++;
4007 }
4008
4009 if (ps->info.info.ps.num_input_clips_culls) {
4010 unsigned vs_offset;
4011
4012 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST0];
4013 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
4014 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false);
4015 ++ps_offset;
4016 }
4017
4018 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST1];
4019 if (vs_offset != AC_EXP_PARAM_UNDEFINED &&
4020 ps->info.info.ps.num_input_clips_culls > 4) {
4021 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false);
4022 ++ps_offset;
4023 }
4024 }
4025
4026 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
4027 unsigned vs_offset;
4028 bool flat_shade;
4029 bool float16;
4030 if (!(ps->info.fs.input_mask & (1u << i)))
4031 continue;
4032
4033 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
4034 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
4035 ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
4036 ++ps_offset;
4037 continue;
4038 }
4039
4040 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
4041 float16 = !!(ps->info.fs.float16_shaded_mask & (1u << ps_offset));
4042
4043 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade, float16);
4044 ++ps_offset;
4045 }
4046
4047 if (ps_offset) {
4048 radeon_set_context_reg_seq(ctx_cs, R_028644_SPI_PS_INPUT_CNTL_0, ps_offset);
4049 for (unsigned i = 0; i < ps_offset; i++) {
4050 radeon_emit(ctx_cs, ps_input_cntl[i]);
4051 }
4052 }
4053 }
4054
4055 static uint32_t
4056 radv_compute_db_shader_control(const struct radv_device *device,
4057 const struct radv_pipeline *pipeline,
4058 const struct radv_shader_variant *ps)
4059 {
4060 unsigned z_order;
4061 if (ps->info.fs.early_fragment_test || !ps->info.info.ps.writes_memory)
4062 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
4063 else
4064 z_order = V_02880C_LATE_Z;
4065
4066 bool disable_rbplus = device->physical_device->rad_info.has_rbplus &&
4067 !device->physical_device->rad_info.rbplus_allowed;
4068
4069 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
4070 * but this appears to break Project Cars (DXVK). See
4071 * https://bugs.freedesktop.org/show_bug.cgi?id=109401
4072 */
4073 bool mask_export_enable = ps->info.info.ps.writes_sample_mask;
4074
4075 return S_02880C_Z_EXPORT_ENABLE(ps->info.info.ps.writes_z) |
4076 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.info.ps.writes_stencil) |
4077 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
4078 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable) |
4079 S_02880C_Z_ORDER(z_order) |
4080 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
4081 S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps->info.fs.post_depth_coverage) |
4082 S_02880C_EXEC_ON_HIER_FAIL(ps->info.info.ps.writes_memory) |
4083 S_02880C_EXEC_ON_NOOP(ps->info.info.ps.writes_memory) |
4084 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus);
4085 }
4086
4087 static void
4088 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf *ctx_cs,
4089 struct radeon_cmdbuf *cs,
4090 struct radv_pipeline *pipeline)
4091 {
4092 struct radv_shader_variant *ps;
4093 uint64_t va;
4094 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
4095
4096 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4097 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
4098
4099 radeon_set_sh_reg_seq(cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
4100 radeon_emit(cs, va >> 8);
4101 radeon_emit(cs, S_00B024_MEM_BASE(va >> 40));
4102 radeon_emit(cs, ps->config.rsrc1);
4103 radeon_emit(cs, ps->config.rsrc2);
4104
4105 radeon_set_context_reg(ctx_cs, R_02880C_DB_SHADER_CONTROL,
4106 radv_compute_db_shader_control(pipeline->device,
4107 pipeline, ps));
4108
4109 radeon_set_context_reg(ctx_cs, R_0286CC_SPI_PS_INPUT_ENA,
4110 ps->config.spi_ps_input_ena);
4111
4112 radeon_set_context_reg(ctx_cs, R_0286D0_SPI_PS_INPUT_ADDR,
4113 ps->config.spi_ps_input_addr);
4114
4115 radeon_set_context_reg(ctx_cs, R_0286D8_SPI_PS_IN_CONTROL,
4116 S_0286D8_NUM_INTERP(ps->info.fs.num_interp) |
4117 S_0286D8_PS_W32_EN(ps->info.info.wave_size == 32));
4118
4119 radeon_set_context_reg(ctx_cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl);
4120
4121 radeon_set_context_reg(ctx_cs, R_028710_SPI_SHADER_Z_FORMAT,
4122 ac_get_spi_shader_z_format(ps->info.info.ps.writes_z,
4123 ps->info.info.ps.writes_stencil,
4124 ps->info.info.ps.writes_sample_mask));
4125
4126 if (pipeline->device->dfsm_allowed) {
4127 /* optimise this? */
4128 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
4129 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
4130 }
4131 }
4132
4133 static void
4134 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf *ctx_cs,
4135 struct radv_pipeline *pipeline)
4136 {
4137 if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10 ||
4138 pipeline->device->physical_device->rad_info.chip_class >= GFX10)
4139 return;
4140
4141 unsigned vtx_reuse_depth = 30;
4142 if (radv_pipeline_has_tess(pipeline) &&
4143 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
4144 vtx_reuse_depth = 14;
4145 }
4146 radeon_set_context_reg(ctx_cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
4147 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth));
4148 }
4149
4150 static uint32_t
4151 radv_compute_vgt_shader_stages_en(const struct radv_pipeline *pipeline)
4152 {
4153 uint32_t stages = 0;
4154 if (radv_pipeline_has_tess(pipeline)) {
4155 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
4156 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
4157
4158 if (radv_pipeline_has_gs(pipeline))
4159 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
4160 S_028B54_GS_EN(1);
4161 else if (radv_pipeline_has_ngg(pipeline))
4162 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
4163 else
4164 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
4165 } else if (radv_pipeline_has_gs(pipeline)) {
4166 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
4167 S_028B54_GS_EN(1);
4168 } else if (radv_pipeline_has_ngg(pipeline)) {
4169 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
4170 }
4171
4172 if (radv_pipeline_has_ngg(pipeline)) {
4173 stages |= S_028B54_PRIMGEN_EN(1);
4174 } else if (radv_pipeline_has_gs(pipeline)) {
4175 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
4176 }
4177
4178 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
4179 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
4180
4181 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4182 uint8_t hs_size = 64, gs_size = 64, vs_size = 64;
4183
4184 if (radv_pipeline_has_tess(pipeline))
4185 hs_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.wave_size;
4186
4187 if (pipeline->shaders[MESA_SHADER_GEOMETRY]) {
4188 vs_size = gs_size = pipeline->shaders[MESA_SHADER_GEOMETRY]->info.info.wave_size;
4189 if (pipeline->gs_copy_shader)
4190 vs_size = pipeline->gs_copy_shader->info.info.wave_size;
4191 } else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
4192 vs_size = pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.info.wave_size;
4193 else if (pipeline->shaders[MESA_SHADER_VERTEX])
4194 vs_size = pipeline->shaders[MESA_SHADER_VERTEX]->info.info.wave_size;
4195
4196 if (radv_pipeline_has_ngg(pipeline))
4197 gs_size = vs_size;
4198
4199 /* legacy GS only supports Wave64 */
4200 stages |= S_028B54_HS_W32_EN(hs_size == 32 ? 1 : 0) |
4201 S_028B54_GS_W32_EN(gs_size == 32 ? 1 : 0) |
4202 S_028B54_VS_W32_EN(vs_size == 32 ? 1 : 0);
4203 }
4204
4205 return stages;
4206 }
4207
4208 static uint32_t
4209 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo *pCreateInfo)
4210 {
4211 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
4212 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
4213
4214 if (!discard_rectangle_info)
4215 return 0xffff;
4216
4217 unsigned mask = 0;
4218
4219 for (unsigned i = 0; i < (1u << MAX_DISCARD_RECTANGLES); ++i) {
4220 /* Interpret i as a bitmask, and then set the bit in the mask if
4221 * that combination of rectangles in which the pixel is contained
4222 * should pass the cliprect test. */
4223 unsigned relevant_subset = i & ((1u << discard_rectangle_info->discardRectangleCount) - 1);
4224
4225 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT &&
4226 !relevant_subset)
4227 continue;
4228
4229 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT &&
4230 relevant_subset)
4231 continue;
4232
4233 mask |= 1u << i;
4234 }
4235
4236 return mask;
4237 }
4238
4239 static void
4240 gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf *ctx_cs,
4241 struct radv_pipeline *pipeline,
4242 const struct radv_tessellation_state *tess,
4243 const struct radv_gs_state *gs_state)
4244 {
4245 bool break_wave_at_eoi = false;
4246 unsigned primgroup_size;
4247 unsigned vertgroup_size;
4248
4249 if (radv_pipeline_has_tess(pipeline)) {
4250 primgroup_size = tess->num_patches; /* must be a multiple of NUM_PATCHES */
4251 vertgroup_size = 0;
4252 } else if (radv_pipeline_has_gs(pipeline)) {
4253 unsigned vgt_gs_onchip_cntl = gs_state->vgt_gs_onchip_cntl;
4254 primgroup_size = G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl);
4255 vertgroup_size = G_028A44_ES_VERTS_PER_SUBGRP(vgt_gs_onchip_cntl);
4256 } else {
4257 primgroup_size = 128; /* recommended without a GS and tess */
4258 vertgroup_size = 0;
4259 }
4260
4261 if (radv_pipeline_has_tess(pipeline)) {
4262 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.uses_prim_id ||
4263 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.info.uses_prim_id)
4264 break_wave_at_eoi = true;
4265 }
4266
4267 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL,
4268 S_03096C_PRIM_GRP_SIZE(primgroup_size) |
4269 S_03096C_VERT_GRP_SIZE(vertgroup_size) |
4270 S_03096C_PACKET_TO_ONE_PA(0) /* line stipple */ |
4271 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi));
4272 }
4273
4274 static void
4275 radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
4276 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4277 const struct radv_graphics_pipeline_create_info *extra,
4278 const struct radv_blend_state *blend,
4279 const struct radv_tessellation_state *tess,
4280 const struct radv_gs_state *gs,
4281 const struct radv_ngg_state *ngg,
4282 unsigned prim, unsigned gs_out)
4283 {
4284 struct radeon_cmdbuf *ctx_cs = &pipeline->ctx_cs;
4285 struct radeon_cmdbuf *cs = &pipeline->cs;
4286
4287 cs->max_dw = 64;
4288 ctx_cs->max_dw = 256;
4289 cs->buf = malloc(4 * (cs->max_dw + ctx_cs->max_dw));
4290 ctx_cs->buf = cs->buf + cs->max_dw;
4291
4292 radv_pipeline_generate_depth_stencil_state(ctx_cs, pipeline, pCreateInfo, extra);
4293 radv_pipeline_generate_blend_state(ctx_cs, pipeline, blend);
4294 radv_pipeline_generate_raster_state(ctx_cs, pipeline, pCreateInfo);
4295 radv_pipeline_generate_multisample_state(ctx_cs, pipeline);
4296 radv_pipeline_generate_vgt_gs_mode(ctx_cs, pipeline);
4297 radv_pipeline_generate_vertex_shader(ctx_cs, cs, pipeline, tess, ngg);
4298 radv_pipeline_generate_tess_shaders(ctx_cs, cs, pipeline, tess, ngg);
4299 radv_pipeline_generate_geometry_shader(ctx_cs, cs, pipeline, gs, ngg);
4300 radv_pipeline_generate_fragment_shader(ctx_cs, cs, pipeline);
4301 radv_pipeline_generate_ps_inputs(ctx_cs, pipeline);
4302 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs, pipeline);
4303 radv_pipeline_generate_binning_state(ctx_cs, pipeline, pCreateInfo);
4304
4305 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 && !radv_pipeline_has_ngg(pipeline))
4306 gfx10_pipeline_generate_ge_cntl(ctx_cs, pipeline, tess, gs);
4307
4308 radeon_set_context_reg(ctx_cs, R_0286E8_SPI_TMPRING_SIZE,
4309 S_0286E8_WAVES(pipeline->max_waves) |
4310 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
4311
4312 radeon_set_context_reg(ctx_cs, R_028B54_VGT_SHADER_STAGES_EN, radv_compute_vgt_shader_stages_en(pipeline));
4313
4314 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
4315 radeon_set_uconfig_reg_idx(pipeline->device->physical_device,
4316 cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
4317 } else {
4318 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
4319 }
4320 radeon_set_context_reg(ctx_cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out);
4321
4322 radeon_set_context_reg(ctx_cs, R_02820C_PA_SC_CLIPRECT_RULE, radv_compute_cliprect_rule(pCreateInfo));
4323
4324 pipeline->ctx_cs_hash = _mesa_hash_data(ctx_cs->buf, ctx_cs->cdw * 4);
4325
4326 assert(ctx_cs->cdw <= ctx_cs->max_dw);
4327 assert(cs->cdw <= cs->max_dw);
4328 }
4329
4330 static struct radv_ia_multi_vgt_param_helpers
4331 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
4332 const struct radv_tessellation_state *tess,
4333 uint32_t prim)
4334 {
4335 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param = {0};
4336 const struct radv_device *device = pipeline->device;
4337
4338 if (radv_pipeline_has_tess(pipeline))
4339 ia_multi_vgt_param.primgroup_size = tess->num_patches;
4340 else if (radv_pipeline_has_gs(pipeline))
4341 ia_multi_vgt_param.primgroup_size = 64;
4342 else
4343 ia_multi_vgt_param.primgroup_size = 128; /* recommended without a GS */
4344
4345 /* GS requirement. */
4346 ia_multi_vgt_param.partial_es_wave = false;
4347 if (radv_pipeline_has_gs(pipeline) && device->physical_device->rad_info.chip_class <= GFX8)
4348 if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3)
4349 ia_multi_vgt_param.partial_es_wave = true;
4350
4351 ia_multi_vgt_param.wd_switch_on_eop = false;
4352 if (device->physical_device->rad_info.chip_class >= GFX7) {
4353 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
4354 * 4 shader engines. Set 1 to pass the assertion below.
4355 * The other cases are hardware requirements. */
4356 if (device->physical_device->rad_info.max_se < 4 ||
4357 prim == V_008958_DI_PT_POLYGON ||
4358 prim == V_008958_DI_PT_LINELOOP ||
4359 prim == V_008958_DI_PT_TRIFAN ||
4360 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
4361 (pipeline->graphics.prim_restart_enable &&
4362 (device->physical_device->rad_info.family < CHIP_POLARIS10 ||
4363 (prim != V_008958_DI_PT_POINTLIST &&
4364 prim != V_008958_DI_PT_LINESTRIP))))
4365 ia_multi_vgt_param.wd_switch_on_eop = true;
4366 }
4367
4368 ia_multi_vgt_param.ia_switch_on_eoi = false;
4369 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input)
4370 ia_multi_vgt_param.ia_switch_on_eoi = true;
4371 if (radv_pipeline_has_gs(pipeline) &&
4372 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.info.uses_prim_id)
4373 ia_multi_vgt_param.ia_switch_on_eoi = true;
4374 if (radv_pipeline_has_tess(pipeline)) {
4375 /* SWITCH_ON_EOI must be set if PrimID is used. */
4376 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.uses_prim_id ||
4377 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.info.uses_prim_id)
4378 ia_multi_vgt_param.ia_switch_on_eoi = true;
4379 }
4380
4381 ia_multi_vgt_param.partial_vs_wave = false;
4382 if (radv_pipeline_has_tess(pipeline)) {
4383 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
4384 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
4385 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
4386 device->physical_device->rad_info.family == CHIP_BONAIRE) &&
4387 radv_pipeline_has_gs(pipeline))
4388 ia_multi_vgt_param.partial_vs_wave = true;
4389 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
4390 if (device->physical_device->rad_info.has_distributed_tess) {
4391 if (radv_pipeline_has_gs(pipeline)) {
4392 if (device->physical_device->rad_info.chip_class <= GFX8)
4393 ia_multi_vgt_param.partial_es_wave = true;
4394 } else {
4395 ia_multi_vgt_param.partial_vs_wave = true;
4396 }
4397 }
4398 }
4399
4400 /* Workaround for a VGT hang when strip primitive types are used with
4401 * primitive restart.
4402 */
4403 if (pipeline->graphics.prim_restart_enable &&
4404 (prim == V_008958_DI_PT_LINESTRIP ||
4405 prim == V_008958_DI_PT_TRISTRIP ||
4406 prim == V_008958_DI_PT_LINESTRIP_ADJ ||
4407 prim == V_008958_DI_PT_TRISTRIP_ADJ)) {
4408 ia_multi_vgt_param.partial_vs_wave = true;
4409 }
4410
4411 if (radv_pipeline_has_gs(pipeline)) {
4412 /* On these chips there is the possibility of a hang if the
4413 * pipeline uses a GS and partial_vs_wave is not set.
4414 *
4415 * This mostly does not hit 4-SE chips, as those typically set
4416 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
4417 * with GS due to another workaround.
4418 *
4419 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
4420 */
4421 if (device->physical_device->rad_info.family == CHIP_TONGA ||
4422 device->physical_device->rad_info.family == CHIP_FIJI ||
4423 device->physical_device->rad_info.family == CHIP_POLARIS10 ||
4424 device->physical_device->rad_info.family == CHIP_POLARIS11 ||
4425 device->physical_device->rad_info.family == CHIP_POLARIS12 ||
4426 device->physical_device->rad_info.family == CHIP_VEGAM) {
4427 ia_multi_vgt_param.partial_vs_wave = true;
4428 }
4429 }
4430
4431 ia_multi_vgt_param.base =
4432 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param.primgroup_size - 1) |
4433 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
4434 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == GFX8 ? 2 : 0) |
4435 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
4436 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
4437
4438 return ia_multi_vgt_param;
4439 }
4440
4441
4442 static void
4443 radv_compute_vertex_input_state(struct radv_pipeline *pipeline,
4444 const VkGraphicsPipelineCreateInfo *pCreateInfo)
4445 {
4446 const VkPipelineVertexInputStateCreateInfo *vi_info =
4447 pCreateInfo->pVertexInputState;
4448 struct radv_vertex_elements_info *velems = &pipeline->vertex_elements;
4449
4450 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
4451 const VkVertexInputAttributeDescription *desc =
4452 &vi_info->pVertexAttributeDescriptions[i];
4453 unsigned loc = desc->location;
4454 const struct vk_format_description *format_desc;
4455
4456 format_desc = vk_format_description(desc->format);
4457
4458 velems->format_size[loc] = format_desc->block.bits / 8;
4459 }
4460
4461 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
4462 const VkVertexInputBindingDescription *desc =
4463 &vi_info->pVertexBindingDescriptions[i];
4464
4465 pipeline->binding_stride[desc->binding] = desc->stride;
4466 pipeline->num_vertex_bindings =
4467 MAX2(pipeline->num_vertex_bindings, desc->binding + 1);
4468 }
4469 }
4470
4471 static struct radv_shader_variant *
4472 radv_pipeline_get_streamout_shader(struct radv_pipeline *pipeline)
4473 {
4474 int i;
4475
4476 for (i = MESA_SHADER_GEOMETRY; i >= MESA_SHADER_VERTEX; i--) {
4477 struct radv_shader_variant *shader =
4478 radv_get_shader(pipeline, i);
4479
4480 if (shader && shader->info.info.so.num_outputs > 0)
4481 return shader;
4482 }
4483
4484 return NULL;
4485 }
4486
4487 static VkResult
4488 radv_pipeline_init(struct radv_pipeline *pipeline,
4489 struct radv_device *device,
4490 struct radv_pipeline_cache *cache,
4491 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4492 const struct radv_graphics_pipeline_create_info *extra)
4493 {
4494 VkResult result;
4495 bool has_view_index = false;
4496
4497 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
4498 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
4499 if (subpass->view_mask)
4500 has_view_index = true;
4501
4502 pipeline->device = device;
4503 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
4504 assert(pipeline->layout);
4505
4506 struct radv_blend_state blend = radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
4507
4508 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
4509 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
4510 radv_init_feedback(creation_feedback);
4511
4512 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
4513
4514 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
4515 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
4516 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
4517 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
4518 pStages[stage] = &pCreateInfo->pStages[i];
4519 if(creation_feedback)
4520 stage_feedbacks[stage] = &creation_feedback->pPipelineStageCreationFeedbacks[i];
4521 }
4522
4523 struct radv_pipeline_key key = radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &blend, has_view_index);
4524 radv_create_shaders(pipeline, device, cache, &key, pStages, pCreateInfo->flags, pipeline_feedback, stage_feedbacks);
4525
4526 pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
4527 radv_pipeline_init_multisample_state(pipeline, &blend, pCreateInfo);
4528 uint32_t gs_out;
4529 uint32_t prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
4530
4531 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
4532
4533 if (radv_pipeline_has_gs(pipeline)) {
4534 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
4535 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
4536 } else if (radv_pipeline_has_tess(pipeline)) {
4537 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.point_mode)
4538 gs_out = V_028A6C_OUTPRIM_TYPE_POINTLIST;
4539 else
4540 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.primitive_mode);
4541 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
4542 } else {
4543 gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
4544 }
4545 if (extra && extra->use_rectlist) {
4546 prim = V_008958_DI_PT_RECTLIST;
4547 gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
4548 pipeline->graphics.can_use_guardband = true;
4549 if (radv_pipeline_has_ngg(pipeline))
4550 gs_out = V_028A6C_VGT_OUT_RECT_V0;
4551 }
4552 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
4553 /* prim vertex count will need TESS changes */
4554 pipeline->graphics.prim_vertex_count = prim_size_table[prim];
4555
4556 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
4557
4558 /* Ensure that some export memory is always allocated, for two reasons:
4559 *
4560 * 1) Correctness: The hardware ignores the EXEC mask if no export
4561 * memory is allocated, so KILL and alpha test do not work correctly
4562 * without this.
4563 * 2) Performance: Every shader needs at least a NULL export, even when
4564 * it writes no color/depth output. The NULL export instruction
4565 * stalls without this setting.
4566 *
4567 * Don't add this to CB_SHADER_MASK.
4568 *
4569 * GFX10 supports pixel shaders without exports by setting both the
4570 * color and Z formats to SPI_SHADER_ZERO. The hw will skip export
4571 * instructions if any are present.
4572 */
4573 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4574 if ((pipeline->device->physical_device->rad_info.chip_class <= GFX9 ||
4575 ps->info.fs.can_discard) &&
4576 !blend.spi_shader_col_format) {
4577 if (!ps->info.info.ps.writes_z &&
4578 !ps->info.info.ps.writes_stencil &&
4579 !ps->info.info.ps.writes_sample_mask)
4580 blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
4581 }
4582
4583 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
4584 if (pipeline->shaders[i]) {
4585 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
4586 }
4587 }
4588
4589 struct radv_ngg_state ngg = {0};
4590 struct radv_gs_state gs = {0};
4591
4592 if (radv_pipeline_has_ngg(pipeline)) {
4593 ngg = calculate_ngg_info(pCreateInfo, pipeline);
4594 } else if (radv_pipeline_has_gs(pipeline)) {
4595 gs = calculate_gs_info(pCreateInfo, pipeline);
4596 calculate_gs_ring_sizes(pipeline, &gs);
4597 }
4598
4599 struct radv_tessellation_state tess = {0};
4600 if (radv_pipeline_has_tess(pipeline)) {
4601 if (prim == V_008958_DI_PT_PATCH) {
4602 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
4603 pipeline->graphics.prim_vertex_count.incr = 1;
4604 }
4605 tess = calculate_tess_state(pipeline, pCreateInfo);
4606 }
4607
4608 pipeline->graphics.ia_multi_vgt_param = radv_compute_ia_multi_vgt_param_helpers(pipeline, &tess, prim);
4609
4610 radv_compute_vertex_input_state(pipeline, pCreateInfo);
4611
4612 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
4613 pipeline->user_data_0[i] = radv_pipeline_stage_to_user_data_0(pipeline, i, device->physical_device->rad_info.chip_class);
4614
4615 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
4616 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
4617 if (loc->sgpr_idx != -1) {
4618 pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX];
4619 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
4620 if (radv_get_shader(pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id)
4621 pipeline->graphics.vtx_emit_num = 3;
4622 else
4623 pipeline->graphics.vtx_emit_num = 2;
4624 }
4625
4626 /* Find the last vertex shader stage that eventually uses streamout. */
4627 pipeline->streamout_shader = radv_pipeline_get_streamout_shader(pipeline);
4628
4629 result = radv_pipeline_scratch_init(device, pipeline);
4630 radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend, &tess, &gs, &ngg, prim, gs_out);
4631
4632 return result;
4633 }
4634
4635 VkResult
4636 radv_graphics_pipeline_create(
4637 VkDevice _device,
4638 VkPipelineCache _cache,
4639 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4640 const struct radv_graphics_pipeline_create_info *extra,
4641 const VkAllocationCallbacks *pAllocator,
4642 VkPipeline *pPipeline)
4643 {
4644 RADV_FROM_HANDLE(radv_device, device, _device);
4645 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
4646 struct radv_pipeline *pipeline;
4647 VkResult result;
4648
4649 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
4650 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4651 if (pipeline == NULL)
4652 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4653
4654 result = radv_pipeline_init(pipeline, device, cache,
4655 pCreateInfo, extra);
4656 if (result != VK_SUCCESS) {
4657 radv_pipeline_destroy(device, pipeline, pAllocator);
4658 return result;
4659 }
4660
4661 *pPipeline = radv_pipeline_to_handle(pipeline);
4662
4663 return VK_SUCCESS;
4664 }
4665
4666 VkResult radv_CreateGraphicsPipelines(
4667 VkDevice _device,
4668 VkPipelineCache pipelineCache,
4669 uint32_t count,
4670 const VkGraphicsPipelineCreateInfo* pCreateInfos,
4671 const VkAllocationCallbacks* pAllocator,
4672 VkPipeline* pPipelines)
4673 {
4674 VkResult result = VK_SUCCESS;
4675 unsigned i = 0;
4676
4677 for (; i < count; i++) {
4678 VkResult r;
4679 r = radv_graphics_pipeline_create(_device,
4680 pipelineCache,
4681 &pCreateInfos[i],
4682 NULL, pAllocator, &pPipelines[i]);
4683 if (r != VK_SUCCESS) {
4684 result = r;
4685 pPipelines[i] = VK_NULL_HANDLE;
4686 }
4687 }
4688
4689 return result;
4690 }
4691
4692
4693 static void
4694 radv_compute_generate_pm4(struct radv_pipeline *pipeline)
4695 {
4696 struct radv_shader_variant *compute_shader;
4697 struct radv_device *device = pipeline->device;
4698 unsigned threads_per_threadgroup;
4699 unsigned threadgroups_per_cu = 1;
4700 unsigned waves_per_threadgroup;
4701 unsigned max_waves_per_sh = 0;
4702 uint64_t va;
4703
4704 pipeline->cs.buf = malloc(20 * 4);
4705 pipeline->cs.max_dw = 20;
4706
4707 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
4708 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
4709
4710 radeon_set_sh_reg_seq(&pipeline->cs, R_00B830_COMPUTE_PGM_LO, 2);
4711 radeon_emit(&pipeline->cs, va >> 8);
4712 radeon_emit(&pipeline->cs, S_00B834_DATA(va >> 40));
4713
4714 radeon_set_sh_reg_seq(&pipeline->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
4715 radeon_emit(&pipeline->cs, compute_shader->config.rsrc1);
4716 radeon_emit(&pipeline->cs, compute_shader->config.rsrc2);
4717
4718 radeon_set_sh_reg(&pipeline->cs, R_00B860_COMPUTE_TMPRING_SIZE,
4719 S_00B860_WAVES(pipeline->max_waves) |
4720 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
4721
4722 /* Calculate best compute resource limits. */
4723 threads_per_threadgroup = compute_shader->info.cs.block_size[0] *
4724 compute_shader->info.cs.block_size[1] *
4725 compute_shader->info.cs.block_size[2];
4726 waves_per_threadgroup = DIV_ROUND_UP(threads_per_threadgroup,
4727 device->physical_device->cs_wave_size);
4728
4729 if (device->physical_device->rad_info.chip_class >= GFX10 &&
4730 waves_per_threadgroup == 1)
4731 threadgroups_per_cu = 2;
4732
4733 radeon_set_sh_reg(&pipeline->cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
4734 ac_get_compute_resource_limits(&device->physical_device->rad_info,
4735 waves_per_threadgroup,
4736 max_waves_per_sh,
4737 threadgroups_per_cu));
4738
4739 radeon_set_sh_reg_seq(&pipeline->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
4740 radeon_emit(&pipeline->cs,
4741 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
4742 radeon_emit(&pipeline->cs,
4743 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
4744 radeon_emit(&pipeline->cs,
4745 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
4746
4747 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
4748 }
4749
4750 static VkResult radv_compute_pipeline_create(
4751 VkDevice _device,
4752 VkPipelineCache _cache,
4753 const VkComputePipelineCreateInfo* pCreateInfo,
4754 const VkAllocationCallbacks* pAllocator,
4755 VkPipeline* pPipeline)
4756 {
4757 RADV_FROM_HANDLE(radv_device, device, _device);
4758 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
4759 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
4760 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
4761 struct radv_pipeline *pipeline;
4762 VkResult result;
4763
4764 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
4765 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4766 if (pipeline == NULL)
4767 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4768
4769 pipeline->device = device;
4770 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
4771 assert(pipeline->layout);
4772
4773 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
4774 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
4775 radv_init_feedback(creation_feedback);
4776
4777 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
4778 if (creation_feedback)
4779 stage_feedbacks[MESA_SHADER_COMPUTE] = &creation_feedback->pPipelineStageCreationFeedbacks[0];
4780
4781 pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
4782 radv_create_shaders(pipeline, device, cache, &(struct radv_pipeline_key) {0}, pStages, pCreateInfo->flags, pipeline_feedback, stage_feedbacks);
4783
4784 pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
4785 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
4786 result = radv_pipeline_scratch_init(device, pipeline);
4787 if (result != VK_SUCCESS) {
4788 radv_pipeline_destroy(device, pipeline, pAllocator);
4789 return result;
4790 }
4791
4792 radv_compute_generate_pm4(pipeline);
4793
4794 *pPipeline = radv_pipeline_to_handle(pipeline);
4795
4796 return VK_SUCCESS;
4797 }
4798
4799 VkResult radv_CreateComputePipelines(
4800 VkDevice _device,
4801 VkPipelineCache pipelineCache,
4802 uint32_t count,
4803 const VkComputePipelineCreateInfo* pCreateInfos,
4804 const VkAllocationCallbacks* pAllocator,
4805 VkPipeline* pPipelines)
4806 {
4807 VkResult result = VK_SUCCESS;
4808
4809 unsigned i = 0;
4810 for (; i < count; i++) {
4811 VkResult r;
4812 r = radv_compute_pipeline_create(_device, pipelineCache,
4813 &pCreateInfos[i],
4814 pAllocator, &pPipelines[i]);
4815 if (r != VK_SUCCESS) {
4816 result = r;
4817 pPipelines[i] = VK_NULL_HANDLE;
4818 }
4819 }
4820
4821 return result;
4822 }
4823
4824
4825 static uint32_t radv_get_executable_count(const struct radv_pipeline *pipeline)
4826 {
4827 uint32_t ret = 0;
4828 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
4829 if (pipeline->shaders[i])
4830 ret += i == MESA_SHADER_GEOMETRY ? 2u : 1u;
4831
4832 }
4833 return ret;
4834 }
4835
4836 static struct radv_shader_variant *
4837 radv_get_shader_from_executable_index(const struct radv_pipeline *pipeline, int index, gl_shader_stage *stage)
4838 {
4839 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
4840 if (!pipeline->shaders[i])
4841 continue;
4842 if (!index) {
4843 *stage = i;
4844 return pipeline->shaders[i];
4845 }
4846
4847 --index;
4848
4849 if (i == MESA_SHADER_GEOMETRY) {
4850 if (!index) {
4851 *stage = i;
4852 return pipeline->gs_copy_shader;
4853 }
4854 --index;
4855 }
4856 }
4857
4858 *stage = -1;
4859 return NULL;
4860 }
4861
4862 /* Basically strlcpy (which does not exist on linux) specialized for
4863 * descriptions. */
4864 static void desc_copy(char *desc, const char *src) {
4865 int len = strlen(src);
4866 assert(len < VK_MAX_DESCRIPTION_SIZE);
4867 memcpy(desc, src, len);
4868 memset(desc + len, 0, VK_MAX_DESCRIPTION_SIZE - len);
4869 }
4870
4871 VkResult radv_GetPipelineExecutablePropertiesKHR(
4872 VkDevice _device,
4873 const VkPipelineInfoKHR* pPipelineInfo,
4874 uint32_t* pExecutableCount,
4875 VkPipelineExecutablePropertiesKHR* pProperties)
4876 {
4877 RADV_FROM_HANDLE(radv_pipeline, pipeline, pPipelineInfo->pipeline);
4878 const uint32_t total_count = radv_get_executable_count(pipeline);
4879
4880 if (!pProperties) {
4881 *pExecutableCount = total_count;
4882 return VK_SUCCESS;
4883 }
4884
4885 const uint32_t count = MIN2(total_count, *pExecutableCount);
4886 for (unsigned i = 0, executable_idx = 0;
4887 i < MESA_SHADER_STAGES && executable_idx < count; ++i) {
4888 if (!pipeline->shaders[i])
4889 continue;
4890 pProperties[executable_idx].stages = mesa_to_vk_shader_stage(i);
4891 const char *name = NULL;
4892 const char *description = NULL;
4893 switch(i) {
4894 case MESA_SHADER_VERTEX:
4895 name = "Vertex Shader";
4896 description = "Vulkan Vertex Shader";
4897 break;
4898 case MESA_SHADER_TESS_CTRL:
4899 if (!pipeline->shaders[MESA_SHADER_VERTEX]) {
4900 pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT;
4901 name = "Vertex + Tessellation Control Shaders";
4902 description = "Combined Vulkan Vertex and Tessellation Control Shaders";
4903 } else {
4904 name = "Tessellation Control Shader";
4905 description = "Vulkan Tessellation Control Shader";
4906 }
4907 break;
4908 case MESA_SHADER_TESS_EVAL:
4909 name = "Tessellation Evaluation Shader";
4910 description = "Vulkan Tessellation Evaluation Shader";
4911 break;
4912 case MESA_SHADER_GEOMETRY:
4913 if (radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_TESS_EVAL]) {
4914 pProperties[executable_idx].stages |= VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT;
4915 name = "Tessellation Evaluation + Geometry Shaders";
4916 description = "Combined Vulkan Tessellation Evaluation and Geometry Shaders";
4917 } else if (!radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_VERTEX]) {
4918 pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT;
4919 name = "Vertex + Geometry Shader";
4920 description = "Combined Vulkan Vertex and Geometry Shaders";
4921 } else {
4922 name = "Geometry Shader";
4923 description = "Vulkan Geometry Shader";
4924 }
4925 break;
4926 case MESA_SHADER_FRAGMENT:
4927 name = "Fragment Shader";
4928 description = "Vulkan Fragment Shader";
4929 break;
4930 case MESA_SHADER_COMPUTE:
4931 name = "Compute Shader";
4932 description = "Vulkan Compute Shader";
4933 break;
4934 }
4935
4936 desc_copy(pProperties[executable_idx].name, name);
4937 desc_copy(pProperties[executable_idx].description, description);
4938
4939 ++executable_idx;
4940 if (i == MESA_SHADER_GEOMETRY) {
4941 assert(pipeline->gs_copy_shader);
4942 if (executable_idx >= count)
4943 break;
4944
4945 pProperties[executable_idx].stages = VK_SHADER_STAGE_GEOMETRY_BIT;
4946 desc_copy(pProperties[executable_idx].name, "GS Copy Shader");
4947 desc_copy(pProperties[executable_idx].description,
4948 "Extra shader stage that loads the GS output ringbuffer into the rasterizer");
4949
4950 ++executable_idx;
4951 }
4952 }
4953
4954 for (unsigned i = 0; i < count; ++i)
4955 pProperties[i].subgroupSize = 64;
4956
4957 VkResult result = *pExecutableCount < total_count ? VK_INCOMPLETE : VK_SUCCESS;
4958 *pExecutableCount = count;
4959 return result;
4960 }
4961
4962 VkResult radv_GetPipelineExecutableStatisticsKHR(
4963 VkDevice _device,
4964 const VkPipelineExecutableInfoKHR* pExecutableInfo,
4965 uint32_t* pStatisticCount,
4966 VkPipelineExecutableStatisticKHR* pStatistics)
4967 {
4968 RADV_FROM_HANDLE(radv_device, device, _device);
4969 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
4970 gl_shader_stage stage;
4971 struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
4972
4973 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
4974 unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
4975 unsigned max_waves = radv_get_max_waves(device, shader, stage);
4976
4977 VkPipelineExecutableStatisticKHR *s = pStatistics;
4978 VkPipelineExecutableStatisticKHR *end = s + (pStatistics ? *pStatisticCount : 0);
4979 VkResult result = VK_SUCCESS;
4980
4981 if (s < end) {
4982 desc_copy(s->name, "SGPRs");
4983 desc_copy(s->description, "Number of SGPR registers allocated per subgroup");
4984 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
4985 s->value.u64 = shader->config.num_sgprs;
4986 }
4987 ++s;
4988
4989 if (s < end) {
4990 desc_copy(s->name, "VGPRs");
4991 desc_copy(s->description, "Number of VGPR registers allocated per subgroup");
4992 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
4993 s->value.u64 = shader->config.num_vgprs;
4994 }
4995 ++s;
4996
4997 if (s < end) {
4998 desc_copy(s->name, "Spilled SGPRs");
4999 desc_copy(s->description, "Number of SGPR registers spilled per subgroup");
5000 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5001 s->value.u64 = shader->config.spilled_sgprs;
5002 }
5003 ++s;
5004
5005 if (s < end) {
5006 desc_copy(s->name, "Spilled VGPRs");
5007 desc_copy(s->description, "Number of VGPR registers spilled per subgroup");
5008 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5009 s->value.u64 = shader->config.spilled_vgprs;
5010 }
5011 ++s;
5012
5013 if (s < end) {
5014 desc_copy(s->name, "PrivMem VGPRs");
5015 desc_copy(s->description, "Number of VGPRs stored in private memory per subgroup");
5016 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5017 s->value.u64 = shader->info.private_mem_vgprs;
5018 }
5019 ++s;
5020
5021 if (s < end) {
5022 desc_copy(s->name, "Code size");
5023 desc_copy(s->description, "Code size in bytes");
5024 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5025 s->value.u64 = shader->code_size;
5026 }
5027 ++s;
5028
5029 if (s < end) {
5030 desc_copy(s->name, "LDS size");
5031 desc_copy(s->description, "LDS size in bytes per workgroup");
5032 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5033 s->value.u64 = shader->config.lds_size * lds_increment;
5034 }
5035 ++s;
5036
5037 if (s < end) {
5038 desc_copy(s->name, "Scratch size");
5039 desc_copy(s->description, "Private memory in bytes per subgroup");
5040 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5041 s->value.u64 = shader->config.scratch_bytes_per_wave;
5042 }
5043 ++s;
5044
5045 if (s < end) {
5046 desc_copy(s->name, "Subgroups per SIMD");
5047 desc_copy(s->description, "The maximum number of subgroups in flight on a SIMD unit");
5048 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5049 s->value.u64 = max_waves;
5050 }
5051 ++s;
5052
5053 if (!pStatistics)
5054 *pStatisticCount = s - pStatistics;
5055 else if (s > end) {
5056 *pStatisticCount = end - pStatistics;
5057 result = VK_INCOMPLETE;
5058 } else {
5059 *pStatisticCount = s - pStatistics;
5060 }
5061
5062 return result;
5063 }
5064
5065 static VkResult radv_copy_representation(void *data, size_t *data_size, const char *src)
5066 {
5067 size_t total_size = strlen(src) + 1;
5068
5069 if (!data) {
5070 *data_size = total_size;
5071 return VK_SUCCESS;
5072 }
5073
5074 size_t size = MIN2(total_size, *data_size);
5075
5076 memcpy(data, src, size);
5077 if (size)
5078 *((char*)data + size - 1) = 0;
5079 return size < total_size ? VK_INCOMPLETE : VK_SUCCESS;
5080 }
5081
5082 VkResult radv_GetPipelineExecutableInternalRepresentationsKHR(
5083 VkDevice device,
5084 const VkPipelineExecutableInfoKHR* pExecutableInfo,
5085 uint32_t* pInternalRepresentationCount,
5086 VkPipelineExecutableInternalRepresentationKHR* pInternalRepresentations)
5087 {
5088 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
5089 gl_shader_stage stage;
5090 struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
5091
5092 VkPipelineExecutableInternalRepresentationKHR *p = pInternalRepresentations;
5093 VkPipelineExecutableInternalRepresentationKHR *end = p + (pInternalRepresentations ? *pInternalRepresentationCount : 0);
5094 VkResult result = VK_SUCCESS;
5095 /* optimized NIR */
5096 if (p < end) {
5097 p->isText = true;
5098 desc_copy(p->name, "NIR Shader(s)");
5099 desc_copy(p->description, "The optimized NIR shader(s)");
5100 if (radv_copy_representation(p->pData, &p->dataSize, shader->nir_string) != VK_SUCCESS)
5101 result = VK_INCOMPLETE;
5102 }
5103 ++p;
5104
5105 /* LLVM IR */
5106 if (p < end) {
5107 p->isText = true;
5108 desc_copy(p->name, "LLVM IR");
5109 desc_copy(p->description, "The LLVM IR after some optimizations");
5110 if (radv_copy_representation(p->pData, &p->dataSize, shader->llvm_ir_string) != VK_SUCCESS)
5111 result = VK_INCOMPLETE;
5112 }
5113 ++p;
5114
5115 /* Disassembler */
5116 if (p < end) {
5117 p->isText = true;
5118 desc_copy(p->name, "Assembly");
5119 desc_copy(p->description, "Final Assembly");
5120 if (radv_copy_representation(p->pData, &p->dataSize, shader->disasm_string) != VK_SUCCESS)
5121 result = VK_INCOMPLETE;
5122 }
5123 ++p;
5124
5125 if (!pInternalRepresentations)
5126 *pInternalRepresentationCount = p - pInternalRepresentations;
5127 else if(p > end) {
5128 result = VK_INCOMPLETE;
5129 *pInternalRepresentationCount = end - pInternalRepresentations;
5130 } else {
5131 *pInternalRepresentationCount = p - pInternalRepresentations;
5132 }
5133
5134 return result;
5135 }