2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "util/disk_cache.h"
29 #include "util/mesa-sha1.h"
30 #include "util/u_atomic.h"
31 #include "radv_debug.h"
32 #include "radv_private.h"
34 #include "radv_shader.h"
36 #include "nir/nir_builder.h"
37 #include "nir/nir_xfb_info.h"
38 #include "spirv/nir_spirv.h"
41 #include <llvm-c/Core.h>
42 #include <llvm-c/TargetMachine.h>
45 #include "ac_binary.h"
46 #include "ac_llvm_util.h"
47 #include "ac_nir_to_llvm.h"
48 #include "vk_format.h"
49 #include "util/debug.h"
50 #include "ac_exp_param.h"
51 #include "ac_shader_util.h"
52 #include "main/menums.h"
54 struct radv_blend_state
{
55 uint32_t blend_enable_4bit
;
56 uint32_t need_src_alpha
;
58 uint32_t cb_color_control
;
59 uint32_t cb_target_mask
;
60 uint32_t cb_target_enabled_4bit
;
61 uint32_t sx_mrt_blend_opt
[8];
62 uint32_t cb_blend_control
[8];
64 uint32_t spi_shader_col_format
;
65 uint32_t cb_shader_mask
;
66 uint32_t db_alpha_to_mask
;
68 uint32_t commutative_4bit
;
70 bool single_cb_enable
;
71 bool mrt0_is_dual_src
;
74 struct radv_dsa_order_invariance
{
75 /* Whether the final result in Z/S buffers is guaranteed to be
76 * invariant under changes to the order in which fragments arrive.
80 /* Whether the set of fragments that pass the combined Z/S test is
81 * guaranteed to be invariant under changes to the order in which
87 struct radv_tessellation_state
{
88 uint32_t ls_hs_config
;
94 static const VkPipelineMultisampleStateCreateInfo
*
95 radv_pipeline_get_multisample_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
97 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
)
98 return pCreateInfo
->pMultisampleState
;
102 static const VkPipelineTessellationStateCreateInfo
*
103 radv_pipeline_get_tessellation_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
105 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
106 if (pCreateInfo
->pStages
[i
].stage
== VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
||
107 pCreateInfo
->pStages
[i
].stage
== VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
) {
108 return pCreateInfo
->pTessellationState
;
114 static const VkPipelineDepthStencilStateCreateInfo
*
115 radv_pipeline_get_depth_stencil_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
117 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
118 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
120 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
121 subpass
->depth_stencil_attachment
)
122 return pCreateInfo
->pDepthStencilState
;
126 static const VkPipelineColorBlendStateCreateInfo
*
127 radv_pipeline_get_color_blend_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
129 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
130 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
132 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
133 subpass
->has_color_att
)
134 return pCreateInfo
->pColorBlendState
;
138 bool radv_pipeline_has_ngg(const struct radv_pipeline
*pipeline
)
140 struct radv_shader_variant
*variant
= NULL
;
141 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
142 variant
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
143 else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
144 variant
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
145 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
146 variant
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
149 return variant
->info
.is_ngg
;
152 bool radv_pipeline_has_ngg_passthrough(const struct radv_pipeline
*pipeline
)
154 assert(radv_pipeline_has_ngg(pipeline
));
156 struct radv_shader_variant
*variant
= NULL
;
157 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
158 variant
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
159 else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
160 variant
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
161 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
162 variant
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
165 return variant
->info
.is_ngg_passthrough
;
168 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline
*pipeline
)
170 if (!radv_pipeline_has_gs(pipeline
))
173 /* The GS copy shader is required if the pipeline has GS on GFX6-GFX9.
174 * On GFX10, it might be required in rare cases if it's not possible to
177 if (radv_pipeline_has_ngg(pipeline
))
180 assert(pipeline
->gs_copy_shader
);
185 radv_pipeline_destroy(struct radv_device
*device
,
186 struct radv_pipeline
*pipeline
,
187 const VkAllocationCallbacks
* allocator
)
189 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
190 if (pipeline
->shaders
[i
])
191 radv_shader_variant_destroy(device
, pipeline
->shaders
[i
]);
193 if (pipeline
->gs_copy_shader
)
194 radv_shader_variant_destroy(device
, pipeline
->gs_copy_shader
);
197 free(pipeline
->cs
.buf
);
198 vk_free2(&device
->alloc
, allocator
, pipeline
);
201 void radv_DestroyPipeline(
203 VkPipeline _pipeline
,
204 const VkAllocationCallbacks
* pAllocator
)
206 RADV_FROM_HANDLE(radv_device
, device
, _device
);
207 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
212 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
215 static uint32_t get_hash_flags(struct radv_device
*device
)
217 uint32_t hash_flags
= 0;
219 if (device
->instance
->debug_flags
& RADV_DEBUG_NO_NGG
)
220 hash_flags
|= RADV_HASH_SHADER_NO_NGG
;
221 if (device
->physical_device
->cs_wave_size
== 32)
222 hash_flags
|= RADV_HASH_SHADER_CS_WAVE32
;
223 if (device
->physical_device
->ps_wave_size
== 32)
224 hash_flags
|= RADV_HASH_SHADER_PS_WAVE32
;
225 if (device
->physical_device
->ge_wave_size
== 32)
226 hash_flags
|= RADV_HASH_SHADER_GE_WAVE32
;
227 if (device
->physical_device
->use_aco
)
228 hash_flags
|= RADV_HASH_SHADER_ACO
;
233 radv_pipeline_scratch_init(struct radv_device
*device
,
234 struct radv_pipeline
*pipeline
)
236 unsigned scratch_bytes_per_wave
= 0;
237 unsigned max_waves
= 0;
238 unsigned min_waves
= 1;
240 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
241 if (pipeline
->shaders
[i
] &&
242 pipeline
->shaders
[i
]->config
.scratch_bytes_per_wave
) {
243 unsigned max_stage_waves
= device
->scratch_waves
;
245 scratch_bytes_per_wave
= MAX2(scratch_bytes_per_wave
,
246 pipeline
->shaders
[i
]->config
.scratch_bytes_per_wave
);
248 max_stage_waves
= MIN2(max_stage_waves
,
249 4 * device
->physical_device
->rad_info
.num_good_compute_units
*
250 (256 / pipeline
->shaders
[i
]->config
.num_vgprs
));
251 max_waves
= MAX2(max_waves
, max_stage_waves
);
255 if (pipeline
->shaders
[MESA_SHADER_COMPUTE
]) {
256 unsigned group_size
= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[0] *
257 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[1] *
258 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[2];
259 min_waves
= MAX2(min_waves
, round_up_u32(group_size
, 64));
262 pipeline
->scratch_bytes_per_wave
= scratch_bytes_per_wave
;
263 pipeline
->max_waves
= max_waves
;
267 static uint32_t si_translate_blend_logic_op(VkLogicOp op
)
270 case VK_LOGIC_OP_CLEAR
:
271 return V_028808_ROP3_CLEAR
;
272 case VK_LOGIC_OP_AND
:
273 return V_028808_ROP3_AND
;
274 case VK_LOGIC_OP_AND_REVERSE
:
275 return V_028808_ROP3_AND_REVERSE
;
276 case VK_LOGIC_OP_COPY
:
277 return V_028808_ROP3_COPY
;
278 case VK_LOGIC_OP_AND_INVERTED
:
279 return V_028808_ROP3_AND_INVERTED
;
280 case VK_LOGIC_OP_NO_OP
:
281 return V_028808_ROP3_NO_OP
;
282 case VK_LOGIC_OP_XOR
:
283 return V_028808_ROP3_XOR
;
285 return V_028808_ROP3_OR
;
286 case VK_LOGIC_OP_NOR
:
287 return V_028808_ROP3_NOR
;
288 case VK_LOGIC_OP_EQUIVALENT
:
289 return V_028808_ROP3_EQUIVALENT
;
290 case VK_LOGIC_OP_INVERT
:
291 return V_028808_ROP3_INVERT
;
292 case VK_LOGIC_OP_OR_REVERSE
:
293 return V_028808_ROP3_OR_REVERSE
;
294 case VK_LOGIC_OP_COPY_INVERTED
:
295 return V_028808_ROP3_COPY_INVERTED
;
296 case VK_LOGIC_OP_OR_INVERTED
:
297 return V_028808_ROP3_OR_INVERTED
;
298 case VK_LOGIC_OP_NAND
:
299 return V_028808_ROP3_NAND
;
300 case VK_LOGIC_OP_SET
:
301 return V_028808_ROP3_SET
;
303 unreachable("Unhandled logic op");
308 static uint32_t si_translate_blend_function(VkBlendOp op
)
311 case VK_BLEND_OP_ADD
:
312 return V_028780_COMB_DST_PLUS_SRC
;
313 case VK_BLEND_OP_SUBTRACT
:
314 return V_028780_COMB_SRC_MINUS_DST
;
315 case VK_BLEND_OP_REVERSE_SUBTRACT
:
316 return V_028780_COMB_DST_MINUS_SRC
;
317 case VK_BLEND_OP_MIN
:
318 return V_028780_COMB_MIN_DST_SRC
;
319 case VK_BLEND_OP_MAX
:
320 return V_028780_COMB_MAX_DST_SRC
;
326 static uint32_t si_translate_blend_factor(VkBlendFactor factor
)
329 case VK_BLEND_FACTOR_ZERO
:
330 return V_028780_BLEND_ZERO
;
331 case VK_BLEND_FACTOR_ONE
:
332 return V_028780_BLEND_ONE
;
333 case VK_BLEND_FACTOR_SRC_COLOR
:
334 return V_028780_BLEND_SRC_COLOR
;
335 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
336 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
337 case VK_BLEND_FACTOR_DST_COLOR
:
338 return V_028780_BLEND_DST_COLOR
;
339 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
:
340 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
341 case VK_BLEND_FACTOR_SRC_ALPHA
:
342 return V_028780_BLEND_SRC_ALPHA
;
343 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
344 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
345 case VK_BLEND_FACTOR_DST_ALPHA
:
346 return V_028780_BLEND_DST_ALPHA
;
347 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
:
348 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
349 case VK_BLEND_FACTOR_CONSTANT_COLOR
:
350 return V_028780_BLEND_CONSTANT_COLOR
;
351 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
:
352 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
353 case VK_BLEND_FACTOR_CONSTANT_ALPHA
:
354 return V_028780_BLEND_CONSTANT_ALPHA
;
355 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
:
356 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
357 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
358 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
359 case VK_BLEND_FACTOR_SRC1_COLOR
:
360 return V_028780_BLEND_SRC1_COLOR
;
361 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
362 return V_028780_BLEND_INV_SRC1_COLOR
;
363 case VK_BLEND_FACTOR_SRC1_ALPHA
:
364 return V_028780_BLEND_SRC1_ALPHA
;
365 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
366 return V_028780_BLEND_INV_SRC1_ALPHA
;
372 static uint32_t si_translate_blend_opt_function(VkBlendOp op
)
375 case VK_BLEND_OP_ADD
:
376 return V_028760_OPT_COMB_ADD
;
377 case VK_BLEND_OP_SUBTRACT
:
378 return V_028760_OPT_COMB_SUBTRACT
;
379 case VK_BLEND_OP_REVERSE_SUBTRACT
:
380 return V_028760_OPT_COMB_REVSUBTRACT
;
381 case VK_BLEND_OP_MIN
:
382 return V_028760_OPT_COMB_MIN
;
383 case VK_BLEND_OP_MAX
:
384 return V_028760_OPT_COMB_MAX
;
386 return V_028760_OPT_COMB_BLEND_DISABLED
;
390 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor
, bool is_alpha
)
393 case VK_BLEND_FACTOR_ZERO
:
394 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
;
395 case VK_BLEND_FACTOR_ONE
:
396 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
;
397 case VK_BLEND_FACTOR_SRC_COLOR
:
398 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
399 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0
;
400 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
401 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
402 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1
;
403 case VK_BLEND_FACTOR_SRC_ALPHA
:
404 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
;
405 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
406 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
;
407 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
408 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
409 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
411 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
416 * Get rid of DST in the blend factors by commuting the operands:
417 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
419 static void si_blend_remove_dst(unsigned *func
, unsigned *src_factor
,
420 unsigned *dst_factor
, unsigned expected_dst
,
421 unsigned replacement_src
)
423 if (*src_factor
== expected_dst
&&
424 *dst_factor
== VK_BLEND_FACTOR_ZERO
) {
425 *src_factor
= VK_BLEND_FACTOR_ZERO
;
426 *dst_factor
= replacement_src
;
428 /* Commuting the operands requires reversing subtractions. */
429 if (*func
== VK_BLEND_OP_SUBTRACT
)
430 *func
= VK_BLEND_OP_REVERSE_SUBTRACT
;
431 else if (*func
== VK_BLEND_OP_REVERSE_SUBTRACT
)
432 *func
= VK_BLEND_OP_SUBTRACT
;
436 static bool si_blend_factor_uses_dst(unsigned factor
)
438 return factor
== VK_BLEND_FACTOR_DST_COLOR
||
439 factor
== VK_BLEND_FACTOR_DST_ALPHA
||
440 factor
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
441 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
||
442 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
;
445 static bool is_dual_src(VkBlendFactor factor
)
448 case VK_BLEND_FACTOR_SRC1_COLOR
:
449 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
450 case VK_BLEND_FACTOR_SRC1_ALPHA
:
451 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
458 static unsigned si_choose_spi_color_format(VkFormat vk_format
,
460 bool blend_need_alpha
)
462 const struct vk_format_description
*desc
= vk_format_description(vk_format
);
463 unsigned format
, ntype
, swap
;
465 /* Alpha is needed for alpha-to-coverage.
466 * Blending may be with or without alpha.
468 unsigned normal
= 0; /* most optimal, may not support blending or export alpha */
469 unsigned alpha
= 0; /* exports alpha, but may not support blending */
470 unsigned blend
= 0; /* supports blending, but may not export alpha */
471 unsigned blend_alpha
= 0; /* least optimal, supports blending and exports alpha */
473 format
= radv_translate_colorformat(vk_format
);
474 ntype
= radv_translate_color_numformat(vk_format
, desc
,
475 vk_format_get_first_non_void_channel(vk_format
));
476 swap
= radv_translate_colorswap(vk_format
, false);
478 /* Choose the SPI color formats. These are required values for Stoney/RB+.
479 * Other chips have multiple choices, though they are not necessarily better.
482 case V_028C70_COLOR_5_6_5
:
483 case V_028C70_COLOR_1_5_5_5
:
484 case V_028C70_COLOR_5_5_5_1
:
485 case V_028C70_COLOR_4_4_4_4
:
486 case V_028C70_COLOR_10_11_11
:
487 case V_028C70_COLOR_11_11_10
:
488 case V_028C70_COLOR_8
:
489 case V_028C70_COLOR_8_8
:
490 case V_028C70_COLOR_8_8_8_8
:
491 case V_028C70_COLOR_10_10_10_2
:
492 case V_028C70_COLOR_2_10_10_10
:
493 if (ntype
== V_028C70_NUMBER_UINT
)
494 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
495 else if (ntype
== V_028C70_NUMBER_SINT
)
496 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
498 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
501 case V_028C70_COLOR_16
:
502 case V_028C70_COLOR_16_16
:
503 case V_028C70_COLOR_16_16_16_16
:
504 if (ntype
== V_028C70_NUMBER_UNORM
||
505 ntype
== V_028C70_NUMBER_SNORM
) {
506 /* UNORM16 and SNORM16 don't support blending */
507 if (ntype
== V_028C70_NUMBER_UNORM
)
508 normal
= alpha
= V_028714_SPI_SHADER_UNORM16_ABGR
;
510 normal
= alpha
= V_028714_SPI_SHADER_SNORM16_ABGR
;
512 /* Use 32 bits per channel for blending. */
513 if (format
== V_028C70_COLOR_16
) {
514 if (swap
== V_028C70_SWAP_STD
) { /* R */
515 blend
= V_028714_SPI_SHADER_32_R
;
516 blend_alpha
= V_028714_SPI_SHADER_32_AR
;
517 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
518 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
521 } else if (format
== V_028C70_COLOR_16_16
) {
522 if (swap
== V_028C70_SWAP_STD
) { /* RG */
523 blend
= V_028714_SPI_SHADER_32_GR
;
524 blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
525 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
526 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
529 } else /* 16_16_16_16 */
530 blend
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
531 } else if (ntype
== V_028C70_NUMBER_UINT
)
532 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
533 else if (ntype
== V_028C70_NUMBER_SINT
)
534 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
535 else if (ntype
== V_028C70_NUMBER_FLOAT
)
536 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
541 case V_028C70_COLOR_32
:
542 if (swap
== V_028C70_SWAP_STD
) { /* R */
543 blend
= normal
= V_028714_SPI_SHADER_32_R
;
544 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
545 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
546 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
551 case V_028C70_COLOR_32_32
:
552 if (swap
== V_028C70_SWAP_STD
) { /* RG */
553 blend
= normal
= V_028714_SPI_SHADER_32_GR
;
554 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
555 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
556 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
561 case V_028C70_COLOR_32_32_32_32
:
562 case V_028C70_COLOR_8_24
:
563 case V_028C70_COLOR_24_8
:
564 case V_028C70_COLOR_X24_8_32_FLOAT
:
565 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
569 unreachable("unhandled blend format");
572 if (blend_enable
&& blend_need_alpha
)
574 else if(blend_need_alpha
)
576 else if(blend_enable
)
583 radv_pipeline_compute_spi_color_formats(struct radv_pipeline
*pipeline
,
584 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
585 struct radv_blend_state
*blend
)
587 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
588 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
589 unsigned col_format
= 0;
590 unsigned num_targets
;
592 for (unsigned i
= 0; i
< (blend
->single_cb_enable
? 1 : subpass
->color_count
); ++i
) {
595 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
596 cf
= V_028714_SPI_SHADER_ZERO
;
598 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
600 blend
->blend_enable_4bit
& (0xfu
<< (i
* 4));
602 cf
= si_choose_spi_color_format(attachment
->format
,
604 blend
->need_src_alpha
& (1 << i
));
607 col_format
|= cf
<< (4 * i
);
610 if (!(col_format
& 0xf) && blend
->need_src_alpha
& (1 << 0)) {
611 /* When a subpass doesn't have any color attachments, write the
612 * alpha channel of MRT0 when alpha coverage is enabled because
613 * the depth attachment needs it.
615 col_format
|= V_028714_SPI_SHADER_32_AR
;
618 /* If the i-th target format is set, all previous target formats must
619 * be non-zero to avoid hangs.
621 num_targets
= (util_last_bit(col_format
) + 3) / 4;
622 for (unsigned i
= 0; i
< num_targets
; i
++) {
623 if (!(col_format
& (0xf << (i
* 4)))) {
624 col_format
|= V_028714_SPI_SHADER_32_R
<< (i
* 4);
628 /* The output for dual source blending should have the same format as
631 if (blend
->mrt0_is_dual_src
)
632 col_format
|= (col_format
& 0xf) << 4;
634 blend
->cb_shader_mask
= ac_get_cb_shader_mask(col_format
);
635 blend
->spi_shader_col_format
= col_format
;
639 format_is_int8(VkFormat format
)
641 const struct vk_format_description
*desc
= vk_format_description(format
);
642 int channel
= vk_format_get_first_non_void_channel(format
);
644 return channel
>= 0 && desc
->channel
[channel
].pure_integer
&&
645 desc
->channel
[channel
].size
== 8;
649 format_is_int10(VkFormat format
)
651 const struct vk_format_description
*desc
= vk_format_description(format
);
653 if (desc
->nr_channels
!= 4)
655 for (unsigned i
= 0; i
< 4; i
++) {
656 if (desc
->channel
[i
].pure_integer
&& desc
->channel
[i
].size
== 10)
663 * Ordered so that for each i,
664 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
666 const VkFormat radv_fs_key_format_exemplars
[NUM_META_FS_KEYS
] = {
667 VK_FORMAT_R32_SFLOAT
,
668 VK_FORMAT_R32G32_SFLOAT
,
669 VK_FORMAT_R8G8B8A8_UNORM
,
670 VK_FORMAT_R16G16B16A16_UNORM
,
671 VK_FORMAT_R16G16B16A16_SNORM
,
672 VK_FORMAT_R16G16B16A16_UINT
,
673 VK_FORMAT_R16G16B16A16_SINT
,
674 VK_FORMAT_R32G32B32A32_SFLOAT
,
675 VK_FORMAT_R8G8B8A8_UINT
,
676 VK_FORMAT_R8G8B8A8_SINT
,
677 VK_FORMAT_A2R10G10B10_UINT_PACK32
,
678 VK_FORMAT_A2R10G10B10_SINT_PACK32
,
681 unsigned radv_format_meta_fs_key(VkFormat format
)
683 unsigned col_format
= si_choose_spi_color_format(format
, false, false);
685 assert(col_format
!= V_028714_SPI_SHADER_32_AR
);
686 if (col_format
>= V_028714_SPI_SHADER_32_AR
)
687 --col_format
; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
689 --col_format
; /* Skip V_028714_SPI_SHADER_ZERO */
690 bool is_int8
= format_is_int8(format
);
691 bool is_int10
= format_is_int10(format
);
693 return col_format
+ (is_int8
? 3 : is_int10
? 5 : 0);
697 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
698 unsigned *is_int8
, unsigned *is_int10
)
700 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
701 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
705 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
706 struct radv_render_pass_attachment
*attachment
;
708 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
711 attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
713 if (format_is_int8(attachment
->format
))
715 if (format_is_int10(attachment
->format
))
721 radv_blend_check_commutativity(struct radv_blend_state
*blend
,
722 VkBlendOp op
, VkBlendFactor src
,
723 VkBlendFactor dst
, unsigned chanmask
)
725 /* Src factor is allowed when it does not depend on Dst. */
726 static const uint32_t src_allowed
=
727 (1u << VK_BLEND_FACTOR_ONE
) |
728 (1u << VK_BLEND_FACTOR_SRC_COLOR
) |
729 (1u << VK_BLEND_FACTOR_SRC_ALPHA
) |
730 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
) |
731 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR
) |
732 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA
) |
733 (1u << VK_BLEND_FACTOR_SRC1_COLOR
) |
734 (1u << VK_BLEND_FACTOR_SRC1_ALPHA
) |
735 (1u << VK_BLEND_FACTOR_ZERO
) |
736 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
) |
737 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
) |
738 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
) |
739 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
) |
740 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
) |
741 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
);
743 if (dst
== VK_BLEND_FACTOR_ONE
&&
744 (src_allowed
& (1u << src
))) {
745 /* Addition is commutative, but floating point addition isn't
746 * associative: subtle changes can be introduced via different
747 * rounding. Be conservative, only enable for min and max.
749 if (op
== VK_BLEND_OP_MAX
|| op
== VK_BLEND_OP_MIN
)
750 blend
->commutative_4bit
|= chanmask
;
754 static struct radv_blend_state
755 radv_pipeline_init_blend_state(struct radv_pipeline
*pipeline
,
756 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
757 const struct radv_graphics_pipeline_create_info
*extra
)
759 const VkPipelineColorBlendStateCreateInfo
*vkblend
= radv_pipeline_get_color_blend_state(pCreateInfo
);
760 const VkPipelineMultisampleStateCreateInfo
*vkms
= radv_pipeline_get_multisample_state(pCreateInfo
);
761 struct radv_blend_state blend
= {0};
762 unsigned mode
= V_028808_CB_NORMAL
;
765 if (extra
&& extra
->custom_blend_mode
) {
766 blend
.single_cb_enable
= true;
767 mode
= extra
->custom_blend_mode
;
770 blend
.cb_color_control
= 0;
772 if (vkblend
->logicOpEnable
)
773 blend
.cb_color_control
|= S_028808_ROP3(si_translate_blend_logic_op(vkblend
->logicOp
));
775 blend
.cb_color_control
|= S_028808_ROP3(V_028808_ROP3_COPY
);
778 blend
.db_alpha_to_mask
= S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
779 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
780 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
781 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
782 S_028B70_OFFSET_ROUND(1);
784 if (vkms
&& vkms
->alphaToCoverageEnable
) {
785 blend
.db_alpha_to_mask
|= S_028B70_ALPHA_TO_MASK_ENABLE(1);
786 blend
.need_src_alpha
|= 0x1;
789 blend
.cb_target_mask
= 0;
791 for (i
= 0; i
< vkblend
->attachmentCount
; i
++) {
792 const VkPipelineColorBlendAttachmentState
*att
= &vkblend
->pAttachments
[i
];
793 unsigned blend_cntl
= 0;
794 unsigned srcRGB_opt
, dstRGB_opt
, srcA_opt
, dstA_opt
;
795 VkBlendOp eqRGB
= att
->colorBlendOp
;
796 VkBlendFactor srcRGB
= att
->srcColorBlendFactor
;
797 VkBlendFactor dstRGB
= att
->dstColorBlendFactor
;
798 VkBlendOp eqA
= att
->alphaBlendOp
;
799 VkBlendFactor srcA
= att
->srcAlphaBlendFactor
;
800 VkBlendFactor dstA
= att
->dstAlphaBlendFactor
;
802 blend
.sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
804 if (!att
->colorWriteMask
)
807 blend
.cb_target_mask
|= (unsigned)att
->colorWriteMask
<< (4 * i
);
808 blend
.cb_target_enabled_4bit
|= 0xf << (4 * i
);
809 if (!att
->blendEnable
) {
810 blend
.cb_blend_control
[i
] = blend_cntl
;
814 if (is_dual_src(srcRGB
) || is_dual_src(dstRGB
) || is_dual_src(srcA
) || is_dual_src(dstA
))
816 blend
.mrt0_is_dual_src
= true;
818 if (eqRGB
== VK_BLEND_OP_MIN
|| eqRGB
== VK_BLEND_OP_MAX
) {
819 srcRGB
= VK_BLEND_FACTOR_ONE
;
820 dstRGB
= VK_BLEND_FACTOR_ONE
;
822 if (eqA
== VK_BLEND_OP_MIN
|| eqA
== VK_BLEND_OP_MAX
) {
823 srcA
= VK_BLEND_FACTOR_ONE
;
824 dstA
= VK_BLEND_FACTOR_ONE
;
827 radv_blend_check_commutativity(&blend
, eqRGB
, srcRGB
, dstRGB
,
829 radv_blend_check_commutativity(&blend
, eqA
, srcA
, dstA
,
832 /* Blending optimizations for RB+.
833 * These transformations don't change the behavior.
835 * First, get rid of DST in the blend factors:
836 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
838 si_blend_remove_dst(&eqRGB
, &srcRGB
, &dstRGB
,
839 VK_BLEND_FACTOR_DST_COLOR
,
840 VK_BLEND_FACTOR_SRC_COLOR
);
842 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
843 VK_BLEND_FACTOR_DST_COLOR
,
844 VK_BLEND_FACTOR_SRC_COLOR
);
846 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
847 VK_BLEND_FACTOR_DST_ALPHA
,
848 VK_BLEND_FACTOR_SRC_ALPHA
);
850 /* Look up the ideal settings from tables. */
851 srcRGB_opt
= si_translate_blend_opt_factor(srcRGB
, false);
852 dstRGB_opt
= si_translate_blend_opt_factor(dstRGB
, false);
853 srcA_opt
= si_translate_blend_opt_factor(srcA
, true);
854 dstA_opt
= si_translate_blend_opt_factor(dstA
, true);
856 /* Handle interdependencies. */
857 if (si_blend_factor_uses_dst(srcRGB
))
858 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
859 if (si_blend_factor_uses_dst(srcA
))
860 dstA_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
862 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
&&
863 (dstRGB
== VK_BLEND_FACTOR_ZERO
||
864 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
865 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
))
866 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
868 /* Set the final value. */
869 blend
.sx_mrt_blend_opt
[i
] =
870 S_028760_COLOR_SRC_OPT(srcRGB_opt
) |
871 S_028760_COLOR_DST_OPT(dstRGB_opt
) |
872 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB
)) |
873 S_028760_ALPHA_SRC_OPT(srcA_opt
) |
874 S_028760_ALPHA_DST_OPT(dstA_opt
) |
875 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA
));
876 blend_cntl
|= S_028780_ENABLE(1);
878 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
879 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
880 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
881 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
882 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
883 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
884 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
885 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
887 blend
.cb_blend_control
[i
] = blend_cntl
;
889 blend
.blend_enable_4bit
|= 0xfu
<< (i
* 4);
891 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
892 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
893 srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
894 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
895 srcRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
||
896 dstRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
)
897 blend
.need_src_alpha
|= 1 << i
;
899 for (i
= vkblend
->attachmentCount
; i
< 8; i
++) {
900 blend
.cb_blend_control
[i
] = 0;
901 blend
.sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
905 if (pipeline
->device
->physical_device
->rad_info
.has_rbplus
) {
906 /* Disable RB+ blend optimizations for dual source blending. */
907 if (blend
.mrt0_is_dual_src
) {
908 for (i
= 0; i
< 8; i
++) {
909 blend
.sx_mrt_blend_opt
[i
] =
910 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE
) |
911 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE
);
915 /* RB+ doesn't work with dual source blending, logic op and
918 if (blend
.mrt0_is_dual_src
||
919 (vkblend
&& vkblend
->logicOpEnable
) ||
920 mode
== V_028808_CB_RESOLVE
)
921 blend
.cb_color_control
|= S_028808_DISABLE_DUAL_QUAD(1);
924 if (blend
.cb_target_mask
)
925 blend
.cb_color_control
|= S_028808_MODE(mode
);
927 blend
.cb_color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
929 radv_pipeline_compute_spi_color_formats(pipeline
, pCreateInfo
, &blend
);
933 static uint32_t si_translate_stencil_op(enum VkStencilOp op
)
936 case VK_STENCIL_OP_KEEP
:
937 return V_02842C_STENCIL_KEEP
;
938 case VK_STENCIL_OP_ZERO
:
939 return V_02842C_STENCIL_ZERO
;
940 case VK_STENCIL_OP_REPLACE
:
941 return V_02842C_STENCIL_REPLACE_TEST
;
942 case VK_STENCIL_OP_INCREMENT_AND_CLAMP
:
943 return V_02842C_STENCIL_ADD_CLAMP
;
944 case VK_STENCIL_OP_DECREMENT_AND_CLAMP
:
945 return V_02842C_STENCIL_SUB_CLAMP
;
946 case VK_STENCIL_OP_INVERT
:
947 return V_02842C_STENCIL_INVERT
;
948 case VK_STENCIL_OP_INCREMENT_AND_WRAP
:
949 return V_02842C_STENCIL_ADD_WRAP
;
950 case VK_STENCIL_OP_DECREMENT_AND_WRAP
:
951 return V_02842C_STENCIL_SUB_WRAP
;
957 static uint32_t si_translate_fill(VkPolygonMode func
)
960 case VK_POLYGON_MODE_FILL
:
961 return V_028814_X_DRAW_TRIANGLES
;
962 case VK_POLYGON_MODE_LINE
:
963 return V_028814_X_DRAW_LINES
;
964 case VK_POLYGON_MODE_POINT
:
965 return V_028814_X_DRAW_POINTS
;
968 return V_028814_X_DRAW_POINTS
;
972 static uint8_t radv_pipeline_get_ps_iter_samples(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
974 const VkPipelineMultisampleStateCreateInfo
*vkms
= pCreateInfo
->pMultisampleState
;
975 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
976 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
977 uint32_t ps_iter_samples
= 1;
978 uint32_t num_samples
;
980 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
982 * "If the VK_AMD_mixed_attachment_samples extension is enabled and the
983 * subpass uses color attachments, totalSamples is the number of
984 * samples of the color attachments. Otherwise, totalSamples is the
985 * value of VkPipelineMultisampleStateCreateInfo::rasterizationSamples
986 * specified at pipeline creation time."
988 if (subpass
->has_color_att
) {
989 num_samples
= subpass
->color_sample_count
;
991 num_samples
= vkms
->rasterizationSamples
;
994 if (vkms
->sampleShadingEnable
) {
995 ps_iter_samples
= ceil(vkms
->minSampleShading
* num_samples
);
996 ps_iter_samples
= util_next_power_of_two(ps_iter_samples
);
998 return ps_iter_samples
;
1002 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
1004 return pCreateInfo
->depthTestEnable
&&
1005 pCreateInfo
->depthWriteEnable
&&
1006 pCreateInfo
->depthCompareOp
!= VK_COMPARE_OP_NEVER
;
1010 radv_writes_stencil(const VkStencilOpState
*state
)
1012 return state
->writeMask
&&
1013 (state
->failOp
!= VK_STENCIL_OP_KEEP
||
1014 state
->passOp
!= VK_STENCIL_OP_KEEP
||
1015 state
->depthFailOp
!= VK_STENCIL_OP_KEEP
);
1019 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
1021 return pCreateInfo
->stencilTestEnable
&&
1022 (radv_writes_stencil(&pCreateInfo
->front
) ||
1023 radv_writes_stencil(&pCreateInfo
->back
));
1027 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
1029 return radv_is_depth_write_enabled(pCreateInfo
) ||
1030 radv_is_stencil_write_enabled(pCreateInfo
);
1034 radv_order_invariant_stencil_op(VkStencilOp op
)
1036 /* REPLACE is normally order invariant, except when the stencil
1037 * reference value is written by the fragment shader. Tracking this
1038 * interaction does not seem worth the effort, so be conservative.
1040 return op
!= VK_STENCIL_OP_INCREMENT_AND_CLAMP
&&
1041 op
!= VK_STENCIL_OP_DECREMENT_AND_CLAMP
&&
1042 op
!= VK_STENCIL_OP_REPLACE
;
1046 radv_order_invariant_stencil_state(const VkStencilOpState
*state
)
1048 /* Compute whether, assuming Z writes are disabled, this stencil state
1049 * is order invariant in the sense that the set of passing fragments as
1050 * well as the final stencil buffer result does not depend on the order
1053 return !state
->writeMask
||
1054 /* The following assumes that Z writes are disabled. */
1055 (state
->compareOp
== VK_COMPARE_OP_ALWAYS
&&
1056 radv_order_invariant_stencil_op(state
->passOp
) &&
1057 radv_order_invariant_stencil_op(state
->depthFailOp
)) ||
1058 (state
->compareOp
== VK_COMPARE_OP_NEVER
&&
1059 radv_order_invariant_stencil_op(state
->failOp
));
1063 radv_pipeline_out_of_order_rast(struct radv_pipeline
*pipeline
,
1064 struct radv_blend_state
*blend
,
1065 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1067 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1068 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
1069 const VkPipelineDepthStencilStateCreateInfo
*vkds
= radv_pipeline_get_depth_stencil_state(pCreateInfo
);
1070 const VkPipelineColorBlendStateCreateInfo
*vkblend
= radv_pipeline_get_color_blend_state(pCreateInfo
);
1071 unsigned colormask
= blend
->cb_target_enabled_4bit
;
1073 if (!pipeline
->device
->physical_device
->out_of_order_rast_allowed
)
1076 /* Be conservative if a logic operation is enabled with color buffers. */
1077 if (colormask
&& vkblend
&& vkblend
->logicOpEnable
)
1080 /* Default depth/stencil invariance when no attachment is bound. */
1081 struct radv_dsa_order_invariance dsa_order_invariant
= {
1082 .zs
= true, .pass_set
= true
1086 struct radv_render_pass_attachment
*attachment
=
1087 pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
1088 bool has_stencil
= vk_format_is_stencil(attachment
->format
);
1089 struct radv_dsa_order_invariance order_invariance
[2];
1090 struct radv_shader_variant
*ps
=
1091 pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
1093 /* Compute depth/stencil order invariance in order to know if
1094 * it's safe to enable out-of-order.
1096 bool zfunc_is_ordered
=
1097 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
||
1098 vkds
->depthCompareOp
== VK_COMPARE_OP_LESS
||
1099 vkds
->depthCompareOp
== VK_COMPARE_OP_LESS_OR_EQUAL
||
1100 vkds
->depthCompareOp
== VK_COMPARE_OP_GREATER
||
1101 vkds
->depthCompareOp
== VK_COMPARE_OP_GREATER_OR_EQUAL
;
1103 bool nozwrite_and_order_invariant_stencil
=
1104 !radv_is_ds_write_enabled(vkds
) ||
1105 (!radv_is_depth_write_enabled(vkds
) &&
1106 radv_order_invariant_stencil_state(&vkds
->front
) &&
1107 radv_order_invariant_stencil_state(&vkds
->back
));
1109 order_invariance
[1].zs
=
1110 nozwrite_and_order_invariant_stencil
||
1111 (!radv_is_stencil_write_enabled(vkds
) &&
1113 order_invariance
[0].zs
=
1114 !radv_is_depth_write_enabled(vkds
) || zfunc_is_ordered
;
1116 order_invariance
[1].pass_set
=
1117 nozwrite_and_order_invariant_stencil
||
1118 (!radv_is_stencil_write_enabled(vkds
) &&
1119 (vkds
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
||
1120 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
));
1121 order_invariance
[0].pass_set
=
1122 !radv_is_depth_write_enabled(vkds
) ||
1123 (vkds
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
||
1124 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
);
1126 dsa_order_invariant
= order_invariance
[has_stencil
];
1127 if (!dsa_order_invariant
.zs
)
1130 /* The set of PS invocations is always order invariant,
1131 * except when early Z/S tests are requested.
1134 ps
->info
.ps
.writes_memory
&&
1135 ps
->info
.ps
.early_fragment_test
&&
1136 !dsa_order_invariant
.pass_set
)
1139 /* Determine if out-of-order rasterization should be disabled
1140 * when occlusion queries are used.
1142 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
=
1143 !dsa_order_invariant
.pass_set
;
1146 /* No color buffers are enabled for writing. */
1150 unsigned blendmask
= colormask
& blend
->blend_enable_4bit
;
1153 /* Only commutative blending. */
1154 if (blendmask
& ~blend
->commutative_4bit
)
1157 if (!dsa_order_invariant
.pass_set
)
1161 if (colormask
& ~blendmask
)
1168 radv_pipeline_init_multisample_state(struct radv_pipeline
*pipeline
,
1169 struct radv_blend_state
*blend
,
1170 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1172 const VkPipelineMultisampleStateCreateInfo
*vkms
= radv_pipeline_get_multisample_state(pCreateInfo
);
1173 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
1174 unsigned num_tile_pipes
= pipeline
->device
->physical_device
->rad_info
.num_tile_pipes
;
1175 bool out_of_order_rast
= false;
1176 int ps_iter_samples
= 1;
1177 uint32_t mask
= 0xffff;
1180 ms
->num_samples
= vkms
->rasterizationSamples
;
1182 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
1184 * "Sample shading is enabled for a graphics pipeline:
1186 * - If the interface of the fragment shader entry point of the
1187 * graphics pipeline includes an input variable decorated
1188 * with SampleId or SamplePosition. In this case
1189 * minSampleShadingFactor takes the value 1.0.
1190 * - Else if the sampleShadingEnable member of the
1191 * VkPipelineMultisampleStateCreateInfo structure specified
1192 * when creating the graphics pipeline is set to VK_TRUE. In
1193 * this case minSampleShadingFactor takes the value of
1194 * VkPipelineMultisampleStateCreateInfo::minSampleShading.
1196 * Otherwise, sample shading is considered disabled."
1198 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.force_persample
) {
1199 ps_iter_samples
= ms
->num_samples
;
1201 ps_iter_samples
= radv_pipeline_get_ps_iter_samples(pCreateInfo
);
1204 ms
->num_samples
= 1;
1207 const struct VkPipelineRasterizationStateRasterizationOrderAMD
*raster_order
=
1208 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD
);
1209 if (raster_order
&& raster_order
->rasterizationOrder
== VK_RASTERIZATION_ORDER_RELAXED_AMD
) {
1210 /* Out-of-order rasterization is explicitly enabled by the
1213 out_of_order_rast
= true;
1215 /* Determine if the driver can enable out-of-order
1216 * rasterization internally.
1219 radv_pipeline_out_of_order_rast(pipeline
, blend
, pCreateInfo
);
1222 ms
->pa_sc_line_cntl
= S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1223 ms
->pa_sc_aa_config
= 0;
1224 ms
->db_eqaa
= S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1225 S_028804_INCOHERENT_EQAA_READS(1) |
1226 S_028804_INTERPOLATE_COMP_Z(1) |
1227 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1228 ms
->pa_sc_mode_cntl_1
=
1229 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1230 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
1231 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast
) |
1232 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1234 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1235 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1236 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1237 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1238 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1239 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1240 ms
->pa_sc_mode_cntl_0
= S_028A48_ALTERNATE_RBS_PER_TILE(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
1241 S_028A48_VPORT_SCISSOR_ENABLE(1);
1243 const VkPipelineRasterizationLineStateCreateInfoEXT
*rast_line
=
1244 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1245 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
);
1247 ms
->pa_sc_mode_cntl_0
|= S_028A48_LINE_STIPPLE_ENABLE(rast_line
->stippledLineEnable
);
1248 if (rast_line
->lineRasterizationMode
== VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT
) {
1249 /* From the Vulkan spec 1.1.129:
1251 * "When VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT lines
1252 * are being rasterized, sample locations may all be
1253 * treated as being at the pixel center (this may
1254 * affect attribute and depth interpolation)."
1256 ms
->num_samples
= 1;
1260 if (ms
->num_samples
> 1) {
1261 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1262 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
1263 uint32_t z_samples
= subpass
->depth_stencil_attachment
? subpass
->depth_sample_count
: ms
->num_samples
;
1264 unsigned log_samples
= util_logbase2(ms
->num_samples
);
1265 unsigned log_z_samples
= util_logbase2(z_samples
);
1266 unsigned log_ps_iter_samples
= util_logbase2(ps_iter_samples
);
1267 ms
->pa_sc_mode_cntl_0
|= S_028A48_MSAA_ENABLE(1);
1268 ms
->pa_sc_line_cntl
|= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1269 ms
->db_eqaa
|= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples
) |
1270 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples
) |
1271 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
1272 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
);
1273 ms
->pa_sc_aa_config
|= S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
1274 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples
)) |
1275 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1276 ms
->pa_sc_mode_cntl_1
|= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1);
1277 if (ps_iter_samples
> 1)
1278 pipeline
->graphics
.spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
1281 if (vkms
&& vkms
->pSampleMask
) {
1282 mask
= vkms
->pSampleMask
[0] & 0xffff;
1285 ms
->pa_sc_aa_mask
[0] = mask
| (mask
<< 16);
1286 ms
->pa_sc_aa_mask
[1] = mask
| (mask
<< 16);
1290 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology
)
1293 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1294 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1295 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1296 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1297 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1299 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1300 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1301 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1302 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1303 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1304 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1307 unreachable("unhandled primitive type");
1312 si_translate_prim(enum VkPrimitiveTopology topology
)
1315 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1316 return V_008958_DI_PT_POINTLIST
;
1317 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1318 return V_008958_DI_PT_LINELIST
;
1319 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1320 return V_008958_DI_PT_LINESTRIP
;
1321 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1322 return V_008958_DI_PT_TRILIST
;
1323 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1324 return V_008958_DI_PT_TRISTRIP
;
1325 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1326 return V_008958_DI_PT_TRIFAN
;
1327 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1328 return V_008958_DI_PT_LINELIST_ADJ
;
1329 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1330 return V_008958_DI_PT_LINESTRIP_ADJ
;
1331 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1332 return V_008958_DI_PT_TRILIST_ADJ
;
1333 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1334 return V_008958_DI_PT_TRISTRIP_ADJ
;
1335 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1336 return V_008958_DI_PT_PATCH
;
1344 si_conv_gl_prim_to_gs_out(unsigned gl_prim
)
1347 case 0: /* GL_POINTS */
1348 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1349 case 1: /* GL_LINES */
1350 case 3: /* GL_LINE_STRIP */
1351 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1352 case 0x8E7A: /* GL_ISOLINES */
1353 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1355 case 4: /* GL_TRIANGLES */
1356 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1357 case 5: /* GL_TRIANGLE_STRIP */
1358 case 7: /* GL_QUADS */
1359 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1367 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology
)
1370 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1371 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1372 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1373 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1374 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1375 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1376 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1377 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1378 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1379 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1380 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1381 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1382 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1383 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1390 static unsigned radv_dynamic_state_mask(VkDynamicState state
)
1393 case VK_DYNAMIC_STATE_VIEWPORT
:
1394 return RADV_DYNAMIC_VIEWPORT
;
1395 case VK_DYNAMIC_STATE_SCISSOR
:
1396 return RADV_DYNAMIC_SCISSOR
;
1397 case VK_DYNAMIC_STATE_LINE_WIDTH
:
1398 return RADV_DYNAMIC_LINE_WIDTH
;
1399 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
1400 return RADV_DYNAMIC_DEPTH_BIAS
;
1401 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
1402 return RADV_DYNAMIC_BLEND_CONSTANTS
;
1403 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
1404 return RADV_DYNAMIC_DEPTH_BOUNDS
;
1405 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
1406 return RADV_DYNAMIC_STENCIL_COMPARE_MASK
;
1407 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
1408 return RADV_DYNAMIC_STENCIL_WRITE_MASK
;
1409 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
1410 return RADV_DYNAMIC_STENCIL_REFERENCE
;
1411 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT
:
1412 return RADV_DYNAMIC_DISCARD_RECTANGLE
;
1413 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT
:
1414 return RADV_DYNAMIC_SAMPLE_LOCATIONS
;
1415 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT
:
1416 return RADV_DYNAMIC_LINE_STIPPLE
;
1418 unreachable("Unhandled dynamic state");
1422 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1424 uint32_t states
= RADV_DYNAMIC_ALL
;
1426 /* If rasterization is disabled we do not care about any of the dynamic states,
1427 * since they are all rasterization related only. */
1428 if (pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
)
1431 if (!pCreateInfo
->pRasterizationState
->depthBiasEnable
)
1432 states
&= ~RADV_DYNAMIC_DEPTH_BIAS
;
1434 if (!pCreateInfo
->pDepthStencilState
||
1435 !pCreateInfo
->pDepthStencilState
->depthBoundsTestEnable
)
1436 states
&= ~RADV_DYNAMIC_DEPTH_BOUNDS
;
1438 if (!pCreateInfo
->pDepthStencilState
||
1439 !pCreateInfo
->pDepthStencilState
->stencilTestEnable
)
1440 states
&= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK
|
1441 RADV_DYNAMIC_STENCIL_WRITE_MASK
|
1442 RADV_DYNAMIC_STENCIL_REFERENCE
);
1444 if (!vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
))
1445 states
&= ~RADV_DYNAMIC_DISCARD_RECTANGLE
;
1447 if (!pCreateInfo
->pMultisampleState
||
1448 !vk_find_struct_const(pCreateInfo
->pMultisampleState
->pNext
,
1449 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
))
1450 states
&= ~RADV_DYNAMIC_SAMPLE_LOCATIONS
;
1452 if (!pCreateInfo
->pRasterizationState
||
1453 !vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1454 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
))
1455 states
&= ~RADV_DYNAMIC_LINE_STIPPLE
;
1457 /* TODO: blend constants & line width. */
1464 radv_pipeline_init_dynamic_state(struct radv_pipeline
*pipeline
,
1465 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1467 uint32_t needed_states
= radv_pipeline_needed_dynamic_state(pCreateInfo
);
1468 uint32_t states
= needed_states
;
1469 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1470 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
1472 pipeline
->dynamic_state
= default_dynamic_state
;
1473 pipeline
->graphics
.needed_dynamic_state
= needed_states
;
1475 if (pCreateInfo
->pDynamicState
) {
1476 /* Remove all of the states that are marked as dynamic */
1477 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1478 for (uint32_t s
= 0; s
< count
; s
++)
1479 states
&= ~radv_dynamic_state_mask(pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1482 struct radv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1484 if (needed_states
& RADV_DYNAMIC_VIEWPORT
) {
1485 assert(pCreateInfo
->pViewportState
);
1487 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1488 if (states
& RADV_DYNAMIC_VIEWPORT
) {
1489 typed_memcpy(dynamic
->viewport
.viewports
,
1490 pCreateInfo
->pViewportState
->pViewports
,
1491 pCreateInfo
->pViewportState
->viewportCount
);
1495 if (needed_states
& RADV_DYNAMIC_SCISSOR
) {
1496 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1497 if (states
& RADV_DYNAMIC_SCISSOR
) {
1498 typed_memcpy(dynamic
->scissor
.scissors
,
1499 pCreateInfo
->pViewportState
->pScissors
,
1500 pCreateInfo
->pViewportState
->scissorCount
);
1504 if (states
& RADV_DYNAMIC_LINE_WIDTH
) {
1505 assert(pCreateInfo
->pRasterizationState
);
1506 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1509 if (states
& RADV_DYNAMIC_DEPTH_BIAS
) {
1510 assert(pCreateInfo
->pRasterizationState
);
1511 dynamic
->depth_bias
.bias
=
1512 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1513 dynamic
->depth_bias
.clamp
=
1514 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1515 dynamic
->depth_bias
.slope
=
1516 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1519 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1521 * pColorBlendState is [...] NULL if the pipeline has rasterization
1522 * disabled or if the subpass of the render pass the pipeline is
1523 * created against does not use any color attachments.
1525 if (subpass
->has_color_att
&& states
& RADV_DYNAMIC_BLEND_CONSTANTS
) {
1526 assert(pCreateInfo
->pColorBlendState
);
1527 typed_memcpy(dynamic
->blend_constants
,
1528 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1531 /* If there is no depthstencil attachment, then don't read
1532 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1533 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1534 * no need to override the depthstencil defaults in
1535 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1537 * Section 9.2 of the Vulkan 1.0.15 spec says:
1539 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1540 * disabled or if the subpass of the render pass the pipeline is created
1541 * against does not use a depth/stencil attachment.
1543 if (needed_states
&& subpass
->depth_stencil_attachment
) {
1544 assert(pCreateInfo
->pDepthStencilState
);
1546 if (states
& RADV_DYNAMIC_DEPTH_BOUNDS
) {
1547 dynamic
->depth_bounds
.min
=
1548 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1549 dynamic
->depth_bounds
.max
=
1550 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1553 if (states
& RADV_DYNAMIC_STENCIL_COMPARE_MASK
) {
1554 dynamic
->stencil_compare_mask
.front
=
1555 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1556 dynamic
->stencil_compare_mask
.back
=
1557 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1560 if (states
& RADV_DYNAMIC_STENCIL_WRITE_MASK
) {
1561 dynamic
->stencil_write_mask
.front
=
1562 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1563 dynamic
->stencil_write_mask
.back
=
1564 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1567 if (states
& RADV_DYNAMIC_STENCIL_REFERENCE
) {
1568 dynamic
->stencil_reference
.front
=
1569 pCreateInfo
->pDepthStencilState
->front
.reference
;
1570 dynamic
->stencil_reference
.back
=
1571 pCreateInfo
->pDepthStencilState
->back
.reference
;
1575 const VkPipelineDiscardRectangleStateCreateInfoEXT
*discard_rectangle_info
=
1576 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
);
1577 if (needed_states
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
1578 dynamic
->discard_rectangle
.count
= discard_rectangle_info
->discardRectangleCount
;
1579 if (states
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
1580 typed_memcpy(dynamic
->discard_rectangle
.rectangles
,
1581 discard_rectangle_info
->pDiscardRectangles
,
1582 discard_rectangle_info
->discardRectangleCount
);
1586 if (needed_states
& RADV_DYNAMIC_SAMPLE_LOCATIONS
) {
1587 const VkPipelineSampleLocationsStateCreateInfoEXT
*sample_location_info
=
1588 vk_find_struct_const(pCreateInfo
->pMultisampleState
->pNext
,
1589 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
);
1590 /* If sampleLocationsEnable is VK_FALSE, the default sample
1591 * locations are used and the values specified in
1592 * sampleLocationsInfo are ignored.
1594 if (sample_location_info
->sampleLocationsEnable
) {
1595 const VkSampleLocationsInfoEXT
*pSampleLocationsInfo
=
1596 &sample_location_info
->sampleLocationsInfo
;
1598 assert(pSampleLocationsInfo
->sampleLocationsCount
<= MAX_SAMPLE_LOCATIONS
);
1600 dynamic
->sample_location
.per_pixel
= pSampleLocationsInfo
->sampleLocationsPerPixel
;
1601 dynamic
->sample_location
.grid_size
= pSampleLocationsInfo
->sampleLocationGridSize
;
1602 dynamic
->sample_location
.count
= pSampleLocationsInfo
->sampleLocationsCount
;
1603 typed_memcpy(&dynamic
->sample_location
.locations
[0],
1604 pSampleLocationsInfo
->pSampleLocations
,
1605 pSampleLocationsInfo
->sampleLocationsCount
);
1609 const VkPipelineRasterizationLineStateCreateInfoEXT
*rast_line_info
=
1610 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1611 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
);
1612 if (needed_states
& RADV_DYNAMIC_LINE_STIPPLE
) {
1613 dynamic
->line_stipple
.factor
= rast_line_info
->lineStippleFactor
;
1614 dynamic
->line_stipple
.pattern
= rast_line_info
->lineStipplePattern
;
1617 pipeline
->dynamic_state
.mask
= states
;
1621 gfx9_get_gs_info(const struct radv_pipeline_key
*key
,
1622 const struct radv_pipeline
*pipeline
,
1624 struct radv_shader_info
*infos
,
1625 struct gfx9_gs_info
*out
)
1627 struct radv_shader_info
*gs_info
= &infos
[MESA_SHADER_GEOMETRY
];
1628 struct radv_es_output_info
*es_info
;
1629 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1630 es_info
= nir
[MESA_SHADER_TESS_CTRL
] ? &gs_info
->tes
.es_info
: &gs_info
->vs
.es_info
;
1632 es_info
= nir
[MESA_SHADER_TESS_CTRL
] ?
1633 &infos
[MESA_SHADER_TESS_EVAL
].tes
.es_info
:
1634 &infos
[MESA_SHADER_VERTEX
].vs
.es_info
;
1636 unsigned gs_num_invocations
= MAX2(gs_info
->gs
.invocations
, 1);
1637 bool uses_adjacency
;
1638 switch(key
->topology
) {
1639 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1640 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1641 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1642 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1643 uses_adjacency
= true;
1646 uses_adjacency
= false;
1650 /* All these are in dwords: */
1651 /* We can't allow using the whole LDS, because GS waves compete with
1652 * other shader stages for LDS space. */
1653 const unsigned max_lds_size
= 8 * 1024;
1654 const unsigned esgs_itemsize
= es_info
->esgs_itemsize
/ 4;
1655 unsigned esgs_lds_size
;
1657 /* All these are per subgroup: */
1658 const unsigned max_out_prims
= 32 * 1024;
1659 const unsigned max_es_verts
= 255;
1660 const unsigned ideal_gs_prims
= 64;
1661 unsigned max_gs_prims
, gs_prims
;
1662 unsigned min_es_verts
, es_verts
, worst_case_es_verts
;
1664 if (uses_adjacency
|| gs_num_invocations
> 1)
1665 max_gs_prims
= 127 / gs_num_invocations
;
1669 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1670 * Make sure we don't go over the maximum value.
1672 if (gs_info
->gs
.vertices_out
> 0) {
1673 max_gs_prims
= MIN2(max_gs_prims
,
1675 (gs_info
->gs
.vertices_out
* gs_num_invocations
));
1677 assert(max_gs_prims
> 0);
1679 /* If the primitive has adjacency, halve the number of vertices
1680 * that will be reused in multiple primitives.
1682 min_es_verts
= gs_info
->gs
.vertices_in
/ (uses_adjacency
? 2 : 1);
1684 gs_prims
= MIN2(ideal_gs_prims
, max_gs_prims
);
1685 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
, max_es_verts
);
1687 /* Compute ESGS LDS size based on the worst case number of ES vertices
1688 * needed to create the target number of GS prims per subgroup.
1690 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
1692 /* If total LDS usage is too big, refactor partitions based on ratio
1693 * of ESGS item sizes.
1695 if (esgs_lds_size
> max_lds_size
) {
1696 /* Our target GS Prims Per Subgroup was too large. Calculate
1697 * the maximum number of GS Prims Per Subgroup that will fit
1698 * into LDS, capped by the maximum that the hardware can support.
1700 gs_prims
= MIN2((max_lds_size
/ (esgs_itemsize
* min_es_verts
)),
1702 assert(gs_prims
> 0);
1703 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
,
1706 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
1707 assert(esgs_lds_size
<= max_lds_size
);
1710 /* Now calculate remaining ESGS information. */
1712 es_verts
= MIN2(esgs_lds_size
/ esgs_itemsize
, max_es_verts
);
1714 es_verts
= max_es_verts
;
1716 /* Vertices for adjacency primitives are not always reused, so restore
1717 * it for ES_VERTS_PER_SUBGRP.
1719 min_es_verts
= gs_info
->gs
.vertices_in
;
1721 /* For normal primitives, the VGT only checks if they are past the ES
1722 * verts per subgroup after allocating a full GS primitive and if they
1723 * are, kick off a new subgroup. But if those additional ES verts are
1724 * unique (e.g. not reused) we need to make sure there is enough LDS
1725 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1727 es_verts
-= min_es_verts
- 1;
1729 uint32_t es_verts_per_subgroup
= es_verts
;
1730 uint32_t gs_prims_per_subgroup
= gs_prims
;
1731 uint32_t gs_inst_prims_in_subgroup
= gs_prims
* gs_num_invocations
;
1732 uint32_t max_prims_per_subgroup
= gs_inst_prims_in_subgroup
* gs_info
->gs
.vertices_out
;
1733 out
->lds_size
= align(esgs_lds_size
, 128) / 128;
1734 out
->vgt_gs_onchip_cntl
= S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup
) |
1735 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup
) |
1736 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup
);
1737 out
->vgt_gs_max_prims_per_subgroup
= S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup
);
1738 out
->vgt_esgs_ring_itemsize
= esgs_itemsize
;
1739 assert(max_prims_per_subgroup
<= max_out_prims
);
1742 static void clamp_gsprims_to_esverts(unsigned *max_gsprims
, unsigned max_esverts
,
1743 unsigned min_verts_per_prim
, bool use_adjacency
)
1745 unsigned max_reuse
= max_esverts
- min_verts_per_prim
;
1748 *max_gsprims
= MIN2(*max_gsprims
, 1 + max_reuse
);
1752 radv_get_num_input_vertices(nir_shader
**nir
)
1754 if (nir
[MESA_SHADER_GEOMETRY
]) {
1755 nir_shader
*gs
= nir
[MESA_SHADER_GEOMETRY
];
1757 return gs
->info
.gs
.vertices_in
;
1760 if (nir
[MESA_SHADER_TESS_CTRL
]) {
1761 nir_shader
*tes
= nir
[MESA_SHADER_TESS_EVAL
];
1763 if (tes
->info
.tess
.point_mode
)
1765 if (tes
->info
.tess
.primitive_mode
== GL_ISOLINES
)
1774 gfx10_get_ngg_info(const struct radv_pipeline_key
*key
,
1775 struct radv_pipeline
*pipeline
,
1777 struct radv_shader_info
*infos
,
1778 struct gfx10_ngg_info
*ngg
)
1780 struct radv_shader_info
*gs_info
= &infos
[MESA_SHADER_GEOMETRY
];
1781 struct radv_es_output_info
*es_info
=
1782 nir
[MESA_SHADER_TESS_CTRL
] ? &gs_info
->tes
.es_info
: &gs_info
->vs
.es_info
;
1783 unsigned gs_type
= nir
[MESA_SHADER_GEOMETRY
] ? MESA_SHADER_GEOMETRY
: MESA_SHADER_VERTEX
;
1784 unsigned max_verts_per_prim
= radv_get_num_input_vertices(nir
);
1785 unsigned min_verts_per_prim
=
1786 gs_type
== MESA_SHADER_GEOMETRY
? max_verts_per_prim
: 1;
1787 unsigned gs_num_invocations
= nir
[MESA_SHADER_GEOMETRY
] ? MAX2(gs_info
->gs
.invocations
, 1) : 1;
1788 bool uses_adjacency
;
1789 switch(key
->topology
) {
1790 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1791 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1792 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1793 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1794 uses_adjacency
= true;
1797 uses_adjacency
= false;
1801 /* All these are in dwords: */
1802 /* We can't allow using the whole LDS, because GS waves compete with
1803 * other shader stages for LDS space.
1805 * TODO: We should really take the shader's internal LDS use into
1806 * account. The linker will fail if the size is greater than
1809 const unsigned max_lds_size
= 8 * 1024 - 768;
1810 const unsigned target_lds_size
= max_lds_size
;
1811 unsigned esvert_lds_size
= 0;
1812 unsigned gsprim_lds_size
= 0;
1814 /* All these are per subgroup: */
1815 bool max_vert_out_per_gs_instance
= false;
1816 unsigned max_esverts_base
= 256;
1817 unsigned max_gsprims_base
= 128; /* default prim group size clamp */
1819 /* Hardware has the following non-natural restrictions on the value
1820 * of GE_CNTL.VERT_GRP_SIZE based on based on the primitive type of
1822 * - at most 252 for any line input primitive type
1823 * - at most 251 for any quad input primitive type
1824 * - at most 251 for triangle strips with adjacency (this happens to
1825 * be the natural limit for triangle *lists* with adjacency)
1827 max_esverts_base
= MIN2(max_esverts_base
, 251 + max_verts_per_prim
- 1);
1829 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1830 unsigned max_out_verts_per_gsprim
=
1831 gs_info
->gs
.vertices_out
* gs_num_invocations
;
1833 if (max_out_verts_per_gsprim
<= 256) {
1834 if (max_out_verts_per_gsprim
) {
1835 max_gsprims_base
= MIN2(max_gsprims_base
,
1836 256 / max_out_verts_per_gsprim
);
1839 /* Use special multi-cycling mode in which each GS
1840 * instance gets its own subgroup. Does not work with
1842 max_vert_out_per_gs_instance
= true;
1843 max_gsprims_base
= 1;
1844 max_out_verts_per_gsprim
= gs_info
->gs
.vertices_out
;
1847 esvert_lds_size
= es_info
->esgs_itemsize
/ 4;
1848 gsprim_lds_size
= (gs_info
->gs
.gsvs_vertex_size
/ 4 + 1) * max_out_verts_per_gsprim
;
1851 /* LDS size for passing data from GS to ES. */
1852 struct radv_streamout_info
*so_info
= nir
[MESA_SHADER_TESS_CTRL
]
1853 ? &infos
[MESA_SHADER_TESS_EVAL
].so
1854 : &infos
[MESA_SHADER_VERTEX
].so
;
1856 if (so_info
->num_outputs
)
1857 esvert_lds_size
= 4 * so_info
->num_outputs
+ 1;
1859 /* GS stores Primitive IDs (one DWORD) into LDS at the address
1860 * corresponding to the ES thread of the provoking vertex. All
1861 * ES threads load and export PrimitiveID for their thread.
1863 if (!nir
[MESA_SHADER_TESS_CTRL
] &&
1864 infos
[MESA_SHADER_VERTEX
].vs
.outinfo
.export_prim_id
)
1865 esvert_lds_size
= MAX2(esvert_lds_size
, 1);
1868 unsigned max_gsprims
= max_gsprims_base
;
1869 unsigned max_esverts
= max_esverts_base
;
1871 if (esvert_lds_size
)
1872 max_esverts
= MIN2(max_esverts
, target_lds_size
/ esvert_lds_size
);
1873 if (gsprim_lds_size
)
1874 max_gsprims
= MIN2(max_gsprims
, target_lds_size
/ gsprim_lds_size
);
1876 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1877 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
, min_verts_per_prim
, uses_adjacency
);
1878 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1880 if (esvert_lds_size
|| gsprim_lds_size
) {
1881 /* Now that we have a rough proportionality between esverts
1882 * and gsprims based on the primitive type, scale both of them
1883 * down simultaneously based on required LDS space.
1885 * We could be smarter about this if we knew how much vertex
1888 unsigned lds_total
= max_esverts
* esvert_lds_size
+
1889 max_gsprims
* gsprim_lds_size
;
1890 if (lds_total
> target_lds_size
) {
1891 max_esverts
= max_esverts
* target_lds_size
/ lds_total
;
1892 max_gsprims
= max_gsprims
* target_lds_size
/ lds_total
;
1894 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1895 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
,
1896 min_verts_per_prim
, uses_adjacency
);
1897 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1901 /* Round up towards full wave sizes for better ALU utilization. */
1902 if (!max_vert_out_per_gs_instance
) {
1903 unsigned orig_max_esverts
;
1904 unsigned orig_max_gsprims
;
1907 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1908 wavesize
= gs_info
->wave_size
;
1910 wavesize
= nir
[MESA_SHADER_TESS_CTRL
]
1911 ? infos
[MESA_SHADER_TESS_EVAL
].wave_size
1912 : infos
[MESA_SHADER_VERTEX
].wave_size
;
1916 orig_max_esverts
= max_esverts
;
1917 orig_max_gsprims
= max_gsprims
;
1919 max_esverts
= align(max_esverts
, wavesize
);
1920 max_esverts
= MIN2(max_esverts
, max_esverts_base
);
1921 if (esvert_lds_size
)
1922 max_esverts
= MIN2(max_esverts
,
1923 (max_lds_size
- max_gsprims
* gsprim_lds_size
) /
1925 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1927 max_gsprims
= align(max_gsprims
, wavesize
);
1928 max_gsprims
= MIN2(max_gsprims
, max_gsprims_base
);
1929 if (gsprim_lds_size
)
1930 max_gsprims
= MIN2(max_gsprims
,
1931 (max_lds_size
- max_esverts
* esvert_lds_size
) /
1933 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
,
1934 min_verts_per_prim
, uses_adjacency
);
1935 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1936 } while (orig_max_esverts
!= max_esverts
|| orig_max_gsprims
!= max_gsprims
);
1939 /* Hardware restriction: minimum value of max_esverts */
1940 max_esverts
= MAX2(max_esverts
, 23 + max_verts_per_prim
);
1942 unsigned max_out_vertices
=
1943 max_vert_out_per_gs_instance
? gs_info
->gs
.vertices_out
:
1944 gs_type
== MESA_SHADER_GEOMETRY
?
1945 max_gsprims
* gs_num_invocations
* gs_info
->gs
.vertices_out
:
1947 assert(max_out_vertices
<= 256);
1949 unsigned prim_amp_factor
= 1;
1950 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1951 /* Number of output primitives per GS input primitive after
1953 prim_amp_factor
= gs_info
->gs
.vertices_out
;
1956 /* The GE only checks against the maximum number of ES verts after
1957 * allocating a full GS primitive. So we need to ensure that whenever
1958 * this check passes, there is enough space for a full primitive without
1961 ngg
->hw_max_esverts
= max_esverts
- max_verts_per_prim
+ 1;
1962 ngg
->max_gsprims
= max_gsprims
;
1963 ngg
->max_out_verts
= max_out_vertices
;
1964 ngg
->prim_amp_factor
= prim_amp_factor
;
1965 ngg
->max_vert_out_per_gs_instance
= max_vert_out_per_gs_instance
;
1966 ngg
->ngg_emit_size
= max_gsprims
* gsprim_lds_size
;
1967 ngg
->esgs_ring_size
= 4 * max_esverts
* esvert_lds_size
;
1969 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1970 ngg
->vgt_esgs_ring_itemsize
= es_info
->esgs_itemsize
/ 4;
1972 ngg
->vgt_esgs_ring_itemsize
= 1;
1975 pipeline
->graphics
.esgs_ring_size
= ngg
->esgs_ring_size
;
1977 assert(ngg
->hw_max_esverts
>= 24); /* HW limitation */
1981 calculate_gs_ring_sizes(struct radv_pipeline
*pipeline
,
1982 const struct gfx9_gs_info
*gs
)
1984 struct radv_device
*device
= pipeline
->device
;
1985 unsigned num_se
= device
->physical_device
->rad_info
.max_se
;
1986 unsigned wave_size
= 64;
1987 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
1988 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
1989 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
1991 unsigned gs_vertex_reuse
=
1992 (device
->physical_device
->rad_info
.chip_class
>= GFX8
? 32 : 16) * num_se
;
1993 unsigned alignment
= 256 * num_se
;
1994 /* The maximum size is 63.999 MB per SE. */
1995 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
1996 struct radv_shader_info
*gs_info
= &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
;
1998 /* Calculate the minimum size. */
1999 unsigned min_esgs_ring_size
= align(gs
->vgt_esgs_ring_itemsize
* 4 * gs_vertex_reuse
*
2000 wave_size
, alignment
);
2001 /* These are recommended sizes, not minimum sizes. */
2002 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
2003 gs
->vgt_esgs_ring_itemsize
* 4 * gs_info
->gs
.vertices_in
;
2004 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
2005 gs_info
->gs
.max_gsvs_emit_size
;
2007 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
2008 esgs_ring_size
= align(esgs_ring_size
, alignment
);
2009 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
2011 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
)
2012 pipeline
->graphics
.esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
2014 pipeline
->graphics
.gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
2017 static void si_multiwave_lds_size_workaround(struct radv_device
*device
,
2020 /* If tessellation is all offchip and on-chip GS isn't used, this
2021 * workaround is not needed.
2025 /* SPI barrier management bug:
2026 * Make sure we have at least 4k of LDS in use to avoid the bug.
2027 * It applies to workgroup sizes of more than one wavefront.
2029 if (device
->physical_device
->rad_info
.family
== CHIP_BONAIRE
||
2030 device
->physical_device
->rad_info
.family
== CHIP_KABINI
)
2031 *lds_size
= MAX2(*lds_size
, 8);
2034 struct radv_shader_variant
*
2035 radv_get_shader(struct radv_pipeline
*pipeline
,
2036 gl_shader_stage stage
)
2038 if (stage
== MESA_SHADER_VERTEX
) {
2039 if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
2040 return pipeline
->shaders
[MESA_SHADER_VERTEX
];
2041 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
])
2042 return pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
2043 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
2044 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
2045 } else if (stage
== MESA_SHADER_TESS_EVAL
) {
2046 if (!radv_pipeline_has_tess(pipeline
))
2048 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
2049 return pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
2050 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
2051 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
2053 return pipeline
->shaders
[stage
];
2056 static struct radv_tessellation_state
2057 calculate_tess_state(struct radv_pipeline
*pipeline
,
2058 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
2060 unsigned num_tcs_input_cp
;
2061 unsigned num_tcs_output_cp
;
2063 unsigned num_patches
;
2064 struct radv_tessellation_state tess
= {0};
2066 num_tcs_input_cp
= pCreateInfo
->pTessellationState
->patchControlPoints
;
2067 num_tcs_output_cp
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.tcs_vertices_out
; //TCS VERTICES OUT
2068 num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2070 lds_size
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.lds_size
;
2072 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2073 assert(lds_size
<= 65536);
2074 lds_size
= align(lds_size
, 512) / 512;
2076 assert(lds_size
<= 32768);
2077 lds_size
= align(lds_size
, 256) / 256;
2079 si_multiwave_lds_size_workaround(pipeline
->device
, &lds_size
);
2081 tess
.lds_size
= lds_size
;
2083 tess
.ls_hs_config
= S_028B58_NUM_PATCHES(num_patches
) |
2084 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp
) |
2085 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp
);
2086 tess
.num_patches
= num_patches
;
2088 struct radv_shader_variant
*tes
= radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
);
2089 unsigned type
= 0, partitioning
= 0, topology
= 0, distribution_mode
= 0;
2091 switch (tes
->info
.tes
.primitive_mode
) {
2093 type
= V_028B6C_TESS_TRIANGLE
;
2096 type
= V_028B6C_TESS_QUAD
;
2099 type
= V_028B6C_TESS_ISOLINE
;
2103 switch (tes
->info
.tes
.spacing
) {
2104 case TESS_SPACING_EQUAL
:
2105 partitioning
= V_028B6C_PART_INTEGER
;
2107 case TESS_SPACING_FRACTIONAL_ODD
:
2108 partitioning
= V_028B6C_PART_FRAC_ODD
;
2110 case TESS_SPACING_FRACTIONAL_EVEN
:
2111 partitioning
= V_028B6C_PART_FRAC_EVEN
;
2117 bool ccw
= tes
->info
.tes
.ccw
;
2118 const VkPipelineTessellationDomainOriginStateCreateInfo
*domain_origin_state
=
2119 vk_find_struct_const(pCreateInfo
->pTessellationState
,
2120 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO
);
2122 if (domain_origin_state
&& domain_origin_state
->domainOrigin
!= VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT
)
2125 if (tes
->info
.tes
.point_mode
)
2126 topology
= V_028B6C_OUTPUT_POINT
;
2127 else if (tes
->info
.tes
.primitive_mode
== GL_ISOLINES
)
2128 topology
= V_028B6C_OUTPUT_LINE
;
2130 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
2132 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
2134 if (pipeline
->device
->physical_device
->rad_info
.has_distributed_tess
) {
2135 if (pipeline
->device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
2136 pipeline
->device
->physical_device
->rad_info
.family
>= CHIP_POLARIS10
)
2137 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
2139 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
2141 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
2143 tess
.tf_param
= S_028B6C_TYPE(type
) |
2144 S_028B6C_PARTITIONING(partitioning
) |
2145 S_028B6C_TOPOLOGY(topology
) |
2146 S_028B6C_DISTRIBUTION_MODE(distribution_mode
);
2151 static const struct radv_prim_vertex_count prim_size_table
[] = {
2152 [V_008958_DI_PT_NONE
] = {0, 0},
2153 [V_008958_DI_PT_POINTLIST
] = {1, 1},
2154 [V_008958_DI_PT_LINELIST
] = {2, 2},
2155 [V_008958_DI_PT_LINESTRIP
] = {2, 1},
2156 [V_008958_DI_PT_TRILIST
] = {3, 3},
2157 [V_008958_DI_PT_TRIFAN
] = {3, 1},
2158 [V_008958_DI_PT_TRISTRIP
] = {3, 1},
2159 [V_008958_DI_PT_LINELIST_ADJ
] = {4, 4},
2160 [V_008958_DI_PT_LINESTRIP_ADJ
] = {4, 1},
2161 [V_008958_DI_PT_TRILIST_ADJ
] = {6, 6},
2162 [V_008958_DI_PT_TRISTRIP_ADJ
] = {6, 2},
2163 [V_008958_DI_PT_RECTLIST
] = {3, 3},
2164 [V_008958_DI_PT_LINELOOP
] = {2, 1},
2165 [V_008958_DI_PT_POLYGON
] = {3, 1},
2166 [V_008958_DI_PT_2D_TRI_STRIP
] = {0, 0},
2169 static const struct radv_vs_output_info
*get_vs_output_info(const struct radv_pipeline
*pipeline
)
2171 if (radv_pipeline_has_gs(pipeline
))
2172 if (radv_pipeline_has_ngg(pipeline
))
2173 return &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.vs
.outinfo
;
2175 return &pipeline
->gs_copy_shader
->info
.vs
.outinfo
;
2176 else if (radv_pipeline_has_tess(pipeline
))
2177 return &pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.outinfo
;
2179 return &pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.outinfo
;
2183 radv_link_shaders(struct radv_pipeline
*pipeline
, nir_shader
**shaders
)
2185 nir_shader
* ordered_shaders
[MESA_SHADER_STAGES
];
2186 int shader_count
= 0;
2188 if(shaders
[MESA_SHADER_FRAGMENT
]) {
2189 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_FRAGMENT
];
2191 if(shaders
[MESA_SHADER_GEOMETRY
]) {
2192 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_GEOMETRY
];
2194 if(shaders
[MESA_SHADER_TESS_EVAL
]) {
2195 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_EVAL
];
2197 if(shaders
[MESA_SHADER_TESS_CTRL
]) {
2198 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_CTRL
];
2200 if(shaders
[MESA_SHADER_VERTEX
]) {
2201 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_VERTEX
];
2204 if (shader_count
> 1) {
2205 unsigned first
= ordered_shaders
[shader_count
- 1]->info
.stage
;
2206 unsigned last
= ordered_shaders
[0]->info
.stage
;
2208 if (ordered_shaders
[0]->info
.stage
== MESA_SHADER_FRAGMENT
&&
2209 ordered_shaders
[1]->info
.has_transform_feedback_varyings
)
2210 nir_link_xfb_varyings(ordered_shaders
[1], ordered_shaders
[0]);
2212 for (int i
= 0; i
< shader_count
; ++i
) {
2213 nir_variable_mode mask
= 0;
2215 if (ordered_shaders
[i
]->info
.stage
!= first
)
2216 mask
= mask
| nir_var_shader_in
;
2218 if (ordered_shaders
[i
]->info
.stage
!= last
)
2219 mask
= mask
| nir_var_shader_out
;
2221 nir_lower_io_to_scalar_early(ordered_shaders
[i
], mask
);
2222 radv_optimize_nir(ordered_shaders
[i
], false, false);
2226 for (int i
= 1; i
< shader_count
; ++i
) {
2227 nir_lower_io_arrays_to_elements(ordered_shaders
[i
],
2228 ordered_shaders
[i
- 1]);
2230 if (nir_link_opt_varyings(ordered_shaders
[i
],
2231 ordered_shaders
[i
- 1]))
2232 radv_optimize_nir(ordered_shaders
[i
- 1], false, false);
2234 nir_remove_dead_variables(ordered_shaders
[i
],
2235 nir_var_shader_out
);
2236 nir_remove_dead_variables(ordered_shaders
[i
- 1],
2239 bool progress
= nir_remove_unused_varyings(ordered_shaders
[i
],
2240 ordered_shaders
[i
- 1]);
2242 nir_compact_varyings(ordered_shaders
[i
],
2243 ordered_shaders
[i
- 1], true);
2246 if (nir_lower_global_vars_to_local(ordered_shaders
[i
])) {
2247 ac_lower_indirect_derefs(ordered_shaders
[i
],
2248 pipeline
->device
->physical_device
->rad_info
.chip_class
);
2250 radv_optimize_nir(ordered_shaders
[i
], false, false);
2252 if (nir_lower_global_vars_to_local(ordered_shaders
[i
- 1])) {
2253 ac_lower_indirect_derefs(ordered_shaders
[i
- 1],
2254 pipeline
->device
->physical_device
->rad_info
.chip_class
);
2256 radv_optimize_nir(ordered_shaders
[i
- 1], false, false);
2262 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo
*input_state
,
2263 uint32_t attrib_binding
)
2265 for (uint32_t i
= 0; i
< input_state
->vertexBindingDescriptionCount
; i
++) {
2266 const VkVertexInputBindingDescription
*input_binding
=
2267 &input_state
->pVertexBindingDescriptions
[i
];
2269 if (input_binding
->binding
== attrib_binding
)
2270 return input_binding
->stride
;
2276 static struct radv_pipeline_key
2277 radv_generate_graphics_pipeline_key(struct radv_pipeline
*pipeline
,
2278 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2279 const struct radv_blend_state
*blend
,
2280 bool has_view_index
)
2282 const VkPipelineVertexInputStateCreateInfo
*input_state
=
2283 pCreateInfo
->pVertexInputState
;
2284 const VkPipelineVertexInputDivisorStateCreateInfoEXT
*divisor_state
=
2285 vk_find_struct_const(input_state
->pNext
, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT
);
2287 struct radv_pipeline_key key
;
2288 memset(&key
, 0, sizeof(key
));
2290 if (pCreateInfo
->flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
)
2291 key
.optimisations_disabled
= 1;
2293 key
.has_multiview_view_index
= has_view_index
;
2295 uint32_t binding_input_rate
= 0;
2296 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
2297 for (unsigned i
= 0; i
< input_state
->vertexBindingDescriptionCount
; ++i
) {
2298 if (input_state
->pVertexBindingDescriptions
[i
].inputRate
) {
2299 unsigned binding
= input_state
->pVertexBindingDescriptions
[i
].binding
;
2300 binding_input_rate
|= 1u << binding
;
2301 instance_rate_divisors
[binding
] = 1;
2304 if (divisor_state
) {
2305 for (unsigned i
= 0; i
< divisor_state
->vertexBindingDivisorCount
; ++i
) {
2306 instance_rate_divisors
[divisor_state
->pVertexBindingDivisors
[i
].binding
] =
2307 divisor_state
->pVertexBindingDivisors
[i
].divisor
;
2311 for (unsigned i
= 0; i
< input_state
->vertexAttributeDescriptionCount
; ++i
) {
2312 const VkVertexInputAttributeDescription
*desc
=
2313 &input_state
->pVertexAttributeDescriptions
[i
];
2314 const struct vk_format_description
*format_desc
;
2315 unsigned location
= desc
->location
;
2316 unsigned binding
= desc
->binding
;
2317 unsigned num_format
, data_format
;
2320 if (binding_input_rate
& (1u << binding
)) {
2321 key
.instance_rate_inputs
|= 1u << location
;
2322 key
.instance_rate_divisors
[location
] = instance_rate_divisors
[binding
];
2325 format_desc
= vk_format_description(desc
->format
);
2326 first_non_void
= vk_format_get_first_non_void_channel(desc
->format
);
2328 num_format
= radv_translate_buffer_numformat(format_desc
, first_non_void
);
2329 data_format
= radv_translate_buffer_dataformat(format_desc
, first_non_void
);
2331 key
.vertex_attribute_formats
[location
] = data_format
| (num_format
<< 4);
2332 key
.vertex_attribute_bindings
[location
] = desc
->binding
;
2333 key
.vertex_attribute_offsets
[location
] = desc
->offset
;
2334 key
.vertex_attribute_strides
[location
] = radv_get_attrib_stride(input_state
, desc
->binding
);
2336 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
&&
2337 pipeline
->device
->physical_device
->rad_info
.family
!= CHIP_STONEY
) {
2338 VkFormat format
= input_state
->pVertexAttributeDescriptions
[i
].format
;
2341 case VK_FORMAT_A2R10G10B10_SNORM_PACK32
:
2342 case VK_FORMAT_A2B10G10R10_SNORM_PACK32
:
2343 adjust
= RADV_ALPHA_ADJUST_SNORM
;
2345 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32
:
2346 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32
:
2347 adjust
= RADV_ALPHA_ADJUST_SSCALED
;
2349 case VK_FORMAT_A2R10G10B10_SINT_PACK32
:
2350 case VK_FORMAT_A2B10G10R10_SINT_PACK32
:
2351 adjust
= RADV_ALPHA_ADJUST_SINT
;
2357 key
.vertex_alpha_adjust
|= adjust
<< (2 * location
);
2360 switch (desc
->format
) {
2361 case VK_FORMAT_B8G8R8A8_UNORM
:
2362 case VK_FORMAT_B8G8R8A8_SNORM
:
2363 case VK_FORMAT_B8G8R8A8_USCALED
:
2364 case VK_FORMAT_B8G8R8A8_SSCALED
:
2365 case VK_FORMAT_B8G8R8A8_UINT
:
2366 case VK_FORMAT_B8G8R8A8_SINT
:
2367 case VK_FORMAT_B8G8R8A8_SRGB
:
2368 case VK_FORMAT_A2R10G10B10_UNORM_PACK32
:
2369 case VK_FORMAT_A2R10G10B10_SNORM_PACK32
:
2370 case VK_FORMAT_A2R10G10B10_USCALED_PACK32
:
2371 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32
:
2372 case VK_FORMAT_A2R10G10B10_UINT_PACK32
:
2373 case VK_FORMAT_A2R10G10B10_SINT_PACK32
:
2374 key
.vertex_post_shuffle
|= 1 << location
;
2381 const VkPipelineTessellationStateCreateInfo
*tess
=
2382 radv_pipeline_get_tessellation_state(pCreateInfo
);
2384 key
.tess_input_vertices
= tess
->patchControlPoints
;
2386 const VkPipelineMultisampleStateCreateInfo
*vkms
=
2387 radv_pipeline_get_multisample_state(pCreateInfo
);
2388 if (vkms
&& vkms
->rasterizationSamples
> 1) {
2389 uint32_t num_samples
= vkms
->rasterizationSamples
;
2390 uint32_t ps_iter_samples
= radv_pipeline_get_ps_iter_samples(pCreateInfo
);
2391 key
.num_samples
= num_samples
;
2392 key
.log2_ps_iter_samples
= util_logbase2(ps_iter_samples
);
2395 key
.col_format
= blend
->spi_shader_col_format
;
2396 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX8
)
2397 radv_pipeline_compute_get_int_clamp(pCreateInfo
, &key
.is_int8
, &key
.is_int10
);
2399 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
)
2400 key
.topology
= pCreateInfo
->pInputAssemblyState
->topology
;
2406 radv_nir_stage_uses_xfb(const nir_shader
*nir
)
2408 nir_xfb_info
*xfb
= nir_gather_xfb_info(nir
, NULL
);
2409 bool uses_xfb
= !!xfb
;
2416 radv_fill_shader_keys(struct radv_device
*device
,
2417 struct radv_shader_variant_key
*keys
,
2418 const struct radv_pipeline_key
*key
,
2421 keys
[MESA_SHADER_VERTEX
].vs
.instance_rate_inputs
= key
->instance_rate_inputs
;
2422 keys
[MESA_SHADER_VERTEX
].vs
.alpha_adjust
= key
->vertex_alpha_adjust
;
2423 keys
[MESA_SHADER_VERTEX
].vs
.post_shuffle
= key
->vertex_post_shuffle
;
2424 for (unsigned i
= 0; i
< MAX_VERTEX_ATTRIBS
; ++i
) {
2425 keys
[MESA_SHADER_VERTEX
].vs
.instance_rate_divisors
[i
] = key
->instance_rate_divisors
[i
];
2426 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_formats
[i
] = key
->vertex_attribute_formats
[i
];
2427 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_bindings
[i
] = key
->vertex_attribute_bindings
[i
];
2428 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_offsets
[i
] = key
->vertex_attribute_offsets
[i
];
2429 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_strides
[i
] = key
->vertex_attribute_strides
[i
];
2431 keys
[MESA_SHADER_VERTEX
].vs
.outprim
= si_conv_prim_to_gs_out(key
->topology
);
2433 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2434 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ls
= true;
2435 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
= 0;
2436 keys
[MESA_SHADER_TESS_CTRL
].tcs
.input_vertices
= key
->tess_input_vertices
;
2437 keys
[MESA_SHADER_TESS_CTRL
].tcs
.primitive_mode
= nir
[MESA_SHADER_TESS_EVAL
]->info
.tess
.primitive_mode
;
2439 keys
[MESA_SHADER_TESS_CTRL
].tcs
.tes_reads_tess_factors
= !!(nir
[MESA_SHADER_TESS_EVAL
]->info
.inputs_read
& (VARYING_BIT_TESS_LEVEL_INNER
| VARYING_BIT_TESS_LEVEL_OUTER
));
2442 if (nir
[MESA_SHADER_GEOMETRY
]) {
2443 if (nir
[MESA_SHADER_TESS_CTRL
])
2444 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_es
= true;
2446 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_es
= true;
2449 if (device
->physical_device
->use_ngg
) {
2450 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2451 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= true;
2453 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= true;
2456 if (nir
[MESA_SHADER_TESS_CTRL
] &&
2457 nir
[MESA_SHADER_GEOMETRY
] &&
2458 nir
[MESA_SHADER_GEOMETRY
]->info
.gs
.invocations
*
2459 nir
[MESA_SHADER_GEOMETRY
]->info
.gs
.vertices_out
> 256) {
2460 /* Fallback to the legacy path if tessellation is
2461 * enabled with extreme geometry because
2462 * EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it
2465 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2468 gl_shader_stage last_xfb_stage
= MESA_SHADER_VERTEX
;
2470 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
2475 bool uses_xfb
= nir
[last_xfb_stage
] &&
2476 radv_nir_stage_uses_xfb(nir
[last_xfb_stage
]);
2478 if (!device
->physical_device
->use_ngg_streamout
&& uses_xfb
) {
2479 if (nir
[MESA_SHADER_TESS_CTRL
])
2480 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2482 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= false;
2485 /* Determine if the pipeline is eligible for the NGG passthrough
2486 * mode. It can't be enabled for geometry shaders, for NGG
2487 * streamout or for vertex shaders that export the primitive ID
2488 * (this is checked later because we don't have the info here.)
2490 if (!nir
[MESA_SHADER_GEOMETRY
] && !uses_xfb
) {
2491 if (nir
[MESA_SHADER_TESS_CTRL
] &&
2492 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
) {
2493 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg_passthrough
= true;
2494 } else if (nir
[MESA_SHADER_VERTEX
] &&
2495 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
) {
2496 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg_passthrough
= true;
2501 for(int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
2502 keys
[i
].has_multiview_view_index
= key
->has_multiview_view_index
;
2504 keys
[MESA_SHADER_FRAGMENT
].fs
.col_format
= key
->col_format
;
2505 keys
[MESA_SHADER_FRAGMENT
].fs
.is_int8
= key
->is_int8
;
2506 keys
[MESA_SHADER_FRAGMENT
].fs
.is_int10
= key
->is_int10
;
2507 keys
[MESA_SHADER_FRAGMENT
].fs
.log2_ps_iter_samples
= key
->log2_ps_iter_samples
;
2508 keys
[MESA_SHADER_FRAGMENT
].fs
.num_samples
= key
->num_samples
;
2510 if (nir
[MESA_SHADER_COMPUTE
]) {
2511 keys
[MESA_SHADER_COMPUTE
].cs
.subgroup_size
= key
->compute_subgroup_size
;
2516 radv_get_wave_size(struct radv_device
*device
,
2517 const VkPipelineShaderStageCreateInfo
*pStage
,
2518 gl_shader_stage stage
,
2519 const struct radv_shader_variant_key
*key
)
2521 if (stage
== MESA_SHADER_GEOMETRY
&& !key
->vs_common_out
.as_ngg
)
2523 else if (stage
== MESA_SHADER_COMPUTE
) {
2524 if (key
->cs
.subgroup_size
) {
2525 /* Return the required subgroup size if specified. */
2526 return key
->cs
.subgroup_size
;
2528 return device
->physical_device
->cs_wave_size
;
2530 else if (stage
== MESA_SHADER_FRAGMENT
)
2531 return device
->physical_device
->ps_wave_size
;
2533 return device
->physical_device
->ge_wave_size
;
2537 radv_fill_shader_info(struct radv_pipeline
*pipeline
,
2538 const VkPipelineShaderStageCreateInfo
**pStages
,
2539 struct radv_shader_variant_key
*keys
,
2540 struct radv_shader_info
*infos
,
2543 unsigned active_stages
= 0;
2544 unsigned filled_stages
= 0;
2546 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2548 active_stages
|= (1 << i
);
2551 if (nir
[MESA_SHADER_FRAGMENT
]) {
2552 radv_nir_shader_info_init(&infos
[MESA_SHADER_FRAGMENT
]);
2553 radv_nir_shader_info_pass(nir
[MESA_SHADER_FRAGMENT
],
2555 &keys
[MESA_SHADER_FRAGMENT
],
2556 &infos
[MESA_SHADER_FRAGMENT
]);
2558 /* TODO: These are no longer used as keys we should refactor this */
2559 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_prim_id
=
2560 infos
[MESA_SHADER_FRAGMENT
].ps
.prim_id_input
;
2561 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_layer_id
=
2562 infos
[MESA_SHADER_FRAGMENT
].ps
.layer_input
;
2563 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_clip_dists
=
2564 !!infos
[MESA_SHADER_FRAGMENT
].ps
.num_input_clips_culls
;
2565 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_prim_id
=
2566 infos
[MESA_SHADER_FRAGMENT
].ps
.prim_id_input
;
2567 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_layer_id
=
2568 infos
[MESA_SHADER_FRAGMENT
].ps
.layer_input
;
2569 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_clip_dists
=
2570 !!infos
[MESA_SHADER_FRAGMENT
].ps
.num_input_clips_culls
;
2572 /* NGG passthrough mode can't be enabled for vertex shaders
2573 * that export the primitive ID.
2575 * TODO: I should really refactor the keys logic.
2577 if (nir
[MESA_SHADER_VERTEX
] &&
2578 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_prim_id
) {
2579 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg_passthrough
= false;
2582 filled_stages
|= (1 << MESA_SHADER_FRAGMENT
);
2585 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
2586 nir
[MESA_SHADER_TESS_CTRL
]) {
2587 struct nir_shader
*combined_nir
[] = {nir
[MESA_SHADER_VERTEX
], nir
[MESA_SHADER_TESS_CTRL
]};
2588 struct radv_shader_variant_key key
= keys
[MESA_SHADER_TESS_CTRL
];
2589 key
.tcs
.vs_key
= keys
[MESA_SHADER_VERTEX
].vs
;
2591 radv_nir_shader_info_init(&infos
[MESA_SHADER_TESS_CTRL
]);
2593 for (int i
= 0; i
< 2; i
++) {
2594 radv_nir_shader_info_pass(combined_nir
[i
],
2595 pipeline
->layout
, &key
,
2596 &infos
[MESA_SHADER_TESS_CTRL
]);
2599 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
=
2600 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_patches
;
2601 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
=
2602 util_last_bit64(infos
[MESA_SHADER_TESS_CTRL
].tcs
.outputs_written
);
2604 filled_stages
|= (1 << MESA_SHADER_VERTEX
);
2605 filled_stages
|= (1 << MESA_SHADER_TESS_CTRL
);
2608 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
2609 nir
[MESA_SHADER_GEOMETRY
]) {
2610 gl_shader_stage pre_stage
= nir
[MESA_SHADER_TESS_EVAL
] ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
2611 struct nir_shader
*combined_nir
[] = {nir
[pre_stage
], nir
[MESA_SHADER_GEOMETRY
]};
2613 radv_nir_shader_info_init(&infos
[MESA_SHADER_GEOMETRY
]);
2615 for (int i
= 0; i
< 2; i
++) {
2616 radv_nir_shader_info_pass(combined_nir
[i
],
2619 &infos
[MESA_SHADER_GEOMETRY
]);
2622 filled_stages
|= (1 << pre_stage
);
2623 filled_stages
|= (1 << MESA_SHADER_GEOMETRY
);
2626 active_stages
^= filled_stages
;
2627 while (active_stages
) {
2628 int i
= u_bit_scan(&active_stages
);
2630 if (i
== MESA_SHADER_TESS_CTRL
) {
2631 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
=
2632 util_last_bit64(infos
[MESA_SHADER_VERTEX
].vs
.ls_outputs_written
);
2635 if (i
== MESA_SHADER_TESS_EVAL
) {
2636 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
=
2637 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_patches
;
2638 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
=
2639 util_last_bit64(infos
[MESA_SHADER_TESS_CTRL
].tcs
.outputs_written
);
2642 radv_nir_shader_info_init(&infos
[i
]);
2643 radv_nir_shader_info_pass(nir
[i
], pipeline
->layout
,
2644 &keys
[i
], &infos
[i
]);
2647 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2649 infos
[i
].wave_size
=
2650 radv_get_wave_size(pipeline
->device
, pStages
[i
],
2656 merge_tess_info(struct shader_info
*tes_info
,
2657 const struct shader_info
*tcs_info
)
2659 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2661 * "PointMode. Controls generation of points rather than triangles
2662 * or lines. This functionality defaults to disabled, and is
2663 * enabled if either shader stage includes the execution mode.
2665 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2666 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2667 * and OutputVertices, it says:
2669 * "One mode must be set in at least one of the tessellation
2672 * So, the fields can be set in either the TCS or TES, but they must
2673 * agree if set in both. Our backend looks at TES, so bitwise-or in
2674 * the values from the TCS.
2676 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
2677 tes_info
->tess
.tcs_vertices_out
== 0 ||
2678 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
2679 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
2681 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
2682 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
2683 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
2684 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
2686 assert(tcs_info
->tess
.primitive_mode
== 0 ||
2687 tes_info
->tess
.primitive_mode
== 0 ||
2688 tcs_info
->tess
.primitive_mode
== tes_info
->tess
.primitive_mode
);
2689 tes_info
->tess
.primitive_mode
|= tcs_info
->tess
.primitive_mode
;
2690 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
2691 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
2695 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT
*ext
)
2700 if (ext
->pPipelineCreationFeedback
) {
2701 ext
->pPipelineCreationFeedback
->flags
= 0;
2702 ext
->pPipelineCreationFeedback
->duration
= 0;
2705 for (unsigned i
= 0; i
< ext
->pipelineStageCreationFeedbackCount
; ++i
) {
2706 ext
->pPipelineStageCreationFeedbacks
[i
].flags
= 0;
2707 ext
->pPipelineStageCreationFeedbacks
[i
].duration
= 0;
2712 void radv_start_feedback(VkPipelineCreationFeedbackEXT
*feedback
)
2717 feedback
->duration
-= radv_get_current_time();
2718 feedback
->flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
;
2722 void radv_stop_feedback(VkPipelineCreationFeedbackEXT
*feedback
, bool cache_hit
)
2727 feedback
->duration
+= radv_get_current_time();
2728 feedback
->flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
|
2729 (cache_hit
? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
: 0);
2732 void radv_create_shaders(struct radv_pipeline
*pipeline
,
2733 struct radv_device
*device
,
2734 struct radv_pipeline_cache
*cache
,
2735 const struct radv_pipeline_key
*key
,
2736 const VkPipelineShaderStageCreateInfo
**pStages
,
2737 const VkPipelineCreateFlags flags
,
2738 VkPipelineCreationFeedbackEXT
*pipeline_feedback
,
2739 VkPipelineCreationFeedbackEXT
**stage_feedbacks
)
2741 struct radv_shader_module fs_m
= {0};
2742 struct radv_shader_module
*modules
[MESA_SHADER_STAGES
] = { 0, };
2743 nir_shader
*nir
[MESA_SHADER_STAGES
] = {0};
2744 struct radv_shader_binary
*binaries
[MESA_SHADER_STAGES
] = {NULL
};
2745 struct radv_shader_variant_key keys
[MESA_SHADER_STAGES
] = {{{{{0}}}}};
2746 struct radv_shader_info infos
[MESA_SHADER_STAGES
] = {0};
2747 unsigned char hash
[20], gs_copy_hash
[20];
2748 bool keep_executable_info
= (flags
& VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR
) || device
->keep_shader_info
;
2750 radv_start_feedback(pipeline_feedback
);
2752 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2754 modules
[i
] = radv_shader_module_from_handle(pStages
[i
]->module
);
2755 if (modules
[i
]->nir
)
2756 _mesa_sha1_compute(modules
[i
]->nir
->info
.name
,
2757 strlen(modules
[i
]->nir
->info
.name
),
2760 pipeline
->active_stages
|= mesa_to_vk_shader_stage(i
);
2764 radv_hash_shaders(hash
, pStages
, pipeline
->layout
, key
, get_hash_flags(device
));
2765 memcpy(gs_copy_hash
, hash
, 20);
2766 gs_copy_hash
[0] ^= 1;
2768 bool found_in_application_cache
= true;
2769 if (modules
[MESA_SHADER_GEOMETRY
] && !keep_executable_info
) {
2770 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
2771 radv_create_shader_variants_from_pipeline_cache(device
, cache
, gs_copy_hash
, variants
,
2772 &found_in_application_cache
);
2773 pipeline
->gs_copy_shader
= variants
[MESA_SHADER_GEOMETRY
];
2776 if (!keep_executable_info
&&
2777 radv_create_shader_variants_from_pipeline_cache(device
, cache
, hash
, pipeline
->shaders
,
2778 &found_in_application_cache
) &&
2779 (!modules
[MESA_SHADER_GEOMETRY
] || pipeline
->gs_copy_shader
)) {
2780 radv_stop_feedback(pipeline_feedback
, found_in_application_cache
);
2784 if (!modules
[MESA_SHADER_FRAGMENT
] && !modules
[MESA_SHADER_COMPUTE
]) {
2786 nir_builder_init_simple_shader(&fs_b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
2787 fs_b
.shader
->info
.name
= ralloc_strdup(fs_b
.shader
, "noop_fs");
2788 fs_m
.nir
= fs_b
.shader
;
2789 modules
[MESA_SHADER_FRAGMENT
] = &fs_m
;
2792 bool use_aco
= device
->physical_device
->use_aco
;
2794 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2795 const VkPipelineShaderStageCreateInfo
*stage
= pStages
[i
];
2800 radv_start_feedback(stage_feedbacks
[i
]);
2802 nir
[i
] = radv_shader_compile_to_nir(device
, modules
[i
],
2803 stage
? stage
->pName
: "main", i
,
2804 stage
? stage
->pSpecializationInfo
: NULL
,
2805 flags
, pipeline
->layout
, use_aco
);
2807 /* We don't want to alter meta shaders IR directly so clone it
2810 if (nir
[i
]->info
.name
) {
2811 nir
[i
] = nir_shader_clone(NULL
, nir
[i
]);
2814 radv_stop_feedback(stage_feedbacks
[i
], false);
2817 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2818 nir_lower_patch_vertices(nir
[MESA_SHADER_TESS_EVAL
], nir
[MESA_SHADER_TESS_CTRL
]->info
.tess
.tcs_vertices_out
, NULL
);
2819 merge_tess_info(&nir
[MESA_SHADER_TESS_EVAL
]->info
, &nir
[MESA_SHADER_TESS_CTRL
]->info
);
2822 if (!(flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
))
2823 radv_link_shaders(pipeline
, nir
);
2825 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2827 NIR_PASS_V(nir
[i
], nir_lower_non_uniform_access
,
2828 nir_lower_non_uniform_ubo_access
|
2829 nir_lower_non_uniform_ssbo_access
|
2830 nir_lower_non_uniform_texture_access
|
2831 nir_lower_non_uniform_image_access
);
2834 NIR_PASS_V(nir
[i
], nir_lower_bool_to_int32
);
2838 if (nir
[MESA_SHADER_FRAGMENT
])
2839 radv_lower_fs_io(nir
[MESA_SHADER_FRAGMENT
]);
2841 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2842 if (radv_can_dump_shader(device
, modules
[i
], false))
2843 nir_print_shader(nir
[i
], stderr
);
2846 radv_fill_shader_keys(device
, keys
, key
, nir
);
2848 radv_fill_shader_info(pipeline
, pStages
, keys
, infos
, nir
);
2850 if ((nir
[MESA_SHADER_VERTEX
] &&
2851 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
) ||
2852 (nir
[MESA_SHADER_TESS_EVAL
] &&
2853 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
)) {
2854 struct gfx10_ngg_info
*ngg_info
;
2856 if (nir
[MESA_SHADER_GEOMETRY
])
2857 ngg_info
= &infos
[MESA_SHADER_GEOMETRY
].ngg_info
;
2858 else if (nir
[MESA_SHADER_TESS_CTRL
])
2859 ngg_info
= &infos
[MESA_SHADER_TESS_EVAL
].ngg_info
;
2861 ngg_info
= &infos
[MESA_SHADER_VERTEX
].ngg_info
;
2863 gfx10_get_ngg_info(key
, pipeline
, nir
, infos
, ngg_info
);
2864 } else if (nir
[MESA_SHADER_GEOMETRY
]) {
2865 struct gfx9_gs_info
*gs_info
=
2866 &infos
[MESA_SHADER_GEOMETRY
].gs_ring_info
;
2868 gfx9_get_gs_info(key
, pipeline
, nir
, infos
, gs_info
);
2871 if(modules
[MESA_SHADER_GEOMETRY
]) {
2872 struct radv_shader_binary
*gs_copy_binary
= NULL
;
2873 if (!pipeline
->gs_copy_shader
&&
2874 !radv_pipeline_has_ngg(pipeline
)) {
2875 struct radv_shader_info info
= {};
2876 struct radv_shader_variant_key key
= {};
2878 key
.has_multiview_view_index
=
2879 keys
[MESA_SHADER_GEOMETRY
].has_multiview_view_index
;
2881 radv_nir_shader_info_pass(nir
[MESA_SHADER_GEOMETRY
],
2882 pipeline
->layout
, &key
,
2884 info
.wave_size
= 64; /* Wave32 not supported. */
2886 pipeline
->gs_copy_shader
= radv_create_gs_copy_shader(
2887 device
, nir
[MESA_SHADER_GEOMETRY
], &info
,
2888 &gs_copy_binary
, keep_executable_info
,
2889 keys
[MESA_SHADER_GEOMETRY
].has_multiview_view_index
,
2893 if (!keep_executable_info
&& pipeline
->gs_copy_shader
) {
2894 struct radv_shader_binary
*binaries
[MESA_SHADER_STAGES
] = {NULL
};
2895 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
2897 binaries
[MESA_SHADER_GEOMETRY
] = gs_copy_binary
;
2898 variants
[MESA_SHADER_GEOMETRY
] = pipeline
->gs_copy_shader
;
2900 radv_pipeline_cache_insert_shaders(device
, cache
,
2905 free(gs_copy_binary
);
2908 if (nir
[MESA_SHADER_FRAGMENT
]) {
2909 if (!pipeline
->shaders
[MESA_SHADER_FRAGMENT
]) {
2910 radv_start_feedback(stage_feedbacks
[MESA_SHADER_FRAGMENT
]);
2912 pipeline
->shaders
[MESA_SHADER_FRAGMENT
] =
2913 radv_shader_variant_compile(device
, modules
[MESA_SHADER_FRAGMENT
], &nir
[MESA_SHADER_FRAGMENT
], 1,
2914 pipeline
->layout
, keys
+ MESA_SHADER_FRAGMENT
,
2915 infos
+ MESA_SHADER_FRAGMENT
,
2916 keep_executable_info
, use_aco
,
2917 &binaries
[MESA_SHADER_FRAGMENT
]);
2919 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_FRAGMENT
], false);
2923 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&& modules
[MESA_SHADER_TESS_CTRL
]) {
2924 if (!pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]) {
2925 struct nir_shader
*combined_nir
[] = {nir
[MESA_SHADER_VERTEX
], nir
[MESA_SHADER_TESS_CTRL
]};
2926 struct radv_shader_variant_key key
= keys
[MESA_SHADER_TESS_CTRL
];
2927 key
.tcs
.vs_key
= keys
[MESA_SHADER_VERTEX
].vs
;
2929 radv_start_feedback(stage_feedbacks
[MESA_SHADER_TESS_CTRL
]);
2931 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] = radv_shader_variant_compile(device
, modules
[MESA_SHADER_TESS_CTRL
], combined_nir
, 2,
2933 &key
, &infos
[MESA_SHADER_TESS_CTRL
], keep_executable_info
,
2934 use_aco
, &binaries
[MESA_SHADER_TESS_CTRL
]);
2936 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_TESS_CTRL
], false);
2938 modules
[MESA_SHADER_VERTEX
] = NULL
;
2939 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2940 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.outputs_written
);
2943 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&& modules
[MESA_SHADER_GEOMETRY
]) {
2944 gl_shader_stage pre_stage
= modules
[MESA_SHADER_TESS_EVAL
] ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
2945 if (!pipeline
->shaders
[MESA_SHADER_GEOMETRY
]) {
2946 struct nir_shader
*combined_nir
[] = {nir
[pre_stage
], nir
[MESA_SHADER_GEOMETRY
]};
2948 radv_start_feedback(stage_feedbacks
[MESA_SHADER_GEOMETRY
]);
2950 pipeline
->shaders
[MESA_SHADER_GEOMETRY
] = radv_shader_variant_compile(device
, modules
[MESA_SHADER_GEOMETRY
], combined_nir
, 2,
2952 &keys
[pre_stage
], &infos
[MESA_SHADER_GEOMETRY
], keep_executable_info
,
2953 use_aco
, &binaries
[MESA_SHADER_GEOMETRY
]);
2955 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_GEOMETRY
], false);
2957 modules
[pre_stage
] = NULL
;
2960 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2961 if(modules
[i
] && !pipeline
->shaders
[i
]) {
2962 if (i
== MESA_SHADER_TESS_CTRL
) {
2963 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.ls_outputs_written
);
2965 if (i
== MESA_SHADER_TESS_EVAL
) {
2966 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2967 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.outputs_written
);
2970 radv_start_feedback(stage_feedbacks
[i
]);
2972 pipeline
->shaders
[i
] = radv_shader_variant_compile(device
, modules
[i
], &nir
[i
], 1,
2974 keys
+ i
, infos
+ i
,keep_executable_info
,
2975 use_aco
, &binaries
[i
]);
2977 radv_stop_feedback(stage_feedbacks
[i
], false);
2981 if (!keep_executable_info
) {
2982 radv_pipeline_cache_insert_shaders(device
, cache
, hash
, pipeline
->shaders
,
2986 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2989 ralloc_free(nir
[i
]);
2991 if (radv_can_dump_shader_stats(device
, modules
[i
]))
2992 radv_shader_dump_stats(device
,
2993 pipeline
->shaders
[i
],
2999 ralloc_free(fs_m
.nir
);
3001 radv_stop_feedback(pipeline_feedback
, false);
3005 radv_pipeline_stage_to_user_data_0(struct radv_pipeline
*pipeline
,
3006 gl_shader_stage stage
, enum chip_class chip_class
)
3008 bool has_gs
= radv_pipeline_has_gs(pipeline
);
3009 bool has_tess
= radv_pipeline_has_tess(pipeline
);
3010 bool has_ngg
= radv_pipeline_has_ngg(pipeline
);
3013 case MESA_SHADER_FRAGMENT
:
3014 return R_00B030_SPI_SHADER_USER_DATA_PS_0
;
3015 case MESA_SHADER_VERTEX
:
3017 if (chip_class
>= GFX10
) {
3018 return R_00B430_SPI_SHADER_USER_DATA_HS_0
;
3019 } else if (chip_class
== GFX9
) {
3020 return R_00B430_SPI_SHADER_USER_DATA_LS_0
;
3022 return R_00B530_SPI_SHADER_USER_DATA_LS_0
;
3028 if (chip_class
>= GFX10
) {
3029 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3031 return R_00B330_SPI_SHADER_USER_DATA_ES_0
;
3036 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3038 return R_00B130_SPI_SHADER_USER_DATA_VS_0
;
3039 case MESA_SHADER_GEOMETRY
:
3040 return chip_class
== GFX9
? R_00B330_SPI_SHADER_USER_DATA_ES_0
:
3041 R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3042 case MESA_SHADER_COMPUTE
:
3043 return R_00B900_COMPUTE_USER_DATA_0
;
3044 case MESA_SHADER_TESS_CTRL
:
3045 return chip_class
== GFX9
? R_00B430_SPI_SHADER_USER_DATA_LS_0
:
3046 R_00B430_SPI_SHADER_USER_DATA_HS_0
;
3047 case MESA_SHADER_TESS_EVAL
:
3049 return chip_class
>= GFX10
? R_00B230_SPI_SHADER_USER_DATA_GS_0
:
3050 R_00B330_SPI_SHADER_USER_DATA_ES_0
;
3051 } else if (has_ngg
) {
3052 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3054 return R_00B130_SPI_SHADER_USER_DATA_VS_0
;
3057 unreachable("unknown shader");
3061 struct radv_bin_size_entry
{
3067 radv_gfx9_compute_bin_size(struct radv_pipeline
*pipeline
, const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3069 static const struct radv_bin_size_entry color_size_table
[][3][9] = {
3073 /* One shader engine */
3079 { UINT_MAX
, { 0, 0}},
3082 /* Two shader engines */
3088 { UINT_MAX
, { 0, 0}},
3091 /* Four shader engines */
3096 { UINT_MAX
, { 0, 0}},
3102 /* One shader engine */
3108 { UINT_MAX
, { 0, 0}},
3111 /* Two shader engines */
3117 { UINT_MAX
, { 0, 0}},
3120 /* Four shader engines */
3127 { UINT_MAX
, { 0, 0}},
3133 /* One shader engine */
3140 { UINT_MAX
, { 0, 0}},
3143 /* Two shader engines */
3151 { UINT_MAX
, { 0, 0}},
3154 /* Four shader engines */
3162 { UINT_MAX
, { 0, 0}},
3166 static const struct radv_bin_size_entry ds_size_table
[][3][9] = {
3170 // One shader engine
3177 { UINT_MAX
, { 0, 0}},
3180 // Two shader engines
3188 { UINT_MAX
, { 0, 0}},
3191 // Four shader engines
3199 { UINT_MAX
, { 0, 0}},
3205 // One shader engine
3213 { UINT_MAX
, { 0, 0}},
3216 // Two shader engines
3225 { UINT_MAX
, { 0, 0}},
3228 // Four shader engines
3237 { UINT_MAX
, { 0, 0}},
3243 // One shader engine
3251 { UINT_MAX
, { 0, 0}},
3254 // Two shader engines
3263 { UINT_MAX
, { 0, 0}},
3266 // Four shader engines
3274 { UINT_MAX
, { 0, 0}},
3279 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3280 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3281 VkExtent2D extent
= {512, 512};
3283 unsigned log_num_rb_per_se
=
3284 util_logbase2_ceil(pipeline
->device
->physical_device
->rad_info
.num_render_backends
/
3285 pipeline
->device
->physical_device
->rad_info
.max_se
);
3286 unsigned log_num_se
= util_logbase2_ceil(pipeline
->device
->physical_device
->rad_info
.max_se
);
3288 unsigned total_samples
= 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline
->graphics
.ms
.pa_sc_aa_config
);
3289 unsigned ps_iter_samples
= 1u << G_028804_PS_ITER_SAMPLES(pipeline
->graphics
.ms
.db_eqaa
);
3290 unsigned effective_samples
= total_samples
;
3291 unsigned color_bytes_per_pixel
= 0;
3293 const VkPipelineColorBlendStateCreateInfo
*vkblend
=
3294 radv_pipeline_get_color_blend_state(pCreateInfo
);
3296 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3297 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3300 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3303 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3304 color_bytes_per_pixel
+= vk_format_get_blocksize(format
);
3307 /* MSAA images typically don't use all samples all the time. */
3308 if (effective_samples
>= 2 && ps_iter_samples
<= 1)
3309 effective_samples
= 2;
3310 color_bytes_per_pixel
*= effective_samples
;
3313 const struct radv_bin_size_entry
*color_entry
= color_size_table
[log_num_rb_per_se
][log_num_se
];
3314 while(color_entry
[1].bpp
<= color_bytes_per_pixel
)
3317 extent
= color_entry
->extent
;
3319 if (subpass
->depth_stencil_attachment
) {
3320 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3322 /* Coefficients taken from AMDVLK */
3323 unsigned depth_coeff
= vk_format_is_depth(attachment
->format
) ? 5 : 0;
3324 unsigned stencil_coeff
= vk_format_is_stencil(attachment
->format
) ? 1 : 0;
3325 unsigned ds_bytes_per_pixel
= 4 * (depth_coeff
+ stencil_coeff
) * total_samples
;
3327 const struct radv_bin_size_entry
*ds_entry
= ds_size_table
[log_num_rb_per_se
][log_num_se
];
3328 while(ds_entry
[1].bpp
<= ds_bytes_per_pixel
)
3331 if (ds_entry
->extent
.width
* ds_entry
->extent
.height
< extent
.width
* extent
.height
)
3332 extent
= ds_entry
->extent
;
3339 radv_gfx10_compute_bin_size(struct radv_pipeline
*pipeline
, const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3341 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3342 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3343 VkExtent2D extent
= {512, 512};
3345 const unsigned db_tag_size
= 64;
3346 const unsigned db_tag_count
= 312;
3347 const unsigned color_tag_size
= 1024;
3348 const unsigned color_tag_count
= 31;
3349 const unsigned fmask_tag_size
= 256;
3350 const unsigned fmask_tag_count
= 44;
3352 const unsigned rb_count
= pipeline
->device
->physical_device
->rad_info
.num_render_backends
;
3353 const unsigned pipe_count
= MAX2(rb_count
, pipeline
->device
->physical_device
->rad_info
.num_sdp_interfaces
);
3355 const unsigned db_tag_part
= (db_tag_count
* rb_count
/ pipe_count
) * db_tag_size
* pipe_count
;
3356 const unsigned color_tag_part
= (color_tag_count
* rb_count
/ pipe_count
) * color_tag_size
* pipe_count
;
3357 const unsigned fmask_tag_part
= (fmask_tag_count
* rb_count
/ pipe_count
) * fmask_tag_size
* pipe_count
;
3359 const unsigned total_samples
= 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline
->graphics
.ms
.pa_sc_aa_config
);
3360 const unsigned samples_log
= util_logbase2_ceil(total_samples
);
3362 unsigned color_bytes_per_pixel
= 0;
3363 unsigned fmask_bytes_per_pixel
= 0;
3365 const VkPipelineColorBlendStateCreateInfo
*vkblend
=
3366 radv_pipeline_get_color_blend_state(pCreateInfo
);
3368 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3369 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3372 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3375 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3376 color_bytes_per_pixel
+= vk_format_get_blocksize(format
);
3378 if (total_samples
> 1) {
3379 assert(samples_log
<= 3);
3380 const unsigned fmask_array
[] = {0, 1, 1, 4};
3381 fmask_bytes_per_pixel
+= fmask_array
[samples_log
];
3385 color_bytes_per_pixel
*= total_samples
;
3387 color_bytes_per_pixel
= MAX2(color_bytes_per_pixel
, 1);
3389 const unsigned color_pixel_count_log
= util_logbase2(color_tag_part
/ color_bytes_per_pixel
);
3390 extent
.width
= 1ull << ((color_pixel_count_log
+ 1) / 2);
3391 extent
.height
= 1ull << (color_pixel_count_log
/ 2);
3393 if (fmask_bytes_per_pixel
) {
3394 const unsigned fmask_pixel_count_log
= util_logbase2(fmask_tag_part
/ fmask_bytes_per_pixel
);
3396 const VkExtent2D fmask_extent
= (VkExtent2D
){
3397 .width
= 1ull << ((fmask_pixel_count_log
+ 1) / 2),
3398 .height
= 1ull << (color_pixel_count_log
/ 2)
3401 if (fmask_extent
.width
* fmask_extent
.height
< extent
.width
* extent
.height
)
3402 extent
= fmask_extent
;
3405 if (subpass
->depth_stencil_attachment
) {
3406 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3408 /* Coefficients taken from AMDVLK */
3409 unsigned depth_coeff
= vk_format_is_depth(attachment
->format
) ? 5 : 0;
3410 unsigned stencil_coeff
= vk_format_is_stencil(attachment
->format
) ? 1 : 0;
3411 unsigned db_bytes_per_pixel
= (depth_coeff
+ stencil_coeff
) * total_samples
;
3413 const unsigned db_pixel_count_log
= util_logbase2(db_tag_part
/ db_bytes_per_pixel
);
3415 const VkExtent2D db_extent
= (VkExtent2D
){
3416 .width
= 1ull << ((db_pixel_count_log
+ 1) / 2),
3417 .height
= 1ull << (color_pixel_count_log
/ 2)
3420 if (db_extent
.width
* db_extent
.height
< extent
.width
* extent
.height
)
3424 extent
.width
= MAX2(extent
.width
, 128);
3425 extent
.height
= MAX2(extent
.width
, 64);
3431 radv_pipeline_generate_disabled_binning_state(struct radeon_cmdbuf
*ctx_cs
,
3432 struct radv_pipeline
*pipeline
,
3433 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3435 uint32_t pa_sc_binner_cntl_0
=
3436 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC
) |
3437 S_028C44_DISABLE_START_OF_PRIM(1);
3438 uint32_t db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
);
3440 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3441 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3442 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3443 const VkPipelineColorBlendStateCreateInfo
*vkblend
=
3444 radv_pipeline_get_color_blend_state(pCreateInfo
);
3445 unsigned min_bytes_per_pixel
= 0;
3448 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3449 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3452 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3455 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3456 unsigned bytes
= vk_format_get_blocksize(format
);
3457 if (!min_bytes_per_pixel
|| bytes
< min_bytes_per_pixel
)
3458 min_bytes_per_pixel
= bytes
;
3462 pa_sc_binner_cntl_0
=
3463 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC
) |
3464 S_028C44_BIN_SIZE_X(0) |
3465 S_028C44_BIN_SIZE_Y(0) |
3466 S_028C44_BIN_SIZE_X_EXTEND(2) | /* 128 */
3467 S_028C44_BIN_SIZE_Y_EXTEND(min_bytes_per_pixel
<= 4 ? 2 : 1) | /* 128 or 64 */
3468 S_028C44_DISABLE_START_OF_PRIM(1);
3471 pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
= pa_sc_binner_cntl_0
;
3472 pipeline
->graphics
.binning
.db_dfsm_control
= db_dfsm_control
;
3475 struct radv_binning_settings
3476 radv_get_binning_settings(const struct radv_physical_device
*pdev
)
3478 struct radv_binning_settings settings
;
3479 if (pdev
->rad_info
.has_dedicated_vram
) {
3480 settings
.context_states_per_bin
= 1;
3481 settings
.persistent_states_per_bin
= 1;
3482 settings
.fpovs_per_batch
= 63;
3484 /* The context states are affected by the scissor bug. */
3485 settings
.context_states_per_bin
= 6;
3486 /* 32 causes hangs for RAVEN. */
3487 settings
.persistent_states_per_bin
= 16;
3488 settings
.fpovs_per_batch
= 63;
3491 if (pdev
->rad_info
.has_gfx9_scissor_bug
)
3492 settings
.context_states_per_bin
= 1;
3498 radv_pipeline_generate_binning_state(struct radeon_cmdbuf
*ctx_cs
,
3499 struct radv_pipeline
*pipeline
,
3500 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3501 const struct radv_blend_state
*blend
)
3503 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX9
)
3506 VkExtent2D bin_size
;
3507 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3508 bin_size
= radv_gfx10_compute_bin_size(pipeline
, pCreateInfo
);
3509 } else if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
3510 bin_size
= radv_gfx9_compute_bin_size(pipeline
, pCreateInfo
);
3512 unreachable("Unhandled generation for binning bin size calculation");
3514 if (pipeline
->device
->pbb_allowed
&& bin_size
.width
&& bin_size
.height
) {
3515 struct radv_binning_settings settings
=
3516 radv_get_binning_settings(pipeline
->device
->physical_device
);
3518 bool disable_start_of_prim
= true;
3519 uint32_t db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
);
3521 const struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3523 if (pipeline
->device
->dfsm_allowed
&& ps
&&
3524 !ps
->info
.ps
.can_discard
&&
3525 !ps
->info
.ps
.writes_memory
&&
3526 blend
->cb_target_enabled_4bit
) {
3527 db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_AUTO
);
3528 disable_start_of_prim
= (blend
->blend_enable_4bit
& blend
->cb_target_enabled_4bit
) != 0;
3531 const uint32_t pa_sc_binner_cntl_0
=
3532 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED
) |
3533 S_028C44_BIN_SIZE_X(bin_size
.width
== 16) |
3534 S_028C44_BIN_SIZE_Y(bin_size
.height
== 16) |
3535 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size
.width
, 32)) - 5) |
3536 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size
.height
, 32)) - 5) |
3537 S_028C44_CONTEXT_STATES_PER_BIN(settings
.context_states_per_bin
- 1) |
3538 S_028C44_PERSISTENT_STATES_PER_BIN(settings
.persistent_states_per_bin
- 1) |
3539 S_028C44_DISABLE_START_OF_PRIM(disable_start_of_prim
) |
3540 S_028C44_FPOVS_PER_BATCH(settings
.fpovs_per_batch
) |
3541 S_028C44_OPTIMAL_BIN_SELECTION(1);
3543 pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
= pa_sc_binner_cntl_0
;
3544 pipeline
->graphics
.binning
.db_dfsm_control
= db_dfsm_control
;
3546 radv_pipeline_generate_disabled_binning_state(ctx_cs
, pipeline
, pCreateInfo
);
3551 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf
*ctx_cs
,
3552 struct radv_pipeline
*pipeline
,
3553 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3554 const struct radv_graphics_pipeline_create_info
*extra
)
3556 const VkPipelineDepthStencilStateCreateInfo
*vkds
= radv_pipeline_get_depth_stencil_state(pCreateInfo
);
3557 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3558 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3559 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3560 struct radv_render_pass_attachment
*attachment
= NULL
;
3561 uint32_t db_depth_control
= 0, db_stencil_control
= 0;
3562 uint32_t db_render_control
= 0, db_render_override2
= 0;
3563 uint32_t db_render_override
= 0;
3565 if (subpass
->depth_stencil_attachment
)
3566 attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3568 bool has_depth_attachment
= attachment
&& vk_format_is_depth(attachment
->format
);
3569 bool has_stencil_attachment
= attachment
&& vk_format_is_stencil(attachment
->format
);
3571 if (vkds
&& has_depth_attachment
) {
3572 db_depth_control
= S_028800_Z_ENABLE(vkds
->depthTestEnable
? 1 : 0) |
3573 S_028800_Z_WRITE_ENABLE(vkds
->depthWriteEnable
? 1 : 0) |
3574 S_028800_ZFUNC(vkds
->depthCompareOp
) |
3575 S_028800_DEPTH_BOUNDS_ENABLE(vkds
->depthBoundsTestEnable
? 1 : 0);
3577 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
3578 db_render_override2
|= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment
->samples
> 2);
3581 if (has_stencil_attachment
&& vkds
&& vkds
->stencilTestEnable
) {
3582 db_depth_control
|= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
3583 db_depth_control
|= S_028800_STENCILFUNC(vkds
->front
.compareOp
);
3584 db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds
->front
.failOp
));
3585 db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds
->front
.passOp
));
3586 db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds
->front
.depthFailOp
));
3588 db_depth_control
|= S_028800_STENCILFUNC_BF(vkds
->back
.compareOp
);
3589 db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds
->back
.failOp
));
3590 db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds
->back
.passOp
));
3591 db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds
->back
.depthFailOp
));
3594 if (attachment
&& extra
) {
3595 db_render_control
|= S_028000_DEPTH_CLEAR_ENABLE(extra
->db_depth_clear
);
3596 db_render_control
|= S_028000_STENCIL_CLEAR_ENABLE(extra
->db_stencil_clear
);
3598 db_render_control
|= S_028000_RESUMMARIZE_ENABLE(extra
->db_resummarize
);
3599 db_render_control
|= S_028000_DEPTH_COMPRESS_DISABLE(extra
->db_flush_depth_inplace
);
3600 db_render_control
|= S_028000_STENCIL_COMPRESS_DISABLE(extra
->db_flush_stencil_inplace
);
3601 db_render_override2
|= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra
->db_depth_disable_expclear
);
3602 db_render_override2
|= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra
->db_stencil_disable_expclear
);
3605 db_render_override
|= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
3606 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
);
3608 if (!pCreateInfo
->pRasterizationState
->depthClampEnable
&&
3609 ps
->info
.ps
.writes_z
) {
3610 /* From VK_EXT_depth_range_unrestricted spec:
3612 * "The behavior described in Primitive Clipping still applies.
3613 * If depth clamping is disabled the depth values are still
3614 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
3615 * depth clamping is enabled the above equation is ignored and
3616 * the depth values are instead clamped to the VkViewport
3617 * minDepth and maxDepth values, which in the case of this
3618 * extension can be outside of the 0.0 to 1.0 range."
3620 db_render_override
|= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
3623 radeon_set_context_reg(ctx_cs
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
3624 radeon_set_context_reg(ctx_cs
, R_02842C_DB_STENCIL_CONTROL
, db_stencil_control
);
3626 radeon_set_context_reg(ctx_cs
, R_028000_DB_RENDER_CONTROL
, db_render_control
);
3627 radeon_set_context_reg(ctx_cs
, R_02800C_DB_RENDER_OVERRIDE
, db_render_override
);
3628 radeon_set_context_reg(ctx_cs
, R_028010_DB_RENDER_OVERRIDE2
, db_render_override2
);
3632 radv_pipeline_generate_blend_state(struct radeon_cmdbuf
*ctx_cs
,
3633 struct radv_pipeline
*pipeline
,
3634 const struct radv_blend_state
*blend
)
3636 radeon_set_context_reg_seq(ctx_cs
, R_028780_CB_BLEND0_CONTROL
, 8);
3637 radeon_emit_array(ctx_cs
, blend
->cb_blend_control
,
3639 radeon_set_context_reg(ctx_cs
, R_028808_CB_COLOR_CONTROL
, blend
->cb_color_control
);
3640 radeon_set_context_reg(ctx_cs
, R_028B70_DB_ALPHA_TO_MASK
, blend
->db_alpha_to_mask
);
3642 if (pipeline
->device
->physical_device
->rad_info
.has_rbplus
) {
3644 radeon_set_context_reg_seq(ctx_cs
, R_028760_SX_MRT0_BLEND_OPT
, 8);
3645 radeon_emit_array(ctx_cs
, blend
->sx_mrt_blend_opt
, 8);
3648 radeon_set_context_reg(ctx_cs
, R_028714_SPI_SHADER_COL_FORMAT
, blend
->spi_shader_col_format
);
3650 radeon_set_context_reg(ctx_cs
, R_028238_CB_TARGET_MASK
, blend
->cb_target_mask
);
3651 radeon_set_context_reg(ctx_cs
, R_02823C_CB_SHADER_MASK
, blend
->cb_shader_mask
);
3653 pipeline
->graphics
.col_format
= blend
->spi_shader_col_format
;
3654 pipeline
->graphics
.cb_target_mask
= blend
->cb_target_mask
;
3657 static const VkConservativeRasterizationModeEXT
3658 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo
*pCreateInfo
)
3660 const VkPipelineRasterizationConservativeStateCreateInfoEXT
*conservative_raster
=
3661 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT
);
3663 if (!conservative_raster
)
3664 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT
;
3665 return conservative_raster
->conservativeRasterizationMode
;
3669 radv_pipeline_generate_raster_state(struct radeon_cmdbuf
*ctx_cs
,
3670 struct radv_pipeline
*pipeline
,
3671 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3673 const VkPipelineRasterizationStateCreateInfo
*vkraster
= pCreateInfo
->pRasterizationState
;
3674 const VkConservativeRasterizationModeEXT mode
=
3675 radv_get_conservative_raster_mode(vkraster
);
3676 uint32_t pa_sc_conservative_rast
= S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
3677 bool depth_clip_disable
= vkraster
->depthClampEnable
;
3679 const VkPipelineRasterizationDepthClipStateCreateInfoEXT
*depth_clip_state
=
3680 vk_find_struct_const(vkraster
->pNext
, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT
);
3681 if (depth_clip_state
) {
3682 depth_clip_disable
= !depth_clip_state
->depthClipEnable
;
3685 radeon_set_context_reg(ctx_cs
, R_028810_PA_CL_CLIP_CNTL
,
3686 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
3687 S_028810_ZCLIP_NEAR_DISABLE(depth_clip_disable
? 1 : 0) |
3688 S_028810_ZCLIP_FAR_DISABLE(depth_clip_disable
? 1 : 0) |
3689 S_028810_DX_RASTERIZATION_KILL(vkraster
->rasterizerDiscardEnable
? 1 : 0) |
3690 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
3692 radeon_set_context_reg(ctx_cs
, R_0286D4_SPI_INTERP_CONTROL_0
,
3693 S_0286D4_FLAT_SHADE_ENA(1) |
3694 S_0286D4_PNT_SPRITE_ENA(1) |
3695 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
3696 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
3697 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
3698 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
3699 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
3701 radeon_set_context_reg(ctx_cs
, R_028BE4_PA_SU_VTX_CNTL
,
3702 S_028BE4_PIX_CENTER(1) | // TODO verify
3703 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN
) |
3704 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH
));
3706 radeon_set_context_reg(ctx_cs
, R_028814_PA_SU_SC_MODE_CNTL
,
3707 S_028814_FACE(vkraster
->frontFace
) |
3708 S_028814_CULL_FRONT(!!(vkraster
->cullMode
& VK_CULL_MODE_FRONT_BIT
)) |
3709 S_028814_CULL_BACK(!!(vkraster
->cullMode
& VK_CULL_MODE_BACK_BIT
)) |
3710 S_028814_POLY_MODE(vkraster
->polygonMode
!= VK_POLYGON_MODE_FILL
) |
3711 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
3712 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
3713 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
3714 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
3715 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster
->depthBiasEnable
? 1 : 0));
3717 /* Conservative rasterization. */
3718 if (mode
!= VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT
) {
3719 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
3721 ms
->pa_sc_aa_config
|= S_028BE0_AA_MASK_CENTROID_DTMN(1);
3722 ms
->db_eqaa
|= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
3723 S_028804_OVERRASTERIZATION_AMOUNT(4);
3725 pa_sc_conservative_rast
= S_028C4C_PREZ_AA_MASK_ENABLE(1) |
3726 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
3727 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
3729 if (mode
== VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT
) {
3730 pa_sc_conservative_rast
|=
3731 S_028C4C_OVER_RAST_ENABLE(1) |
3732 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
3733 S_028C4C_UNDER_RAST_ENABLE(0) |
3734 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
3735 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
3737 assert(mode
== VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT
);
3738 pa_sc_conservative_rast
|=
3739 S_028C4C_OVER_RAST_ENABLE(0) |
3740 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
3741 S_028C4C_UNDER_RAST_ENABLE(1) |
3742 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
3743 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
3747 radeon_set_context_reg(ctx_cs
, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
,
3748 pa_sc_conservative_rast
);
3753 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf
*ctx_cs
,
3754 struct radv_pipeline
*pipeline
)
3756 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
3758 radeon_set_context_reg_seq(ctx_cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
3759 radeon_emit(ctx_cs
, ms
->pa_sc_aa_mask
[0]);
3760 radeon_emit(ctx_cs
, ms
->pa_sc_aa_mask
[1]);
3762 radeon_set_context_reg(ctx_cs
, R_028804_DB_EQAA
, ms
->db_eqaa
);
3763 radeon_set_context_reg(ctx_cs
, R_028A48_PA_SC_MODE_CNTL_0
, ms
->pa_sc_mode_cntl_0
);
3764 radeon_set_context_reg(ctx_cs
, R_028A4C_PA_SC_MODE_CNTL_1
, ms
->pa_sc_mode_cntl_1
);
3765 radeon_set_context_reg(ctx_cs
, R_028BDC_PA_SC_LINE_CNTL
, ms
->pa_sc_line_cntl
);
3766 radeon_set_context_reg(ctx_cs
, R_028BE0_PA_SC_AA_CONFIG
, ms
->pa_sc_aa_config
);
3768 /* The exclusion bits can be set to improve rasterization efficiency
3769 * if no sample lies on the pixel boundary (-8 sample offset). It's
3770 * currently always TRUE because the driver doesn't support 16 samples.
3772 bool exclusion
= pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
3773 radeon_set_context_reg(ctx_cs
, R_02882C_PA_SU_PRIM_FILTER_CNTL
,
3774 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion
) |
3775 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion
));
3777 /* GFX9: Flush DFSM when the AA mode changes. */
3778 if (pipeline
->device
->dfsm_allowed
) {
3779 radeon_emit(ctx_cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3780 radeon_emit(ctx_cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
3785 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf
*ctx_cs
,
3786 struct radv_pipeline
*pipeline
)
3788 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3789 const struct radv_shader_variant
*vs
=
3790 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] ?
3791 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] :
3792 pipeline
->shaders
[MESA_SHADER_VERTEX
];
3793 unsigned vgt_primitiveid_en
= 0;
3794 uint32_t vgt_gs_mode
= 0;
3796 if (radv_pipeline_has_ngg(pipeline
))
3799 if (radv_pipeline_has_gs(pipeline
)) {
3800 const struct radv_shader_variant
*gs
=
3801 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3803 vgt_gs_mode
= ac_vgt_gs_mode(gs
->info
.gs
.vertices_out
,
3804 pipeline
->device
->physical_device
->rad_info
.chip_class
);
3805 } else if (outinfo
->export_prim_id
|| vs
->info
.uses_prim_id
) {
3806 vgt_gs_mode
= S_028A40_MODE(V_028A40_GS_SCENARIO_A
);
3807 vgt_primitiveid_en
|= S_028A84_PRIMITIVEID_EN(1);
3810 radeon_set_context_reg(ctx_cs
, R_028A84_VGT_PRIMITIVEID_EN
, vgt_primitiveid_en
);
3811 radeon_set_context_reg(ctx_cs
, R_028A40_VGT_GS_MODE
, vgt_gs_mode
);
3815 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf
*ctx_cs
,
3816 struct radeon_cmdbuf
*cs
,
3817 struct radv_pipeline
*pipeline
,
3818 struct radv_shader_variant
*shader
)
3820 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3822 radeon_set_sh_reg_seq(cs
, R_00B120_SPI_SHADER_PGM_LO_VS
, 4);
3823 radeon_emit(cs
, va
>> 8);
3824 radeon_emit(cs
, S_00B124_MEM_BASE(va
>> 40));
3825 radeon_emit(cs
, shader
->config
.rsrc1
);
3826 radeon_emit(cs
, shader
->config
.rsrc2
);
3828 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3829 unsigned clip_dist_mask
, cull_dist_mask
, total_mask
;
3830 clip_dist_mask
= outinfo
->clip_dist_mask
;
3831 cull_dist_mask
= outinfo
->cull_dist_mask
;
3832 total_mask
= clip_dist_mask
| cull_dist_mask
;
3833 bool misc_vec_ena
= outinfo
->writes_pointsize
||
3834 outinfo
->writes_layer
||
3835 outinfo
->writes_viewport_index
;
3836 unsigned spi_vs_out_config
, nparams
;
3838 /* VS is required to export at least one param. */
3839 nparams
= MAX2(outinfo
->param_exports
, 1);
3840 spi_vs_out_config
= S_0286C4_VS_EXPORT_COUNT(nparams
- 1);
3842 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3843 spi_vs_out_config
|= S_0286C4_NO_PC_EXPORT(outinfo
->param_exports
== 0);
3846 radeon_set_context_reg(ctx_cs
, R_0286C4_SPI_VS_OUT_CONFIG
, spi_vs_out_config
);
3848 radeon_set_context_reg(ctx_cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
3849 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
3850 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
3851 V_02870C_SPI_SHADER_4COMP
:
3852 V_02870C_SPI_SHADER_NONE
) |
3853 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
3854 V_02870C_SPI_SHADER_4COMP
:
3855 V_02870C_SPI_SHADER_NONE
) |
3856 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
3857 V_02870C_SPI_SHADER_4COMP
:
3858 V_02870C_SPI_SHADER_NONE
));
3860 radeon_set_context_reg(ctx_cs
, R_028818_PA_CL_VTE_CNTL
,
3861 S_028818_VTX_W0_FMT(1) |
3862 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3863 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3864 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3866 radeon_set_context_reg(ctx_cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
3867 S_02881C_USE_VTX_POINT_SIZE(outinfo
->writes_pointsize
) |
3868 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo
->writes_layer
) |
3869 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo
->writes_viewport_index
) |
3870 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
3871 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
) |
3872 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0f) != 0) |
3873 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xf0) != 0) |
3874 cull_dist_mask
<< 8 |
3877 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
)
3878 radeon_set_context_reg(ctx_cs
, R_028AB4_VGT_REUSE_OFF
,
3879 outinfo
->writes_viewport_index
);
3883 radv_pipeline_generate_hw_es(struct radeon_cmdbuf
*cs
,
3884 struct radv_pipeline
*pipeline
,
3885 struct radv_shader_variant
*shader
)
3887 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3889 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 4);
3890 radeon_emit(cs
, va
>> 8);
3891 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
3892 radeon_emit(cs
, shader
->config
.rsrc1
);
3893 radeon_emit(cs
, shader
->config
.rsrc2
);
3897 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf
*cs
,
3898 struct radv_pipeline
*pipeline
,
3899 struct radv_shader_variant
*shader
,
3900 const struct radv_tessellation_state
*tess
)
3902 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3903 uint32_t rsrc2
= shader
->config
.rsrc2
;
3905 radeon_set_sh_reg_seq(cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
3906 radeon_emit(cs
, va
>> 8);
3907 radeon_emit(cs
, S_00B524_MEM_BASE(va
>> 40));
3909 rsrc2
|= S_00B52C_LDS_SIZE(tess
->lds_size
);
3910 if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX7
&&
3911 pipeline
->device
->physical_device
->rad_info
.family
!= CHIP_HAWAII
)
3912 radeon_set_sh_reg(cs
, R_00B52C_SPI_SHADER_PGM_RSRC2_LS
, rsrc2
);
3914 radeon_set_sh_reg_seq(cs
, R_00B528_SPI_SHADER_PGM_RSRC1_LS
, 2);
3915 radeon_emit(cs
, shader
->config
.rsrc1
);
3916 radeon_emit(cs
, rsrc2
);
3920 radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf
*ctx_cs
,
3921 struct radeon_cmdbuf
*cs
,
3922 struct radv_pipeline
*pipeline
,
3923 struct radv_shader_variant
*shader
)
3925 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3926 gl_shader_stage es_type
=
3927 radv_pipeline_has_tess(pipeline
) ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
3928 struct radv_shader_variant
*es
=
3929 es_type
== MESA_SHADER_TESS_EVAL
? pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] : pipeline
->shaders
[MESA_SHADER_VERTEX
];
3930 const struct gfx10_ngg_info
*ngg_state
= &shader
->info
.ngg_info
;
3932 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 2);
3933 radeon_emit(cs
, va
>> 8);
3934 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
3935 radeon_set_sh_reg_seq(cs
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, 2);
3936 radeon_emit(cs
, shader
->config
.rsrc1
);
3937 radeon_emit(cs
, shader
->config
.rsrc2
);
3939 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3940 unsigned clip_dist_mask
, cull_dist_mask
, total_mask
;
3941 clip_dist_mask
= outinfo
->clip_dist_mask
;
3942 cull_dist_mask
= outinfo
->cull_dist_mask
;
3943 total_mask
= clip_dist_mask
| cull_dist_mask
;
3944 bool misc_vec_ena
= outinfo
->writes_pointsize
||
3945 outinfo
->writes_layer
||
3946 outinfo
->writes_viewport_index
;
3947 bool es_enable_prim_id
= outinfo
->export_prim_id
||
3948 (es
&& es
->info
.uses_prim_id
);
3949 bool break_wave_at_eoi
= false;
3953 if (es_type
== MESA_SHADER_TESS_EVAL
) {
3954 struct radv_shader_variant
*gs
=
3955 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3957 if (es_enable_prim_id
|| (gs
&& gs
->info
.uses_prim_id
))
3958 break_wave_at_eoi
= true;
3961 nparams
= MAX2(outinfo
->param_exports
, 1);
3962 radeon_set_context_reg(ctx_cs
, R_0286C4_SPI_VS_OUT_CONFIG
,
3963 S_0286C4_VS_EXPORT_COUNT(nparams
- 1) |
3964 S_0286C4_NO_PC_EXPORT(outinfo
->param_exports
== 0));
3966 radeon_set_context_reg(ctx_cs
, R_028708_SPI_SHADER_IDX_FORMAT
,
3967 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP
));
3968 radeon_set_context_reg(ctx_cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
3969 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
3970 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
3971 V_02870C_SPI_SHADER_4COMP
:
3972 V_02870C_SPI_SHADER_NONE
) |
3973 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
3974 V_02870C_SPI_SHADER_4COMP
:
3975 V_02870C_SPI_SHADER_NONE
) |
3976 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
3977 V_02870C_SPI_SHADER_4COMP
:
3978 V_02870C_SPI_SHADER_NONE
));
3980 radeon_set_context_reg(ctx_cs
, R_028818_PA_CL_VTE_CNTL
,
3981 S_028818_VTX_W0_FMT(1) |
3982 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3983 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3984 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3985 radeon_set_context_reg(ctx_cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
3986 S_02881C_USE_VTX_POINT_SIZE(outinfo
->writes_pointsize
) |
3987 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo
->writes_layer
) |
3988 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo
->writes_viewport_index
) |
3989 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
3990 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
) |
3991 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0f) != 0) |
3992 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xf0) != 0) |
3993 cull_dist_mask
<< 8 |
3996 radeon_set_context_reg(ctx_cs
, R_028A84_VGT_PRIMITIVEID_EN
,
3997 S_028A84_PRIMITIVEID_EN(es_enable_prim_id
) |
3998 S_028A84_NGG_DISABLE_PROVOK_REUSE(outinfo
->export_prim_id
));
4000 radeon_set_context_reg(ctx_cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
4001 ngg_state
->vgt_esgs_ring_itemsize
);
4003 /* NGG specific registers. */
4004 struct radv_shader_variant
*gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
4005 uint32_t gs_num_invocations
= gs
? gs
->info
.gs
.invocations
: 1;
4007 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
,
4008 S_028A44_ES_VERTS_PER_SUBGRP(ngg_state
->hw_max_esverts
) |
4009 S_028A44_GS_PRIMS_PER_SUBGRP(ngg_state
->max_gsprims
) |
4010 S_028A44_GS_INST_PRIMS_IN_SUBGRP(ngg_state
->max_gsprims
* gs_num_invocations
));
4011 radeon_set_context_reg(ctx_cs
, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP
,
4012 S_0287FC_MAX_VERTS_PER_SUBGROUP(ngg_state
->max_out_verts
));
4013 radeon_set_context_reg(ctx_cs
, R_028B4C_GE_NGG_SUBGRP_CNTL
,
4014 S_028B4C_PRIM_AMP_FACTOR(ngg_state
->prim_amp_factor
) |
4015 S_028B4C_THDS_PER_SUBGRP(0)); /* for fast launch */
4016 radeon_set_context_reg(ctx_cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
4017 S_028B90_CNT(gs_num_invocations
) |
4018 S_028B90_ENABLE(gs_num_invocations
> 1) |
4019 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(ngg_state
->max_vert_out_per_gs_instance
));
4021 /* User edge flags are set by the pos exports. If user edge flags are
4022 * not used, we must use hw-generated edge flags and pass them via
4023 * the prim export to prevent drawing lines on internal edges of
4024 * decomposed primitives (such as quads) with polygon mode = lines.
4026 * TODO: We should combine hw-generated edge flags with user edge
4027 * flags in the shader.
4029 radeon_set_context_reg(ctx_cs
, R_028838_PA_CL_NGG_CNTL
,
4030 S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline
) &&
4031 !radv_pipeline_has_gs(pipeline
)));
4033 ge_cntl
= S_03096C_PRIM_GRP_SIZE(ngg_state
->max_gsprims
) |
4034 S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
4035 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
);
4037 /* Bug workaround for a possible hang with non-tessellation cases.
4038 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
4040 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
4042 if ((pipeline
->device
->physical_device
->rad_info
.family
== CHIP_NAVI10
||
4043 pipeline
->device
->physical_device
->rad_info
.family
== CHIP_NAVI12
||
4044 pipeline
->device
->physical_device
->rad_info
.family
== CHIP_NAVI14
) &&
4045 !radv_pipeline_has_tess(pipeline
) &&
4046 ngg_state
->hw_max_esverts
!= 256) {
4047 ge_cntl
&= C_03096C_VERT_GRP_SIZE
;
4049 if (ngg_state
->hw_max_esverts
> 5) {
4050 ge_cntl
|= S_03096C_VERT_GRP_SIZE(ngg_state
->hw_max_esverts
- 5);
4054 radeon_set_uconfig_reg(ctx_cs
, R_03096C_GE_CNTL
, ge_cntl
);
4058 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf
*cs
,
4059 struct radv_pipeline
*pipeline
,
4060 struct radv_shader_variant
*shader
,
4061 const struct radv_tessellation_state
*tess
)
4063 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
4065 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4066 unsigned hs_rsrc2
= shader
->config
.rsrc2
;
4068 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4069 hs_rsrc2
|= S_00B42C_LDS_SIZE_GFX10(tess
->lds_size
);
4071 hs_rsrc2
|= S_00B42C_LDS_SIZE_GFX9(tess
->lds_size
);
4074 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4075 radeon_set_sh_reg_seq(cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
4076 radeon_emit(cs
, va
>> 8);
4077 radeon_emit(cs
, S_00B524_MEM_BASE(va
>> 40));
4079 radeon_set_sh_reg_seq(cs
, R_00B410_SPI_SHADER_PGM_LO_LS
, 2);
4080 radeon_emit(cs
, va
>> 8);
4081 radeon_emit(cs
, S_00B414_MEM_BASE(va
>> 40));
4084 radeon_set_sh_reg_seq(cs
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
, 2);
4085 radeon_emit(cs
, shader
->config
.rsrc1
);
4086 radeon_emit(cs
, hs_rsrc2
);
4088 radeon_set_sh_reg_seq(cs
, R_00B420_SPI_SHADER_PGM_LO_HS
, 4);
4089 radeon_emit(cs
, va
>> 8);
4090 radeon_emit(cs
, S_00B424_MEM_BASE(va
>> 40));
4091 radeon_emit(cs
, shader
->config
.rsrc1
);
4092 radeon_emit(cs
, shader
->config
.rsrc2
);
4097 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf
*ctx_cs
,
4098 struct radeon_cmdbuf
*cs
,
4099 struct radv_pipeline
*pipeline
,
4100 const struct radv_tessellation_state
*tess
)
4102 struct radv_shader_variant
*vs
;
4104 /* Skip shaders merged into HS/GS */
4105 vs
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
4109 if (vs
->info
.vs
.as_ls
)
4110 radv_pipeline_generate_hw_ls(cs
, pipeline
, vs
, tess
);
4111 else if (vs
->info
.vs
.as_es
)
4112 radv_pipeline_generate_hw_es(cs
, pipeline
, vs
);
4113 else if (vs
->info
.is_ngg
)
4114 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, vs
);
4116 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, vs
);
4120 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf
*ctx_cs
,
4121 struct radeon_cmdbuf
*cs
,
4122 struct radv_pipeline
*pipeline
,
4123 const struct radv_tessellation_state
*tess
)
4125 if (!radv_pipeline_has_tess(pipeline
))
4128 struct radv_shader_variant
*tes
, *tcs
;
4130 tcs
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
4131 tes
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
4134 if (tes
->info
.is_ngg
) {
4135 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, tes
);
4136 } else if (tes
->info
.tes
.as_es
)
4137 radv_pipeline_generate_hw_es(cs
, pipeline
, tes
);
4139 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, tes
);
4142 radv_pipeline_generate_hw_hs(cs
, pipeline
, tcs
, tess
);
4144 radeon_set_context_reg(ctx_cs
, R_028B6C_VGT_TF_PARAM
,
4147 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
)
4148 radeon_set_context_reg_idx(ctx_cs
, R_028B58_VGT_LS_HS_CONFIG
, 2,
4149 tess
->ls_hs_config
);
4151 radeon_set_context_reg(ctx_cs
, R_028B58_VGT_LS_HS_CONFIG
,
4152 tess
->ls_hs_config
);
4154 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
&&
4155 !radv_pipeline_has_gs(pipeline
) && !radv_pipeline_has_ngg(pipeline
)) {
4156 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
,
4157 S_028A44_ES_VERTS_PER_SUBGRP(250) |
4158 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
4159 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
4164 radv_pipeline_generate_hw_gs(struct radeon_cmdbuf
*ctx_cs
,
4165 struct radeon_cmdbuf
*cs
,
4166 struct radv_pipeline
*pipeline
,
4167 struct radv_shader_variant
*gs
)
4169 const struct gfx9_gs_info
*gs_state
= &gs
->info
.gs_ring_info
;
4170 unsigned gs_max_out_vertices
;
4171 uint8_t *num_components
;
4176 gs_max_out_vertices
= gs
->info
.gs
.vertices_out
;
4177 max_stream
= gs
->info
.gs
.max_stream
;
4178 num_components
= gs
->info
.gs
.num_stream_output_components
;
4180 offset
= num_components
[0] * gs_max_out_vertices
;
4182 radeon_set_context_reg_seq(ctx_cs
, R_028A60_VGT_GSVS_RING_OFFSET_1
, 3);
4183 radeon_emit(ctx_cs
, offset
);
4184 if (max_stream
>= 1)
4185 offset
+= num_components
[1] * gs_max_out_vertices
;
4186 radeon_emit(ctx_cs
, offset
);
4187 if (max_stream
>= 2)
4188 offset
+= num_components
[2] * gs_max_out_vertices
;
4189 radeon_emit(ctx_cs
, offset
);
4190 if (max_stream
>= 3)
4191 offset
+= num_components
[3] * gs_max_out_vertices
;
4192 radeon_set_context_reg(ctx_cs
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, offset
);
4194 radeon_set_context_reg_seq(ctx_cs
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, 4);
4195 radeon_emit(ctx_cs
, num_components
[0]);
4196 radeon_emit(ctx_cs
, (max_stream
>= 1) ? num_components
[1] : 0);
4197 radeon_emit(ctx_cs
, (max_stream
>= 2) ? num_components
[2] : 0);
4198 radeon_emit(ctx_cs
, (max_stream
>= 3) ? num_components
[3] : 0);
4200 uint32_t gs_num_invocations
= gs
->info
.gs
.invocations
;
4201 radeon_set_context_reg(ctx_cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
4202 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
4203 S_028B90_ENABLE(gs_num_invocations
> 0));
4205 radeon_set_context_reg(ctx_cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
4206 gs_state
->vgt_esgs_ring_itemsize
);
4208 va
= radv_buffer_get_va(gs
->bo
) + gs
->bo_offset
;
4210 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4211 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4212 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 2);
4213 radeon_emit(cs
, va
>> 8);
4214 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
4216 radeon_set_sh_reg_seq(cs
, R_00B210_SPI_SHADER_PGM_LO_ES
, 2);
4217 radeon_emit(cs
, va
>> 8);
4218 radeon_emit(cs
, S_00B214_MEM_BASE(va
>> 40));
4221 radeon_set_sh_reg_seq(cs
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, 2);
4222 radeon_emit(cs
, gs
->config
.rsrc1
);
4223 radeon_emit(cs
, gs
->config
.rsrc2
| S_00B22C_LDS_SIZE(gs_state
->lds_size
));
4225 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
, gs_state
->vgt_gs_onchip_cntl
);
4226 radeon_set_context_reg(ctx_cs
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
, gs_state
->vgt_gs_max_prims_per_subgroup
);
4228 radeon_set_sh_reg_seq(cs
, R_00B220_SPI_SHADER_PGM_LO_GS
, 4);
4229 radeon_emit(cs
, va
>> 8);
4230 radeon_emit(cs
, S_00B224_MEM_BASE(va
>> 40));
4231 radeon_emit(cs
, gs
->config
.rsrc1
);
4232 radeon_emit(cs
, gs
->config
.rsrc2
);
4235 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, pipeline
->gs_copy_shader
);
4239 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf
*ctx_cs
,
4240 struct radeon_cmdbuf
*cs
,
4241 struct radv_pipeline
*pipeline
)
4243 struct radv_shader_variant
*gs
;
4245 gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
4249 if (gs
->info
.is_ngg
)
4250 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, gs
);
4252 radv_pipeline_generate_hw_gs(ctx_cs
, cs
, pipeline
, gs
);
4254 radeon_set_context_reg(ctx_cs
, R_028B38_VGT_GS_MAX_VERT_OUT
,
4255 gs
->info
.gs
.vertices_out
);
4258 static uint32_t offset_to_ps_input(uint32_t offset
, bool flat_shade
,
4259 bool explicit, bool float16
)
4261 uint32_t ps_input_cntl
;
4262 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
4263 ps_input_cntl
= S_028644_OFFSET(offset
);
4264 if (flat_shade
|| explicit)
4265 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
4267 /* Force parameter cache to be read in passthrough
4270 ps_input_cntl
|= S_028644_OFFSET(1 << 5);
4273 ps_input_cntl
|= S_028644_FP16_INTERP_MODE(1) |
4274 S_028644_ATTR0_VALID(1);
4277 /* The input is a DEFAULT_VAL constant. */
4278 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
4279 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
4280 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
4281 ps_input_cntl
= S_028644_OFFSET(0x20) |
4282 S_028644_DEFAULT_VAL(offset
);
4284 return ps_input_cntl
;
4288 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf
*ctx_cs
,
4289 struct radv_pipeline
*pipeline
)
4291 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4292 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
4293 uint32_t ps_input_cntl
[32];
4295 unsigned ps_offset
= 0;
4297 if (ps
->info
.ps
.prim_id_input
) {
4298 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
];
4299 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
4300 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false, false);
4305 if (ps
->info
.ps
.layer_input
||
4306 ps
->info
.needs_multiview_view_index
) {
4307 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
];
4308 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
)
4309 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false, false);
4311 ps_input_cntl
[ps_offset
] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000
, true, false, false);
4315 if (ps
->info
.ps
.has_pcoord
) {
4317 val
= S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
4318 ps_input_cntl
[ps_offset
] = val
;
4322 if (ps
->info
.ps
.num_input_clips_culls
) {
4325 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST0
];
4326 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
4327 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, false, false, false);
4331 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST1
];
4332 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
&&
4333 ps
->info
.ps
.num_input_clips_culls
> 4) {
4334 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, false, false, false);
4339 for (unsigned i
= 0; i
< 32 && (1u << i
) <= ps
->info
.ps
.input_mask
; ++i
) {
4344 if (!(ps
->info
.ps
.input_mask
& (1u << i
)))
4347 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_VAR0
+ i
];
4348 if (vs_offset
== AC_EXP_PARAM_UNDEFINED
) {
4349 ps_input_cntl
[ps_offset
] = S_028644_OFFSET(0x20);
4354 flat_shade
= !!(ps
->info
.ps
.flat_shaded_mask
& (1u << ps_offset
));
4355 explicit = !!(ps
->info
.ps
.explicit_shaded_mask
& (1u << ps_offset
));
4356 float16
= !!(ps
->info
.ps
.float16_shaded_mask
& (1u << ps_offset
));
4358 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, flat_shade
, explicit, float16
);
4363 radeon_set_context_reg_seq(ctx_cs
, R_028644_SPI_PS_INPUT_CNTL_0
, ps_offset
);
4364 for (unsigned i
= 0; i
< ps_offset
; i
++) {
4365 radeon_emit(ctx_cs
, ps_input_cntl
[i
]);
4371 radv_compute_db_shader_control(const struct radv_device
*device
,
4372 const struct radv_pipeline
*pipeline
,
4373 const struct radv_shader_variant
*ps
)
4376 if (ps
->info
.ps
.early_fragment_test
|| !ps
->info
.ps
.writes_memory
)
4377 z_order
= V_02880C_EARLY_Z_THEN_LATE_Z
;
4379 z_order
= V_02880C_LATE_Z
;
4381 bool disable_rbplus
= device
->physical_device
->rad_info
.has_rbplus
&&
4382 !device
->physical_device
->rad_info
.rbplus_allowed
;
4384 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
4385 * but this appears to break Project Cars (DXVK). See
4386 * https://bugs.freedesktop.org/show_bug.cgi?id=109401
4388 bool mask_export_enable
= ps
->info
.ps
.writes_sample_mask
;
4390 return S_02880C_Z_EXPORT_ENABLE(ps
->info
.ps
.writes_z
) |
4391 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps
->info
.ps
.writes_stencil
) |
4392 S_02880C_KILL_ENABLE(!!ps
->info
.ps
.can_discard
) |
4393 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable
) |
4394 S_02880C_Z_ORDER(z_order
) |
4395 S_02880C_DEPTH_BEFORE_SHADER(ps
->info
.ps
.early_fragment_test
) |
4396 S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps
->info
.ps
.post_depth_coverage
) |
4397 S_02880C_EXEC_ON_HIER_FAIL(ps
->info
.ps
.writes_memory
) |
4398 S_02880C_EXEC_ON_NOOP(ps
->info
.ps
.writes_memory
) |
4399 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus
);
4403 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf
*ctx_cs
,
4404 struct radeon_cmdbuf
*cs
,
4405 struct radv_pipeline
*pipeline
)
4407 struct radv_shader_variant
*ps
;
4409 assert (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
4411 ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4412 va
= radv_buffer_get_va(ps
->bo
) + ps
->bo_offset
;
4414 radeon_set_sh_reg_seq(cs
, R_00B020_SPI_SHADER_PGM_LO_PS
, 4);
4415 radeon_emit(cs
, va
>> 8);
4416 radeon_emit(cs
, S_00B024_MEM_BASE(va
>> 40));
4417 radeon_emit(cs
, ps
->config
.rsrc1
);
4418 radeon_emit(cs
, ps
->config
.rsrc2
);
4420 radeon_set_context_reg(ctx_cs
, R_02880C_DB_SHADER_CONTROL
,
4421 radv_compute_db_shader_control(pipeline
->device
,
4424 radeon_set_context_reg(ctx_cs
, R_0286CC_SPI_PS_INPUT_ENA
,
4425 ps
->config
.spi_ps_input_ena
);
4427 radeon_set_context_reg(ctx_cs
, R_0286D0_SPI_PS_INPUT_ADDR
,
4428 ps
->config
.spi_ps_input_addr
);
4430 radeon_set_context_reg(ctx_cs
, R_0286D8_SPI_PS_IN_CONTROL
,
4431 S_0286D8_NUM_INTERP(ps
->info
.ps
.num_interp
) |
4432 S_0286D8_PS_W32_EN(ps
->info
.wave_size
== 32));
4434 radeon_set_context_reg(ctx_cs
, R_0286E0_SPI_BARYC_CNTL
, pipeline
->graphics
.spi_baryc_cntl
);
4436 radeon_set_context_reg(ctx_cs
, R_028710_SPI_SHADER_Z_FORMAT
,
4437 ac_get_spi_shader_z_format(ps
->info
.ps
.writes_z
,
4438 ps
->info
.ps
.writes_stencil
,
4439 ps
->info
.ps
.writes_sample_mask
));
4441 if (pipeline
->device
->dfsm_allowed
) {
4442 /* optimise this? */
4443 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
4444 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
4449 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf
*ctx_cs
,
4450 struct radv_pipeline
*pipeline
)
4452 if (pipeline
->device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
||
4453 pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
)
4456 unsigned vtx_reuse_depth
= 30;
4457 if (radv_pipeline_has_tess(pipeline
) &&
4458 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.tes
.spacing
== TESS_SPACING_FRACTIONAL_ODD
) {
4459 vtx_reuse_depth
= 14;
4461 radeon_set_context_reg(ctx_cs
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
4462 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth
));
4466 radv_compute_vgt_shader_stages_en(const struct radv_pipeline
*pipeline
)
4468 uint32_t stages
= 0;
4469 if (radv_pipeline_has_tess(pipeline
)) {
4470 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
4471 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
4473 if (radv_pipeline_has_gs(pipeline
))
4474 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
4476 else if (radv_pipeline_has_ngg(pipeline
))
4477 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
);
4479 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
4480 } else if (radv_pipeline_has_gs(pipeline
)) {
4481 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
4483 } else if (radv_pipeline_has_ngg(pipeline
)) {
4484 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
);
4487 if (radv_pipeline_has_ngg(pipeline
)) {
4488 stages
|= S_028B54_PRIMGEN_EN(1);
4489 if (pipeline
->streamout_shader
)
4490 stages
|= S_028B54_NGG_WAVE_ID_EN(1);
4491 if (radv_pipeline_has_ngg_passthrough(pipeline
))
4492 stages
|= S_028B54_PRIMGEN_PASSTHRU_EN(1);
4493 } else if (radv_pipeline_has_gs(pipeline
)) {
4494 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
4497 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
4498 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
4500 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4501 uint8_t hs_size
= 64, gs_size
= 64, vs_size
= 64;
4503 if (radv_pipeline_has_tess(pipeline
))
4504 hs_size
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.wave_size
;
4506 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
]) {
4507 vs_size
= gs_size
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.wave_size
;
4508 if (pipeline
->gs_copy_shader
)
4509 vs_size
= pipeline
->gs_copy_shader
->info
.wave_size
;
4510 } else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
4511 vs_size
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.wave_size
;
4512 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
4513 vs_size
= pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.wave_size
;
4515 if (radv_pipeline_has_ngg(pipeline
))
4518 /* legacy GS only supports Wave64 */
4519 stages
|= S_028B54_HS_W32_EN(hs_size
== 32 ? 1 : 0) |
4520 S_028B54_GS_W32_EN(gs_size
== 32 ? 1 : 0) |
4521 S_028B54_VS_W32_EN(vs_size
== 32 ? 1 : 0);
4528 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
4530 const VkPipelineDiscardRectangleStateCreateInfoEXT
*discard_rectangle_info
=
4531 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
);
4533 if (!discard_rectangle_info
)
4538 for (unsigned i
= 0; i
< (1u << MAX_DISCARD_RECTANGLES
); ++i
) {
4539 /* Interpret i as a bitmask, and then set the bit in the mask if
4540 * that combination of rectangles in which the pixel is contained
4541 * should pass the cliprect test. */
4542 unsigned relevant_subset
= i
& ((1u << discard_rectangle_info
->discardRectangleCount
) - 1);
4544 if (discard_rectangle_info
->discardRectangleMode
== VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT
&&
4548 if (discard_rectangle_info
->discardRectangleMode
== VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT
&&
4559 gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf
*ctx_cs
,
4560 struct radv_pipeline
*pipeline
,
4561 const struct radv_tessellation_state
*tess
)
4563 bool break_wave_at_eoi
= false;
4564 unsigned primgroup_size
;
4565 unsigned vertgroup_size
= 256; /* 256 = disable vertex grouping */
4567 if (radv_pipeline_has_tess(pipeline
)) {
4568 primgroup_size
= tess
->num_patches
; /* must be a multiple of NUM_PATCHES */
4569 } else if (radv_pipeline_has_gs(pipeline
)) {
4570 const struct gfx9_gs_info
*gs_state
=
4571 &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.gs_ring_info
;
4572 unsigned vgt_gs_onchip_cntl
= gs_state
->vgt_gs_onchip_cntl
;
4573 primgroup_size
= G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl
);
4575 primgroup_size
= 128; /* recommended without a GS and tess */
4578 if (radv_pipeline_has_tess(pipeline
)) {
4579 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.uses_prim_id
||
4580 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.uses_prim_id
)
4581 break_wave_at_eoi
= true;
4584 radeon_set_uconfig_reg(ctx_cs
, R_03096C_GE_CNTL
,
4585 S_03096C_PRIM_GRP_SIZE(primgroup_size
) |
4586 S_03096C_VERT_GRP_SIZE(vertgroup_size
) |
4587 S_03096C_PACKET_TO_ONE_PA(0) /* line stipple */ |
4588 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
));
4592 radv_pipeline_generate_pm4(struct radv_pipeline
*pipeline
,
4593 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
4594 const struct radv_graphics_pipeline_create_info
*extra
,
4595 const struct radv_blend_state
*blend
,
4596 const struct radv_tessellation_state
*tess
,
4597 unsigned prim
, unsigned gs_out
)
4599 struct radeon_cmdbuf
*ctx_cs
= &pipeline
->ctx_cs
;
4600 struct radeon_cmdbuf
*cs
= &pipeline
->cs
;
4603 ctx_cs
->max_dw
= 256;
4604 cs
->buf
= malloc(4 * (cs
->max_dw
+ ctx_cs
->max_dw
));
4605 ctx_cs
->buf
= cs
->buf
+ cs
->max_dw
;
4607 radv_pipeline_generate_depth_stencil_state(ctx_cs
, pipeline
, pCreateInfo
, extra
);
4608 radv_pipeline_generate_blend_state(ctx_cs
, pipeline
, blend
);
4609 radv_pipeline_generate_raster_state(ctx_cs
, pipeline
, pCreateInfo
);
4610 radv_pipeline_generate_multisample_state(ctx_cs
, pipeline
);
4611 radv_pipeline_generate_vgt_gs_mode(ctx_cs
, pipeline
);
4612 radv_pipeline_generate_vertex_shader(ctx_cs
, cs
, pipeline
, tess
);
4613 radv_pipeline_generate_tess_shaders(ctx_cs
, cs
, pipeline
, tess
);
4614 radv_pipeline_generate_geometry_shader(ctx_cs
, cs
, pipeline
);
4615 radv_pipeline_generate_fragment_shader(ctx_cs
, cs
, pipeline
);
4616 radv_pipeline_generate_ps_inputs(ctx_cs
, pipeline
);
4617 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs
, pipeline
);
4618 radv_pipeline_generate_binning_state(ctx_cs
, pipeline
, pCreateInfo
, blend
);
4620 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
&& !radv_pipeline_has_ngg(pipeline
))
4621 gfx10_pipeline_generate_ge_cntl(ctx_cs
, pipeline
, tess
);
4623 radeon_set_context_reg(ctx_cs
, R_028B54_VGT_SHADER_STAGES_EN
, radv_compute_vgt_shader_stages_en(pipeline
));
4625 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
4626 radeon_set_uconfig_reg_idx(pipeline
->device
->physical_device
,
4627 cs
, R_030908_VGT_PRIMITIVE_TYPE
, 1, prim
);
4629 radeon_set_config_reg(cs
, R_008958_VGT_PRIMITIVE_TYPE
, prim
);
4631 radeon_set_context_reg(ctx_cs
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
, gs_out
);
4633 radeon_set_context_reg(ctx_cs
, R_02820C_PA_SC_CLIPRECT_RULE
, radv_compute_cliprect_rule(pCreateInfo
));
4635 pipeline
->ctx_cs_hash
= _mesa_hash_data(ctx_cs
->buf
, ctx_cs
->cdw
* 4);
4637 assert(ctx_cs
->cdw
<= ctx_cs
->max_dw
);
4638 assert(cs
->cdw
<= cs
->max_dw
);
4641 static struct radv_ia_multi_vgt_param_helpers
4642 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline
*pipeline
,
4643 const struct radv_tessellation_state
*tess
,
4646 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param
= {0};
4647 const struct radv_device
*device
= pipeline
->device
;
4649 if (radv_pipeline_has_tess(pipeline
))
4650 ia_multi_vgt_param
.primgroup_size
= tess
->num_patches
;
4651 else if (radv_pipeline_has_gs(pipeline
))
4652 ia_multi_vgt_param
.primgroup_size
= 64;
4654 ia_multi_vgt_param
.primgroup_size
= 128; /* recommended without a GS */
4656 /* GS requirement. */
4657 ia_multi_vgt_param
.partial_es_wave
= false;
4658 if (radv_pipeline_has_gs(pipeline
) && device
->physical_device
->rad_info
.chip_class
<= GFX8
)
4659 if (SI_GS_PER_ES
/ ia_multi_vgt_param
.primgroup_size
>= pipeline
->device
->gs_table_depth
- 3)
4660 ia_multi_vgt_param
.partial_es_wave
= true;
4662 ia_multi_vgt_param
.wd_switch_on_eop
= false;
4663 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
4664 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
4665 * 4 shader engines. Set 1 to pass the assertion below.
4666 * The other cases are hardware requirements. */
4667 if (device
->physical_device
->rad_info
.max_se
< 4 ||
4668 prim
== V_008958_DI_PT_POLYGON
||
4669 prim
== V_008958_DI_PT_LINELOOP
||
4670 prim
== V_008958_DI_PT_TRIFAN
||
4671 prim
== V_008958_DI_PT_TRISTRIP_ADJ
||
4672 (pipeline
->graphics
.prim_restart_enable
&&
4673 (device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
||
4674 (prim
!= V_008958_DI_PT_POINTLIST
&&
4675 prim
!= V_008958_DI_PT_LINESTRIP
))))
4676 ia_multi_vgt_param
.wd_switch_on_eop
= true;
4679 ia_multi_vgt_param
.ia_switch_on_eoi
= false;
4680 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.prim_id_input
)
4681 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4682 if (radv_pipeline_has_gs(pipeline
) &&
4683 pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.uses_prim_id
)
4684 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4685 if (radv_pipeline_has_tess(pipeline
)) {
4686 /* SWITCH_ON_EOI must be set if PrimID is used. */
4687 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.uses_prim_id
||
4688 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.uses_prim_id
)
4689 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4692 ia_multi_vgt_param
.partial_vs_wave
= false;
4693 if (radv_pipeline_has_tess(pipeline
)) {
4694 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
4695 if ((device
->physical_device
->rad_info
.family
== CHIP_TAHITI
||
4696 device
->physical_device
->rad_info
.family
== CHIP_PITCAIRN
||
4697 device
->physical_device
->rad_info
.family
== CHIP_BONAIRE
) &&
4698 radv_pipeline_has_gs(pipeline
))
4699 ia_multi_vgt_param
.partial_vs_wave
= true;
4700 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
4701 if (device
->physical_device
->rad_info
.has_distributed_tess
) {
4702 if (radv_pipeline_has_gs(pipeline
)) {
4703 if (device
->physical_device
->rad_info
.chip_class
<= GFX8
)
4704 ia_multi_vgt_param
.partial_es_wave
= true;
4706 ia_multi_vgt_param
.partial_vs_wave
= true;
4711 /* Workaround for a VGT hang when strip primitive types are used with
4712 * primitive restart.
4714 if (pipeline
->graphics
.prim_restart_enable
&&
4715 (prim
== V_008958_DI_PT_LINESTRIP
||
4716 prim
== V_008958_DI_PT_TRISTRIP
||
4717 prim
== V_008958_DI_PT_LINESTRIP_ADJ
||
4718 prim
== V_008958_DI_PT_TRISTRIP_ADJ
)) {
4719 ia_multi_vgt_param
.partial_vs_wave
= true;
4722 if (radv_pipeline_has_gs(pipeline
)) {
4723 /* On these chips there is the possibility of a hang if the
4724 * pipeline uses a GS and partial_vs_wave is not set.
4726 * This mostly does not hit 4-SE chips, as those typically set
4727 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
4728 * with GS due to another workaround.
4730 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
4732 if (device
->physical_device
->rad_info
.family
== CHIP_TONGA
||
4733 device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
4734 device
->physical_device
->rad_info
.family
== CHIP_POLARIS10
||
4735 device
->physical_device
->rad_info
.family
== CHIP_POLARIS11
||
4736 device
->physical_device
->rad_info
.family
== CHIP_POLARIS12
||
4737 device
->physical_device
->rad_info
.family
== CHIP_VEGAM
) {
4738 ia_multi_vgt_param
.partial_vs_wave
= true;
4742 ia_multi_vgt_param
.base
=
4743 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param
.primgroup_size
- 1) |
4744 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
4745 S_028AA8_MAX_PRIMGRP_IN_WAVE(device
->physical_device
->rad_info
.chip_class
== GFX8
? 2 : 0) |
4746 S_030960_EN_INST_OPT_BASIC(device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
4747 S_030960_EN_INST_OPT_ADV(device
->physical_device
->rad_info
.chip_class
>= GFX9
);
4749 return ia_multi_vgt_param
;
4754 radv_compute_vertex_input_state(struct radv_pipeline
*pipeline
,
4755 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
4757 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
4758 pCreateInfo
->pVertexInputState
;
4759 struct radv_vertex_elements_info
*velems
= &pipeline
->vertex_elements
;
4761 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
4762 const VkVertexInputAttributeDescription
*desc
=
4763 &vi_info
->pVertexAttributeDescriptions
[i
];
4764 unsigned loc
= desc
->location
;
4765 const struct vk_format_description
*format_desc
;
4767 format_desc
= vk_format_description(desc
->format
);
4769 velems
->format_size
[loc
] = format_desc
->block
.bits
/ 8;
4772 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
4773 const VkVertexInputBindingDescription
*desc
=
4774 &vi_info
->pVertexBindingDescriptions
[i
];
4776 pipeline
->binding_stride
[desc
->binding
] = desc
->stride
;
4777 pipeline
->num_vertex_bindings
=
4778 MAX2(pipeline
->num_vertex_bindings
, desc
->binding
+ 1);
4782 static struct radv_shader_variant
*
4783 radv_pipeline_get_streamout_shader(struct radv_pipeline
*pipeline
)
4787 for (i
= MESA_SHADER_GEOMETRY
; i
>= MESA_SHADER_VERTEX
; i
--) {
4788 struct radv_shader_variant
*shader
=
4789 radv_get_shader(pipeline
, i
);
4791 if (shader
&& shader
->info
.so
.num_outputs
> 0)
4799 radv_secure_compile(struct radv_pipeline
*pipeline
,
4800 struct radv_device
*device
,
4801 const struct radv_pipeline_key
*key
,
4802 const VkPipelineShaderStageCreateInfo
**pStages
,
4803 const VkPipelineCreateFlags flags
,
4804 unsigned num_stages
)
4806 uint8_t allowed_pipeline_hashes
[2][20];
4807 radv_hash_shaders(allowed_pipeline_hashes
[0], pStages
,
4808 pipeline
->layout
, key
, get_hash_flags(device
));
4810 /* Generate the GC copy hash */
4811 memcpy(allowed_pipeline_hashes
[1], allowed_pipeline_hashes
[0], 20);
4812 allowed_pipeline_hashes
[1][0] ^= 1;
4814 uint8_t allowed_hashes
[2][20];
4815 for (unsigned i
= 0; i
< 2; ++i
) {
4816 disk_cache_compute_key(device
->physical_device
->disk_cache
,
4817 allowed_pipeline_hashes
[i
], 20,
4821 /* Do an early exit if all cache entries are already there. */
4822 bool may_need_copy_shader
= pStages
[MESA_SHADER_GEOMETRY
];
4823 void *main_entry
= disk_cache_get(device
->physical_device
->disk_cache
, allowed_hashes
[0], NULL
);
4824 void *copy_entry
= NULL
;
4825 if (may_need_copy_shader
)
4826 copy_entry
= disk_cache_get(device
->physical_device
->disk_cache
, allowed_hashes
[1], NULL
);
4828 bool has_all_cache_entries
= main_entry
&& (!may_need_copy_shader
|| copy_entry
);
4832 if(has_all_cache_entries
)
4835 unsigned process
= 0;
4836 uint8_t sc_threads
= device
->instance
->num_sc_threads
;
4838 mtx_lock(&device
->sc_state
->secure_compile_mutex
);
4839 if (device
->sc_state
->secure_compile_thread_counter
< sc_threads
) {
4840 device
->sc_state
->secure_compile_thread_counter
++;
4841 for (unsigned i
= 0; i
< sc_threads
; i
++) {
4842 if (!device
->sc_state
->secure_compile_processes
[i
].in_use
) {
4843 device
->sc_state
->secure_compile_processes
[i
].in_use
= true;
4848 mtx_unlock(&device
->sc_state
->secure_compile_mutex
);
4851 mtx_unlock(&device
->sc_state
->secure_compile_mutex
);
4854 int fd_secure_input
= device
->sc_state
->secure_compile_processes
[process
].fd_secure_input
;
4855 int fd_secure_output
= device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
;
4857 /* Fork a copy of the slim untainted secure compile process */
4858 enum radv_secure_compile_type sc_type
= RADV_SC_TYPE_FORK_DEVICE
;
4859 write(fd_secure_input
, &sc_type
, sizeof(sc_type
));
4861 if (!radv_sc_read(fd_secure_output
, &sc_type
, sizeof(sc_type
), true) ||
4862 sc_type
!= RADV_SC_TYPE_INIT_SUCCESS
)
4863 return VK_ERROR_DEVICE_LOST
;
4865 fd_secure_input
= device
->sc_state
->secure_compile_processes
[process
].fd_server
;
4866 fd_secure_output
= device
->sc_state
->secure_compile_processes
[process
].fd_client
;
4868 /* Write pipeline / shader module out to secure process via pipe */
4869 sc_type
= RADV_SC_TYPE_COMPILE_PIPELINE
;
4870 write(fd_secure_input
, &sc_type
, sizeof(sc_type
));
4872 /* Write pipeline layout out to secure process */
4873 struct radv_pipeline_layout
*layout
= pipeline
->layout
;
4874 write(fd_secure_input
, layout
, sizeof(struct radv_pipeline_layout
));
4875 write(fd_secure_input
, &layout
->num_sets
, sizeof(uint32_t));
4876 for (uint32_t set
= 0; set
< layout
->num_sets
; set
++) {
4877 write(fd_secure_input
, &layout
->set
[set
].layout
->layout_size
, sizeof(uint32_t));
4878 write(fd_secure_input
, layout
->set
[set
].layout
, layout
->set
[set
].layout
->layout_size
);
4881 /* Write pipeline key out to secure process */
4882 write(fd_secure_input
, key
, sizeof(struct radv_pipeline_key
));
4884 /* Write pipeline create flags out to secure process */
4885 write(fd_secure_input
, &flags
, sizeof(VkPipelineCreateFlags
));
4887 /* Write stage and shader information out to secure process */
4888 write(fd_secure_input
, &num_stages
, sizeof(uint32_t));
4889 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
4893 /* Write stage out to secure process */
4894 gl_shader_stage stage
= ffs(pStages
[i
]->stage
) - 1;
4895 write(fd_secure_input
, &stage
, sizeof(gl_shader_stage
));
4897 /* Write entry point name out to secure process */
4898 size_t name_size
= strlen(pStages
[i
]->pName
) + 1;
4899 write(fd_secure_input
, &name_size
, sizeof(size_t));
4900 write(fd_secure_input
, pStages
[i
]->pName
, name_size
);
4902 /* Write shader module out to secure process */
4903 struct radv_shader_module
*module
= radv_shader_module_from_handle(pStages
[i
]->module
);
4904 assert(!module
->nir
);
4905 size_t module_size
= sizeof(struct radv_shader_module
) + module
->size
;
4906 write(fd_secure_input
, &module_size
, sizeof(size_t));
4907 write(fd_secure_input
, module
, module_size
);
4909 /* Write specialization info out to secure process */
4910 const VkSpecializationInfo
*specInfo
= pStages
[i
]->pSpecializationInfo
;
4911 bool has_spec_info
= specInfo
? true : false;
4912 write(fd_secure_input
, &has_spec_info
, sizeof(bool));
4914 write(fd_secure_input
, &specInfo
->dataSize
, sizeof(size_t));
4915 write(fd_secure_input
, specInfo
->pData
, specInfo
->dataSize
);
4917 write(fd_secure_input
, &specInfo
->mapEntryCount
, sizeof(uint32_t));
4918 for (uint32_t j
= 0; j
< specInfo
->mapEntryCount
; j
++)
4919 write(fd_secure_input
, &specInfo
->pMapEntries
[j
], sizeof(VkSpecializationMapEntry
));
4923 /* Read the data returned from the secure process */
4924 while (sc_type
!= RADV_SC_TYPE_COMPILE_PIPELINE_FINISHED
) {
4925 if (!radv_sc_read(fd_secure_output
, &sc_type
, sizeof(sc_type
), true))
4926 return VK_ERROR_DEVICE_LOST
;
4928 if (sc_type
== RADV_SC_TYPE_WRITE_DISK_CACHE
) {
4929 assert(device
->physical_device
->disk_cache
);
4931 uint8_t disk_sha1
[20];
4932 if (!radv_sc_read(fd_secure_output
, disk_sha1
, sizeof(uint8_t) * 20, true))
4933 return VK_ERROR_DEVICE_LOST
;
4935 if (memcmp(disk_sha1
, allowed_hashes
[0], 20) &&
4936 memcmp(disk_sha1
, allowed_hashes
[1], 20))
4937 return VK_ERROR_DEVICE_LOST
;
4939 uint32_t entry_size
;
4940 if (!radv_sc_read(fd_secure_output
, &entry_size
, sizeof(uint32_t), true))
4941 return VK_ERROR_DEVICE_LOST
;
4943 struct cache_entry
*entry
= malloc(entry_size
);
4944 if (!radv_sc_read(fd_secure_output
, entry
, entry_size
, true))
4945 return VK_ERROR_DEVICE_LOST
;
4947 disk_cache_put(device
->physical_device
->disk_cache
,
4948 disk_sha1
, entry
, entry_size
,
4952 } else if (sc_type
== RADV_SC_TYPE_READ_DISK_CACHE
) {
4953 uint8_t disk_sha1
[20];
4954 if (!radv_sc_read(fd_secure_output
, disk_sha1
, sizeof(uint8_t) * 20, true))
4955 return VK_ERROR_DEVICE_LOST
;
4957 if (memcmp(disk_sha1
, allowed_hashes
[0], 20) &&
4958 memcmp(disk_sha1
, allowed_hashes
[1], 20))
4959 return VK_ERROR_DEVICE_LOST
;
4962 struct cache_entry
*entry
= (struct cache_entry
*)
4963 disk_cache_get(device
->physical_device
->disk_cache
,
4966 uint8_t found
= entry
? 1 : 0;
4967 write(fd_secure_input
, &found
, sizeof(uint8_t));
4970 write(fd_secure_input
, &size
, sizeof(size_t));
4971 write(fd_secure_input
, entry
, size
);
4978 sc_type
= RADV_SC_TYPE_DESTROY_DEVICE
;
4979 write(fd_secure_input
, &sc_type
, sizeof(sc_type
));
4981 mtx_lock(&device
->sc_state
->secure_compile_mutex
);
4982 device
->sc_state
->secure_compile_thread_counter
--;
4983 device
->sc_state
->secure_compile_processes
[process
].in_use
= false;
4984 mtx_unlock(&device
->sc_state
->secure_compile_mutex
);
4990 radv_pipeline_init(struct radv_pipeline
*pipeline
,
4991 struct radv_device
*device
,
4992 struct radv_pipeline_cache
*cache
,
4993 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
4994 const struct radv_graphics_pipeline_create_info
*extra
)
4997 bool has_view_index
= false;
4999 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
5000 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
5001 if (subpass
->view_mask
)
5002 has_view_index
= true;
5004 pipeline
->device
= device
;
5005 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
5006 assert(pipeline
->layout
);
5008 struct radv_blend_state blend
= radv_pipeline_init_blend_state(pipeline
, pCreateInfo
, extra
);
5010 const VkPipelineCreationFeedbackCreateInfoEXT
*creation_feedback
=
5011 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
5012 radv_init_feedback(creation_feedback
);
5014 VkPipelineCreationFeedbackEXT
*pipeline_feedback
= creation_feedback
? creation_feedback
->pPipelineCreationFeedback
: NULL
;
5016 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
5017 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
5018 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
5019 gl_shader_stage stage
= ffs(pCreateInfo
->pStages
[i
].stage
) - 1;
5020 pStages
[stage
] = &pCreateInfo
->pStages
[i
];
5021 if(creation_feedback
)
5022 stage_feedbacks
[stage
] = &creation_feedback
->pPipelineStageCreationFeedbacks
[i
];
5025 struct radv_pipeline_key key
= radv_generate_graphics_pipeline_key(pipeline
, pCreateInfo
, &blend
, has_view_index
);
5026 if (radv_device_use_secure_compile(device
->instance
)) {
5027 return radv_secure_compile(pipeline
, device
, &key
, pStages
, pCreateInfo
->flags
, pCreateInfo
->stageCount
);
5029 radv_create_shaders(pipeline
, device
, cache
, &key
, pStages
, pCreateInfo
->flags
, pipeline_feedback
, stage_feedbacks
);
5032 pipeline
->graphics
.spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
5033 radv_pipeline_init_multisample_state(pipeline
, &blend
, pCreateInfo
);
5035 uint32_t prim
= si_translate_prim(pCreateInfo
->pInputAssemblyState
->topology
);
5037 pipeline
->graphics
.topology
= pCreateInfo
->pInputAssemblyState
->topology
;
5038 pipeline
->graphics
.can_use_guardband
= radv_prim_can_use_guardband(pCreateInfo
->pInputAssemblyState
->topology
);
5040 if (radv_pipeline_has_gs(pipeline
)) {
5041 gs_out
= si_conv_gl_prim_to_gs_out(pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.gs
.output_prim
);
5042 pipeline
->graphics
.can_use_guardband
= gs_out
== V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
5043 } else if (radv_pipeline_has_tess(pipeline
)) {
5044 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.point_mode
)
5045 gs_out
= V_028A6C_OUTPRIM_TYPE_POINTLIST
;
5047 gs_out
= si_conv_gl_prim_to_gs_out(pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.primitive_mode
);
5048 pipeline
->graphics
.can_use_guardband
= gs_out
== V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
5050 gs_out
= si_conv_prim_to_gs_out(pCreateInfo
->pInputAssemblyState
->topology
);
5052 if (extra
&& extra
->use_rectlist
) {
5053 prim
= V_008958_DI_PT_RECTLIST
;
5054 gs_out
= V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
5055 pipeline
->graphics
.can_use_guardband
= true;
5056 if (radv_pipeline_has_ngg(pipeline
))
5057 gs_out
= V_028A6C_VGT_OUT_RECT_V0
;
5059 pipeline
->graphics
.prim_restart_enable
= !!pCreateInfo
->pInputAssemblyState
->primitiveRestartEnable
;
5060 /* prim vertex count will need TESS changes */
5061 pipeline
->graphics
.prim_vertex_count
= prim_size_table
[prim
];
5063 radv_pipeline_init_dynamic_state(pipeline
, pCreateInfo
);
5065 /* Ensure that some export memory is always allocated, for two reasons:
5067 * 1) Correctness: The hardware ignores the EXEC mask if no export
5068 * memory is allocated, so KILL and alpha test do not work correctly
5070 * 2) Performance: Every shader needs at least a NULL export, even when
5071 * it writes no color/depth output. The NULL export instruction
5072 * stalls without this setting.
5074 * Don't add this to CB_SHADER_MASK.
5076 * GFX10 supports pixel shaders without exports by setting both the
5077 * color and Z formats to SPI_SHADER_ZERO. The hw will skip export
5078 * instructions if any are present.
5080 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
5081 if ((pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX9
||
5082 ps
->info
.ps
.can_discard
) &&
5083 !blend
.spi_shader_col_format
) {
5084 if (!ps
->info
.ps
.writes_z
&&
5085 !ps
->info
.ps
.writes_stencil
&&
5086 !ps
->info
.ps
.writes_sample_mask
)
5087 blend
.spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
5090 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
5091 if (pipeline
->shaders
[i
]) {
5092 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[i
]->info
.need_indirect_descriptor_sets
;
5096 if (radv_pipeline_has_gs(pipeline
) && !radv_pipeline_has_ngg(pipeline
)) {
5097 struct radv_shader_variant
*gs
=
5098 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
5100 calculate_gs_ring_sizes(pipeline
, &gs
->info
.gs_ring_info
);
5103 struct radv_tessellation_state tess
= {0};
5104 if (radv_pipeline_has_tess(pipeline
)) {
5105 if (prim
== V_008958_DI_PT_PATCH
) {
5106 pipeline
->graphics
.prim_vertex_count
.min
= pCreateInfo
->pTessellationState
->patchControlPoints
;
5107 pipeline
->graphics
.prim_vertex_count
.incr
= 1;
5109 tess
= calculate_tess_state(pipeline
, pCreateInfo
);
5112 pipeline
->graphics
.ia_multi_vgt_param
= radv_compute_ia_multi_vgt_param_helpers(pipeline
, &tess
, prim
);
5114 radv_compute_vertex_input_state(pipeline
, pCreateInfo
);
5116 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++)
5117 pipeline
->user_data_0
[i
] = radv_pipeline_stage_to_user_data_0(pipeline
, i
, device
->physical_device
->rad_info
.chip_class
);
5119 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_VERTEX
,
5120 AC_UD_VS_BASE_VERTEX_START_INSTANCE
);
5121 if (loc
->sgpr_idx
!= -1) {
5122 pipeline
->graphics
.vtx_base_sgpr
= pipeline
->user_data_0
[MESA_SHADER_VERTEX
];
5123 pipeline
->graphics
.vtx_base_sgpr
+= loc
->sgpr_idx
* 4;
5124 if (radv_get_shader(pipeline
, MESA_SHADER_VERTEX
)->info
.vs
.needs_draw_id
)
5125 pipeline
->graphics
.vtx_emit_num
= 3;
5127 pipeline
->graphics
.vtx_emit_num
= 2;
5130 /* Find the last vertex shader stage that eventually uses streamout. */
5131 pipeline
->streamout_shader
= radv_pipeline_get_streamout_shader(pipeline
);
5133 result
= radv_pipeline_scratch_init(device
, pipeline
);
5134 radv_pipeline_generate_pm4(pipeline
, pCreateInfo
, extra
, &blend
, &tess
, prim
, gs_out
);
5140 radv_graphics_pipeline_create(
5142 VkPipelineCache _cache
,
5143 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
5144 const struct radv_graphics_pipeline_create_info
*extra
,
5145 const VkAllocationCallbacks
*pAllocator
,
5146 VkPipeline
*pPipeline
)
5148 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5149 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
5150 struct radv_pipeline
*pipeline
;
5153 pipeline
= vk_zalloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
5154 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5155 if (pipeline
== NULL
)
5156 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5158 result
= radv_pipeline_init(pipeline
, device
, cache
,
5159 pCreateInfo
, extra
);
5160 if (result
!= VK_SUCCESS
) {
5161 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
5165 *pPipeline
= radv_pipeline_to_handle(pipeline
);
5170 VkResult
radv_CreateGraphicsPipelines(
5172 VkPipelineCache pipelineCache
,
5174 const VkGraphicsPipelineCreateInfo
* pCreateInfos
,
5175 const VkAllocationCallbacks
* pAllocator
,
5176 VkPipeline
* pPipelines
)
5178 VkResult result
= VK_SUCCESS
;
5181 for (; i
< count
; i
++) {
5183 r
= radv_graphics_pipeline_create(_device
,
5186 NULL
, pAllocator
, &pPipelines
[i
]);
5187 if (r
!= VK_SUCCESS
) {
5189 pPipelines
[i
] = VK_NULL_HANDLE
;
5198 radv_compute_generate_pm4(struct radv_pipeline
*pipeline
)
5200 struct radv_shader_variant
*compute_shader
;
5201 struct radv_device
*device
= pipeline
->device
;
5202 unsigned threads_per_threadgroup
;
5203 unsigned threadgroups_per_cu
= 1;
5204 unsigned waves_per_threadgroup
;
5205 unsigned max_waves_per_sh
= 0;
5208 pipeline
->cs
.max_dw
= device
->physical_device
->rad_info
.chip_class
>= GFX10
? 22 : 20;
5209 pipeline
->cs
.buf
= malloc(pipeline
->cs
.max_dw
* 4);
5211 compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
5212 va
= radv_buffer_get_va(compute_shader
->bo
) + compute_shader
->bo_offset
;
5214 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B830_COMPUTE_PGM_LO
, 2);
5215 radeon_emit(&pipeline
->cs
, va
>> 8);
5216 radeon_emit(&pipeline
->cs
, S_00B834_DATA(va
>> 40));
5218 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B848_COMPUTE_PGM_RSRC1
, 2);
5219 radeon_emit(&pipeline
->cs
, compute_shader
->config
.rsrc1
);
5220 radeon_emit(&pipeline
->cs
, compute_shader
->config
.rsrc2
);
5221 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
5222 radeon_set_sh_reg(&pipeline
->cs
, R_00B8A0_COMPUTE_PGM_RSRC3
, compute_shader
->config
.rsrc3
);
5225 /* Calculate best compute resource limits. */
5226 threads_per_threadgroup
= compute_shader
->info
.cs
.block_size
[0] *
5227 compute_shader
->info
.cs
.block_size
[1] *
5228 compute_shader
->info
.cs
.block_size
[2];
5229 waves_per_threadgroup
= DIV_ROUND_UP(threads_per_threadgroup
,
5230 compute_shader
->info
.wave_size
);
5232 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
&&
5233 waves_per_threadgroup
== 1)
5234 threadgroups_per_cu
= 2;
5236 radeon_set_sh_reg(&pipeline
->cs
, R_00B854_COMPUTE_RESOURCE_LIMITS
,
5237 ac_get_compute_resource_limits(&device
->physical_device
->rad_info
,
5238 waves_per_threadgroup
,
5240 threadgroups_per_cu
));
5242 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
5243 radeon_emit(&pipeline
->cs
,
5244 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[0]));
5245 radeon_emit(&pipeline
->cs
,
5246 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[1]));
5247 radeon_emit(&pipeline
->cs
,
5248 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[2]));
5250 assert(pipeline
->cs
.cdw
<= pipeline
->cs
.max_dw
);
5253 static struct radv_pipeline_key
5254 radv_generate_compute_pipeline_key(struct radv_pipeline
*pipeline
,
5255 const VkComputePipelineCreateInfo
*pCreateInfo
)
5257 const VkPipelineShaderStageCreateInfo
*stage
= &pCreateInfo
->stage
;
5258 struct radv_pipeline_key key
;
5259 memset(&key
, 0, sizeof(key
));
5261 if (pCreateInfo
->flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
)
5262 key
.optimisations_disabled
= 1;
5264 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT
*subgroup_size
=
5265 vk_find_struct_const(stage
->pNext
,
5266 PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT
);
5268 if (subgroup_size
) {
5269 assert(subgroup_size
->requiredSubgroupSize
== 32 ||
5270 subgroup_size
->requiredSubgroupSize
== 64);
5271 key
.compute_subgroup_size
= subgroup_size
->requiredSubgroupSize
;
5277 static VkResult
radv_compute_pipeline_create(
5279 VkPipelineCache _cache
,
5280 const VkComputePipelineCreateInfo
* pCreateInfo
,
5281 const VkAllocationCallbacks
* pAllocator
,
5282 VkPipeline
* pPipeline
)
5284 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5285 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
5286 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
5287 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
5288 struct radv_pipeline
*pipeline
;
5291 pipeline
= vk_zalloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
5292 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5293 if (pipeline
== NULL
)
5294 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5296 pipeline
->device
= device
;
5297 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
5298 assert(pipeline
->layout
);
5300 const VkPipelineCreationFeedbackCreateInfoEXT
*creation_feedback
=
5301 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
5302 radv_init_feedback(creation_feedback
);
5304 VkPipelineCreationFeedbackEXT
*pipeline_feedback
= creation_feedback
? creation_feedback
->pPipelineCreationFeedback
: NULL
;
5305 if (creation_feedback
)
5306 stage_feedbacks
[MESA_SHADER_COMPUTE
] = &creation_feedback
->pPipelineStageCreationFeedbacks
[0];
5308 pStages
[MESA_SHADER_COMPUTE
] = &pCreateInfo
->stage
;
5310 struct radv_pipeline_key key
=
5311 radv_generate_compute_pipeline_key(pipeline
, pCreateInfo
);
5313 if (radv_device_use_secure_compile(device
->instance
)) {
5314 result
= radv_secure_compile(pipeline
, device
, &key
, pStages
, pCreateInfo
->flags
, 1);
5315 *pPipeline
= radv_pipeline_to_handle(pipeline
);
5319 radv_create_shaders(pipeline
, device
, cache
, &key
, pStages
, pCreateInfo
->flags
, pipeline_feedback
, stage_feedbacks
);
5322 pipeline
->user_data_0
[MESA_SHADER_COMPUTE
] = radv_pipeline_stage_to_user_data_0(pipeline
, MESA_SHADER_COMPUTE
, device
->physical_device
->rad_info
.chip_class
);
5323 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.need_indirect_descriptor_sets
;
5324 result
= radv_pipeline_scratch_init(device
, pipeline
);
5325 if (result
!= VK_SUCCESS
) {
5326 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
5330 radv_compute_generate_pm4(pipeline
);
5332 *pPipeline
= radv_pipeline_to_handle(pipeline
);
5337 VkResult
radv_CreateComputePipelines(
5339 VkPipelineCache pipelineCache
,
5341 const VkComputePipelineCreateInfo
* pCreateInfos
,
5342 const VkAllocationCallbacks
* pAllocator
,
5343 VkPipeline
* pPipelines
)
5345 VkResult result
= VK_SUCCESS
;
5348 for (; i
< count
; i
++) {
5350 r
= radv_compute_pipeline_create(_device
, pipelineCache
,
5352 pAllocator
, &pPipelines
[i
]);
5353 if (r
!= VK_SUCCESS
) {
5355 pPipelines
[i
] = VK_NULL_HANDLE
;
5363 static uint32_t radv_get_executable_count(const struct radv_pipeline
*pipeline
)
5366 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
5367 if (!pipeline
->shaders
[i
])
5370 if (i
== MESA_SHADER_GEOMETRY
&&
5371 !radv_pipeline_has_ngg(pipeline
)) {
5381 static struct radv_shader_variant
*
5382 radv_get_shader_from_executable_index(const struct radv_pipeline
*pipeline
, int index
, gl_shader_stage
*stage
)
5384 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
5385 if (!pipeline
->shaders
[i
])
5389 return pipeline
->shaders
[i
];
5394 if (i
== MESA_SHADER_GEOMETRY
&&
5395 !radv_pipeline_has_ngg(pipeline
)) {
5398 return pipeline
->gs_copy_shader
;
5408 /* Basically strlcpy (which does not exist on linux) specialized for
5410 static void desc_copy(char *desc
, const char *src
) {
5411 int len
= strlen(src
);
5412 assert(len
< VK_MAX_DESCRIPTION_SIZE
);
5413 memcpy(desc
, src
, len
);
5414 memset(desc
+ len
, 0, VK_MAX_DESCRIPTION_SIZE
- len
);
5417 VkResult
radv_GetPipelineExecutablePropertiesKHR(
5419 const VkPipelineInfoKHR
* pPipelineInfo
,
5420 uint32_t* pExecutableCount
,
5421 VkPipelineExecutablePropertiesKHR
* pProperties
)
5423 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pPipelineInfo
->pipeline
);
5424 const uint32_t total_count
= radv_get_executable_count(pipeline
);
5427 *pExecutableCount
= total_count
;
5431 const uint32_t count
= MIN2(total_count
, *pExecutableCount
);
5432 for (unsigned i
= 0, executable_idx
= 0;
5433 i
< MESA_SHADER_STAGES
&& executable_idx
< count
; ++i
) {
5434 if (!pipeline
->shaders
[i
])
5436 pProperties
[executable_idx
].stages
= mesa_to_vk_shader_stage(i
);
5437 const char *name
= NULL
;
5438 const char *description
= NULL
;
5440 case MESA_SHADER_VERTEX
:
5441 name
= "Vertex Shader";
5442 description
= "Vulkan Vertex Shader";
5444 case MESA_SHADER_TESS_CTRL
:
5445 if (!pipeline
->shaders
[MESA_SHADER_VERTEX
]) {
5446 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_VERTEX_BIT
;
5447 name
= "Vertex + Tessellation Control Shaders";
5448 description
= "Combined Vulkan Vertex and Tessellation Control Shaders";
5450 name
= "Tessellation Control Shader";
5451 description
= "Vulkan Tessellation Control Shader";
5454 case MESA_SHADER_TESS_EVAL
:
5455 name
= "Tessellation Evaluation Shader";
5456 description
= "Vulkan Tessellation Evaluation Shader";
5458 case MESA_SHADER_GEOMETRY
:
5459 if (radv_pipeline_has_tess(pipeline
) && !pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]) {
5460 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
;
5461 name
= "Tessellation Evaluation + Geometry Shaders";
5462 description
= "Combined Vulkan Tessellation Evaluation and Geometry Shaders";
5463 } else if (!radv_pipeline_has_tess(pipeline
) && !pipeline
->shaders
[MESA_SHADER_VERTEX
]) {
5464 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_VERTEX_BIT
;
5465 name
= "Vertex + Geometry Shader";
5466 description
= "Combined Vulkan Vertex and Geometry Shaders";
5468 name
= "Geometry Shader";
5469 description
= "Vulkan Geometry Shader";
5472 case MESA_SHADER_FRAGMENT
:
5473 name
= "Fragment Shader";
5474 description
= "Vulkan Fragment Shader";
5476 case MESA_SHADER_COMPUTE
:
5477 name
= "Compute Shader";
5478 description
= "Vulkan Compute Shader";
5482 pProperties
[executable_idx
].subgroupSize
= pipeline
->shaders
[i
]->info
.wave_size
;
5483 desc_copy(pProperties
[executable_idx
].name
, name
);
5484 desc_copy(pProperties
[executable_idx
].description
, description
);
5487 if (i
== MESA_SHADER_GEOMETRY
&&
5488 !radv_pipeline_has_ngg(pipeline
)) {
5489 assert(pipeline
->gs_copy_shader
);
5490 if (executable_idx
>= count
)
5493 pProperties
[executable_idx
].stages
= VK_SHADER_STAGE_GEOMETRY_BIT
;
5494 pProperties
[executable_idx
].subgroupSize
= 64;
5495 desc_copy(pProperties
[executable_idx
].name
, "GS Copy Shader");
5496 desc_copy(pProperties
[executable_idx
].description
,
5497 "Extra shader stage that loads the GS output ringbuffer into the rasterizer");
5503 VkResult result
= *pExecutableCount
< total_count
? VK_INCOMPLETE
: VK_SUCCESS
;
5504 *pExecutableCount
= count
;
5508 VkResult
radv_GetPipelineExecutableStatisticsKHR(
5510 const VkPipelineExecutableInfoKHR
* pExecutableInfo
,
5511 uint32_t* pStatisticCount
,
5512 VkPipelineExecutableStatisticKHR
* pStatistics
)
5514 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5515 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pExecutableInfo
->pipeline
);
5516 gl_shader_stage stage
;
5517 struct radv_shader_variant
*shader
= radv_get_shader_from_executable_index(pipeline
, pExecutableInfo
->executableIndex
, &stage
);
5519 enum chip_class chip_class
= device
->physical_device
->rad_info
.chip_class
;
5520 unsigned lds_increment
= chip_class
>= GFX7
? 512 : 256;
5521 unsigned max_waves
= radv_get_max_waves(device
, shader
, stage
);
5523 VkPipelineExecutableStatisticKHR
*s
= pStatistics
;
5524 VkPipelineExecutableStatisticKHR
*end
= s
+ (pStatistics
? *pStatisticCount
: 0);
5525 VkResult result
= VK_SUCCESS
;
5528 desc_copy(s
->name
, "SGPRs");
5529 desc_copy(s
->description
, "Number of SGPR registers allocated per subgroup");
5530 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5531 s
->value
.u64
= shader
->config
.num_sgprs
;
5536 desc_copy(s
->name
, "VGPRs");
5537 desc_copy(s
->description
, "Number of VGPR registers allocated per subgroup");
5538 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5539 s
->value
.u64
= shader
->config
.num_vgprs
;
5544 desc_copy(s
->name
, "Spilled SGPRs");
5545 desc_copy(s
->description
, "Number of SGPR registers spilled per subgroup");
5546 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5547 s
->value
.u64
= shader
->config
.spilled_sgprs
;
5552 desc_copy(s
->name
, "Spilled VGPRs");
5553 desc_copy(s
->description
, "Number of VGPR registers spilled per subgroup");
5554 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5555 s
->value
.u64
= shader
->config
.spilled_vgprs
;
5560 desc_copy(s
->name
, "PrivMem VGPRs");
5561 desc_copy(s
->description
, "Number of VGPRs stored in private memory per subgroup");
5562 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5563 s
->value
.u64
= shader
->info
.private_mem_vgprs
;
5568 desc_copy(s
->name
, "Code size");
5569 desc_copy(s
->description
, "Code size in bytes");
5570 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5571 s
->value
.u64
= shader
->exec_size
;
5576 desc_copy(s
->name
, "LDS size");
5577 desc_copy(s
->description
, "LDS size in bytes per workgroup");
5578 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5579 s
->value
.u64
= shader
->config
.lds_size
* lds_increment
;
5584 desc_copy(s
->name
, "Scratch size");
5585 desc_copy(s
->description
, "Private memory in bytes per subgroup");
5586 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5587 s
->value
.u64
= shader
->config
.scratch_bytes_per_wave
;
5592 desc_copy(s
->name
, "Subgroups per SIMD");
5593 desc_copy(s
->description
, "The maximum number of subgroups in flight on a SIMD unit");
5594 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5595 s
->value
.u64
= max_waves
;
5600 *pStatisticCount
= s
- pStatistics
;
5602 *pStatisticCount
= end
- pStatistics
;
5603 result
= VK_INCOMPLETE
;
5605 *pStatisticCount
= s
- pStatistics
;
5611 static VkResult
radv_copy_representation(void *data
, size_t *data_size
, const char *src
)
5613 size_t total_size
= strlen(src
) + 1;
5616 *data_size
= total_size
;
5620 size_t size
= MIN2(total_size
, *data_size
);
5622 memcpy(data
, src
, size
);
5624 *((char*)data
+ size
- 1) = 0;
5625 return size
< total_size
? VK_INCOMPLETE
: VK_SUCCESS
;
5628 VkResult
radv_GetPipelineExecutableInternalRepresentationsKHR(
5630 const VkPipelineExecutableInfoKHR
* pExecutableInfo
,
5631 uint32_t* pInternalRepresentationCount
,
5632 VkPipelineExecutableInternalRepresentationKHR
* pInternalRepresentations
)
5634 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pExecutableInfo
->pipeline
);
5635 gl_shader_stage stage
;
5636 struct radv_shader_variant
*shader
= radv_get_shader_from_executable_index(pipeline
, pExecutableInfo
->executableIndex
, &stage
);
5638 VkPipelineExecutableInternalRepresentationKHR
*p
= pInternalRepresentations
;
5639 VkPipelineExecutableInternalRepresentationKHR
*end
= p
+ (pInternalRepresentations
? *pInternalRepresentationCount
: 0);
5640 VkResult result
= VK_SUCCESS
;
5644 desc_copy(p
->name
, "NIR Shader(s)");
5645 desc_copy(p
->description
, "The optimized NIR shader(s)");
5646 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->nir_string
) != VK_SUCCESS
)
5647 result
= VK_INCOMPLETE
;
5654 if (shader
->aco_used
) {
5655 desc_copy(p
->name
, "ACO IR");
5656 desc_copy(p
->description
, "The ACO IR after some optimizations");
5658 desc_copy(p
->name
, "LLVM IR");
5659 desc_copy(p
->description
, "The LLVM IR after some optimizations");
5661 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->ir_string
) != VK_SUCCESS
)
5662 result
= VK_INCOMPLETE
;
5669 desc_copy(p
->name
, "Assembly");
5670 desc_copy(p
->description
, "Final Assembly");
5671 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->disasm_string
) != VK_SUCCESS
)
5672 result
= VK_INCOMPLETE
;
5676 if (!pInternalRepresentations
)
5677 *pInternalRepresentationCount
= p
- pInternalRepresentations
;
5679 result
= VK_INCOMPLETE
;
5680 *pInternalRepresentationCount
= end
- pInternalRepresentations
;
5682 *pInternalRepresentationCount
= p
- pInternalRepresentations
;