projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv: Expose VK_KHX_multiview.
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_private.h"
31 #include "nir/nir.h"
32 #include "nir/nir_builder.h"
33 #include "spirv/nir_spirv.h"
34
35 #include <llvm-c/Core.h>
36 #include <llvm-c/TargetMachine.h>
37
38 #include "sid.h"
39 #include "gfx9d.h"
40 #include "r600d_common.h"
41 #include "ac_binary.h"
42 #include "ac_llvm_util.h"
43 #include "ac_nir_to_llvm.h"
44 #include "vk_format.h"
45 #include "util/debug.h"
46 #include "ac_exp_param.h"
47
48 void radv_shader_variant_destroy(struct radv_device *device,
49 struct radv_shader_variant *variant);
50
51 static const struct nir_shader_compiler_options nir_options = {
52 .vertex_id_zero_based = true,
53 .lower_scmp = true,
54 .lower_flrp32 = true,
55 .lower_fsat = true,
56 .lower_fdiv = true,
57 .lower_sub = true,
58 .lower_pack_snorm_2x16 = true,
59 .lower_pack_snorm_4x8 = true,
60 .lower_pack_unorm_2x16 = true,
61 .lower_pack_unorm_4x8 = true,
62 .lower_unpack_snorm_2x16 = true,
63 .lower_unpack_snorm_4x8 = true,
64 .lower_unpack_unorm_2x16 = true,
65 .lower_unpack_unorm_4x8 = true,
66 .lower_extract_byte = true,
67 .lower_extract_word = true,
68 .max_unroll_iterations = 32
69 };
70
71 VkResult radv_CreateShaderModule(
72 VkDevice _device,
73 const VkShaderModuleCreateInfo* pCreateInfo,
74 const VkAllocationCallbacks* pAllocator,
75 VkShaderModule* pShaderModule)
76 {
77 RADV_FROM_HANDLE(radv_device, device, _device);
78 struct radv_shader_module *module;
79
80 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
81 assert(pCreateInfo->flags == 0);
82
83 module = vk_alloc2(&device->alloc, pAllocator,
84 sizeof(*module) + pCreateInfo->codeSize, 8,
85 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
86 if (module == NULL)
87 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
88
89 module->nir = NULL;
90 module->size = pCreateInfo->codeSize;
91 memcpy(module->data, pCreateInfo->pCode, module->size);
92
93 _mesa_sha1_compute(module->data, module->size, module->sha1);
94
95 *pShaderModule = radv_shader_module_to_handle(module);
96
97 return VK_SUCCESS;
98 }
99
100 void radv_DestroyShaderModule(
101 VkDevice _device,
102 VkShaderModule _module,
103 const VkAllocationCallbacks* pAllocator)
104 {
105 RADV_FROM_HANDLE(radv_device, device, _device);
106 RADV_FROM_HANDLE(radv_shader_module, module, _module);
107
108 if (!module)
109 return;
110
111 vk_free2(&device->alloc, pAllocator, module);
112 }
113
114
115 static void
116 radv_pipeline_destroy(struct radv_device *device,
117 struct radv_pipeline *pipeline,
118 const VkAllocationCallbacks* allocator)
119 {
120 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
121 if (pipeline->shaders[i])
122 radv_shader_variant_destroy(device, pipeline->shaders[i]);
123
124 if (pipeline->gs_copy_shader)
125 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
126
127 vk_free2(&device->alloc, allocator, pipeline);
128 }
129
130 void radv_DestroyPipeline(
131 VkDevice _device,
132 VkPipeline _pipeline,
133 const VkAllocationCallbacks* pAllocator)
134 {
135 RADV_FROM_HANDLE(radv_device, device, _device);
136 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
137
138 if (!_pipeline)
139 return;
140
141 radv_pipeline_destroy(device, pipeline, pAllocator);
142 }
143
144
145 static void
146 radv_optimize_nir(struct nir_shader *shader)
147 {
148 bool progress;
149
150 do {
151 progress = false;
152
153 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
154 NIR_PASS_V(shader, nir_lower_64bit_pack);
155 NIR_PASS_V(shader, nir_lower_alu_to_scalar);
156 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
157
158 NIR_PASS(progress, shader, nir_copy_prop);
159 NIR_PASS(progress, shader, nir_opt_remove_phis);
160 NIR_PASS(progress, shader, nir_opt_dce);
161 if (nir_opt_trivial_continues(shader)) {
162 progress = true;
163 NIR_PASS(progress, shader, nir_copy_prop);
164 NIR_PASS(progress, shader, nir_opt_dce);
165 }
166 NIR_PASS(progress, shader, nir_opt_if);
167 NIR_PASS(progress, shader, nir_opt_dead_cf);
168 NIR_PASS(progress, shader, nir_opt_cse);
169 NIR_PASS(progress, shader, nir_opt_peephole_select, 8);
170 NIR_PASS(progress, shader, nir_opt_algebraic);
171 NIR_PASS(progress, shader, nir_opt_constant_folding);
172 NIR_PASS(progress, shader, nir_opt_undef);
173 NIR_PASS(progress, shader, nir_opt_conditional_discard);
174 if (shader->options->max_unroll_iterations) {
175 NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
176 }
177 } while (progress);
178 }
179
180 static nir_shader *
181 radv_shader_compile_to_nir(struct radv_device *device,
182 struct radv_shader_module *module,
183 const char *entrypoint_name,
184 gl_shader_stage stage,
185 const VkSpecializationInfo *spec_info,
186 bool dump)
187 {
188 if (strcmp(entrypoint_name, "main") != 0) {
189 radv_finishme("Multiple shaders per module not really supported");
190 }
191
192 nir_shader *nir;
193 nir_function *entry_point;
194 if (module->nir) {
195 /* Some things such as our meta clear/blit code will give us a NIR
196 * shader directly. In that case, we just ignore the SPIR-V entirely
197 * and just use the NIR shader */
198 nir = module->nir;
199 nir->options = &nir_options;
200 nir_validate_shader(nir);
201
202 assert(exec_list_length(&nir->functions) == 1);
203 struct exec_node *node = exec_list_get_head(&nir->functions);
204 entry_point = exec_node_data(nir_function, node, node);
205 } else {
206 uint32_t *spirv = (uint32_t *) module->data;
207 assert(module->size % 4 == 0);
208
209 uint32_t num_spec_entries = 0;
210 struct nir_spirv_specialization *spec_entries = NULL;
211 if (spec_info && spec_info->mapEntryCount > 0) {
212 num_spec_entries = spec_info->mapEntryCount;
213 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
214 for (uint32_t i = 0; i < num_spec_entries; i++) {
215 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
216 const void *data = spec_info->pData + entry.offset;
217 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
218
219 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
220 if (spec_info->dataSize == 8)
221 spec_entries[i].data64 = *(const uint64_t *)data;
222 else
223 spec_entries[i].data32 = *(const uint32_t *)data;
224 }
225 }
226 const struct nir_spirv_supported_extensions supported_ext = {
227 .draw_parameters = true,
228 .float64 = true,
229 .image_read_without_format = true,
230 .image_write_without_format = true,
231 .tessellation = true,
232 .int64 = true,
233 .multiview = true,
234 .variable_pointers = true,
235 };
236 entry_point = spirv_to_nir(spirv, module->size / 4,
237 spec_entries, num_spec_entries,
238 stage, entrypoint_name, &supported_ext, &nir_options);
239 nir = entry_point->shader;
240 assert(nir->stage == stage);
241 nir_validate_shader(nir);
242
243 free(spec_entries);
244
245 /* We have to lower away local constant initializers right before we
246 * inline functions. That way they get properly initialized at the top
247 * of the function and not at the top of its caller.
248 */
249 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_local);
250 NIR_PASS_V(nir, nir_lower_returns);
251 NIR_PASS_V(nir, nir_inline_functions);
252
253 /* Pick off the single entrypoint that we want */
254 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
255 if (func != entry_point)
256 exec_node_remove(&func->node);
257 }
258 assert(exec_list_length(&nir->functions) == 1);
259 entry_point->name = ralloc_strdup(entry_point, "main");
260
261 NIR_PASS_V(nir, nir_remove_dead_variables,
262 nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
263
264 /* Now that we've deleted all but the main function, we can go ahead and
265 * lower the rest of the constant initializers.
266 */
267 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
268 NIR_PASS_V(nir, nir_lower_system_values);
269 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
270 }
271
272 /* Vulkan uses the separate-shader linking model */
273 nir->info.separate_shader = true;
274
275 nir_shader_gather_info(nir, entry_point->impl);
276
277 nir_variable_mode indirect_mask = 0;
278 indirect_mask |= nir_var_shader_in;
279 indirect_mask |= nir_var_local;
280
281 nir_lower_indirect_derefs(nir, indirect_mask);
282
283 static const nir_lower_tex_options tex_options = {
284 .lower_txp = ~0,
285 };
286
287 nir_lower_tex(nir, &tex_options);
288
289 nir_lower_vars_to_ssa(nir);
290 nir_lower_var_copies(nir);
291 nir_lower_global_vars_to_local(nir);
292 nir_remove_dead_variables(nir, nir_var_local);
293 radv_optimize_nir(nir);
294
295 if (dump)
296 nir_print_shader(nir, stderr);
297
298 return nir;
299 }
300
301 static const char *radv_get_shader_name(struct radv_shader_variant *var,
302 gl_shader_stage stage)
303 {
304 switch (stage) {
305 case MESA_SHADER_VERTEX: return var->info.vs.as_ls ? "Vertex Shader as LS" : var->info.vs.as_es ? "Vertex Shader as ES" : "Vertex Shader as VS";
306 case MESA_SHADER_GEOMETRY: return "Geometry Shader";
307 case MESA_SHADER_FRAGMENT: return "Pixel Shader";
308 case MESA_SHADER_COMPUTE: return "Compute Shader";
309 case MESA_SHADER_TESS_CTRL: return "Tessellation Control Shader";
310 case MESA_SHADER_TESS_EVAL: return var->info.tes.as_es ? "Tessellation Evaluation Shader as ES" : "Tessellation Evaluation Shader as VS";
311 default:
312 return "Unknown shader";
313 };
314
315 }
316 static void radv_dump_pipeline_stats(struct radv_device *device, struct radv_pipeline *pipeline)
317 {
318 unsigned lds_increment = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
319 struct radv_shader_variant *var;
320 struct ac_shader_config *conf;
321 int i;
322 FILE *file = stderr;
323 unsigned max_simd_waves = 10;
324 unsigned lds_per_wave = 0;
325
326 for (i = 0; i < MESA_SHADER_STAGES; i++) {
327 if (!pipeline->shaders[i])
328 continue;
329 var = pipeline->shaders[i];
330
331 conf = &var->config;
332
333 if (i == MESA_SHADER_FRAGMENT) {
334 lds_per_wave = conf->lds_size * lds_increment +
335 align(var->info.fs.num_interp * 48, lds_increment);
336 }
337
338 if (conf->num_sgprs) {
339 if (device->physical_device->rad_info.chip_class >= VI)
340 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
341 else
342 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
343 }
344
345 if (conf->num_vgprs)
346 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
347
348 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
349 * that PS can use.
350 */
351 if (lds_per_wave)
352 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
353
354 fprintf(file, "\n%s:\n",
355 radv_get_shader_name(var, i));
356 if (i == MESA_SHADER_FRAGMENT) {
357 fprintf(file, "*** SHADER CONFIG ***\n"
358 "SPI_PS_INPUT_ADDR = 0x%04x\n"
359 "SPI_PS_INPUT_ENA = 0x%04x\n",
360 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
361 }
362 fprintf(file, "*** SHADER STATS ***\n"
363 "SGPRS: %d\n"
364 "VGPRS: %d\n"
365 "Spilled SGPRs: %d\n"
366 "Spilled VGPRs: %d\n"
367 "Code Size: %d bytes\n"
368 "LDS: %d blocks\n"
369 "Scratch: %d bytes per wave\n"
370 "Max Waves: %d\n"
371 "********************\n\n\n",
372 conf->num_sgprs, conf->num_vgprs,
373 conf->spilled_sgprs, conf->spilled_vgprs, var->code_size,
374 conf->lds_size, conf->scratch_bytes_per_wave,
375 max_simd_waves);
376 }
377 }
378
379 void radv_shader_variant_destroy(struct radv_device *device,
380 struct radv_shader_variant *variant)
381 {
382 if (!p_atomic_dec_zero(&variant->ref_count))
383 return;
384
385 mtx_lock(&device->shader_slab_mutex);
386 list_del(&variant->slab_list);
387 mtx_unlock(&device->shader_slab_mutex);
388
389 free(variant);
390 }
391
392 static void radv_fill_shader_variant(struct radv_device *device,
393 struct radv_shader_variant *variant,
394 struct ac_shader_binary *binary,
395 gl_shader_stage stage)
396 {
397 bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0;
398 unsigned vgpr_comp_cnt = 0;
399
400 if (scratch_enabled && !device->llvm_supports_spill)
401 radv_finishme("shader scratch support only available with LLVM 4.0");
402
403 variant->code_size = binary->code_size;
404 variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
405 S_00B12C_SCRATCH_EN(scratch_enabled);
406
407 switch (stage) {
408 case MESA_SHADER_TESS_EVAL:
409 vgpr_comp_cnt = 3;
410 /* fallthrough */
411 case MESA_SHADER_TESS_CTRL:
412 variant->rsrc2 |= S_00B42C_OC_LDS_EN(1);
413 break;
414 case MESA_SHADER_VERTEX:
415 case MESA_SHADER_GEOMETRY:
416 vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
417 break;
418 case MESA_SHADER_FRAGMENT:
419 break;
420 case MESA_SHADER_COMPUTE:
421 variant->rsrc2 |=
422 S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) |
423 S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) |
424 S_00B84C_TG_SIZE_EN(1) |
425 S_00B84C_LDS_SIZE(variant->config.lds_size);
426 break;
427 default:
428 unreachable("unsupported shader type");
429 break;
430 }
431
432 variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
433 S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) |
434 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
435 S_00B848_DX10_CLAMP(1) |
436 S_00B848_FLOAT_MODE(variant->config.float_mode);
437
438 void *ptr = radv_alloc_shader_memory(device, variant);
439 memcpy(ptr, binary->code, binary->code_size);
440 }
441
442 static struct radv_shader_variant *radv_shader_variant_create(struct radv_device *device,
443 struct nir_shader *shader,
444 struct radv_pipeline_layout *layout,
445 const struct ac_shader_variant_key *key,
446 void** code_out,
447 unsigned *code_size_out,
448 bool dump)
449 {
450 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
451 enum radeon_family chip_family = device->physical_device->rad_info.family;
452 LLVMTargetMachineRef tm;
453 if (!variant)
454 return NULL;
455
456 struct ac_nir_compiler_options options = {0};
457 options.layout = layout;
458 if (key)
459 options.key = *key;
460
461 struct ac_shader_binary binary;
462 enum ac_target_machine_options tm_options = 0;
463 options.unsafe_math = !!(device->debug_flags & RADV_DEBUG_UNSAFE_MATH);
464 options.family = chip_family;
465 options.chip_class = device->physical_device->rad_info.chip_class;
466 options.supports_spill = device->llvm_supports_spill;
467 if (options.supports_spill)
468 tm_options |= AC_TM_SUPPORTS_SPILL;
469 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
470 tm_options |= AC_TM_SISCHED;
471 tm = ac_create_target_machine(chip_family, tm_options);
472 ac_compile_nir_shader(tm, &binary, &variant->config,
473 &variant->info, shader, &options, dump);
474 LLVMDisposeTargetMachine(tm);
475
476 radv_fill_shader_variant(device, variant, &binary, shader->stage);
477
478 if (code_out) {
479 *code_out = binary.code;
480 *code_size_out = binary.code_size;
481 } else
482 free(binary.code);
483 free(binary.config);
484 free(binary.rodata);
485 free(binary.global_symbol_offsets);
486 free(binary.relocs);
487 free(binary.disasm_string);
488 variant->ref_count = 1;
489 return variant;
490 }
491
492 static struct radv_shader_variant *
493 radv_pipeline_create_gs_copy_shader(struct radv_pipeline *pipeline,
494 struct nir_shader *nir,
495 void** code_out,
496 unsigned *code_size_out,
497 bool dump_shader,
498 bool multiview)
499 {
500 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
501 enum radeon_family chip_family = pipeline->device->physical_device->rad_info.family;
502 LLVMTargetMachineRef tm;
503 if (!variant)
504 return NULL;
505
506 struct ac_nir_compiler_options options = {0};
507 struct ac_shader_binary binary;
508 enum ac_target_machine_options tm_options = 0;
509 options.family = chip_family;
510 options.chip_class = pipeline->device->physical_device->rad_info.chip_class;
511 options.key.has_multiview_view_index = multiview;
512 if (options.supports_spill)
513 tm_options |= AC_TM_SUPPORTS_SPILL;
514 if (pipeline->device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
515 tm_options |= AC_TM_SISCHED;
516 tm = ac_create_target_machine(chip_family, tm_options);
517 ac_create_gs_copy_shader(tm, nir, &binary, &variant->config, &variant->info, &options, dump_shader);
518 LLVMDisposeTargetMachine(tm);
519
520 radv_fill_shader_variant(pipeline->device, variant, &binary, MESA_SHADER_VERTEX);
521
522 if (code_out) {
523 *code_out = binary.code;
524 *code_size_out = binary.code_size;
525 } else
526 free(binary.code);
527 free(binary.config);
528 free(binary.rodata);
529 free(binary.global_symbol_offsets);
530 free(binary.relocs);
531 free(binary.disasm_string);
532 variant->ref_count = 1;
533 return variant;
534 }
535
536 static struct radv_shader_variant *
537 radv_pipeline_compile(struct radv_pipeline *pipeline,
538 struct radv_pipeline_cache *cache,
539 struct radv_shader_module *module,
540 const char *entrypoint,
541 gl_shader_stage stage,
542 const VkSpecializationInfo *spec_info,
543 struct radv_pipeline_layout *layout,
544 const struct ac_shader_variant_key *key)
545 {
546 unsigned char sha1[20];
547 unsigned char gs_copy_sha1[20];
548 struct radv_shader_variant *variant;
549 nir_shader *nir;
550 void *code = NULL;
551 unsigned code_size = 0;
552 bool dump = (pipeline->device->debug_flags & RADV_DEBUG_DUMP_SHADERS);
553
554 if (module->nir)
555 _mesa_sha1_compute(module->nir->info.name,
556 strlen(module->nir->info.name),
557 module->sha1);
558
559 radv_hash_shader(sha1, module, entrypoint, spec_info, layout, key, 0);
560 if (stage == MESA_SHADER_GEOMETRY)
561 radv_hash_shader(gs_copy_sha1, module, entrypoint, spec_info,
562 layout, key, 1);
563
564 variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
565 cache,
566 sha1);
567
568 if (stage == MESA_SHADER_GEOMETRY) {
569 pipeline->gs_copy_shader =
570 radv_create_shader_variant_from_pipeline_cache(
571 pipeline->device,
572 cache,
573 gs_copy_sha1);
574 }
575
576 if (variant &&
577 (stage != MESA_SHADER_GEOMETRY || pipeline->gs_copy_shader))
578 return variant;
579
580 nir = radv_shader_compile_to_nir(pipeline->device,
581 module, entrypoint, stage,
582 spec_info, dump);
583 if (nir == NULL)
584 return NULL;
585
586 if (!variant) {
587 variant = radv_shader_variant_create(pipeline->device, nir,
588 layout, key, &code,
589 &code_size, dump);
590 }
591
592 if (stage == MESA_SHADER_GEOMETRY && !pipeline->gs_copy_shader) {
593 void *gs_copy_code = NULL;
594 unsigned gs_copy_code_size = 0;
595 pipeline->gs_copy_shader = radv_pipeline_create_gs_copy_shader(
596 pipeline, nir, &gs_copy_code, &gs_copy_code_size, dump, key->has_multiview_view_index);
597
598 if (pipeline->gs_copy_shader) {
599 pipeline->gs_copy_shader =
600 radv_pipeline_cache_insert_shader(cache,
601 gs_copy_sha1,
602 pipeline->gs_copy_shader,
603 gs_copy_code,
604 gs_copy_code_size);
605 }
606 }
607 if (!module->nir)
608 ralloc_free(nir);
609
610 if (variant)
611 variant = radv_pipeline_cache_insert_shader(cache, sha1, variant,
612 code, code_size);
613
614 if (code)
615 free(code);
616 return variant;
617 }
618
619 static struct ac_shader_variant_key
620 radv_compute_tes_key(bool as_es, bool export_prim_id)
621 {
622 struct ac_shader_variant_key key;
623 memset(&key, 0, sizeof(key));
624 key.tes.as_es = as_es;
625 /* export prim id only happens when no geom shader */
626 if (!as_es)
627 key.tes.export_prim_id = export_prim_id;
628 return key;
629 }
630
631 static struct ac_shader_variant_key
632 radv_compute_tcs_key(unsigned primitive_mode, unsigned input_vertices)
633 {
634 struct ac_shader_variant_key key;
635 memset(&key, 0, sizeof(key));
636 key.tcs.primitive_mode = primitive_mode;
637 key.tcs.input_vertices = input_vertices;
638 return key;
639 }
640
641 static void
642 radv_tess_pipeline_compile(struct radv_pipeline *pipeline,
643 struct radv_pipeline_cache *cache,
644 struct radv_shader_module *tcs_module,
645 struct radv_shader_module *tes_module,
646 const char *tcs_entrypoint,
647 const char *tes_entrypoint,
648 const VkSpecializationInfo *tcs_spec_info,
649 const VkSpecializationInfo *tes_spec_info,
650 struct radv_pipeline_layout *layout,
651 unsigned input_vertices,
652 bool has_view_index)
653 {
654 unsigned char tcs_sha1[20], tes_sha1[20];
655 struct radv_shader_variant *tes_variant = NULL, *tcs_variant = NULL;
656 nir_shader *tes_nir, *tcs_nir;
657 void *tes_code = NULL, *tcs_code = NULL;
658 unsigned tes_code_size = 0, tcs_code_size = 0;
659 struct ac_shader_variant_key tes_key;
660 struct ac_shader_variant_key tcs_key;
661 bool dump = (pipeline->device->debug_flags & RADV_DEBUG_DUMP_SHADERS);
662
663 tes_key = radv_compute_tes_key(radv_pipeline_has_gs(pipeline),
664 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input);
665 tes_key.has_multiview_view_index = has_view_index;
666 if (tes_module->nir)
667 _mesa_sha1_compute(tes_module->nir->info.name,
668 strlen(tes_module->nir->info.name),
669 tes_module->sha1);
670 radv_hash_shader(tes_sha1, tes_module, tes_entrypoint, tes_spec_info, layout, &tes_key, 0);
671
672 tes_variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
673 cache,
674 tes_sha1);
675
676 if (tes_variant) {
677 tcs_key = radv_compute_tcs_key(tes_variant->info.tes.primitive_mode, input_vertices);
678
679 if (tcs_module->nir)
680 _mesa_sha1_compute(tcs_module->nir->info.name,
681 strlen(tcs_module->nir->info.name),
682 tcs_module->sha1);
683
684 radv_hash_shader(tcs_sha1, tcs_module, tcs_entrypoint, tcs_spec_info, layout, &tcs_key, 0);
685
686 tcs_variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
687 cache,
688 tcs_sha1);
689 }
690
691 if (tcs_variant && tes_variant) {
692 pipeline->shaders[MESA_SHADER_TESS_CTRL] = tcs_variant;
693 pipeline->shaders[MESA_SHADER_TESS_EVAL] = tes_variant;
694 return;
695 }
696
697 tes_nir = radv_shader_compile_to_nir(pipeline->device,
698 tes_module, tes_entrypoint, MESA_SHADER_TESS_EVAL,
699 tes_spec_info, dump);
700 if (tes_nir == NULL)
701 return;
702
703 tcs_nir = radv_shader_compile_to_nir(pipeline->device,
704 tcs_module, tcs_entrypoint, MESA_SHADER_TESS_CTRL,
705 tcs_spec_info, dump);
706 if (tcs_nir == NULL)
707 return;
708
709 nir_lower_tes_patch_vertices(tes_nir,
710 tcs_nir->info.tess.tcs_vertices_out);
711
712 tes_variant = radv_shader_variant_create(pipeline->device, tes_nir,
713 layout, &tes_key, &tes_code,
714 &tes_code_size, dump);
715
716 tcs_key = radv_compute_tcs_key(tes_nir->info.tess.primitive_mode, input_vertices);
717 if (tcs_module->nir)
718 _mesa_sha1_compute(tcs_module->nir->info.name,
719 strlen(tcs_module->nir->info.name),
720 tcs_module->sha1);
721
722 radv_hash_shader(tcs_sha1, tcs_module, tcs_entrypoint, tcs_spec_info, layout, &tcs_key, 0);
723
724 tcs_variant = radv_shader_variant_create(pipeline->device, tcs_nir,
725 layout, &tcs_key, &tcs_code,
726 &tcs_code_size, dump);
727
728 if (!tes_module->nir)
729 ralloc_free(tes_nir);
730
731 if (!tcs_module->nir)
732 ralloc_free(tcs_nir);
733
734 if (tes_variant)
735 tes_variant = radv_pipeline_cache_insert_shader(cache, tes_sha1, tes_variant,
736 tes_code, tes_code_size);
737
738 if (tcs_variant)
739 tcs_variant = radv_pipeline_cache_insert_shader(cache, tcs_sha1, tcs_variant,
740 tcs_code, tcs_code_size);
741
742 if (tes_code)
743 free(tes_code);
744 if (tcs_code)
745 free(tcs_code);
746 pipeline->shaders[MESA_SHADER_TESS_CTRL] = tcs_variant;
747 pipeline->shaders[MESA_SHADER_TESS_EVAL] = tes_variant;
748 return;
749 }
750
751 static VkResult
752 radv_pipeline_scratch_init(struct radv_device *device,
753 struct radv_pipeline *pipeline)
754 {
755 unsigned scratch_bytes_per_wave = 0;
756 unsigned max_waves = 0;
757 unsigned min_waves = 1;
758
759 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
760 if (pipeline->shaders[i]) {
761 unsigned max_stage_waves = device->scratch_waves;
762
763 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
764 pipeline->shaders[i]->config.scratch_bytes_per_wave);
765
766 max_stage_waves = MIN2(max_stage_waves,
767 4 * device->physical_device->rad_info.num_good_compute_units *
768 (256 / pipeline->shaders[i]->config.num_vgprs));
769 max_waves = MAX2(max_waves, max_stage_waves);
770 }
771 }
772
773 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
774 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
775 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
776 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
777 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
778 }
779
780 if (scratch_bytes_per_wave)
781 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
782
783 if (scratch_bytes_per_wave && max_waves < min_waves) {
784 /* Not really true at this moment, but will be true on first
785 * execution. Avoid having hanging shaders. */
786 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
787 }
788 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
789 pipeline->max_waves = max_waves;
790 return VK_SUCCESS;
791 }
792
793 static uint32_t si_translate_blend_function(VkBlendOp op)
794 {
795 switch (op) {
796 case VK_BLEND_OP_ADD:
797 return V_028780_COMB_DST_PLUS_SRC;
798 case VK_BLEND_OP_SUBTRACT:
799 return V_028780_COMB_SRC_MINUS_DST;
800 case VK_BLEND_OP_REVERSE_SUBTRACT:
801 return V_028780_COMB_DST_MINUS_SRC;
802 case VK_BLEND_OP_MIN:
803 return V_028780_COMB_MIN_DST_SRC;
804 case VK_BLEND_OP_MAX:
805 return V_028780_COMB_MAX_DST_SRC;
806 default:
807 return 0;
808 }
809 }
810
811 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
812 {
813 switch (factor) {
814 case VK_BLEND_FACTOR_ZERO:
815 return V_028780_BLEND_ZERO;
816 case VK_BLEND_FACTOR_ONE:
817 return V_028780_BLEND_ONE;
818 case VK_BLEND_FACTOR_SRC_COLOR:
819 return V_028780_BLEND_SRC_COLOR;
820 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
821 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
822 case VK_BLEND_FACTOR_DST_COLOR:
823 return V_028780_BLEND_DST_COLOR;
824 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
825 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
826 case VK_BLEND_FACTOR_SRC_ALPHA:
827 return V_028780_BLEND_SRC_ALPHA;
828 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
829 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
830 case VK_BLEND_FACTOR_DST_ALPHA:
831 return V_028780_BLEND_DST_ALPHA;
832 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
833 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
834 case VK_BLEND_FACTOR_CONSTANT_COLOR:
835 return V_028780_BLEND_CONSTANT_COLOR;
836 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
837 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
838 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
839 return V_028780_BLEND_CONSTANT_ALPHA;
840 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
841 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
842 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
843 return V_028780_BLEND_SRC_ALPHA_SATURATE;
844 case VK_BLEND_FACTOR_SRC1_COLOR:
845 return V_028780_BLEND_SRC1_COLOR;
846 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
847 return V_028780_BLEND_INV_SRC1_COLOR;
848 case VK_BLEND_FACTOR_SRC1_ALPHA:
849 return V_028780_BLEND_SRC1_ALPHA;
850 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
851 return V_028780_BLEND_INV_SRC1_ALPHA;
852 default:
853 return 0;
854 }
855 }
856
857 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
858 {
859 switch (op) {
860 case VK_BLEND_OP_ADD:
861 return V_028760_OPT_COMB_ADD;
862 case VK_BLEND_OP_SUBTRACT:
863 return V_028760_OPT_COMB_SUBTRACT;
864 case VK_BLEND_OP_REVERSE_SUBTRACT:
865 return V_028760_OPT_COMB_REVSUBTRACT;
866 case VK_BLEND_OP_MIN:
867 return V_028760_OPT_COMB_MIN;
868 case VK_BLEND_OP_MAX:
869 return V_028760_OPT_COMB_MAX;
870 default:
871 return V_028760_OPT_COMB_BLEND_DISABLED;
872 }
873 }
874
875 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
876 {
877 switch (factor) {
878 case VK_BLEND_FACTOR_ZERO:
879 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
880 case VK_BLEND_FACTOR_ONE:
881 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
882 case VK_BLEND_FACTOR_SRC_COLOR:
883 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
884 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
885 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
886 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
887 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
888 case VK_BLEND_FACTOR_SRC_ALPHA:
889 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
890 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
891 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
892 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
893 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
894 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
895 default:
896 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
897 }
898 }
899
900 /**
901 * Get rid of DST in the blend factors by commuting the operands:
902 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
903 */
904 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
905 unsigned *dst_factor, unsigned expected_dst,
906 unsigned replacement_src)
907 {
908 if (*src_factor == expected_dst &&
909 *dst_factor == VK_BLEND_FACTOR_ZERO) {
910 *src_factor = VK_BLEND_FACTOR_ZERO;
911 *dst_factor = replacement_src;
912
913 /* Commuting the operands requires reversing subtractions. */
914 if (*func == VK_BLEND_OP_SUBTRACT)
915 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
916 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
917 *func = VK_BLEND_OP_SUBTRACT;
918 }
919 }
920
921 static bool si_blend_factor_uses_dst(unsigned factor)
922 {
923 return factor == VK_BLEND_FACTOR_DST_COLOR ||
924 factor == VK_BLEND_FACTOR_DST_ALPHA ||
925 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
926 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
927 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
928 }
929
930 static bool is_dual_src(VkBlendFactor factor)
931 {
932 switch (factor) {
933 case VK_BLEND_FACTOR_SRC1_COLOR:
934 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
935 case VK_BLEND_FACTOR_SRC1_ALPHA:
936 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
937 return true;
938 default:
939 return false;
940 }
941 }
942
943 static unsigned si_choose_spi_color_format(VkFormat vk_format,
944 bool blend_enable,
945 bool blend_need_alpha)
946 {
947 const struct vk_format_description *desc = vk_format_description(vk_format);
948 unsigned format, ntype, swap;
949
950 /* Alpha is needed for alpha-to-coverage.
951 * Blending may be with or without alpha.
952 */
953 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
954 unsigned alpha = 0; /* exports alpha, but may not support blending */
955 unsigned blend = 0; /* supports blending, but may not export alpha */
956 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
957
958 format = radv_translate_colorformat(vk_format);
959 ntype = radv_translate_color_numformat(vk_format, desc,
960 vk_format_get_first_non_void_channel(vk_format));
961 swap = radv_translate_colorswap(vk_format, false);
962
963 /* Choose the SPI color formats. These are required values for Stoney/RB+.
964 * Other chips have multiple choices, though they are not necessarily better.
965 */
966 switch (format) {
967 case V_028C70_COLOR_5_6_5:
968 case V_028C70_COLOR_1_5_5_5:
969 case V_028C70_COLOR_5_5_5_1:
970 case V_028C70_COLOR_4_4_4_4:
971 case V_028C70_COLOR_10_11_11:
972 case V_028C70_COLOR_11_11_10:
973 case V_028C70_COLOR_8:
974 case V_028C70_COLOR_8_8:
975 case V_028C70_COLOR_8_8_8_8:
976 case V_028C70_COLOR_10_10_10_2:
977 case V_028C70_COLOR_2_10_10_10:
978 if (ntype == V_028C70_NUMBER_UINT)
979 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
980 else if (ntype == V_028C70_NUMBER_SINT)
981 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
982 else
983 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
984 break;
985
986 case V_028C70_COLOR_16:
987 case V_028C70_COLOR_16_16:
988 case V_028C70_COLOR_16_16_16_16:
989 if (ntype == V_028C70_NUMBER_UNORM ||
990 ntype == V_028C70_NUMBER_SNORM) {
991 /* UNORM16 and SNORM16 don't support blending */
992 if (ntype == V_028C70_NUMBER_UNORM)
993 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
994 else
995 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
996
997 /* Use 32 bits per channel for blending. */
998 if (format == V_028C70_COLOR_16) {
999 if (swap == V_028C70_SWAP_STD) { /* R */
1000 blend = V_028714_SPI_SHADER_32_R;
1001 blend_alpha = V_028714_SPI_SHADER_32_AR;
1002 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
1003 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
1004 else
1005 assert(0);
1006 } else if (format == V_028C70_COLOR_16_16) {
1007 if (swap == V_028C70_SWAP_STD) { /* RG */
1008 blend = V_028714_SPI_SHADER_32_GR;
1009 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1010 } else if (swap == V_028C70_SWAP_ALT) /* RA */
1011 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
1012 else
1013 assert(0);
1014 } else /* 16_16_16_16 */
1015 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1016 } else if (ntype == V_028C70_NUMBER_UINT)
1017 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
1018 else if (ntype == V_028C70_NUMBER_SINT)
1019 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
1020 else if (ntype == V_028C70_NUMBER_FLOAT)
1021 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
1022 else
1023 assert(0);
1024 break;
1025
1026 case V_028C70_COLOR_32:
1027 if (swap == V_028C70_SWAP_STD) { /* R */
1028 blend = normal = V_028714_SPI_SHADER_32_R;
1029 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
1030 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
1031 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
1032 else
1033 assert(0);
1034 break;
1035
1036 case V_028C70_COLOR_32_32:
1037 if (swap == V_028C70_SWAP_STD) { /* RG */
1038 blend = normal = V_028714_SPI_SHADER_32_GR;
1039 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1040 } else if (swap == V_028C70_SWAP_ALT) /* RA */
1041 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
1042 else
1043 assert(0);
1044 break;
1045
1046 case V_028C70_COLOR_32_32_32_32:
1047 case V_028C70_COLOR_8_24:
1048 case V_028C70_COLOR_24_8:
1049 case V_028C70_COLOR_X24_8_32_FLOAT:
1050 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
1051 break;
1052
1053 default:
1054 unreachable("unhandled blend format");
1055 }
1056
1057 if (blend_enable && blend_need_alpha)
1058 return blend_alpha;
1059 else if(blend_need_alpha)
1060 return alpha;
1061 else if(blend_enable)
1062 return blend;
1063 else
1064 return normal;
1065 }
1066
1067 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
1068 {
1069 unsigned i, cb_shader_mask = 0;
1070
1071 for (i = 0; i < 8; i++) {
1072 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
1073 case V_028714_SPI_SHADER_ZERO:
1074 break;
1075 case V_028714_SPI_SHADER_32_R:
1076 cb_shader_mask |= 0x1 << (i * 4);
1077 break;
1078 case V_028714_SPI_SHADER_32_GR:
1079 cb_shader_mask |= 0x3 << (i * 4);
1080 break;
1081 case V_028714_SPI_SHADER_32_AR:
1082 cb_shader_mask |= 0x9 << (i * 4);
1083 break;
1084 case V_028714_SPI_SHADER_FP16_ABGR:
1085 case V_028714_SPI_SHADER_UNORM16_ABGR:
1086 case V_028714_SPI_SHADER_SNORM16_ABGR:
1087 case V_028714_SPI_SHADER_UINT16_ABGR:
1088 case V_028714_SPI_SHADER_SINT16_ABGR:
1089 case V_028714_SPI_SHADER_32_ABGR:
1090 cb_shader_mask |= 0xf << (i * 4);
1091 break;
1092 default:
1093 assert(0);
1094 }
1095 }
1096 return cb_shader_mask;
1097 }
1098
1099 static void
1100 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
1101 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1102 uint32_t blend_enable,
1103 uint32_t blend_need_alpha,
1104 bool single_cb_enable,
1105 bool blend_mrt0_is_dual_src)
1106 {
1107 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1108 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
1109 struct radv_blend_state *blend = &pipeline->graphics.blend;
1110 unsigned col_format = 0;
1111
1112 for (unsigned i = 0; i < (single_cb_enable ? 1 : subpass->color_count); ++i) {
1113 unsigned cf;
1114
1115 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1116 cf = V_028714_SPI_SHADER_ZERO;
1117 } else {
1118 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
1119
1120 cf = si_choose_spi_color_format(attachment->format,
1121 blend_enable & (1 << i),
1122 blend_need_alpha & (1 << i));
1123 }
1124
1125 col_format |= cf << (4 * i);
1126 }
1127
1128 blend->cb_shader_mask = si_get_cb_shader_mask(col_format);
1129
1130 if (blend_mrt0_is_dual_src)
1131 col_format |= (col_format & 0xf) << 4;
1132 blend->spi_shader_col_format = col_format;
1133 }
1134
1135 static bool
1136 format_is_int8(VkFormat format)
1137 {
1138 const struct vk_format_description *desc = vk_format_description(format);
1139 int channel = vk_format_get_first_non_void_channel(format);
1140
1141 return channel >= 0 && desc->channel[channel].pure_integer &&
1142 desc->channel[channel].size == 8;
1143 }
1144
1145 static bool
1146 format_is_int10(VkFormat format)
1147 {
1148 const struct vk_format_description *desc = vk_format_description(format);
1149
1150 if (desc->nr_channels != 4)
1151 return false;
1152 for (unsigned i = 0; i < 4; i++) {
1153 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
1154 return true;
1155 }
1156 return false;
1157 }
1158
1159 unsigned radv_format_meta_fs_key(VkFormat format)
1160 {
1161 unsigned col_format = si_choose_spi_color_format(format, false, false) - 1;
1162 bool is_int8 = format_is_int8(format);
1163 bool is_int10 = format_is_int10(format);
1164
1165 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
1166 }
1167
1168 static void
1169 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo *pCreateInfo,
1170 unsigned *is_int8, unsigned *is_int10)
1171 {
1172 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1173 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
1174 *is_int8 = 0;
1175 *is_int10 = 0;
1176
1177 for (unsigned i = 0; i < subpass->color_count; ++i) {
1178 struct radv_render_pass_attachment *attachment;
1179
1180 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
1181 continue;
1182
1183 attachment = pass->attachments + subpass->color_attachments[i].attachment;
1184
1185 if (format_is_int8(attachment->format))
1186 *is_int8 |= 1 << i;
1187 if (format_is_int10(attachment->format))
1188 *is_int10 |= 1 << i;
1189 }
1190 }
1191
1192 static void
1193 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
1194 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1195 const struct radv_graphics_pipeline_create_info *extra)
1196 {
1197 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
1198 struct radv_blend_state *blend = &pipeline->graphics.blend;
1199 unsigned mode = V_028808_CB_NORMAL;
1200 uint32_t blend_enable = 0, blend_need_alpha = 0;
1201 bool blend_mrt0_is_dual_src = false;
1202 int i;
1203 bool single_cb_enable = false;
1204
1205 if (!vkblend)
1206 return;
1207
1208 if (extra && extra->custom_blend_mode) {
1209 single_cb_enable = true;
1210 mode = extra->custom_blend_mode;
1211 }
1212 blend->cb_color_control = 0;
1213 if (vkblend->logicOpEnable)
1214 blend->cb_color_control |= S_028808_ROP3(vkblend->logicOp | (vkblend->logicOp << 4));
1215 else
1216 blend->cb_color_control |= S_028808_ROP3(0xcc);
1217
1218 blend->db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
1219 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
1220 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
1221 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
1222
1223 blend->cb_target_mask = 0;
1224 for (i = 0; i < vkblend->attachmentCount; i++) {
1225 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
1226 unsigned blend_cntl = 0;
1227 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
1228 VkBlendOp eqRGB = att->colorBlendOp;
1229 VkBlendFactor srcRGB = att->srcColorBlendFactor;
1230 VkBlendFactor dstRGB = att->dstColorBlendFactor;
1231 VkBlendOp eqA = att->alphaBlendOp;
1232 VkBlendFactor srcA = att->srcAlphaBlendFactor;
1233 VkBlendFactor dstA = att->dstAlphaBlendFactor;
1234
1235 blend->sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
1236
1237 if (!att->colorWriteMask)
1238 continue;
1239
1240 blend->cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
1241 if (!att->blendEnable) {
1242 blend->cb_blend_control[i] = blend_cntl;
1243 continue;
1244 }
1245
1246 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
1247 if (i == 0)
1248 blend_mrt0_is_dual_src = true;
1249
1250 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
1251 srcRGB = VK_BLEND_FACTOR_ONE;
1252 dstRGB = VK_BLEND_FACTOR_ONE;
1253 }
1254 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
1255 srcA = VK_BLEND_FACTOR_ONE;
1256 dstA = VK_BLEND_FACTOR_ONE;
1257 }
1258
1259 /* Blending optimizations for RB+.
1260 * These transformations don't change the behavior.
1261 *
1262 * First, get rid of DST in the blend factors:
1263 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
1264 */
1265 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
1266 VK_BLEND_FACTOR_DST_COLOR,
1267 VK_BLEND_FACTOR_SRC_COLOR);
1268
1269 si_blend_remove_dst(&eqA, &srcA, &dstA,
1270 VK_BLEND_FACTOR_DST_COLOR,
1271 VK_BLEND_FACTOR_SRC_COLOR);
1272
1273 si_blend_remove_dst(&eqA, &srcA, &dstA,
1274 VK_BLEND_FACTOR_DST_ALPHA,
1275 VK_BLEND_FACTOR_SRC_ALPHA);
1276
1277 /* Look up the ideal settings from tables. */
1278 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
1279 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
1280 srcA_opt = si_translate_blend_opt_factor(srcA, true);
1281 dstA_opt = si_translate_blend_opt_factor(dstA, true);
1282
1283 /* Handle interdependencies. */
1284 if (si_blend_factor_uses_dst(srcRGB))
1285 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
1286 if (si_blend_factor_uses_dst(srcA))
1287 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
1288
1289 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
1290 (dstRGB == VK_BLEND_FACTOR_ZERO ||
1291 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
1292 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
1293 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
1294
1295 /* Set the final value. */
1296 blend->sx_mrt_blend_opt[i] =
1297 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
1298 S_028760_COLOR_DST_OPT(dstRGB_opt) |
1299 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
1300 S_028760_ALPHA_SRC_OPT(srcA_opt) |
1301 S_028760_ALPHA_DST_OPT(dstA_opt) |
1302 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
1303 blend_cntl |= S_028780_ENABLE(1);
1304
1305 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
1306 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
1307 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
1308 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
1309 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
1310 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
1311 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
1312 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
1313 }
1314 blend->cb_blend_control[i] = blend_cntl;
1315
1316 blend_enable |= 1 << i;
1317
1318 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
1319 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
1320 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
1321 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
1322 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
1323 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
1324 blend_need_alpha |= 1 << i;
1325 }
1326 for (i = vkblend->attachmentCount; i < 8; i++) {
1327 blend->cb_blend_control[i] = 0;
1328 blend->sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
1329 }
1330
1331 /* disable RB+ for now */
1332 if (pipeline->device->physical_device->has_rbplus)
1333 blend->cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
1334
1335 if (blend->cb_target_mask)
1336 blend->cb_color_control |= S_028808_MODE(mode);
1337 else
1338 blend->cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
1339
1340 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo,
1341 blend_enable, blend_need_alpha, single_cb_enable, blend_mrt0_is_dual_src);
1342 }
1343
1344 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
1345 {
1346 switch (op) {
1347 case VK_STENCIL_OP_KEEP:
1348 return V_02842C_STENCIL_KEEP;
1349 case VK_STENCIL_OP_ZERO:
1350 return V_02842C_STENCIL_ZERO;
1351 case VK_STENCIL_OP_REPLACE:
1352 return V_02842C_STENCIL_REPLACE_TEST;
1353 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
1354 return V_02842C_STENCIL_ADD_CLAMP;
1355 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
1356 return V_02842C_STENCIL_SUB_CLAMP;
1357 case VK_STENCIL_OP_INVERT:
1358 return V_02842C_STENCIL_INVERT;
1359 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
1360 return V_02842C_STENCIL_ADD_WRAP;
1361 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
1362 return V_02842C_STENCIL_SUB_WRAP;
1363 default:
1364 return 0;
1365 }
1366 }
1367 static void
1368 radv_pipeline_init_depth_stencil_state(struct radv_pipeline *pipeline,
1369 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1370 const struct radv_graphics_pipeline_create_info *extra)
1371 {
1372 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
1373 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
1374
1375 memset(ds, 0, sizeof(*ds));
1376 if (!vkds)
1377 return;
1378
1379 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1380 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
1381 if (subpass->depth_stencil_attachment.attachment == VK_ATTACHMENT_UNUSED)
1382 return;
1383
1384 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment.attachment;
1385 bool has_depth_attachment = vk_format_is_depth(attachment->format);
1386 bool has_stencil_attachment = vk_format_is_stencil(attachment->format);
1387
1388 if (has_depth_attachment) {
1389 ds->db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
1390 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
1391 S_028800_ZFUNC(vkds->depthCompareOp) |
1392 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
1393 }
1394
1395 if (has_stencil_attachment && vkds->stencilTestEnable) {
1396 ds->db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
1397 ds->db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
1398 ds->db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
1399 ds->db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
1400 ds->db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
1401
1402 ds->db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
1403 ds->db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
1404 ds->db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
1405 ds->db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
1406 }
1407
1408 if (extra) {
1409
1410 ds->db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
1411 ds->db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
1412
1413 ds->db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
1414 ds->db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
1415 ds->db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
1416 ds->db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
1417 ds->db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
1418 }
1419 }
1420
1421 static uint32_t si_translate_fill(VkPolygonMode func)
1422 {
1423 switch(func) {
1424 case VK_POLYGON_MODE_FILL:
1425 return V_028814_X_DRAW_TRIANGLES;
1426 case VK_POLYGON_MODE_LINE:
1427 return V_028814_X_DRAW_LINES;
1428 case VK_POLYGON_MODE_POINT:
1429 return V_028814_X_DRAW_POINTS;
1430 default:
1431 assert(0);
1432 return V_028814_X_DRAW_POINTS;
1433 }
1434 }
1435 static void
1436 radv_pipeline_init_raster_state(struct radv_pipeline *pipeline,
1437 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1438 {
1439 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
1440 struct radv_raster_state *raster = &pipeline->graphics.raster;
1441
1442 memset(raster, 0, sizeof(*raster));
1443
1444 raster->spi_interp_control =
1445 S_0286D4_FLAT_SHADE_ENA(1) |
1446 S_0286D4_PNT_SPRITE_ENA(1) |
1447 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
1448 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
1449 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
1450 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
1451 S_0286D4_PNT_SPRITE_TOP_1(0); // vulkan is top to bottom - 1.0 at bottom
1452
1453
1454 raster->pa_cl_clip_cntl = S_028810_PS_UCP_MODE(3) |
1455 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
1456 S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1457 S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1458 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
1459 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
1460
1461 raster->pa_su_vtx_cntl =
1462 S_028BE4_PIX_CENTER(1) | // TODO verify
1463 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
1464 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH);
1465
1466 raster->pa_su_sc_mode_cntl =
1467 S_028814_FACE(vkraster->frontFace) |
1468 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
1469 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
1470 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
1471 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1472 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1473 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1474 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1475 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0);
1476
1477 }
1478
1479 static void
1480 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1481 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1482 {
1483 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
1484 struct radv_blend_state *blend = &pipeline->graphics.blend;
1485 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1486 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1487 int ps_iter_samples = 1;
1488 uint32_t mask = 0xffff;
1489
1490 if (vkms)
1491 ms->num_samples = vkms->rasterizationSamples;
1492 else
1493 ms->num_samples = 1;
1494
1495 if (vkms && vkms->sampleShadingEnable) {
1496 ps_iter_samples = ceil(vkms->minSampleShading * ms->num_samples);
1497 } else if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.force_persample) {
1498 ps_iter_samples = ms->num_samples;
1499 }
1500
1501 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1502 ms->pa_sc_aa_config = 0;
1503 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1504 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1505 ms->pa_sc_mode_cntl_1 =
1506 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1507 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1508 /* always 1: */
1509 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1510 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1511 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1512 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1513 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1514 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1515 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9);
1516
1517 if (ms->num_samples > 1) {
1518 unsigned log_samples = util_logbase2(ms->num_samples);
1519 unsigned log_ps_iter_samples = util_logbase2(util_next_power_of_two(ps_iter_samples));
1520 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
1521 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1522 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1523 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1524 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1525 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1526 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1527 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
1528 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1529 ms->pa_sc_mode_cntl_1 |= EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1530 }
1531
1532 if (vkms) {
1533 if (vkms->alphaToCoverageEnable)
1534 blend->db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
1535
1536 if (vkms->pSampleMask)
1537 mask = vkms->pSampleMask[0] & 0xffff;
1538 }
1539
1540 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1541 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1542 }
1543
1544 static bool
1545 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1546 {
1547 switch (topology) {
1548 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1549 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1550 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1551 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1552 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1553 return false;
1554 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1555 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1556 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1557 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1558 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1559 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1560 return true;
1561 default:
1562 unreachable("unhandled primitive type");
1563 }
1564 }
1565
1566 static uint32_t
1567 si_translate_prim(enum VkPrimitiveTopology topology)
1568 {
1569 switch (topology) {
1570 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1571 return V_008958_DI_PT_POINTLIST;
1572 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1573 return V_008958_DI_PT_LINELIST;
1574 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1575 return V_008958_DI_PT_LINESTRIP;
1576 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1577 return V_008958_DI_PT_TRILIST;
1578 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1579 return V_008958_DI_PT_TRISTRIP;
1580 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1581 return V_008958_DI_PT_TRIFAN;
1582 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1583 return V_008958_DI_PT_LINELIST_ADJ;
1584 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1585 return V_008958_DI_PT_LINESTRIP_ADJ;
1586 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1587 return V_008958_DI_PT_TRILIST_ADJ;
1588 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1589 return V_008958_DI_PT_TRISTRIP_ADJ;
1590 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1591 return V_008958_DI_PT_PATCH;
1592 default:
1593 assert(0);
1594 return 0;
1595 }
1596 }
1597
1598 static uint32_t
1599 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1600 {
1601 switch (gl_prim) {
1602 case 0: /* GL_POINTS */
1603 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1604 case 1: /* GL_LINES */
1605 case 3: /* GL_LINE_STRIP */
1606 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1607 case 0x8E7A: /* GL_ISOLINES */
1608 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1609
1610 case 4: /* GL_TRIANGLES */
1611 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1612 case 5: /* GL_TRIANGLE_STRIP */
1613 case 7: /* GL_QUADS */
1614 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1615 default:
1616 assert(0);
1617 return 0;
1618 }
1619 }
1620
1621 static uint32_t
1622 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1623 {
1624 switch (topology) {
1625 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1626 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1627 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1628 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1629 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1630 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1631 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1632 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1633 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1634 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1635 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1636 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1637 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1638 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1639 default:
1640 assert(0);
1641 return 0;
1642 }
1643 }
1644
1645 static unsigned si_map_swizzle(unsigned swizzle)
1646 {
1647 switch (swizzle) {
1648 case VK_SWIZZLE_Y:
1649 return V_008F0C_SQ_SEL_Y;
1650 case VK_SWIZZLE_Z:
1651 return V_008F0C_SQ_SEL_Z;
1652 case VK_SWIZZLE_W:
1653 return V_008F0C_SQ_SEL_W;
1654 case VK_SWIZZLE_0:
1655 return V_008F0C_SQ_SEL_0;
1656 case VK_SWIZZLE_1:
1657 return V_008F0C_SQ_SEL_1;
1658 default: /* VK_SWIZZLE_X */
1659 return V_008F0C_SQ_SEL_X;
1660 }
1661 }
1662
1663 static void
1664 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1665 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1666 {
1667 radv_cmd_dirty_mask_t states = RADV_CMD_DIRTY_DYNAMIC_ALL;
1668 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1669 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1670
1671 pipeline->dynamic_state = default_dynamic_state;
1672
1673 if (pCreateInfo->pDynamicState) {
1674 /* Remove all of the states that are marked as dynamic */
1675 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1676 for (uint32_t s = 0; s < count; s++)
1677 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
1678 }
1679
1680 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1681
1682 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1683 *
1684 * pViewportState is [...] NULL if the pipeline
1685 * has rasterization disabled.
1686 */
1687 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1688 assert(pCreateInfo->pViewportState);
1689
1690 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1691 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
1692 typed_memcpy(dynamic->viewport.viewports,
1693 pCreateInfo->pViewportState->pViewports,
1694 pCreateInfo->pViewportState->viewportCount);
1695 }
1696
1697 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1698 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
1699 typed_memcpy(dynamic->scissor.scissors,
1700 pCreateInfo->pViewportState->pScissors,
1701 pCreateInfo->pViewportState->scissorCount);
1702 }
1703 }
1704
1705 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
1706 assert(pCreateInfo->pRasterizationState);
1707 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1708 }
1709
1710 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
1711 assert(pCreateInfo->pRasterizationState);
1712 dynamic->depth_bias.bias =
1713 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1714 dynamic->depth_bias.clamp =
1715 pCreateInfo->pRasterizationState->depthBiasClamp;
1716 dynamic->depth_bias.slope =
1717 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1718 }
1719
1720 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1721 *
1722 * pColorBlendState is [...] NULL if the pipeline has rasterization
1723 * disabled or if the subpass of the render pass the pipeline is
1724 * created against does not use any color attachments.
1725 */
1726 bool uses_color_att = false;
1727 for (unsigned i = 0; i < subpass->color_count; ++i) {
1728 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1729 uses_color_att = true;
1730 break;
1731 }
1732 }
1733
1734 if (uses_color_att && states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
1735 assert(pCreateInfo->pColorBlendState);
1736 typed_memcpy(dynamic->blend_constants,
1737 pCreateInfo->pColorBlendState->blendConstants, 4);
1738 }
1739
1740 /* If there is no depthstencil attachment, then don't read
1741 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1742 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1743 * no need to override the depthstencil defaults in
1744 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1745 *
1746 * Section 9.2 of the Vulkan 1.0.15 spec says:
1747 *
1748 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1749 * disabled or if the subpass of the render pass the pipeline is created
1750 * against does not use a depth/stencil attachment.
1751 */
1752 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
1753 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1754 assert(pCreateInfo->pDepthStencilState);
1755
1756 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
1757 dynamic->depth_bounds.min =
1758 pCreateInfo->pDepthStencilState->minDepthBounds;
1759 dynamic->depth_bounds.max =
1760 pCreateInfo->pDepthStencilState->maxDepthBounds;
1761 }
1762
1763 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
1764 dynamic->stencil_compare_mask.front =
1765 pCreateInfo->pDepthStencilState->front.compareMask;
1766 dynamic->stencil_compare_mask.back =
1767 pCreateInfo->pDepthStencilState->back.compareMask;
1768 }
1769
1770 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
1771 dynamic->stencil_write_mask.front =
1772 pCreateInfo->pDepthStencilState->front.writeMask;
1773 dynamic->stencil_write_mask.back =
1774 pCreateInfo->pDepthStencilState->back.writeMask;
1775 }
1776
1777 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
1778 dynamic->stencil_reference.front =
1779 pCreateInfo->pDepthStencilState->front.reference;
1780 dynamic->stencil_reference.back =
1781 pCreateInfo->pDepthStencilState->back.reference;
1782 }
1783 }
1784
1785 pipeline->dynamic_state_mask = states;
1786 }
1787
1788 static struct ac_shader_variant_key
1789 radv_compute_vs_key(const VkGraphicsPipelineCreateInfo *pCreateInfo, bool as_es, bool as_ls, bool export_prim_id)
1790 {
1791 struct ac_shader_variant_key key;
1792 const VkPipelineVertexInputStateCreateInfo *input_state =
1793 pCreateInfo->pVertexInputState;
1794
1795 memset(&key, 0, sizeof(key));
1796 key.vs.instance_rate_inputs = 0;
1797 key.vs.as_es = as_es;
1798 key.vs.as_ls = as_ls;
1799 key.vs.export_prim_id = export_prim_id;
1800
1801 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
1802 unsigned binding;
1803 binding = input_state->pVertexAttributeDescriptions[i].binding;
1804 if (input_state->pVertexBindingDescriptions[binding].inputRate)
1805 key.vs.instance_rate_inputs |= 1u << input_state->pVertexAttributeDescriptions[i].location;
1806 }
1807 return key;
1808 }
1809
1810 static void
1811 calculate_gs_ring_sizes(struct radv_pipeline *pipeline)
1812 {
1813 struct radv_device *device = pipeline->device;
1814 unsigned num_se = device->physical_device->rad_info.max_se;
1815 unsigned wave_size = 64;
1816 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1817 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1818 unsigned alignment = 256 * num_se;
1819 /* The maximum size is 63.999 MB per SE. */
1820 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1821 struct ac_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1822 struct ac_es_output_info *es_info = radv_pipeline_has_tess(pipeline) ?
1823 &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.es_info :
1824 &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info;
1825
1826 /* Calculate the minimum size. */
1827 unsigned min_esgs_ring_size = align(es_info->esgs_itemsize * gs_vertex_reuse *
1828 wave_size, alignment);
1829 /* These are recommended sizes, not minimum sizes. */
1830 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1831 es_info->esgs_itemsize * gs_info->gs.vertices_in;
1832 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1833 gs_info->gs.max_gsvs_emit_size * 1; // no streams in VK (gs->max_gs_stream + 1);
1834
1835 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1836 esgs_ring_size = align(esgs_ring_size, alignment);
1837 gsvs_ring_size = align(gsvs_ring_size, alignment);
1838
1839 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1840 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1841 }
1842
1843 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1844 unsigned *lds_size)
1845 {
1846 /* SPI barrier management bug:
1847 * Make sure we have at least 4k of LDS in use to avoid the bug.
1848 * It applies to workgroup sizes of more than one wavefront.
1849 */
1850 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1851 device->physical_device->rad_info.family == CHIP_KABINI ||
1852 device->physical_device->rad_info.family == CHIP_MULLINS)
1853 *lds_size = MAX2(*lds_size, 8);
1854 }
1855
1856 static void
1857 calculate_tess_state(struct radv_pipeline *pipeline,
1858 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1859 {
1860 unsigned num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1861 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
1862 unsigned num_tcs_patch_outputs;
1863 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
1864 unsigned input_patch_size, output_patch_size, output_patch0_offset;
1865 unsigned lds_size, hardware_lds_size;
1866 unsigned perpatch_output_offset;
1867 unsigned num_patches;
1868 struct radv_tessellation_state *tess = &pipeline->graphics.tess;
1869
1870 /* This calculates how shader inputs and outputs among VS, TCS, and TES
1871 * are laid out in LDS. */
1872 num_tcs_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outputs_written);
1873
1874 num_tcs_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written); //tcs->outputs_written
1875 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1876 num_tcs_patch_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.patch_outputs_written);
1877
1878 /* Ensure that we only need one wave per SIMD so we don't need to check
1879 * resource usage. Also ensures that the number of tcs in and out
1880 * vertices per threadgroup are at most 256.
1881 */
1882 input_vertex_size = num_tcs_inputs * 16;
1883 output_vertex_size = num_tcs_outputs * 16;
1884
1885 input_patch_size = num_tcs_input_cp * input_vertex_size;
1886
1887 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
1888 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
1889 /* Ensure that we only need one wave per SIMD so we don't need to check
1890 * resource usage. Also ensures that the number of tcs in and out
1891 * vertices per threadgroup are at most 256.
1892 */
1893 num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
1894
1895 /* Make sure that the data fits in LDS. This assumes the shaders only
1896 * use LDS for the inputs and outputs.
1897 */
1898 hardware_lds_size = pipeline->device->physical_device->rad_info.chip_class >= CIK ? 65536 : 32768;
1899 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
1900
1901 /* Make sure the output data fits in the offchip buffer */
1902 num_patches = MIN2(num_patches,
1903 (pipeline->device->tess_offchip_block_dw_size * 4) /
1904 output_patch_size);
1905
1906 /* Not necessary for correctness, but improves performance. The
1907 * specific value is taken from the proprietary driver.
1908 */
1909 num_patches = MIN2(num_patches, 40);
1910
1911 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
1912 if (pipeline->device->physical_device->rad_info.chip_class == SI) {
1913 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
1914 num_patches = MIN2(num_patches, one_wave);
1915 }
1916
1917 output_patch0_offset = input_patch_size * num_patches;
1918 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
1919
1920 lds_size = output_patch0_offset + output_patch_size * num_patches;
1921
1922 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
1923 assert(lds_size <= 65536);
1924 lds_size = align(lds_size, 512) / 512;
1925 } else {
1926 assert(lds_size <= 32768);
1927 lds_size = align(lds_size, 256) / 256;
1928 }
1929 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1930
1931 tess->lds_size = lds_size;
1932
1933 tess->tcs_in_layout = (input_patch_size / 4) |
1934 ((input_vertex_size / 4) << 13);
1935 tess->tcs_out_layout = (output_patch_size / 4) |
1936 ((output_vertex_size / 4) << 13);
1937 tess->tcs_out_offsets = (output_patch0_offset / 16) |
1938 ((perpatch_output_offset / 16) << 16);
1939 tess->offchip_layout = (pervertex_output_patch_size * num_patches << 16) |
1940 (num_tcs_output_cp << 9) | num_patches;
1941
1942 tess->ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1943 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1944 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1945 tess->num_patches = num_patches;
1946 tess->num_tcs_input_cp = num_tcs_input_cp;
1947
1948 struct radv_shader_variant *tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
1949 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1950
1951 switch (tes->info.tes.primitive_mode) {
1952 case GL_TRIANGLES:
1953 type = V_028B6C_TESS_TRIANGLE;
1954 break;
1955 case GL_QUADS:
1956 type = V_028B6C_TESS_QUAD;
1957 break;
1958 case GL_ISOLINES:
1959 type = V_028B6C_TESS_ISOLINE;
1960 break;
1961 }
1962
1963 switch (tes->info.tes.spacing) {
1964 case TESS_SPACING_EQUAL:
1965 partitioning = V_028B6C_PART_INTEGER;
1966 break;
1967 case TESS_SPACING_FRACTIONAL_ODD:
1968 partitioning = V_028B6C_PART_FRAC_ODD;
1969 break;
1970 case TESS_SPACING_FRACTIONAL_EVEN:
1971 partitioning = V_028B6C_PART_FRAC_EVEN;
1972 break;
1973 default:
1974 break;
1975 }
1976
1977 if (tes->info.tes.point_mode)
1978 topology = V_028B6C_OUTPUT_POINT;
1979 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
1980 topology = V_028B6C_OUTPUT_LINE;
1981 else if (tes->info.tes.ccw)
1982 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
1983 else
1984 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
1985
1986 if (pipeline->device->has_distributed_tess) {
1987 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
1988 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
1989 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
1990 else
1991 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
1992 } else
1993 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
1994
1995 tess->tf_param = S_028B6C_TYPE(type) |
1996 S_028B6C_PARTITIONING(partitioning) |
1997 S_028B6C_TOPOLOGY(topology) |
1998 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
1999 }
2000
2001 static const struct radv_prim_vertex_count prim_size_table[] = {
2002 [V_008958_DI_PT_NONE] = {0, 0},
2003 [V_008958_DI_PT_POINTLIST] = {1, 1},
2004 [V_008958_DI_PT_LINELIST] = {2, 2},
2005 [V_008958_DI_PT_LINESTRIP] = {2, 1},
2006 [V_008958_DI_PT_TRILIST] = {3, 3},
2007 [V_008958_DI_PT_TRIFAN] = {3, 1},
2008 [V_008958_DI_PT_TRISTRIP] = {3, 1},
2009 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
2010 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
2011 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
2012 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
2013 [V_008958_DI_PT_RECTLIST] = {3, 3},
2014 [V_008958_DI_PT_LINELOOP] = {2, 1},
2015 [V_008958_DI_PT_POLYGON] = {3, 1},
2016 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
2017 };
2018
2019 static uint32_t si_vgt_gs_mode(struct radv_shader_variant *gs)
2020 {
2021 unsigned gs_max_vert_out = gs->info.gs.vertices_out;
2022 unsigned cut_mode;
2023
2024 if (gs_max_vert_out <= 128) {
2025 cut_mode = V_028A40_GS_CUT_128;
2026 } else if (gs_max_vert_out <= 256) {
2027 cut_mode = V_028A40_GS_CUT_256;
2028 } else if (gs_max_vert_out <= 512) {
2029 cut_mode = V_028A40_GS_CUT_512;
2030 } else {
2031 assert(gs_max_vert_out <= 1024);
2032 cut_mode = V_028A40_GS_CUT_1024;
2033 }
2034
2035 return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
2036 S_028A40_CUT_MODE(cut_mode)|
2037 S_028A40_ES_WRITE_OPTIMIZE(1) |
2038 S_028A40_GS_WRITE_OPTIMIZE(1);
2039 }
2040
2041 static void calculate_vgt_gs_mode(struct radv_pipeline *pipeline)
2042 {
2043 struct radv_shader_variant *vs;
2044 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : (radv_pipeline_has_tess(pipeline) ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX]);
2045
2046 struct ac_vs_output_info *outinfo = &vs->info.vs.outinfo;
2047
2048 pipeline->graphics.vgt_primitiveid_en = false;
2049 pipeline->graphics.vgt_gs_mode = 0;
2050
2051 if (radv_pipeline_has_gs(pipeline)) {
2052 pipeline->graphics.vgt_gs_mode = si_vgt_gs_mode(pipeline->shaders[MESA_SHADER_GEOMETRY]);
2053 } else if (outinfo->export_prim_id) {
2054 pipeline->graphics.vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
2055 pipeline->graphics.vgt_primitiveid_en = true;
2056 }
2057 }
2058
2059 static void calculate_pa_cl_vs_out_cntl(struct radv_pipeline *pipeline)
2060 {
2061 struct radv_shader_variant *vs;
2062 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : (radv_pipeline_has_tess(pipeline) ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX]);
2063
2064 struct ac_vs_output_info *outinfo = &vs->info.vs.outinfo;
2065
2066 unsigned clip_dist_mask, cull_dist_mask, total_mask;
2067 clip_dist_mask = outinfo->clip_dist_mask;
2068 cull_dist_mask = outinfo->cull_dist_mask;
2069 total_mask = clip_dist_mask | cull_dist_mask;
2070
2071 bool misc_vec_ena = outinfo->writes_pointsize ||
2072 outinfo->writes_layer ||
2073 outinfo->writes_viewport_index;
2074 pipeline->graphics.pa_cl_vs_out_cntl =
2075 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
2076 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
2077 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
2078 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2079 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
2080 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
2081 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
2082 cull_dist_mask << 8 |
2083 clip_dist_mask;
2084
2085 }
2086
2087 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade)
2088 {
2089 uint32_t ps_input_cntl;
2090 if (offset <= AC_EXP_PARAM_OFFSET_31) {
2091 ps_input_cntl = S_028644_OFFSET(offset);
2092 if (flat_shade)
2093 ps_input_cntl |= S_028644_FLAT_SHADE(1);
2094 } else {
2095 /* The input is a DEFAULT_VAL constant. */
2096 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
2097 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
2098 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
2099 ps_input_cntl = S_028644_OFFSET(0x20) |
2100 S_028644_DEFAULT_VAL(offset);
2101 }
2102 return ps_input_cntl;
2103 }
2104
2105 static void calculate_ps_inputs(struct radv_pipeline *pipeline)
2106 {
2107 struct radv_shader_variant *ps, *vs;
2108 struct ac_vs_output_info *outinfo;
2109
2110 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
2111 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : (radv_pipeline_has_tess(pipeline) ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX]);
2112
2113 outinfo = &vs->info.vs.outinfo;
2114
2115 unsigned ps_offset = 0;
2116
2117 if (ps->info.fs.prim_id_input) {
2118 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
2119 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
2120 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
2121 ++ps_offset;
2122 }
2123 }
2124
2125 if (ps->info.fs.layer_input) {
2126 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
2127 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
2128 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
2129 else
2130 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true);
2131 ++ps_offset;
2132 }
2133
2134 if (ps->info.fs.has_pcoord) {
2135 unsigned val;
2136 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
2137 pipeline->graphics.ps_input_cntl[ps_offset] = val;
2138 ps_offset++;
2139 }
2140
2141 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
2142 unsigned vs_offset;
2143 bool flat_shade;
2144 if (!(ps->info.fs.input_mask & (1u << i)))
2145 continue;
2146
2147 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
2148 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
2149 pipeline->graphics.ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
2150 ++ps_offset;
2151 continue;
2152 }
2153
2154 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
2155
2156 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade);
2157 ++ps_offset;
2158 }
2159
2160 pipeline->graphics.ps_input_cntl_num = ps_offset;
2161 }
2162
2163 VkResult
2164 radv_pipeline_init(struct radv_pipeline *pipeline,
2165 struct radv_device *device,
2166 struct radv_pipeline_cache *cache,
2167 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2168 const struct radv_graphics_pipeline_create_info *extra,
2169 const VkAllocationCallbacks *alloc)
2170 {
2171 struct radv_shader_module fs_m = {0};
2172 VkResult result;
2173 bool has_view_index = false;
2174
2175 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2176 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2177 if (subpass->view_mask)
2178 has_view_index = true;
2179 if (alloc == NULL)
2180 alloc = &device->alloc;
2181
2182 pipeline->device = device;
2183 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
2184
2185 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
2186 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
2187 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
2188 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
2189 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
2190 pStages[stage] = &pCreateInfo->pStages[i];
2191 modules[stage] = radv_shader_module_from_handle(pStages[stage]->module);
2192 }
2193
2194 radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
2195
2196 if (!modules[MESA_SHADER_FRAGMENT]) {
2197 nir_builder fs_b;
2198 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
2199 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
2200 fs_m.nir = fs_b.shader;
2201 modules[MESA_SHADER_FRAGMENT] = &fs_m;
2202 }
2203
2204 if (modules[MESA_SHADER_FRAGMENT]) {
2205 struct ac_shader_variant_key key = {0};
2206 key.fs.col_format = pipeline->graphics.blend.spi_shader_col_format;
2207 if (pCreateInfo->pMultisampleState &&
2208 pCreateInfo->pMultisampleState->rasterizationSamples > 1)
2209 key.fs.multisample = true;
2210
2211 if (pipeline->device->physical_device->rad_info.chip_class < VI)
2212 radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.fs.is_int8, &key.fs.is_int10);
2213
2214 const VkPipelineShaderStageCreateInfo *stage = pStages[MESA_SHADER_FRAGMENT];
2215
2216 pipeline->shaders[MESA_SHADER_FRAGMENT] =
2217 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_FRAGMENT],
2218 stage ? stage->pName : "main",
2219 MESA_SHADER_FRAGMENT,
2220 stage ? stage->pSpecializationInfo : NULL,
2221 pipeline->layout, &key);
2222 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_FRAGMENT);
2223 }
2224
2225 if (fs_m.nir)
2226 ralloc_free(fs_m.nir);
2227
2228 if (modules[MESA_SHADER_VERTEX]) {
2229 bool as_es = false;
2230 bool as_ls = false;
2231 bool export_prim_id = false;
2232 if (modules[MESA_SHADER_TESS_CTRL])
2233 as_ls = true;
2234 else if (modules[MESA_SHADER_GEOMETRY])
2235 as_es = true;
2236 else if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input)
2237 export_prim_id = true;
2238 struct ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo, as_es, as_ls, export_prim_id);
2239 key.has_multiview_view_index = has_view_index;
2240
2241 pipeline->shaders[MESA_SHADER_VERTEX] =
2242 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_VERTEX],
2243 pStages[MESA_SHADER_VERTEX]->pName,
2244 MESA_SHADER_VERTEX,
2245 pStages[MESA_SHADER_VERTEX]->pSpecializationInfo,
2246 pipeline->layout, &key);
2247
2248 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_VERTEX);
2249 }
2250
2251 if (modules[MESA_SHADER_GEOMETRY]) {
2252 struct ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo, false, false, false);
2253 key.has_multiview_view_index = has_view_index;
2254
2255 pipeline->shaders[MESA_SHADER_GEOMETRY] =
2256 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_GEOMETRY],
2257 pStages[MESA_SHADER_GEOMETRY]->pName,
2258 MESA_SHADER_GEOMETRY,
2259 pStages[MESA_SHADER_GEOMETRY]->pSpecializationInfo,
2260 pipeline->layout, &key);
2261
2262 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_GEOMETRY);
2263 }
2264
2265 if (modules[MESA_SHADER_TESS_EVAL]) {
2266 assert(modules[MESA_SHADER_TESS_CTRL]);
2267
2268 radv_tess_pipeline_compile(pipeline,
2269 cache,
2270 modules[MESA_SHADER_TESS_CTRL],
2271 modules[MESA_SHADER_TESS_EVAL],
2272 pStages[MESA_SHADER_TESS_CTRL]->pName,
2273 pStages[MESA_SHADER_TESS_EVAL]->pName,
2274 pStages[MESA_SHADER_TESS_CTRL]->pSpecializationInfo,
2275 pStages[MESA_SHADER_TESS_EVAL]->pSpecializationInfo,
2276 pipeline->layout,
2277 pCreateInfo->pTessellationState->patchControlPoints,
2278 has_view_index);
2279 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_TESS_EVAL) |
2280 mesa_to_vk_shader_stage(MESA_SHADER_TESS_CTRL);
2281 }
2282
2283 radv_pipeline_init_depth_stencil_state(pipeline, pCreateInfo, extra);
2284 radv_pipeline_init_raster_state(pipeline, pCreateInfo);
2285 radv_pipeline_init_multisample_state(pipeline, pCreateInfo);
2286 pipeline->graphics.prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
2287 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
2288
2289 if (radv_pipeline_has_gs(pipeline)) {
2290 pipeline->graphics.gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
2291 pipeline->graphics.can_use_guardband = pipeline->graphics.gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
2292 } else {
2293 pipeline->graphics.gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
2294 }
2295 if (extra && extra->use_rectlist) {
2296 pipeline->graphics.prim = V_008958_DI_PT_RECTLIST;
2297 pipeline->graphics.gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
2298 pipeline->graphics.can_use_guardband = true;
2299 }
2300 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
2301 /* prim vertex count will need TESS changes */
2302 pipeline->graphics.prim_vertex_count = prim_size_table[pipeline->graphics.prim];
2303
2304 /* Ensure that some export memory is always allocated, for two reasons:
2305 *
2306 * 1) Correctness: The hardware ignores the EXEC mask if no export
2307 * memory is allocated, so KILL and alpha test do not work correctly
2308 * without this.
2309 * 2) Performance: Every shader needs at least a NULL export, even when
2310 * it writes no color/depth output. The NULL export instruction
2311 * stalls without this setting.
2312 *
2313 * Don't add this to CB_SHADER_MASK.
2314 */
2315 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
2316 if (!pipeline->graphics.blend.spi_shader_col_format) {
2317 if (!ps->info.fs.writes_z &&
2318 !ps->info.fs.writes_stencil &&
2319 !ps->info.fs.writes_sample_mask)
2320 pipeline->graphics.blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
2321 }
2322
2323 unsigned z_order;
2324 pipeline->graphics.db_shader_control = 0;
2325 if (ps->info.fs.early_fragment_test || !ps->info.fs.writes_memory)
2326 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
2327 else
2328 z_order = V_02880C_LATE_Z;
2329
2330 pipeline->graphics.db_shader_control =
2331 S_02880C_Z_EXPORT_ENABLE(ps->info.fs.writes_z) |
2332 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.fs.writes_stencil) |
2333 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
2334 S_02880C_MASK_EXPORT_ENABLE(ps->info.fs.writes_sample_mask) |
2335 S_02880C_Z_ORDER(z_order) |
2336 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
2337 S_02880C_EXEC_ON_HIER_FAIL(ps->info.fs.writes_memory) |
2338 S_02880C_EXEC_ON_NOOP(ps->info.fs.writes_memory);
2339
2340 if (pipeline->device->physical_device->has_rbplus)
2341 pipeline->graphics.db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
2342
2343 pipeline->graphics.shader_z_format =
2344 ps->info.fs.writes_sample_mask ? V_028710_SPI_SHADER_32_ABGR :
2345 ps->info.fs.writes_stencil ? V_028710_SPI_SHADER_32_GR :
2346 ps->info.fs.writes_z ? V_028710_SPI_SHADER_32_R :
2347 V_028710_SPI_SHADER_ZERO;
2348
2349 calculate_vgt_gs_mode(pipeline);
2350 calculate_pa_cl_vs_out_cntl(pipeline);
2351 calculate_ps_inputs(pipeline);
2352
2353 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
2354 if (pipeline->shaders[i]) {
2355 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
2356 }
2357 }
2358
2359 uint32_t stages = 0;
2360 if (radv_pipeline_has_tess(pipeline)) {
2361 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2362 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
2363
2364 if (radv_pipeline_has_gs(pipeline))
2365 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
2366 S_028B54_GS_EN(1) |
2367 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2368 else
2369 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2370
2371 } else if (radv_pipeline_has_gs(pipeline))
2372 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
2373 S_028B54_GS_EN(1) |
2374 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2375
2376 if (device->physical_device->rad_info.chip_class >= GFX9)
2377 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
2378
2379 pipeline->graphics.vgt_shader_stages_en = stages;
2380
2381 if (radv_pipeline_has_gs(pipeline))
2382 calculate_gs_ring_sizes(pipeline);
2383
2384 if (radv_pipeline_has_tess(pipeline)) {
2385 if (pipeline->graphics.prim == V_008958_DI_PT_PATCH) {
2386 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
2387 pipeline->graphics.prim_vertex_count.incr = 1;
2388 }
2389 calculate_tess_state(pipeline, pCreateInfo);
2390 }
2391
2392 const VkPipelineVertexInputStateCreateInfo *vi_info =
2393 pCreateInfo->pVertexInputState;
2394 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
2395 const VkVertexInputAttributeDescription *desc =
2396 &vi_info->pVertexAttributeDescriptions[i];
2397 unsigned loc = desc->location;
2398 const struct vk_format_description *format_desc;
2399 int first_non_void;
2400 uint32_t num_format, data_format;
2401 format_desc = vk_format_description(desc->format);
2402 first_non_void = vk_format_get_first_non_void_channel(desc->format);
2403
2404 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
2405 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
2406
2407 pipeline->va_rsrc_word3[loc] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc->swizzle[0])) |
2408 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc->swizzle[1])) |
2409 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc->swizzle[2])) |
2410 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc->swizzle[3])) |
2411 S_008F0C_NUM_FORMAT(num_format) |
2412 S_008F0C_DATA_FORMAT(data_format);
2413 pipeline->va_format_size[loc] = format_desc->block.bits / 8;
2414 pipeline->va_offset[loc] = desc->offset;
2415 pipeline->va_binding[loc] = desc->binding;
2416 pipeline->num_vertex_attribs = MAX2(pipeline->num_vertex_attribs, loc + 1);
2417 }
2418
2419 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
2420 const VkVertexInputBindingDescription *desc =
2421 &vi_info->pVertexBindingDescriptions[i];
2422
2423 pipeline->binding_stride[desc->binding] = desc->stride;
2424 }
2425
2426 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
2427 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2428 if (loc->sgpr_idx != -1) {
2429 pipeline->graphics.vtx_base_sgpr = radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
2430 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
2431 if (pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id)
2432 pipeline->graphics.vtx_emit_num = 3;
2433 else
2434 pipeline->graphics.vtx_emit_num = 2;
2435 }
2436 if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
2437 radv_dump_pipeline_stats(device, pipeline);
2438 }
2439
2440 result = radv_pipeline_scratch_init(device, pipeline);
2441 return result;
2442 }
2443
2444 VkResult
2445 radv_graphics_pipeline_create(
2446 VkDevice _device,
2447 VkPipelineCache _cache,
2448 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2449 const struct radv_graphics_pipeline_create_info *extra,
2450 const VkAllocationCallbacks *pAllocator,
2451 VkPipeline *pPipeline)
2452 {
2453 RADV_FROM_HANDLE(radv_device, device, _device);
2454 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
2455 struct radv_pipeline *pipeline;
2456 VkResult result;
2457
2458 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
2459 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2460 if (pipeline == NULL)
2461 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2462
2463 memset(pipeline, 0, sizeof(*pipeline));
2464 result = radv_pipeline_init(pipeline, device, cache,
2465 pCreateInfo, extra, pAllocator);
2466 if (result != VK_SUCCESS) {
2467 radv_pipeline_destroy(device, pipeline, pAllocator);
2468 return result;
2469 }
2470
2471 *pPipeline = radv_pipeline_to_handle(pipeline);
2472
2473 return VK_SUCCESS;
2474 }
2475
2476 VkResult radv_CreateGraphicsPipelines(
2477 VkDevice _device,
2478 VkPipelineCache pipelineCache,
2479 uint32_t count,
2480 const VkGraphicsPipelineCreateInfo* pCreateInfos,
2481 const VkAllocationCallbacks* pAllocator,
2482 VkPipeline* pPipelines)
2483 {
2484 VkResult result = VK_SUCCESS;
2485 unsigned i = 0;
2486
2487 for (; i < count; i++) {
2488 VkResult r;
2489 r = radv_graphics_pipeline_create(_device,
2490 pipelineCache,
2491 &pCreateInfos[i],
2492 NULL, pAllocator, &pPipelines[i]);
2493 if (r != VK_SUCCESS) {
2494 result = r;
2495 pPipelines[i] = VK_NULL_HANDLE;
2496 }
2497 }
2498
2499 return result;
2500 }
2501
2502 static VkResult radv_compute_pipeline_create(
2503 VkDevice _device,
2504 VkPipelineCache _cache,
2505 const VkComputePipelineCreateInfo* pCreateInfo,
2506 const VkAllocationCallbacks* pAllocator,
2507 VkPipeline* pPipeline)
2508 {
2509 RADV_FROM_HANDLE(radv_device, device, _device);
2510 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
2511 RADV_FROM_HANDLE(radv_shader_module, module, pCreateInfo->stage.module);
2512 struct radv_pipeline *pipeline;
2513 VkResult result;
2514
2515 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
2516 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2517 if (pipeline == NULL)
2518 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2519
2520 memset(pipeline, 0, sizeof(*pipeline));
2521 pipeline->device = device;
2522 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
2523
2524 pipeline->shaders[MESA_SHADER_COMPUTE] =
2525 radv_pipeline_compile(pipeline, cache, module,
2526 pCreateInfo->stage.pName,
2527 MESA_SHADER_COMPUTE,
2528 pCreateInfo->stage.pSpecializationInfo,
2529 pipeline->layout, NULL);
2530
2531
2532 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
2533 result = radv_pipeline_scratch_init(device, pipeline);
2534 if (result != VK_SUCCESS) {
2535 radv_pipeline_destroy(device, pipeline, pAllocator);
2536 return result;
2537 }
2538
2539 *pPipeline = radv_pipeline_to_handle(pipeline);
2540
2541 if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
2542 radv_dump_pipeline_stats(device, pipeline);
2543 }
2544 return VK_SUCCESS;
2545 }
2546 VkResult radv_CreateComputePipelines(
2547 VkDevice _device,
2548 VkPipelineCache pipelineCache,
2549 uint32_t count,
2550 const VkComputePipelineCreateInfo* pCreateInfos,
2551 const VkAllocationCallbacks* pAllocator,
2552 VkPipeline* pPipelines)
2553 {
2554 VkResult result = VK_SUCCESS;
2555
2556 unsigned i = 0;
2557 for (; i < count; i++) {
2558 VkResult r;
2559 r = radv_compute_pipeline_create(_device, pipelineCache,
2560 &pCreateInfos[i],
2561 pAllocator, &pPipelines[i]);
2562 if (r != VK_SUCCESS) {
2563 result = r;
2564 pPipelines[i] = VK_NULL_HANDLE;
2565 }
2566 }
2567
2568 return result;
2569 }
2570
2571 void *radv_alloc_shader_memory(struct radv_device *device,
2572 struct radv_shader_variant *shader)
2573 {
2574 mtx_lock(&device->shader_slab_mutex);
2575 list_for_each_entry(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
2576 uint64_t offset = 0;
2577 list_for_each_entry(struct radv_shader_variant, s, &slab->shaders, slab_list) {
2578 if (s->bo_offset - offset >= shader->code_size) {
2579 shader->bo = slab->bo;
2580 shader->bo_offset = offset;
2581 list_addtail(&shader->slab_list, &s->slab_list);
2582 mtx_unlock(&device->shader_slab_mutex);
2583 return slab->ptr + offset;
2584 }
2585 offset = align_u64(s->bo_offset + s->code_size, 256);
2586 }
2587 if (slab->size - offset >= shader->code_size) {
2588 shader->bo = slab->bo;
2589 shader->bo_offset = offset;
2590 list_addtail(&shader->slab_list, &slab->shaders);
2591 mtx_unlock(&device->shader_slab_mutex);
2592 return slab->ptr + offset;
2593 }
2594 }
2595
2596 mtx_unlock(&device->shader_slab_mutex);
2597 struct radv_shader_slab *slab = calloc(1, sizeof(struct radv_shader_slab));
2598
2599 slab->size = 256 * 1024;
2600 slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
2601 RADEON_DOMAIN_VRAM, 0);
2602 slab->ptr = (char*)device->ws->buffer_map(slab->bo);
2603 list_inithead(&slab->shaders);
2604
2605 mtx_lock(&device->shader_slab_mutex);
2606 list_add(&slab->slabs, &device->shader_slabs);
2607
2608 shader->bo = slab->bo;
2609 shader->bo_offset = 0;
2610 list_add(&shader->slab_list, &slab->shaders);
2611 mtx_unlock(&device->shader_slab_mutex);
2612 return slab->ptr;
2613 }
2614
2615 void radv_destroy_shader_slabs(struct radv_device *device)
2616 {
2617 list_for_each_entry_safe(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
2618 device->ws->buffer_destroy(slab->bo);
2619 free(slab);
2620 }
2621 mtx_destroy(&device->shader_slab_mutex);
2622 }