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radv: ignore pTessellationState if the pipeline doesn't use tess
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/disk_cache.h"
29 #include "util/mesa-sha1.h"
30 #include "util/u_atomic.h"
31 #include "radv_debug.h"
32 #include "radv_private.h"
33 #include "radv_cs.h"
34 #include "radv_shader.h"
35 #include "nir/nir.h"
36 #include "nir/nir_builder.h"
37 #include "nir/nir_xfb_info.h"
38 #include "spirv/nir_spirv.h"
39 #include "vk_util.h"
40
41 #include <llvm-c/Core.h>
42 #include <llvm-c/TargetMachine.h>
43
44 #include "sid.h"
45 #include "ac_binary.h"
46 #include "ac_llvm_util.h"
47 #include "ac_nir_to_llvm.h"
48 #include "vk_format.h"
49 #include "util/debug.h"
50 #include "ac_exp_param.h"
51 #include "ac_shader_util.h"
52 #include "main/menums.h"
53
54 struct radv_blend_state {
55 uint32_t blend_enable_4bit;
56 uint32_t need_src_alpha;
57
58 uint32_t cb_color_control;
59 uint32_t cb_target_mask;
60 uint32_t cb_target_enabled_4bit;
61 uint32_t sx_mrt_blend_opt[8];
62 uint32_t cb_blend_control[8];
63
64 uint32_t spi_shader_col_format;
65 uint32_t cb_shader_mask;
66 uint32_t db_alpha_to_mask;
67
68 uint32_t commutative_4bit;
69
70 bool single_cb_enable;
71 bool mrt0_is_dual_src;
72 };
73
74 struct radv_dsa_order_invariance {
75 /* Whether the final result in Z/S buffers is guaranteed to be
76 * invariant under changes to the order in which fragments arrive.
77 */
78 bool zs;
79
80 /* Whether the set of fragments that pass the combined Z/S test is
81 * guaranteed to be invariant under changes to the order in which
82 * fragments arrive.
83 */
84 bool pass_set;
85 };
86
87 struct radv_tessellation_state {
88 uint32_t ls_hs_config;
89 unsigned num_patches;
90 unsigned lds_size;
91 uint32_t tf_param;
92 };
93
94 static const VkPipelineMultisampleStateCreateInfo *
95 radv_pipeline_get_multisample_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
96 {
97 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
98 return pCreateInfo->pMultisampleState;
99 return NULL;
100 }
101
102 static const VkPipelineTessellationStateCreateInfo *
103 radv_pipeline_get_tessellation_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
104 {
105 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
106 if (pCreateInfo->pStages[i].stage == VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT ||
107 pCreateInfo->pStages[i].stage == VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) {
108 return pCreateInfo->pTessellationState;
109 }
110 }
111 return NULL;
112 }
113
114 bool radv_pipeline_has_ngg(const struct radv_pipeline *pipeline)
115 {
116 struct radv_shader_variant *variant = NULL;
117 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
118 variant = pipeline->shaders[MESA_SHADER_GEOMETRY];
119 else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
120 variant = pipeline->shaders[MESA_SHADER_TESS_EVAL];
121 else if (pipeline->shaders[MESA_SHADER_VERTEX])
122 variant = pipeline->shaders[MESA_SHADER_VERTEX];
123 else
124 return false;
125 return variant->info.is_ngg;
126 }
127
128 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline *pipeline)
129 {
130 if (!radv_pipeline_has_gs(pipeline))
131 return false;
132
133 /* The GS copy shader is required if the pipeline has GS on GFX6-GFX9.
134 * On GFX10, it might be required in rare cases if it's not possible to
135 * enable NGG.
136 */
137 if (radv_pipeline_has_ngg(pipeline))
138 return false;
139
140 assert(pipeline->gs_copy_shader);
141 return true;
142 }
143
144 static void
145 radv_pipeline_destroy(struct radv_device *device,
146 struct radv_pipeline *pipeline,
147 const VkAllocationCallbacks* allocator)
148 {
149 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
150 if (pipeline->shaders[i])
151 radv_shader_variant_destroy(device, pipeline->shaders[i]);
152
153 if (pipeline->gs_copy_shader)
154 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
155
156 if(pipeline->cs.buf)
157 free(pipeline->cs.buf);
158 vk_free2(&device->alloc, allocator, pipeline);
159 }
160
161 void radv_DestroyPipeline(
162 VkDevice _device,
163 VkPipeline _pipeline,
164 const VkAllocationCallbacks* pAllocator)
165 {
166 RADV_FROM_HANDLE(radv_device, device, _device);
167 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
168
169 if (!_pipeline)
170 return;
171
172 radv_pipeline_destroy(device, pipeline, pAllocator);
173 }
174
175 static uint32_t get_hash_flags(struct radv_device *device)
176 {
177 uint32_t hash_flags = 0;
178
179 if (device->instance->debug_flags & RADV_DEBUG_NO_NGG)
180 hash_flags |= RADV_HASH_SHADER_NO_NGG;
181 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
182 hash_flags |= RADV_HASH_SHADER_SISCHED;
183 if (device->physical_device->cs_wave_size == 32)
184 hash_flags |= RADV_HASH_SHADER_CS_WAVE32;
185 if (device->physical_device->ps_wave_size == 32)
186 hash_flags |= RADV_HASH_SHADER_PS_WAVE32;
187 if (device->physical_device->ge_wave_size == 32)
188 hash_flags |= RADV_HASH_SHADER_GE_WAVE32;
189 if (device->physical_device->use_aco)
190 hash_flags |= RADV_HASH_SHADER_ACO;
191 return hash_flags;
192 }
193
194 static VkResult
195 radv_pipeline_scratch_init(struct radv_device *device,
196 struct radv_pipeline *pipeline)
197 {
198 unsigned scratch_bytes_per_wave = 0;
199 unsigned max_waves = 0;
200 unsigned min_waves = 1;
201
202 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
203 if (pipeline->shaders[i] &&
204 pipeline->shaders[i]->config.scratch_bytes_per_wave) {
205 unsigned max_stage_waves = device->scratch_waves;
206
207 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
208 pipeline->shaders[i]->config.scratch_bytes_per_wave);
209
210 max_stage_waves = MIN2(max_stage_waves,
211 4 * device->physical_device->rad_info.num_good_compute_units *
212 (256 / pipeline->shaders[i]->config.num_vgprs));
213 max_waves = MAX2(max_waves, max_stage_waves);
214 }
215 }
216
217 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
218 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
219 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
220 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
221 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
222 }
223
224 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
225 pipeline->max_waves = max_waves;
226 return VK_SUCCESS;
227 }
228
229 static uint32_t si_translate_blend_logic_op(VkLogicOp op)
230 {
231 switch (op) {
232 case VK_LOGIC_OP_CLEAR:
233 return V_028808_ROP3_CLEAR;
234 case VK_LOGIC_OP_AND:
235 return V_028808_ROP3_AND;
236 case VK_LOGIC_OP_AND_REVERSE:
237 return V_028808_ROP3_AND_REVERSE;
238 case VK_LOGIC_OP_COPY:
239 return V_028808_ROP3_COPY;
240 case VK_LOGIC_OP_AND_INVERTED:
241 return V_028808_ROP3_AND_INVERTED;
242 case VK_LOGIC_OP_NO_OP:
243 return V_028808_ROP3_NO_OP;
244 case VK_LOGIC_OP_XOR:
245 return V_028808_ROP3_XOR;
246 case VK_LOGIC_OP_OR:
247 return V_028808_ROP3_OR;
248 case VK_LOGIC_OP_NOR:
249 return V_028808_ROP3_NOR;
250 case VK_LOGIC_OP_EQUIVALENT:
251 return V_028808_ROP3_EQUIVALENT;
252 case VK_LOGIC_OP_INVERT:
253 return V_028808_ROP3_INVERT;
254 case VK_LOGIC_OP_OR_REVERSE:
255 return V_028808_ROP3_OR_REVERSE;
256 case VK_LOGIC_OP_COPY_INVERTED:
257 return V_028808_ROP3_COPY_INVERTED;
258 case VK_LOGIC_OP_OR_INVERTED:
259 return V_028808_ROP3_OR_INVERTED;
260 case VK_LOGIC_OP_NAND:
261 return V_028808_ROP3_NAND;
262 case VK_LOGIC_OP_SET:
263 return V_028808_ROP3_SET;
264 default:
265 unreachable("Unhandled logic op");
266 }
267 }
268
269
270 static uint32_t si_translate_blend_function(VkBlendOp op)
271 {
272 switch (op) {
273 case VK_BLEND_OP_ADD:
274 return V_028780_COMB_DST_PLUS_SRC;
275 case VK_BLEND_OP_SUBTRACT:
276 return V_028780_COMB_SRC_MINUS_DST;
277 case VK_BLEND_OP_REVERSE_SUBTRACT:
278 return V_028780_COMB_DST_MINUS_SRC;
279 case VK_BLEND_OP_MIN:
280 return V_028780_COMB_MIN_DST_SRC;
281 case VK_BLEND_OP_MAX:
282 return V_028780_COMB_MAX_DST_SRC;
283 default:
284 return 0;
285 }
286 }
287
288 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
289 {
290 switch (factor) {
291 case VK_BLEND_FACTOR_ZERO:
292 return V_028780_BLEND_ZERO;
293 case VK_BLEND_FACTOR_ONE:
294 return V_028780_BLEND_ONE;
295 case VK_BLEND_FACTOR_SRC_COLOR:
296 return V_028780_BLEND_SRC_COLOR;
297 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
298 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
299 case VK_BLEND_FACTOR_DST_COLOR:
300 return V_028780_BLEND_DST_COLOR;
301 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
302 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
303 case VK_BLEND_FACTOR_SRC_ALPHA:
304 return V_028780_BLEND_SRC_ALPHA;
305 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
306 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
307 case VK_BLEND_FACTOR_DST_ALPHA:
308 return V_028780_BLEND_DST_ALPHA;
309 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
310 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
311 case VK_BLEND_FACTOR_CONSTANT_COLOR:
312 return V_028780_BLEND_CONSTANT_COLOR;
313 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
314 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
315 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
316 return V_028780_BLEND_CONSTANT_ALPHA;
317 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
318 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
319 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
320 return V_028780_BLEND_SRC_ALPHA_SATURATE;
321 case VK_BLEND_FACTOR_SRC1_COLOR:
322 return V_028780_BLEND_SRC1_COLOR;
323 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
324 return V_028780_BLEND_INV_SRC1_COLOR;
325 case VK_BLEND_FACTOR_SRC1_ALPHA:
326 return V_028780_BLEND_SRC1_ALPHA;
327 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
328 return V_028780_BLEND_INV_SRC1_ALPHA;
329 default:
330 return 0;
331 }
332 }
333
334 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
335 {
336 switch (op) {
337 case VK_BLEND_OP_ADD:
338 return V_028760_OPT_COMB_ADD;
339 case VK_BLEND_OP_SUBTRACT:
340 return V_028760_OPT_COMB_SUBTRACT;
341 case VK_BLEND_OP_REVERSE_SUBTRACT:
342 return V_028760_OPT_COMB_REVSUBTRACT;
343 case VK_BLEND_OP_MIN:
344 return V_028760_OPT_COMB_MIN;
345 case VK_BLEND_OP_MAX:
346 return V_028760_OPT_COMB_MAX;
347 default:
348 return V_028760_OPT_COMB_BLEND_DISABLED;
349 }
350 }
351
352 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
353 {
354 switch (factor) {
355 case VK_BLEND_FACTOR_ZERO:
356 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
357 case VK_BLEND_FACTOR_ONE:
358 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
359 case VK_BLEND_FACTOR_SRC_COLOR:
360 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
361 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
362 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
363 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
364 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
365 case VK_BLEND_FACTOR_SRC_ALPHA:
366 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
367 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
368 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
369 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
370 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
371 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
372 default:
373 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
374 }
375 }
376
377 /**
378 * Get rid of DST in the blend factors by commuting the operands:
379 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
380 */
381 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
382 unsigned *dst_factor, unsigned expected_dst,
383 unsigned replacement_src)
384 {
385 if (*src_factor == expected_dst &&
386 *dst_factor == VK_BLEND_FACTOR_ZERO) {
387 *src_factor = VK_BLEND_FACTOR_ZERO;
388 *dst_factor = replacement_src;
389
390 /* Commuting the operands requires reversing subtractions. */
391 if (*func == VK_BLEND_OP_SUBTRACT)
392 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
393 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
394 *func = VK_BLEND_OP_SUBTRACT;
395 }
396 }
397
398 static bool si_blend_factor_uses_dst(unsigned factor)
399 {
400 return factor == VK_BLEND_FACTOR_DST_COLOR ||
401 factor == VK_BLEND_FACTOR_DST_ALPHA ||
402 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
403 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
404 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
405 }
406
407 static bool is_dual_src(VkBlendFactor factor)
408 {
409 switch (factor) {
410 case VK_BLEND_FACTOR_SRC1_COLOR:
411 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
412 case VK_BLEND_FACTOR_SRC1_ALPHA:
413 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
414 return true;
415 default:
416 return false;
417 }
418 }
419
420 static unsigned si_choose_spi_color_format(VkFormat vk_format,
421 bool blend_enable,
422 bool blend_need_alpha)
423 {
424 const struct vk_format_description *desc = vk_format_description(vk_format);
425 unsigned format, ntype, swap;
426
427 /* Alpha is needed for alpha-to-coverage.
428 * Blending may be with or without alpha.
429 */
430 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
431 unsigned alpha = 0; /* exports alpha, but may not support blending */
432 unsigned blend = 0; /* supports blending, but may not export alpha */
433 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
434
435 format = radv_translate_colorformat(vk_format);
436 ntype = radv_translate_color_numformat(vk_format, desc,
437 vk_format_get_first_non_void_channel(vk_format));
438 swap = radv_translate_colorswap(vk_format, false);
439
440 /* Choose the SPI color formats. These are required values for Stoney/RB+.
441 * Other chips have multiple choices, though they are not necessarily better.
442 */
443 switch (format) {
444 case V_028C70_COLOR_5_6_5:
445 case V_028C70_COLOR_1_5_5_5:
446 case V_028C70_COLOR_5_5_5_1:
447 case V_028C70_COLOR_4_4_4_4:
448 case V_028C70_COLOR_10_11_11:
449 case V_028C70_COLOR_11_11_10:
450 case V_028C70_COLOR_8:
451 case V_028C70_COLOR_8_8:
452 case V_028C70_COLOR_8_8_8_8:
453 case V_028C70_COLOR_10_10_10_2:
454 case V_028C70_COLOR_2_10_10_10:
455 if (ntype == V_028C70_NUMBER_UINT)
456 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
457 else if (ntype == V_028C70_NUMBER_SINT)
458 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
459 else
460 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
461 break;
462
463 case V_028C70_COLOR_16:
464 case V_028C70_COLOR_16_16:
465 case V_028C70_COLOR_16_16_16_16:
466 if (ntype == V_028C70_NUMBER_UNORM ||
467 ntype == V_028C70_NUMBER_SNORM) {
468 /* UNORM16 and SNORM16 don't support blending */
469 if (ntype == V_028C70_NUMBER_UNORM)
470 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
471 else
472 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
473
474 /* Use 32 bits per channel for blending. */
475 if (format == V_028C70_COLOR_16) {
476 if (swap == V_028C70_SWAP_STD) { /* R */
477 blend = V_028714_SPI_SHADER_32_R;
478 blend_alpha = V_028714_SPI_SHADER_32_AR;
479 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
480 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
481 else
482 assert(0);
483 } else if (format == V_028C70_COLOR_16_16) {
484 if (swap == V_028C70_SWAP_STD) { /* RG */
485 blend = V_028714_SPI_SHADER_32_GR;
486 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
487 } else if (swap == V_028C70_SWAP_ALT) /* RA */
488 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
489 else
490 assert(0);
491 } else /* 16_16_16_16 */
492 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
493 } else if (ntype == V_028C70_NUMBER_UINT)
494 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
495 else if (ntype == V_028C70_NUMBER_SINT)
496 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
497 else if (ntype == V_028C70_NUMBER_FLOAT)
498 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
499 else
500 assert(0);
501 break;
502
503 case V_028C70_COLOR_32:
504 if (swap == V_028C70_SWAP_STD) { /* R */
505 blend = normal = V_028714_SPI_SHADER_32_R;
506 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
507 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
508 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
509 else
510 assert(0);
511 break;
512
513 case V_028C70_COLOR_32_32:
514 if (swap == V_028C70_SWAP_STD) { /* RG */
515 blend = normal = V_028714_SPI_SHADER_32_GR;
516 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
517 } else if (swap == V_028C70_SWAP_ALT) /* RA */
518 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
519 else
520 assert(0);
521 break;
522
523 case V_028C70_COLOR_32_32_32_32:
524 case V_028C70_COLOR_8_24:
525 case V_028C70_COLOR_24_8:
526 case V_028C70_COLOR_X24_8_32_FLOAT:
527 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
528 break;
529
530 default:
531 unreachable("unhandled blend format");
532 }
533
534 if (blend_enable && blend_need_alpha)
535 return blend_alpha;
536 else if(blend_need_alpha)
537 return alpha;
538 else if(blend_enable)
539 return blend;
540 else
541 return normal;
542 }
543
544 static void
545 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
546 const VkGraphicsPipelineCreateInfo *pCreateInfo,
547 struct radv_blend_state *blend)
548 {
549 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
550 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
551 unsigned col_format = 0;
552 unsigned num_targets;
553
554 for (unsigned i = 0; i < (blend->single_cb_enable ? 1 : subpass->color_count); ++i) {
555 unsigned cf;
556
557 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
558 cf = V_028714_SPI_SHADER_ZERO;
559 } else {
560 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
561 bool blend_enable =
562 blend->blend_enable_4bit & (0xfu << (i * 4));
563
564 cf = si_choose_spi_color_format(attachment->format,
565 blend_enable,
566 blend->need_src_alpha & (1 << i));
567 }
568
569 col_format |= cf << (4 * i);
570 }
571
572 if (!(col_format & 0xf) && blend->need_src_alpha & (1 << 0)) {
573 /* When a subpass doesn't have any color attachments, write the
574 * alpha channel of MRT0 when alpha coverage is enabled because
575 * the depth attachment needs it.
576 */
577 col_format |= V_028714_SPI_SHADER_32_AR;
578 }
579
580 /* If the i-th target format is set, all previous target formats must
581 * be non-zero to avoid hangs.
582 */
583 num_targets = (util_last_bit(col_format) + 3) / 4;
584 for (unsigned i = 0; i < num_targets; i++) {
585 if (!(col_format & (0xf << (i * 4)))) {
586 col_format |= V_028714_SPI_SHADER_32_R << (i * 4);
587 }
588 }
589
590 /* The output for dual source blending should have the same format as
591 * the first output.
592 */
593 if (blend->mrt0_is_dual_src)
594 col_format |= (col_format & 0xf) << 4;
595
596 blend->cb_shader_mask = ac_get_cb_shader_mask(col_format);
597 blend->spi_shader_col_format = col_format;
598 }
599
600 static bool
601 format_is_int8(VkFormat format)
602 {
603 const struct vk_format_description *desc = vk_format_description(format);
604 int channel = vk_format_get_first_non_void_channel(format);
605
606 return channel >= 0 && desc->channel[channel].pure_integer &&
607 desc->channel[channel].size == 8;
608 }
609
610 static bool
611 format_is_int10(VkFormat format)
612 {
613 const struct vk_format_description *desc = vk_format_description(format);
614
615 if (desc->nr_channels != 4)
616 return false;
617 for (unsigned i = 0; i < 4; i++) {
618 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
619 return true;
620 }
621 return false;
622 }
623
624 /*
625 * Ordered so that for each i,
626 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
627 */
628 const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS] = {
629 VK_FORMAT_R32_SFLOAT,
630 VK_FORMAT_R32G32_SFLOAT,
631 VK_FORMAT_R8G8B8A8_UNORM,
632 VK_FORMAT_R16G16B16A16_UNORM,
633 VK_FORMAT_R16G16B16A16_SNORM,
634 VK_FORMAT_R16G16B16A16_UINT,
635 VK_FORMAT_R16G16B16A16_SINT,
636 VK_FORMAT_R32G32B32A32_SFLOAT,
637 VK_FORMAT_R8G8B8A8_UINT,
638 VK_FORMAT_R8G8B8A8_SINT,
639 VK_FORMAT_A2R10G10B10_UINT_PACK32,
640 VK_FORMAT_A2R10G10B10_SINT_PACK32,
641 };
642
643 unsigned radv_format_meta_fs_key(VkFormat format)
644 {
645 unsigned col_format = si_choose_spi_color_format(format, false, false);
646
647 assert(col_format != V_028714_SPI_SHADER_32_AR);
648 if (col_format >= V_028714_SPI_SHADER_32_AR)
649 --col_format; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
650
651 --col_format; /* Skip V_028714_SPI_SHADER_ZERO */
652 bool is_int8 = format_is_int8(format);
653 bool is_int10 = format_is_int10(format);
654
655 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
656 }
657
658 static void
659 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo *pCreateInfo,
660 unsigned *is_int8, unsigned *is_int10)
661 {
662 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
663 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
664 *is_int8 = 0;
665 *is_int10 = 0;
666
667 for (unsigned i = 0; i < subpass->color_count; ++i) {
668 struct radv_render_pass_attachment *attachment;
669
670 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
671 continue;
672
673 attachment = pass->attachments + subpass->color_attachments[i].attachment;
674
675 if (format_is_int8(attachment->format))
676 *is_int8 |= 1 << i;
677 if (format_is_int10(attachment->format))
678 *is_int10 |= 1 << i;
679 }
680 }
681
682 static void
683 radv_blend_check_commutativity(struct radv_blend_state *blend,
684 VkBlendOp op, VkBlendFactor src,
685 VkBlendFactor dst, unsigned chanmask)
686 {
687 /* Src factor is allowed when it does not depend on Dst. */
688 static const uint32_t src_allowed =
689 (1u << VK_BLEND_FACTOR_ONE) |
690 (1u << VK_BLEND_FACTOR_SRC_COLOR) |
691 (1u << VK_BLEND_FACTOR_SRC_ALPHA) |
692 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE) |
693 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR) |
694 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA) |
695 (1u << VK_BLEND_FACTOR_SRC1_COLOR) |
696 (1u << VK_BLEND_FACTOR_SRC1_ALPHA) |
697 (1u << VK_BLEND_FACTOR_ZERO) |
698 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR) |
699 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA) |
700 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR) |
701 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA) |
702 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR) |
703 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA);
704
705 if (dst == VK_BLEND_FACTOR_ONE &&
706 (src_allowed & (1u << src))) {
707 /* Addition is commutative, but floating point addition isn't
708 * associative: subtle changes can be introduced via different
709 * rounding. Be conservative, only enable for min and max.
710 */
711 if (op == VK_BLEND_OP_MAX || op == VK_BLEND_OP_MIN)
712 blend->commutative_4bit |= chanmask;
713 }
714 }
715
716 static struct radv_blend_state
717 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
718 const VkGraphicsPipelineCreateInfo *pCreateInfo,
719 const struct radv_graphics_pipeline_create_info *extra)
720 {
721 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
722 const VkPipelineMultisampleStateCreateInfo *vkms = radv_pipeline_get_multisample_state(pCreateInfo);
723 struct radv_blend_state blend = {0};
724 unsigned mode = V_028808_CB_NORMAL;
725 int i;
726
727 if (!vkblend)
728 return blend;
729
730 if (extra && extra->custom_blend_mode) {
731 blend.single_cb_enable = true;
732 mode = extra->custom_blend_mode;
733 }
734 blend.cb_color_control = 0;
735 if (vkblend->logicOpEnable)
736 blend.cb_color_control |= S_028808_ROP3(si_translate_blend_logic_op(vkblend->logicOp));
737 else
738 blend.cb_color_control |= S_028808_ROP3(V_028808_ROP3_COPY);
739
740 blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
741 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
742 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
743 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
744 S_028B70_OFFSET_ROUND(1);
745
746 if (vkms && vkms->alphaToCoverageEnable) {
747 blend.db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
748 blend.need_src_alpha |= 0x1;
749 }
750
751 blend.cb_target_mask = 0;
752 for (i = 0; i < vkblend->attachmentCount; i++) {
753 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
754 unsigned blend_cntl = 0;
755 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
756 VkBlendOp eqRGB = att->colorBlendOp;
757 VkBlendFactor srcRGB = att->srcColorBlendFactor;
758 VkBlendFactor dstRGB = att->dstColorBlendFactor;
759 VkBlendOp eqA = att->alphaBlendOp;
760 VkBlendFactor srcA = att->srcAlphaBlendFactor;
761 VkBlendFactor dstA = att->dstAlphaBlendFactor;
762
763 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
764
765 if (!att->colorWriteMask)
766 continue;
767
768 blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
769 blend.cb_target_enabled_4bit |= 0xf << (4 * i);
770 if (!att->blendEnable) {
771 blend.cb_blend_control[i] = blend_cntl;
772 continue;
773 }
774
775 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
776 if (i == 0)
777 blend.mrt0_is_dual_src = true;
778
779 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
780 srcRGB = VK_BLEND_FACTOR_ONE;
781 dstRGB = VK_BLEND_FACTOR_ONE;
782 }
783 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
784 srcA = VK_BLEND_FACTOR_ONE;
785 dstA = VK_BLEND_FACTOR_ONE;
786 }
787
788 radv_blend_check_commutativity(&blend, eqRGB, srcRGB, dstRGB,
789 0x7 << (4 * i));
790 radv_blend_check_commutativity(&blend, eqA, srcA, dstA,
791 0x8 << (4 * i));
792
793 /* Blending optimizations for RB+.
794 * These transformations don't change the behavior.
795 *
796 * First, get rid of DST in the blend factors:
797 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
798 */
799 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
800 VK_BLEND_FACTOR_DST_COLOR,
801 VK_BLEND_FACTOR_SRC_COLOR);
802
803 si_blend_remove_dst(&eqA, &srcA, &dstA,
804 VK_BLEND_FACTOR_DST_COLOR,
805 VK_BLEND_FACTOR_SRC_COLOR);
806
807 si_blend_remove_dst(&eqA, &srcA, &dstA,
808 VK_BLEND_FACTOR_DST_ALPHA,
809 VK_BLEND_FACTOR_SRC_ALPHA);
810
811 /* Look up the ideal settings from tables. */
812 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
813 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
814 srcA_opt = si_translate_blend_opt_factor(srcA, true);
815 dstA_opt = si_translate_blend_opt_factor(dstA, true);
816
817 /* Handle interdependencies. */
818 if (si_blend_factor_uses_dst(srcRGB))
819 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
820 if (si_blend_factor_uses_dst(srcA))
821 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
822
823 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
824 (dstRGB == VK_BLEND_FACTOR_ZERO ||
825 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
826 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
827 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
828
829 /* Set the final value. */
830 blend.sx_mrt_blend_opt[i] =
831 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
832 S_028760_COLOR_DST_OPT(dstRGB_opt) |
833 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
834 S_028760_ALPHA_SRC_OPT(srcA_opt) |
835 S_028760_ALPHA_DST_OPT(dstA_opt) |
836 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
837 blend_cntl |= S_028780_ENABLE(1);
838
839 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
840 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
841 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
842 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
843 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
844 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
845 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
846 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
847 }
848 blend.cb_blend_control[i] = blend_cntl;
849
850 blend.blend_enable_4bit |= 0xfu << (i * 4);
851
852 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
853 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
854 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
855 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
856 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
857 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
858 blend.need_src_alpha |= 1 << i;
859 }
860 for (i = vkblend->attachmentCount; i < 8; i++) {
861 blend.cb_blend_control[i] = 0;
862 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
863 }
864
865 if (pipeline->device->physical_device->rad_info.has_rbplus) {
866 /* Disable RB+ blend optimizations for dual source blending. */
867 if (blend.mrt0_is_dual_src) {
868 for (i = 0; i < 8; i++) {
869 blend.sx_mrt_blend_opt[i] =
870 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
871 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
872 }
873 }
874
875 /* RB+ doesn't work with dual source blending, logic op and
876 * RESOLVE.
877 */
878 if (blend.mrt0_is_dual_src || vkblend->logicOpEnable ||
879 mode == V_028808_CB_RESOLVE)
880 blend.cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
881 }
882
883 if (blend.cb_target_mask)
884 blend.cb_color_control |= S_028808_MODE(mode);
885 else
886 blend.cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
887
888 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo, &blend);
889 return blend;
890 }
891
892 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
893 {
894 switch (op) {
895 case VK_STENCIL_OP_KEEP:
896 return V_02842C_STENCIL_KEEP;
897 case VK_STENCIL_OP_ZERO:
898 return V_02842C_STENCIL_ZERO;
899 case VK_STENCIL_OP_REPLACE:
900 return V_02842C_STENCIL_REPLACE_TEST;
901 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
902 return V_02842C_STENCIL_ADD_CLAMP;
903 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
904 return V_02842C_STENCIL_SUB_CLAMP;
905 case VK_STENCIL_OP_INVERT:
906 return V_02842C_STENCIL_INVERT;
907 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
908 return V_02842C_STENCIL_ADD_WRAP;
909 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
910 return V_02842C_STENCIL_SUB_WRAP;
911 default:
912 return 0;
913 }
914 }
915
916 static uint32_t si_translate_fill(VkPolygonMode func)
917 {
918 switch(func) {
919 case VK_POLYGON_MODE_FILL:
920 return V_028814_X_DRAW_TRIANGLES;
921 case VK_POLYGON_MODE_LINE:
922 return V_028814_X_DRAW_LINES;
923 case VK_POLYGON_MODE_POINT:
924 return V_028814_X_DRAW_POINTS;
925 default:
926 assert(0);
927 return V_028814_X_DRAW_POINTS;
928 }
929 }
930
931 static uint8_t radv_pipeline_get_ps_iter_samples(const VkPipelineMultisampleStateCreateInfo *vkms)
932 {
933 uint32_t num_samples = vkms->rasterizationSamples;
934 uint32_t ps_iter_samples = 1;
935
936 if (vkms->sampleShadingEnable) {
937 ps_iter_samples = ceil(vkms->minSampleShading * num_samples);
938 ps_iter_samples = util_next_power_of_two(ps_iter_samples);
939 }
940 return ps_iter_samples;
941 }
942
943 static bool
944 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
945 {
946 return pCreateInfo->depthTestEnable &&
947 pCreateInfo->depthWriteEnable &&
948 pCreateInfo->depthCompareOp != VK_COMPARE_OP_NEVER;
949 }
950
951 static bool
952 radv_writes_stencil(const VkStencilOpState *state)
953 {
954 return state->writeMask &&
955 (state->failOp != VK_STENCIL_OP_KEEP ||
956 state->passOp != VK_STENCIL_OP_KEEP ||
957 state->depthFailOp != VK_STENCIL_OP_KEEP);
958 }
959
960 static bool
961 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
962 {
963 return pCreateInfo->stencilTestEnable &&
964 (radv_writes_stencil(&pCreateInfo->front) ||
965 radv_writes_stencil(&pCreateInfo->back));
966 }
967
968 static bool
969 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
970 {
971 return radv_is_depth_write_enabled(pCreateInfo) ||
972 radv_is_stencil_write_enabled(pCreateInfo);
973 }
974
975 static bool
976 radv_order_invariant_stencil_op(VkStencilOp op)
977 {
978 /* REPLACE is normally order invariant, except when the stencil
979 * reference value is written by the fragment shader. Tracking this
980 * interaction does not seem worth the effort, so be conservative.
981 */
982 return op != VK_STENCIL_OP_INCREMENT_AND_CLAMP &&
983 op != VK_STENCIL_OP_DECREMENT_AND_CLAMP &&
984 op != VK_STENCIL_OP_REPLACE;
985 }
986
987 static bool
988 radv_order_invariant_stencil_state(const VkStencilOpState *state)
989 {
990 /* Compute whether, assuming Z writes are disabled, this stencil state
991 * is order invariant in the sense that the set of passing fragments as
992 * well as the final stencil buffer result does not depend on the order
993 * of fragments.
994 */
995 return !state->writeMask ||
996 /* The following assumes that Z writes are disabled. */
997 (state->compareOp == VK_COMPARE_OP_ALWAYS &&
998 radv_order_invariant_stencil_op(state->passOp) &&
999 radv_order_invariant_stencil_op(state->depthFailOp)) ||
1000 (state->compareOp == VK_COMPARE_OP_NEVER &&
1001 radv_order_invariant_stencil_op(state->failOp));
1002 }
1003
1004 static bool
1005 radv_pipeline_out_of_order_rast(struct radv_pipeline *pipeline,
1006 struct radv_blend_state *blend,
1007 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1008 {
1009 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1010 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
1011 unsigned colormask = blend->cb_target_enabled_4bit;
1012
1013 if (!pipeline->device->physical_device->out_of_order_rast_allowed)
1014 return false;
1015
1016 /* Be conservative if a logic operation is enabled with color buffers. */
1017 if (colormask && pCreateInfo->pColorBlendState->logicOpEnable)
1018 return false;
1019
1020 /* Default depth/stencil invariance when no attachment is bound. */
1021 struct radv_dsa_order_invariance dsa_order_invariant = {
1022 .zs = true, .pass_set = true
1023 };
1024
1025 if (pCreateInfo->pDepthStencilState &&
1026 subpass->depth_stencil_attachment) {
1027 const VkPipelineDepthStencilStateCreateInfo *vkds =
1028 pCreateInfo->pDepthStencilState;
1029 struct radv_render_pass_attachment *attachment =
1030 pass->attachments + subpass->depth_stencil_attachment->attachment;
1031 bool has_stencil = vk_format_is_stencil(attachment->format);
1032 struct radv_dsa_order_invariance order_invariance[2];
1033 struct radv_shader_variant *ps =
1034 pipeline->shaders[MESA_SHADER_FRAGMENT];
1035
1036 /* Compute depth/stencil order invariance in order to know if
1037 * it's safe to enable out-of-order.
1038 */
1039 bool zfunc_is_ordered =
1040 vkds->depthCompareOp == VK_COMPARE_OP_NEVER ||
1041 vkds->depthCompareOp == VK_COMPARE_OP_LESS ||
1042 vkds->depthCompareOp == VK_COMPARE_OP_LESS_OR_EQUAL ||
1043 vkds->depthCompareOp == VK_COMPARE_OP_GREATER ||
1044 vkds->depthCompareOp == VK_COMPARE_OP_GREATER_OR_EQUAL;
1045
1046 bool nozwrite_and_order_invariant_stencil =
1047 !radv_is_ds_write_enabled(vkds) ||
1048 (!radv_is_depth_write_enabled(vkds) &&
1049 radv_order_invariant_stencil_state(&vkds->front) &&
1050 radv_order_invariant_stencil_state(&vkds->back));
1051
1052 order_invariance[1].zs =
1053 nozwrite_and_order_invariant_stencil ||
1054 (!radv_is_stencil_write_enabled(vkds) &&
1055 zfunc_is_ordered);
1056 order_invariance[0].zs =
1057 !radv_is_depth_write_enabled(vkds) || zfunc_is_ordered;
1058
1059 order_invariance[1].pass_set =
1060 nozwrite_and_order_invariant_stencil ||
1061 (!radv_is_stencil_write_enabled(vkds) &&
1062 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1063 vkds->depthCompareOp == VK_COMPARE_OP_NEVER));
1064 order_invariance[0].pass_set =
1065 !radv_is_depth_write_enabled(vkds) ||
1066 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1067 vkds->depthCompareOp == VK_COMPARE_OP_NEVER);
1068
1069 dsa_order_invariant = order_invariance[has_stencil];
1070 if (!dsa_order_invariant.zs)
1071 return false;
1072
1073 /* The set of PS invocations is always order invariant,
1074 * except when early Z/S tests are requested.
1075 */
1076 if (ps &&
1077 ps->info.ps.writes_memory &&
1078 ps->info.ps.early_fragment_test &&
1079 !dsa_order_invariant.pass_set)
1080 return false;
1081
1082 /* Determine if out-of-order rasterization should be disabled
1083 * when occlusion queries are used.
1084 */
1085 pipeline->graphics.disable_out_of_order_rast_for_occlusion =
1086 !dsa_order_invariant.pass_set;
1087 }
1088
1089 /* No color buffers are enabled for writing. */
1090 if (!colormask)
1091 return true;
1092
1093 unsigned blendmask = colormask & blend->blend_enable_4bit;
1094
1095 if (blendmask) {
1096 /* Only commutative blending. */
1097 if (blendmask & ~blend->commutative_4bit)
1098 return false;
1099
1100 if (!dsa_order_invariant.pass_set)
1101 return false;
1102 }
1103
1104 if (colormask & ~blendmask)
1105 return false;
1106
1107 return true;
1108 }
1109
1110 static void
1111 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1112 struct radv_blend_state *blend,
1113 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1114 {
1115 const VkPipelineMultisampleStateCreateInfo *vkms = radv_pipeline_get_multisample_state(pCreateInfo);
1116 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1117 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1118 bool out_of_order_rast = false;
1119 int ps_iter_samples = 1;
1120 uint32_t mask = 0xffff;
1121
1122 if (vkms) {
1123 ms->num_samples = vkms->rasterizationSamples;
1124
1125 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
1126 *
1127 * "Sample shading is enabled for a graphics pipeline:
1128 *
1129 * - If the interface of the fragment shader entry point of the
1130 * graphics pipeline includes an input variable decorated
1131 * with SampleId or SamplePosition. In this case
1132 * minSampleShadingFactor takes the value 1.0.
1133 * - Else if the sampleShadingEnable member of the
1134 * VkPipelineMultisampleStateCreateInfo structure specified
1135 * when creating the graphics pipeline is set to VK_TRUE. In
1136 * this case minSampleShadingFactor takes the value of
1137 * VkPipelineMultisampleStateCreateInfo::minSampleShading.
1138 *
1139 * Otherwise, sample shading is considered disabled."
1140 */
1141 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.force_persample) {
1142 ps_iter_samples = ms->num_samples;
1143 } else {
1144 ps_iter_samples = radv_pipeline_get_ps_iter_samples(vkms);
1145 }
1146 } else {
1147 ms->num_samples = 1;
1148 }
1149
1150 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
1151 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
1152 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
1153 /* Out-of-order rasterization is explicitly enabled by the
1154 * application.
1155 */
1156 out_of_order_rast = true;
1157 } else {
1158 /* Determine if the driver can enable out-of-order
1159 * rasterization internally.
1160 */
1161 out_of_order_rast =
1162 radv_pipeline_out_of_order_rast(pipeline, blend, pCreateInfo);
1163 }
1164
1165 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1166 ms->pa_sc_aa_config = 0;
1167 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1168 S_028804_INCOHERENT_EQAA_READS(1) |
1169 S_028804_INTERPOLATE_COMP_Z(1) |
1170 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1171 ms->pa_sc_mode_cntl_1 =
1172 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1173 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1174 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
1175 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1176 /* always 1: */
1177 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1178 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1179 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1180 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1181 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1182 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1183 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9) |
1184 S_028A48_VPORT_SCISSOR_ENABLE(1);
1185
1186 if (ms->num_samples > 1) {
1187 unsigned log_samples = util_logbase2(ms->num_samples);
1188 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
1189 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
1190 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1191 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1192 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1193 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1194 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1195 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1196 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples)) |
1197 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1198 ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1199 if (ps_iter_samples > 1)
1200 pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1201 }
1202
1203 if (vkms && vkms->pSampleMask) {
1204 mask = vkms->pSampleMask[0] & 0xffff;
1205 }
1206
1207 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1208 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1209 }
1210
1211 static bool
1212 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1213 {
1214 switch (topology) {
1215 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1216 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1217 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1218 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1219 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1220 return false;
1221 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1222 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1223 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1224 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1225 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1226 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1227 return true;
1228 default:
1229 unreachable("unhandled primitive type");
1230 }
1231 }
1232
1233 static uint32_t
1234 si_translate_prim(enum VkPrimitiveTopology topology)
1235 {
1236 switch (topology) {
1237 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1238 return V_008958_DI_PT_POINTLIST;
1239 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1240 return V_008958_DI_PT_LINELIST;
1241 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1242 return V_008958_DI_PT_LINESTRIP;
1243 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1244 return V_008958_DI_PT_TRILIST;
1245 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1246 return V_008958_DI_PT_TRISTRIP;
1247 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1248 return V_008958_DI_PT_TRIFAN;
1249 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1250 return V_008958_DI_PT_LINELIST_ADJ;
1251 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1252 return V_008958_DI_PT_LINESTRIP_ADJ;
1253 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1254 return V_008958_DI_PT_TRILIST_ADJ;
1255 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1256 return V_008958_DI_PT_TRISTRIP_ADJ;
1257 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1258 return V_008958_DI_PT_PATCH;
1259 default:
1260 assert(0);
1261 return 0;
1262 }
1263 }
1264
1265 static uint32_t
1266 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1267 {
1268 switch (gl_prim) {
1269 case 0: /* GL_POINTS */
1270 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1271 case 1: /* GL_LINES */
1272 case 3: /* GL_LINE_STRIP */
1273 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1274 case 0x8E7A: /* GL_ISOLINES */
1275 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1276
1277 case 4: /* GL_TRIANGLES */
1278 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1279 case 5: /* GL_TRIANGLE_STRIP */
1280 case 7: /* GL_QUADS */
1281 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1282 default:
1283 assert(0);
1284 return 0;
1285 }
1286 }
1287
1288 static uint32_t
1289 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1290 {
1291 switch (topology) {
1292 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1293 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1294 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1295 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1296 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1297 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1298 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1299 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1300 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1301 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1302 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1303 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1304 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1305 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1306 default:
1307 assert(0);
1308 return 0;
1309 }
1310 }
1311
1312 static unsigned radv_dynamic_state_mask(VkDynamicState state)
1313 {
1314 switch(state) {
1315 case VK_DYNAMIC_STATE_VIEWPORT:
1316 return RADV_DYNAMIC_VIEWPORT;
1317 case VK_DYNAMIC_STATE_SCISSOR:
1318 return RADV_DYNAMIC_SCISSOR;
1319 case VK_DYNAMIC_STATE_LINE_WIDTH:
1320 return RADV_DYNAMIC_LINE_WIDTH;
1321 case VK_DYNAMIC_STATE_DEPTH_BIAS:
1322 return RADV_DYNAMIC_DEPTH_BIAS;
1323 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
1324 return RADV_DYNAMIC_BLEND_CONSTANTS;
1325 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
1326 return RADV_DYNAMIC_DEPTH_BOUNDS;
1327 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
1328 return RADV_DYNAMIC_STENCIL_COMPARE_MASK;
1329 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
1330 return RADV_DYNAMIC_STENCIL_WRITE_MASK;
1331 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
1332 return RADV_DYNAMIC_STENCIL_REFERENCE;
1333 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT:
1334 return RADV_DYNAMIC_DISCARD_RECTANGLE;
1335 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT:
1336 return RADV_DYNAMIC_SAMPLE_LOCATIONS;
1337 default:
1338 unreachable("Unhandled dynamic state");
1339 }
1340 }
1341
1342 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
1343 {
1344 uint32_t states = RADV_DYNAMIC_ALL;
1345
1346 /* If rasterization is disabled we do not care about any of the dynamic states,
1347 * since they are all rasterization related only. */
1348 if (pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
1349 return 0;
1350
1351 if (!pCreateInfo->pRasterizationState->depthBiasEnable)
1352 states &= ~RADV_DYNAMIC_DEPTH_BIAS;
1353
1354 if (!pCreateInfo->pDepthStencilState ||
1355 !pCreateInfo->pDepthStencilState->depthBoundsTestEnable)
1356 states &= ~RADV_DYNAMIC_DEPTH_BOUNDS;
1357
1358 if (!pCreateInfo->pDepthStencilState ||
1359 !pCreateInfo->pDepthStencilState->stencilTestEnable)
1360 states &= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK |
1361 RADV_DYNAMIC_STENCIL_WRITE_MASK |
1362 RADV_DYNAMIC_STENCIL_REFERENCE);
1363
1364 if (!vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT))
1365 states &= ~RADV_DYNAMIC_DISCARD_RECTANGLE;
1366
1367 if (!pCreateInfo->pMultisampleState ||
1368 !vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1369 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT))
1370 states &= ~RADV_DYNAMIC_SAMPLE_LOCATIONS;
1371
1372 /* TODO: blend constants & line width. */
1373
1374 return states;
1375 }
1376
1377
1378 static void
1379 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1380 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1381 {
1382 uint32_t needed_states = radv_pipeline_needed_dynamic_state(pCreateInfo);
1383 uint32_t states = needed_states;
1384 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1385 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1386
1387 pipeline->dynamic_state = default_dynamic_state;
1388 pipeline->graphics.needed_dynamic_state = needed_states;
1389
1390 if (pCreateInfo->pDynamicState) {
1391 /* Remove all of the states that are marked as dynamic */
1392 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1393 for (uint32_t s = 0; s < count; s++)
1394 states &= ~radv_dynamic_state_mask(pCreateInfo->pDynamicState->pDynamicStates[s]);
1395 }
1396
1397 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1398
1399 if (needed_states & RADV_DYNAMIC_VIEWPORT) {
1400 assert(pCreateInfo->pViewportState);
1401
1402 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1403 if (states & RADV_DYNAMIC_VIEWPORT) {
1404 typed_memcpy(dynamic->viewport.viewports,
1405 pCreateInfo->pViewportState->pViewports,
1406 pCreateInfo->pViewportState->viewportCount);
1407 }
1408 }
1409
1410 if (needed_states & RADV_DYNAMIC_SCISSOR) {
1411 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1412 if (states & RADV_DYNAMIC_SCISSOR) {
1413 typed_memcpy(dynamic->scissor.scissors,
1414 pCreateInfo->pViewportState->pScissors,
1415 pCreateInfo->pViewportState->scissorCount);
1416 }
1417 }
1418
1419 if (states & RADV_DYNAMIC_LINE_WIDTH) {
1420 assert(pCreateInfo->pRasterizationState);
1421 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1422 }
1423
1424 if (states & RADV_DYNAMIC_DEPTH_BIAS) {
1425 assert(pCreateInfo->pRasterizationState);
1426 dynamic->depth_bias.bias =
1427 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1428 dynamic->depth_bias.clamp =
1429 pCreateInfo->pRasterizationState->depthBiasClamp;
1430 dynamic->depth_bias.slope =
1431 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1432 }
1433
1434 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1435 *
1436 * pColorBlendState is [...] NULL if the pipeline has rasterization
1437 * disabled or if the subpass of the render pass the pipeline is
1438 * created against does not use any color attachments.
1439 */
1440 if (subpass->has_color_att && states & RADV_DYNAMIC_BLEND_CONSTANTS) {
1441 assert(pCreateInfo->pColorBlendState);
1442 typed_memcpy(dynamic->blend_constants,
1443 pCreateInfo->pColorBlendState->blendConstants, 4);
1444 }
1445
1446 /* If there is no depthstencil attachment, then don't read
1447 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1448 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1449 * no need to override the depthstencil defaults in
1450 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1451 *
1452 * Section 9.2 of the Vulkan 1.0.15 spec says:
1453 *
1454 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1455 * disabled or if the subpass of the render pass the pipeline is created
1456 * against does not use a depth/stencil attachment.
1457 */
1458 if (needed_states && subpass->depth_stencil_attachment) {
1459 assert(pCreateInfo->pDepthStencilState);
1460
1461 if (states & RADV_DYNAMIC_DEPTH_BOUNDS) {
1462 dynamic->depth_bounds.min =
1463 pCreateInfo->pDepthStencilState->minDepthBounds;
1464 dynamic->depth_bounds.max =
1465 pCreateInfo->pDepthStencilState->maxDepthBounds;
1466 }
1467
1468 if (states & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
1469 dynamic->stencil_compare_mask.front =
1470 pCreateInfo->pDepthStencilState->front.compareMask;
1471 dynamic->stencil_compare_mask.back =
1472 pCreateInfo->pDepthStencilState->back.compareMask;
1473 }
1474
1475 if (states & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
1476 dynamic->stencil_write_mask.front =
1477 pCreateInfo->pDepthStencilState->front.writeMask;
1478 dynamic->stencil_write_mask.back =
1479 pCreateInfo->pDepthStencilState->back.writeMask;
1480 }
1481
1482 if (states & RADV_DYNAMIC_STENCIL_REFERENCE) {
1483 dynamic->stencil_reference.front =
1484 pCreateInfo->pDepthStencilState->front.reference;
1485 dynamic->stencil_reference.back =
1486 pCreateInfo->pDepthStencilState->back.reference;
1487 }
1488 }
1489
1490 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
1491 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
1492 if (needed_states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1493 dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount;
1494 if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1495 typed_memcpy(dynamic->discard_rectangle.rectangles,
1496 discard_rectangle_info->pDiscardRectangles,
1497 discard_rectangle_info->discardRectangleCount);
1498 }
1499 }
1500
1501 if (needed_states & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
1502 const VkPipelineSampleLocationsStateCreateInfoEXT *sample_location_info =
1503 vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1504 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
1505 /* If sampleLocationsEnable is VK_FALSE, the default sample
1506 * locations are used and the values specified in
1507 * sampleLocationsInfo are ignored.
1508 */
1509 if (sample_location_info->sampleLocationsEnable) {
1510 const VkSampleLocationsInfoEXT *pSampleLocationsInfo =
1511 &sample_location_info->sampleLocationsInfo;
1512
1513 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
1514
1515 dynamic->sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
1516 dynamic->sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
1517 dynamic->sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
1518 typed_memcpy(&dynamic->sample_location.locations[0],
1519 pSampleLocationsInfo->pSampleLocations,
1520 pSampleLocationsInfo->sampleLocationsCount);
1521 }
1522 }
1523
1524 pipeline->dynamic_state.mask = states;
1525 }
1526
1527 static void
1528 gfx9_get_gs_info(const struct radv_pipeline_key *key,
1529 const struct radv_pipeline *pipeline,
1530 nir_shader **nir,
1531 struct radv_shader_info *infos,
1532 struct gfx9_gs_info *out)
1533 {
1534 struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY];
1535 struct radv_es_output_info *es_info;
1536 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
1537 es_info = nir[MESA_SHADER_TESS_CTRL] ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1538 else
1539 es_info = nir[MESA_SHADER_TESS_CTRL] ?
1540 &infos[MESA_SHADER_TESS_EVAL].tes.es_info :
1541 &infos[MESA_SHADER_VERTEX].vs.es_info;
1542
1543 unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
1544 bool uses_adjacency;
1545 switch(key->topology) {
1546 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1547 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1548 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1549 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1550 uses_adjacency = true;
1551 break;
1552 default:
1553 uses_adjacency = false;
1554 break;
1555 }
1556
1557 /* All these are in dwords: */
1558 /* We can't allow using the whole LDS, because GS waves compete with
1559 * other shader stages for LDS space. */
1560 const unsigned max_lds_size = 8 * 1024;
1561 const unsigned esgs_itemsize = es_info->esgs_itemsize / 4;
1562 unsigned esgs_lds_size;
1563
1564 /* All these are per subgroup: */
1565 const unsigned max_out_prims = 32 * 1024;
1566 const unsigned max_es_verts = 255;
1567 const unsigned ideal_gs_prims = 64;
1568 unsigned max_gs_prims, gs_prims;
1569 unsigned min_es_verts, es_verts, worst_case_es_verts;
1570
1571 if (uses_adjacency || gs_num_invocations > 1)
1572 max_gs_prims = 127 / gs_num_invocations;
1573 else
1574 max_gs_prims = 255;
1575
1576 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1577 * Make sure we don't go over the maximum value.
1578 */
1579 if (gs_info->gs.vertices_out > 0) {
1580 max_gs_prims = MIN2(max_gs_prims,
1581 max_out_prims /
1582 (gs_info->gs.vertices_out * gs_num_invocations));
1583 }
1584 assert(max_gs_prims > 0);
1585
1586 /* If the primitive has adjacency, halve the number of vertices
1587 * that will be reused in multiple primitives.
1588 */
1589 min_es_verts = gs_info->gs.vertices_in / (uses_adjacency ? 2 : 1);
1590
1591 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
1592 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
1593
1594 /* Compute ESGS LDS size based on the worst case number of ES vertices
1595 * needed to create the target number of GS prims per subgroup.
1596 */
1597 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1598
1599 /* If total LDS usage is too big, refactor partitions based on ratio
1600 * of ESGS item sizes.
1601 */
1602 if (esgs_lds_size > max_lds_size) {
1603 /* Our target GS Prims Per Subgroup was too large. Calculate
1604 * the maximum number of GS Prims Per Subgroup that will fit
1605 * into LDS, capped by the maximum that the hardware can support.
1606 */
1607 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
1608 max_gs_prims);
1609 assert(gs_prims > 0);
1610 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
1611 max_es_verts);
1612
1613 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1614 assert(esgs_lds_size <= max_lds_size);
1615 }
1616
1617 /* Now calculate remaining ESGS information. */
1618 if (esgs_lds_size)
1619 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
1620 else
1621 es_verts = max_es_verts;
1622
1623 /* Vertices for adjacency primitives are not always reused, so restore
1624 * it for ES_VERTS_PER_SUBGRP.
1625 */
1626 min_es_verts = gs_info->gs.vertices_in;
1627
1628 /* For normal primitives, the VGT only checks if they are past the ES
1629 * verts per subgroup after allocating a full GS primitive and if they
1630 * are, kick off a new subgroup. But if those additional ES verts are
1631 * unique (e.g. not reused) we need to make sure there is enough LDS
1632 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1633 */
1634 es_verts -= min_es_verts - 1;
1635
1636 uint32_t es_verts_per_subgroup = es_verts;
1637 uint32_t gs_prims_per_subgroup = gs_prims;
1638 uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
1639 uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out;
1640 out->lds_size = align(esgs_lds_size, 128) / 128;
1641 out->vgt_gs_onchip_cntl = S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) |
1642 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) |
1643 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup);
1644 out->vgt_gs_max_prims_per_subgroup = S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup);
1645 out->vgt_esgs_ring_itemsize = esgs_itemsize;
1646 assert(max_prims_per_subgroup <= max_out_prims);
1647 }
1648
1649 static void clamp_gsprims_to_esverts(unsigned *max_gsprims, unsigned max_esverts,
1650 unsigned min_verts_per_prim, bool use_adjacency)
1651 {
1652 unsigned max_reuse = max_esverts - min_verts_per_prim;
1653 if (use_adjacency)
1654 max_reuse /= 2;
1655 *max_gsprims = MIN2(*max_gsprims, 1 + max_reuse);
1656 }
1657
1658 static unsigned
1659 radv_get_num_input_vertices(nir_shader **nir)
1660 {
1661 if (nir[MESA_SHADER_GEOMETRY]) {
1662 nir_shader *gs = nir[MESA_SHADER_GEOMETRY];
1663
1664 return gs->info.gs.vertices_in;
1665 }
1666
1667 if (nir[MESA_SHADER_TESS_CTRL]) {
1668 nir_shader *tes = nir[MESA_SHADER_TESS_EVAL];
1669
1670 if (tes->info.tess.point_mode)
1671 return 1;
1672 if (tes->info.tess.primitive_mode == GL_ISOLINES)
1673 return 2;
1674 return 3;
1675 }
1676
1677 return 3;
1678 }
1679
1680 static void
1681 gfx10_get_ngg_info(const struct radv_pipeline_key *key,
1682 struct radv_pipeline *pipeline,
1683 nir_shader **nir,
1684 struct radv_shader_info *infos,
1685 struct gfx10_ngg_info *ngg)
1686 {
1687 struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY];
1688 struct radv_es_output_info *es_info =
1689 nir[MESA_SHADER_TESS_CTRL] ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1690 unsigned gs_type = nir[MESA_SHADER_GEOMETRY] ? MESA_SHADER_GEOMETRY : MESA_SHADER_VERTEX;
1691 unsigned max_verts_per_prim = radv_get_num_input_vertices(nir);
1692 unsigned min_verts_per_prim =
1693 gs_type == MESA_SHADER_GEOMETRY ? max_verts_per_prim : 1;
1694 unsigned gs_num_invocations = nir[MESA_SHADER_GEOMETRY] ? MAX2(gs_info->gs.invocations, 1) : 1;
1695 bool uses_adjacency;
1696 switch(key->topology) {
1697 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1698 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1699 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1700 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1701 uses_adjacency = true;
1702 break;
1703 default:
1704 uses_adjacency = false;
1705 break;
1706 }
1707
1708 /* All these are in dwords: */
1709 /* We can't allow using the whole LDS, because GS waves compete with
1710 * other shader stages for LDS space.
1711 *
1712 * TODO: We should really take the shader's internal LDS use into
1713 * account. The linker will fail if the size is greater than
1714 * 8K dwords.
1715 */
1716 const unsigned max_lds_size = 8 * 1024 - 768;
1717 const unsigned target_lds_size = max_lds_size;
1718 unsigned esvert_lds_size = 0;
1719 unsigned gsprim_lds_size = 0;
1720
1721 /* All these are per subgroup: */
1722 bool max_vert_out_per_gs_instance = false;
1723 unsigned max_esverts_base = 256;
1724 unsigned max_gsprims_base = 128; /* default prim group size clamp */
1725
1726 /* Hardware has the following non-natural restrictions on the value
1727 * of GE_CNTL.VERT_GRP_SIZE based on based on the primitive type of
1728 * the draw:
1729 * - at most 252 for any line input primitive type
1730 * - at most 251 for any quad input primitive type
1731 * - at most 251 for triangle strips with adjacency (this happens to
1732 * be the natural limit for triangle *lists* with adjacency)
1733 */
1734 max_esverts_base = MIN2(max_esverts_base, 251 + max_verts_per_prim - 1);
1735
1736 if (gs_type == MESA_SHADER_GEOMETRY) {
1737 unsigned max_out_verts_per_gsprim =
1738 gs_info->gs.vertices_out * gs_num_invocations;
1739
1740 if (max_out_verts_per_gsprim <= 256) {
1741 if (max_out_verts_per_gsprim) {
1742 max_gsprims_base = MIN2(max_gsprims_base,
1743 256 / max_out_verts_per_gsprim);
1744 }
1745 } else {
1746 /* Use special multi-cycling mode in which each GS
1747 * instance gets its own subgroup. Does not work with
1748 * tessellation. */
1749 max_vert_out_per_gs_instance = true;
1750 max_gsprims_base = 1;
1751 max_out_verts_per_gsprim = gs_info->gs.vertices_out;
1752 }
1753
1754 esvert_lds_size = es_info->esgs_itemsize / 4;
1755 gsprim_lds_size = (gs_info->gs.gsvs_vertex_size / 4 + 1) * max_out_verts_per_gsprim;
1756 } else {
1757 /* VS and TES. */
1758 /* LDS size for passing data from GS to ES. */
1759 struct radv_streamout_info *so_info = nir[MESA_SHADER_TESS_CTRL]
1760 ? &infos[MESA_SHADER_TESS_EVAL].so
1761 : &infos[MESA_SHADER_VERTEX].so;
1762
1763 if (so_info->num_outputs)
1764 esvert_lds_size = 4 * so_info->num_outputs + 1;
1765
1766 /* GS stores Primitive IDs (one DWORD) into LDS at the address
1767 * corresponding to the ES thread of the provoking vertex. All
1768 * ES threads load and export PrimitiveID for their thread.
1769 */
1770 if (!nir[MESA_SHADER_TESS_CTRL] &&
1771 infos[MESA_SHADER_VERTEX].vs.outinfo.export_prim_id)
1772 esvert_lds_size = MAX2(esvert_lds_size, 1);
1773 }
1774
1775 unsigned max_gsprims = max_gsprims_base;
1776 unsigned max_esverts = max_esverts_base;
1777
1778 if (esvert_lds_size)
1779 max_esverts = MIN2(max_esverts, target_lds_size / esvert_lds_size);
1780 if (gsprim_lds_size)
1781 max_gsprims = MIN2(max_gsprims, target_lds_size / gsprim_lds_size);
1782
1783 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1784 clamp_gsprims_to_esverts(&max_gsprims, max_esverts, min_verts_per_prim, uses_adjacency);
1785 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1786
1787 if (esvert_lds_size || gsprim_lds_size) {
1788 /* Now that we have a rough proportionality between esverts
1789 * and gsprims based on the primitive type, scale both of them
1790 * down simultaneously based on required LDS space.
1791 *
1792 * We could be smarter about this if we knew how much vertex
1793 * reuse to expect.
1794 */
1795 unsigned lds_total = max_esverts * esvert_lds_size +
1796 max_gsprims * gsprim_lds_size;
1797 if (lds_total > target_lds_size) {
1798 max_esverts = max_esverts * target_lds_size / lds_total;
1799 max_gsprims = max_gsprims * target_lds_size / lds_total;
1800
1801 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1802 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1803 min_verts_per_prim, uses_adjacency);
1804 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1805 }
1806 }
1807
1808 /* Round up towards full wave sizes for better ALU utilization. */
1809 if (!max_vert_out_per_gs_instance) {
1810 unsigned orig_max_esverts;
1811 unsigned orig_max_gsprims;
1812 unsigned wavesize;
1813
1814 if (gs_type == MESA_SHADER_GEOMETRY) {
1815 wavesize = gs_info->wave_size;
1816 } else {
1817 wavesize = nir[MESA_SHADER_TESS_CTRL]
1818 ? infos[MESA_SHADER_TESS_EVAL].wave_size
1819 : infos[MESA_SHADER_VERTEX].wave_size;
1820 }
1821
1822 do {
1823 orig_max_esverts = max_esverts;
1824 orig_max_gsprims = max_gsprims;
1825
1826 max_esverts = align(max_esverts, wavesize);
1827 max_esverts = MIN2(max_esverts, max_esverts_base);
1828 if (esvert_lds_size)
1829 max_esverts = MIN2(max_esverts,
1830 (max_lds_size - max_gsprims * gsprim_lds_size) /
1831 esvert_lds_size);
1832 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1833
1834 max_gsprims = align(max_gsprims, wavesize);
1835 max_gsprims = MIN2(max_gsprims, max_gsprims_base);
1836 if (gsprim_lds_size)
1837 max_gsprims = MIN2(max_gsprims,
1838 (max_lds_size - max_esverts * esvert_lds_size) /
1839 gsprim_lds_size);
1840 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1841 min_verts_per_prim, uses_adjacency);
1842 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1843 } while (orig_max_esverts != max_esverts || orig_max_gsprims != max_gsprims);
1844 }
1845
1846 /* Hardware restriction: minimum value of max_esverts */
1847 max_esverts = MAX2(max_esverts, 23 + max_verts_per_prim);
1848
1849 unsigned max_out_vertices =
1850 max_vert_out_per_gs_instance ? gs_info->gs.vertices_out :
1851 gs_type == MESA_SHADER_GEOMETRY ?
1852 max_gsprims * gs_num_invocations * gs_info->gs.vertices_out :
1853 max_esverts;
1854 assert(max_out_vertices <= 256);
1855
1856 unsigned prim_amp_factor = 1;
1857 if (gs_type == MESA_SHADER_GEOMETRY) {
1858 /* Number of output primitives per GS input primitive after
1859 * GS instancing. */
1860 prim_amp_factor = gs_info->gs.vertices_out;
1861 }
1862
1863 /* The GE only checks against the maximum number of ES verts after
1864 * allocating a full GS primitive. So we need to ensure that whenever
1865 * this check passes, there is enough space for a full primitive without
1866 * vertex reuse.
1867 */
1868 ngg->hw_max_esverts = max_esverts - max_verts_per_prim + 1;
1869 ngg->max_gsprims = max_gsprims;
1870 ngg->max_out_verts = max_out_vertices;
1871 ngg->prim_amp_factor = prim_amp_factor;
1872 ngg->max_vert_out_per_gs_instance = max_vert_out_per_gs_instance;
1873 ngg->ngg_emit_size = max_gsprims * gsprim_lds_size;
1874 ngg->esgs_ring_size = 4 * max_esverts * esvert_lds_size;
1875
1876 if (gs_type == MESA_SHADER_GEOMETRY) {
1877 ngg->vgt_esgs_ring_itemsize = es_info->esgs_itemsize / 4;
1878 } else {
1879 ngg->vgt_esgs_ring_itemsize = 1;
1880 }
1881
1882 pipeline->graphics.esgs_ring_size = ngg->esgs_ring_size;
1883
1884 assert(ngg->hw_max_esverts >= 24); /* HW limitation */
1885 }
1886
1887 static void
1888 calculate_gs_ring_sizes(struct radv_pipeline *pipeline,
1889 const struct gfx9_gs_info *gs)
1890 {
1891 struct radv_device *device = pipeline->device;
1892 unsigned num_se = device->physical_device->rad_info.max_se;
1893 unsigned wave_size = 64;
1894 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1895 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
1896 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
1897 */
1898 unsigned gs_vertex_reuse =
1899 (device->physical_device->rad_info.chip_class >= GFX8 ? 32 : 16) * num_se;
1900 unsigned alignment = 256 * num_se;
1901 /* The maximum size is 63.999 MB per SE. */
1902 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1903 struct radv_shader_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1904
1905 /* Calculate the minimum size. */
1906 unsigned min_esgs_ring_size = align(gs->vgt_esgs_ring_itemsize * 4 * gs_vertex_reuse *
1907 wave_size, alignment);
1908 /* These are recommended sizes, not minimum sizes. */
1909 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1910 gs->vgt_esgs_ring_itemsize * 4 * gs_info->gs.vertices_in;
1911 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1912 gs_info->gs.max_gsvs_emit_size;
1913
1914 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1915 esgs_ring_size = align(esgs_ring_size, alignment);
1916 gsvs_ring_size = align(gsvs_ring_size, alignment);
1917
1918 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
1919 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1920
1921 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1922 }
1923
1924 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1925 unsigned *lds_size)
1926 {
1927 /* If tessellation is all offchip and on-chip GS isn't used, this
1928 * workaround is not needed.
1929 */
1930 return;
1931
1932 /* SPI barrier management bug:
1933 * Make sure we have at least 4k of LDS in use to avoid the bug.
1934 * It applies to workgroup sizes of more than one wavefront.
1935 */
1936 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1937 device->physical_device->rad_info.family == CHIP_KABINI)
1938 *lds_size = MAX2(*lds_size, 8);
1939 }
1940
1941 struct radv_shader_variant *
1942 radv_get_shader(struct radv_pipeline *pipeline,
1943 gl_shader_stage stage)
1944 {
1945 if (stage == MESA_SHADER_VERTEX) {
1946 if (pipeline->shaders[MESA_SHADER_VERTEX])
1947 return pipeline->shaders[MESA_SHADER_VERTEX];
1948 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
1949 return pipeline->shaders[MESA_SHADER_TESS_CTRL];
1950 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1951 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1952 } else if (stage == MESA_SHADER_TESS_EVAL) {
1953 if (!radv_pipeline_has_tess(pipeline))
1954 return NULL;
1955 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
1956 return pipeline->shaders[MESA_SHADER_TESS_EVAL];
1957 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1958 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1959 }
1960 return pipeline->shaders[stage];
1961 }
1962
1963 static struct radv_tessellation_state
1964 calculate_tess_state(struct radv_pipeline *pipeline,
1965 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1966 {
1967 unsigned num_tcs_input_cp;
1968 unsigned num_tcs_output_cp;
1969 unsigned lds_size;
1970 unsigned num_patches;
1971 struct radv_tessellation_state tess = {0};
1972
1973 num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1974 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1975 num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
1976
1977 lds_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.lds_size;
1978
1979 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
1980 assert(lds_size <= 65536);
1981 lds_size = align(lds_size, 512) / 512;
1982 } else {
1983 assert(lds_size <= 32768);
1984 lds_size = align(lds_size, 256) / 256;
1985 }
1986 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1987
1988 tess.lds_size = lds_size;
1989
1990 tess.ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1991 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1992 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1993 tess.num_patches = num_patches;
1994
1995 struct radv_shader_variant *tes = radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL);
1996 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1997
1998 switch (tes->info.tes.primitive_mode) {
1999 case GL_TRIANGLES:
2000 type = V_028B6C_TESS_TRIANGLE;
2001 break;
2002 case GL_QUADS:
2003 type = V_028B6C_TESS_QUAD;
2004 break;
2005 case GL_ISOLINES:
2006 type = V_028B6C_TESS_ISOLINE;
2007 break;
2008 }
2009
2010 switch (tes->info.tes.spacing) {
2011 case TESS_SPACING_EQUAL:
2012 partitioning = V_028B6C_PART_INTEGER;
2013 break;
2014 case TESS_SPACING_FRACTIONAL_ODD:
2015 partitioning = V_028B6C_PART_FRAC_ODD;
2016 break;
2017 case TESS_SPACING_FRACTIONAL_EVEN:
2018 partitioning = V_028B6C_PART_FRAC_EVEN;
2019 break;
2020 default:
2021 break;
2022 }
2023
2024 bool ccw = tes->info.tes.ccw;
2025 const VkPipelineTessellationDomainOriginStateCreateInfo *domain_origin_state =
2026 vk_find_struct_const(pCreateInfo->pTessellationState,
2027 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO);
2028
2029 if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT)
2030 ccw = !ccw;
2031
2032 if (tes->info.tes.point_mode)
2033 topology = V_028B6C_OUTPUT_POINT;
2034 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
2035 topology = V_028B6C_OUTPUT_LINE;
2036 else if (ccw)
2037 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
2038 else
2039 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
2040
2041 if (pipeline->device->physical_device->rad_info.has_distributed_tess) {
2042 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
2043 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
2044 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
2045 else
2046 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
2047 } else
2048 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
2049
2050 tess.tf_param = S_028B6C_TYPE(type) |
2051 S_028B6C_PARTITIONING(partitioning) |
2052 S_028B6C_TOPOLOGY(topology) |
2053 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
2054
2055 return tess;
2056 }
2057
2058 static const struct radv_prim_vertex_count prim_size_table[] = {
2059 [V_008958_DI_PT_NONE] = {0, 0},
2060 [V_008958_DI_PT_POINTLIST] = {1, 1},
2061 [V_008958_DI_PT_LINELIST] = {2, 2},
2062 [V_008958_DI_PT_LINESTRIP] = {2, 1},
2063 [V_008958_DI_PT_TRILIST] = {3, 3},
2064 [V_008958_DI_PT_TRIFAN] = {3, 1},
2065 [V_008958_DI_PT_TRISTRIP] = {3, 1},
2066 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
2067 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
2068 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
2069 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
2070 [V_008958_DI_PT_RECTLIST] = {3, 3},
2071 [V_008958_DI_PT_LINELOOP] = {2, 1},
2072 [V_008958_DI_PT_POLYGON] = {3, 1},
2073 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
2074 };
2075
2076 static const struct radv_vs_output_info *get_vs_output_info(const struct radv_pipeline *pipeline)
2077 {
2078 if (radv_pipeline_has_gs(pipeline))
2079 if (radv_pipeline_has_ngg(pipeline))
2080 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.vs.outinfo;
2081 else
2082 return &pipeline->gs_copy_shader->info.vs.outinfo;
2083 else if (radv_pipeline_has_tess(pipeline))
2084 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
2085 else
2086 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
2087 }
2088
2089 static void
2090 radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
2091 {
2092 nir_shader* ordered_shaders[MESA_SHADER_STAGES];
2093 int shader_count = 0;
2094
2095 if(shaders[MESA_SHADER_FRAGMENT]) {
2096 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
2097 }
2098 if(shaders[MESA_SHADER_GEOMETRY]) {
2099 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
2100 }
2101 if(shaders[MESA_SHADER_TESS_EVAL]) {
2102 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
2103 }
2104 if(shaders[MESA_SHADER_TESS_CTRL]) {
2105 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
2106 }
2107 if(shaders[MESA_SHADER_VERTEX]) {
2108 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
2109 }
2110
2111 if (shader_count > 1) {
2112 unsigned first = ordered_shaders[shader_count - 1]->info.stage;
2113 unsigned last = ordered_shaders[0]->info.stage;
2114
2115 if (ordered_shaders[0]->info.stage == MESA_SHADER_FRAGMENT &&
2116 ordered_shaders[1]->info.has_transform_feedback_varyings)
2117 nir_link_xfb_varyings(ordered_shaders[1], ordered_shaders[0]);
2118
2119 for (int i = 0; i < shader_count; ++i) {
2120 nir_variable_mode mask = 0;
2121
2122 if (ordered_shaders[i]->info.stage != first)
2123 mask = mask | nir_var_shader_in;
2124
2125 if (ordered_shaders[i]->info.stage != last)
2126 mask = mask | nir_var_shader_out;
2127
2128 nir_lower_io_to_scalar_early(ordered_shaders[i], mask);
2129 radv_optimize_nir(ordered_shaders[i], false, false);
2130 }
2131 }
2132
2133 for (int i = 1; i < shader_count; ++i) {
2134 nir_lower_io_arrays_to_elements(ordered_shaders[i],
2135 ordered_shaders[i - 1]);
2136
2137 if (nir_link_opt_varyings(ordered_shaders[i],
2138 ordered_shaders[i - 1]))
2139 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2140
2141 nir_remove_dead_variables(ordered_shaders[i],
2142 nir_var_shader_out);
2143 nir_remove_dead_variables(ordered_shaders[i - 1],
2144 nir_var_shader_in);
2145
2146 bool progress = nir_remove_unused_varyings(ordered_shaders[i],
2147 ordered_shaders[i - 1]);
2148
2149 nir_compact_varyings(ordered_shaders[i],
2150 ordered_shaders[i - 1], true);
2151
2152 if (progress) {
2153 if (nir_lower_global_vars_to_local(ordered_shaders[i])) {
2154 ac_lower_indirect_derefs(ordered_shaders[i],
2155 pipeline->device->physical_device->rad_info.chip_class);
2156 }
2157 radv_optimize_nir(ordered_shaders[i], false, false);
2158
2159 if (nir_lower_global_vars_to_local(ordered_shaders[i - 1])) {
2160 ac_lower_indirect_derefs(ordered_shaders[i - 1],
2161 pipeline->device->physical_device->rad_info.chip_class);
2162 }
2163 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2164 }
2165 }
2166 }
2167
2168 static uint32_t
2169 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo *input_state,
2170 uint32_t attrib_binding)
2171 {
2172 for (uint32_t i = 0; i < input_state->vertexBindingDescriptionCount; i++) {
2173 const VkVertexInputBindingDescription *input_binding =
2174 &input_state->pVertexBindingDescriptions[i];
2175
2176 if (input_binding->binding == attrib_binding)
2177 return input_binding->stride;
2178 }
2179
2180 return 0;
2181 }
2182
2183 static struct radv_pipeline_key
2184 radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
2185 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2186 const struct radv_blend_state *blend,
2187 bool has_view_index)
2188 {
2189 const VkPipelineVertexInputStateCreateInfo *input_state =
2190 pCreateInfo->pVertexInputState;
2191 const VkPipelineVertexInputDivisorStateCreateInfoEXT *divisor_state =
2192 vk_find_struct_const(input_state->pNext, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT);
2193
2194 struct radv_pipeline_key key;
2195 memset(&key, 0, sizeof(key));
2196
2197 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
2198 key.optimisations_disabled = 1;
2199
2200 key.has_multiview_view_index = has_view_index;
2201
2202 uint32_t binding_input_rate = 0;
2203 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
2204 for (unsigned i = 0; i < input_state->vertexBindingDescriptionCount; ++i) {
2205 if (input_state->pVertexBindingDescriptions[i].inputRate) {
2206 unsigned binding = input_state->pVertexBindingDescriptions[i].binding;
2207 binding_input_rate |= 1u << binding;
2208 instance_rate_divisors[binding] = 1;
2209 }
2210 }
2211 if (divisor_state) {
2212 for (unsigned i = 0; i < divisor_state->vertexBindingDivisorCount; ++i) {
2213 instance_rate_divisors[divisor_state->pVertexBindingDivisors[i].binding] =
2214 divisor_state->pVertexBindingDivisors[i].divisor;
2215 }
2216 }
2217
2218 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
2219 const VkVertexInputAttributeDescription *desc =
2220 &input_state->pVertexAttributeDescriptions[i];
2221 const struct vk_format_description *format_desc;
2222 unsigned location = desc->location;
2223 unsigned binding = desc->binding;
2224 unsigned num_format, data_format;
2225 int first_non_void;
2226
2227 if (binding_input_rate & (1u << binding)) {
2228 key.instance_rate_inputs |= 1u << location;
2229 key.instance_rate_divisors[location] = instance_rate_divisors[binding];
2230 }
2231
2232 format_desc = vk_format_description(desc->format);
2233 first_non_void = vk_format_get_first_non_void_channel(desc->format);
2234
2235 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
2236 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
2237
2238 key.vertex_attribute_formats[location] = data_format | (num_format << 4);
2239 key.vertex_attribute_bindings[location] = desc->binding;
2240 key.vertex_attribute_offsets[location] = desc->offset;
2241 key.vertex_attribute_strides[location] = radv_get_attrib_stride(input_state, desc->binding);
2242
2243 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8 &&
2244 pipeline->device->physical_device->rad_info.family != CHIP_STONEY) {
2245 VkFormat format = input_state->pVertexAttributeDescriptions[i].format;
2246 uint64_t adjust;
2247 switch(format) {
2248 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2249 case VK_FORMAT_A2B10G10R10_SNORM_PACK32:
2250 adjust = RADV_ALPHA_ADJUST_SNORM;
2251 break;
2252 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2253 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32:
2254 adjust = RADV_ALPHA_ADJUST_SSCALED;
2255 break;
2256 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2257 case VK_FORMAT_A2B10G10R10_SINT_PACK32:
2258 adjust = RADV_ALPHA_ADJUST_SINT;
2259 break;
2260 default:
2261 adjust = 0;
2262 break;
2263 }
2264 key.vertex_alpha_adjust |= adjust << (2 * location);
2265 }
2266
2267 switch (desc->format) {
2268 case VK_FORMAT_B8G8R8A8_UNORM:
2269 case VK_FORMAT_B8G8R8A8_SNORM:
2270 case VK_FORMAT_B8G8R8A8_USCALED:
2271 case VK_FORMAT_B8G8R8A8_SSCALED:
2272 case VK_FORMAT_B8G8R8A8_UINT:
2273 case VK_FORMAT_B8G8R8A8_SINT:
2274 case VK_FORMAT_B8G8R8A8_SRGB:
2275 case VK_FORMAT_A2R10G10B10_UNORM_PACK32:
2276 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2277 case VK_FORMAT_A2R10G10B10_USCALED_PACK32:
2278 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2279 case VK_FORMAT_A2R10G10B10_UINT_PACK32:
2280 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2281 key.vertex_post_shuffle |= 1 << location;
2282 break;
2283 default:
2284 break;
2285 }
2286 }
2287
2288 const VkPipelineTessellationStateCreateInfo *tess =
2289 radv_pipeline_get_tessellation_state(pCreateInfo);
2290 if (tess)
2291 key.tess_input_vertices = tess->patchControlPoints;
2292
2293 const VkPipelineMultisampleStateCreateInfo *vkms =
2294 radv_pipeline_get_multisample_state(pCreateInfo);
2295 if (vkms && vkms->rasterizationSamples > 1) {
2296 uint32_t num_samples = vkms->rasterizationSamples;
2297 uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(vkms);
2298 key.num_samples = num_samples;
2299 key.log2_ps_iter_samples = util_logbase2(ps_iter_samples);
2300 }
2301
2302 key.col_format = blend->spi_shader_col_format;
2303 if (pipeline->device->physical_device->rad_info.chip_class < GFX8)
2304 radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.is_int8, &key.is_int10);
2305
2306 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10)
2307 key.topology = pCreateInfo->pInputAssemblyState->topology;
2308
2309 return key;
2310 }
2311
2312 static bool
2313 radv_nir_stage_uses_xfb(const nir_shader *nir)
2314 {
2315 nir_xfb_info *xfb = nir_gather_xfb_info(nir, NULL);
2316 bool uses_xfb = !!xfb;
2317
2318 ralloc_free(xfb);
2319 return uses_xfb;
2320 }
2321
2322 static void
2323 radv_fill_shader_keys(struct radv_device *device,
2324 struct radv_shader_variant_key *keys,
2325 const struct radv_pipeline_key *key,
2326 nir_shader **nir)
2327 {
2328 keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
2329 keys[MESA_SHADER_VERTEX].vs.alpha_adjust = key->vertex_alpha_adjust;
2330 keys[MESA_SHADER_VERTEX].vs.post_shuffle = key->vertex_post_shuffle;
2331 for (unsigned i = 0; i < MAX_VERTEX_ATTRIBS; ++i) {
2332 keys[MESA_SHADER_VERTEX].vs.instance_rate_divisors[i] = key->instance_rate_divisors[i];
2333 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_formats[i] = key->vertex_attribute_formats[i];
2334 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_bindings[i] = key->vertex_attribute_bindings[i];
2335 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_offsets[i] = key->vertex_attribute_offsets[i];
2336 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_strides[i] = key->vertex_attribute_strides[i];
2337 }
2338 keys[MESA_SHADER_VERTEX].vs.outprim = si_conv_prim_to_gs_out(key->topology);
2339
2340 if (nir[MESA_SHADER_TESS_CTRL]) {
2341 keys[MESA_SHADER_VERTEX].vs_common_out.as_ls = true;
2342 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = 0;
2343 keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices;
2344 keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
2345
2346 keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
2347 }
2348
2349 if (nir[MESA_SHADER_GEOMETRY]) {
2350 if (nir[MESA_SHADER_TESS_CTRL])
2351 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_es = true;
2352 else
2353 keys[MESA_SHADER_VERTEX].vs_common_out.as_es = true;
2354 }
2355
2356 if (device->physical_device->use_ngg) {
2357 if (nir[MESA_SHADER_TESS_CTRL]) {
2358 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = true;
2359 } else {
2360 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = true;
2361 }
2362
2363 if (nir[MESA_SHADER_TESS_CTRL] &&
2364 nir[MESA_SHADER_GEOMETRY] &&
2365 nir[MESA_SHADER_GEOMETRY]->info.gs.invocations *
2366 nir[MESA_SHADER_GEOMETRY]->info.gs.vertices_out > 256) {
2367 /* Fallback to the legacy path if tessellation is
2368 * enabled with extreme geometry because
2369 * EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it
2370 * might hang.
2371 */
2372 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2373 }
2374
2375 /*
2376 * Disable NGG with geometry shaders. There are a bunch of
2377 * issues still:
2378 * * GS primitives in pipeline statistic queries do not get
2379 * updates. See dEQP-VK.query_pool.statistics_query.geometry_shader_primitives
2380 *
2381 * Furthermore, XGL/AMDVLK also disables this as of 9b632ef.
2382 */
2383 if (nir[MESA_SHADER_GEOMETRY]) {
2384 if (nir[MESA_SHADER_TESS_CTRL])
2385 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2386 else
2387 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2388 }
2389
2390 if (!device->physical_device->use_ngg_streamout) {
2391 gl_shader_stage last_xfb_stage = MESA_SHADER_VERTEX;
2392
2393 for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
2394 if (nir[i])
2395 last_xfb_stage = i;
2396 }
2397
2398 if (nir[last_xfb_stage] &&
2399 radv_nir_stage_uses_xfb(nir[last_xfb_stage])) {
2400 if (nir[MESA_SHADER_TESS_CTRL])
2401 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2402 else
2403 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2404 }
2405 }
2406 }
2407
2408 for(int i = 0; i < MESA_SHADER_STAGES; ++i)
2409 keys[i].has_multiview_view_index = key->has_multiview_view_index;
2410
2411 keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format;
2412 keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8;
2413 keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
2414 keys[MESA_SHADER_FRAGMENT].fs.log2_ps_iter_samples = key->log2_ps_iter_samples;
2415 keys[MESA_SHADER_FRAGMENT].fs.num_samples = key->num_samples;
2416
2417 if (nir[MESA_SHADER_COMPUTE]) {
2418 keys[MESA_SHADER_COMPUTE].cs.subgroup_size = key->compute_subgroup_size;
2419 }
2420 }
2421
2422 static uint8_t
2423 radv_get_wave_size(struct radv_device *device,
2424 const VkPipelineShaderStageCreateInfo *pStage,
2425 gl_shader_stage stage,
2426 const struct radv_shader_variant_key *key)
2427 {
2428 if (stage == MESA_SHADER_GEOMETRY && !key->vs_common_out.as_ngg)
2429 return 64;
2430 else if (stage == MESA_SHADER_COMPUTE) {
2431 if (key->cs.subgroup_size) {
2432 /* Return the required subgroup size if specified. */
2433 return key->cs.subgroup_size;
2434 }
2435 return device->physical_device->cs_wave_size;
2436 }
2437 else if (stage == MESA_SHADER_FRAGMENT)
2438 return device->physical_device->ps_wave_size;
2439 else
2440 return device->physical_device->ge_wave_size;
2441 }
2442
2443 static void
2444 radv_fill_shader_info(struct radv_pipeline *pipeline,
2445 const VkPipelineShaderStageCreateInfo **pStages,
2446 struct radv_shader_variant_key *keys,
2447 struct radv_shader_info *infos,
2448 nir_shader **nir)
2449 {
2450 unsigned active_stages = 0;
2451 unsigned filled_stages = 0;
2452
2453 for (int i = 0; i < MESA_SHADER_STAGES; i++) {
2454 if (nir[i])
2455 active_stages |= (1 << i);
2456 }
2457
2458 if (nir[MESA_SHADER_FRAGMENT]) {
2459 radv_nir_shader_info_init(&infos[MESA_SHADER_FRAGMENT]);
2460 radv_nir_shader_info_pass(nir[MESA_SHADER_FRAGMENT],
2461 pipeline->layout,
2462 &keys[MESA_SHADER_FRAGMENT],
2463 &infos[MESA_SHADER_FRAGMENT]);
2464
2465 /* TODO: These are no longer used as keys we should refactor this */
2466 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id =
2467 infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
2468 keys[MESA_SHADER_VERTEX].vs_common_out.export_layer_id =
2469 infos[MESA_SHADER_FRAGMENT].ps.layer_input;
2470 keys[MESA_SHADER_VERTEX].vs_common_out.export_clip_dists =
2471 !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
2472 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_prim_id =
2473 infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
2474 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_layer_id =
2475 infos[MESA_SHADER_FRAGMENT].ps.layer_input;
2476 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_clip_dists =
2477 !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
2478
2479 filled_stages |= (1 << MESA_SHADER_FRAGMENT);
2480 }
2481
2482 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
2483 nir[MESA_SHADER_TESS_CTRL]) {
2484 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2485 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2486 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2487
2488 radv_nir_shader_info_init(&infos[MESA_SHADER_TESS_CTRL]);
2489
2490 for (int i = 0; i < 2; i++) {
2491 radv_nir_shader_info_pass(combined_nir[i],
2492 pipeline->layout, &key,
2493 &infos[MESA_SHADER_TESS_CTRL]);
2494 }
2495
2496 keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
2497 infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
2498 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs =
2499 util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written);
2500
2501 filled_stages |= (1 << MESA_SHADER_VERTEX);
2502 filled_stages |= (1 << MESA_SHADER_TESS_CTRL);
2503 }
2504
2505 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
2506 nir[MESA_SHADER_GEOMETRY]) {
2507 gl_shader_stage pre_stage = nir[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2508 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2509
2510 radv_nir_shader_info_init(&infos[MESA_SHADER_GEOMETRY]);
2511
2512 for (int i = 0; i < 2; i++) {
2513 radv_nir_shader_info_pass(combined_nir[i],
2514 pipeline->layout,
2515 &keys[pre_stage],
2516 &infos[MESA_SHADER_GEOMETRY]);
2517 }
2518
2519 filled_stages |= (1 << pre_stage);
2520 filled_stages |= (1 << MESA_SHADER_GEOMETRY);
2521 }
2522
2523 active_stages ^= filled_stages;
2524 while (active_stages) {
2525 int i = u_bit_scan(&active_stages);
2526
2527 if (i == MESA_SHADER_TESS_CTRL) {
2528 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs =
2529 util_last_bit64(infos[MESA_SHADER_VERTEX].vs.ls_outputs_written);
2530 }
2531
2532 if (i == MESA_SHADER_TESS_EVAL) {
2533 keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
2534 infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
2535 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs =
2536 util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written);
2537 }
2538
2539 radv_nir_shader_info_init(&infos[i]);
2540 radv_nir_shader_info_pass(nir[i], pipeline->layout,
2541 &keys[i], &infos[i]);
2542 }
2543
2544 for (int i = 0; i < MESA_SHADER_STAGES; i++) {
2545 if (nir[i])
2546 infos[i].wave_size =
2547 radv_get_wave_size(pipeline->device, pStages[i],
2548 i, &keys[i]);
2549 }
2550 }
2551
2552 static void
2553 merge_tess_info(struct shader_info *tes_info,
2554 const struct shader_info *tcs_info)
2555 {
2556 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2557 *
2558 * "PointMode. Controls generation of points rather than triangles
2559 * or lines. This functionality defaults to disabled, and is
2560 * enabled if either shader stage includes the execution mode.
2561 *
2562 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2563 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2564 * and OutputVertices, it says:
2565 *
2566 * "One mode must be set in at least one of the tessellation
2567 * shader stages."
2568 *
2569 * So, the fields can be set in either the TCS or TES, but they must
2570 * agree if set in both. Our backend looks at TES, so bitwise-or in
2571 * the values from the TCS.
2572 */
2573 assert(tcs_info->tess.tcs_vertices_out == 0 ||
2574 tes_info->tess.tcs_vertices_out == 0 ||
2575 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
2576 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
2577
2578 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2579 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2580 tcs_info->tess.spacing == tes_info->tess.spacing);
2581 tes_info->tess.spacing |= tcs_info->tess.spacing;
2582
2583 assert(tcs_info->tess.primitive_mode == 0 ||
2584 tes_info->tess.primitive_mode == 0 ||
2585 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
2586 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
2587 tes_info->tess.ccw |= tcs_info->tess.ccw;
2588 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
2589 }
2590
2591 static
2592 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT *ext)
2593 {
2594 if (!ext)
2595 return;
2596
2597 if (ext->pPipelineCreationFeedback) {
2598 ext->pPipelineCreationFeedback->flags = 0;
2599 ext->pPipelineCreationFeedback->duration = 0;
2600 }
2601
2602 for (unsigned i = 0; i < ext->pipelineStageCreationFeedbackCount; ++i) {
2603 ext->pPipelineStageCreationFeedbacks[i].flags = 0;
2604 ext->pPipelineStageCreationFeedbacks[i].duration = 0;
2605 }
2606 }
2607
2608 static
2609 void radv_start_feedback(VkPipelineCreationFeedbackEXT *feedback)
2610 {
2611 if (!feedback)
2612 return;
2613
2614 feedback->duration -= radv_get_current_time();
2615 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT;
2616 }
2617
2618 static
2619 void radv_stop_feedback(VkPipelineCreationFeedbackEXT *feedback, bool cache_hit)
2620 {
2621 if (!feedback)
2622 return;
2623
2624 feedback->duration += radv_get_current_time();
2625 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT |
2626 (cache_hit ? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT : 0);
2627 }
2628
2629 static
2630 bool radv_aco_supported_stage(gl_shader_stage stage, bool has_gs, bool has_ts)
2631 {
2632 return (stage == MESA_SHADER_VERTEX && !has_gs && !has_ts) ||
2633 stage == MESA_SHADER_FRAGMENT ||
2634 stage == MESA_SHADER_COMPUTE;
2635 }
2636
2637 void radv_create_shaders(struct radv_pipeline *pipeline,
2638 struct radv_device *device,
2639 struct radv_pipeline_cache *cache,
2640 const struct radv_pipeline_key *key,
2641 const VkPipelineShaderStageCreateInfo **pStages,
2642 const VkPipelineCreateFlags flags,
2643 VkPipelineCreationFeedbackEXT *pipeline_feedback,
2644 VkPipelineCreationFeedbackEXT **stage_feedbacks)
2645 {
2646 struct radv_shader_module fs_m = {0};
2647 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
2648 nir_shader *nir[MESA_SHADER_STAGES] = {0};
2649 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2650 struct radv_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{{0}}}}};
2651 struct radv_shader_info infos[MESA_SHADER_STAGES] = {0};
2652 unsigned char hash[20], gs_copy_hash[20];
2653 bool keep_executable_info = (flags & VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR) || device->keep_shader_info;
2654
2655 radv_start_feedback(pipeline_feedback);
2656
2657 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2658 if (pStages[i]) {
2659 modules[i] = radv_shader_module_from_handle(pStages[i]->module);
2660 if (modules[i]->nir)
2661 _mesa_sha1_compute(modules[i]->nir->info.name,
2662 strlen(modules[i]->nir->info.name),
2663 modules[i]->sha1);
2664
2665 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
2666 }
2667 }
2668
2669 radv_hash_shaders(hash, pStages, pipeline->layout, key, get_hash_flags(device));
2670 memcpy(gs_copy_hash, hash, 20);
2671 gs_copy_hash[0] ^= 1;
2672
2673 bool found_in_application_cache = true;
2674 if (modules[MESA_SHADER_GEOMETRY] && !keep_executable_info) {
2675 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2676 radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants,
2677 &found_in_application_cache);
2678 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
2679 }
2680
2681 if (!keep_executable_info &&
2682 radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders,
2683 &found_in_application_cache) &&
2684 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
2685 radv_stop_feedback(pipeline_feedback, found_in_application_cache);
2686 return;
2687 }
2688
2689 if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
2690 nir_builder fs_b;
2691 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
2692 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
2693 fs_m.nir = fs_b.shader;
2694 modules[MESA_SHADER_FRAGMENT] = &fs_m;
2695 }
2696
2697 bool has_gs = modules[MESA_SHADER_GEOMETRY];
2698 bool has_ts = modules[MESA_SHADER_TESS_CTRL] || modules[MESA_SHADER_TESS_EVAL];
2699 bool use_aco = device->physical_device->use_aco;
2700
2701 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2702 const VkPipelineShaderStageCreateInfo *stage = pStages[i];
2703
2704 if (!modules[i])
2705 continue;
2706
2707 radv_start_feedback(stage_feedbacks[i]);
2708
2709 bool aco = use_aco && radv_aco_supported_stage(i, has_gs, has_ts);
2710 nir[i] = radv_shader_compile_to_nir(device, modules[i],
2711 stage ? stage->pName : "main", i,
2712 stage ? stage->pSpecializationInfo : NULL,
2713 flags, pipeline->layout, aco);
2714
2715 /* We don't want to alter meta shaders IR directly so clone it
2716 * first.
2717 */
2718 if (nir[i]->info.name) {
2719 nir[i] = nir_shader_clone(NULL, nir[i]);
2720 }
2721
2722 radv_stop_feedback(stage_feedbacks[i], false);
2723 }
2724
2725 if (nir[MESA_SHADER_TESS_CTRL]) {
2726 nir_lower_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out, NULL);
2727 merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
2728 }
2729
2730 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
2731 radv_link_shaders(pipeline, nir);
2732
2733 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2734 if (nir[i]) {
2735 NIR_PASS_V(nir[i], nir_lower_non_uniform_access,
2736 nir_lower_non_uniform_ubo_access |
2737 nir_lower_non_uniform_ssbo_access |
2738 nir_lower_non_uniform_texture_access |
2739 nir_lower_non_uniform_image_access);
2740
2741 bool aco = use_aco && radv_aco_supported_stage(i, has_gs, has_ts);
2742 if (!aco)
2743 NIR_PASS_V(nir[i], nir_lower_bool_to_int32);
2744 }
2745
2746 if (radv_can_dump_shader(device, modules[i], false))
2747 nir_print_shader(nir[i], stderr);
2748 }
2749
2750 if (nir[MESA_SHADER_FRAGMENT])
2751 radv_lower_fs_io(nir[MESA_SHADER_FRAGMENT]);
2752
2753 radv_fill_shader_keys(device, keys, key, nir);
2754
2755 radv_fill_shader_info(pipeline, pStages, keys, infos, nir);
2756
2757 if ((nir[MESA_SHADER_VERTEX] &&
2758 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg) ||
2759 (nir[MESA_SHADER_TESS_EVAL] &&
2760 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg)) {
2761 struct gfx10_ngg_info *ngg_info;
2762
2763 if (nir[MESA_SHADER_GEOMETRY])
2764 ngg_info = &infos[MESA_SHADER_GEOMETRY].ngg_info;
2765 else if (nir[MESA_SHADER_TESS_CTRL])
2766 ngg_info = &infos[MESA_SHADER_TESS_EVAL].ngg_info;
2767 else
2768 ngg_info = &infos[MESA_SHADER_VERTEX].ngg_info;
2769
2770 gfx10_get_ngg_info(key, pipeline, nir, infos, ngg_info);
2771 } else if (nir[MESA_SHADER_GEOMETRY]) {
2772 struct gfx9_gs_info *gs_info =
2773 &infos[MESA_SHADER_GEOMETRY].gs_ring_info;
2774
2775 gfx9_get_gs_info(key, pipeline, nir, infos, gs_info);
2776 }
2777
2778 if (nir[MESA_SHADER_FRAGMENT]) {
2779 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
2780 radv_start_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT]);
2781
2782 bool aco = use_aco && radv_aco_supported_stage(MESA_SHADER_FRAGMENT, has_gs, has_ts);
2783 pipeline->shaders[MESA_SHADER_FRAGMENT] =
2784 radv_shader_variant_compile(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
2785 pipeline->layout, keys + MESA_SHADER_FRAGMENT,
2786 infos + MESA_SHADER_FRAGMENT,
2787 keep_executable_info, aco,
2788 &binaries[MESA_SHADER_FRAGMENT]);
2789
2790 radv_stop_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT], false);
2791 }
2792
2793 /* TODO: These are no longer used as keys we should refactor this */
2794 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id =
2795 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.prim_id_input;
2796 keys[MESA_SHADER_VERTEX].vs_common_out.export_layer_id =
2797 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.layer_input;
2798 keys[MESA_SHADER_VERTEX].vs_common_out.export_clip_dists =
2799 !!pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.num_input_clips_culls;
2800 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_prim_id =
2801 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.prim_id_input;
2802 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_layer_id =
2803 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.layer_input;
2804 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_clip_dists =
2805 !!pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.num_input_clips_culls;
2806 }
2807
2808 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
2809 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
2810 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2811 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2812 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2813
2814 radv_start_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL]);
2815
2816 pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_compile(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
2817 pipeline->layout,
2818 &key, &infos[MESA_SHADER_TESS_CTRL], keep_executable_info,
2819 false, &binaries[MESA_SHADER_TESS_CTRL]);
2820
2821 radv_stop_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL], false);
2822 }
2823 modules[MESA_SHADER_VERTEX] = NULL;
2824 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2825 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written);
2826 }
2827
2828 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
2829 gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2830 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
2831 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2832
2833 radv_start_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY]);
2834
2835 pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_compile(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
2836 pipeline->layout,
2837 &keys[pre_stage], &infos[MESA_SHADER_GEOMETRY], keep_executable_info,
2838 false, &binaries[MESA_SHADER_GEOMETRY]);
2839
2840 radv_stop_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY], false);
2841 }
2842 modules[pre_stage] = NULL;
2843 }
2844
2845 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2846 if(modules[i] && !pipeline->shaders[i]) {
2847 if (i == MESA_SHADER_TESS_CTRL) {
2848 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.ls_outputs_written);
2849 }
2850 if (i == MESA_SHADER_TESS_EVAL) {
2851 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2852 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written);
2853 }
2854
2855 radv_start_feedback(stage_feedbacks[i]);
2856
2857 bool aco = use_aco && radv_aco_supported_stage(i, has_gs, has_ts);
2858 pipeline->shaders[i] = radv_shader_variant_compile(device, modules[i], &nir[i], 1,
2859 pipeline->layout,
2860 keys + i, infos + i,keep_executable_info,
2861 aco, &binaries[i]);
2862
2863 radv_stop_feedback(stage_feedbacks[i], false);
2864 }
2865 }
2866
2867 if(modules[MESA_SHADER_GEOMETRY]) {
2868 struct radv_shader_binary *gs_copy_binary = NULL;
2869 if (!pipeline->gs_copy_shader &&
2870 !radv_pipeline_has_ngg(pipeline)) {
2871 struct radv_shader_info info = {};
2872 struct radv_shader_variant_key key = {};
2873
2874 key.has_multiview_view_index =
2875 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index;
2876
2877 radv_nir_shader_info_pass(nir[MESA_SHADER_GEOMETRY],
2878 pipeline->layout, &key,
2879 &info);
2880 info.wave_size = 64; /* Wave32 not supported. */
2881
2882 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
2883 device, nir[MESA_SHADER_GEOMETRY], &info,
2884 &gs_copy_binary, keep_executable_info,
2885 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
2886 }
2887
2888 if (!keep_executable_info && pipeline->gs_copy_shader) {
2889 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2890 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2891
2892 binaries[MESA_SHADER_GEOMETRY] = gs_copy_binary;
2893 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
2894
2895 radv_pipeline_cache_insert_shaders(device, cache,
2896 gs_copy_hash,
2897 variants,
2898 binaries);
2899 }
2900 free(gs_copy_binary);
2901 }
2902
2903 if (!keep_executable_info) {
2904 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
2905 binaries);
2906 }
2907
2908 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2909 free(binaries[i]);
2910 if (nir[i]) {
2911 ralloc_free(nir[i]);
2912
2913 if (radv_can_dump_shader_stats(device, modules[i]))
2914 radv_shader_dump_stats(device,
2915 pipeline->shaders[i],
2916 i, stderr);
2917 }
2918 }
2919
2920 if (fs_m.nir)
2921 ralloc_free(fs_m.nir);
2922
2923 radv_stop_feedback(pipeline_feedback, false);
2924 }
2925
2926 static uint32_t
2927 radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
2928 gl_shader_stage stage, enum chip_class chip_class)
2929 {
2930 bool has_gs = radv_pipeline_has_gs(pipeline);
2931 bool has_tess = radv_pipeline_has_tess(pipeline);
2932 bool has_ngg = radv_pipeline_has_ngg(pipeline);
2933
2934 switch (stage) {
2935 case MESA_SHADER_FRAGMENT:
2936 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
2937 case MESA_SHADER_VERTEX:
2938 if (has_tess) {
2939 if (chip_class >= GFX10) {
2940 return R_00B430_SPI_SHADER_USER_DATA_HS_0;
2941 } else if (chip_class == GFX9) {
2942 return R_00B430_SPI_SHADER_USER_DATA_LS_0;
2943 } else {
2944 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
2945 }
2946
2947 }
2948
2949 if (has_gs) {
2950 if (chip_class >= GFX10) {
2951 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
2952 } else {
2953 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
2954 }
2955 }
2956
2957 if (has_ngg)
2958 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
2959
2960 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
2961 case MESA_SHADER_GEOMETRY:
2962 return chip_class == GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
2963 R_00B230_SPI_SHADER_USER_DATA_GS_0;
2964 case MESA_SHADER_COMPUTE:
2965 return R_00B900_COMPUTE_USER_DATA_0;
2966 case MESA_SHADER_TESS_CTRL:
2967 return chip_class == GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
2968 R_00B430_SPI_SHADER_USER_DATA_HS_0;
2969 case MESA_SHADER_TESS_EVAL:
2970 if (has_gs) {
2971 return chip_class >= GFX10 ? R_00B230_SPI_SHADER_USER_DATA_GS_0 :
2972 R_00B330_SPI_SHADER_USER_DATA_ES_0;
2973 } else if (has_ngg) {
2974 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
2975 } else {
2976 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
2977 }
2978 default:
2979 unreachable("unknown shader");
2980 }
2981 }
2982
2983 struct radv_bin_size_entry {
2984 unsigned bpp;
2985 VkExtent2D extent;
2986 };
2987
2988 static VkExtent2D
2989 radv_gfx9_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
2990 {
2991 static const struct radv_bin_size_entry color_size_table[][3][9] = {
2992 {
2993 /* One RB / SE */
2994 {
2995 /* One shader engine */
2996 { 0, {128, 128}},
2997 { 1, { 64, 128}},
2998 { 2, { 32, 128}},
2999 { 3, { 16, 128}},
3000 { 17, { 0, 0}},
3001 { UINT_MAX, { 0, 0}},
3002 },
3003 {
3004 /* Two shader engines */
3005 { 0, {128, 128}},
3006 { 2, { 64, 128}},
3007 { 3, { 32, 128}},
3008 { 5, { 16, 128}},
3009 { 17, { 0, 0}},
3010 { UINT_MAX, { 0, 0}},
3011 },
3012 {
3013 /* Four shader engines */
3014 { 0, {128, 128}},
3015 { 3, { 64, 128}},
3016 { 5, { 16, 128}},
3017 { 17, { 0, 0}},
3018 { UINT_MAX, { 0, 0}},
3019 },
3020 },
3021 {
3022 /* Two RB / SE */
3023 {
3024 /* One shader engine */
3025 { 0, {128, 128}},
3026 { 2, { 64, 128}},
3027 { 3, { 32, 128}},
3028 { 5, { 16, 128}},
3029 { 33, { 0, 0}},
3030 { UINT_MAX, { 0, 0}},
3031 },
3032 {
3033 /* Two shader engines */
3034 { 0, {128, 128}},
3035 { 3, { 64, 128}},
3036 { 5, { 32, 128}},
3037 { 9, { 16, 128}},
3038 { 33, { 0, 0}},
3039 { UINT_MAX, { 0, 0}},
3040 },
3041 {
3042 /* Four shader engines */
3043 { 0, {256, 256}},
3044 { 2, {128, 256}},
3045 { 3, {128, 128}},
3046 { 5, { 64, 128}},
3047 { 9, { 16, 128}},
3048 { 33, { 0, 0}},
3049 { UINT_MAX, { 0, 0}},
3050 },
3051 },
3052 {
3053 /* Four RB / SE */
3054 {
3055 /* One shader engine */
3056 { 0, {128, 256}},
3057 { 2, {128, 128}},
3058 { 3, { 64, 128}},
3059 { 5, { 32, 128}},
3060 { 9, { 16, 128}},
3061 { 33, { 0, 0}},
3062 { UINT_MAX, { 0, 0}},
3063 },
3064 {
3065 /* Two shader engines */
3066 { 0, {256, 256}},
3067 { 2, {128, 256}},
3068 { 3, {128, 128}},
3069 { 5, { 64, 128}},
3070 { 9, { 32, 128}},
3071 { 17, { 16, 128}},
3072 { 33, { 0, 0}},
3073 { UINT_MAX, { 0, 0}},
3074 },
3075 {
3076 /* Four shader engines */
3077 { 0, {256, 512}},
3078 { 2, {256, 256}},
3079 { 3, {128, 256}},
3080 { 5, {128, 128}},
3081 { 9, { 64, 128}},
3082 { 17, { 16, 128}},
3083 { 33, { 0, 0}},
3084 { UINT_MAX, { 0, 0}},
3085 },
3086 },
3087 };
3088 static const struct radv_bin_size_entry ds_size_table[][3][9] = {
3089 {
3090 // One RB / SE
3091 {
3092 // One shader engine
3093 { 0, {128, 256}},
3094 { 2, {128, 128}},
3095 { 4, { 64, 128}},
3096 { 7, { 32, 128}},
3097 { 13, { 16, 128}},
3098 { 49, { 0, 0}},
3099 { UINT_MAX, { 0, 0}},
3100 },
3101 {
3102 // Two shader engines
3103 { 0, {256, 256}},
3104 { 2, {128, 256}},
3105 { 4, {128, 128}},
3106 { 7, { 64, 128}},
3107 { 13, { 32, 128}},
3108 { 25, { 16, 128}},
3109 { 49, { 0, 0}},
3110 { UINT_MAX, { 0, 0}},
3111 },
3112 {
3113 // Four shader engines
3114 { 0, {256, 512}},
3115 { 2, {256, 256}},
3116 { 4, {128, 256}},
3117 { 7, {128, 128}},
3118 { 13, { 64, 128}},
3119 { 25, { 16, 128}},
3120 { 49, { 0, 0}},
3121 { UINT_MAX, { 0, 0}},
3122 },
3123 },
3124 {
3125 // Two RB / SE
3126 {
3127 // One shader engine
3128 { 0, {256, 256}},
3129 { 2, {128, 256}},
3130 { 4, {128, 128}},
3131 { 7, { 64, 128}},
3132 { 13, { 32, 128}},
3133 { 25, { 16, 128}},
3134 { 97, { 0, 0}},
3135 { UINT_MAX, { 0, 0}},
3136 },
3137 {
3138 // Two shader engines
3139 { 0, {256, 512}},
3140 { 2, {256, 256}},
3141 { 4, {128, 256}},
3142 { 7, {128, 128}},
3143 { 13, { 64, 128}},
3144 { 25, { 32, 128}},
3145 { 49, { 16, 128}},
3146 { 97, { 0, 0}},
3147 { UINT_MAX, { 0, 0}},
3148 },
3149 {
3150 // Four shader engines
3151 { 0, {512, 512}},
3152 { 2, {256, 512}},
3153 { 4, {256, 256}},
3154 { 7, {128, 256}},
3155 { 13, {128, 128}},
3156 { 25, { 64, 128}},
3157 { 49, { 16, 128}},
3158 { 97, { 0, 0}},
3159 { UINT_MAX, { 0, 0}},
3160 },
3161 },
3162 {
3163 // Four RB / SE
3164 {
3165 // One shader engine
3166 { 0, {256, 512}},
3167 { 2, {256, 256}},
3168 { 4, {128, 256}},
3169 { 7, {128, 128}},
3170 { 13, { 64, 128}},
3171 { 25, { 32, 128}},
3172 { 49, { 16, 128}},
3173 { UINT_MAX, { 0, 0}},
3174 },
3175 {
3176 // Two shader engines
3177 { 0, {512, 512}},
3178 { 2, {256, 512}},
3179 { 4, {256, 256}},
3180 { 7, {128, 256}},
3181 { 13, {128, 128}},
3182 { 25, { 64, 128}},
3183 { 49, { 32, 128}},
3184 { 97, { 16, 128}},
3185 { UINT_MAX, { 0, 0}},
3186 },
3187 {
3188 // Four shader engines
3189 { 0, {512, 512}},
3190 { 4, {256, 512}},
3191 { 7, {256, 256}},
3192 { 13, {128, 256}},
3193 { 25, {128, 128}},
3194 { 49, { 64, 128}},
3195 { 97, { 16, 128}},
3196 { UINT_MAX, { 0, 0}},
3197 },
3198 },
3199 };
3200
3201 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3202 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3203 VkExtent2D extent = {512, 512};
3204
3205 unsigned log_num_rb_per_se =
3206 util_logbase2_ceil(pipeline->device->physical_device->rad_info.num_render_backends /
3207 pipeline->device->physical_device->rad_info.max_se);
3208 unsigned log_num_se = util_logbase2_ceil(pipeline->device->physical_device->rad_info.max_se);
3209
3210 unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
3211 unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->graphics.ms.db_eqaa);
3212 unsigned effective_samples = total_samples;
3213 unsigned color_bytes_per_pixel = 0;
3214
3215 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
3216 if (vkblend) {
3217 for (unsigned i = 0; i < subpass->color_count; i++) {
3218 if (!vkblend->pAttachments[i].colorWriteMask)
3219 continue;
3220
3221 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3222 continue;
3223
3224 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3225 color_bytes_per_pixel += vk_format_get_blocksize(format);
3226 }
3227
3228 /* MSAA images typically don't use all samples all the time. */
3229 if (effective_samples >= 2 && ps_iter_samples <= 1)
3230 effective_samples = 2;
3231 color_bytes_per_pixel *= effective_samples;
3232 }
3233
3234 const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se];
3235 while(color_entry[1].bpp <= color_bytes_per_pixel)
3236 ++color_entry;
3237
3238 extent = color_entry->extent;
3239
3240 if (subpass->depth_stencil_attachment) {
3241 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3242
3243 /* Coefficients taken from AMDVLK */
3244 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
3245 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
3246 unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples;
3247
3248 const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se];
3249 while(ds_entry[1].bpp <= ds_bytes_per_pixel)
3250 ++ds_entry;
3251
3252 if (ds_entry->extent.width * ds_entry->extent.height < extent.width * extent.height)
3253 extent = ds_entry->extent;
3254 }
3255
3256 return extent;
3257 }
3258
3259 static VkExtent2D
3260 radv_gfx10_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
3261 {
3262 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3263 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3264 VkExtent2D extent = {512, 512};
3265
3266 const unsigned db_tag_size = 64;
3267 const unsigned db_tag_count = 312;
3268 const unsigned color_tag_size = 1024;
3269 const unsigned color_tag_count = 31;
3270 const unsigned fmask_tag_size = 256;
3271 const unsigned fmask_tag_count = 44;
3272
3273 const unsigned rb_count = pipeline->device->physical_device->rad_info.num_render_backends;
3274 const unsigned pipe_count = MAX2(rb_count, pipeline->device->physical_device->rad_info.num_sdp_interfaces);
3275
3276 const unsigned db_tag_part = (db_tag_count * rb_count / pipe_count) * db_tag_size * pipe_count;
3277 const unsigned color_tag_part = (color_tag_count * rb_count / pipe_count) * color_tag_size * pipe_count;
3278 const unsigned fmask_tag_part = (fmask_tag_count * rb_count / pipe_count) * fmask_tag_size * pipe_count;
3279
3280 const unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
3281 const unsigned samples_log = util_logbase2_ceil(total_samples);
3282
3283 unsigned color_bytes_per_pixel = 0;
3284 unsigned fmask_bytes_per_pixel = 0;
3285
3286 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
3287 if (vkblend) {
3288 for (unsigned i = 0; i < subpass->color_count; i++) {
3289 if (!vkblend->pAttachments[i].colorWriteMask)
3290 continue;
3291
3292 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3293 continue;
3294
3295 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3296 color_bytes_per_pixel += vk_format_get_blocksize(format);
3297
3298 if (total_samples > 1) {
3299 assert(samples_log <= 3);
3300 const unsigned fmask_array[] = {0, 1, 1, 4};
3301 fmask_bytes_per_pixel += fmask_array[samples_log];
3302 }
3303 }
3304
3305 color_bytes_per_pixel *= total_samples;
3306 }
3307 color_bytes_per_pixel = MAX2(color_bytes_per_pixel, 1);
3308
3309 const unsigned color_pixel_count_log = util_logbase2(color_tag_part / color_bytes_per_pixel);
3310 extent.width = 1ull << ((color_pixel_count_log + 1) / 2);
3311 extent.height = 1ull << (color_pixel_count_log / 2);
3312
3313 if (fmask_bytes_per_pixel) {
3314 const unsigned fmask_pixel_count_log = util_logbase2(fmask_tag_part / fmask_bytes_per_pixel);
3315
3316 const VkExtent2D fmask_extent = (VkExtent2D){
3317 .width = 1ull << ((fmask_pixel_count_log + 1) / 2),
3318 .height = 1ull << (color_pixel_count_log / 2)
3319 };
3320
3321 if (fmask_extent.width * fmask_extent.height < extent.width * extent.height)
3322 extent = fmask_extent;
3323 }
3324
3325 if (subpass->depth_stencil_attachment) {
3326 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3327
3328 /* Coefficients taken from AMDVLK */
3329 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
3330 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
3331 unsigned db_bytes_per_pixel = (depth_coeff + stencil_coeff) * total_samples;
3332
3333 const unsigned db_pixel_count_log = util_logbase2(db_tag_part / db_bytes_per_pixel);
3334
3335 const VkExtent2D db_extent = (VkExtent2D){
3336 .width = 1ull << ((db_pixel_count_log + 1) / 2),
3337 .height = 1ull << (color_pixel_count_log / 2)
3338 };
3339
3340 if (db_extent.width * db_extent.height < extent.width * extent.height)
3341 extent = db_extent;
3342 }
3343
3344 extent.width = MAX2(extent.width, 128);
3345 extent.height = MAX2(extent.width, 64);
3346
3347 return extent;
3348 }
3349
3350 static void
3351 radv_pipeline_generate_disabled_binning_state(struct radeon_cmdbuf *ctx_cs,
3352 struct radv_pipeline *pipeline,
3353 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3354 {
3355 uint32_t pa_sc_binner_cntl_0 =
3356 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
3357 S_028C44_DISABLE_START_OF_PRIM(1);
3358 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
3359
3360 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3361 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3362 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3363 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
3364 unsigned min_bytes_per_pixel = 0;
3365
3366 if (vkblend) {
3367 for (unsigned i = 0; i < subpass->color_count; i++) {
3368 if (!vkblend->pAttachments[i].colorWriteMask)
3369 continue;
3370
3371 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3372 continue;
3373
3374 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3375 unsigned bytes = vk_format_get_blocksize(format);
3376 if (!min_bytes_per_pixel || bytes < min_bytes_per_pixel)
3377 min_bytes_per_pixel = bytes;
3378 }
3379 }
3380
3381 pa_sc_binner_cntl_0 =
3382 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC) |
3383 S_028C44_BIN_SIZE_X(0) |
3384 S_028C44_BIN_SIZE_Y(0) |
3385 S_028C44_BIN_SIZE_X_EXTEND(2) | /* 128 */
3386 S_028C44_BIN_SIZE_Y_EXTEND(min_bytes_per_pixel <= 4 ? 2 : 1) | /* 128 or 64 */
3387 S_028C44_DISABLE_START_OF_PRIM(1);
3388 }
3389
3390 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
3391 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
3392 }
3393
3394 static void
3395 radv_pipeline_generate_binning_state(struct radeon_cmdbuf *ctx_cs,
3396 struct radv_pipeline *pipeline,
3397 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3398 const struct radv_blend_state *blend)
3399 {
3400 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
3401 return;
3402
3403 VkExtent2D bin_size;
3404 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3405 bin_size = radv_gfx10_compute_bin_size(pipeline, pCreateInfo);
3406 } else if (pipeline->device->physical_device->rad_info.chip_class == GFX9) {
3407 bin_size = radv_gfx9_compute_bin_size(pipeline, pCreateInfo);
3408 } else
3409 unreachable("Unhandled generation for binning bin size calculation");
3410
3411 if (pipeline->device->pbb_allowed && bin_size.width && bin_size.height) {
3412 unsigned context_states_per_bin; /* allowed range: [1, 6] */
3413 unsigned persistent_states_per_bin; /* allowed range: [1, 32] */
3414 unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */
3415
3416 if (pipeline->device->physical_device->rad_info.has_dedicated_vram) {
3417 context_states_per_bin = 1;
3418 persistent_states_per_bin = 1;
3419 fpovs_per_batch = 63;
3420 } else {
3421 /* The context states are affected by the scissor bug. */
3422 context_states_per_bin = pipeline->device->physical_device->rad_info.has_gfx9_scissor_bug ? 1 : 6;
3423 /* 32 causes hangs for RAVEN. */
3424 persistent_states_per_bin = 16;
3425 fpovs_per_batch = 63;
3426 }
3427
3428 bool disable_start_of_prim = true;
3429 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
3430
3431 const struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3432
3433 if (pipeline->device->dfsm_allowed && ps &&
3434 !ps->info.ps.can_discard &&
3435 !ps->info.ps.writes_memory &&
3436 blend->cb_target_enabled_4bit) {
3437 db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_AUTO);
3438 disable_start_of_prim = (blend->blend_enable_4bit & blend->cb_target_enabled_4bit) != 0;
3439 }
3440
3441 const uint32_t pa_sc_binner_cntl_0 =
3442 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
3443 S_028C44_BIN_SIZE_X(bin_size.width == 16) |
3444 S_028C44_BIN_SIZE_Y(bin_size.height == 16) |
3445 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size.width, 32)) - 5) |
3446 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size.height, 32)) - 5) |
3447 S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin - 1) |
3448 S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin - 1) |
3449 S_028C44_DISABLE_START_OF_PRIM(disable_start_of_prim) |
3450 S_028C44_FPOVS_PER_BATCH(fpovs_per_batch) |
3451 S_028C44_OPTIMAL_BIN_SELECTION(1);
3452
3453 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
3454 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
3455 } else
3456 radv_pipeline_generate_disabled_binning_state(ctx_cs, pipeline, pCreateInfo);
3457 }
3458
3459
3460 static void
3461 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf *ctx_cs,
3462 struct radv_pipeline *pipeline,
3463 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3464 const struct radv_graphics_pipeline_create_info *extra)
3465 {
3466 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
3467 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3468 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3469 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3470 struct radv_render_pass_attachment *attachment = NULL;
3471 uint32_t db_depth_control = 0, db_stencil_control = 0;
3472 uint32_t db_render_control = 0, db_render_override2 = 0;
3473 uint32_t db_render_override = 0;
3474
3475 if (subpass->depth_stencil_attachment)
3476 attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3477
3478 bool has_depth_attachment = attachment && vk_format_is_depth(attachment->format);
3479 bool has_stencil_attachment = attachment && vk_format_is_stencil(attachment->format);
3480
3481 if (vkds && has_depth_attachment) {
3482 db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
3483 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
3484 S_028800_ZFUNC(vkds->depthCompareOp) |
3485 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
3486
3487 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
3488 db_render_override2 |= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment->samples > 2);
3489 }
3490
3491 if (has_stencil_attachment && vkds && vkds->stencilTestEnable) {
3492 db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
3493 db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
3494 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
3495 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
3496 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
3497
3498 db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
3499 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
3500 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
3501 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
3502 }
3503
3504 if (attachment && extra) {
3505 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
3506 db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
3507
3508 db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
3509 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
3510 db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
3511 db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
3512 db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
3513 }
3514
3515 db_render_override |= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3516 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
3517
3518 if (!pCreateInfo->pRasterizationState->depthClampEnable &&
3519 ps->info.ps.writes_z) {
3520 /* From VK_EXT_depth_range_unrestricted spec:
3521 *
3522 * "The behavior described in Primitive Clipping still applies.
3523 * If depth clamping is disabled the depth values are still
3524 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
3525 * depth clamping is enabled the above equation is ignored and
3526 * the depth values are instead clamped to the VkViewport
3527 * minDepth and maxDepth values, which in the case of this
3528 * extension can be outside of the 0.0 to 1.0 range."
3529 */
3530 db_render_override |= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
3531 }
3532
3533 radeon_set_context_reg(ctx_cs, R_028800_DB_DEPTH_CONTROL, db_depth_control);
3534 radeon_set_context_reg(ctx_cs, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
3535
3536 radeon_set_context_reg(ctx_cs, R_028000_DB_RENDER_CONTROL, db_render_control);
3537 radeon_set_context_reg(ctx_cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
3538 radeon_set_context_reg(ctx_cs, R_028010_DB_RENDER_OVERRIDE2, db_render_override2);
3539 }
3540
3541 static void
3542 radv_pipeline_generate_blend_state(struct radeon_cmdbuf *ctx_cs,
3543 struct radv_pipeline *pipeline,
3544 const struct radv_blend_state *blend)
3545 {
3546 radeon_set_context_reg_seq(ctx_cs, R_028780_CB_BLEND0_CONTROL, 8);
3547 radeon_emit_array(ctx_cs, blend->cb_blend_control,
3548 8);
3549 radeon_set_context_reg(ctx_cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control);
3550 radeon_set_context_reg(ctx_cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask);
3551
3552 if (pipeline->device->physical_device->rad_info.has_rbplus) {
3553
3554 radeon_set_context_reg_seq(ctx_cs, R_028760_SX_MRT0_BLEND_OPT, 8);
3555 radeon_emit_array(ctx_cs, blend->sx_mrt_blend_opt, 8);
3556 }
3557
3558 radeon_set_context_reg(ctx_cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
3559
3560 radeon_set_context_reg(ctx_cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
3561 radeon_set_context_reg(ctx_cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
3562
3563 pipeline->graphics.col_format = blend->spi_shader_col_format;
3564 pipeline->graphics.cb_target_mask = blend->cb_target_mask;
3565 }
3566
3567 static const VkConservativeRasterizationModeEXT
3568 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo *pCreateInfo)
3569 {
3570 const VkPipelineRasterizationConservativeStateCreateInfoEXT *conservative_raster =
3571 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT);
3572
3573 if (!conservative_raster)
3574 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT;
3575 return conservative_raster->conservativeRasterizationMode;
3576 }
3577
3578 static void
3579 radv_pipeline_generate_raster_state(struct radeon_cmdbuf *ctx_cs,
3580 struct radv_pipeline *pipeline,
3581 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3582 {
3583 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
3584 const VkConservativeRasterizationModeEXT mode =
3585 radv_get_conservative_raster_mode(vkraster);
3586 uint32_t pa_sc_conservative_rast = S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
3587 bool depth_clip_disable = vkraster->depthClampEnable;
3588
3589 const VkPipelineRasterizationDepthClipStateCreateInfoEXT *depth_clip_state =
3590 vk_find_struct_const(vkraster->pNext, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT);
3591 if (depth_clip_state) {
3592 depth_clip_disable = !depth_clip_state->depthClipEnable;
3593 }
3594
3595 radeon_set_context_reg(ctx_cs, R_028810_PA_CL_CLIP_CNTL,
3596 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
3597 S_028810_ZCLIP_NEAR_DISABLE(depth_clip_disable ? 1 : 0) |
3598 S_028810_ZCLIP_FAR_DISABLE(depth_clip_disable ? 1 : 0) |
3599 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
3600 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
3601
3602 radeon_set_context_reg(ctx_cs, R_0286D4_SPI_INTERP_CONTROL_0,
3603 S_0286D4_FLAT_SHADE_ENA(1) |
3604 S_0286D4_PNT_SPRITE_ENA(1) |
3605 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
3606 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
3607 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
3608 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
3609 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
3610
3611 radeon_set_context_reg(ctx_cs, R_028BE4_PA_SU_VTX_CNTL,
3612 S_028BE4_PIX_CENTER(1) | // TODO verify
3613 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
3614 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
3615
3616 radeon_set_context_reg(ctx_cs, R_028814_PA_SU_SC_MODE_CNTL,
3617 S_028814_FACE(vkraster->frontFace) |
3618 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
3619 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
3620 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
3621 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
3622 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
3623 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
3624 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
3625 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0));
3626
3627 /* Conservative rasterization. */
3628 if (mode != VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT) {
3629 struct radv_multisample_state *ms = &pipeline->graphics.ms;
3630
3631 ms->pa_sc_aa_config |= S_028BE0_AA_MASK_CENTROID_DTMN(1);
3632 ms->db_eqaa |= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
3633 S_028804_OVERRASTERIZATION_AMOUNT(4);
3634
3635 pa_sc_conservative_rast = S_028C4C_PREZ_AA_MASK_ENABLE(1) |
3636 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
3637 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
3638
3639 if (mode == VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT) {
3640 pa_sc_conservative_rast |=
3641 S_028C4C_OVER_RAST_ENABLE(1) |
3642 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
3643 S_028C4C_UNDER_RAST_ENABLE(0) |
3644 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
3645 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
3646 } else {
3647 assert(mode == VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT);
3648 pa_sc_conservative_rast |=
3649 S_028C4C_OVER_RAST_ENABLE(0) |
3650 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
3651 S_028C4C_UNDER_RAST_ENABLE(1) |
3652 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
3653 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
3654 }
3655 }
3656
3657 radeon_set_context_reg(ctx_cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
3658 pa_sc_conservative_rast);
3659 }
3660
3661
3662 static void
3663 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf *ctx_cs,
3664 struct radv_pipeline *pipeline)
3665 {
3666 struct radv_multisample_state *ms = &pipeline->graphics.ms;
3667
3668 radeon_set_context_reg_seq(ctx_cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3669 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[0]);
3670 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[1]);
3671
3672 radeon_set_context_reg(ctx_cs, R_028804_DB_EQAA, ms->db_eqaa);
3673 radeon_set_context_reg(ctx_cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
3674 radeon_set_context_reg(ctx_cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
3675 radeon_set_context_reg(ctx_cs, R_028BDC_PA_SC_LINE_CNTL, ms->pa_sc_line_cntl);
3676 radeon_set_context_reg(ctx_cs, R_028BE0_PA_SC_AA_CONFIG, ms->pa_sc_aa_config);
3677
3678 /* The exclusion bits can be set to improve rasterization efficiency
3679 * if no sample lies on the pixel boundary (-8 sample offset). It's
3680 * currently always TRUE because the driver doesn't support 16 samples.
3681 */
3682 bool exclusion = pipeline->device->physical_device->rad_info.chip_class >= GFX7;
3683 radeon_set_context_reg(ctx_cs, R_02882C_PA_SU_PRIM_FILTER_CNTL,
3684 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
3685 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
3686
3687 /* GFX9: Flush DFSM when the AA mode changes. */
3688 if (pipeline->device->dfsm_allowed) {
3689 radeon_emit(ctx_cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3690 radeon_emit(ctx_cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3691 }
3692 }
3693
3694 static void
3695 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf *ctx_cs,
3696 struct radv_pipeline *pipeline)
3697 {
3698 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3699 const struct radv_shader_variant *vs =
3700 pipeline->shaders[MESA_SHADER_TESS_EVAL] ?
3701 pipeline->shaders[MESA_SHADER_TESS_EVAL] :
3702 pipeline->shaders[MESA_SHADER_VERTEX];
3703 unsigned vgt_primitiveid_en = 0;
3704 uint32_t vgt_gs_mode = 0;
3705
3706 if (radv_pipeline_has_ngg(pipeline))
3707 return;
3708
3709 if (radv_pipeline_has_gs(pipeline)) {
3710 const struct radv_shader_variant *gs =
3711 pipeline->shaders[MESA_SHADER_GEOMETRY];
3712
3713 vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out,
3714 pipeline->device->physical_device->rad_info.chip_class);
3715 } else if (outinfo->export_prim_id || vs->info.uses_prim_id) {
3716 vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
3717 vgt_primitiveid_en |= S_028A84_PRIMITIVEID_EN(1);
3718 }
3719
3720 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN, vgt_primitiveid_en);
3721 radeon_set_context_reg(ctx_cs, R_028A40_VGT_GS_MODE, vgt_gs_mode);
3722 }
3723
3724 static void
3725 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs,
3726 struct radeon_cmdbuf *cs,
3727 struct radv_pipeline *pipeline,
3728 struct radv_shader_variant *shader)
3729 {
3730 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3731
3732 radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
3733 radeon_emit(cs, va >> 8);
3734 radeon_emit(cs, S_00B124_MEM_BASE(va >> 40));
3735 radeon_emit(cs, shader->config.rsrc1);
3736 radeon_emit(cs, shader->config.rsrc2);
3737
3738 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3739 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3740 clip_dist_mask = outinfo->clip_dist_mask;
3741 cull_dist_mask = outinfo->cull_dist_mask;
3742 total_mask = clip_dist_mask | cull_dist_mask;
3743 bool misc_vec_ena = outinfo->writes_pointsize ||
3744 outinfo->writes_layer ||
3745 outinfo->writes_viewport_index;
3746 unsigned spi_vs_out_config, nparams;
3747
3748 /* VS is required to export at least one param. */
3749 nparams = MAX2(outinfo->param_exports, 1);
3750 spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
3751
3752 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3753 spi_vs_out_config |= S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0);
3754 }
3755
3756 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG, spi_vs_out_config);
3757
3758 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
3759 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
3760 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
3761 V_02870C_SPI_SHADER_4COMP :
3762 V_02870C_SPI_SHADER_NONE) |
3763 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
3764 V_02870C_SPI_SHADER_4COMP :
3765 V_02870C_SPI_SHADER_NONE) |
3766 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
3767 V_02870C_SPI_SHADER_4COMP :
3768 V_02870C_SPI_SHADER_NONE));
3769
3770 radeon_set_context_reg(ctx_cs, R_028818_PA_CL_VTE_CNTL,
3771 S_028818_VTX_W0_FMT(1) |
3772 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3773 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3774 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3775
3776 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
3777 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
3778 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
3779 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
3780 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
3781 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
3782 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
3783 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
3784 cull_dist_mask << 8 |
3785 clip_dist_mask);
3786
3787 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
3788 radeon_set_context_reg(ctx_cs, R_028AB4_VGT_REUSE_OFF,
3789 outinfo->writes_viewport_index);
3790 }
3791
3792 static void
3793 radv_pipeline_generate_hw_es(struct radeon_cmdbuf *cs,
3794 struct radv_pipeline *pipeline,
3795 struct radv_shader_variant *shader)
3796 {
3797 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3798
3799 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
3800 radeon_emit(cs, va >> 8);
3801 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3802 radeon_emit(cs, shader->config.rsrc1);
3803 radeon_emit(cs, shader->config.rsrc2);
3804 }
3805
3806 static void
3807 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf *cs,
3808 struct radv_pipeline *pipeline,
3809 struct radv_shader_variant *shader,
3810 const struct radv_tessellation_state *tess)
3811 {
3812 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3813 uint32_t rsrc2 = shader->config.rsrc2;
3814
3815 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
3816 radeon_emit(cs, va >> 8);
3817 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
3818
3819 rsrc2 |= S_00B52C_LDS_SIZE(tess->lds_size);
3820 if (pipeline->device->physical_device->rad_info.chip_class == GFX7 &&
3821 pipeline->device->physical_device->rad_info.family != CHIP_HAWAII)
3822 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
3823
3824 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
3825 radeon_emit(cs, shader->config.rsrc1);
3826 radeon_emit(cs, rsrc2);
3827 }
3828
3829 static void
3830 radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs,
3831 struct radeon_cmdbuf *cs,
3832 struct radv_pipeline *pipeline,
3833 struct radv_shader_variant *shader)
3834 {
3835 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3836 gl_shader_stage es_type =
3837 radv_pipeline_has_tess(pipeline) ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
3838 struct radv_shader_variant *es =
3839 es_type == MESA_SHADER_TESS_EVAL ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX];
3840 const struct gfx10_ngg_info *ngg_state = &shader->info.ngg_info;
3841
3842 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
3843 radeon_emit(cs, va >> 8);
3844 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3845 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
3846 radeon_emit(cs, shader->config.rsrc1);
3847 radeon_emit(cs, shader->config.rsrc2);
3848
3849 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3850 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3851 clip_dist_mask = outinfo->clip_dist_mask;
3852 cull_dist_mask = outinfo->cull_dist_mask;
3853 total_mask = clip_dist_mask | cull_dist_mask;
3854 bool misc_vec_ena = outinfo->writes_pointsize ||
3855 outinfo->writes_layer ||
3856 outinfo->writes_viewport_index;
3857 bool es_enable_prim_id = outinfo->export_prim_id ||
3858 (es && es->info.uses_prim_id);
3859 bool break_wave_at_eoi = false;
3860 unsigned ge_cntl;
3861 unsigned nparams;
3862
3863 if (es_type == MESA_SHADER_TESS_EVAL) {
3864 struct radv_shader_variant *gs =
3865 pipeline->shaders[MESA_SHADER_GEOMETRY];
3866
3867 if (es_enable_prim_id || (gs && gs->info.uses_prim_id))
3868 break_wave_at_eoi = true;
3869 }
3870
3871 nparams = MAX2(outinfo->param_exports, 1);
3872 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG,
3873 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
3874 S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0));
3875
3876 radeon_set_context_reg(ctx_cs, R_028708_SPI_SHADER_IDX_FORMAT,
3877 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP));
3878 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
3879 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
3880 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
3881 V_02870C_SPI_SHADER_4COMP :
3882 V_02870C_SPI_SHADER_NONE) |
3883 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
3884 V_02870C_SPI_SHADER_4COMP :
3885 V_02870C_SPI_SHADER_NONE) |
3886 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
3887 V_02870C_SPI_SHADER_4COMP :
3888 V_02870C_SPI_SHADER_NONE));
3889
3890 radeon_set_context_reg(ctx_cs, R_028818_PA_CL_VTE_CNTL,
3891 S_028818_VTX_W0_FMT(1) |
3892 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3893 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3894 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3895 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
3896 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
3897 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
3898 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
3899 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
3900 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
3901 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
3902 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
3903 cull_dist_mask << 8 |
3904 clip_dist_mask);
3905
3906 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN,
3907 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
3908 S_028A84_NGG_DISABLE_PROVOK_REUSE(es_enable_prim_id));
3909
3910 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
3911 ngg_state->vgt_esgs_ring_itemsize);
3912
3913 /* NGG specific registers. */
3914 struct radv_shader_variant *gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
3915 uint32_t gs_num_invocations = gs ? gs->info.gs.invocations : 1;
3916
3917 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
3918 S_028A44_ES_VERTS_PER_SUBGRP(ngg_state->hw_max_esverts) |
3919 S_028A44_GS_PRIMS_PER_SUBGRP(ngg_state->max_gsprims) |
3920 S_028A44_GS_INST_PRIMS_IN_SUBGRP(ngg_state->max_gsprims * gs_num_invocations));
3921 radeon_set_context_reg(ctx_cs, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
3922 S_0287FC_MAX_VERTS_PER_SUBGROUP(ngg_state->max_out_verts));
3923 radeon_set_context_reg(ctx_cs, R_028B4C_GE_NGG_SUBGRP_CNTL,
3924 S_028B4C_PRIM_AMP_FACTOR(ngg_state->prim_amp_factor) |
3925 S_028B4C_THDS_PER_SUBGRP(0)); /* for fast launch */
3926 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
3927 S_028B90_CNT(gs_num_invocations) |
3928 S_028B90_ENABLE(gs_num_invocations > 1) |
3929 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(ngg_state->max_vert_out_per_gs_instance));
3930
3931 /* User edge flags are set by the pos exports. If user edge flags are
3932 * not used, we must use hw-generated edge flags and pass them via
3933 * the prim export to prevent drawing lines on internal edges of
3934 * decomposed primitives (such as quads) with polygon mode = lines.
3935 *
3936 * TODO: We should combine hw-generated edge flags with user edge
3937 * flags in the shader.
3938 */
3939 radeon_set_context_reg(ctx_cs, R_028838_PA_CL_NGG_CNTL,
3940 S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline) &&
3941 !radv_pipeline_has_gs(pipeline)));
3942
3943 ge_cntl = S_03096C_PRIM_GRP_SIZE(ngg_state->max_gsprims) |
3944 S_03096C_VERT_GRP_SIZE(ngg_state->hw_max_esverts) |
3945 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
3946
3947 /* Bug workaround for a possible hang with non-tessellation cases.
3948 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
3949 *
3950 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
3951 */
3952 if ((pipeline->device->physical_device->rad_info.family == CHIP_NAVI10 ||
3953 pipeline->device->physical_device->rad_info.family == CHIP_NAVI12 ||
3954 pipeline->device->physical_device->rad_info.family == CHIP_NAVI14) &&
3955 !radv_pipeline_has_tess(pipeline) &&
3956 ngg_state->hw_max_esverts != 256) {
3957 ge_cntl &= C_03096C_VERT_GRP_SIZE;
3958
3959 if (ngg_state->hw_max_esverts > 5) {
3960 ge_cntl |= S_03096C_VERT_GRP_SIZE(ngg_state->hw_max_esverts - 5);
3961 }
3962 }
3963
3964 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL, ge_cntl);
3965 }
3966
3967 static void
3968 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf *cs,
3969 struct radv_pipeline *pipeline,
3970 struct radv_shader_variant *shader,
3971 const struct radv_tessellation_state *tess)
3972 {
3973 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3974
3975 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
3976 unsigned hs_rsrc2 = shader->config.rsrc2;
3977
3978 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3979 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX10(tess->lds_size);
3980 } else {
3981 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX9(tess->lds_size);
3982 }
3983
3984 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3985 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
3986 radeon_emit(cs, va >> 8);
3987 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
3988 } else {
3989 radeon_set_sh_reg_seq(cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
3990 radeon_emit(cs, va >> 8);
3991 radeon_emit(cs, S_00B414_MEM_BASE(va >> 40));
3992 }
3993
3994 radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
3995 radeon_emit(cs, shader->config.rsrc1);
3996 radeon_emit(cs, hs_rsrc2);
3997 } else {
3998 radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
3999 radeon_emit(cs, va >> 8);
4000 radeon_emit(cs, S_00B424_MEM_BASE(va >> 40));
4001 radeon_emit(cs, shader->config.rsrc1);
4002 radeon_emit(cs, shader->config.rsrc2);
4003 }
4004 }
4005
4006 static void
4007 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf *ctx_cs,
4008 struct radeon_cmdbuf *cs,
4009 struct radv_pipeline *pipeline,
4010 const struct radv_tessellation_state *tess)
4011 {
4012 struct radv_shader_variant *vs;
4013
4014 /* Skip shaders merged into HS/GS */
4015 vs = pipeline->shaders[MESA_SHADER_VERTEX];
4016 if (!vs)
4017 return;
4018
4019 if (vs->info.vs.as_ls)
4020 radv_pipeline_generate_hw_ls(cs, pipeline, vs, tess);
4021 else if (vs->info.vs.as_es)
4022 radv_pipeline_generate_hw_es(cs, pipeline, vs);
4023 else if (vs->info.is_ngg)
4024 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, vs);
4025 else
4026 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, vs);
4027 }
4028
4029 static void
4030 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf *ctx_cs,
4031 struct radeon_cmdbuf *cs,
4032 struct radv_pipeline *pipeline,
4033 const struct radv_tessellation_state *tess)
4034 {
4035 if (!radv_pipeline_has_tess(pipeline))
4036 return;
4037
4038 struct radv_shader_variant *tes, *tcs;
4039
4040 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
4041 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
4042
4043 if (tes) {
4044 if (tes->info.is_ngg) {
4045 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, tes);
4046 } else if (tes->info.tes.as_es)
4047 radv_pipeline_generate_hw_es(cs, pipeline, tes);
4048 else
4049 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, tes);
4050 }
4051
4052 radv_pipeline_generate_hw_hs(cs, pipeline, tcs, tess);
4053
4054 radeon_set_context_reg(ctx_cs, R_028B6C_VGT_TF_PARAM,
4055 tess->tf_param);
4056
4057 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7)
4058 radeon_set_context_reg_idx(ctx_cs, R_028B58_VGT_LS_HS_CONFIG, 2,
4059 tess->ls_hs_config);
4060 else
4061 radeon_set_context_reg(ctx_cs, R_028B58_VGT_LS_HS_CONFIG,
4062 tess->ls_hs_config);
4063
4064 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 &&
4065 !radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) {
4066 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
4067 S_028A44_ES_VERTS_PER_SUBGRP(250) |
4068 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
4069 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
4070 }
4071 }
4072
4073 static void
4074 radv_pipeline_generate_hw_gs(struct radeon_cmdbuf *ctx_cs,
4075 struct radeon_cmdbuf *cs,
4076 struct radv_pipeline *pipeline,
4077 struct radv_shader_variant *gs)
4078 {
4079 const struct gfx9_gs_info *gs_state = &gs->info.gs_ring_info;
4080 unsigned gs_max_out_vertices;
4081 uint8_t *num_components;
4082 uint8_t max_stream;
4083 unsigned offset;
4084 uint64_t va;
4085
4086 gs_max_out_vertices = gs->info.gs.vertices_out;
4087 max_stream = gs->info.gs.max_stream;
4088 num_components = gs->info.gs.num_stream_output_components;
4089
4090 offset = num_components[0] * gs_max_out_vertices;
4091
4092 radeon_set_context_reg_seq(ctx_cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
4093 radeon_emit(ctx_cs, offset);
4094 if (max_stream >= 1)
4095 offset += num_components[1] * gs_max_out_vertices;
4096 radeon_emit(ctx_cs, offset);
4097 if (max_stream >= 2)
4098 offset += num_components[2] * gs_max_out_vertices;
4099 radeon_emit(ctx_cs, offset);
4100 if (max_stream >= 3)
4101 offset += num_components[3] * gs_max_out_vertices;
4102 radeon_set_context_reg(ctx_cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
4103
4104 radeon_set_context_reg_seq(ctx_cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
4105 radeon_emit(ctx_cs, num_components[0]);
4106 radeon_emit(ctx_cs, (max_stream >= 1) ? num_components[1] : 0);
4107 radeon_emit(ctx_cs, (max_stream >= 2) ? num_components[2] : 0);
4108 radeon_emit(ctx_cs, (max_stream >= 3) ? num_components[3] : 0);
4109
4110 uint32_t gs_num_invocations = gs->info.gs.invocations;
4111 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
4112 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
4113 S_028B90_ENABLE(gs_num_invocations > 0));
4114
4115 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
4116 gs_state->vgt_esgs_ring_itemsize);
4117
4118 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
4119
4120 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
4121 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4122 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
4123 radeon_emit(cs, va >> 8);
4124 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
4125 } else {
4126 radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
4127 radeon_emit(cs, va >> 8);
4128 radeon_emit(cs, S_00B214_MEM_BASE(va >> 40));
4129 }
4130
4131 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
4132 radeon_emit(cs, gs->config.rsrc1);
4133 radeon_emit(cs, gs->config.rsrc2 | S_00B22C_LDS_SIZE(gs_state->lds_size));
4134
4135 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL, gs_state->vgt_gs_onchip_cntl);
4136 radeon_set_context_reg(ctx_cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, gs_state->vgt_gs_max_prims_per_subgroup);
4137 } else {
4138 radeon_set_sh_reg_seq(cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
4139 radeon_emit(cs, va >> 8);
4140 radeon_emit(cs, S_00B224_MEM_BASE(va >> 40));
4141 radeon_emit(cs, gs->config.rsrc1);
4142 radeon_emit(cs, gs->config.rsrc2);
4143 }
4144
4145 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, pipeline->gs_copy_shader);
4146 }
4147
4148 static void
4149 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf *ctx_cs,
4150 struct radeon_cmdbuf *cs,
4151 struct radv_pipeline *pipeline)
4152 {
4153 struct radv_shader_variant *gs;
4154
4155 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
4156 if (!gs)
4157 return;
4158
4159 if (gs->info.is_ngg)
4160 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, gs);
4161 else
4162 radv_pipeline_generate_hw_gs(ctx_cs, cs, pipeline, gs);
4163
4164 radeon_set_context_reg(ctx_cs, R_028B38_VGT_GS_MAX_VERT_OUT,
4165 gs->info.gs.vertices_out);
4166 }
4167
4168 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade, bool float16)
4169 {
4170 uint32_t ps_input_cntl;
4171 if (offset <= AC_EXP_PARAM_OFFSET_31) {
4172 ps_input_cntl = S_028644_OFFSET(offset);
4173 if (flat_shade)
4174 ps_input_cntl |= S_028644_FLAT_SHADE(1);
4175 if (float16) {
4176 ps_input_cntl |= S_028644_FP16_INTERP_MODE(1) |
4177 S_028644_ATTR0_VALID(1);
4178 }
4179 } else {
4180 /* The input is a DEFAULT_VAL constant. */
4181 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
4182 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
4183 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
4184 ps_input_cntl = S_028644_OFFSET(0x20) |
4185 S_028644_DEFAULT_VAL(offset);
4186 }
4187 return ps_input_cntl;
4188 }
4189
4190 static void
4191 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf *ctx_cs,
4192 struct radv_pipeline *pipeline)
4193 {
4194 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4195 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
4196 uint32_t ps_input_cntl[32];
4197
4198 unsigned ps_offset = 0;
4199
4200 if (ps->info.ps.prim_id_input) {
4201 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
4202 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
4203 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false);
4204 ++ps_offset;
4205 }
4206 }
4207
4208 if (ps->info.ps.layer_input ||
4209 ps->info.needs_multiview_view_index) {
4210 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
4211 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
4212 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false);
4213 else
4214 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true, false);
4215 ++ps_offset;
4216 }
4217
4218 if (ps->info.ps.has_pcoord) {
4219 unsigned val;
4220 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
4221 ps_input_cntl[ps_offset] = val;
4222 ps_offset++;
4223 }
4224
4225 if (ps->info.ps.num_input_clips_culls) {
4226 unsigned vs_offset;
4227
4228 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST0];
4229 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
4230 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false);
4231 ++ps_offset;
4232 }
4233
4234 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST1];
4235 if (vs_offset != AC_EXP_PARAM_UNDEFINED &&
4236 ps->info.ps.num_input_clips_culls > 4) {
4237 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false);
4238 ++ps_offset;
4239 }
4240 }
4241
4242 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.ps.input_mask; ++i) {
4243 unsigned vs_offset;
4244 bool flat_shade;
4245 bool float16;
4246 if (!(ps->info.ps.input_mask & (1u << i)))
4247 continue;
4248
4249 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
4250 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
4251 ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
4252 ++ps_offset;
4253 continue;
4254 }
4255
4256 flat_shade = !!(ps->info.ps.flat_shaded_mask & (1u << ps_offset));
4257 float16 = !!(ps->info.ps.float16_shaded_mask & (1u << ps_offset));
4258
4259 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade, float16);
4260 ++ps_offset;
4261 }
4262
4263 if (ps_offset) {
4264 radeon_set_context_reg_seq(ctx_cs, R_028644_SPI_PS_INPUT_CNTL_0, ps_offset);
4265 for (unsigned i = 0; i < ps_offset; i++) {
4266 radeon_emit(ctx_cs, ps_input_cntl[i]);
4267 }
4268 }
4269 }
4270
4271 static uint32_t
4272 radv_compute_db_shader_control(const struct radv_device *device,
4273 const struct radv_pipeline *pipeline,
4274 const struct radv_shader_variant *ps)
4275 {
4276 unsigned z_order;
4277 if (ps->info.ps.early_fragment_test || !ps->info.ps.writes_memory)
4278 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
4279 else
4280 z_order = V_02880C_LATE_Z;
4281
4282 bool disable_rbplus = device->physical_device->rad_info.has_rbplus &&
4283 !device->physical_device->rad_info.rbplus_allowed;
4284
4285 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
4286 * but this appears to break Project Cars (DXVK). See
4287 * https://bugs.freedesktop.org/show_bug.cgi?id=109401
4288 */
4289 bool mask_export_enable = ps->info.ps.writes_sample_mask;
4290
4291 return S_02880C_Z_EXPORT_ENABLE(ps->info.ps.writes_z) |
4292 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.ps.writes_stencil) |
4293 S_02880C_KILL_ENABLE(!!ps->info.ps.can_discard) |
4294 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable) |
4295 S_02880C_Z_ORDER(z_order) |
4296 S_02880C_DEPTH_BEFORE_SHADER(ps->info.ps.early_fragment_test) |
4297 S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps->info.ps.post_depth_coverage) |
4298 S_02880C_EXEC_ON_HIER_FAIL(ps->info.ps.writes_memory) |
4299 S_02880C_EXEC_ON_NOOP(ps->info.ps.writes_memory) |
4300 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus);
4301 }
4302
4303 static void
4304 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf *ctx_cs,
4305 struct radeon_cmdbuf *cs,
4306 struct radv_pipeline *pipeline)
4307 {
4308 struct radv_shader_variant *ps;
4309 uint64_t va;
4310 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
4311
4312 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4313 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
4314
4315 radeon_set_sh_reg_seq(cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
4316 radeon_emit(cs, va >> 8);
4317 radeon_emit(cs, S_00B024_MEM_BASE(va >> 40));
4318 radeon_emit(cs, ps->config.rsrc1);
4319 radeon_emit(cs, ps->config.rsrc2);
4320
4321 radeon_set_context_reg(ctx_cs, R_02880C_DB_SHADER_CONTROL,
4322 radv_compute_db_shader_control(pipeline->device,
4323 pipeline, ps));
4324
4325 radeon_set_context_reg(ctx_cs, R_0286CC_SPI_PS_INPUT_ENA,
4326 ps->config.spi_ps_input_ena);
4327
4328 radeon_set_context_reg(ctx_cs, R_0286D0_SPI_PS_INPUT_ADDR,
4329 ps->config.spi_ps_input_addr);
4330
4331 radeon_set_context_reg(ctx_cs, R_0286D8_SPI_PS_IN_CONTROL,
4332 S_0286D8_NUM_INTERP(ps->info.ps.num_interp) |
4333 S_0286D8_PS_W32_EN(ps->info.wave_size == 32));
4334
4335 radeon_set_context_reg(ctx_cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl);
4336
4337 radeon_set_context_reg(ctx_cs, R_028710_SPI_SHADER_Z_FORMAT,
4338 ac_get_spi_shader_z_format(ps->info.ps.writes_z,
4339 ps->info.ps.writes_stencil,
4340 ps->info.ps.writes_sample_mask));
4341
4342 if (pipeline->device->dfsm_allowed) {
4343 /* optimise this? */
4344 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
4345 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
4346 }
4347 }
4348
4349 static void
4350 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf *ctx_cs,
4351 struct radv_pipeline *pipeline)
4352 {
4353 if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10 ||
4354 pipeline->device->physical_device->rad_info.chip_class >= GFX10)
4355 return;
4356
4357 unsigned vtx_reuse_depth = 30;
4358 if (radv_pipeline_has_tess(pipeline) &&
4359 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
4360 vtx_reuse_depth = 14;
4361 }
4362 radeon_set_context_reg(ctx_cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
4363 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth));
4364 }
4365
4366 static uint32_t
4367 radv_compute_vgt_shader_stages_en(const struct radv_pipeline *pipeline)
4368 {
4369 uint32_t stages = 0;
4370 if (radv_pipeline_has_tess(pipeline)) {
4371 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
4372 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
4373
4374 if (radv_pipeline_has_gs(pipeline))
4375 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
4376 S_028B54_GS_EN(1);
4377 else if (radv_pipeline_has_ngg(pipeline))
4378 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
4379 else
4380 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
4381 } else if (radv_pipeline_has_gs(pipeline)) {
4382 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
4383 S_028B54_GS_EN(1);
4384 } else if (radv_pipeline_has_ngg(pipeline)) {
4385 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
4386 }
4387
4388 if (radv_pipeline_has_ngg(pipeline)) {
4389 stages |= S_028B54_PRIMGEN_EN(1);
4390 if (pipeline->streamout_shader)
4391 stages |= S_028B54_NGG_WAVE_ID_EN(1);
4392 } else if (radv_pipeline_has_gs(pipeline)) {
4393 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
4394 }
4395
4396 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
4397 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
4398
4399 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4400 uint8_t hs_size = 64, gs_size = 64, vs_size = 64;
4401
4402 if (radv_pipeline_has_tess(pipeline))
4403 hs_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.wave_size;
4404
4405 if (pipeline->shaders[MESA_SHADER_GEOMETRY]) {
4406 vs_size = gs_size = pipeline->shaders[MESA_SHADER_GEOMETRY]->info.wave_size;
4407 if (pipeline->gs_copy_shader)
4408 vs_size = pipeline->gs_copy_shader->info.wave_size;
4409 } else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
4410 vs_size = pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.wave_size;
4411 else if (pipeline->shaders[MESA_SHADER_VERTEX])
4412 vs_size = pipeline->shaders[MESA_SHADER_VERTEX]->info.wave_size;
4413
4414 if (radv_pipeline_has_ngg(pipeline))
4415 gs_size = vs_size;
4416
4417 /* legacy GS only supports Wave64 */
4418 stages |= S_028B54_HS_W32_EN(hs_size == 32 ? 1 : 0) |
4419 S_028B54_GS_W32_EN(gs_size == 32 ? 1 : 0) |
4420 S_028B54_VS_W32_EN(vs_size == 32 ? 1 : 0);
4421 }
4422
4423 return stages;
4424 }
4425
4426 static uint32_t
4427 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo *pCreateInfo)
4428 {
4429 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
4430 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
4431
4432 if (!discard_rectangle_info)
4433 return 0xffff;
4434
4435 unsigned mask = 0;
4436
4437 for (unsigned i = 0; i < (1u << MAX_DISCARD_RECTANGLES); ++i) {
4438 /* Interpret i as a bitmask, and then set the bit in the mask if
4439 * that combination of rectangles in which the pixel is contained
4440 * should pass the cliprect test. */
4441 unsigned relevant_subset = i & ((1u << discard_rectangle_info->discardRectangleCount) - 1);
4442
4443 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT &&
4444 !relevant_subset)
4445 continue;
4446
4447 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT &&
4448 relevant_subset)
4449 continue;
4450
4451 mask |= 1u << i;
4452 }
4453
4454 return mask;
4455 }
4456
4457 static void
4458 gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf *ctx_cs,
4459 struct radv_pipeline *pipeline,
4460 const struct radv_tessellation_state *tess)
4461 {
4462 bool break_wave_at_eoi = false;
4463 unsigned primgroup_size;
4464 unsigned vertgroup_size;
4465
4466 if (radv_pipeline_has_tess(pipeline)) {
4467 primgroup_size = tess->num_patches; /* must be a multiple of NUM_PATCHES */
4468 vertgroup_size = 0;
4469 } else if (radv_pipeline_has_gs(pipeline)) {
4470 const struct gfx9_gs_info *gs_state =
4471 &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs_ring_info;
4472 unsigned vgt_gs_onchip_cntl = gs_state->vgt_gs_onchip_cntl;
4473 primgroup_size = G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl);
4474 vertgroup_size = G_028A44_ES_VERTS_PER_SUBGRP(vgt_gs_onchip_cntl);
4475 } else {
4476 primgroup_size = 128; /* recommended without a GS and tess */
4477 vertgroup_size = 0;
4478 }
4479
4480 if (radv_pipeline_has_tess(pipeline)) {
4481 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
4482 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.uses_prim_id)
4483 break_wave_at_eoi = true;
4484 }
4485
4486 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL,
4487 S_03096C_PRIM_GRP_SIZE(primgroup_size) |
4488 S_03096C_VERT_GRP_SIZE(vertgroup_size) |
4489 S_03096C_PACKET_TO_ONE_PA(0) /* line stipple */ |
4490 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi));
4491 }
4492
4493 static void
4494 radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
4495 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4496 const struct radv_graphics_pipeline_create_info *extra,
4497 const struct radv_blend_state *blend,
4498 const struct radv_tessellation_state *tess,
4499 unsigned prim, unsigned gs_out)
4500 {
4501 struct radeon_cmdbuf *ctx_cs = &pipeline->ctx_cs;
4502 struct radeon_cmdbuf *cs = &pipeline->cs;
4503
4504 cs->max_dw = 64;
4505 ctx_cs->max_dw = 256;
4506 cs->buf = malloc(4 * (cs->max_dw + ctx_cs->max_dw));
4507 ctx_cs->buf = cs->buf + cs->max_dw;
4508
4509 radv_pipeline_generate_depth_stencil_state(ctx_cs, pipeline, pCreateInfo, extra);
4510 radv_pipeline_generate_blend_state(ctx_cs, pipeline, blend);
4511 radv_pipeline_generate_raster_state(ctx_cs, pipeline, pCreateInfo);
4512 radv_pipeline_generate_multisample_state(ctx_cs, pipeline);
4513 radv_pipeline_generate_vgt_gs_mode(ctx_cs, pipeline);
4514 radv_pipeline_generate_vertex_shader(ctx_cs, cs, pipeline, tess);
4515 radv_pipeline_generate_tess_shaders(ctx_cs, cs, pipeline, tess);
4516 radv_pipeline_generate_geometry_shader(ctx_cs, cs, pipeline);
4517 radv_pipeline_generate_fragment_shader(ctx_cs, cs, pipeline);
4518 radv_pipeline_generate_ps_inputs(ctx_cs, pipeline);
4519 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs, pipeline);
4520 radv_pipeline_generate_binning_state(ctx_cs, pipeline, pCreateInfo, blend);
4521
4522 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 && !radv_pipeline_has_ngg(pipeline))
4523 gfx10_pipeline_generate_ge_cntl(ctx_cs, pipeline, tess);
4524
4525 radeon_set_context_reg(ctx_cs, R_028B54_VGT_SHADER_STAGES_EN, radv_compute_vgt_shader_stages_en(pipeline));
4526
4527 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
4528 radeon_set_uconfig_reg_idx(pipeline->device->physical_device,
4529 cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
4530 } else {
4531 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
4532 }
4533 radeon_set_context_reg(ctx_cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out);
4534
4535 radeon_set_context_reg(ctx_cs, R_02820C_PA_SC_CLIPRECT_RULE, radv_compute_cliprect_rule(pCreateInfo));
4536
4537 pipeline->ctx_cs_hash = _mesa_hash_data(ctx_cs->buf, ctx_cs->cdw * 4);
4538
4539 assert(ctx_cs->cdw <= ctx_cs->max_dw);
4540 assert(cs->cdw <= cs->max_dw);
4541 }
4542
4543 static struct radv_ia_multi_vgt_param_helpers
4544 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
4545 const struct radv_tessellation_state *tess,
4546 uint32_t prim)
4547 {
4548 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param = {0};
4549 const struct radv_device *device = pipeline->device;
4550
4551 if (radv_pipeline_has_tess(pipeline))
4552 ia_multi_vgt_param.primgroup_size = tess->num_patches;
4553 else if (radv_pipeline_has_gs(pipeline))
4554 ia_multi_vgt_param.primgroup_size = 64;
4555 else
4556 ia_multi_vgt_param.primgroup_size = 128; /* recommended without a GS */
4557
4558 /* GS requirement. */
4559 ia_multi_vgt_param.partial_es_wave = false;
4560 if (radv_pipeline_has_gs(pipeline) && device->physical_device->rad_info.chip_class <= GFX8)
4561 if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3)
4562 ia_multi_vgt_param.partial_es_wave = true;
4563
4564 ia_multi_vgt_param.wd_switch_on_eop = false;
4565 if (device->physical_device->rad_info.chip_class >= GFX7) {
4566 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
4567 * 4 shader engines. Set 1 to pass the assertion below.
4568 * The other cases are hardware requirements. */
4569 if (device->physical_device->rad_info.max_se < 4 ||
4570 prim == V_008958_DI_PT_POLYGON ||
4571 prim == V_008958_DI_PT_LINELOOP ||
4572 prim == V_008958_DI_PT_TRIFAN ||
4573 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
4574 (pipeline->graphics.prim_restart_enable &&
4575 (device->physical_device->rad_info.family < CHIP_POLARIS10 ||
4576 (prim != V_008958_DI_PT_POINTLIST &&
4577 prim != V_008958_DI_PT_LINESTRIP))))
4578 ia_multi_vgt_param.wd_switch_on_eop = true;
4579 }
4580
4581 ia_multi_vgt_param.ia_switch_on_eoi = false;
4582 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.prim_id_input)
4583 ia_multi_vgt_param.ia_switch_on_eoi = true;
4584 if (radv_pipeline_has_gs(pipeline) &&
4585 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.uses_prim_id)
4586 ia_multi_vgt_param.ia_switch_on_eoi = true;
4587 if (radv_pipeline_has_tess(pipeline)) {
4588 /* SWITCH_ON_EOI must be set if PrimID is used. */
4589 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
4590 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.uses_prim_id)
4591 ia_multi_vgt_param.ia_switch_on_eoi = true;
4592 }
4593
4594 ia_multi_vgt_param.partial_vs_wave = false;
4595 if (radv_pipeline_has_tess(pipeline)) {
4596 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
4597 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
4598 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
4599 device->physical_device->rad_info.family == CHIP_BONAIRE) &&
4600 radv_pipeline_has_gs(pipeline))
4601 ia_multi_vgt_param.partial_vs_wave = true;
4602 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
4603 if (device->physical_device->rad_info.has_distributed_tess) {
4604 if (radv_pipeline_has_gs(pipeline)) {
4605 if (device->physical_device->rad_info.chip_class <= GFX8)
4606 ia_multi_vgt_param.partial_es_wave = true;
4607 } else {
4608 ia_multi_vgt_param.partial_vs_wave = true;
4609 }
4610 }
4611 }
4612
4613 /* Workaround for a VGT hang when strip primitive types are used with
4614 * primitive restart.
4615 */
4616 if (pipeline->graphics.prim_restart_enable &&
4617 (prim == V_008958_DI_PT_LINESTRIP ||
4618 prim == V_008958_DI_PT_TRISTRIP ||
4619 prim == V_008958_DI_PT_LINESTRIP_ADJ ||
4620 prim == V_008958_DI_PT_TRISTRIP_ADJ)) {
4621 ia_multi_vgt_param.partial_vs_wave = true;
4622 }
4623
4624 if (radv_pipeline_has_gs(pipeline)) {
4625 /* On these chips there is the possibility of a hang if the
4626 * pipeline uses a GS and partial_vs_wave is not set.
4627 *
4628 * This mostly does not hit 4-SE chips, as those typically set
4629 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
4630 * with GS due to another workaround.
4631 *
4632 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
4633 */
4634 if (device->physical_device->rad_info.family == CHIP_TONGA ||
4635 device->physical_device->rad_info.family == CHIP_FIJI ||
4636 device->physical_device->rad_info.family == CHIP_POLARIS10 ||
4637 device->physical_device->rad_info.family == CHIP_POLARIS11 ||
4638 device->physical_device->rad_info.family == CHIP_POLARIS12 ||
4639 device->physical_device->rad_info.family == CHIP_VEGAM) {
4640 ia_multi_vgt_param.partial_vs_wave = true;
4641 }
4642 }
4643
4644 ia_multi_vgt_param.base =
4645 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param.primgroup_size - 1) |
4646 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
4647 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == GFX8 ? 2 : 0) |
4648 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
4649 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
4650
4651 return ia_multi_vgt_param;
4652 }
4653
4654
4655 static void
4656 radv_compute_vertex_input_state(struct radv_pipeline *pipeline,
4657 const VkGraphicsPipelineCreateInfo *pCreateInfo)
4658 {
4659 const VkPipelineVertexInputStateCreateInfo *vi_info =
4660 pCreateInfo->pVertexInputState;
4661 struct radv_vertex_elements_info *velems = &pipeline->vertex_elements;
4662
4663 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
4664 const VkVertexInputAttributeDescription *desc =
4665 &vi_info->pVertexAttributeDescriptions[i];
4666 unsigned loc = desc->location;
4667 const struct vk_format_description *format_desc;
4668
4669 format_desc = vk_format_description(desc->format);
4670
4671 velems->format_size[loc] = format_desc->block.bits / 8;
4672 }
4673
4674 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
4675 const VkVertexInputBindingDescription *desc =
4676 &vi_info->pVertexBindingDescriptions[i];
4677
4678 pipeline->binding_stride[desc->binding] = desc->stride;
4679 pipeline->num_vertex_bindings =
4680 MAX2(pipeline->num_vertex_bindings, desc->binding + 1);
4681 }
4682 }
4683
4684 static struct radv_shader_variant *
4685 radv_pipeline_get_streamout_shader(struct radv_pipeline *pipeline)
4686 {
4687 int i;
4688
4689 for (i = MESA_SHADER_GEOMETRY; i >= MESA_SHADER_VERTEX; i--) {
4690 struct radv_shader_variant *shader =
4691 radv_get_shader(pipeline, i);
4692
4693 if (shader && shader->info.so.num_outputs > 0)
4694 return shader;
4695 }
4696
4697 return NULL;
4698 }
4699
4700 static VkResult
4701 radv_secure_compile(struct radv_pipeline *pipeline,
4702 struct radv_device *device,
4703 const struct radv_pipeline_key *key,
4704 const VkPipelineShaderStageCreateInfo **pStages,
4705 const VkPipelineCreateFlags flags,
4706 unsigned num_stages)
4707 {
4708 uint8_t allowed_pipeline_hashes[2][20];
4709 radv_hash_shaders(allowed_pipeline_hashes[0], pStages,
4710 pipeline->layout, key, get_hash_flags(device));
4711
4712 /* Generate the GC copy hash */
4713 memcpy(allowed_pipeline_hashes[1], allowed_pipeline_hashes[0], 20);
4714 allowed_pipeline_hashes[1][0] ^= 1;
4715
4716 uint8_t allowed_hashes[2][20];
4717 for (unsigned i = 0; i < 2; ++i) {
4718 disk_cache_compute_key(device->physical_device->disk_cache,
4719 allowed_pipeline_hashes[i], 20,
4720 allowed_hashes[i]);
4721 }
4722
4723 /* Do an early exit if all cache entries are already there. */
4724 bool may_need_copy_shader = pStages[MESA_SHADER_GEOMETRY];
4725 void *main_entry = disk_cache_get(device->physical_device->disk_cache, allowed_hashes[0], NULL);
4726 void *copy_entry = NULL;
4727 if (may_need_copy_shader)
4728 copy_entry = disk_cache_get(device->physical_device->disk_cache, allowed_hashes[1], NULL);
4729
4730 bool has_all_cache_entries = main_entry && (!may_need_copy_shader || copy_entry);
4731 free(main_entry);
4732 free(copy_entry);
4733
4734 if(has_all_cache_entries)
4735 return VK_SUCCESS;
4736
4737 unsigned process = 0;
4738 uint8_t sc_threads = device->instance->num_sc_threads;
4739 while (true) {
4740 mtx_lock(&device->sc_state->secure_compile_mutex);
4741 if (device->sc_state->secure_compile_thread_counter < sc_threads) {
4742 device->sc_state->secure_compile_thread_counter++;
4743 for (unsigned i = 0; i < sc_threads; i++) {
4744 if (!device->sc_state->secure_compile_processes[i].in_use) {
4745 device->sc_state->secure_compile_processes[i].in_use = true;
4746 process = i;
4747 break;
4748 }
4749 }
4750 mtx_unlock(&device->sc_state->secure_compile_mutex);
4751 break;
4752 }
4753 mtx_unlock(&device->sc_state->secure_compile_mutex);
4754 }
4755
4756 int fd_secure_input = device->sc_state->secure_compile_processes[process].fd_secure_input;
4757 int fd_secure_output = device->sc_state->secure_compile_processes[process].fd_secure_output;
4758
4759 /* Fork a copy of the slim untainted secure compile process */
4760 enum radv_secure_compile_type sc_type = RADV_SC_TYPE_FORK_DEVICE;
4761 write(fd_secure_input, &sc_type, sizeof(sc_type));
4762
4763 if (!radv_sc_read(fd_secure_output, &sc_type, sizeof(sc_type), true) ||
4764 sc_type != RADV_SC_TYPE_INIT_SUCCESS)
4765 return VK_ERROR_DEVICE_LOST;
4766
4767 fd_secure_input = device->sc_state->secure_compile_processes[process].fd_server;
4768 fd_secure_output = device->sc_state->secure_compile_processes[process].fd_client;
4769
4770 /* Write pipeline / shader module out to secure process via pipe */
4771 sc_type = RADV_SC_TYPE_COMPILE_PIPELINE;
4772 write(fd_secure_input, &sc_type, sizeof(sc_type));
4773
4774 /* Write pipeline layout out to secure process */
4775 struct radv_pipeline_layout *layout = pipeline->layout;
4776 write(fd_secure_input, layout, sizeof(struct radv_pipeline_layout));
4777 write(fd_secure_input, &layout->num_sets, sizeof(uint32_t));
4778 for (uint32_t set = 0; set < layout->num_sets; set++) {
4779 write(fd_secure_input, &layout->set[set].layout->layout_size, sizeof(uint32_t));
4780 write(fd_secure_input, layout->set[set].layout, layout->set[set].layout->layout_size);
4781 }
4782
4783 /* Write pipeline key out to secure process */
4784 write(fd_secure_input, key, sizeof(struct radv_pipeline_key));
4785
4786 /* Write pipeline create flags out to secure process */
4787 write(fd_secure_input, &flags, sizeof(VkPipelineCreateFlags));
4788
4789 /* Write stage and shader information out to secure process */
4790 write(fd_secure_input, &num_stages, sizeof(uint32_t));
4791 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
4792 if (!pStages[i])
4793 continue;
4794
4795 /* Write stage out to secure process */
4796 gl_shader_stage stage = ffs(pStages[i]->stage) - 1;
4797 write(fd_secure_input, &stage, sizeof(gl_shader_stage));
4798
4799 /* Write entry point name out to secure process */
4800 size_t name_size = strlen(pStages[i]->pName) + 1;
4801 write(fd_secure_input, &name_size, sizeof(size_t));
4802 write(fd_secure_input, pStages[i]->pName, name_size);
4803
4804 /* Write shader module out to secure process */
4805 struct radv_shader_module *module = radv_shader_module_from_handle(pStages[i]->module);
4806 assert(!module->nir);
4807 size_t module_size = sizeof(struct radv_shader_module) + module->size;
4808 write(fd_secure_input, &module_size, sizeof(size_t));
4809 write(fd_secure_input, module, module_size);
4810
4811 /* Write specialization info out to secure process */
4812 const VkSpecializationInfo *specInfo = pStages[i]->pSpecializationInfo;
4813 bool has_spec_info = specInfo ? true : false;
4814 write(fd_secure_input, &has_spec_info, sizeof(bool));
4815 if (specInfo) {
4816 write(fd_secure_input, &specInfo->dataSize, sizeof(size_t));
4817 write(fd_secure_input, specInfo->pData, specInfo->dataSize);
4818
4819 write(fd_secure_input, &specInfo->mapEntryCount, sizeof(uint32_t));
4820 for (uint32_t j = 0; j < specInfo->mapEntryCount; j++)
4821 write(fd_secure_input, &specInfo->pMapEntries[j], sizeof(VkSpecializationMapEntry));
4822 }
4823 }
4824
4825 /* Read the data returned from the secure process */
4826 while (sc_type != RADV_SC_TYPE_COMPILE_PIPELINE_FINISHED) {
4827 if (!radv_sc_read(fd_secure_output, &sc_type, sizeof(sc_type), true))
4828 return VK_ERROR_DEVICE_LOST;
4829
4830 if (sc_type == RADV_SC_TYPE_WRITE_DISK_CACHE) {
4831 assert(device->physical_device->disk_cache);
4832
4833 uint8_t disk_sha1[20];
4834 if (!radv_sc_read(fd_secure_output, disk_sha1, sizeof(uint8_t) * 20, true))
4835 return VK_ERROR_DEVICE_LOST;
4836
4837 if (memcmp(disk_sha1, allowed_hashes[0], 20) &&
4838 memcmp(disk_sha1, allowed_hashes[1], 20))
4839 return VK_ERROR_DEVICE_LOST;
4840
4841 uint32_t entry_size;
4842 if (!radv_sc_read(fd_secure_output, &entry_size, sizeof(uint32_t), true))
4843 return VK_ERROR_DEVICE_LOST;
4844
4845 struct cache_entry *entry = malloc(entry_size);
4846 if (!radv_sc_read(fd_secure_output, entry, entry_size, true))
4847 return VK_ERROR_DEVICE_LOST;
4848
4849 disk_cache_put(device->physical_device->disk_cache,
4850 disk_sha1, entry, entry_size,
4851 NULL);
4852
4853 free(entry);
4854 } else if (sc_type == RADV_SC_TYPE_READ_DISK_CACHE) {
4855 uint8_t disk_sha1[20];
4856 if (!radv_sc_read(fd_secure_output, disk_sha1, sizeof(uint8_t) * 20, true))
4857 return VK_ERROR_DEVICE_LOST;
4858
4859 if (memcmp(disk_sha1, allowed_hashes[0], 20) &&
4860 memcmp(disk_sha1, allowed_hashes[1], 20))
4861 return VK_ERROR_DEVICE_LOST;
4862
4863 size_t size;
4864 struct cache_entry *entry = (struct cache_entry *)
4865 disk_cache_get(device->physical_device->disk_cache,
4866 disk_sha1, &size);
4867
4868 uint8_t found = entry ? 1 : 0;
4869 write(fd_secure_input, &found, sizeof(uint8_t));
4870
4871 if (found) {
4872 write(fd_secure_input, &size, sizeof(size_t));
4873 write(fd_secure_input, entry, size);
4874 }
4875
4876 free(entry);
4877 }
4878 }
4879
4880 sc_type = RADV_SC_TYPE_DESTROY_DEVICE;
4881 write(fd_secure_input, &sc_type, sizeof(sc_type));
4882
4883 mtx_lock(&device->sc_state->secure_compile_mutex);
4884 device->sc_state->secure_compile_thread_counter--;
4885 device->sc_state->secure_compile_processes[process].in_use = false;
4886 mtx_unlock(&device->sc_state->secure_compile_mutex);
4887
4888 return VK_SUCCESS;
4889 }
4890
4891 static VkResult
4892 radv_pipeline_init(struct radv_pipeline *pipeline,
4893 struct radv_device *device,
4894 struct radv_pipeline_cache *cache,
4895 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4896 const struct radv_graphics_pipeline_create_info *extra)
4897 {
4898 VkResult result;
4899 bool has_view_index = false;
4900
4901 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
4902 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
4903 if (subpass->view_mask)
4904 has_view_index = true;
4905
4906 pipeline->device = device;
4907 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
4908 assert(pipeline->layout);
4909
4910 struct radv_blend_state blend = radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
4911
4912 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
4913 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
4914 radv_init_feedback(creation_feedback);
4915
4916 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
4917
4918 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
4919 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
4920 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
4921 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
4922 pStages[stage] = &pCreateInfo->pStages[i];
4923 if(creation_feedback)
4924 stage_feedbacks[stage] = &creation_feedback->pPipelineStageCreationFeedbacks[i];
4925 }
4926
4927 struct radv_pipeline_key key = radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &blend, has_view_index);
4928 if (radv_device_use_secure_compile(device->instance)) {
4929 return radv_secure_compile(pipeline, device, &key, pStages, pCreateInfo->flags, pCreateInfo->stageCount);
4930 } else {
4931 radv_create_shaders(pipeline, device, cache, &key, pStages, pCreateInfo->flags, pipeline_feedback, stage_feedbacks);
4932 }
4933
4934 pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
4935 radv_pipeline_init_multisample_state(pipeline, &blend, pCreateInfo);
4936 uint32_t gs_out;
4937 uint32_t prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
4938
4939 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
4940
4941 if (radv_pipeline_has_gs(pipeline)) {
4942 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
4943 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
4944 } else if (radv_pipeline_has_tess(pipeline)) {
4945 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.point_mode)
4946 gs_out = V_028A6C_OUTPRIM_TYPE_POINTLIST;
4947 else
4948 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.primitive_mode);
4949 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
4950 } else {
4951 gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
4952 }
4953 if (extra && extra->use_rectlist) {
4954 prim = V_008958_DI_PT_RECTLIST;
4955 gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
4956 pipeline->graphics.can_use_guardband = true;
4957 if (radv_pipeline_has_ngg(pipeline))
4958 gs_out = V_028A6C_VGT_OUT_RECT_V0;
4959 }
4960 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
4961 /* prim vertex count will need TESS changes */
4962 pipeline->graphics.prim_vertex_count = prim_size_table[prim];
4963
4964 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
4965
4966 /* Ensure that some export memory is always allocated, for two reasons:
4967 *
4968 * 1) Correctness: The hardware ignores the EXEC mask if no export
4969 * memory is allocated, so KILL and alpha test do not work correctly
4970 * without this.
4971 * 2) Performance: Every shader needs at least a NULL export, even when
4972 * it writes no color/depth output. The NULL export instruction
4973 * stalls without this setting.
4974 *
4975 * Don't add this to CB_SHADER_MASK.
4976 *
4977 * GFX10 supports pixel shaders without exports by setting both the
4978 * color and Z formats to SPI_SHADER_ZERO. The hw will skip export
4979 * instructions if any are present.
4980 */
4981 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4982 if ((pipeline->device->physical_device->rad_info.chip_class <= GFX9 ||
4983 ps->info.ps.can_discard) &&
4984 !blend.spi_shader_col_format) {
4985 if (!ps->info.ps.writes_z &&
4986 !ps->info.ps.writes_stencil &&
4987 !ps->info.ps.writes_sample_mask)
4988 blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
4989 }
4990
4991 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
4992 if (pipeline->shaders[i]) {
4993 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
4994 }
4995 }
4996
4997 if (radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) {
4998 struct radv_shader_variant *gs =
4999 pipeline->shaders[MESA_SHADER_GEOMETRY];
5000
5001 calculate_gs_ring_sizes(pipeline, &gs->info.gs_ring_info);
5002 }
5003
5004 struct radv_tessellation_state tess = {0};
5005 if (radv_pipeline_has_tess(pipeline)) {
5006 if (prim == V_008958_DI_PT_PATCH) {
5007 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
5008 pipeline->graphics.prim_vertex_count.incr = 1;
5009 }
5010 tess = calculate_tess_state(pipeline, pCreateInfo);
5011 }
5012
5013 pipeline->graphics.ia_multi_vgt_param = radv_compute_ia_multi_vgt_param_helpers(pipeline, &tess, prim);
5014
5015 radv_compute_vertex_input_state(pipeline, pCreateInfo);
5016
5017 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
5018 pipeline->user_data_0[i] = radv_pipeline_stage_to_user_data_0(pipeline, i, device->physical_device->rad_info.chip_class);
5019
5020 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
5021 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
5022 if (loc->sgpr_idx != -1) {
5023 pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX];
5024 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
5025 if (radv_get_shader(pipeline, MESA_SHADER_VERTEX)->info.vs.needs_draw_id)
5026 pipeline->graphics.vtx_emit_num = 3;
5027 else
5028 pipeline->graphics.vtx_emit_num = 2;
5029 }
5030
5031 /* Find the last vertex shader stage that eventually uses streamout. */
5032 pipeline->streamout_shader = radv_pipeline_get_streamout_shader(pipeline);
5033
5034 result = radv_pipeline_scratch_init(device, pipeline);
5035 radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend, &tess, prim, gs_out);
5036
5037 return result;
5038 }
5039
5040 VkResult
5041 radv_graphics_pipeline_create(
5042 VkDevice _device,
5043 VkPipelineCache _cache,
5044 const VkGraphicsPipelineCreateInfo *pCreateInfo,
5045 const struct radv_graphics_pipeline_create_info *extra,
5046 const VkAllocationCallbacks *pAllocator,
5047 VkPipeline *pPipeline)
5048 {
5049 RADV_FROM_HANDLE(radv_device, device, _device);
5050 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
5051 struct radv_pipeline *pipeline;
5052 VkResult result;
5053
5054 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
5055 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5056 if (pipeline == NULL)
5057 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5058
5059 result = radv_pipeline_init(pipeline, device, cache,
5060 pCreateInfo, extra);
5061 if (result != VK_SUCCESS) {
5062 radv_pipeline_destroy(device, pipeline, pAllocator);
5063 return result;
5064 }
5065
5066 *pPipeline = radv_pipeline_to_handle(pipeline);
5067
5068 return VK_SUCCESS;
5069 }
5070
5071 VkResult radv_CreateGraphicsPipelines(
5072 VkDevice _device,
5073 VkPipelineCache pipelineCache,
5074 uint32_t count,
5075 const VkGraphicsPipelineCreateInfo* pCreateInfos,
5076 const VkAllocationCallbacks* pAllocator,
5077 VkPipeline* pPipelines)
5078 {
5079 VkResult result = VK_SUCCESS;
5080 unsigned i = 0;
5081
5082 for (; i < count; i++) {
5083 VkResult r;
5084 r = radv_graphics_pipeline_create(_device,
5085 pipelineCache,
5086 &pCreateInfos[i],
5087 NULL, pAllocator, &pPipelines[i]);
5088 if (r != VK_SUCCESS) {
5089 result = r;
5090 pPipelines[i] = VK_NULL_HANDLE;
5091 }
5092 }
5093
5094 return result;
5095 }
5096
5097
5098 static void
5099 radv_compute_generate_pm4(struct radv_pipeline *pipeline)
5100 {
5101 struct radv_shader_variant *compute_shader;
5102 struct radv_device *device = pipeline->device;
5103 unsigned threads_per_threadgroup;
5104 unsigned threadgroups_per_cu = 1;
5105 unsigned waves_per_threadgroup;
5106 unsigned max_waves_per_sh = 0;
5107 uint64_t va;
5108
5109 pipeline->cs.max_dw = device->physical_device->rad_info.chip_class >= GFX10 ? 22 : 20;
5110 pipeline->cs.buf = malloc(pipeline->cs.max_dw * 4);
5111
5112 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
5113 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
5114
5115 radeon_set_sh_reg_seq(&pipeline->cs, R_00B830_COMPUTE_PGM_LO, 2);
5116 radeon_emit(&pipeline->cs, va >> 8);
5117 radeon_emit(&pipeline->cs, S_00B834_DATA(va >> 40));
5118
5119 radeon_set_sh_reg_seq(&pipeline->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
5120 radeon_emit(&pipeline->cs, compute_shader->config.rsrc1);
5121 radeon_emit(&pipeline->cs, compute_shader->config.rsrc2);
5122 if (device->physical_device->rad_info.chip_class >= GFX10) {
5123 radeon_set_sh_reg(&pipeline->cs, R_00B8A0_COMPUTE_PGM_RSRC3, compute_shader->config.rsrc3);
5124 }
5125
5126 /* Calculate best compute resource limits. */
5127 threads_per_threadgroup = compute_shader->info.cs.block_size[0] *
5128 compute_shader->info.cs.block_size[1] *
5129 compute_shader->info.cs.block_size[2];
5130 waves_per_threadgroup = DIV_ROUND_UP(threads_per_threadgroup,
5131 compute_shader->info.wave_size);
5132
5133 if (device->physical_device->rad_info.chip_class >= GFX10 &&
5134 waves_per_threadgroup == 1)
5135 threadgroups_per_cu = 2;
5136
5137 radeon_set_sh_reg(&pipeline->cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
5138 ac_get_compute_resource_limits(&device->physical_device->rad_info,
5139 waves_per_threadgroup,
5140 max_waves_per_sh,
5141 threadgroups_per_cu));
5142
5143 radeon_set_sh_reg_seq(&pipeline->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
5144 radeon_emit(&pipeline->cs,
5145 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
5146 radeon_emit(&pipeline->cs,
5147 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
5148 radeon_emit(&pipeline->cs,
5149 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
5150
5151 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
5152 }
5153
5154 static struct radv_pipeline_key
5155 radv_generate_compute_pipeline_key(struct radv_pipeline *pipeline,
5156 const VkComputePipelineCreateInfo *pCreateInfo)
5157 {
5158 const VkPipelineShaderStageCreateInfo *stage = &pCreateInfo->stage;
5159 struct radv_pipeline_key key;
5160 memset(&key, 0, sizeof(key));
5161
5162 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
5163 key.optimisations_disabled = 1;
5164
5165 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT *subgroup_size =
5166 vk_find_struct_const(stage->pNext,
5167 PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT);
5168
5169 if (subgroup_size) {
5170 assert(subgroup_size->requiredSubgroupSize == 32 ||
5171 subgroup_size->requiredSubgroupSize == 64);
5172 key.compute_subgroup_size = subgroup_size->requiredSubgroupSize;
5173 }
5174
5175 return key;
5176 }
5177
5178 static VkResult radv_compute_pipeline_create(
5179 VkDevice _device,
5180 VkPipelineCache _cache,
5181 const VkComputePipelineCreateInfo* pCreateInfo,
5182 const VkAllocationCallbacks* pAllocator,
5183 VkPipeline* pPipeline)
5184 {
5185 RADV_FROM_HANDLE(radv_device, device, _device);
5186 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
5187 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
5188 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
5189 struct radv_pipeline *pipeline;
5190 VkResult result;
5191
5192 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
5193 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5194 if (pipeline == NULL)
5195 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5196
5197 pipeline->device = device;
5198 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
5199 assert(pipeline->layout);
5200
5201 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
5202 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
5203 radv_init_feedback(creation_feedback);
5204
5205 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
5206 if (creation_feedback)
5207 stage_feedbacks[MESA_SHADER_COMPUTE] = &creation_feedback->pPipelineStageCreationFeedbacks[0];
5208
5209 pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
5210
5211 struct radv_pipeline_key key =
5212 radv_generate_compute_pipeline_key(pipeline, pCreateInfo);
5213
5214 if (radv_device_use_secure_compile(device->instance)) {
5215 result = radv_secure_compile(pipeline, device, &key, pStages, pCreateInfo->flags, 1);
5216 *pPipeline = radv_pipeline_to_handle(pipeline);
5217
5218 return result;
5219 } else {
5220 radv_create_shaders(pipeline, device, cache, &key, pStages, pCreateInfo->flags, pipeline_feedback, stage_feedbacks);
5221 }
5222
5223 pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
5224 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
5225 result = radv_pipeline_scratch_init(device, pipeline);
5226 if (result != VK_SUCCESS) {
5227 radv_pipeline_destroy(device, pipeline, pAllocator);
5228 return result;
5229 }
5230
5231 radv_compute_generate_pm4(pipeline);
5232
5233 *pPipeline = radv_pipeline_to_handle(pipeline);
5234
5235 return VK_SUCCESS;
5236 }
5237
5238 VkResult radv_CreateComputePipelines(
5239 VkDevice _device,
5240 VkPipelineCache pipelineCache,
5241 uint32_t count,
5242 const VkComputePipelineCreateInfo* pCreateInfos,
5243 const VkAllocationCallbacks* pAllocator,
5244 VkPipeline* pPipelines)
5245 {
5246 VkResult result = VK_SUCCESS;
5247
5248 unsigned i = 0;
5249 for (; i < count; i++) {
5250 VkResult r;
5251 r = radv_compute_pipeline_create(_device, pipelineCache,
5252 &pCreateInfos[i],
5253 pAllocator, &pPipelines[i]);
5254 if (r != VK_SUCCESS) {
5255 result = r;
5256 pPipelines[i] = VK_NULL_HANDLE;
5257 }
5258 }
5259
5260 return result;
5261 }
5262
5263
5264 static uint32_t radv_get_executable_count(const struct radv_pipeline *pipeline)
5265 {
5266 uint32_t ret = 0;
5267 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
5268 if (!pipeline->shaders[i])
5269 continue;
5270
5271 if (i == MESA_SHADER_GEOMETRY &&
5272 !radv_pipeline_has_ngg(pipeline)) {
5273 ret += 2u;
5274 } else {
5275 ret += 1u;
5276 }
5277
5278 }
5279 return ret;
5280 }
5281
5282 static struct radv_shader_variant *
5283 radv_get_shader_from_executable_index(const struct radv_pipeline *pipeline, int index, gl_shader_stage *stage)
5284 {
5285 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
5286 if (!pipeline->shaders[i])
5287 continue;
5288 if (!index) {
5289 *stage = i;
5290 return pipeline->shaders[i];
5291 }
5292
5293 --index;
5294
5295 if (i == MESA_SHADER_GEOMETRY &&
5296 !radv_pipeline_has_ngg(pipeline)) {
5297 if (!index) {
5298 *stage = i;
5299 return pipeline->gs_copy_shader;
5300 }
5301 --index;
5302 }
5303 }
5304
5305 *stage = -1;
5306 return NULL;
5307 }
5308
5309 /* Basically strlcpy (which does not exist on linux) specialized for
5310 * descriptions. */
5311 static void desc_copy(char *desc, const char *src) {
5312 int len = strlen(src);
5313 assert(len < VK_MAX_DESCRIPTION_SIZE);
5314 memcpy(desc, src, len);
5315 memset(desc + len, 0, VK_MAX_DESCRIPTION_SIZE - len);
5316 }
5317
5318 VkResult radv_GetPipelineExecutablePropertiesKHR(
5319 VkDevice _device,
5320 const VkPipelineInfoKHR* pPipelineInfo,
5321 uint32_t* pExecutableCount,
5322 VkPipelineExecutablePropertiesKHR* pProperties)
5323 {
5324 RADV_FROM_HANDLE(radv_pipeline, pipeline, pPipelineInfo->pipeline);
5325 const uint32_t total_count = radv_get_executable_count(pipeline);
5326
5327 if (!pProperties) {
5328 *pExecutableCount = total_count;
5329 return VK_SUCCESS;
5330 }
5331
5332 const uint32_t count = MIN2(total_count, *pExecutableCount);
5333 for (unsigned i = 0, executable_idx = 0;
5334 i < MESA_SHADER_STAGES && executable_idx < count; ++i) {
5335 if (!pipeline->shaders[i])
5336 continue;
5337 pProperties[executable_idx].stages = mesa_to_vk_shader_stage(i);
5338 const char *name = NULL;
5339 const char *description = NULL;
5340 switch(i) {
5341 case MESA_SHADER_VERTEX:
5342 name = "Vertex Shader";
5343 description = "Vulkan Vertex Shader";
5344 break;
5345 case MESA_SHADER_TESS_CTRL:
5346 if (!pipeline->shaders[MESA_SHADER_VERTEX]) {
5347 pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT;
5348 name = "Vertex + Tessellation Control Shaders";
5349 description = "Combined Vulkan Vertex and Tessellation Control Shaders";
5350 } else {
5351 name = "Tessellation Control Shader";
5352 description = "Vulkan Tessellation Control Shader";
5353 }
5354 break;
5355 case MESA_SHADER_TESS_EVAL:
5356 name = "Tessellation Evaluation Shader";
5357 description = "Vulkan Tessellation Evaluation Shader";
5358 break;
5359 case MESA_SHADER_GEOMETRY:
5360 if (radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_TESS_EVAL]) {
5361 pProperties[executable_idx].stages |= VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT;
5362 name = "Tessellation Evaluation + Geometry Shaders";
5363 description = "Combined Vulkan Tessellation Evaluation and Geometry Shaders";
5364 } else if (!radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_VERTEX]) {
5365 pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT;
5366 name = "Vertex + Geometry Shader";
5367 description = "Combined Vulkan Vertex and Geometry Shaders";
5368 } else {
5369 name = "Geometry Shader";
5370 description = "Vulkan Geometry Shader";
5371 }
5372 break;
5373 case MESA_SHADER_FRAGMENT:
5374 name = "Fragment Shader";
5375 description = "Vulkan Fragment Shader";
5376 break;
5377 case MESA_SHADER_COMPUTE:
5378 name = "Compute Shader";
5379 description = "Vulkan Compute Shader";
5380 break;
5381 }
5382
5383 pProperties[executable_idx].subgroupSize = pipeline->shaders[i]->info.wave_size;
5384 desc_copy(pProperties[executable_idx].name, name);
5385 desc_copy(pProperties[executable_idx].description, description);
5386
5387 ++executable_idx;
5388 if (i == MESA_SHADER_GEOMETRY &&
5389 !radv_pipeline_has_ngg(pipeline)) {
5390 assert(pipeline->gs_copy_shader);
5391 if (executable_idx >= count)
5392 break;
5393
5394 pProperties[executable_idx].stages = VK_SHADER_STAGE_GEOMETRY_BIT;
5395 pProperties[executable_idx].subgroupSize = 64;
5396 desc_copy(pProperties[executable_idx].name, "GS Copy Shader");
5397 desc_copy(pProperties[executable_idx].description,
5398 "Extra shader stage that loads the GS output ringbuffer into the rasterizer");
5399
5400 ++executable_idx;
5401 }
5402 }
5403
5404 VkResult result = *pExecutableCount < total_count ? VK_INCOMPLETE : VK_SUCCESS;
5405 *pExecutableCount = count;
5406 return result;
5407 }
5408
5409 VkResult radv_GetPipelineExecutableStatisticsKHR(
5410 VkDevice _device,
5411 const VkPipelineExecutableInfoKHR* pExecutableInfo,
5412 uint32_t* pStatisticCount,
5413 VkPipelineExecutableStatisticKHR* pStatistics)
5414 {
5415 RADV_FROM_HANDLE(radv_device, device, _device);
5416 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
5417 gl_shader_stage stage;
5418 struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
5419
5420 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
5421 unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
5422 unsigned max_waves = radv_get_max_waves(device, shader, stage);
5423
5424 VkPipelineExecutableStatisticKHR *s = pStatistics;
5425 VkPipelineExecutableStatisticKHR *end = s + (pStatistics ? *pStatisticCount : 0);
5426 VkResult result = VK_SUCCESS;
5427
5428 if (s < end) {
5429 desc_copy(s->name, "SGPRs");
5430 desc_copy(s->description, "Number of SGPR registers allocated per subgroup");
5431 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5432 s->value.u64 = shader->config.num_sgprs;
5433 }
5434 ++s;
5435
5436 if (s < end) {
5437 desc_copy(s->name, "VGPRs");
5438 desc_copy(s->description, "Number of VGPR registers allocated per subgroup");
5439 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5440 s->value.u64 = shader->config.num_vgprs;
5441 }
5442 ++s;
5443
5444 if (s < end) {
5445 desc_copy(s->name, "Spilled SGPRs");
5446 desc_copy(s->description, "Number of SGPR registers spilled per subgroup");
5447 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5448 s->value.u64 = shader->config.spilled_sgprs;
5449 }
5450 ++s;
5451
5452 if (s < end) {
5453 desc_copy(s->name, "Spilled VGPRs");
5454 desc_copy(s->description, "Number of VGPR registers spilled per subgroup");
5455 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5456 s->value.u64 = shader->config.spilled_vgprs;
5457 }
5458 ++s;
5459
5460 if (s < end) {
5461 desc_copy(s->name, "PrivMem VGPRs");
5462 desc_copy(s->description, "Number of VGPRs stored in private memory per subgroup");
5463 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5464 s->value.u64 = shader->info.private_mem_vgprs;
5465 }
5466 ++s;
5467
5468 if (s < end) {
5469 desc_copy(s->name, "Code size");
5470 desc_copy(s->description, "Code size in bytes");
5471 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5472 s->value.u64 = shader->exec_size;
5473 }
5474 ++s;
5475
5476 if (s < end) {
5477 desc_copy(s->name, "LDS size");
5478 desc_copy(s->description, "LDS size in bytes per workgroup");
5479 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5480 s->value.u64 = shader->config.lds_size * lds_increment;
5481 }
5482 ++s;
5483
5484 if (s < end) {
5485 desc_copy(s->name, "Scratch size");
5486 desc_copy(s->description, "Private memory in bytes per subgroup");
5487 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5488 s->value.u64 = shader->config.scratch_bytes_per_wave;
5489 }
5490 ++s;
5491
5492 if (s < end) {
5493 desc_copy(s->name, "Subgroups per SIMD");
5494 desc_copy(s->description, "The maximum number of subgroups in flight on a SIMD unit");
5495 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5496 s->value.u64 = max_waves;
5497 }
5498 ++s;
5499
5500 if (!pStatistics)
5501 *pStatisticCount = s - pStatistics;
5502 else if (s > end) {
5503 *pStatisticCount = end - pStatistics;
5504 result = VK_INCOMPLETE;
5505 } else {
5506 *pStatisticCount = s - pStatistics;
5507 }
5508
5509 return result;
5510 }
5511
5512 static VkResult radv_copy_representation(void *data, size_t *data_size, const char *src)
5513 {
5514 size_t total_size = strlen(src) + 1;
5515
5516 if (!data) {
5517 *data_size = total_size;
5518 return VK_SUCCESS;
5519 }
5520
5521 size_t size = MIN2(total_size, *data_size);
5522
5523 memcpy(data, src, size);
5524 if (size)
5525 *((char*)data + size - 1) = 0;
5526 return size < total_size ? VK_INCOMPLETE : VK_SUCCESS;
5527 }
5528
5529 VkResult radv_GetPipelineExecutableInternalRepresentationsKHR(
5530 VkDevice device,
5531 const VkPipelineExecutableInfoKHR* pExecutableInfo,
5532 uint32_t* pInternalRepresentationCount,
5533 VkPipelineExecutableInternalRepresentationKHR* pInternalRepresentations)
5534 {
5535 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
5536 gl_shader_stage stage;
5537 struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
5538
5539 VkPipelineExecutableInternalRepresentationKHR *p = pInternalRepresentations;
5540 VkPipelineExecutableInternalRepresentationKHR *end = p + (pInternalRepresentations ? *pInternalRepresentationCount : 0);
5541 VkResult result = VK_SUCCESS;
5542 /* optimized NIR */
5543 if (p < end) {
5544 p->isText = true;
5545 desc_copy(p->name, "NIR Shader(s)");
5546 desc_copy(p->description, "The optimized NIR shader(s)");
5547 if (radv_copy_representation(p->pData, &p->dataSize, shader->nir_string) != VK_SUCCESS)
5548 result = VK_INCOMPLETE;
5549 }
5550 ++p;
5551
5552 /* backend IR */
5553 if (p < end) {
5554 p->isText = true;
5555 if (shader->aco_used) {
5556 desc_copy(p->name, "ACO IR");
5557 desc_copy(p->description, "The ACO IR after some optimizations");
5558 } else {
5559 desc_copy(p->name, "LLVM IR");
5560 desc_copy(p->description, "The LLVM IR after some optimizations");
5561 }
5562 if (radv_copy_representation(p->pData, &p->dataSize, shader->ir_string) != VK_SUCCESS)
5563 result = VK_INCOMPLETE;
5564 }
5565 ++p;
5566
5567 /* Disassembler */
5568 if (p < end) {
5569 p->isText = true;
5570 desc_copy(p->name, "Assembly");
5571 desc_copy(p->description, "Final Assembly");
5572 if (radv_copy_representation(p->pData, &p->dataSize, shader->disasm_string) != VK_SUCCESS)
5573 result = VK_INCOMPLETE;
5574 }
5575 ++p;
5576
5577 if (!pInternalRepresentations)
5578 *pInternalRepresentationCount = p - pInternalRepresentations;
5579 else if(p > end) {
5580 result = VK_INCOMPLETE;
5581 *pInternalRepresentationCount = end - pInternalRepresentations;
5582 } else {
5583 *pInternalRepresentationCount = p - pInternalRepresentations;
5584 }
5585
5586 return result;
5587 }