projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
ac: move num_sdp_interfaces into radeon_info
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_cs.h"
33 #include "radv_shader.h"
34 #include "nir/nir.h"
35 #include "nir/nir_builder.h"
36 #include "nir/nir_xfb_info.h"
37 #include "spirv/nir_spirv.h"
38 #include "vk_util.h"
39
40 #include <llvm-c/Core.h>
41 #include <llvm-c/TargetMachine.h>
42
43 #include "sid.h"
44 #include "ac_binary.h"
45 #include "ac_llvm_util.h"
46 #include "ac_nir_to_llvm.h"
47 #include "vk_format.h"
48 #include "util/debug.h"
49 #include "ac_exp_param.h"
50 #include "ac_shader_util.h"
51 #include "main/menums.h"
52
53 struct radv_blend_state {
54 uint32_t blend_enable_4bit;
55 uint32_t need_src_alpha;
56
57 uint32_t cb_color_control;
58 uint32_t cb_target_mask;
59 uint32_t cb_target_enabled_4bit;
60 uint32_t sx_mrt_blend_opt[8];
61 uint32_t cb_blend_control[8];
62
63 uint32_t spi_shader_col_format;
64 uint32_t cb_shader_mask;
65 uint32_t db_alpha_to_mask;
66
67 uint32_t commutative_4bit;
68
69 bool single_cb_enable;
70 bool mrt0_is_dual_src;
71 };
72
73 struct radv_dsa_order_invariance {
74 /* Whether the final result in Z/S buffers is guaranteed to be
75 * invariant under changes to the order in which fragments arrive.
76 */
77 bool zs;
78
79 /* Whether the set of fragments that pass the combined Z/S test is
80 * guaranteed to be invariant under changes to the order in which
81 * fragments arrive.
82 */
83 bool pass_set;
84 };
85
86 struct radv_tessellation_state {
87 uint32_t ls_hs_config;
88 unsigned num_patches;
89 unsigned lds_size;
90 uint32_t tf_param;
91 };
92
93 bool radv_pipeline_has_ngg(const struct radv_pipeline *pipeline)
94 {
95 struct radv_shader_variant *variant = NULL;
96 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
97 variant = pipeline->shaders[MESA_SHADER_GEOMETRY];
98 else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
99 variant = pipeline->shaders[MESA_SHADER_TESS_EVAL];
100 else if (pipeline->shaders[MESA_SHADER_VERTEX])
101 variant = pipeline->shaders[MESA_SHADER_VERTEX];
102 else
103 return false;
104 return variant->info.is_ngg;
105 }
106
107 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline *pipeline)
108 {
109 if (!radv_pipeline_has_gs(pipeline))
110 return false;
111
112 /* The GS copy shader is required if the pipeline has GS on GFX6-GFX9.
113 * On GFX10, it might be required in rare cases if it's not possible to
114 * enable NGG.
115 */
116 if (radv_pipeline_has_ngg(pipeline))
117 return false;
118
119 assert(pipeline->gs_copy_shader);
120 return true;
121 }
122
123 static void
124 radv_pipeline_destroy(struct radv_device *device,
125 struct radv_pipeline *pipeline,
126 const VkAllocationCallbacks* allocator)
127 {
128 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
129 if (pipeline->shaders[i])
130 radv_shader_variant_destroy(device, pipeline->shaders[i]);
131
132 if (pipeline->gs_copy_shader)
133 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
134
135 if(pipeline->cs.buf)
136 free(pipeline->cs.buf);
137 vk_free2(&device->alloc, allocator, pipeline);
138 }
139
140 void radv_DestroyPipeline(
141 VkDevice _device,
142 VkPipeline _pipeline,
143 const VkAllocationCallbacks* pAllocator)
144 {
145 RADV_FROM_HANDLE(radv_device, device, _device);
146 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
147
148 if (!_pipeline)
149 return;
150
151 radv_pipeline_destroy(device, pipeline, pAllocator);
152 }
153
154 static uint32_t get_hash_flags(struct radv_device *device)
155 {
156 uint32_t hash_flags = 0;
157
158 if (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH)
159 hash_flags |= RADV_HASH_SHADER_UNSAFE_MATH;
160 if (device->instance->debug_flags & RADV_DEBUG_NO_NGG)
161 hash_flags |= RADV_HASH_SHADER_NO_NGG;
162 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
163 hash_flags |= RADV_HASH_SHADER_SISCHED;
164 if (device->physical_device->cs_wave_size == 32)
165 hash_flags |= RADV_HASH_SHADER_CS_WAVE32;
166 if (device->physical_device->ps_wave_size == 32)
167 hash_flags |= RADV_HASH_SHADER_PS_WAVE32;
168 if (device->physical_device->ge_wave_size == 32)
169 hash_flags |= RADV_HASH_SHADER_GE_WAVE32;
170 return hash_flags;
171 }
172
173 static VkResult
174 radv_pipeline_scratch_init(struct radv_device *device,
175 struct radv_pipeline *pipeline)
176 {
177 unsigned scratch_bytes_per_wave = 0;
178 unsigned max_waves = 0;
179 unsigned min_waves = 1;
180
181 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
182 if (pipeline->shaders[i]) {
183 unsigned max_stage_waves = device->scratch_waves;
184
185 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
186 pipeline->shaders[i]->config.scratch_bytes_per_wave);
187
188 max_stage_waves = MIN2(max_stage_waves,
189 4 * device->physical_device->rad_info.num_good_compute_units *
190 (256 / pipeline->shaders[i]->config.num_vgprs));
191 max_waves = MAX2(max_waves, max_stage_waves);
192 }
193 }
194
195 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
196 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
197 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
198 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
199 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
200 }
201
202 if (scratch_bytes_per_wave)
203 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
204
205 if (scratch_bytes_per_wave && max_waves < min_waves) {
206 /* Not really true at this moment, but will be true on first
207 * execution. Avoid having hanging shaders. */
208 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
209 }
210 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
211 pipeline->max_waves = max_waves;
212 return VK_SUCCESS;
213 }
214
215 static uint32_t si_translate_blend_logic_op(VkLogicOp op)
216 {
217 switch (op) {
218 case VK_LOGIC_OP_CLEAR:
219 return V_028808_ROP3_CLEAR;
220 case VK_LOGIC_OP_AND:
221 return V_028808_ROP3_AND;
222 case VK_LOGIC_OP_AND_REVERSE:
223 return V_028808_ROP3_AND_REVERSE;
224 case VK_LOGIC_OP_COPY:
225 return V_028808_ROP3_COPY;
226 case VK_LOGIC_OP_AND_INVERTED:
227 return V_028808_ROP3_AND_INVERTED;
228 case VK_LOGIC_OP_NO_OP:
229 return V_028808_ROP3_NO_OP;
230 case VK_LOGIC_OP_XOR:
231 return V_028808_ROP3_XOR;
232 case VK_LOGIC_OP_OR:
233 return V_028808_ROP3_OR;
234 case VK_LOGIC_OP_NOR:
235 return V_028808_ROP3_NOR;
236 case VK_LOGIC_OP_EQUIVALENT:
237 return V_028808_ROP3_EQUIVALENT;
238 case VK_LOGIC_OP_INVERT:
239 return V_028808_ROP3_INVERT;
240 case VK_LOGIC_OP_OR_REVERSE:
241 return V_028808_ROP3_OR_REVERSE;
242 case VK_LOGIC_OP_COPY_INVERTED:
243 return V_028808_ROP3_COPY_INVERTED;
244 case VK_LOGIC_OP_OR_INVERTED:
245 return V_028808_ROP3_OR_INVERTED;
246 case VK_LOGIC_OP_NAND:
247 return V_028808_ROP3_NAND;
248 case VK_LOGIC_OP_SET:
249 return V_028808_ROP3_SET;
250 default:
251 unreachable("Unhandled logic op");
252 }
253 }
254
255
256 static uint32_t si_translate_blend_function(VkBlendOp op)
257 {
258 switch (op) {
259 case VK_BLEND_OP_ADD:
260 return V_028780_COMB_DST_PLUS_SRC;
261 case VK_BLEND_OP_SUBTRACT:
262 return V_028780_COMB_SRC_MINUS_DST;
263 case VK_BLEND_OP_REVERSE_SUBTRACT:
264 return V_028780_COMB_DST_MINUS_SRC;
265 case VK_BLEND_OP_MIN:
266 return V_028780_COMB_MIN_DST_SRC;
267 case VK_BLEND_OP_MAX:
268 return V_028780_COMB_MAX_DST_SRC;
269 default:
270 return 0;
271 }
272 }
273
274 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
275 {
276 switch (factor) {
277 case VK_BLEND_FACTOR_ZERO:
278 return V_028780_BLEND_ZERO;
279 case VK_BLEND_FACTOR_ONE:
280 return V_028780_BLEND_ONE;
281 case VK_BLEND_FACTOR_SRC_COLOR:
282 return V_028780_BLEND_SRC_COLOR;
283 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
284 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
285 case VK_BLEND_FACTOR_DST_COLOR:
286 return V_028780_BLEND_DST_COLOR;
287 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
288 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
289 case VK_BLEND_FACTOR_SRC_ALPHA:
290 return V_028780_BLEND_SRC_ALPHA;
291 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
292 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
293 case VK_BLEND_FACTOR_DST_ALPHA:
294 return V_028780_BLEND_DST_ALPHA;
295 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
296 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
297 case VK_BLEND_FACTOR_CONSTANT_COLOR:
298 return V_028780_BLEND_CONSTANT_COLOR;
299 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
300 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
301 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
302 return V_028780_BLEND_CONSTANT_ALPHA;
303 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
304 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
305 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
306 return V_028780_BLEND_SRC_ALPHA_SATURATE;
307 case VK_BLEND_FACTOR_SRC1_COLOR:
308 return V_028780_BLEND_SRC1_COLOR;
309 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
310 return V_028780_BLEND_INV_SRC1_COLOR;
311 case VK_BLEND_FACTOR_SRC1_ALPHA:
312 return V_028780_BLEND_SRC1_ALPHA;
313 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
314 return V_028780_BLEND_INV_SRC1_ALPHA;
315 default:
316 return 0;
317 }
318 }
319
320 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
321 {
322 switch (op) {
323 case VK_BLEND_OP_ADD:
324 return V_028760_OPT_COMB_ADD;
325 case VK_BLEND_OP_SUBTRACT:
326 return V_028760_OPT_COMB_SUBTRACT;
327 case VK_BLEND_OP_REVERSE_SUBTRACT:
328 return V_028760_OPT_COMB_REVSUBTRACT;
329 case VK_BLEND_OP_MIN:
330 return V_028760_OPT_COMB_MIN;
331 case VK_BLEND_OP_MAX:
332 return V_028760_OPT_COMB_MAX;
333 default:
334 return V_028760_OPT_COMB_BLEND_DISABLED;
335 }
336 }
337
338 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
339 {
340 switch (factor) {
341 case VK_BLEND_FACTOR_ZERO:
342 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
343 case VK_BLEND_FACTOR_ONE:
344 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
345 case VK_BLEND_FACTOR_SRC_COLOR:
346 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
347 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
348 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
349 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
350 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
351 case VK_BLEND_FACTOR_SRC_ALPHA:
352 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
353 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
354 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
355 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
356 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
357 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
358 default:
359 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
360 }
361 }
362
363 /**
364 * Get rid of DST in the blend factors by commuting the operands:
365 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
366 */
367 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
368 unsigned *dst_factor, unsigned expected_dst,
369 unsigned replacement_src)
370 {
371 if (*src_factor == expected_dst &&
372 *dst_factor == VK_BLEND_FACTOR_ZERO) {
373 *src_factor = VK_BLEND_FACTOR_ZERO;
374 *dst_factor = replacement_src;
375
376 /* Commuting the operands requires reversing subtractions. */
377 if (*func == VK_BLEND_OP_SUBTRACT)
378 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
379 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
380 *func = VK_BLEND_OP_SUBTRACT;
381 }
382 }
383
384 static bool si_blend_factor_uses_dst(unsigned factor)
385 {
386 return factor == VK_BLEND_FACTOR_DST_COLOR ||
387 factor == VK_BLEND_FACTOR_DST_ALPHA ||
388 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
389 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
390 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
391 }
392
393 static bool is_dual_src(VkBlendFactor factor)
394 {
395 switch (factor) {
396 case VK_BLEND_FACTOR_SRC1_COLOR:
397 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
398 case VK_BLEND_FACTOR_SRC1_ALPHA:
399 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
400 return true;
401 default:
402 return false;
403 }
404 }
405
406 static unsigned si_choose_spi_color_format(VkFormat vk_format,
407 bool blend_enable,
408 bool blend_need_alpha)
409 {
410 const struct vk_format_description *desc = vk_format_description(vk_format);
411 unsigned format, ntype, swap;
412
413 /* Alpha is needed for alpha-to-coverage.
414 * Blending may be with or without alpha.
415 */
416 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
417 unsigned alpha = 0; /* exports alpha, but may not support blending */
418 unsigned blend = 0; /* supports blending, but may not export alpha */
419 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
420
421 format = radv_translate_colorformat(vk_format);
422 ntype = radv_translate_color_numformat(vk_format, desc,
423 vk_format_get_first_non_void_channel(vk_format));
424 swap = radv_translate_colorswap(vk_format, false);
425
426 /* Choose the SPI color formats. These are required values for Stoney/RB+.
427 * Other chips have multiple choices, though they are not necessarily better.
428 */
429 switch (format) {
430 case V_028C70_COLOR_5_6_5:
431 case V_028C70_COLOR_1_5_5_5:
432 case V_028C70_COLOR_5_5_5_1:
433 case V_028C70_COLOR_4_4_4_4:
434 case V_028C70_COLOR_10_11_11:
435 case V_028C70_COLOR_11_11_10:
436 case V_028C70_COLOR_8:
437 case V_028C70_COLOR_8_8:
438 case V_028C70_COLOR_8_8_8_8:
439 case V_028C70_COLOR_10_10_10_2:
440 case V_028C70_COLOR_2_10_10_10:
441 if (ntype == V_028C70_NUMBER_UINT)
442 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
443 else if (ntype == V_028C70_NUMBER_SINT)
444 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
445 else
446 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
447 break;
448
449 case V_028C70_COLOR_16:
450 case V_028C70_COLOR_16_16:
451 case V_028C70_COLOR_16_16_16_16:
452 if (ntype == V_028C70_NUMBER_UNORM ||
453 ntype == V_028C70_NUMBER_SNORM) {
454 /* UNORM16 and SNORM16 don't support blending */
455 if (ntype == V_028C70_NUMBER_UNORM)
456 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
457 else
458 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
459
460 /* Use 32 bits per channel for blending. */
461 if (format == V_028C70_COLOR_16) {
462 if (swap == V_028C70_SWAP_STD) { /* R */
463 blend = V_028714_SPI_SHADER_32_R;
464 blend_alpha = V_028714_SPI_SHADER_32_AR;
465 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
466 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
467 else
468 assert(0);
469 } else if (format == V_028C70_COLOR_16_16) {
470 if (swap == V_028C70_SWAP_STD) { /* RG */
471 blend = V_028714_SPI_SHADER_32_GR;
472 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
473 } else if (swap == V_028C70_SWAP_ALT) /* RA */
474 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
475 else
476 assert(0);
477 } else /* 16_16_16_16 */
478 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
479 } else if (ntype == V_028C70_NUMBER_UINT)
480 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
481 else if (ntype == V_028C70_NUMBER_SINT)
482 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
483 else if (ntype == V_028C70_NUMBER_FLOAT)
484 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
485 else
486 assert(0);
487 break;
488
489 case V_028C70_COLOR_32:
490 if (swap == V_028C70_SWAP_STD) { /* R */
491 blend = normal = V_028714_SPI_SHADER_32_R;
492 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
493 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
494 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
495 else
496 assert(0);
497 break;
498
499 case V_028C70_COLOR_32_32:
500 if (swap == V_028C70_SWAP_STD) { /* RG */
501 blend = normal = V_028714_SPI_SHADER_32_GR;
502 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
503 } else if (swap == V_028C70_SWAP_ALT) /* RA */
504 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
505 else
506 assert(0);
507 break;
508
509 case V_028C70_COLOR_32_32_32_32:
510 case V_028C70_COLOR_8_24:
511 case V_028C70_COLOR_24_8:
512 case V_028C70_COLOR_X24_8_32_FLOAT:
513 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
514 break;
515
516 default:
517 unreachable("unhandled blend format");
518 }
519
520 if (blend_enable && blend_need_alpha)
521 return blend_alpha;
522 else if(blend_need_alpha)
523 return alpha;
524 else if(blend_enable)
525 return blend;
526 else
527 return normal;
528 }
529
530 static void
531 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
532 const VkGraphicsPipelineCreateInfo *pCreateInfo,
533 struct radv_blend_state *blend)
534 {
535 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
536 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
537 unsigned col_format = 0;
538 unsigned num_targets;
539
540 for (unsigned i = 0; i < (blend->single_cb_enable ? 1 : subpass->color_count); ++i) {
541 unsigned cf;
542
543 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
544 cf = V_028714_SPI_SHADER_ZERO;
545 } else {
546 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
547 bool blend_enable =
548 blend->blend_enable_4bit & (0xfu << (i * 4));
549
550 cf = si_choose_spi_color_format(attachment->format,
551 blend_enable,
552 blend->need_src_alpha & (1 << i));
553 }
554
555 col_format |= cf << (4 * i);
556 }
557
558 if (!(col_format & 0xf) && blend->need_src_alpha & (1 << 0)) {
559 /* When a subpass doesn't have any color attachments, write the
560 * alpha channel of MRT0 when alpha coverage is enabled because
561 * the depth attachment needs it.
562 */
563 col_format |= V_028714_SPI_SHADER_32_AR;
564 }
565
566 /* If the i-th target format is set, all previous target formats must
567 * be non-zero to avoid hangs.
568 */
569 num_targets = (util_last_bit(col_format) + 3) / 4;
570 for (unsigned i = 0; i < num_targets; i++) {
571 if (!(col_format & (0xf << (i * 4)))) {
572 col_format |= V_028714_SPI_SHADER_32_R << (i * 4);
573 }
574 }
575
576 /* The output for dual source blending should have the same format as
577 * the first output.
578 */
579 if (blend->mrt0_is_dual_src)
580 col_format |= (col_format & 0xf) << 4;
581
582 blend->cb_shader_mask = ac_get_cb_shader_mask(col_format);
583 blend->spi_shader_col_format = col_format;
584 }
585
586 static bool
587 format_is_int8(VkFormat format)
588 {
589 const struct vk_format_description *desc = vk_format_description(format);
590 int channel = vk_format_get_first_non_void_channel(format);
591
592 return channel >= 0 && desc->channel[channel].pure_integer &&
593 desc->channel[channel].size == 8;
594 }
595
596 static bool
597 format_is_int10(VkFormat format)
598 {
599 const struct vk_format_description *desc = vk_format_description(format);
600
601 if (desc->nr_channels != 4)
602 return false;
603 for (unsigned i = 0; i < 4; i++) {
604 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
605 return true;
606 }
607 return false;
608 }
609
610 /*
611 * Ordered so that for each i,
612 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
613 */
614 const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS] = {
615 VK_FORMAT_R32_SFLOAT,
616 VK_FORMAT_R32G32_SFLOAT,
617 VK_FORMAT_R8G8B8A8_UNORM,
618 VK_FORMAT_R16G16B16A16_UNORM,
619 VK_FORMAT_R16G16B16A16_SNORM,
620 VK_FORMAT_R16G16B16A16_UINT,
621 VK_FORMAT_R16G16B16A16_SINT,
622 VK_FORMAT_R32G32B32A32_SFLOAT,
623 VK_FORMAT_R8G8B8A8_UINT,
624 VK_FORMAT_R8G8B8A8_SINT,
625 VK_FORMAT_A2R10G10B10_UINT_PACK32,
626 VK_FORMAT_A2R10G10B10_SINT_PACK32,
627 };
628
629 unsigned radv_format_meta_fs_key(VkFormat format)
630 {
631 unsigned col_format = si_choose_spi_color_format(format, false, false);
632
633 assert(col_format != V_028714_SPI_SHADER_32_AR);
634 if (col_format >= V_028714_SPI_SHADER_32_AR)
635 --col_format; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
636
637 --col_format; /* Skip V_028714_SPI_SHADER_ZERO */
638 bool is_int8 = format_is_int8(format);
639 bool is_int10 = format_is_int10(format);
640
641 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
642 }
643
644 static void
645 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo *pCreateInfo,
646 unsigned *is_int8, unsigned *is_int10)
647 {
648 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
649 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
650 *is_int8 = 0;
651 *is_int10 = 0;
652
653 for (unsigned i = 0; i < subpass->color_count; ++i) {
654 struct radv_render_pass_attachment *attachment;
655
656 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
657 continue;
658
659 attachment = pass->attachments + subpass->color_attachments[i].attachment;
660
661 if (format_is_int8(attachment->format))
662 *is_int8 |= 1 << i;
663 if (format_is_int10(attachment->format))
664 *is_int10 |= 1 << i;
665 }
666 }
667
668 static void
669 radv_blend_check_commutativity(struct radv_blend_state *blend,
670 VkBlendOp op, VkBlendFactor src,
671 VkBlendFactor dst, unsigned chanmask)
672 {
673 /* Src factor is allowed when it does not depend on Dst. */
674 static const uint32_t src_allowed =
675 (1u << VK_BLEND_FACTOR_ONE) |
676 (1u << VK_BLEND_FACTOR_SRC_COLOR) |
677 (1u << VK_BLEND_FACTOR_SRC_ALPHA) |
678 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE) |
679 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR) |
680 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA) |
681 (1u << VK_BLEND_FACTOR_SRC1_COLOR) |
682 (1u << VK_BLEND_FACTOR_SRC1_ALPHA) |
683 (1u << VK_BLEND_FACTOR_ZERO) |
684 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR) |
685 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA) |
686 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR) |
687 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA) |
688 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR) |
689 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA);
690
691 if (dst == VK_BLEND_FACTOR_ONE &&
692 (src_allowed & (1u << src))) {
693 /* Addition is commutative, but floating point addition isn't
694 * associative: subtle changes can be introduced via different
695 * rounding. Be conservative, only enable for min and max.
696 */
697 if (op == VK_BLEND_OP_MAX || op == VK_BLEND_OP_MIN)
698 blend->commutative_4bit |= chanmask;
699 }
700 }
701
702 static struct radv_blend_state
703 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
704 const VkGraphicsPipelineCreateInfo *pCreateInfo,
705 const struct radv_graphics_pipeline_create_info *extra)
706 {
707 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
708 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
709 struct radv_blend_state blend = {0};
710 unsigned mode = V_028808_CB_NORMAL;
711 int i;
712
713 if (!vkblend)
714 return blend;
715
716 if (extra && extra->custom_blend_mode) {
717 blend.single_cb_enable = true;
718 mode = extra->custom_blend_mode;
719 }
720 blend.cb_color_control = 0;
721 if (vkblend->logicOpEnable)
722 blend.cb_color_control |= S_028808_ROP3(si_translate_blend_logic_op(vkblend->logicOp));
723 else
724 blend.cb_color_control |= S_028808_ROP3(V_028808_ROP3_COPY);
725
726 blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
727 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
728 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
729 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
730 S_028B70_OFFSET_ROUND(1);
731
732 if (vkms && vkms->alphaToCoverageEnable) {
733 blend.db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
734 blend.need_src_alpha |= 0x1;
735 }
736
737 blend.cb_target_mask = 0;
738 for (i = 0; i < vkblend->attachmentCount; i++) {
739 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
740 unsigned blend_cntl = 0;
741 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
742 VkBlendOp eqRGB = att->colorBlendOp;
743 VkBlendFactor srcRGB = att->srcColorBlendFactor;
744 VkBlendFactor dstRGB = att->dstColorBlendFactor;
745 VkBlendOp eqA = att->alphaBlendOp;
746 VkBlendFactor srcA = att->srcAlphaBlendFactor;
747 VkBlendFactor dstA = att->dstAlphaBlendFactor;
748
749 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
750
751 if (!att->colorWriteMask)
752 continue;
753
754 blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
755 blend.cb_target_enabled_4bit |= 0xf << (4 * i);
756 if (!att->blendEnable) {
757 blend.cb_blend_control[i] = blend_cntl;
758 continue;
759 }
760
761 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
762 if (i == 0)
763 blend.mrt0_is_dual_src = true;
764
765 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
766 srcRGB = VK_BLEND_FACTOR_ONE;
767 dstRGB = VK_BLEND_FACTOR_ONE;
768 }
769 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
770 srcA = VK_BLEND_FACTOR_ONE;
771 dstA = VK_BLEND_FACTOR_ONE;
772 }
773
774 radv_blend_check_commutativity(&blend, eqRGB, srcRGB, dstRGB,
775 0x7 << (4 * i));
776 radv_blend_check_commutativity(&blend, eqA, srcA, dstA,
777 0x8 << (4 * i));
778
779 /* Blending optimizations for RB+.
780 * These transformations don't change the behavior.
781 *
782 * First, get rid of DST in the blend factors:
783 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
784 */
785 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
786 VK_BLEND_FACTOR_DST_COLOR,
787 VK_BLEND_FACTOR_SRC_COLOR);
788
789 si_blend_remove_dst(&eqA, &srcA, &dstA,
790 VK_BLEND_FACTOR_DST_COLOR,
791 VK_BLEND_FACTOR_SRC_COLOR);
792
793 si_blend_remove_dst(&eqA, &srcA, &dstA,
794 VK_BLEND_FACTOR_DST_ALPHA,
795 VK_BLEND_FACTOR_SRC_ALPHA);
796
797 /* Look up the ideal settings from tables. */
798 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
799 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
800 srcA_opt = si_translate_blend_opt_factor(srcA, true);
801 dstA_opt = si_translate_blend_opt_factor(dstA, true);
802
803 /* Handle interdependencies. */
804 if (si_blend_factor_uses_dst(srcRGB))
805 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
806 if (si_blend_factor_uses_dst(srcA))
807 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
808
809 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
810 (dstRGB == VK_BLEND_FACTOR_ZERO ||
811 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
812 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
813 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
814
815 /* Set the final value. */
816 blend.sx_mrt_blend_opt[i] =
817 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
818 S_028760_COLOR_DST_OPT(dstRGB_opt) |
819 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
820 S_028760_ALPHA_SRC_OPT(srcA_opt) |
821 S_028760_ALPHA_DST_OPT(dstA_opt) |
822 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
823 blend_cntl |= S_028780_ENABLE(1);
824
825 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
826 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
827 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
828 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
829 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
830 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
831 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
832 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
833 }
834 blend.cb_blend_control[i] = blend_cntl;
835
836 blend.blend_enable_4bit |= 0xfu << (i * 4);
837
838 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
839 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
840 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
841 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
842 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
843 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
844 blend.need_src_alpha |= 1 << i;
845 }
846 for (i = vkblend->attachmentCount; i < 8; i++) {
847 blend.cb_blend_control[i] = 0;
848 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
849 }
850
851 if (pipeline->device->physical_device->rad_info.has_rbplus) {
852 /* Disable RB+ blend optimizations for dual source blending. */
853 if (blend.mrt0_is_dual_src) {
854 for (i = 0; i < 8; i++) {
855 blend.sx_mrt_blend_opt[i] =
856 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
857 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
858 }
859 }
860
861 /* RB+ doesn't work with dual source blending, logic op and
862 * RESOLVE.
863 */
864 if (blend.mrt0_is_dual_src || vkblend->logicOpEnable ||
865 mode == V_028808_CB_RESOLVE)
866 blend.cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
867 }
868
869 if (blend.cb_target_mask)
870 blend.cb_color_control |= S_028808_MODE(mode);
871 else
872 blend.cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
873
874 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo, &blend);
875 return blend;
876 }
877
878 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
879 {
880 switch (op) {
881 case VK_STENCIL_OP_KEEP:
882 return V_02842C_STENCIL_KEEP;
883 case VK_STENCIL_OP_ZERO:
884 return V_02842C_STENCIL_ZERO;
885 case VK_STENCIL_OP_REPLACE:
886 return V_02842C_STENCIL_REPLACE_TEST;
887 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
888 return V_02842C_STENCIL_ADD_CLAMP;
889 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
890 return V_02842C_STENCIL_SUB_CLAMP;
891 case VK_STENCIL_OP_INVERT:
892 return V_02842C_STENCIL_INVERT;
893 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
894 return V_02842C_STENCIL_ADD_WRAP;
895 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
896 return V_02842C_STENCIL_SUB_WRAP;
897 default:
898 return 0;
899 }
900 }
901
902 static uint32_t si_translate_fill(VkPolygonMode func)
903 {
904 switch(func) {
905 case VK_POLYGON_MODE_FILL:
906 return V_028814_X_DRAW_TRIANGLES;
907 case VK_POLYGON_MODE_LINE:
908 return V_028814_X_DRAW_LINES;
909 case VK_POLYGON_MODE_POINT:
910 return V_028814_X_DRAW_POINTS;
911 default:
912 assert(0);
913 return V_028814_X_DRAW_POINTS;
914 }
915 }
916
917 static uint8_t radv_pipeline_get_ps_iter_samples(const VkPipelineMultisampleStateCreateInfo *vkms)
918 {
919 uint32_t num_samples = vkms->rasterizationSamples;
920 uint32_t ps_iter_samples = 1;
921
922 if (vkms->sampleShadingEnable) {
923 ps_iter_samples = ceil(vkms->minSampleShading * num_samples);
924 ps_iter_samples = util_next_power_of_two(ps_iter_samples);
925 }
926 return ps_iter_samples;
927 }
928
929 static bool
930 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
931 {
932 return pCreateInfo->depthTestEnable &&
933 pCreateInfo->depthWriteEnable &&
934 pCreateInfo->depthCompareOp != VK_COMPARE_OP_NEVER;
935 }
936
937 static bool
938 radv_writes_stencil(const VkStencilOpState *state)
939 {
940 return state->writeMask &&
941 (state->failOp != VK_STENCIL_OP_KEEP ||
942 state->passOp != VK_STENCIL_OP_KEEP ||
943 state->depthFailOp != VK_STENCIL_OP_KEEP);
944 }
945
946 static bool
947 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
948 {
949 return pCreateInfo->stencilTestEnable &&
950 (radv_writes_stencil(&pCreateInfo->front) ||
951 radv_writes_stencil(&pCreateInfo->back));
952 }
953
954 static bool
955 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
956 {
957 return radv_is_depth_write_enabled(pCreateInfo) ||
958 radv_is_stencil_write_enabled(pCreateInfo);
959 }
960
961 static bool
962 radv_order_invariant_stencil_op(VkStencilOp op)
963 {
964 /* REPLACE is normally order invariant, except when the stencil
965 * reference value is written by the fragment shader. Tracking this
966 * interaction does not seem worth the effort, so be conservative.
967 */
968 return op != VK_STENCIL_OP_INCREMENT_AND_CLAMP &&
969 op != VK_STENCIL_OP_DECREMENT_AND_CLAMP &&
970 op != VK_STENCIL_OP_REPLACE;
971 }
972
973 static bool
974 radv_order_invariant_stencil_state(const VkStencilOpState *state)
975 {
976 /* Compute whether, assuming Z writes are disabled, this stencil state
977 * is order invariant in the sense that the set of passing fragments as
978 * well as the final stencil buffer result does not depend on the order
979 * of fragments.
980 */
981 return !state->writeMask ||
982 /* The following assumes that Z writes are disabled. */
983 (state->compareOp == VK_COMPARE_OP_ALWAYS &&
984 radv_order_invariant_stencil_op(state->passOp) &&
985 radv_order_invariant_stencil_op(state->depthFailOp)) ||
986 (state->compareOp == VK_COMPARE_OP_NEVER &&
987 radv_order_invariant_stencil_op(state->failOp));
988 }
989
990 static bool
991 radv_pipeline_out_of_order_rast(struct radv_pipeline *pipeline,
992 struct radv_blend_state *blend,
993 const VkGraphicsPipelineCreateInfo *pCreateInfo)
994 {
995 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
996 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
997 unsigned colormask = blend->cb_target_enabled_4bit;
998
999 if (!pipeline->device->physical_device->out_of_order_rast_allowed)
1000 return false;
1001
1002 /* Be conservative if a logic operation is enabled with color buffers. */
1003 if (colormask && pCreateInfo->pColorBlendState->logicOpEnable)
1004 return false;
1005
1006 /* Default depth/stencil invariance when no attachment is bound. */
1007 struct radv_dsa_order_invariance dsa_order_invariant = {
1008 .zs = true, .pass_set = true
1009 };
1010
1011 if (pCreateInfo->pDepthStencilState &&
1012 subpass->depth_stencil_attachment) {
1013 const VkPipelineDepthStencilStateCreateInfo *vkds =
1014 pCreateInfo->pDepthStencilState;
1015 struct radv_render_pass_attachment *attachment =
1016 pass->attachments + subpass->depth_stencil_attachment->attachment;
1017 bool has_stencil = vk_format_is_stencil(attachment->format);
1018 struct radv_dsa_order_invariance order_invariance[2];
1019 struct radv_shader_variant *ps =
1020 pipeline->shaders[MESA_SHADER_FRAGMENT];
1021
1022 /* Compute depth/stencil order invariance in order to know if
1023 * it's safe to enable out-of-order.
1024 */
1025 bool zfunc_is_ordered =
1026 vkds->depthCompareOp == VK_COMPARE_OP_NEVER ||
1027 vkds->depthCompareOp == VK_COMPARE_OP_LESS ||
1028 vkds->depthCompareOp == VK_COMPARE_OP_LESS_OR_EQUAL ||
1029 vkds->depthCompareOp == VK_COMPARE_OP_GREATER ||
1030 vkds->depthCompareOp == VK_COMPARE_OP_GREATER_OR_EQUAL;
1031
1032 bool nozwrite_and_order_invariant_stencil =
1033 !radv_is_ds_write_enabled(vkds) ||
1034 (!radv_is_depth_write_enabled(vkds) &&
1035 radv_order_invariant_stencil_state(&vkds->front) &&
1036 radv_order_invariant_stencil_state(&vkds->back));
1037
1038 order_invariance[1].zs =
1039 nozwrite_and_order_invariant_stencil ||
1040 (!radv_is_stencil_write_enabled(vkds) &&
1041 zfunc_is_ordered);
1042 order_invariance[0].zs =
1043 !radv_is_depth_write_enabled(vkds) || zfunc_is_ordered;
1044
1045 order_invariance[1].pass_set =
1046 nozwrite_and_order_invariant_stencil ||
1047 (!radv_is_stencil_write_enabled(vkds) &&
1048 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1049 vkds->depthCompareOp == VK_COMPARE_OP_NEVER));
1050 order_invariance[0].pass_set =
1051 !radv_is_depth_write_enabled(vkds) ||
1052 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1053 vkds->depthCompareOp == VK_COMPARE_OP_NEVER);
1054
1055 dsa_order_invariant = order_invariance[has_stencil];
1056 if (!dsa_order_invariant.zs)
1057 return false;
1058
1059 /* The set of PS invocations is always order invariant,
1060 * except when early Z/S tests are requested.
1061 */
1062 if (ps &&
1063 ps->info.ps.writes_memory &&
1064 ps->info.ps.early_fragment_test &&
1065 !dsa_order_invariant.pass_set)
1066 return false;
1067
1068 /* Determine if out-of-order rasterization should be disabled
1069 * when occlusion queries are used.
1070 */
1071 pipeline->graphics.disable_out_of_order_rast_for_occlusion =
1072 !dsa_order_invariant.pass_set;
1073 }
1074
1075 /* No color buffers are enabled for writing. */
1076 if (!colormask)
1077 return true;
1078
1079 unsigned blendmask = colormask & blend->blend_enable_4bit;
1080
1081 if (blendmask) {
1082 /* Only commutative blending. */
1083 if (blendmask & ~blend->commutative_4bit)
1084 return false;
1085
1086 if (!dsa_order_invariant.pass_set)
1087 return false;
1088 }
1089
1090 if (colormask & ~blendmask)
1091 return false;
1092
1093 return true;
1094 }
1095
1096 static void
1097 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1098 struct radv_blend_state *blend,
1099 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1100 {
1101 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
1102 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1103 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1104 bool out_of_order_rast = false;
1105 int ps_iter_samples = 1;
1106 uint32_t mask = 0xffff;
1107
1108 if (vkms)
1109 ms->num_samples = vkms->rasterizationSamples;
1110 else
1111 ms->num_samples = 1;
1112
1113 if (vkms)
1114 ps_iter_samples = radv_pipeline_get_ps_iter_samples(vkms);
1115 if (vkms && !vkms->sampleShadingEnable && pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.force_persample) {
1116 ps_iter_samples = ms->num_samples;
1117 }
1118
1119 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
1120 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
1121 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
1122 /* Out-of-order rasterization is explicitly enabled by the
1123 * application.
1124 */
1125 out_of_order_rast = true;
1126 } else {
1127 /* Determine if the driver can enable out-of-order
1128 * rasterization internally.
1129 */
1130 out_of_order_rast =
1131 radv_pipeline_out_of_order_rast(pipeline, blend, pCreateInfo);
1132 }
1133
1134 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1135 ms->pa_sc_aa_config = 0;
1136 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1137 S_028804_INCOHERENT_EQAA_READS(1) |
1138 S_028804_INTERPOLATE_COMP_Z(1) |
1139 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1140 ms->pa_sc_mode_cntl_1 =
1141 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1142 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1143 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
1144 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1145 /* always 1: */
1146 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1147 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1148 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1149 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1150 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1151 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1152 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9) |
1153 S_028A48_VPORT_SCISSOR_ENABLE(1);
1154
1155 if (ms->num_samples > 1) {
1156 unsigned log_samples = util_logbase2(ms->num_samples);
1157 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
1158 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
1159 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1160 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1161 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1162 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1163 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1164 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1165 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples)) |
1166 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1167 ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1168 if (ps_iter_samples > 1)
1169 pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1170 }
1171
1172 if (vkms && vkms->pSampleMask) {
1173 mask = vkms->pSampleMask[0] & 0xffff;
1174 }
1175
1176 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1177 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1178 }
1179
1180 static bool
1181 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1182 {
1183 switch (topology) {
1184 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1185 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1186 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1187 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1188 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1189 return false;
1190 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1191 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1192 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1193 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1194 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1195 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1196 return true;
1197 default:
1198 unreachable("unhandled primitive type");
1199 }
1200 }
1201
1202 static uint32_t
1203 si_translate_prim(enum VkPrimitiveTopology topology)
1204 {
1205 switch (topology) {
1206 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1207 return V_008958_DI_PT_POINTLIST;
1208 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1209 return V_008958_DI_PT_LINELIST;
1210 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1211 return V_008958_DI_PT_LINESTRIP;
1212 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1213 return V_008958_DI_PT_TRILIST;
1214 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1215 return V_008958_DI_PT_TRISTRIP;
1216 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1217 return V_008958_DI_PT_TRIFAN;
1218 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1219 return V_008958_DI_PT_LINELIST_ADJ;
1220 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1221 return V_008958_DI_PT_LINESTRIP_ADJ;
1222 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1223 return V_008958_DI_PT_TRILIST_ADJ;
1224 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1225 return V_008958_DI_PT_TRISTRIP_ADJ;
1226 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1227 return V_008958_DI_PT_PATCH;
1228 default:
1229 assert(0);
1230 return 0;
1231 }
1232 }
1233
1234 static uint32_t
1235 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1236 {
1237 switch (gl_prim) {
1238 case 0: /* GL_POINTS */
1239 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1240 case 1: /* GL_LINES */
1241 case 3: /* GL_LINE_STRIP */
1242 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1243 case 0x8E7A: /* GL_ISOLINES */
1244 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1245
1246 case 4: /* GL_TRIANGLES */
1247 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1248 case 5: /* GL_TRIANGLE_STRIP */
1249 case 7: /* GL_QUADS */
1250 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1251 default:
1252 assert(0);
1253 return 0;
1254 }
1255 }
1256
1257 static uint32_t
1258 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1259 {
1260 switch (topology) {
1261 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1262 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1263 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1264 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1265 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1266 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1267 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1268 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1269 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1270 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1271 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1272 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1273 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1274 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1275 default:
1276 assert(0);
1277 return 0;
1278 }
1279 }
1280
1281 static unsigned radv_dynamic_state_mask(VkDynamicState state)
1282 {
1283 switch(state) {
1284 case VK_DYNAMIC_STATE_VIEWPORT:
1285 return RADV_DYNAMIC_VIEWPORT;
1286 case VK_DYNAMIC_STATE_SCISSOR:
1287 return RADV_DYNAMIC_SCISSOR;
1288 case VK_DYNAMIC_STATE_LINE_WIDTH:
1289 return RADV_DYNAMIC_LINE_WIDTH;
1290 case VK_DYNAMIC_STATE_DEPTH_BIAS:
1291 return RADV_DYNAMIC_DEPTH_BIAS;
1292 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
1293 return RADV_DYNAMIC_BLEND_CONSTANTS;
1294 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
1295 return RADV_DYNAMIC_DEPTH_BOUNDS;
1296 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
1297 return RADV_DYNAMIC_STENCIL_COMPARE_MASK;
1298 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
1299 return RADV_DYNAMIC_STENCIL_WRITE_MASK;
1300 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
1301 return RADV_DYNAMIC_STENCIL_REFERENCE;
1302 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT:
1303 return RADV_DYNAMIC_DISCARD_RECTANGLE;
1304 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT:
1305 return RADV_DYNAMIC_SAMPLE_LOCATIONS;
1306 default:
1307 unreachable("Unhandled dynamic state");
1308 }
1309 }
1310
1311 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
1312 {
1313 uint32_t states = RADV_DYNAMIC_ALL;
1314
1315 /* If rasterization is disabled we do not care about any of the dynamic states,
1316 * since they are all rasterization related only. */
1317 if (pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
1318 return 0;
1319
1320 if (!pCreateInfo->pRasterizationState->depthBiasEnable)
1321 states &= ~RADV_DYNAMIC_DEPTH_BIAS;
1322
1323 if (!pCreateInfo->pDepthStencilState ||
1324 !pCreateInfo->pDepthStencilState->depthBoundsTestEnable)
1325 states &= ~RADV_DYNAMIC_DEPTH_BOUNDS;
1326
1327 if (!pCreateInfo->pDepthStencilState ||
1328 !pCreateInfo->pDepthStencilState->stencilTestEnable)
1329 states &= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK |
1330 RADV_DYNAMIC_STENCIL_WRITE_MASK |
1331 RADV_DYNAMIC_STENCIL_REFERENCE);
1332
1333 if (!vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT))
1334 states &= ~RADV_DYNAMIC_DISCARD_RECTANGLE;
1335
1336 if (!pCreateInfo->pMultisampleState ||
1337 !vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1338 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT))
1339 states &= ~RADV_DYNAMIC_SAMPLE_LOCATIONS;
1340
1341 /* TODO: blend constants & line width. */
1342
1343 return states;
1344 }
1345
1346
1347 static void
1348 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1349 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1350 {
1351 uint32_t needed_states = radv_pipeline_needed_dynamic_state(pCreateInfo);
1352 uint32_t states = needed_states;
1353 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1354 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1355
1356 pipeline->dynamic_state = default_dynamic_state;
1357 pipeline->graphics.needed_dynamic_state = needed_states;
1358
1359 if (pCreateInfo->pDynamicState) {
1360 /* Remove all of the states that are marked as dynamic */
1361 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1362 for (uint32_t s = 0; s < count; s++)
1363 states &= ~radv_dynamic_state_mask(pCreateInfo->pDynamicState->pDynamicStates[s]);
1364 }
1365
1366 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1367
1368 if (needed_states & RADV_DYNAMIC_VIEWPORT) {
1369 assert(pCreateInfo->pViewportState);
1370
1371 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1372 if (states & RADV_DYNAMIC_VIEWPORT) {
1373 typed_memcpy(dynamic->viewport.viewports,
1374 pCreateInfo->pViewportState->pViewports,
1375 pCreateInfo->pViewportState->viewportCount);
1376 }
1377 }
1378
1379 if (needed_states & RADV_DYNAMIC_SCISSOR) {
1380 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1381 if (states & RADV_DYNAMIC_SCISSOR) {
1382 typed_memcpy(dynamic->scissor.scissors,
1383 pCreateInfo->pViewportState->pScissors,
1384 pCreateInfo->pViewportState->scissorCount);
1385 }
1386 }
1387
1388 if (states & RADV_DYNAMIC_LINE_WIDTH) {
1389 assert(pCreateInfo->pRasterizationState);
1390 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1391 }
1392
1393 if (states & RADV_DYNAMIC_DEPTH_BIAS) {
1394 assert(pCreateInfo->pRasterizationState);
1395 dynamic->depth_bias.bias =
1396 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1397 dynamic->depth_bias.clamp =
1398 pCreateInfo->pRasterizationState->depthBiasClamp;
1399 dynamic->depth_bias.slope =
1400 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1401 }
1402
1403 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1404 *
1405 * pColorBlendState is [...] NULL if the pipeline has rasterization
1406 * disabled or if the subpass of the render pass the pipeline is
1407 * created against does not use any color attachments.
1408 */
1409 if (subpass->has_color_att && states & RADV_DYNAMIC_BLEND_CONSTANTS) {
1410 assert(pCreateInfo->pColorBlendState);
1411 typed_memcpy(dynamic->blend_constants,
1412 pCreateInfo->pColorBlendState->blendConstants, 4);
1413 }
1414
1415 /* If there is no depthstencil attachment, then don't read
1416 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1417 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1418 * no need to override the depthstencil defaults in
1419 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1420 *
1421 * Section 9.2 of the Vulkan 1.0.15 spec says:
1422 *
1423 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1424 * disabled or if the subpass of the render pass the pipeline is created
1425 * against does not use a depth/stencil attachment.
1426 */
1427 if (needed_states && subpass->depth_stencil_attachment) {
1428 assert(pCreateInfo->pDepthStencilState);
1429
1430 if (states & RADV_DYNAMIC_DEPTH_BOUNDS) {
1431 dynamic->depth_bounds.min =
1432 pCreateInfo->pDepthStencilState->minDepthBounds;
1433 dynamic->depth_bounds.max =
1434 pCreateInfo->pDepthStencilState->maxDepthBounds;
1435 }
1436
1437 if (states & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
1438 dynamic->stencil_compare_mask.front =
1439 pCreateInfo->pDepthStencilState->front.compareMask;
1440 dynamic->stencil_compare_mask.back =
1441 pCreateInfo->pDepthStencilState->back.compareMask;
1442 }
1443
1444 if (states & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
1445 dynamic->stencil_write_mask.front =
1446 pCreateInfo->pDepthStencilState->front.writeMask;
1447 dynamic->stencil_write_mask.back =
1448 pCreateInfo->pDepthStencilState->back.writeMask;
1449 }
1450
1451 if (states & RADV_DYNAMIC_STENCIL_REFERENCE) {
1452 dynamic->stencil_reference.front =
1453 pCreateInfo->pDepthStencilState->front.reference;
1454 dynamic->stencil_reference.back =
1455 pCreateInfo->pDepthStencilState->back.reference;
1456 }
1457 }
1458
1459 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
1460 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
1461 if (needed_states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1462 dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount;
1463 if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1464 typed_memcpy(dynamic->discard_rectangle.rectangles,
1465 discard_rectangle_info->pDiscardRectangles,
1466 discard_rectangle_info->discardRectangleCount);
1467 }
1468 }
1469
1470 if (needed_states & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
1471 const VkPipelineSampleLocationsStateCreateInfoEXT *sample_location_info =
1472 vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1473 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
1474 /* If sampleLocationsEnable is VK_FALSE, the default sample
1475 * locations are used and the values specified in
1476 * sampleLocationsInfo are ignored.
1477 */
1478 if (sample_location_info->sampleLocationsEnable) {
1479 const VkSampleLocationsInfoEXT *pSampleLocationsInfo =
1480 &sample_location_info->sampleLocationsInfo;
1481
1482 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
1483
1484 dynamic->sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
1485 dynamic->sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
1486 dynamic->sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
1487 typed_memcpy(&dynamic->sample_location.locations[0],
1488 pSampleLocationsInfo->pSampleLocations,
1489 pSampleLocationsInfo->sampleLocationsCount);
1490 }
1491 }
1492
1493 pipeline->dynamic_state.mask = states;
1494 }
1495
1496 static void
1497 gfx9_get_gs_info(const VkGraphicsPipelineCreateInfo *pCreateInfo,
1498 const struct radv_pipeline *pipeline,
1499 nir_shader **nir,
1500 struct radv_shader_info *infos,
1501 struct gfx9_gs_info *out)
1502 {
1503 struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY];
1504 struct radv_es_output_info *es_info;
1505 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
1506 es_info = nir[MESA_SHADER_TESS_CTRL] ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1507 else
1508 es_info = nir[MESA_SHADER_TESS_CTRL] ?
1509 &infos[MESA_SHADER_TESS_EVAL].tes.es_info :
1510 &infos[MESA_SHADER_VERTEX].vs.es_info;
1511
1512 unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
1513 bool uses_adjacency;
1514 switch(pCreateInfo->pInputAssemblyState->topology) {
1515 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1516 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1517 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1518 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1519 uses_adjacency = true;
1520 break;
1521 default:
1522 uses_adjacency = false;
1523 break;
1524 }
1525
1526 /* All these are in dwords: */
1527 /* We can't allow using the whole LDS, because GS waves compete with
1528 * other shader stages for LDS space. */
1529 const unsigned max_lds_size = 8 * 1024;
1530 const unsigned esgs_itemsize = es_info->esgs_itemsize / 4;
1531 unsigned esgs_lds_size;
1532
1533 /* All these are per subgroup: */
1534 const unsigned max_out_prims = 32 * 1024;
1535 const unsigned max_es_verts = 255;
1536 const unsigned ideal_gs_prims = 64;
1537 unsigned max_gs_prims, gs_prims;
1538 unsigned min_es_verts, es_verts, worst_case_es_verts;
1539
1540 if (uses_adjacency || gs_num_invocations > 1)
1541 max_gs_prims = 127 / gs_num_invocations;
1542 else
1543 max_gs_prims = 255;
1544
1545 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1546 * Make sure we don't go over the maximum value.
1547 */
1548 if (gs_info->gs.vertices_out > 0) {
1549 max_gs_prims = MIN2(max_gs_prims,
1550 max_out_prims /
1551 (gs_info->gs.vertices_out * gs_num_invocations));
1552 }
1553 assert(max_gs_prims > 0);
1554
1555 /* If the primitive has adjacency, halve the number of vertices
1556 * that will be reused in multiple primitives.
1557 */
1558 min_es_verts = gs_info->gs.vertices_in / (uses_adjacency ? 2 : 1);
1559
1560 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
1561 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
1562
1563 /* Compute ESGS LDS size based on the worst case number of ES vertices
1564 * needed to create the target number of GS prims per subgroup.
1565 */
1566 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1567
1568 /* If total LDS usage is too big, refactor partitions based on ratio
1569 * of ESGS item sizes.
1570 */
1571 if (esgs_lds_size > max_lds_size) {
1572 /* Our target GS Prims Per Subgroup was too large. Calculate
1573 * the maximum number of GS Prims Per Subgroup that will fit
1574 * into LDS, capped by the maximum that the hardware can support.
1575 */
1576 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
1577 max_gs_prims);
1578 assert(gs_prims > 0);
1579 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
1580 max_es_verts);
1581
1582 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1583 assert(esgs_lds_size <= max_lds_size);
1584 }
1585
1586 /* Now calculate remaining ESGS information. */
1587 if (esgs_lds_size)
1588 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
1589 else
1590 es_verts = max_es_verts;
1591
1592 /* Vertices for adjacency primitives are not always reused, so restore
1593 * it for ES_VERTS_PER_SUBGRP.
1594 */
1595 min_es_verts = gs_info->gs.vertices_in;
1596
1597 /* For normal primitives, the VGT only checks if they are past the ES
1598 * verts per subgroup after allocating a full GS primitive and if they
1599 * are, kick off a new subgroup. But if those additional ES verts are
1600 * unique (e.g. not reused) we need to make sure there is enough LDS
1601 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1602 */
1603 es_verts -= min_es_verts - 1;
1604
1605 uint32_t es_verts_per_subgroup = es_verts;
1606 uint32_t gs_prims_per_subgroup = gs_prims;
1607 uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
1608 uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out;
1609 out->lds_size = align(esgs_lds_size, 128) / 128;
1610 out->vgt_gs_onchip_cntl = S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) |
1611 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) |
1612 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup);
1613 out->vgt_gs_max_prims_per_subgroup = S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup);
1614 out->vgt_esgs_ring_itemsize = esgs_itemsize;
1615 assert(max_prims_per_subgroup <= max_out_prims);
1616 }
1617
1618 static void clamp_gsprims_to_esverts(unsigned *max_gsprims, unsigned max_esverts,
1619 unsigned min_verts_per_prim, bool use_adjacency)
1620 {
1621 unsigned max_reuse = max_esverts - min_verts_per_prim;
1622 if (use_adjacency)
1623 max_reuse /= 2;
1624 *max_gsprims = MIN2(*max_gsprims, 1 + max_reuse);
1625 }
1626
1627 static unsigned
1628 radv_get_num_input_vertices(nir_shader **nir)
1629 {
1630 if (nir[MESA_SHADER_GEOMETRY]) {
1631 nir_shader *gs = nir[MESA_SHADER_GEOMETRY];
1632
1633 return gs->info.gs.vertices_in;
1634 }
1635
1636 if (nir[MESA_SHADER_TESS_CTRL]) {
1637 nir_shader *tes = nir[MESA_SHADER_TESS_EVAL];
1638
1639 if (tes->info.tess.point_mode)
1640 return 1;
1641 if (tes->info.tess.primitive_mode == GL_ISOLINES)
1642 return 2;
1643 return 3;
1644 }
1645
1646 return 3;
1647 }
1648
1649 static void
1650 gfx10_get_ngg_info(const VkGraphicsPipelineCreateInfo *pCreateInfo,
1651 struct radv_pipeline *pipeline,
1652 nir_shader **nir,
1653 struct radv_shader_info *infos,
1654 struct gfx10_ngg_info *ngg)
1655 {
1656 struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY];
1657 struct radv_es_output_info *es_info =
1658 nir[MESA_SHADER_TESS_CTRL] ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1659 unsigned gs_type = nir[MESA_SHADER_GEOMETRY] ? MESA_SHADER_GEOMETRY : MESA_SHADER_VERTEX;
1660 unsigned max_verts_per_prim = radv_get_num_input_vertices(nir);
1661 unsigned min_verts_per_prim =
1662 gs_type == MESA_SHADER_GEOMETRY ? max_verts_per_prim : 1;
1663 unsigned gs_num_invocations = nir[MESA_SHADER_GEOMETRY] ? MAX2(gs_info->gs.invocations, 1) : 1;
1664 bool uses_adjacency;
1665 switch(pCreateInfo->pInputAssemblyState->topology) {
1666 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1667 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1668 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1669 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1670 uses_adjacency = true;
1671 break;
1672 default:
1673 uses_adjacency = false;
1674 break;
1675 }
1676
1677 /* All these are in dwords: */
1678 /* We can't allow using the whole LDS, because GS waves compete with
1679 * other shader stages for LDS space.
1680 *
1681 * TODO: We should really take the shader's internal LDS use into
1682 * account. The linker will fail if the size is greater than
1683 * 8K dwords.
1684 */
1685 const unsigned max_lds_size = 8 * 1024 - 768;
1686 const unsigned target_lds_size = max_lds_size;
1687 unsigned esvert_lds_size = 0;
1688 unsigned gsprim_lds_size = 0;
1689
1690 /* All these are per subgroup: */
1691 bool max_vert_out_per_gs_instance = false;
1692 unsigned max_esverts_base = 256;
1693 unsigned max_gsprims_base = 128; /* default prim group size clamp */
1694
1695 /* Hardware has the following non-natural restrictions on the value
1696 * of GE_CNTL.VERT_GRP_SIZE based on based on the primitive type of
1697 * the draw:
1698 * - at most 252 for any line input primitive type
1699 * - at most 251 for any quad input primitive type
1700 * - at most 251 for triangle strips with adjacency (this happens to
1701 * be the natural limit for triangle *lists* with adjacency)
1702 */
1703 max_esverts_base = MIN2(max_esverts_base, 251 + max_verts_per_prim - 1);
1704
1705 if (gs_type == MESA_SHADER_GEOMETRY) {
1706 unsigned max_out_verts_per_gsprim =
1707 gs_info->gs.vertices_out * gs_num_invocations;
1708
1709 if (max_out_verts_per_gsprim <= 256) {
1710 if (max_out_verts_per_gsprim) {
1711 max_gsprims_base = MIN2(max_gsprims_base,
1712 256 / max_out_verts_per_gsprim);
1713 }
1714 } else {
1715 /* Use special multi-cycling mode in which each GS
1716 * instance gets its own subgroup. Does not work with
1717 * tessellation. */
1718 max_vert_out_per_gs_instance = true;
1719 max_gsprims_base = 1;
1720 max_out_verts_per_gsprim = gs_info->gs.vertices_out;
1721 }
1722
1723 esvert_lds_size = es_info->esgs_itemsize / 4;
1724 gsprim_lds_size = (gs_info->gs.gsvs_vertex_size / 4 + 1) * max_out_verts_per_gsprim;
1725 } else {
1726 /* VS and TES. */
1727 /* LDS size for passing data from GS to ES. */
1728 struct radv_streamout_info *so_info = nir[MESA_SHADER_TESS_CTRL]
1729 ? &infos[MESA_SHADER_TESS_EVAL].so
1730 : &infos[MESA_SHADER_VERTEX].so;
1731
1732 if (so_info->num_outputs)
1733 esvert_lds_size = 4 * so_info->num_outputs + 1;
1734
1735 /* GS stores Primitive IDs (one DWORD) into LDS at the address
1736 * corresponding to the ES thread of the provoking vertex. All
1737 * ES threads load and export PrimitiveID for their thread.
1738 */
1739 if (!nir[MESA_SHADER_TESS_CTRL] &&
1740 infos[MESA_SHADER_VERTEX].vs.outinfo.export_prim_id)
1741 esvert_lds_size = MAX2(esvert_lds_size, 1);
1742 }
1743
1744 unsigned max_gsprims = max_gsprims_base;
1745 unsigned max_esverts = max_esverts_base;
1746
1747 if (esvert_lds_size)
1748 max_esverts = MIN2(max_esverts, target_lds_size / esvert_lds_size);
1749 if (gsprim_lds_size)
1750 max_gsprims = MIN2(max_gsprims, target_lds_size / gsprim_lds_size);
1751
1752 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1753 clamp_gsprims_to_esverts(&max_gsprims, max_esverts, min_verts_per_prim, uses_adjacency);
1754 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1755
1756 if (esvert_lds_size || gsprim_lds_size) {
1757 /* Now that we have a rough proportionality between esverts
1758 * and gsprims based on the primitive type, scale both of them
1759 * down simultaneously based on required LDS space.
1760 *
1761 * We could be smarter about this if we knew how much vertex
1762 * reuse to expect.
1763 */
1764 unsigned lds_total = max_esverts * esvert_lds_size +
1765 max_gsprims * gsprim_lds_size;
1766 if (lds_total > target_lds_size) {
1767 max_esverts = max_esverts * target_lds_size / lds_total;
1768 max_gsprims = max_gsprims * target_lds_size / lds_total;
1769
1770 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1771 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1772 min_verts_per_prim, uses_adjacency);
1773 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1774 }
1775 }
1776
1777 /* Round up towards full wave sizes for better ALU utilization. */
1778 if (!max_vert_out_per_gs_instance) {
1779 const unsigned wavesize = pipeline->device->physical_device->ge_wave_size;
1780 unsigned orig_max_esverts;
1781 unsigned orig_max_gsprims;
1782 do {
1783 orig_max_esverts = max_esverts;
1784 orig_max_gsprims = max_gsprims;
1785
1786 max_esverts = align(max_esverts, wavesize);
1787 max_esverts = MIN2(max_esverts, max_esverts_base);
1788 if (esvert_lds_size)
1789 max_esverts = MIN2(max_esverts,
1790 (max_lds_size - max_gsprims * gsprim_lds_size) /
1791 esvert_lds_size);
1792 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1793
1794 max_gsprims = align(max_gsprims, wavesize);
1795 max_gsprims = MIN2(max_gsprims, max_gsprims_base);
1796 if (gsprim_lds_size)
1797 max_gsprims = MIN2(max_gsprims,
1798 (max_lds_size - max_esverts * esvert_lds_size) /
1799 gsprim_lds_size);
1800 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1801 min_verts_per_prim, uses_adjacency);
1802 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1803 } while (orig_max_esverts != max_esverts || orig_max_gsprims != max_gsprims);
1804 }
1805
1806 /* Hardware restriction: minimum value of max_esverts */
1807 max_esverts = MAX2(max_esverts, 23 + max_verts_per_prim);
1808
1809 unsigned max_out_vertices =
1810 max_vert_out_per_gs_instance ? gs_info->gs.vertices_out :
1811 gs_type == MESA_SHADER_GEOMETRY ?
1812 max_gsprims * gs_num_invocations * gs_info->gs.vertices_out :
1813 max_esverts;
1814 assert(max_out_vertices <= 256);
1815
1816 unsigned prim_amp_factor = 1;
1817 if (gs_type == MESA_SHADER_GEOMETRY) {
1818 /* Number of output primitives per GS input primitive after
1819 * GS instancing. */
1820 prim_amp_factor = gs_info->gs.vertices_out;
1821 }
1822
1823 /* The GE only checks against the maximum number of ES verts after
1824 * allocating a full GS primitive. So we need to ensure that whenever
1825 * this check passes, there is enough space for a full primitive without
1826 * vertex reuse.
1827 */
1828 ngg->hw_max_esverts = max_esverts - max_verts_per_prim + 1;
1829 ngg->max_gsprims = max_gsprims;
1830 ngg->max_out_verts = max_out_vertices;
1831 ngg->prim_amp_factor = prim_amp_factor;
1832 ngg->max_vert_out_per_gs_instance = max_vert_out_per_gs_instance;
1833 ngg->ngg_emit_size = max_gsprims * gsprim_lds_size;
1834 ngg->esgs_ring_size = 4 * max_esverts * esvert_lds_size;
1835
1836 if (gs_type == MESA_SHADER_GEOMETRY) {
1837 ngg->vgt_esgs_ring_itemsize = es_info->esgs_itemsize / 4;
1838 } else {
1839 ngg->vgt_esgs_ring_itemsize = 1;
1840 }
1841
1842 pipeline->graphics.esgs_ring_size = ngg->esgs_ring_size;
1843
1844 assert(ngg->hw_max_esverts >= 24); /* HW limitation */
1845 }
1846
1847 static void
1848 calculate_gs_ring_sizes(struct radv_pipeline *pipeline,
1849 const struct gfx9_gs_info *gs)
1850 {
1851 struct radv_device *device = pipeline->device;
1852 unsigned num_se = device->physical_device->rad_info.max_se;
1853 unsigned wave_size = 64;
1854 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1855 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
1856 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
1857 */
1858 unsigned gs_vertex_reuse =
1859 (device->physical_device->rad_info.chip_class >= GFX8 ? 32 : 16) * num_se;
1860 unsigned alignment = 256 * num_se;
1861 /* The maximum size is 63.999 MB per SE. */
1862 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1863 struct radv_shader_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1864
1865 /* Calculate the minimum size. */
1866 unsigned min_esgs_ring_size = align(gs->vgt_esgs_ring_itemsize * 4 * gs_vertex_reuse *
1867 wave_size, alignment);
1868 /* These are recommended sizes, not minimum sizes. */
1869 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1870 gs->vgt_esgs_ring_itemsize * 4 * gs_info->gs.vertices_in;
1871 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1872 gs_info->gs.max_gsvs_emit_size;
1873
1874 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1875 esgs_ring_size = align(esgs_ring_size, alignment);
1876 gsvs_ring_size = align(gsvs_ring_size, alignment);
1877
1878 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
1879 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1880
1881 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1882 }
1883
1884 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1885 unsigned *lds_size)
1886 {
1887 /* If tessellation is all offchip and on-chip GS isn't used, this
1888 * workaround is not needed.
1889 */
1890 return;
1891
1892 /* SPI barrier management bug:
1893 * Make sure we have at least 4k of LDS in use to avoid the bug.
1894 * It applies to workgroup sizes of more than one wavefront.
1895 */
1896 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1897 device->physical_device->rad_info.family == CHIP_KABINI)
1898 *lds_size = MAX2(*lds_size, 8);
1899 }
1900
1901 struct radv_shader_variant *
1902 radv_get_shader(struct radv_pipeline *pipeline,
1903 gl_shader_stage stage)
1904 {
1905 if (stage == MESA_SHADER_VERTEX) {
1906 if (pipeline->shaders[MESA_SHADER_VERTEX])
1907 return pipeline->shaders[MESA_SHADER_VERTEX];
1908 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
1909 return pipeline->shaders[MESA_SHADER_TESS_CTRL];
1910 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1911 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1912 } else if (stage == MESA_SHADER_TESS_EVAL) {
1913 if (!radv_pipeline_has_tess(pipeline))
1914 return NULL;
1915 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
1916 return pipeline->shaders[MESA_SHADER_TESS_EVAL];
1917 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1918 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1919 }
1920 return pipeline->shaders[stage];
1921 }
1922
1923 static struct radv_tessellation_state
1924 calculate_tess_state(struct radv_pipeline *pipeline,
1925 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1926 {
1927 unsigned num_tcs_input_cp;
1928 unsigned num_tcs_output_cp;
1929 unsigned lds_size;
1930 unsigned num_patches;
1931 struct radv_tessellation_state tess = {0};
1932
1933 num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1934 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1935 num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
1936
1937 lds_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.lds_size;
1938
1939 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
1940 assert(lds_size <= 65536);
1941 lds_size = align(lds_size, 512) / 512;
1942 } else {
1943 assert(lds_size <= 32768);
1944 lds_size = align(lds_size, 256) / 256;
1945 }
1946 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1947
1948 tess.lds_size = lds_size;
1949
1950 tess.ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1951 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1952 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1953 tess.num_patches = num_patches;
1954
1955 struct radv_shader_variant *tes = radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL);
1956 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1957
1958 switch (tes->info.tes.primitive_mode) {
1959 case GL_TRIANGLES:
1960 type = V_028B6C_TESS_TRIANGLE;
1961 break;
1962 case GL_QUADS:
1963 type = V_028B6C_TESS_QUAD;
1964 break;
1965 case GL_ISOLINES:
1966 type = V_028B6C_TESS_ISOLINE;
1967 break;
1968 }
1969
1970 switch (tes->info.tes.spacing) {
1971 case TESS_SPACING_EQUAL:
1972 partitioning = V_028B6C_PART_INTEGER;
1973 break;
1974 case TESS_SPACING_FRACTIONAL_ODD:
1975 partitioning = V_028B6C_PART_FRAC_ODD;
1976 break;
1977 case TESS_SPACING_FRACTIONAL_EVEN:
1978 partitioning = V_028B6C_PART_FRAC_EVEN;
1979 break;
1980 default:
1981 break;
1982 }
1983
1984 bool ccw = tes->info.tes.ccw;
1985 const VkPipelineTessellationDomainOriginStateCreateInfo *domain_origin_state =
1986 vk_find_struct_const(pCreateInfo->pTessellationState,
1987 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO);
1988
1989 if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT)
1990 ccw = !ccw;
1991
1992 if (tes->info.tes.point_mode)
1993 topology = V_028B6C_OUTPUT_POINT;
1994 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
1995 topology = V_028B6C_OUTPUT_LINE;
1996 else if (ccw)
1997 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
1998 else
1999 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
2000
2001 if (pipeline->device->physical_device->rad_info.has_distributed_tess) {
2002 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
2003 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
2004 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
2005 else
2006 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
2007 } else
2008 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
2009
2010 tess.tf_param = S_028B6C_TYPE(type) |
2011 S_028B6C_PARTITIONING(partitioning) |
2012 S_028B6C_TOPOLOGY(topology) |
2013 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
2014
2015 return tess;
2016 }
2017
2018 static const struct radv_prim_vertex_count prim_size_table[] = {
2019 [V_008958_DI_PT_NONE] = {0, 0},
2020 [V_008958_DI_PT_POINTLIST] = {1, 1},
2021 [V_008958_DI_PT_LINELIST] = {2, 2},
2022 [V_008958_DI_PT_LINESTRIP] = {2, 1},
2023 [V_008958_DI_PT_TRILIST] = {3, 3},
2024 [V_008958_DI_PT_TRIFAN] = {3, 1},
2025 [V_008958_DI_PT_TRISTRIP] = {3, 1},
2026 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
2027 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
2028 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
2029 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
2030 [V_008958_DI_PT_RECTLIST] = {3, 3},
2031 [V_008958_DI_PT_LINELOOP] = {2, 1},
2032 [V_008958_DI_PT_POLYGON] = {3, 1},
2033 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
2034 };
2035
2036 static const struct radv_vs_output_info *get_vs_output_info(const struct radv_pipeline *pipeline)
2037 {
2038 if (radv_pipeline_has_gs(pipeline))
2039 if (radv_pipeline_has_ngg(pipeline))
2040 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.vs.outinfo;
2041 else
2042 return &pipeline->gs_copy_shader->info.vs.outinfo;
2043 else if (radv_pipeline_has_tess(pipeline))
2044 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
2045 else
2046 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
2047 }
2048
2049 static void
2050 radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
2051 {
2052 nir_shader* ordered_shaders[MESA_SHADER_STAGES];
2053 int shader_count = 0;
2054
2055 if(shaders[MESA_SHADER_FRAGMENT]) {
2056 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
2057 }
2058 if(shaders[MESA_SHADER_GEOMETRY]) {
2059 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
2060 }
2061 if(shaders[MESA_SHADER_TESS_EVAL]) {
2062 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
2063 }
2064 if(shaders[MESA_SHADER_TESS_CTRL]) {
2065 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
2066 }
2067 if(shaders[MESA_SHADER_VERTEX]) {
2068 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
2069 }
2070
2071 if (shader_count > 1) {
2072 unsigned first = ordered_shaders[shader_count - 1]->info.stage;
2073 unsigned last = ordered_shaders[0]->info.stage;
2074
2075 if (ordered_shaders[0]->info.stage == MESA_SHADER_FRAGMENT &&
2076 ordered_shaders[1]->info.has_transform_feedback_varyings)
2077 nir_link_xfb_varyings(ordered_shaders[1], ordered_shaders[0]);
2078
2079 for (int i = 0; i < shader_count; ++i) {
2080 nir_variable_mode mask = 0;
2081
2082 if (ordered_shaders[i]->info.stage != first)
2083 mask = mask | nir_var_shader_in;
2084
2085 if (ordered_shaders[i]->info.stage != last)
2086 mask = mask | nir_var_shader_out;
2087
2088 nir_lower_io_to_scalar_early(ordered_shaders[i], mask);
2089 radv_optimize_nir(ordered_shaders[i], false, false);
2090 }
2091 }
2092
2093 for (int i = 1; i < shader_count; ++i) {
2094 nir_lower_io_arrays_to_elements(ordered_shaders[i],
2095 ordered_shaders[i - 1]);
2096
2097 if (nir_link_opt_varyings(ordered_shaders[i],
2098 ordered_shaders[i - 1]))
2099 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2100
2101 nir_remove_dead_variables(ordered_shaders[i],
2102 nir_var_shader_out);
2103 nir_remove_dead_variables(ordered_shaders[i - 1],
2104 nir_var_shader_in);
2105
2106 bool progress = nir_remove_unused_varyings(ordered_shaders[i],
2107 ordered_shaders[i - 1]);
2108
2109 nir_compact_varyings(ordered_shaders[i],
2110 ordered_shaders[i - 1], true);
2111
2112 if (progress) {
2113 if (nir_lower_global_vars_to_local(ordered_shaders[i])) {
2114 ac_lower_indirect_derefs(ordered_shaders[i],
2115 pipeline->device->physical_device->rad_info.chip_class);
2116 }
2117 radv_optimize_nir(ordered_shaders[i], false, false);
2118
2119 if (nir_lower_global_vars_to_local(ordered_shaders[i - 1])) {
2120 ac_lower_indirect_derefs(ordered_shaders[i - 1],
2121 pipeline->device->physical_device->rad_info.chip_class);
2122 }
2123 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2124 }
2125 }
2126 }
2127
2128 static uint32_t
2129 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo *input_state,
2130 uint32_t attrib_binding)
2131 {
2132 for (uint32_t i = 0; i < input_state->vertexBindingDescriptionCount; i++) {
2133 const VkVertexInputBindingDescription *input_binding =
2134 &input_state->pVertexBindingDescriptions[i];
2135
2136 if (input_binding->binding == attrib_binding)
2137 return input_binding->stride;
2138 }
2139
2140 return 0;
2141 }
2142
2143 static struct radv_pipeline_key
2144 radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
2145 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2146 const struct radv_blend_state *blend,
2147 bool has_view_index)
2148 {
2149 const VkPipelineVertexInputStateCreateInfo *input_state =
2150 pCreateInfo->pVertexInputState;
2151 const VkPipelineVertexInputDivisorStateCreateInfoEXT *divisor_state =
2152 vk_find_struct_const(input_state->pNext, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT);
2153
2154 struct radv_pipeline_key key;
2155 memset(&key, 0, sizeof(key));
2156
2157 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
2158 key.optimisations_disabled = 1;
2159
2160 key.has_multiview_view_index = has_view_index;
2161
2162 uint32_t binding_input_rate = 0;
2163 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
2164 for (unsigned i = 0; i < input_state->vertexBindingDescriptionCount; ++i) {
2165 if (input_state->pVertexBindingDescriptions[i].inputRate) {
2166 unsigned binding = input_state->pVertexBindingDescriptions[i].binding;
2167 binding_input_rate |= 1u << binding;
2168 instance_rate_divisors[binding] = 1;
2169 }
2170 }
2171 if (divisor_state) {
2172 for (unsigned i = 0; i < divisor_state->vertexBindingDivisorCount; ++i) {
2173 instance_rate_divisors[divisor_state->pVertexBindingDivisors[i].binding] =
2174 divisor_state->pVertexBindingDivisors[i].divisor;
2175 }
2176 }
2177
2178 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
2179 const VkVertexInputAttributeDescription *desc =
2180 &input_state->pVertexAttributeDescriptions[i];
2181 const struct vk_format_description *format_desc;
2182 unsigned location = desc->location;
2183 unsigned binding = desc->binding;
2184 unsigned num_format, data_format;
2185 int first_non_void;
2186
2187 if (binding_input_rate & (1u << binding)) {
2188 key.instance_rate_inputs |= 1u << location;
2189 key.instance_rate_divisors[location] = instance_rate_divisors[binding];
2190 }
2191
2192 format_desc = vk_format_description(desc->format);
2193 first_non_void = vk_format_get_first_non_void_channel(desc->format);
2194
2195 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
2196 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
2197
2198 key.vertex_attribute_formats[location] = data_format | (num_format << 4);
2199 key.vertex_attribute_bindings[location] = desc->binding;
2200 key.vertex_attribute_offsets[location] = desc->offset;
2201 key.vertex_attribute_strides[location] = radv_get_attrib_stride(input_state, desc->binding);
2202
2203 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8 &&
2204 pipeline->device->physical_device->rad_info.family != CHIP_STONEY) {
2205 VkFormat format = input_state->pVertexAttributeDescriptions[i].format;
2206 uint64_t adjust;
2207 switch(format) {
2208 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2209 case VK_FORMAT_A2B10G10R10_SNORM_PACK32:
2210 adjust = RADV_ALPHA_ADJUST_SNORM;
2211 break;
2212 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2213 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32:
2214 adjust = RADV_ALPHA_ADJUST_SSCALED;
2215 break;
2216 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2217 case VK_FORMAT_A2B10G10R10_SINT_PACK32:
2218 adjust = RADV_ALPHA_ADJUST_SINT;
2219 break;
2220 default:
2221 adjust = 0;
2222 break;
2223 }
2224 key.vertex_alpha_adjust |= adjust << (2 * location);
2225 }
2226
2227 switch (desc->format) {
2228 case VK_FORMAT_B8G8R8A8_UNORM:
2229 case VK_FORMAT_B8G8R8A8_SNORM:
2230 case VK_FORMAT_B8G8R8A8_USCALED:
2231 case VK_FORMAT_B8G8R8A8_SSCALED:
2232 case VK_FORMAT_B8G8R8A8_UINT:
2233 case VK_FORMAT_B8G8R8A8_SINT:
2234 case VK_FORMAT_B8G8R8A8_SRGB:
2235 case VK_FORMAT_A2R10G10B10_UNORM_PACK32:
2236 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2237 case VK_FORMAT_A2R10G10B10_USCALED_PACK32:
2238 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2239 case VK_FORMAT_A2R10G10B10_UINT_PACK32:
2240 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2241 key.vertex_post_shuffle |= 1 << location;
2242 break;
2243 default:
2244 break;
2245 }
2246 }
2247
2248 if (pCreateInfo->pTessellationState)
2249 key.tess_input_vertices = pCreateInfo->pTessellationState->patchControlPoints;
2250
2251
2252 if (pCreateInfo->pMultisampleState &&
2253 pCreateInfo->pMultisampleState->rasterizationSamples > 1) {
2254 uint32_t num_samples = pCreateInfo->pMultisampleState->rasterizationSamples;
2255 uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo->pMultisampleState);
2256 key.num_samples = num_samples;
2257 key.log2_ps_iter_samples = util_logbase2(ps_iter_samples);
2258 }
2259
2260 key.col_format = blend->spi_shader_col_format;
2261 if (pipeline->device->physical_device->rad_info.chip_class < GFX8)
2262 radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.is_int8, &key.is_int10);
2263
2264 return key;
2265 }
2266
2267 static bool
2268 radv_nir_stage_uses_xfb(const nir_shader *nir)
2269 {
2270 nir_xfb_info *xfb = nir_gather_xfb_info(nir, NULL);
2271 bool uses_xfb = !!xfb;
2272
2273 ralloc_free(xfb);
2274 return uses_xfb;
2275 }
2276
2277 static void
2278 radv_fill_shader_keys(struct radv_device *device,
2279 struct radv_shader_variant_key *keys,
2280 const struct radv_pipeline_key *key,
2281 nir_shader **nir)
2282 {
2283 keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
2284 keys[MESA_SHADER_VERTEX].vs.alpha_adjust = key->vertex_alpha_adjust;
2285 keys[MESA_SHADER_VERTEX].vs.post_shuffle = key->vertex_post_shuffle;
2286 for (unsigned i = 0; i < MAX_VERTEX_ATTRIBS; ++i) {
2287 keys[MESA_SHADER_VERTEX].vs.instance_rate_divisors[i] = key->instance_rate_divisors[i];
2288 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_formats[i] = key->vertex_attribute_formats[i];
2289 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_bindings[i] = key->vertex_attribute_bindings[i];
2290 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_offsets[i] = key->vertex_attribute_offsets[i];
2291 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_strides[i] = key->vertex_attribute_strides[i];
2292 }
2293
2294 if (nir[MESA_SHADER_TESS_CTRL]) {
2295 keys[MESA_SHADER_VERTEX].vs_common_out.as_ls = true;
2296 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = 0;
2297 keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices;
2298 keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
2299
2300 keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
2301 }
2302
2303 if (nir[MESA_SHADER_GEOMETRY]) {
2304 if (nir[MESA_SHADER_TESS_CTRL])
2305 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_es = true;
2306 else
2307 keys[MESA_SHADER_VERTEX].vs_common_out.as_es = true;
2308 }
2309
2310 if (device->physical_device->rad_info.chip_class >= GFX10 &&
2311 device->physical_device->rad_info.family != CHIP_NAVI14 &&
2312 !(device->instance->debug_flags & RADV_DEBUG_NO_NGG)) {
2313 if (nir[MESA_SHADER_TESS_CTRL]) {
2314 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = true;
2315 } else {
2316 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = true;
2317 }
2318
2319 if (nir[MESA_SHADER_TESS_CTRL] &&
2320 nir[MESA_SHADER_GEOMETRY] &&
2321 nir[MESA_SHADER_GEOMETRY]->info.gs.invocations *
2322 nir[MESA_SHADER_GEOMETRY]->info.gs.vertices_out > 256) {
2323 /* Fallback to the legacy path if tessellation is
2324 * enabled with extreme geometry because
2325 * EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it
2326 * might hang.
2327 */
2328 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2329 }
2330
2331 /*
2332 * Disable NGG with geometry shaders. There are a bunch of
2333 * issues still:
2334 * * GS primitives in pipeline statistic queries do not get
2335 * updates. See dEQP-VK.query_pool.statistics_query.geometry_shader_primitives
2336 * * General issues with the last primitive missing/corrupt:
2337 * https://bugs.freedesktop.org/show_bug.cgi?id=111248
2338 *
2339 * Furthermore, XGL/AMDVLK also disables this as of 9b632ef.
2340 */
2341 if (nir[MESA_SHADER_GEOMETRY]) {
2342 if (nir[MESA_SHADER_TESS_CTRL])
2343 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2344 else
2345 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2346 }
2347
2348 if (!device->physical_device->use_ngg_streamout) {
2349 gl_shader_stage last_xfb_stage = MESA_SHADER_VERTEX;
2350
2351 for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
2352 if (nir[i])
2353 last_xfb_stage = i;
2354 }
2355
2356 if (nir[last_xfb_stage] &&
2357 radv_nir_stage_uses_xfb(nir[last_xfb_stage])) {
2358 if (nir[MESA_SHADER_TESS_CTRL])
2359 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2360 else
2361 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2362 }
2363 }
2364 }
2365
2366 for(int i = 0; i < MESA_SHADER_STAGES; ++i)
2367 keys[i].has_multiview_view_index = key->has_multiview_view_index;
2368
2369 keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format;
2370 keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8;
2371 keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
2372 keys[MESA_SHADER_FRAGMENT].fs.log2_ps_iter_samples = key->log2_ps_iter_samples;
2373 keys[MESA_SHADER_FRAGMENT].fs.num_samples = key->num_samples;
2374 }
2375
2376 static void
2377 radv_fill_shader_info(struct radv_pipeline *pipeline,
2378 struct radv_shader_variant_key *keys,
2379 struct radv_shader_info *infos,
2380 nir_shader **nir)
2381 {
2382 unsigned active_stages = 0;
2383 unsigned filled_stages = 0;
2384
2385 for (int i = 0; i < MESA_SHADER_STAGES; i++) {
2386 if (nir[i])
2387 active_stages |= (1 << i);
2388 }
2389
2390 if (nir[MESA_SHADER_FRAGMENT]) {
2391 radv_nir_shader_info_init(&infos[MESA_SHADER_FRAGMENT]);
2392 radv_nir_shader_info_pass(nir[MESA_SHADER_FRAGMENT],
2393 pipeline->layout,
2394 &keys[MESA_SHADER_FRAGMENT],
2395 &infos[MESA_SHADER_FRAGMENT]);
2396
2397 /* TODO: These are no longer used as keys we should refactor this */
2398 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id =
2399 infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
2400 keys[MESA_SHADER_VERTEX].vs_common_out.export_layer_id =
2401 infos[MESA_SHADER_FRAGMENT].ps.layer_input;
2402 keys[MESA_SHADER_VERTEX].vs_common_out.export_clip_dists =
2403 !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
2404 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_prim_id =
2405 infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
2406 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_layer_id =
2407 infos[MESA_SHADER_FRAGMENT].ps.layer_input;
2408 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_clip_dists =
2409 !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
2410
2411 filled_stages |= (1 << MESA_SHADER_FRAGMENT);
2412 }
2413
2414 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
2415 nir[MESA_SHADER_TESS_CTRL]) {
2416 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2417 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2418 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2419
2420 radv_nir_shader_info_init(&infos[MESA_SHADER_TESS_CTRL]);
2421
2422 for (int i = 0; i < 2; i++) {
2423 radv_nir_shader_info_pass(combined_nir[i],
2424 pipeline->layout, &key,
2425 &infos[MESA_SHADER_TESS_CTRL]);
2426 }
2427
2428 keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
2429 infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
2430 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs =
2431 util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written);
2432
2433 filled_stages |= (1 << MESA_SHADER_VERTEX);
2434 filled_stages |= (1 << MESA_SHADER_TESS_CTRL);
2435 }
2436
2437 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
2438 nir[MESA_SHADER_GEOMETRY]) {
2439 gl_shader_stage pre_stage = nir[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2440 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2441
2442 radv_nir_shader_info_init(&infos[MESA_SHADER_GEOMETRY]);
2443
2444 for (int i = 0; i < 2; i++) {
2445 radv_nir_shader_info_pass(combined_nir[i],
2446 pipeline->layout,
2447 &keys[pre_stage],
2448 &infos[MESA_SHADER_GEOMETRY]);
2449 }
2450
2451 filled_stages |= (1 << pre_stage);
2452 filled_stages |= (1 << MESA_SHADER_GEOMETRY);
2453 }
2454
2455 active_stages ^= filled_stages;
2456 while (active_stages) {
2457 int i = u_bit_scan(&active_stages);
2458
2459 if (i == MESA_SHADER_TESS_CTRL) {
2460 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs =
2461 util_last_bit64(infos[MESA_SHADER_VERTEX].vs.ls_outputs_written);
2462 }
2463
2464 if (i == MESA_SHADER_TESS_EVAL) {
2465 keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
2466 infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
2467 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs =
2468 util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written);
2469 }
2470
2471 radv_nir_shader_info_init(&infos[i]);
2472 radv_nir_shader_info_pass(nir[i], pipeline->layout,
2473 &keys[i], &infos[i]);
2474 }
2475 }
2476
2477 static void
2478 merge_tess_info(struct shader_info *tes_info,
2479 const struct shader_info *tcs_info)
2480 {
2481 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2482 *
2483 * "PointMode. Controls generation of points rather than triangles
2484 * or lines. This functionality defaults to disabled, and is
2485 * enabled if either shader stage includes the execution mode.
2486 *
2487 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2488 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2489 * and OutputVertices, it says:
2490 *
2491 * "One mode must be set in at least one of the tessellation
2492 * shader stages."
2493 *
2494 * So, the fields can be set in either the TCS or TES, but they must
2495 * agree if set in both. Our backend looks at TES, so bitwise-or in
2496 * the values from the TCS.
2497 */
2498 assert(tcs_info->tess.tcs_vertices_out == 0 ||
2499 tes_info->tess.tcs_vertices_out == 0 ||
2500 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
2501 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
2502
2503 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2504 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2505 tcs_info->tess.spacing == tes_info->tess.spacing);
2506 tes_info->tess.spacing |= tcs_info->tess.spacing;
2507
2508 assert(tcs_info->tess.primitive_mode == 0 ||
2509 tes_info->tess.primitive_mode == 0 ||
2510 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
2511 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
2512 tes_info->tess.ccw |= tcs_info->tess.ccw;
2513 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
2514 }
2515
2516 static
2517 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT *ext)
2518 {
2519 if (!ext)
2520 return;
2521
2522 if (ext->pPipelineCreationFeedback) {
2523 ext->pPipelineCreationFeedback->flags = 0;
2524 ext->pPipelineCreationFeedback->duration = 0;
2525 }
2526
2527 for (unsigned i = 0; i < ext->pipelineStageCreationFeedbackCount; ++i) {
2528 ext->pPipelineStageCreationFeedbacks[i].flags = 0;
2529 ext->pPipelineStageCreationFeedbacks[i].duration = 0;
2530 }
2531 }
2532
2533 static
2534 void radv_start_feedback(VkPipelineCreationFeedbackEXT *feedback)
2535 {
2536 if (!feedback)
2537 return;
2538
2539 feedback->duration -= radv_get_current_time();
2540 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT;
2541 }
2542
2543 static
2544 void radv_stop_feedback(VkPipelineCreationFeedbackEXT *feedback, bool cache_hit)
2545 {
2546 if (!feedback)
2547 return;
2548
2549 feedback->duration += radv_get_current_time();
2550 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT |
2551 (cache_hit ? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT : 0);
2552 }
2553
2554 static
2555 void radv_create_shaders(struct radv_pipeline *pipeline,
2556 struct radv_device *device,
2557 struct radv_pipeline_cache *cache,
2558 const struct radv_pipeline_key *key,
2559 const VkPipelineShaderStageCreateInfo **pStages,
2560 const VkPipelineCreateFlags flags,
2561 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2562 VkPipelineCreationFeedbackEXT *pipeline_feedback,
2563 VkPipelineCreationFeedbackEXT **stage_feedbacks)
2564 {
2565 struct radv_shader_module fs_m = {0};
2566 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
2567 nir_shader *nir[MESA_SHADER_STAGES] = {0};
2568 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2569 struct radv_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{{0}}}}};
2570 struct radv_shader_info infos[MESA_SHADER_STAGES] = {0};
2571 unsigned char hash[20], gs_copy_hash[20];
2572 bool keep_executable_info = (flags & VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR) || device->keep_shader_info;
2573
2574 radv_start_feedback(pipeline_feedback);
2575
2576 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2577 if (pStages[i]) {
2578 modules[i] = radv_shader_module_from_handle(pStages[i]->module);
2579 if (modules[i]->nir)
2580 _mesa_sha1_compute(modules[i]->nir->info.name,
2581 strlen(modules[i]->nir->info.name),
2582 modules[i]->sha1);
2583
2584 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
2585 }
2586 }
2587
2588 radv_hash_shaders(hash, pStages, pipeline->layout, key, get_hash_flags(device));
2589 memcpy(gs_copy_hash, hash, 20);
2590 gs_copy_hash[0] ^= 1;
2591
2592 bool found_in_application_cache = true;
2593 if (modules[MESA_SHADER_GEOMETRY] && !keep_executable_info) {
2594 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2595 radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants,
2596 &found_in_application_cache);
2597 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
2598 }
2599
2600 if (!keep_executable_info &&
2601 radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders,
2602 &found_in_application_cache) &&
2603 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
2604 radv_stop_feedback(pipeline_feedback, found_in_application_cache);
2605 return;
2606 }
2607
2608 if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
2609 nir_builder fs_b;
2610 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
2611 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
2612 fs_m.nir = fs_b.shader;
2613 modules[MESA_SHADER_FRAGMENT] = &fs_m;
2614 }
2615
2616 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2617 const VkPipelineShaderStageCreateInfo *stage = pStages[i];
2618
2619 if (!modules[i])
2620 continue;
2621
2622 radv_start_feedback(stage_feedbacks[i]);
2623
2624 nir[i] = radv_shader_compile_to_nir(device, modules[i],
2625 stage ? stage->pName : "main", i,
2626 stage ? stage->pSpecializationInfo : NULL,
2627 flags, pipeline->layout);
2628
2629 /* We don't want to alter meta shaders IR directly so clone it
2630 * first.
2631 */
2632 if (nir[i]->info.name) {
2633 nir[i] = nir_shader_clone(NULL, nir[i]);
2634 }
2635
2636 radv_stop_feedback(stage_feedbacks[i], false);
2637 }
2638
2639 if (nir[MESA_SHADER_TESS_CTRL]) {
2640 nir_lower_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out, NULL);
2641 merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
2642 }
2643
2644 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
2645 radv_link_shaders(pipeline, nir);
2646
2647 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2648 if (nir[i]) {
2649 NIR_PASS_V(nir[i], nir_lower_non_uniform_access,
2650 nir_lower_non_uniform_ubo_access |
2651 nir_lower_non_uniform_ssbo_access |
2652 nir_lower_non_uniform_texture_access |
2653 nir_lower_non_uniform_image_access);
2654 NIR_PASS_V(nir[i], nir_lower_bool_to_int32);
2655 }
2656
2657 if (radv_can_dump_shader(device, modules[i], false))
2658 nir_print_shader(nir[i], stderr);
2659 }
2660
2661 if (nir[MESA_SHADER_FRAGMENT])
2662 radv_lower_fs_io(nir[MESA_SHADER_FRAGMENT]);
2663
2664 radv_fill_shader_keys(device, keys, key, nir);
2665
2666 radv_fill_shader_info(pipeline, keys, infos, nir);
2667
2668 if ((nir[MESA_SHADER_VERTEX] &&
2669 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg) ||
2670 (nir[MESA_SHADER_TESS_EVAL] &&
2671 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg)) {
2672 struct gfx10_ngg_info *ngg_info;
2673
2674 if (nir[MESA_SHADER_GEOMETRY])
2675 ngg_info = &infos[MESA_SHADER_GEOMETRY].ngg_info;
2676 else if (nir[MESA_SHADER_TESS_CTRL])
2677 ngg_info = &infos[MESA_SHADER_TESS_EVAL].ngg_info;
2678 else
2679 ngg_info = &infos[MESA_SHADER_VERTEX].ngg_info;
2680
2681 gfx10_get_ngg_info(pCreateInfo, pipeline, nir, infos, ngg_info);
2682 } else if (nir[MESA_SHADER_GEOMETRY]) {
2683 struct gfx9_gs_info *gs_info =
2684 &infos[MESA_SHADER_GEOMETRY].gs_ring_info;
2685
2686 gfx9_get_gs_info(pCreateInfo, pipeline, nir, infos, gs_info);
2687 }
2688
2689 if (nir[MESA_SHADER_FRAGMENT]) {
2690 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
2691 radv_start_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT]);
2692
2693 pipeline->shaders[MESA_SHADER_FRAGMENT] =
2694 radv_shader_variant_compile(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
2695 pipeline->layout, keys + MESA_SHADER_FRAGMENT,
2696 infos + MESA_SHADER_FRAGMENT,
2697 keep_executable_info, &binaries[MESA_SHADER_FRAGMENT]);
2698
2699 radv_stop_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT], false);
2700 }
2701
2702 /* TODO: These are no longer used as keys we should refactor this */
2703 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id =
2704 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.prim_id_input;
2705 keys[MESA_SHADER_VERTEX].vs_common_out.export_layer_id =
2706 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.layer_input;
2707 keys[MESA_SHADER_VERTEX].vs_common_out.export_clip_dists =
2708 !!pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.num_input_clips_culls;
2709 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_prim_id =
2710 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.prim_id_input;
2711 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_layer_id =
2712 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.layer_input;
2713 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_clip_dists =
2714 !!pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.num_input_clips_culls;
2715 }
2716
2717 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
2718 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
2719 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2720 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2721 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2722
2723 radv_start_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL]);
2724
2725 pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_compile(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
2726 pipeline->layout,
2727 &key, &infos[MESA_SHADER_TESS_CTRL], keep_executable_info,
2728 &binaries[MESA_SHADER_TESS_CTRL]);
2729
2730 radv_stop_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL], false);
2731 }
2732 modules[MESA_SHADER_VERTEX] = NULL;
2733 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2734 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written);
2735 }
2736
2737 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
2738 gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2739 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
2740 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2741
2742 radv_start_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY]);
2743
2744 pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_compile(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
2745 pipeline->layout,
2746 &keys[pre_stage], &infos[MESA_SHADER_GEOMETRY], keep_executable_info,
2747 &binaries[MESA_SHADER_GEOMETRY]);
2748
2749 radv_stop_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY], false);
2750 }
2751 modules[pre_stage] = NULL;
2752 }
2753
2754 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2755 if(modules[i] && !pipeline->shaders[i]) {
2756 if (i == MESA_SHADER_TESS_CTRL) {
2757 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.ls_outputs_written);
2758 }
2759 if (i == MESA_SHADER_TESS_EVAL) {
2760 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2761 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written);
2762 }
2763
2764 radv_start_feedback(stage_feedbacks[i]);
2765
2766 pipeline->shaders[i] = radv_shader_variant_compile(device, modules[i], &nir[i], 1,
2767 pipeline->layout,
2768 keys + i, infos + i,keep_executable_info,
2769 &binaries[i]);
2770
2771 radv_stop_feedback(stage_feedbacks[i], false);
2772 }
2773 }
2774
2775 if(modules[MESA_SHADER_GEOMETRY]) {
2776 struct radv_shader_binary *gs_copy_binary = NULL;
2777 if (!pipeline->gs_copy_shader &&
2778 !radv_pipeline_has_ngg(pipeline)) {
2779 struct radv_shader_info info = {};
2780 struct radv_shader_variant_key key = {};
2781
2782 key.has_multiview_view_index =
2783 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index;
2784
2785 radv_nir_shader_info_pass(nir[MESA_SHADER_GEOMETRY],
2786 pipeline->layout, &key,
2787 &info);
2788
2789 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
2790 device, nir[MESA_SHADER_GEOMETRY], &info,
2791 &gs_copy_binary, keep_executable_info,
2792 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
2793 }
2794
2795 if (!keep_executable_info && pipeline->gs_copy_shader) {
2796 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2797 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2798
2799 binaries[MESA_SHADER_GEOMETRY] = gs_copy_binary;
2800 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
2801
2802 radv_pipeline_cache_insert_shaders(device, cache,
2803 gs_copy_hash,
2804 variants,
2805 binaries);
2806 }
2807 free(gs_copy_binary);
2808 }
2809
2810 if (!keep_executable_info) {
2811 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
2812 binaries);
2813 }
2814
2815 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2816 free(binaries[i]);
2817 if (nir[i]) {
2818 ralloc_free(nir[i]);
2819
2820 if (radv_can_dump_shader_stats(device, modules[i]))
2821 radv_shader_dump_stats(device,
2822 pipeline->shaders[i],
2823 i, stderr);
2824 }
2825 }
2826
2827 if (fs_m.nir)
2828 ralloc_free(fs_m.nir);
2829
2830 radv_stop_feedback(pipeline_feedback, false);
2831 }
2832
2833 static uint32_t
2834 radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
2835 gl_shader_stage stage, enum chip_class chip_class)
2836 {
2837 bool has_gs = radv_pipeline_has_gs(pipeline);
2838 bool has_tess = radv_pipeline_has_tess(pipeline);
2839 bool has_ngg = radv_pipeline_has_ngg(pipeline);
2840
2841 switch (stage) {
2842 case MESA_SHADER_FRAGMENT:
2843 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
2844 case MESA_SHADER_VERTEX:
2845 if (has_tess) {
2846 if (chip_class >= GFX10) {
2847 return R_00B430_SPI_SHADER_USER_DATA_HS_0;
2848 } else if (chip_class == GFX9) {
2849 return R_00B430_SPI_SHADER_USER_DATA_LS_0;
2850 } else {
2851 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
2852 }
2853
2854 }
2855
2856 if (has_gs) {
2857 if (chip_class >= GFX10) {
2858 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
2859 } else {
2860 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
2861 }
2862 }
2863
2864 if (has_ngg)
2865 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
2866
2867 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
2868 case MESA_SHADER_GEOMETRY:
2869 return chip_class == GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
2870 R_00B230_SPI_SHADER_USER_DATA_GS_0;
2871 case MESA_SHADER_COMPUTE:
2872 return R_00B900_COMPUTE_USER_DATA_0;
2873 case MESA_SHADER_TESS_CTRL:
2874 return chip_class == GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
2875 R_00B430_SPI_SHADER_USER_DATA_HS_0;
2876 case MESA_SHADER_TESS_EVAL:
2877 if (has_gs) {
2878 return chip_class >= GFX10 ? R_00B230_SPI_SHADER_USER_DATA_GS_0 :
2879 R_00B330_SPI_SHADER_USER_DATA_ES_0;
2880 } else if (has_ngg) {
2881 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
2882 } else {
2883 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
2884 }
2885 default:
2886 unreachable("unknown shader");
2887 }
2888 }
2889
2890 struct radv_bin_size_entry {
2891 unsigned bpp;
2892 VkExtent2D extent;
2893 };
2894
2895 static VkExtent2D
2896 radv_gfx9_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
2897 {
2898 static const struct radv_bin_size_entry color_size_table[][3][9] = {
2899 {
2900 /* One RB / SE */
2901 {
2902 /* One shader engine */
2903 { 0, {128, 128}},
2904 { 1, { 64, 128}},
2905 { 2, { 32, 128}},
2906 { 3, { 16, 128}},
2907 { 17, { 0, 0}},
2908 { UINT_MAX, { 0, 0}},
2909 },
2910 {
2911 /* Two shader engines */
2912 { 0, {128, 128}},
2913 { 2, { 64, 128}},
2914 { 3, { 32, 128}},
2915 { 5, { 16, 128}},
2916 { 17, { 0, 0}},
2917 { UINT_MAX, { 0, 0}},
2918 },
2919 {
2920 /* Four shader engines */
2921 { 0, {128, 128}},
2922 { 3, { 64, 128}},
2923 { 5, { 16, 128}},
2924 { 17, { 0, 0}},
2925 { UINT_MAX, { 0, 0}},
2926 },
2927 },
2928 {
2929 /* Two RB / SE */
2930 {
2931 /* One shader engine */
2932 { 0, {128, 128}},
2933 { 2, { 64, 128}},
2934 { 3, { 32, 128}},
2935 { 5, { 16, 128}},
2936 { 33, { 0, 0}},
2937 { UINT_MAX, { 0, 0}},
2938 },
2939 {
2940 /* Two shader engines */
2941 { 0, {128, 128}},
2942 { 3, { 64, 128}},
2943 { 5, { 32, 128}},
2944 { 9, { 16, 128}},
2945 { 33, { 0, 0}},
2946 { UINT_MAX, { 0, 0}},
2947 },
2948 {
2949 /* Four shader engines */
2950 { 0, {256, 256}},
2951 { 2, {128, 256}},
2952 { 3, {128, 128}},
2953 { 5, { 64, 128}},
2954 { 9, { 16, 128}},
2955 { 33, { 0, 0}},
2956 { UINT_MAX, { 0, 0}},
2957 },
2958 },
2959 {
2960 /* Four RB / SE */
2961 {
2962 /* One shader engine */
2963 { 0, {128, 256}},
2964 { 2, {128, 128}},
2965 { 3, { 64, 128}},
2966 { 5, { 32, 128}},
2967 { 9, { 16, 128}},
2968 { 33, { 0, 0}},
2969 { UINT_MAX, { 0, 0}},
2970 },
2971 {
2972 /* Two shader engines */
2973 { 0, {256, 256}},
2974 { 2, {128, 256}},
2975 { 3, {128, 128}},
2976 { 5, { 64, 128}},
2977 { 9, { 32, 128}},
2978 { 17, { 16, 128}},
2979 { 33, { 0, 0}},
2980 { UINT_MAX, { 0, 0}},
2981 },
2982 {
2983 /* Four shader engines */
2984 { 0, {256, 512}},
2985 { 2, {256, 256}},
2986 { 3, {128, 256}},
2987 { 5, {128, 128}},
2988 { 9, { 64, 128}},
2989 { 17, { 16, 128}},
2990 { 33, { 0, 0}},
2991 { UINT_MAX, { 0, 0}},
2992 },
2993 },
2994 };
2995 static const struct radv_bin_size_entry ds_size_table[][3][9] = {
2996 {
2997 // One RB / SE
2998 {
2999 // One shader engine
3000 { 0, {128, 256}},
3001 { 2, {128, 128}},
3002 { 4, { 64, 128}},
3003 { 7, { 32, 128}},
3004 { 13, { 16, 128}},
3005 { 49, { 0, 0}},
3006 { UINT_MAX, { 0, 0}},
3007 },
3008 {
3009 // Two shader engines
3010 { 0, {256, 256}},
3011 { 2, {128, 256}},
3012 { 4, {128, 128}},
3013 { 7, { 64, 128}},
3014 { 13, { 32, 128}},
3015 { 25, { 16, 128}},
3016 { 49, { 0, 0}},
3017 { UINT_MAX, { 0, 0}},
3018 },
3019 {
3020 // Four shader engines
3021 { 0, {256, 512}},
3022 { 2, {256, 256}},
3023 { 4, {128, 256}},
3024 { 7, {128, 128}},
3025 { 13, { 64, 128}},
3026 { 25, { 16, 128}},
3027 { 49, { 0, 0}},
3028 { UINT_MAX, { 0, 0}},
3029 },
3030 },
3031 {
3032 // Two RB / SE
3033 {
3034 // One shader engine
3035 { 0, {256, 256}},
3036 { 2, {128, 256}},
3037 { 4, {128, 128}},
3038 { 7, { 64, 128}},
3039 { 13, { 32, 128}},
3040 { 25, { 16, 128}},
3041 { 97, { 0, 0}},
3042 { UINT_MAX, { 0, 0}},
3043 },
3044 {
3045 // Two shader engines
3046 { 0, {256, 512}},
3047 { 2, {256, 256}},
3048 { 4, {128, 256}},
3049 { 7, {128, 128}},
3050 { 13, { 64, 128}},
3051 { 25, { 32, 128}},
3052 { 49, { 16, 128}},
3053 { 97, { 0, 0}},
3054 { UINT_MAX, { 0, 0}},
3055 },
3056 {
3057 // Four shader engines
3058 { 0, {512, 512}},
3059 { 2, {256, 512}},
3060 { 4, {256, 256}},
3061 { 7, {128, 256}},
3062 { 13, {128, 128}},
3063 { 25, { 64, 128}},
3064 { 49, { 16, 128}},
3065 { 97, { 0, 0}},
3066 { UINT_MAX, { 0, 0}},
3067 },
3068 },
3069 {
3070 // Four RB / SE
3071 {
3072 // One shader engine
3073 { 0, {256, 512}},
3074 { 2, {256, 256}},
3075 { 4, {128, 256}},
3076 { 7, {128, 128}},
3077 { 13, { 64, 128}},
3078 { 25, { 32, 128}},
3079 { 49, { 16, 128}},
3080 { UINT_MAX, { 0, 0}},
3081 },
3082 {
3083 // Two shader engines
3084 { 0, {512, 512}},
3085 { 2, {256, 512}},
3086 { 4, {256, 256}},
3087 { 7, {128, 256}},
3088 { 13, {128, 128}},
3089 { 25, { 64, 128}},
3090 { 49, { 32, 128}},
3091 { 97, { 16, 128}},
3092 { UINT_MAX, { 0, 0}},
3093 },
3094 {
3095 // Four shader engines
3096 { 0, {512, 512}},
3097 { 4, {256, 512}},
3098 { 7, {256, 256}},
3099 { 13, {128, 256}},
3100 { 25, {128, 128}},
3101 { 49, { 64, 128}},
3102 { 97, { 16, 128}},
3103 { UINT_MAX, { 0, 0}},
3104 },
3105 },
3106 };
3107
3108 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3109 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3110 VkExtent2D extent = {512, 512};
3111
3112 unsigned log_num_rb_per_se =
3113 util_logbase2_ceil(pipeline->device->physical_device->rad_info.num_render_backends /
3114 pipeline->device->physical_device->rad_info.max_se);
3115 unsigned log_num_se = util_logbase2_ceil(pipeline->device->physical_device->rad_info.max_se);
3116
3117 unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
3118 unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->graphics.ms.db_eqaa);
3119 unsigned effective_samples = total_samples;
3120 unsigned color_bytes_per_pixel = 0;
3121
3122 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
3123 if (vkblend) {
3124 for (unsigned i = 0; i < subpass->color_count; i++) {
3125 if (!vkblend->pAttachments[i].colorWriteMask)
3126 continue;
3127
3128 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3129 continue;
3130
3131 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3132 color_bytes_per_pixel += vk_format_get_blocksize(format);
3133 }
3134
3135 /* MSAA images typically don't use all samples all the time. */
3136 if (effective_samples >= 2 && ps_iter_samples <= 1)
3137 effective_samples = 2;
3138 color_bytes_per_pixel *= effective_samples;
3139 }
3140
3141 const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se];
3142 while(color_entry[1].bpp <= color_bytes_per_pixel)
3143 ++color_entry;
3144
3145 extent = color_entry->extent;
3146
3147 if (subpass->depth_stencil_attachment) {
3148 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3149
3150 /* Coefficients taken from AMDVLK */
3151 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
3152 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
3153 unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples;
3154
3155 const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se];
3156 while(ds_entry[1].bpp <= ds_bytes_per_pixel)
3157 ++ds_entry;
3158
3159 if (ds_entry->extent.width * ds_entry->extent.height < extent.width * extent.height)
3160 extent = ds_entry->extent;
3161 }
3162
3163 return extent;
3164 }
3165
3166 static VkExtent2D
3167 radv_gfx10_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
3168 {
3169 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3170 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3171 VkExtent2D extent = {512, 512};
3172
3173 const unsigned db_tag_size = 64;
3174 const unsigned db_tag_count = 312;
3175 const unsigned color_tag_size = 1024;
3176 const unsigned color_tag_count = 31;
3177 const unsigned fmask_tag_size = 256;
3178 const unsigned fmask_tag_count = 44;
3179
3180 const unsigned rb_count = pipeline->device->physical_device->rad_info.num_render_backends;
3181 const unsigned pipe_count = MAX2(rb_count, pipeline->device->physical_device->rad_info.num_sdp_interfaces);
3182
3183 const unsigned db_tag_part = (db_tag_count * rb_count / pipe_count) * db_tag_size * pipe_count;
3184 const unsigned color_tag_part = (color_tag_count * rb_count / pipe_count) * color_tag_size * pipe_count;
3185 const unsigned fmask_tag_part = (fmask_tag_count * rb_count / pipe_count) * fmask_tag_size * pipe_count;
3186
3187 const unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
3188 const unsigned samples_log = util_logbase2_ceil(total_samples);
3189
3190 unsigned color_bytes_per_pixel = 0;
3191 unsigned fmask_bytes_per_pixel = 0;
3192
3193 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
3194 if (vkblend) {
3195 for (unsigned i = 0; i < subpass->color_count; i++) {
3196 if (!vkblend->pAttachments[i].colorWriteMask)
3197 continue;
3198
3199 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3200 continue;
3201
3202 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3203 color_bytes_per_pixel += vk_format_get_blocksize(format);
3204
3205 if (total_samples > 1) {
3206 const unsigned fmask_array[] = {0, 1, 1, 4};
3207 fmask_bytes_per_pixel += fmask_array[samples_log];
3208 }
3209 }
3210
3211 color_bytes_per_pixel *= total_samples;
3212 }
3213 color_bytes_per_pixel = MAX2(color_bytes_per_pixel, 1);
3214
3215 const unsigned color_pixel_count_log = util_logbase2(color_tag_part / color_bytes_per_pixel);
3216 extent.width = 1ull << ((color_pixel_count_log + 1) / 2);
3217 extent.height = 1ull << (color_pixel_count_log / 2);
3218
3219 if (fmask_bytes_per_pixel) {
3220 const unsigned fmask_pixel_count_log = util_logbase2(fmask_tag_part / fmask_bytes_per_pixel);
3221
3222 const VkExtent2D fmask_extent = (VkExtent2D){
3223 .width = 1ull << ((fmask_pixel_count_log + 1) / 2),
3224 .height = 1ull << (color_pixel_count_log / 2)
3225 };
3226
3227 if (fmask_extent.width * fmask_extent.height < extent.width * extent.height)
3228 extent = fmask_extent;
3229 }
3230
3231 if (subpass->depth_stencil_attachment) {
3232 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3233
3234 /* Coefficients taken from AMDVLK */
3235 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
3236 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
3237 unsigned db_bytes_per_pixel = (depth_coeff + stencil_coeff) * total_samples;
3238
3239 const unsigned db_pixel_count_log = util_logbase2(db_tag_part / db_bytes_per_pixel);
3240
3241 const VkExtent2D db_extent = (VkExtent2D){
3242 .width = 1ull << ((db_pixel_count_log + 1) / 2),
3243 .height = 1ull << (color_pixel_count_log / 2)
3244 };
3245
3246 if (db_extent.width * db_extent.height < extent.width * extent.height)
3247 extent = db_extent;
3248 }
3249
3250 extent.width = MAX2(extent.width, 128);
3251 extent.height = MAX2(extent.width, 64);
3252
3253 return extent;
3254 }
3255
3256 static void
3257 radv_pipeline_generate_disabled_binning_state(struct radeon_cmdbuf *ctx_cs,
3258 struct radv_pipeline *pipeline,
3259 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3260 {
3261 uint32_t pa_sc_binner_cntl_0 =
3262 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
3263 S_028C44_DISABLE_START_OF_PRIM(1);
3264 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
3265
3266 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3267 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3268 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3269 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
3270 unsigned min_bytes_per_pixel = 0;
3271
3272 if (vkblend) {
3273 for (unsigned i = 0; i < subpass->color_count; i++) {
3274 if (!vkblend->pAttachments[i].colorWriteMask)
3275 continue;
3276
3277 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3278 continue;
3279
3280 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3281 unsigned bytes = vk_format_get_blocksize(format);
3282 if (!min_bytes_per_pixel || bytes < min_bytes_per_pixel)
3283 min_bytes_per_pixel = bytes;
3284 }
3285 }
3286
3287 pa_sc_binner_cntl_0 =
3288 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC) |
3289 S_028C44_BIN_SIZE_X(0) |
3290 S_028C44_BIN_SIZE_Y(0) |
3291 S_028C44_BIN_SIZE_X_EXTEND(2) | /* 128 */
3292 S_028C44_BIN_SIZE_Y_EXTEND(min_bytes_per_pixel <= 4 ? 2 : 1) | /* 128 or 64 */
3293 S_028C44_DISABLE_START_OF_PRIM(1);
3294 }
3295
3296 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
3297 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
3298 }
3299
3300 static void
3301 radv_pipeline_generate_binning_state(struct radeon_cmdbuf *ctx_cs,
3302 struct radv_pipeline *pipeline,
3303 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3304 {
3305 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
3306 return;
3307
3308 VkExtent2D bin_size;
3309 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3310 bin_size = radv_gfx10_compute_bin_size(pipeline, pCreateInfo);
3311 } else if (pipeline->device->physical_device->rad_info.chip_class == GFX9) {
3312 bin_size = radv_gfx9_compute_bin_size(pipeline, pCreateInfo);
3313 } else
3314 unreachable("Unhandled generation for binning bin size calculation");
3315
3316 if (pipeline->device->pbb_allowed && bin_size.width && bin_size.height) {
3317 unsigned context_states_per_bin; /* allowed range: [1, 6] */
3318 unsigned persistent_states_per_bin; /* allowed range: [1, 32] */
3319 unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */
3320
3321 if (pipeline->device->physical_device->rad_info.has_dedicated_vram) {
3322 context_states_per_bin = 1;
3323 persistent_states_per_bin = 1;
3324 fpovs_per_batch = 63;
3325 } else {
3326 /* The context states are affected by the scissor bug. */
3327 context_states_per_bin = pipeline->device->physical_device->rad_info.has_gfx9_scissor_bug ? 1 : 6;
3328 /* 32 causes hangs for RAVEN. */
3329 persistent_states_per_bin = 16;
3330 fpovs_per_batch = 63;
3331 }
3332
3333 const uint32_t pa_sc_binner_cntl_0 =
3334 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
3335 S_028C44_BIN_SIZE_X(bin_size.width == 16) |
3336 S_028C44_BIN_SIZE_Y(bin_size.height == 16) |
3337 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size.width, 32)) - 5) |
3338 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size.height, 32)) - 5) |
3339 S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin - 1) |
3340 S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin - 1) |
3341 S_028C44_DISABLE_START_OF_PRIM(1) |
3342 S_028C44_FPOVS_PER_BATCH(fpovs_per_batch) |
3343 S_028C44_OPTIMAL_BIN_SELECTION(1);
3344
3345 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
3346
3347 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
3348 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
3349 } else
3350 radv_pipeline_generate_disabled_binning_state(ctx_cs, pipeline, pCreateInfo);
3351 }
3352
3353
3354 static void
3355 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf *ctx_cs,
3356 struct radv_pipeline *pipeline,
3357 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3358 const struct radv_graphics_pipeline_create_info *extra)
3359 {
3360 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
3361 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3362 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3363 struct radv_render_pass_attachment *attachment = NULL;
3364 uint32_t db_depth_control = 0, db_stencil_control = 0;
3365 uint32_t db_render_control = 0, db_render_override2 = 0;
3366 uint32_t db_render_override = 0;
3367
3368 if (subpass->depth_stencil_attachment)
3369 attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3370
3371 bool has_depth_attachment = attachment && vk_format_is_depth(attachment->format);
3372 bool has_stencil_attachment = attachment && vk_format_is_stencil(attachment->format);
3373
3374 if (vkds && has_depth_attachment) {
3375 db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
3376 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
3377 S_028800_ZFUNC(vkds->depthCompareOp) |
3378 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
3379
3380 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
3381 db_render_override2 |= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment->samples > 2);
3382 }
3383
3384 if (has_stencil_attachment && vkds && vkds->stencilTestEnable) {
3385 db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
3386 db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
3387 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
3388 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
3389 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
3390
3391 db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
3392 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
3393 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
3394 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
3395 }
3396
3397 if (attachment && extra) {
3398 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
3399 db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
3400
3401 db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
3402 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
3403 db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
3404 db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
3405 db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
3406 }
3407
3408 db_render_override |= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3409 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
3410
3411 if (!pCreateInfo->pRasterizationState->depthClampEnable) {
3412 /* From VK_EXT_depth_range_unrestricted spec:
3413 *
3414 * "The behavior described in Primitive Clipping still applies.
3415 * If depth clamping is disabled the depth values are still
3416 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
3417 * depth clamping is enabled the above equation is ignored and
3418 * the depth values are instead clamped to the VkViewport
3419 * minDepth and maxDepth values, which in the case of this
3420 * extension can be outside of the 0.0 to 1.0 range."
3421 */
3422 db_render_override |= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
3423 }
3424
3425 radeon_set_context_reg(ctx_cs, R_028800_DB_DEPTH_CONTROL, db_depth_control);
3426 radeon_set_context_reg(ctx_cs, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
3427
3428 radeon_set_context_reg(ctx_cs, R_028000_DB_RENDER_CONTROL, db_render_control);
3429 radeon_set_context_reg(ctx_cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
3430 radeon_set_context_reg(ctx_cs, R_028010_DB_RENDER_OVERRIDE2, db_render_override2);
3431 }
3432
3433 static void
3434 radv_pipeline_generate_blend_state(struct radeon_cmdbuf *ctx_cs,
3435 struct radv_pipeline *pipeline,
3436 const struct radv_blend_state *blend)
3437 {
3438 radeon_set_context_reg_seq(ctx_cs, R_028780_CB_BLEND0_CONTROL, 8);
3439 radeon_emit_array(ctx_cs, blend->cb_blend_control,
3440 8);
3441 radeon_set_context_reg(ctx_cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control);
3442 radeon_set_context_reg(ctx_cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask);
3443
3444 if (pipeline->device->physical_device->rad_info.has_rbplus) {
3445
3446 radeon_set_context_reg_seq(ctx_cs, R_028760_SX_MRT0_BLEND_OPT, 8);
3447 radeon_emit_array(ctx_cs, blend->sx_mrt_blend_opt, 8);
3448 }
3449
3450 radeon_set_context_reg(ctx_cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
3451
3452 radeon_set_context_reg(ctx_cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
3453 radeon_set_context_reg(ctx_cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
3454
3455 pipeline->graphics.col_format = blend->spi_shader_col_format;
3456 pipeline->graphics.cb_target_mask = blend->cb_target_mask;
3457 }
3458
3459 static const VkConservativeRasterizationModeEXT
3460 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo *pCreateInfo)
3461 {
3462 const VkPipelineRasterizationConservativeStateCreateInfoEXT *conservative_raster =
3463 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT);
3464
3465 if (!conservative_raster)
3466 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT;
3467 return conservative_raster->conservativeRasterizationMode;
3468 }
3469
3470 static void
3471 radv_pipeline_generate_raster_state(struct radeon_cmdbuf *ctx_cs,
3472 struct radv_pipeline *pipeline,
3473 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3474 {
3475 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
3476 const VkConservativeRasterizationModeEXT mode =
3477 radv_get_conservative_raster_mode(vkraster);
3478 uint32_t pa_sc_conservative_rast = S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
3479 bool depth_clip_disable = vkraster->depthClampEnable;
3480
3481 const VkPipelineRasterizationDepthClipStateCreateInfoEXT *depth_clip_state =
3482 vk_find_struct_const(vkraster->pNext, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT);
3483 if (depth_clip_state) {
3484 depth_clip_disable = !depth_clip_state->depthClipEnable;
3485 }
3486
3487 radeon_set_context_reg(ctx_cs, R_028810_PA_CL_CLIP_CNTL,
3488 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
3489 S_028810_ZCLIP_NEAR_DISABLE(depth_clip_disable ? 1 : 0) |
3490 S_028810_ZCLIP_FAR_DISABLE(depth_clip_disable ? 1 : 0) |
3491 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
3492 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
3493
3494 radeon_set_context_reg(ctx_cs, R_0286D4_SPI_INTERP_CONTROL_0,
3495 S_0286D4_FLAT_SHADE_ENA(1) |
3496 S_0286D4_PNT_SPRITE_ENA(1) |
3497 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
3498 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
3499 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
3500 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
3501 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
3502
3503 radeon_set_context_reg(ctx_cs, R_028BE4_PA_SU_VTX_CNTL,
3504 S_028BE4_PIX_CENTER(1) | // TODO verify
3505 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
3506 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
3507
3508 radeon_set_context_reg(ctx_cs, R_028814_PA_SU_SC_MODE_CNTL,
3509 S_028814_FACE(vkraster->frontFace) |
3510 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
3511 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
3512 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
3513 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
3514 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
3515 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
3516 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
3517 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0));
3518
3519 /* Conservative rasterization. */
3520 if (mode != VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT) {
3521 struct radv_multisample_state *ms = &pipeline->graphics.ms;
3522
3523 ms->pa_sc_aa_config |= S_028BE0_AA_MASK_CENTROID_DTMN(1);
3524 ms->db_eqaa |= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
3525 S_028804_OVERRASTERIZATION_AMOUNT(4);
3526
3527 pa_sc_conservative_rast = S_028C4C_PREZ_AA_MASK_ENABLE(1) |
3528 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
3529 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
3530
3531 if (mode == VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT) {
3532 pa_sc_conservative_rast |=
3533 S_028C4C_OVER_RAST_ENABLE(1) |
3534 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
3535 S_028C4C_UNDER_RAST_ENABLE(0) |
3536 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
3537 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
3538 } else {
3539 assert(mode == VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT);
3540 pa_sc_conservative_rast |=
3541 S_028C4C_OVER_RAST_ENABLE(0) |
3542 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
3543 S_028C4C_UNDER_RAST_ENABLE(1) |
3544 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
3545 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
3546 }
3547 }
3548
3549 radeon_set_context_reg(ctx_cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
3550 pa_sc_conservative_rast);
3551 }
3552
3553
3554 static void
3555 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf *ctx_cs,
3556 struct radv_pipeline *pipeline)
3557 {
3558 struct radv_multisample_state *ms = &pipeline->graphics.ms;
3559
3560 radeon_set_context_reg_seq(ctx_cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3561 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[0]);
3562 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[1]);
3563
3564 radeon_set_context_reg(ctx_cs, R_028804_DB_EQAA, ms->db_eqaa);
3565 radeon_set_context_reg(ctx_cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
3566
3567 /* The exclusion bits can be set to improve rasterization efficiency
3568 * if no sample lies on the pixel boundary (-8 sample offset). It's
3569 * currently always TRUE because the driver doesn't support 16 samples.
3570 */
3571 bool exclusion = pipeline->device->physical_device->rad_info.chip_class >= GFX7;
3572 radeon_set_context_reg(ctx_cs, R_02882C_PA_SU_PRIM_FILTER_CNTL,
3573 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
3574 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
3575 }
3576
3577 static void
3578 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf *ctx_cs,
3579 struct radv_pipeline *pipeline)
3580 {
3581 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3582 const struct radv_shader_variant *vs =
3583 pipeline->shaders[MESA_SHADER_TESS_EVAL] ?
3584 pipeline->shaders[MESA_SHADER_TESS_EVAL] :
3585 pipeline->shaders[MESA_SHADER_VERTEX];
3586 unsigned vgt_primitiveid_en = 0;
3587 uint32_t vgt_gs_mode = 0;
3588
3589 if (radv_pipeline_has_ngg(pipeline))
3590 return;
3591
3592 if (radv_pipeline_has_gs(pipeline)) {
3593 const struct radv_shader_variant *gs =
3594 pipeline->shaders[MESA_SHADER_GEOMETRY];
3595
3596 vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out,
3597 pipeline->device->physical_device->rad_info.chip_class);
3598 } else if (outinfo->export_prim_id || vs->info.uses_prim_id) {
3599 vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
3600 vgt_primitiveid_en |= S_028A84_PRIMITIVEID_EN(1);
3601 }
3602
3603 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN, vgt_primitiveid_en);
3604 radeon_set_context_reg(ctx_cs, R_028A40_VGT_GS_MODE, vgt_gs_mode);
3605 }
3606
3607 static void
3608 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs,
3609 struct radeon_cmdbuf *cs,
3610 struct radv_pipeline *pipeline,
3611 struct radv_shader_variant *shader)
3612 {
3613 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3614
3615 radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
3616 radeon_emit(cs, va >> 8);
3617 radeon_emit(cs, S_00B124_MEM_BASE(va >> 40));
3618 radeon_emit(cs, shader->config.rsrc1);
3619 radeon_emit(cs, shader->config.rsrc2);
3620
3621 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3622 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3623 clip_dist_mask = outinfo->clip_dist_mask;
3624 cull_dist_mask = outinfo->cull_dist_mask;
3625 total_mask = clip_dist_mask | cull_dist_mask;
3626 bool misc_vec_ena = outinfo->writes_pointsize ||
3627 outinfo->writes_layer ||
3628 outinfo->writes_viewport_index;
3629 unsigned spi_vs_out_config, nparams;
3630
3631 /* VS is required to export at least one param. */
3632 nparams = MAX2(outinfo->param_exports, 1);
3633 spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
3634
3635 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3636 spi_vs_out_config |= S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0);
3637 }
3638
3639 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG, spi_vs_out_config);
3640
3641 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
3642 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
3643 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
3644 V_02870C_SPI_SHADER_4COMP :
3645 V_02870C_SPI_SHADER_NONE) |
3646 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
3647 V_02870C_SPI_SHADER_4COMP :
3648 V_02870C_SPI_SHADER_NONE) |
3649 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
3650 V_02870C_SPI_SHADER_4COMP :
3651 V_02870C_SPI_SHADER_NONE));
3652
3653 radeon_set_context_reg(ctx_cs, R_028818_PA_CL_VTE_CNTL,
3654 S_028818_VTX_W0_FMT(1) |
3655 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3656 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3657 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3658
3659 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
3660 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
3661 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
3662 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
3663 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
3664 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
3665 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
3666 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
3667 cull_dist_mask << 8 |
3668 clip_dist_mask);
3669
3670 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
3671 radeon_set_context_reg(ctx_cs, R_028AB4_VGT_REUSE_OFF,
3672 outinfo->writes_viewport_index);
3673 }
3674
3675 static void
3676 radv_pipeline_generate_hw_es(struct radeon_cmdbuf *cs,
3677 struct radv_pipeline *pipeline,
3678 struct radv_shader_variant *shader)
3679 {
3680 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3681
3682 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
3683 radeon_emit(cs, va >> 8);
3684 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3685 radeon_emit(cs, shader->config.rsrc1);
3686 radeon_emit(cs, shader->config.rsrc2);
3687 }
3688
3689 static void
3690 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf *cs,
3691 struct radv_pipeline *pipeline,
3692 struct radv_shader_variant *shader,
3693 const struct radv_tessellation_state *tess)
3694 {
3695 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3696 uint32_t rsrc2 = shader->config.rsrc2;
3697
3698 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
3699 radeon_emit(cs, va >> 8);
3700 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
3701
3702 rsrc2 |= S_00B52C_LDS_SIZE(tess->lds_size);
3703 if (pipeline->device->physical_device->rad_info.chip_class == GFX7 &&
3704 pipeline->device->physical_device->rad_info.family != CHIP_HAWAII)
3705 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
3706
3707 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
3708 radeon_emit(cs, shader->config.rsrc1);
3709 radeon_emit(cs, rsrc2);
3710 }
3711
3712 static void
3713 radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs,
3714 struct radeon_cmdbuf *cs,
3715 struct radv_pipeline *pipeline,
3716 struct radv_shader_variant *shader)
3717 {
3718 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3719 gl_shader_stage es_type =
3720 radv_pipeline_has_tess(pipeline) ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
3721 struct radv_shader_variant *es =
3722 es_type == MESA_SHADER_TESS_EVAL ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX];
3723 const struct gfx10_ngg_info *ngg_state = &shader->info.ngg_info;
3724
3725 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
3726 radeon_emit(cs, va >> 8);
3727 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3728 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
3729 radeon_emit(cs, shader->config.rsrc1);
3730 radeon_emit(cs, shader->config.rsrc2);
3731
3732 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3733 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3734 clip_dist_mask = outinfo->clip_dist_mask;
3735 cull_dist_mask = outinfo->cull_dist_mask;
3736 total_mask = clip_dist_mask | cull_dist_mask;
3737 bool misc_vec_ena = outinfo->writes_pointsize ||
3738 outinfo->writes_layer ||
3739 outinfo->writes_viewport_index;
3740 bool es_enable_prim_id = outinfo->export_prim_id ||
3741 (es && es->info.uses_prim_id);
3742 bool break_wave_at_eoi = false;
3743 unsigned ge_cntl;
3744 unsigned nparams;
3745
3746 if (es_type == MESA_SHADER_TESS_EVAL) {
3747 struct radv_shader_variant *gs =
3748 pipeline->shaders[MESA_SHADER_GEOMETRY];
3749
3750 if (es_enable_prim_id || (gs && gs->info.uses_prim_id))
3751 break_wave_at_eoi = true;
3752 }
3753
3754 nparams = MAX2(outinfo->param_exports, 1);
3755 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG,
3756 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
3757 S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0));
3758
3759 radeon_set_context_reg(ctx_cs, R_028708_SPI_SHADER_IDX_FORMAT,
3760 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP));
3761 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
3762 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
3763 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
3764 V_02870C_SPI_SHADER_4COMP :
3765 V_02870C_SPI_SHADER_NONE) |
3766 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
3767 V_02870C_SPI_SHADER_4COMP :
3768 V_02870C_SPI_SHADER_NONE) |
3769 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
3770 V_02870C_SPI_SHADER_4COMP :
3771 V_02870C_SPI_SHADER_NONE));
3772
3773 radeon_set_context_reg(ctx_cs, R_028818_PA_CL_VTE_CNTL,
3774 S_028818_VTX_W0_FMT(1) |
3775 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3776 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3777 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3778 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
3779 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
3780 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
3781 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
3782 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
3783 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
3784 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
3785 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
3786 cull_dist_mask << 8 |
3787 clip_dist_mask);
3788
3789 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN,
3790 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
3791 S_028A84_NGG_DISABLE_PROVOK_REUSE(es_enable_prim_id));
3792
3793 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
3794 ngg_state->vgt_esgs_ring_itemsize);
3795
3796 /* NGG specific registers. */
3797 struct radv_shader_variant *gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
3798 uint32_t gs_num_invocations = gs ? gs->info.gs.invocations : 1;
3799
3800 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
3801 S_028A44_ES_VERTS_PER_SUBGRP(ngg_state->hw_max_esverts) |
3802 S_028A44_GS_PRIMS_PER_SUBGRP(ngg_state->max_gsprims) |
3803 S_028A44_GS_INST_PRIMS_IN_SUBGRP(ngg_state->max_gsprims * gs_num_invocations));
3804 radeon_set_context_reg(ctx_cs, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
3805 S_0287FC_MAX_VERTS_PER_SUBGROUP(ngg_state->max_out_verts));
3806 radeon_set_context_reg(ctx_cs, R_028B4C_GE_NGG_SUBGRP_CNTL,
3807 S_028B4C_PRIM_AMP_FACTOR(ngg_state->prim_amp_factor) |
3808 S_028B4C_THDS_PER_SUBGRP(0)); /* for fast launch */
3809 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
3810 S_028B90_CNT(gs_num_invocations) |
3811 S_028B90_ENABLE(gs_num_invocations > 1) |
3812 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(ngg_state->max_vert_out_per_gs_instance));
3813
3814 /* User edge flags are set by the pos exports. If user edge flags are
3815 * not used, we must use hw-generated edge flags and pass them via
3816 * the prim export to prevent drawing lines on internal edges of
3817 * decomposed primitives (such as quads) with polygon mode = lines.
3818 *
3819 * TODO: We should combine hw-generated edge flags with user edge
3820 * flags in the shader.
3821 */
3822 radeon_set_context_reg(ctx_cs, R_028838_PA_CL_NGG_CNTL,
3823 S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline) &&
3824 !radv_pipeline_has_gs(pipeline)));
3825
3826 ge_cntl = S_03096C_PRIM_GRP_SIZE(ngg_state->max_gsprims) |
3827 S_03096C_VERT_GRP_SIZE(ngg_state->hw_max_esverts) |
3828 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
3829
3830 /* Bug workaround for a possible hang with non-tessellation cases.
3831 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
3832 *
3833 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
3834 */
3835 if ((pipeline->device->physical_device->rad_info.family == CHIP_NAVI10 ||
3836 pipeline->device->physical_device->rad_info.family == CHIP_NAVI12 ||
3837 pipeline->device->physical_device->rad_info.family == CHIP_NAVI14) &&
3838 !radv_pipeline_has_tess(pipeline) &&
3839 ngg_state->hw_max_esverts != 256) {
3840 ge_cntl &= C_03096C_VERT_GRP_SIZE;
3841
3842 if (ngg_state->hw_max_esverts > 5) {
3843 ge_cntl |= S_03096C_VERT_GRP_SIZE(ngg_state->hw_max_esverts - 5);
3844 }
3845 }
3846
3847 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL, ge_cntl);
3848 }
3849
3850 static void
3851 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf *cs,
3852 struct radv_pipeline *pipeline,
3853 struct radv_shader_variant *shader,
3854 const struct radv_tessellation_state *tess)
3855 {
3856 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3857
3858 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
3859 unsigned hs_rsrc2 = shader->config.rsrc2;
3860
3861 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3862 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX10(tess->lds_size);
3863 } else {
3864 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX9(tess->lds_size);
3865 }
3866
3867 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3868 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
3869 radeon_emit(cs, va >> 8);
3870 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
3871 } else {
3872 radeon_set_sh_reg_seq(cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
3873 radeon_emit(cs, va >> 8);
3874 radeon_emit(cs, S_00B414_MEM_BASE(va >> 40));
3875 }
3876
3877 radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
3878 radeon_emit(cs, shader->config.rsrc1);
3879 radeon_emit(cs, hs_rsrc2);
3880 } else {
3881 radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
3882 radeon_emit(cs, va >> 8);
3883 radeon_emit(cs, S_00B424_MEM_BASE(va >> 40));
3884 radeon_emit(cs, shader->config.rsrc1);
3885 radeon_emit(cs, shader->config.rsrc2);
3886 }
3887 }
3888
3889 static void
3890 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf *ctx_cs,
3891 struct radeon_cmdbuf *cs,
3892 struct radv_pipeline *pipeline,
3893 const struct radv_tessellation_state *tess)
3894 {
3895 struct radv_shader_variant *vs;
3896
3897 /* Skip shaders merged into HS/GS */
3898 vs = pipeline->shaders[MESA_SHADER_VERTEX];
3899 if (!vs)
3900 return;
3901
3902 if (vs->info.vs.as_ls)
3903 radv_pipeline_generate_hw_ls(cs, pipeline, vs, tess);
3904 else if (vs->info.vs.as_es)
3905 radv_pipeline_generate_hw_es(cs, pipeline, vs);
3906 else if (vs->info.is_ngg)
3907 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, vs);
3908 else
3909 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, vs);
3910 }
3911
3912 static void
3913 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf *ctx_cs,
3914 struct radeon_cmdbuf *cs,
3915 struct radv_pipeline *pipeline,
3916 const struct radv_tessellation_state *tess)
3917 {
3918 if (!radv_pipeline_has_tess(pipeline))
3919 return;
3920
3921 struct radv_shader_variant *tes, *tcs;
3922
3923 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
3924 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
3925
3926 if (tes) {
3927 if (tes->info.is_ngg) {
3928 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, tes);
3929 } else if (tes->info.tes.as_es)
3930 radv_pipeline_generate_hw_es(cs, pipeline, tes);
3931 else
3932 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, tes);
3933 }
3934
3935 radv_pipeline_generate_hw_hs(cs, pipeline, tcs, tess);
3936
3937 radeon_set_context_reg(ctx_cs, R_028B6C_VGT_TF_PARAM,
3938 tess->tf_param);
3939
3940 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7)
3941 radeon_set_context_reg_idx(ctx_cs, R_028B58_VGT_LS_HS_CONFIG, 2,
3942 tess->ls_hs_config);
3943 else
3944 radeon_set_context_reg(ctx_cs, R_028B58_VGT_LS_HS_CONFIG,
3945 tess->ls_hs_config);
3946
3947 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 &&
3948 !radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) {
3949 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
3950 S_028A44_ES_VERTS_PER_SUBGRP(250) |
3951 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
3952 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
3953 }
3954 }
3955
3956 static void
3957 radv_pipeline_generate_hw_gs(struct radeon_cmdbuf *ctx_cs,
3958 struct radeon_cmdbuf *cs,
3959 struct radv_pipeline *pipeline,
3960 struct radv_shader_variant *gs)
3961 {
3962 const struct gfx9_gs_info *gs_state = &gs->info.gs_ring_info;
3963 unsigned gs_max_out_vertices;
3964 uint8_t *num_components;
3965 uint8_t max_stream;
3966 unsigned offset;
3967 uint64_t va;
3968
3969 gs_max_out_vertices = gs->info.gs.vertices_out;
3970 max_stream = gs->info.gs.max_stream;
3971 num_components = gs->info.gs.num_stream_output_components;
3972
3973 offset = num_components[0] * gs_max_out_vertices;
3974
3975 radeon_set_context_reg_seq(ctx_cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
3976 radeon_emit(ctx_cs, offset);
3977 if (max_stream >= 1)
3978 offset += num_components[1] * gs_max_out_vertices;
3979 radeon_emit(ctx_cs, offset);
3980 if (max_stream >= 2)
3981 offset += num_components[2] * gs_max_out_vertices;
3982 radeon_emit(ctx_cs, offset);
3983 if (max_stream >= 3)
3984 offset += num_components[3] * gs_max_out_vertices;
3985 radeon_set_context_reg(ctx_cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
3986
3987 radeon_set_context_reg_seq(ctx_cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
3988 radeon_emit(ctx_cs, num_components[0]);
3989 radeon_emit(ctx_cs, (max_stream >= 1) ? num_components[1] : 0);
3990 radeon_emit(ctx_cs, (max_stream >= 2) ? num_components[2] : 0);
3991 radeon_emit(ctx_cs, (max_stream >= 3) ? num_components[3] : 0);
3992
3993 uint32_t gs_num_invocations = gs->info.gs.invocations;
3994 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
3995 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
3996 S_028B90_ENABLE(gs_num_invocations > 0));
3997
3998 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
3999 gs_state->vgt_esgs_ring_itemsize);
4000
4001 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
4002
4003 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
4004 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4005 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
4006 radeon_emit(cs, va >> 8);
4007 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
4008 } else {
4009 radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
4010 radeon_emit(cs, va >> 8);
4011 radeon_emit(cs, S_00B214_MEM_BASE(va >> 40));
4012 }
4013
4014 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
4015 radeon_emit(cs, gs->config.rsrc1);
4016 radeon_emit(cs, gs->config.rsrc2 | S_00B22C_LDS_SIZE(gs_state->lds_size));
4017
4018 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL, gs_state->vgt_gs_onchip_cntl);
4019 radeon_set_context_reg(ctx_cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, gs_state->vgt_gs_max_prims_per_subgroup);
4020 } else {
4021 radeon_set_sh_reg_seq(cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
4022 radeon_emit(cs, va >> 8);
4023 radeon_emit(cs, S_00B224_MEM_BASE(va >> 40));
4024 radeon_emit(cs, gs->config.rsrc1);
4025 radeon_emit(cs, gs->config.rsrc2);
4026 }
4027
4028 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, pipeline->gs_copy_shader);
4029 }
4030
4031 static void
4032 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf *ctx_cs,
4033 struct radeon_cmdbuf *cs,
4034 struct radv_pipeline *pipeline)
4035 {
4036 struct radv_shader_variant *gs;
4037
4038 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
4039 if (!gs)
4040 return;
4041
4042 if (gs->info.is_ngg)
4043 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, gs);
4044 else
4045 radv_pipeline_generate_hw_gs(ctx_cs, cs, pipeline, gs);
4046
4047 radeon_set_context_reg(ctx_cs, R_028B38_VGT_GS_MAX_VERT_OUT,
4048 gs->info.gs.vertices_out);
4049 }
4050
4051 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade, bool float16)
4052 {
4053 uint32_t ps_input_cntl;
4054 if (offset <= AC_EXP_PARAM_OFFSET_31) {
4055 ps_input_cntl = S_028644_OFFSET(offset);
4056 if (flat_shade)
4057 ps_input_cntl |= S_028644_FLAT_SHADE(1);
4058 if (float16) {
4059 ps_input_cntl |= S_028644_FP16_INTERP_MODE(1) |
4060 S_028644_ATTR0_VALID(1);
4061 }
4062 } else {
4063 /* The input is a DEFAULT_VAL constant. */
4064 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
4065 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
4066 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
4067 ps_input_cntl = S_028644_OFFSET(0x20) |
4068 S_028644_DEFAULT_VAL(offset);
4069 }
4070 return ps_input_cntl;
4071 }
4072
4073 static void
4074 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf *ctx_cs,
4075 struct radv_pipeline *pipeline)
4076 {
4077 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4078 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
4079 uint32_t ps_input_cntl[32];
4080
4081 unsigned ps_offset = 0;
4082
4083 if (ps->info.ps.prim_id_input) {
4084 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
4085 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
4086 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false);
4087 ++ps_offset;
4088 }
4089 }
4090
4091 if (ps->info.ps.layer_input ||
4092 ps->info.needs_multiview_view_index) {
4093 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
4094 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
4095 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false);
4096 else
4097 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true, false);
4098 ++ps_offset;
4099 }
4100
4101 if (ps->info.ps.has_pcoord) {
4102 unsigned val;
4103 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
4104 ps_input_cntl[ps_offset] = val;
4105 ps_offset++;
4106 }
4107
4108 if (ps->info.ps.num_input_clips_culls) {
4109 unsigned vs_offset;
4110
4111 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST0];
4112 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
4113 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false);
4114 ++ps_offset;
4115 }
4116
4117 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST1];
4118 if (vs_offset != AC_EXP_PARAM_UNDEFINED &&
4119 ps->info.ps.num_input_clips_culls > 4) {
4120 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false);
4121 ++ps_offset;
4122 }
4123 }
4124
4125 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.ps.input_mask; ++i) {
4126 unsigned vs_offset;
4127 bool flat_shade;
4128 bool float16;
4129 if (!(ps->info.ps.input_mask & (1u << i)))
4130 continue;
4131
4132 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
4133 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
4134 ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
4135 ++ps_offset;
4136 continue;
4137 }
4138
4139 flat_shade = !!(ps->info.ps.flat_shaded_mask & (1u << ps_offset));
4140 float16 = !!(ps->info.ps.float16_shaded_mask & (1u << ps_offset));
4141
4142 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade, float16);
4143 ++ps_offset;
4144 }
4145
4146 if (ps_offset) {
4147 radeon_set_context_reg_seq(ctx_cs, R_028644_SPI_PS_INPUT_CNTL_0, ps_offset);
4148 for (unsigned i = 0; i < ps_offset; i++) {
4149 radeon_emit(ctx_cs, ps_input_cntl[i]);
4150 }
4151 }
4152 }
4153
4154 static uint32_t
4155 radv_compute_db_shader_control(const struct radv_device *device,
4156 const struct radv_pipeline *pipeline,
4157 const struct radv_shader_variant *ps)
4158 {
4159 unsigned z_order;
4160 if (ps->info.ps.early_fragment_test || !ps->info.ps.writes_memory)
4161 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
4162 else
4163 z_order = V_02880C_LATE_Z;
4164
4165 bool disable_rbplus = device->physical_device->rad_info.has_rbplus &&
4166 !device->physical_device->rad_info.rbplus_allowed;
4167
4168 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
4169 * but this appears to break Project Cars (DXVK). See
4170 * https://bugs.freedesktop.org/show_bug.cgi?id=109401
4171 */
4172 bool mask_export_enable = ps->info.ps.writes_sample_mask;
4173
4174 return S_02880C_Z_EXPORT_ENABLE(ps->info.ps.writes_z) |
4175 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.ps.writes_stencil) |
4176 S_02880C_KILL_ENABLE(!!ps->info.ps.can_discard) |
4177 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable) |
4178 S_02880C_Z_ORDER(z_order) |
4179 S_02880C_DEPTH_BEFORE_SHADER(ps->info.ps.early_fragment_test) |
4180 S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps->info.ps.post_depth_coverage) |
4181 S_02880C_EXEC_ON_HIER_FAIL(ps->info.ps.writes_memory) |
4182 S_02880C_EXEC_ON_NOOP(ps->info.ps.writes_memory) |
4183 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus);
4184 }
4185
4186 static void
4187 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf *ctx_cs,
4188 struct radeon_cmdbuf *cs,
4189 struct radv_pipeline *pipeline)
4190 {
4191 struct radv_shader_variant *ps;
4192 uint64_t va;
4193 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
4194
4195 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4196 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
4197
4198 radeon_set_sh_reg_seq(cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
4199 radeon_emit(cs, va >> 8);
4200 radeon_emit(cs, S_00B024_MEM_BASE(va >> 40));
4201 radeon_emit(cs, ps->config.rsrc1);
4202 radeon_emit(cs, ps->config.rsrc2);
4203
4204 radeon_set_context_reg(ctx_cs, R_02880C_DB_SHADER_CONTROL,
4205 radv_compute_db_shader_control(pipeline->device,
4206 pipeline, ps));
4207
4208 radeon_set_context_reg(ctx_cs, R_0286CC_SPI_PS_INPUT_ENA,
4209 ps->config.spi_ps_input_ena);
4210
4211 radeon_set_context_reg(ctx_cs, R_0286D0_SPI_PS_INPUT_ADDR,
4212 ps->config.spi_ps_input_addr);
4213
4214 radeon_set_context_reg(ctx_cs, R_0286D8_SPI_PS_IN_CONTROL,
4215 S_0286D8_NUM_INTERP(ps->info.ps.num_interp) |
4216 S_0286D8_PS_W32_EN(ps->info.wave_size == 32));
4217
4218 radeon_set_context_reg(ctx_cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl);
4219
4220 radeon_set_context_reg(ctx_cs, R_028710_SPI_SHADER_Z_FORMAT,
4221 ac_get_spi_shader_z_format(ps->info.ps.writes_z,
4222 ps->info.ps.writes_stencil,
4223 ps->info.ps.writes_sample_mask));
4224
4225 if (pipeline->device->dfsm_allowed) {
4226 /* optimise this? */
4227 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
4228 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
4229 }
4230 }
4231
4232 static void
4233 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf *ctx_cs,
4234 struct radv_pipeline *pipeline)
4235 {
4236 if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10 ||
4237 pipeline->device->physical_device->rad_info.chip_class >= GFX10)
4238 return;
4239
4240 unsigned vtx_reuse_depth = 30;
4241 if (radv_pipeline_has_tess(pipeline) &&
4242 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
4243 vtx_reuse_depth = 14;
4244 }
4245 radeon_set_context_reg(ctx_cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
4246 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth));
4247 }
4248
4249 static uint32_t
4250 radv_compute_vgt_shader_stages_en(const struct radv_pipeline *pipeline)
4251 {
4252 uint32_t stages = 0;
4253 if (radv_pipeline_has_tess(pipeline)) {
4254 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
4255 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
4256
4257 if (radv_pipeline_has_gs(pipeline))
4258 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
4259 S_028B54_GS_EN(1);
4260 else if (radv_pipeline_has_ngg(pipeline))
4261 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
4262 else
4263 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
4264 } else if (radv_pipeline_has_gs(pipeline)) {
4265 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
4266 S_028B54_GS_EN(1);
4267 } else if (radv_pipeline_has_ngg(pipeline)) {
4268 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
4269 }
4270
4271 if (radv_pipeline_has_ngg(pipeline)) {
4272 stages |= S_028B54_PRIMGEN_EN(1);
4273 if (pipeline->streamout_shader)
4274 stages |= S_028B54_NGG_WAVE_ID_EN(1);
4275 } else if (radv_pipeline_has_gs(pipeline)) {
4276 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
4277 }
4278
4279 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
4280 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
4281
4282 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4283 uint8_t hs_size = 64, gs_size = 64, vs_size = 64;
4284
4285 if (radv_pipeline_has_tess(pipeline))
4286 hs_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.wave_size;
4287
4288 if (pipeline->shaders[MESA_SHADER_GEOMETRY]) {
4289 vs_size = gs_size = pipeline->shaders[MESA_SHADER_GEOMETRY]->info.wave_size;
4290 if (pipeline->gs_copy_shader)
4291 vs_size = pipeline->gs_copy_shader->info.wave_size;
4292 } else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
4293 vs_size = pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.wave_size;
4294 else if (pipeline->shaders[MESA_SHADER_VERTEX])
4295 vs_size = pipeline->shaders[MESA_SHADER_VERTEX]->info.wave_size;
4296
4297 if (radv_pipeline_has_ngg(pipeline))
4298 gs_size = vs_size;
4299
4300 /* legacy GS only supports Wave64 */
4301 stages |= S_028B54_HS_W32_EN(hs_size == 32 ? 1 : 0) |
4302 S_028B54_GS_W32_EN(gs_size == 32 ? 1 : 0) |
4303 S_028B54_VS_W32_EN(vs_size == 32 ? 1 : 0);
4304 }
4305
4306 return stages;
4307 }
4308
4309 static uint32_t
4310 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo *pCreateInfo)
4311 {
4312 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
4313 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
4314
4315 if (!discard_rectangle_info)
4316 return 0xffff;
4317
4318 unsigned mask = 0;
4319
4320 for (unsigned i = 0; i < (1u << MAX_DISCARD_RECTANGLES); ++i) {
4321 /* Interpret i as a bitmask, and then set the bit in the mask if
4322 * that combination of rectangles in which the pixel is contained
4323 * should pass the cliprect test. */
4324 unsigned relevant_subset = i & ((1u << discard_rectangle_info->discardRectangleCount) - 1);
4325
4326 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT &&
4327 !relevant_subset)
4328 continue;
4329
4330 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT &&
4331 relevant_subset)
4332 continue;
4333
4334 mask |= 1u << i;
4335 }
4336
4337 return mask;
4338 }
4339
4340 static void
4341 gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf *ctx_cs,
4342 struct radv_pipeline *pipeline,
4343 const struct radv_tessellation_state *tess)
4344 {
4345 bool break_wave_at_eoi = false;
4346 unsigned primgroup_size;
4347 unsigned vertgroup_size;
4348
4349 if (radv_pipeline_has_tess(pipeline)) {
4350 primgroup_size = tess->num_patches; /* must be a multiple of NUM_PATCHES */
4351 vertgroup_size = 0;
4352 } else if (radv_pipeline_has_gs(pipeline)) {
4353 const struct gfx9_gs_info *gs_state =
4354 &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs_ring_info;
4355 unsigned vgt_gs_onchip_cntl = gs_state->vgt_gs_onchip_cntl;
4356 primgroup_size = G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl);
4357 vertgroup_size = G_028A44_ES_VERTS_PER_SUBGRP(vgt_gs_onchip_cntl);
4358 } else {
4359 primgroup_size = 128; /* recommended without a GS and tess */
4360 vertgroup_size = 0;
4361 }
4362
4363 if (radv_pipeline_has_tess(pipeline)) {
4364 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
4365 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.uses_prim_id)
4366 break_wave_at_eoi = true;
4367 }
4368
4369 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL,
4370 S_03096C_PRIM_GRP_SIZE(primgroup_size) |
4371 S_03096C_VERT_GRP_SIZE(vertgroup_size) |
4372 S_03096C_PACKET_TO_ONE_PA(0) /* line stipple */ |
4373 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi));
4374 }
4375
4376 static void
4377 radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
4378 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4379 const struct radv_graphics_pipeline_create_info *extra,
4380 const struct radv_blend_state *blend,
4381 const struct radv_tessellation_state *tess,
4382 unsigned prim, unsigned gs_out)
4383 {
4384 struct radeon_cmdbuf *ctx_cs = &pipeline->ctx_cs;
4385 struct radeon_cmdbuf *cs = &pipeline->cs;
4386
4387 cs->max_dw = 64;
4388 ctx_cs->max_dw = 256;
4389 cs->buf = malloc(4 * (cs->max_dw + ctx_cs->max_dw));
4390 ctx_cs->buf = cs->buf + cs->max_dw;
4391
4392 radv_pipeline_generate_depth_stencil_state(ctx_cs, pipeline, pCreateInfo, extra);
4393 radv_pipeline_generate_blend_state(ctx_cs, pipeline, blend);
4394 radv_pipeline_generate_raster_state(ctx_cs, pipeline, pCreateInfo);
4395 radv_pipeline_generate_multisample_state(ctx_cs, pipeline);
4396 radv_pipeline_generate_vgt_gs_mode(ctx_cs, pipeline);
4397 radv_pipeline_generate_vertex_shader(ctx_cs, cs, pipeline, tess);
4398 radv_pipeline_generate_tess_shaders(ctx_cs, cs, pipeline, tess);
4399 radv_pipeline_generate_geometry_shader(ctx_cs, cs, pipeline);
4400 radv_pipeline_generate_fragment_shader(ctx_cs, cs, pipeline);
4401 radv_pipeline_generate_ps_inputs(ctx_cs, pipeline);
4402 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs, pipeline);
4403 radv_pipeline_generate_binning_state(ctx_cs, pipeline, pCreateInfo);
4404
4405 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 && !radv_pipeline_has_ngg(pipeline))
4406 gfx10_pipeline_generate_ge_cntl(ctx_cs, pipeline, tess);
4407
4408 radeon_set_context_reg(ctx_cs, R_0286E8_SPI_TMPRING_SIZE,
4409 S_0286E8_WAVES(pipeline->max_waves) |
4410 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
4411
4412 radeon_set_context_reg(ctx_cs, R_028B54_VGT_SHADER_STAGES_EN, radv_compute_vgt_shader_stages_en(pipeline));
4413
4414 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
4415 radeon_set_uconfig_reg_idx(pipeline->device->physical_device,
4416 cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
4417 } else {
4418 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
4419 }
4420 radeon_set_context_reg(ctx_cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out);
4421
4422 radeon_set_context_reg(ctx_cs, R_02820C_PA_SC_CLIPRECT_RULE, radv_compute_cliprect_rule(pCreateInfo));
4423
4424 pipeline->ctx_cs_hash = _mesa_hash_data(ctx_cs->buf, ctx_cs->cdw * 4);
4425
4426 assert(ctx_cs->cdw <= ctx_cs->max_dw);
4427 assert(cs->cdw <= cs->max_dw);
4428 }
4429
4430 static struct radv_ia_multi_vgt_param_helpers
4431 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
4432 const struct radv_tessellation_state *tess,
4433 uint32_t prim)
4434 {
4435 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param = {0};
4436 const struct radv_device *device = pipeline->device;
4437
4438 if (radv_pipeline_has_tess(pipeline))
4439 ia_multi_vgt_param.primgroup_size = tess->num_patches;
4440 else if (radv_pipeline_has_gs(pipeline))
4441 ia_multi_vgt_param.primgroup_size = 64;
4442 else
4443 ia_multi_vgt_param.primgroup_size = 128; /* recommended without a GS */
4444
4445 /* GS requirement. */
4446 ia_multi_vgt_param.partial_es_wave = false;
4447 if (radv_pipeline_has_gs(pipeline) && device->physical_device->rad_info.chip_class <= GFX8)
4448 if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3)
4449 ia_multi_vgt_param.partial_es_wave = true;
4450
4451 ia_multi_vgt_param.wd_switch_on_eop = false;
4452 if (device->physical_device->rad_info.chip_class >= GFX7) {
4453 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
4454 * 4 shader engines. Set 1 to pass the assertion below.
4455 * The other cases are hardware requirements. */
4456 if (device->physical_device->rad_info.max_se < 4 ||
4457 prim == V_008958_DI_PT_POLYGON ||
4458 prim == V_008958_DI_PT_LINELOOP ||
4459 prim == V_008958_DI_PT_TRIFAN ||
4460 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
4461 (pipeline->graphics.prim_restart_enable &&
4462 (device->physical_device->rad_info.family < CHIP_POLARIS10 ||
4463 (prim != V_008958_DI_PT_POINTLIST &&
4464 prim != V_008958_DI_PT_LINESTRIP))))
4465 ia_multi_vgt_param.wd_switch_on_eop = true;
4466 }
4467
4468 ia_multi_vgt_param.ia_switch_on_eoi = false;
4469 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.prim_id_input)
4470 ia_multi_vgt_param.ia_switch_on_eoi = true;
4471 if (radv_pipeline_has_gs(pipeline) &&
4472 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.uses_prim_id)
4473 ia_multi_vgt_param.ia_switch_on_eoi = true;
4474 if (radv_pipeline_has_tess(pipeline)) {
4475 /* SWITCH_ON_EOI must be set if PrimID is used. */
4476 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
4477 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.uses_prim_id)
4478 ia_multi_vgt_param.ia_switch_on_eoi = true;
4479 }
4480
4481 ia_multi_vgt_param.partial_vs_wave = false;
4482 if (radv_pipeline_has_tess(pipeline)) {
4483 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
4484 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
4485 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
4486 device->physical_device->rad_info.family == CHIP_BONAIRE) &&
4487 radv_pipeline_has_gs(pipeline))
4488 ia_multi_vgt_param.partial_vs_wave = true;
4489 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
4490 if (device->physical_device->rad_info.has_distributed_tess) {
4491 if (radv_pipeline_has_gs(pipeline)) {
4492 if (device->physical_device->rad_info.chip_class <= GFX8)
4493 ia_multi_vgt_param.partial_es_wave = true;
4494 } else {
4495 ia_multi_vgt_param.partial_vs_wave = true;
4496 }
4497 }
4498 }
4499
4500 /* Workaround for a VGT hang when strip primitive types are used with
4501 * primitive restart.
4502 */
4503 if (pipeline->graphics.prim_restart_enable &&
4504 (prim == V_008958_DI_PT_LINESTRIP ||
4505 prim == V_008958_DI_PT_TRISTRIP ||
4506 prim == V_008958_DI_PT_LINESTRIP_ADJ ||
4507 prim == V_008958_DI_PT_TRISTRIP_ADJ)) {
4508 ia_multi_vgt_param.partial_vs_wave = true;
4509 }
4510
4511 if (radv_pipeline_has_gs(pipeline)) {
4512 /* On these chips there is the possibility of a hang if the
4513 * pipeline uses a GS and partial_vs_wave is not set.
4514 *
4515 * This mostly does not hit 4-SE chips, as those typically set
4516 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
4517 * with GS due to another workaround.
4518 *
4519 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
4520 */
4521 if (device->physical_device->rad_info.family == CHIP_TONGA ||
4522 device->physical_device->rad_info.family == CHIP_FIJI ||
4523 device->physical_device->rad_info.family == CHIP_POLARIS10 ||
4524 device->physical_device->rad_info.family == CHIP_POLARIS11 ||
4525 device->physical_device->rad_info.family == CHIP_POLARIS12 ||
4526 device->physical_device->rad_info.family == CHIP_VEGAM) {
4527 ia_multi_vgt_param.partial_vs_wave = true;
4528 }
4529 }
4530
4531 ia_multi_vgt_param.base =
4532 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param.primgroup_size - 1) |
4533 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
4534 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == GFX8 ? 2 : 0) |
4535 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
4536 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
4537
4538 return ia_multi_vgt_param;
4539 }
4540
4541
4542 static void
4543 radv_compute_vertex_input_state(struct radv_pipeline *pipeline,
4544 const VkGraphicsPipelineCreateInfo *pCreateInfo)
4545 {
4546 const VkPipelineVertexInputStateCreateInfo *vi_info =
4547 pCreateInfo->pVertexInputState;
4548 struct radv_vertex_elements_info *velems = &pipeline->vertex_elements;
4549
4550 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
4551 const VkVertexInputAttributeDescription *desc =
4552 &vi_info->pVertexAttributeDescriptions[i];
4553 unsigned loc = desc->location;
4554 const struct vk_format_description *format_desc;
4555
4556 format_desc = vk_format_description(desc->format);
4557
4558 velems->format_size[loc] = format_desc->block.bits / 8;
4559 }
4560
4561 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
4562 const VkVertexInputBindingDescription *desc =
4563 &vi_info->pVertexBindingDescriptions[i];
4564
4565 pipeline->binding_stride[desc->binding] = desc->stride;
4566 pipeline->num_vertex_bindings =
4567 MAX2(pipeline->num_vertex_bindings, desc->binding + 1);
4568 }
4569 }
4570
4571 static struct radv_shader_variant *
4572 radv_pipeline_get_streamout_shader(struct radv_pipeline *pipeline)
4573 {
4574 int i;
4575
4576 for (i = MESA_SHADER_GEOMETRY; i >= MESA_SHADER_VERTEX; i--) {
4577 struct radv_shader_variant *shader =
4578 radv_get_shader(pipeline, i);
4579
4580 if (shader && shader->info.so.num_outputs > 0)
4581 return shader;
4582 }
4583
4584 return NULL;
4585 }
4586
4587 static VkResult
4588 radv_pipeline_init(struct radv_pipeline *pipeline,
4589 struct radv_device *device,
4590 struct radv_pipeline_cache *cache,
4591 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4592 const struct radv_graphics_pipeline_create_info *extra)
4593 {
4594 VkResult result;
4595 bool has_view_index = false;
4596
4597 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
4598 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
4599 if (subpass->view_mask)
4600 has_view_index = true;
4601
4602 pipeline->device = device;
4603 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
4604 assert(pipeline->layout);
4605
4606 struct radv_blend_state blend = radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
4607
4608 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
4609 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
4610 radv_init_feedback(creation_feedback);
4611
4612 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
4613
4614 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
4615 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
4616 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
4617 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
4618 pStages[stage] = &pCreateInfo->pStages[i];
4619 if(creation_feedback)
4620 stage_feedbacks[stage] = &creation_feedback->pPipelineStageCreationFeedbacks[i];
4621 }
4622
4623 struct radv_pipeline_key key = radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &blend, has_view_index);
4624 radv_create_shaders(pipeline, device, cache, &key, pStages, pCreateInfo->flags, pCreateInfo, pipeline_feedback, stage_feedbacks);
4625
4626 pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
4627 radv_pipeline_init_multisample_state(pipeline, &blend, pCreateInfo);
4628 uint32_t gs_out;
4629 uint32_t prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
4630
4631 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
4632
4633 if (radv_pipeline_has_gs(pipeline)) {
4634 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
4635 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
4636 } else if (radv_pipeline_has_tess(pipeline)) {
4637 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.point_mode)
4638 gs_out = V_028A6C_OUTPRIM_TYPE_POINTLIST;
4639 else
4640 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.primitive_mode);
4641 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
4642 } else {
4643 gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
4644 }
4645 if (extra && extra->use_rectlist) {
4646 prim = V_008958_DI_PT_RECTLIST;
4647 gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
4648 pipeline->graphics.can_use_guardband = true;
4649 if (radv_pipeline_has_ngg(pipeline))
4650 gs_out = V_028A6C_VGT_OUT_RECT_V0;
4651 }
4652 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
4653 /* prim vertex count will need TESS changes */
4654 pipeline->graphics.prim_vertex_count = prim_size_table[prim];
4655
4656 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
4657
4658 /* Ensure that some export memory is always allocated, for two reasons:
4659 *
4660 * 1) Correctness: The hardware ignores the EXEC mask if no export
4661 * memory is allocated, so KILL and alpha test do not work correctly
4662 * without this.
4663 * 2) Performance: Every shader needs at least a NULL export, even when
4664 * it writes no color/depth output. The NULL export instruction
4665 * stalls without this setting.
4666 *
4667 * Don't add this to CB_SHADER_MASK.
4668 *
4669 * GFX10 supports pixel shaders without exports by setting both the
4670 * color and Z formats to SPI_SHADER_ZERO. The hw will skip export
4671 * instructions if any are present.
4672 */
4673 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4674 if ((pipeline->device->physical_device->rad_info.chip_class <= GFX9 ||
4675 ps->info.ps.can_discard) &&
4676 !blend.spi_shader_col_format) {
4677 if (!ps->info.ps.writes_z &&
4678 !ps->info.ps.writes_stencil &&
4679 !ps->info.ps.writes_sample_mask)
4680 blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
4681 }
4682
4683 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
4684 if (pipeline->shaders[i]) {
4685 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
4686 }
4687 }
4688
4689 if (radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) {
4690 struct radv_shader_variant *gs =
4691 pipeline->shaders[MESA_SHADER_GEOMETRY];
4692
4693 calculate_gs_ring_sizes(pipeline, &gs->info.gs_ring_info);
4694 }
4695
4696 struct radv_tessellation_state tess = {0};
4697 if (radv_pipeline_has_tess(pipeline)) {
4698 if (prim == V_008958_DI_PT_PATCH) {
4699 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
4700 pipeline->graphics.prim_vertex_count.incr = 1;
4701 }
4702 tess = calculate_tess_state(pipeline, pCreateInfo);
4703 }
4704
4705 pipeline->graphics.ia_multi_vgt_param = radv_compute_ia_multi_vgt_param_helpers(pipeline, &tess, prim);
4706
4707 radv_compute_vertex_input_state(pipeline, pCreateInfo);
4708
4709 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
4710 pipeline->user_data_0[i] = radv_pipeline_stage_to_user_data_0(pipeline, i, device->physical_device->rad_info.chip_class);
4711
4712 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
4713 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
4714 if (loc->sgpr_idx != -1) {
4715 pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX];
4716 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
4717 if (radv_get_shader(pipeline, MESA_SHADER_VERTEX)->info.vs.needs_draw_id)
4718 pipeline->graphics.vtx_emit_num = 3;
4719 else
4720 pipeline->graphics.vtx_emit_num = 2;
4721 }
4722
4723 /* Find the last vertex shader stage that eventually uses streamout. */
4724 pipeline->streamout_shader = radv_pipeline_get_streamout_shader(pipeline);
4725
4726 result = radv_pipeline_scratch_init(device, pipeline);
4727 radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend, &tess, prim, gs_out);
4728
4729 return result;
4730 }
4731
4732 VkResult
4733 radv_graphics_pipeline_create(
4734 VkDevice _device,
4735 VkPipelineCache _cache,
4736 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4737 const struct radv_graphics_pipeline_create_info *extra,
4738 const VkAllocationCallbacks *pAllocator,
4739 VkPipeline *pPipeline)
4740 {
4741 RADV_FROM_HANDLE(radv_device, device, _device);
4742 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
4743 struct radv_pipeline *pipeline;
4744 VkResult result;
4745
4746 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
4747 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4748 if (pipeline == NULL)
4749 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4750
4751 result = radv_pipeline_init(pipeline, device, cache,
4752 pCreateInfo, extra);
4753 if (result != VK_SUCCESS) {
4754 radv_pipeline_destroy(device, pipeline, pAllocator);
4755 return result;
4756 }
4757
4758 *pPipeline = radv_pipeline_to_handle(pipeline);
4759
4760 return VK_SUCCESS;
4761 }
4762
4763 VkResult radv_CreateGraphicsPipelines(
4764 VkDevice _device,
4765 VkPipelineCache pipelineCache,
4766 uint32_t count,
4767 const VkGraphicsPipelineCreateInfo* pCreateInfos,
4768 const VkAllocationCallbacks* pAllocator,
4769 VkPipeline* pPipelines)
4770 {
4771 VkResult result = VK_SUCCESS;
4772 unsigned i = 0;
4773
4774 for (; i < count; i++) {
4775 VkResult r;
4776 r = radv_graphics_pipeline_create(_device,
4777 pipelineCache,
4778 &pCreateInfos[i],
4779 NULL, pAllocator, &pPipelines[i]);
4780 if (r != VK_SUCCESS) {
4781 result = r;
4782 pPipelines[i] = VK_NULL_HANDLE;
4783 }
4784 }
4785
4786 return result;
4787 }
4788
4789
4790 static void
4791 radv_compute_generate_pm4(struct radv_pipeline *pipeline)
4792 {
4793 struct radv_shader_variant *compute_shader;
4794 struct radv_device *device = pipeline->device;
4795 unsigned threads_per_threadgroup;
4796 unsigned threadgroups_per_cu = 1;
4797 unsigned waves_per_threadgroup;
4798 unsigned max_waves_per_sh = 0;
4799 uint64_t va;
4800
4801 pipeline->cs.buf = malloc(20 * 4);
4802 pipeline->cs.max_dw = 20;
4803
4804 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
4805 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
4806
4807 radeon_set_sh_reg_seq(&pipeline->cs, R_00B830_COMPUTE_PGM_LO, 2);
4808 radeon_emit(&pipeline->cs, va >> 8);
4809 radeon_emit(&pipeline->cs, S_00B834_DATA(va >> 40));
4810
4811 radeon_set_sh_reg_seq(&pipeline->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
4812 radeon_emit(&pipeline->cs, compute_shader->config.rsrc1);
4813 radeon_emit(&pipeline->cs, compute_shader->config.rsrc2);
4814
4815 radeon_set_sh_reg(&pipeline->cs, R_00B860_COMPUTE_TMPRING_SIZE,
4816 S_00B860_WAVES(pipeline->max_waves) |
4817 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
4818
4819 /* Calculate best compute resource limits. */
4820 threads_per_threadgroup = compute_shader->info.cs.block_size[0] *
4821 compute_shader->info.cs.block_size[1] *
4822 compute_shader->info.cs.block_size[2];
4823 waves_per_threadgroup = DIV_ROUND_UP(threads_per_threadgroup,
4824 device->physical_device->cs_wave_size);
4825
4826 if (device->physical_device->rad_info.chip_class >= GFX10 &&
4827 waves_per_threadgroup == 1)
4828 threadgroups_per_cu = 2;
4829
4830 radeon_set_sh_reg(&pipeline->cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
4831 ac_get_compute_resource_limits(&device->physical_device->rad_info,
4832 waves_per_threadgroup,
4833 max_waves_per_sh,
4834 threadgroups_per_cu));
4835
4836 radeon_set_sh_reg_seq(&pipeline->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
4837 radeon_emit(&pipeline->cs,
4838 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
4839 radeon_emit(&pipeline->cs,
4840 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
4841 radeon_emit(&pipeline->cs,
4842 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
4843
4844 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
4845 }
4846
4847 static VkResult radv_compute_pipeline_create(
4848 VkDevice _device,
4849 VkPipelineCache _cache,
4850 const VkComputePipelineCreateInfo* pCreateInfo,
4851 const VkAllocationCallbacks* pAllocator,
4852 VkPipeline* pPipeline)
4853 {
4854 RADV_FROM_HANDLE(radv_device, device, _device);
4855 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
4856 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
4857 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
4858 struct radv_pipeline *pipeline;
4859 VkResult result;
4860
4861 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
4862 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4863 if (pipeline == NULL)
4864 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4865
4866 pipeline->device = device;
4867 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
4868 assert(pipeline->layout);
4869
4870 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
4871 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
4872 radv_init_feedback(creation_feedback);
4873
4874 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
4875 if (creation_feedback)
4876 stage_feedbacks[MESA_SHADER_COMPUTE] = &creation_feedback->pPipelineStageCreationFeedbacks[0];
4877
4878 pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
4879 radv_create_shaders(pipeline, device, cache, &(struct radv_pipeline_key) {0}, pStages, pCreateInfo->flags, NULL, pipeline_feedback, stage_feedbacks);
4880
4881 pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
4882 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
4883 result = radv_pipeline_scratch_init(device, pipeline);
4884 if (result != VK_SUCCESS) {
4885 radv_pipeline_destroy(device, pipeline, pAllocator);
4886 return result;
4887 }
4888
4889 radv_compute_generate_pm4(pipeline);
4890
4891 *pPipeline = radv_pipeline_to_handle(pipeline);
4892
4893 return VK_SUCCESS;
4894 }
4895
4896 VkResult radv_CreateComputePipelines(
4897 VkDevice _device,
4898 VkPipelineCache pipelineCache,
4899 uint32_t count,
4900 const VkComputePipelineCreateInfo* pCreateInfos,
4901 const VkAllocationCallbacks* pAllocator,
4902 VkPipeline* pPipelines)
4903 {
4904 VkResult result = VK_SUCCESS;
4905
4906 unsigned i = 0;
4907 for (; i < count; i++) {
4908 VkResult r;
4909 r = radv_compute_pipeline_create(_device, pipelineCache,
4910 &pCreateInfos[i],
4911 pAllocator, &pPipelines[i]);
4912 if (r != VK_SUCCESS) {
4913 result = r;
4914 pPipelines[i] = VK_NULL_HANDLE;
4915 }
4916 }
4917
4918 return result;
4919 }
4920
4921
4922 static uint32_t radv_get_executable_count(const struct radv_pipeline *pipeline)
4923 {
4924 uint32_t ret = 0;
4925 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
4926 if (pipeline->shaders[i])
4927 ret += i == MESA_SHADER_GEOMETRY ? 2u : 1u;
4928
4929 }
4930 return ret;
4931 }
4932
4933 static struct radv_shader_variant *
4934 radv_get_shader_from_executable_index(const struct radv_pipeline *pipeline, int index, gl_shader_stage *stage)
4935 {
4936 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
4937 if (!pipeline->shaders[i])
4938 continue;
4939 if (!index) {
4940 *stage = i;
4941 return pipeline->shaders[i];
4942 }
4943
4944 --index;
4945
4946 if (i == MESA_SHADER_GEOMETRY) {
4947 if (!index) {
4948 *stage = i;
4949 return pipeline->gs_copy_shader;
4950 }
4951 --index;
4952 }
4953 }
4954
4955 *stage = -1;
4956 return NULL;
4957 }
4958
4959 /* Basically strlcpy (which does not exist on linux) specialized for
4960 * descriptions. */
4961 static void desc_copy(char *desc, const char *src) {
4962 int len = strlen(src);
4963 assert(len < VK_MAX_DESCRIPTION_SIZE);
4964 memcpy(desc, src, len);
4965 memset(desc + len, 0, VK_MAX_DESCRIPTION_SIZE - len);
4966 }
4967
4968 VkResult radv_GetPipelineExecutablePropertiesKHR(
4969 VkDevice _device,
4970 const VkPipelineInfoKHR* pPipelineInfo,
4971 uint32_t* pExecutableCount,
4972 VkPipelineExecutablePropertiesKHR* pProperties)
4973 {
4974 RADV_FROM_HANDLE(radv_pipeline, pipeline, pPipelineInfo->pipeline);
4975 const uint32_t total_count = radv_get_executable_count(pipeline);
4976
4977 if (!pProperties) {
4978 *pExecutableCount = total_count;
4979 return VK_SUCCESS;
4980 }
4981
4982 const uint32_t count = MIN2(total_count, *pExecutableCount);
4983 for (unsigned i = 0, executable_idx = 0;
4984 i < MESA_SHADER_STAGES && executable_idx < count; ++i) {
4985 if (!pipeline->shaders[i])
4986 continue;
4987 pProperties[executable_idx].stages = mesa_to_vk_shader_stage(i);
4988 const char *name = NULL;
4989 const char *description = NULL;
4990 switch(i) {
4991 case MESA_SHADER_VERTEX:
4992 name = "Vertex Shader";
4993 description = "Vulkan Vertex Shader";
4994 break;
4995 case MESA_SHADER_TESS_CTRL:
4996 if (!pipeline->shaders[MESA_SHADER_VERTEX]) {
4997 pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT;
4998 name = "Vertex + Tessellation Control Shaders";
4999 description = "Combined Vulkan Vertex and Tessellation Control Shaders";
5000 } else {
5001 name = "Tessellation Control Shader";
5002 description = "Vulkan Tessellation Control Shader";
5003 }
5004 break;
5005 case MESA_SHADER_TESS_EVAL:
5006 name = "Tessellation Evaluation Shader";
5007 description = "Vulkan Tessellation Evaluation Shader";
5008 break;
5009 case MESA_SHADER_GEOMETRY:
5010 if (radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_TESS_EVAL]) {
5011 pProperties[executable_idx].stages |= VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT;
5012 name = "Tessellation Evaluation + Geometry Shaders";
5013 description = "Combined Vulkan Tessellation Evaluation and Geometry Shaders";
5014 } else if (!radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_VERTEX]) {
5015 pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT;
5016 name = "Vertex + Geometry Shader";
5017 description = "Combined Vulkan Vertex and Geometry Shaders";
5018 } else {
5019 name = "Geometry Shader";
5020 description = "Vulkan Geometry Shader";
5021 }
5022 break;
5023 case MESA_SHADER_FRAGMENT:
5024 name = "Fragment Shader";
5025 description = "Vulkan Fragment Shader";
5026 break;
5027 case MESA_SHADER_COMPUTE:
5028 name = "Compute Shader";
5029 description = "Vulkan Compute Shader";
5030 break;
5031 }
5032
5033 desc_copy(pProperties[executable_idx].name, name);
5034 desc_copy(pProperties[executable_idx].description, description);
5035
5036 ++executable_idx;
5037 if (i == MESA_SHADER_GEOMETRY) {
5038 assert(pipeline->gs_copy_shader);
5039 if (executable_idx >= count)
5040 break;
5041
5042 pProperties[executable_idx].stages = VK_SHADER_STAGE_GEOMETRY_BIT;
5043 desc_copy(pProperties[executable_idx].name, "GS Copy Shader");
5044 desc_copy(pProperties[executable_idx].description,
5045 "Extra shader stage that loads the GS output ringbuffer into the rasterizer");
5046
5047 ++executable_idx;
5048 }
5049 }
5050
5051 for (unsigned i = 0; i < count; ++i)
5052 pProperties[i].subgroupSize = 64;
5053
5054 VkResult result = *pExecutableCount < total_count ? VK_INCOMPLETE : VK_SUCCESS;
5055 *pExecutableCount = count;
5056 return result;
5057 }
5058
5059 VkResult radv_GetPipelineExecutableStatisticsKHR(
5060 VkDevice _device,
5061 const VkPipelineExecutableInfoKHR* pExecutableInfo,
5062 uint32_t* pStatisticCount,
5063 VkPipelineExecutableStatisticKHR* pStatistics)
5064 {
5065 RADV_FROM_HANDLE(radv_device, device, _device);
5066 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
5067 gl_shader_stage stage;
5068 struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
5069
5070 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
5071 unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
5072 unsigned max_waves = radv_get_max_waves(device, shader, stage);
5073
5074 VkPipelineExecutableStatisticKHR *s = pStatistics;
5075 VkPipelineExecutableStatisticKHR *end = s + (pStatistics ? *pStatisticCount : 0);
5076 VkResult result = VK_SUCCESS;
5077
5078 if (s < end) {
5079 desc_copy(s->name, "SGPRs");
5080 desc_copy(s->description, "Number of SGPR registers allocated per subgroup");
5081 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5082 s->value.u64 = shader->config.num_sgprs;
5083 }
5084 ++s;
5085
5086 if (s < end) {
5087 desc_copy(s->name, "VGPRs");
5088 desc_copy(s->description, "Number of VGPR registers allocated per subgroup");
5089 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5090 s->value.u64 = shader->config.num_vgprs;
5091 }
5092 ++s;
5093
5094 if (s < end) {
5095 desc_copy(s->name, "Spilled SGPRs");
5096 desc_copy(s->description, "Number of SGPR registers spilled per subgroup");
5097 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5098 s->value.u64 = shader->config.spilled_sgprs;
5099 }
5100 ++s;
5101
5102 if (s < end) {
5103 desc_copy(s->name, "Spilled VGPRs");
5104 desc_copy(s->description, "Number of VGPR registers spilled per subgroup");
5105 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5106 s->value.u64 = shader->config.spilled_vgprs;
5107 }
5108 ++s;
5109
5110 if (s < end) {
5111 desc_copy(s->name, "PrivMem VGPRs");
5112 desc_copy(s->description, "Number of VGPRs stored in private memory per subgroup");
5113 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5114 s->value.u64 = shader->info.private_mem_vgprs;
5115 }
5116 ++s;
5117
5118 if (s < end) {
5119 desc_copy(s->name, "Code size");
5120 desc_copy(s->description, "Code size in bytes");
5121 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5122 s->value.u64 = shader->exec_size;
5123 }
5124 ++s;
5125
5126 if (s < end) {
5127 desc_copy(s->name, "LDS size");
5128 desc_copy(s->description, "LDS size in bytes per workgroup");
5129 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5130 s->value.u64 = shader->config.lds_size * lds_increment;
5131 }
5132 ++s;
5133
5134 if (s < end) {
5135 desc_copy(s->name, "Scratch size");
5136 desc_copy(s->description, "Private memory in bytes per subgroup");
5137 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5138 s->value.u64 = shader->config.scratch_bytes_per_wave;
5139 }
5140 ++s;
5141
5142 if (s < end) {
5143 desc_copy(s->name, "Subgroups per SIMD");
5144 desc_copy(s->description, "The maximum number of subgroups in flight on a SIMD unit");
5145 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5146 s->value.u64 = max_waves;
5147 }
5148 ++s;
5149
5150 if (!pStatistics)
5151 *pStatisticCount = s - pStatistics;
5152 else if (s > end) {
5153 *pStatisticCount = end - pStatistics;
5154 result = VK_INCOMPLETE;
5155 } else {
5156 *pStatisticCount = s - pStatistics;
5157 }
5158
5159 return result;
5160 }
5161
5162 static VkResult radv_copy_representation(void *data, size_t *data_size, const char *src)
5163 {
5164 size_t total_size = strlen(src) + 1;
5165
5166 if (!data) {
5167 *data_size = total_size;
5168 return VK_SUCCESS;
5169 }
5170
5171 size_t size = MIN2(total_size, *data_size);
5172
5173 memcpy(data, src, size);
5174 if (size)
5175 *((char*)data + size - 1) = 0;
5176 return size < total_size ? VK_INCOMPLETE : VK_SUCCESS;
5177 }
5178
5179 VkResult radv_GetPipelineExecutableInternalRepresentationsKHR(
5180 VkDevice device,
5181 const VkPipelineExecutableInfoKHR* pExecutableInfo,
5182 uint32_t* pInternalRepresentationCount,
5183 VkPipelineExecutableInternalRepresentationKHR* pInternalRepresentations)
5184 {
5185 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
5186 gl_shader_stage stage;
5187 struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
5188
5189 VkPipelineExecutableInternalRepresentationKHR *p = pInternalRepresentations;
5190 VkPipelineExecutableInternalRepresentationKHR *end = p + (pInternalRepresentations ? *pInternalRepresentationCount : 0);
5191 VkResult result = VK_SUCCESS;
5192 /* optimized NIR */
5193 if (p < end) {
5194 p->isText = true;
5195 desc_copy(p->name, "NIR Shader(s)");
5196 desc_copy(p->description, "The optimized NIR shader(s)");
5197 if (radv_copy_representation(p->pData, &p->dataSize, shader->nir_string) != VK_SUCCESS)
5198 result = VK_INCOMPLETE;
5199 }
5200 ++p;
5201
5202 /* LLVM IR */
5203 if (p < end) {
5204 p->isText = true;
5205 desc_copy(p->name, "LLVM IR");
5206 desc_copy(p->description, "The LLVM IR after some optimizations");
5207 if (radv_copy_representation(p->pData, &p->dataSize, shader->llvm_ir_string) != VK_SUCCESS)
5208 result = VK_INCOMPLETE;
5209 }
5210 ++p;
5211
5212 /* Disassembler */
5213 if (p < end) {
5214 p->isText = true;
5215 desc_copy(p->name, "Assembly");
5216 desc_copy(p->description, "Final Assembly");
5217 if (radv_copy_representation(p->pData, &p->dataSize, shader->disasm_string) != VK_SUCCESS)
5218 result = VK_INCOMPLETE;
5219 }
5220 ++p;
5221
5222 if (!pInternalRepresentations)
5223 *pInternalRepresentationCount = p - pInternalRepresentations;
5224 else if(p > end) {
5225 result = VK_INCOMPLETE;
5226 *pInternalRepresentationCount = end - pInternalRepresentations;
5227 } else {
5228 *pInternalRepresentationCount = p - pInternalRepresentations;
5229 }
5230
5231 return result;
5232 }