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radv/gfx10: fix primitive indices orientation for NGG GS
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/disk_cache.h"
29 #include "util/mesa-sha1.h"
30 #include "util/u_atomic.h"
31 #include "radv_debug.h"
32 #include "radv_private.h"
33 #include "radv_cs.h"
34 #include "radv_shader.h"
35 #include "nir/nir.h"
36 #include "nir/nir_builder.h"
37 #include "nir/nir_xfb_info.h"
38 #include "spirv/nir_spirv.h"
39 #include "vk_util.h"
40
41 #include <llvm-c/Core.h>
42 #include <llvm-c/TargetMachine.h>
43
44 #include "sid.h"
45 #include "ac_binary.h"
46 #include "ac_llvm_util.h"
47 #include "ac_nir_to_llvm.h"
48 #include "vk_format.h"
49 #include "util/debug.h"
50 #include "ac_exp_param.h"
51 #include "ac_shader_util.h"
52 #include "main/menums.h"
53
54 struct radv_blend_state {
55 uint32_t blend_enable_4bit;
56 uint32_t need_src_alpha;
57
58 uint32_t cb_color_control;
59 uint32_t cb_target_mask;
60 uint32_t cb_target_enabled_4bit;
61 uint32_t sx_mrt_blend_opt[8];
62 uint32_t cb_blend_control[8];
63
64 uint32_t spi_shader_col_format;
65 uint32_t cb_shader_mask;
66 uint32_t db_alpha_to_mask;
67
68 uint32_t commutative_4bit;
69
70 bool single_cb_enable;
71 bool mrt0_is_dual_src;
72 };
73
74 struct radv_dsa_order_invariance {
75 /* Whether the final result in Z/S buffers is guaranteed to be
76 * invariant under changes to the order in which fragments arrive.
77 */
78 bool zs;
79
80 /* Whether the set of fragments that pass the combined Z/S test is
81 * guaranteed to be invariant under changes to the order in which
82 * fragments arrive.
83 */
84 bool pass_set;
85 };
86
87 struct radv_tessellation_state {
88 uint32_t ls_hs_config;
89 unsigned num_patches;
90 unsigned lds_size;
91 uint32_t tf_param;
92 };
93
94 bool radv_pipeline_has_ngg(const struct radv_pipeline *pipeline)
95 {
96 struct radv_shader_variant *variant = NULL;
97 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
98 variant = pipeline->shaders[MESA_SHADER_GEOMETRY];
99 else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
100 variant = pipeline->shaders[MESA_SHADER_TESS_EVAL];
101 else if (pipeline->shaders[MESA_SHADER_VERTEX])
102 variant = pipeline->shaders[MESA_SHADER_VERTEX];
103 else
104 return false;
105 return variant->info.is_ngg;
106 }
107
108 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline *pipeline)
109 {
110 if (!radv_pipeline_has_gs(pipeline))
111 return false;
112
113 /* The GS copy shader is required if the pipeline has GS on GFX6-GFX9.
114 * On GFX10, it might be required in rare cases if it's not possible to
115 * enable NGG.
116 */
117 if (radv_pipeline_has_ngg(pipeline))
118 return false;
119
120 assert(pipeline->gs_copy_shader);
121 return true;
122 }
123
124 static void
125 radv_pipeline_destroy(struct radv_device *device,
126 struct radv_pipeline *pipeline,
127 const VkAllocationCallbacks* allocator)
128 {
129 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
130 if (pipeline->shaders[i])
131 radv_shader_variant_destroy(device, pipeline->shaders[i]);
132
133 if (pipeline->gs_copy_shader)
134 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
135
136 if(pipeline->cs.buf)
137 free(pipeline->cs.buf);
138 vk_free2(&device->alloc, allocator, pipeline);
139 }
140
141 void radv_DestroyPipeline(
142 VkDevice _device,
143 VkPipeline _pipeline,
144 const VkAllocationCallbacks* pAllocator)
145 {
146 RADV_FROM_HANDLE(radv_device, device, _device);
147 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
148
149 if (!_pipeline)
150 return;
151
152 radv_pipeline_destroy(device, pipeline, pAllocator);
153 }
154
155 static uint32_t get_hash_flags(struct radv_device *device)
156 {
157 uint32_t hash_flags = 0;
158
159 if (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH)
160 hash_flags |= RADV_HASH_SHADER_UNSAFE_MATH;
161 if (device->instance->debug_flags & RADV_DEBUG_NO_NGG)
162 hash_flags |= RADV_HASH_SHADER_NO_NGG;
163 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
164 hash_flags |= RADV_HASH_SHADER_SISCHED;
165 if (device->physical_device->cs_wave_size == 32)
166 hash_flags |= RADV_HASH_SHADER_CS_WAVE32;
167 if (device->physical_device->ps_wave_size == 32)
168 hash_flags |= RADV_HASH_SHADER_PS_WAVE32;
169 if (device->physical_device->ge_wave_size == 32)
170 hash_flags |= RADV_HASH_SHADER_GE_WAVE32;
171 if (device->physical_device->use_aco)
172 hash_flags |= RADV_HASH_SHADER_ACO;
173 return hash_flags;
174 }
175
176 static VkResult
177 radv_pipeline_scratch_init(struct radv_device *device,
178 struct radv_pipeline *pipeline)
179 {
180 unsigned scratch_bytes_per_wave = 0;
181 unsigned max_waves = 0;
182 unsigned min_waves = 1;
183
184 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
185 if (pipeline->shaders[i]) {
186 unsigned max_stage_waves = device->scratch_waves;
187
188 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
189 pipeline->shaders[i]->config.scratch_bytes_per_wave);
190
191 max_stage_waves = MIN2(max_stage_waves,
192 4 * device->physical_device->rad_info.num_good_compute_units *
193 (256 / pipeline->shaders[i]->config.num_vgprs));
194 max_waves = MAX2(max_waves, max_stage_waves);
195 }
196 }
197
198 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
199 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
200 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
201 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
202 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
203 }
204
205 if (scratch_bytes_per_wave)
206 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
207
208 if (scratch_bytes_per_wave && max_waves < min_waves) {
209 /* Not really true at this moment, but will be true on first
210 * execution. Avoid having hanging shaders. */
211 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
212 }
213 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
214 pipeline->max_waves = max_waves;
215 return VK_SUCCESS;
216 }
217
218 static uint32_t si_translate_blend_logic_op(VkLogicOp op)
219 {
220 switch (op) {
221 case VK_LOGIC_OP_CLEAR:
222 return V_028808_ROP3_CLEAR;
223 case VK_LOGIC_OP_AND:
224 return V_028808_ROP3_AND;
225 case VK_LOGIC_OP_AND_REVERSE:
226 return V_028808_ROP3_AND_REVERSE;
227 case VK_LOGIC_OP_COPY:
228 return V_028808_ROP3_COPY;
229 case VK_LOGIC_OP_AND_INVERTED:
230 return V_028808_ROP3_AND_INVERTED;
231 case VK_LOGIC_OP_NO_OP:
232 return V_028808_ROP3_NO_OP;
233 case VK_LOGIC_OP_XOR:
234 return V_028808_ROP3_XOR;
235 case VK_LOGIC_OP_OR:
236 return V_028808_ROP3_OR;
237 case VK_LOGIC_OP_NOR:
238 return V_028808_ROP3_NOR;
239 case VK_LOGIC_OP_EQUIVALENT:
240 return V_028808_ROP3_EQUIVALENT;
241 case VK_LOGIC_OP_INVERT:
242 return V_028808_ROP3_INVERT;
243 case VK_LOGIC_OP_OR_REVERSE:
244 return V_028808_ROP3_OR_REVERSE;
245 case VK_LOGIC_OP_COPY_INVERTED:
246 return V_028808_ROP3_COPY_INVERTED;
247 case VK_LOGIC_OP_OR_INVERTED:
248 return V_028808_ROP3_OR_INVERTED;
249 case VK_LOGIC_OP_NAND:
250 return V_028808_ROP3_NAND;
251 case VK_LOGIC_OP_SET:
252 return V_028808_ROP3_SET;
253 default:
254 unreachable("Unhandled logic op");
255 }
256 }
257
258
259 static uint32_t si_translate_blend_function(VkBlendOp op)
260 {
261 switch (op) {
262 case VK_BLEND_OP_ADD:
263 return V_028780_COMB_DST_PLUS_SRC;
264 case VK_BLEND_OP_SUBTRACT:
265 return V_028780_COMB_SRC_MINUS_DST;
266 case VK_BLEND_OP_REVERSE_SUBTRACT:
267 return V_028780_COMB_DST_MINUS_SRC;
268 case VK_BLEND_OP_MIN:
269 return V_028780_COMB_MIN_DST_SRC;
270 case VK_BLEND_OP_MAX:
271 return V_028780_COMB_MAX_DST_SRC;
272 default:
273 return 0;
274 }
275 }
276
277 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
278 {
279 switch (factor) {
280 case VK_BLEND_FACTOR_ZERO:
281 return V_028780_BLEND_ZERO;
282 case VK_BLEND_FACTOR_ONE:
283 return V_028780_BLEND_ONE;
284 case VK_BLEND_FACTOR_SRC_COLOR:
285 return V_028780_BLEND_SRC_COLOR;
286 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
287 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
288 case VK_BLEND_FACTOR_DST_COLOR:
289 return V_028780_BLEND_DST_COLOR;
290 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
291 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
292 case VK_BLEND_FACTOR_SRC_ALPHA:
293 return V_028780_BLEND_SRC_ALPHA;
294 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
295 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
296 case VK_BLEND_FACTOR_DST_ALPHA:
297 return V_028780_BLEND_DST_ALPHA;
298 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
299 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
300 case VK_BLEND_FACTOR_CONSTANT_COLOR:
301 return V_028780_BLEND_CONSTANT_COLOR;
302 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
303 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
304 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
305 return V_028780_BLEND_CONSTANT_ALPHA;
306 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
307 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
308 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
309 return V_028780_BLEND_SRC_ALPHA_SATURATE;
310 case VK_BLEND_FACTOR_SRC1_COLOR:
311 return V_028780_BLEND_SRC1_COLOR;
312 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
313 return V_028780_BLEND_INV_SRC1_COLOR;
314 case VK_BLEND_FACTOR_SRC1_ALPHA:
315 return V_028780_BLEND_SRC1_ALPHA;
316 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
317 return V_028780_BLEND_INV_SRC1_ALPHA;
318 default:
319 return 0;
320 }
321 }
322
323 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
324 {
325 switch (op) {
326 case VK_BLEND_OP_ADD:
327 return V_028760_OPT_COMB_ADD;
328 case VK_BLEND_OP_SUBTRACT:
329 return V_028760_OPT_COMB_SUBTRACT;
330 case VK_BLEND_OP_REVERSE_SUBTRACT:
331 return V_028760_OPT_COMB_REVSUBTRACT;
332 case VK_BLEND_OP_MIN:
333 return V_028760_OPT_COMB_MIN;
334 case VK_BLEND_OP_MAX:
335 return V_028760_OPT_COMB_MAX;
336 default:
337 return V_028760_OPT_COMB_BLEND_DISABLED;
338 }
339 }
340
341 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
342 {
343 switch (factor) {
344 case VK_BLEND_FACTOR_ZERO:
345 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
346 case VK_BLEND_FACTOR_ONE:
347 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
348 case VK_BLEND_FACTOR_SRC_COLOR:
349 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
350 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
351 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
352 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
353 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
354 case VK_BLEND_FACTOR_SRC_ALPHA:
355 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
356 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
357 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
358 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
359 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
360 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
361 default:
362 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
363 }
364 }
365
366 /**
367 * Get rid of DST in the blend factors by commuting the operands:
368 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
369 */
370 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
371 unsigned *dst_factor, unsigned expected_dst,
372 unsigned replacement_src)
373 {
374 if (*src_factor == expected_dst &&
375 *dst_factor == VK_BLEND_FACTOR_ZERO) {
376 *src_factor = VK_BLEND_FACTOR_ZERO;
377 *dst_factor = replacement_src;
378
379 /* Commuting the operands requires reversing subtractions. */
380 if (*func == VK_BLEND_OP_SUBTRACT)
381 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
382 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
383 *func = VK_BLEND_OP_SUBTRACT;
384 }
385 }
386
387 static bool si_blend_factor_uses_dst(unsigned factor)
388 {
389 return factor == VK_BLEND_FACTOR_DST_COLOR ||
390 factor == VK_BLEND_FACTOR_DST_ALPHA ||
391 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
392 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
393 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
394 }
395
396 static bool is_dual_src(VkBlendFactor factor)
397 {
398 switch (factor) {
399 case VK_BLEND_FACTOR_SRC1_COLOR:
400 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
401 case VK_BLEND_FACTOR_SRC1_ALPHA:
402 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
403 return true;
404 default:
405 return false;
406 }
407 }
408
409 static unsigned si_choose_spi_color_format(VkFormat vk_format,
410 bool blend_enable,
411 bool blend_need_alpha)
412 {
413 const struct vk_format_description *desc = vk_format_description(vk_format);
414 unsigned format, ntype, swap;
415
416 /* Alpha is needed for alpha-to-coverage.
417 * Blending may be with or without alpha.
418 */
419 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
420 unsigned alpha = 0; /* exports alpha, but may not support blending */
421 unsigned blend = 0; /* supports blending, but may not export alpha */
422 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
423
424 format = radv_translate_colorformat(vk_format);
425 ntype = radv_translate_color_numformat(vk_format, desc,
426 vk_format_get_first_non_void_channel(vk_format));
427 swap = radv_translate_colorswap(vk_format, false);
428
429 /* Choose the SPI color formats. These are required values for Stoney/RB+.
430 * Other chips have multiple choices, though they are not necessarily better.
431 */
432 switch (format) {
433 case V_028C70_COLOR_5_6_5:
434 case V_028C70_COLOR_1_5_5_5:
435 case V_028C70_COLOR_5_5_5_1:
436 case V_028C70_COLOR_4_4_4_4:
437 case V_028C70_COLOR_10_11_11:
438 case V_028C70_COLOR_11_11_10:
439 case V_028C70_COLOR_8:
440 case V_028C70_COLOR_8_8:
441 case V_028C70_COLOR_8_8_8_8:
442 case V_028C70_COLOR_10_10_10_2:
443 case V_028C70_COLOR_2_10_10_10:
444 if (ntype == V_028C70_NUMBER_UINT)
445 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
446 else if (ntype == V_028C70_NUMBER_SINT)
447 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
448 else
449 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
450 break;
451
452 case V_028C70_COLOR_16:
453 case V_028C70_COLOR_16_16:
454 case V_028C70_COLOR_16_16_16_16:
455 if (ntype == V_028C70_NUMBER_UNORM ||
456 ntype == V_028C70_NUMBER_SNORM) {
457 /* UNORM16 and SNORM16 don't support blending */
458 if (ntype == V_028C70_NUMBER_UNORM)
459 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
460 else
461 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
462
463 /* Use 32 bits per channel for blending. */
464 if (format == V_028C70_COLOR_16) {
465 if (swap == V_028C70_SWAP_STD) { /* R */
466 blend = V_028714_SPI_SHADER_32_R;
467 blend_alpha = V_028714_SPI_SHADER_32_AR;
468 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
469 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
470 else
471 assert(0);
472 } else if (format == V_028C70_COLOR_16_16) {
473 if (swap == V_028C70_SWAP_STD) { /* RG */
474 blend = V_028714_SPI_SHADER_32_GR;
475 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
476 } else if (swap == V_028C70_SWAP_ALT) /* RA */
477 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
478 else
479 assert(0);
480 } else /* 16_16_16_16 */
481 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
482 } else if (ntype == V_028C70_NUMBER_UINT)
483 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
484 else if (ntype == V_028C70_NUMBER_SINT)
485 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
486 else if (ntype == V_028C70_NUMBER_FLOAT)
487 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
488 else
489 assert(0);
490 break;
491
492 case V_028C70_COLOR_32:
493 if (swap == V_028C70_SWAP_STD) { /* R */
494 blend = normal = V_028714_SPI_SHADER_32_R;
495 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
496 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
497 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
498 else
499 assert(0);
500 break;
501
502 case V_028C70_COLOR_32_32:
503 if (swap == V_028C70_SWAP_STD) { /* RG */
504 blend = normal = V_028714_SPI_SHADER_32_GR;
505 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
506 } else if (swap == V_028C70_SWAP_ALT) /* RA */
507 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
508 else
509 assert(0);
510 break;
511
512 case V_028C70_COLOR_32_32_32_32:
513 case V_028C70_COLOR_8_24:
514 case V_028C70_COLOR_24_8:
515 case V_028C70_COLOR_X24_8_32_FLOAT:
516 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
517 break;
518
519 default:
520 unreachable("unhandled blend format");
521 }
522
523 if (blend_enable && blend_need_alpha)
524 return blend_alpha;
525 else if(blend_need_alpha)
526 return alpha;
527 else if(blend_enable)
528 return blend;
529 else
530 return normal;
531 }
532
533 static void
534 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
535 const VkGraphicsPipelineCreateInfo *pCreateInfo,
536 struct radv_blend_state *blend)
537 {
538 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
539 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
540 unsigned col_format = 0;
541 unsigned num_targets;
542
543 for (unsigned i = 0; i < (blend->single_cb_enable ? 1 : subpass->color_count); ++i) {
544 unsigned cf;
545
546 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
547 cf = V_028714_SPI_SHADER_ZERO;
548 } else {
549 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
550 bool blend_enable =
551 blend->blend_enable_4bit & (0xfu << (i * 4));
552
553 cf = si_choose_spi_color_format(attachment->format,
554 blend_enable,
555 blend->need_src_alpha & (1 << i));
556 }
557
558 col_format |= cf << (4 * i);
559 }
560
561 if (!(col_format & 0xf) && blend->need_src_alpha & (1 << 0)) {
562 /* When a subpass doesn't have any color attachments, write the
563 * alpha channel of MRT0 when alpha coverage is enabled because
564 * the depth attachment needs it.
565 */
566 col_format |= V_028714_SPI_SHADER_32_AR;
567 }
568
569 /* If the i-th target format is set, all previous target formats must
570 * be non-zero to avoid hangs.
571 */
572 num_targets = (util_last_bit(col_format) + 3) / 4;
573 for (unsigned i = 0; i < num_targets; i++) {
574 if (!(col_format & (0xf << (i * 4)))) {
575 col_format |= V_028714_SPI_SHADER_32_R << (i * 4);
576 }
577 }
578
579 /* The output for dual source blending should have the same format as
580 * the first output.
581 */
582 if (blend->mrt0_is_dual_src)
583 col_format |= (col_format & 0xf) << 4;
584
585 blend->cb_shader_mask = ac_get_cb_shader_mask(col_format);
586 blend->spi_shader_col_format = col_format;
587 }
588
589 static bool
590 format_is_int8(VkFormat format)
591 {
592 const struct vk_format_description *desc = vk_format_description(format);
593 int channel = vk_format_get_first_non_void_channel(format);
594
595 return channel >= 0 && desc->channel[channel].pure_integer &&
596 desc->channel[channel].size == 8;
597 }
598
599 static bool
600 format_is_int10(VkFormat format)
601 {
602 const struct vk_format_description *desc = vk_format_description(format);
603
604 if (desc->nr_channels != 4)
605 return false;
606 for (unsigned i = 0; i < 4; i++) {
607 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
608 return true;
609 }
610 return false;
611 }
612
613 /*
614 * Ordered so that for each i,
615 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
616 */
617 const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS] = {
618 VK_FORMAT_R32_SFLOAT,
619 VK_FORMAT_R32G32_SFLOAT,
620 VK_FORMAT_R8G8B8A8_UNORM,
621 VK_FORMAT_R16G16B16A16_UNORM,
622 VK_FORMAT_R16G16B16A16_SNORM,
623 VK_FORMAT_R16G16B16A16_UINT,
624 VK_FORMAT_R16G16B16A16_SINT,
625 VK_FORMAT_R32G32B32A32_SFLOAT,
626 VK_FORMAT_R8G8B8A8_UINT,
627 VK_FORMAT_R8G8B8A8_SINT,
628 VK_FORMAT_A2R10G10B10_UINT_PACK32,
629 VK_FORMAT_A2R10G10B10_SINT_PACK32,
630 };
631
632 unsigned radv_format_meta_fs_key(VkFormat format)
633 {
634 unsigned col_format = si_choose_spi_color_format(format, false, false);
635
636 assert(col_format != V_028714_SPI_SHADER_32_AR);
637 if (col_format >= V_028714_SPI_SHADER_32_AR)
638 --col_format; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
639
640 --col_format; /* Skip V_028714_SPI_SHADER_ZERO */
641 bool is_int8 = format_is_int8(format);
642 bool is_int10 = format_is_int10(format);
643
644 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
645 }
646
647 static void
648 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo *pCreateInfo,
649 unsigned *is_int8, unsigned *is_int10)
650 {
651 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
652 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
653 *is_int8 = 0;
654 *is_int10 = 0;
655
656 for (unsigned i = 0; i < subpass->color_count; ++i) {
657 struct radv_render_pass_attachment *attachment;
658
659 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
660 continue;
661
662 attachment = pass->attachments + subpass->color_attachments[i].attachment;
663
664 if (format_is_int8(attachment->format))
665 *is_int8 |= 1 << i;
666 if (format_is_int10(attachment->format))
667 *is_int10 |= 1 << i;
668 }
669 }
670
671 static void
672 radv_blend_check_commutativity(struct radv_blend_state *blend,
673 VkBlendOp op, VkBlendFactor src,
674 VkBlendFactor dst, unsigned chanmask)
675 {
676 /* Src factor is allowed when it does not depend on Dst. */
677 static const uint32_t src_allowed =
678 (1u << VK_BLEND_FACTOR_ONE) |
679 (1u << VK_BLEND_FACTOR_SRC_COLOR) |
680 (1u << VK_BLEND_FACTOR_SRC_ALPHA) |
681 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE) |
682 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR) |
683 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA) |
684 (1u << VK_BLEND_FACTOR_SRC1_COLOR) |
685 (1u << VK_BLEND_FACTOR_SRC1_ALPHA) |
686 (1u << VK_BLEND_FACTOR_ZERO) |
687 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR) |
688 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA) |
689 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR) |
690 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA) |
691 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR) |
692 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA);
693
694 if (dst == VK_BLEND_FACTOR_ONE &&
695 (src_allowed & (1u << src))) {
696 /* Addition is commutative, but floating point addition isn't
697 * associative: subtle changes can be introduced via different
698 * rounding. Be conservative, only enable for min and max.
699 */
700 if (op == VK_BLEND_OP_MAX || op == VK_BLEND_OP_MIN)
701 blend->commutative_4bit |= chanmask;
702 }
703 }
704
705 static struct radv_blend_state
706 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
707 const VkGraphicsPipelineCreateInfo *pCreateInfo,
708 const struct radv_graphics_pipeline_create_info *extra)
709 {
710 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
711 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
712 struct radv_blend_state blend = {0};
713 unsigned mode = V_028808_CB_NORMAL;
714 int i;
715
716 if (!vkblend)
717 return blend;
718
719 if (extra && extra->custom_blend_mode) {
720 blend.single_cb_enable = true;
721 mode = extra->custom_blend_mode;
722 }
723 blend.cb_color_control = 0;
724 if (vkblend->logicOpEnable)
725 blend.cb_color_control |= S_028808_ROP3(si_translate_blend_logic_op(vkblend->logicOp));
726 else
727 blend.cb_color_control |= S_028808_ROP3(V_028808_ROP3_COPY);
728
729 blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
730 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
731 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
732 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
733 S_028B70_OFFSET_ROUND(1);
734
735 if (vkms && vkms->alphaToCoverageEnable) {
736 blend.db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
737 blend.need_src_alpha |= 0x1;
738 }
739
740 blend.cb_target_mask = 0;
741 for (i = 0; i < vkblend->attachmentCount; i++) {
742 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
743 unsigned blend_cntl = 0;
744 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
745 VkBlendOp eqRGB = att->colorBlendOp;
746 VkBlendFactor srcRGB = att->srcColorBlendFactor;
747 VkBlendFactor dstRGB = att->dstColorBlendFactor;
748 VkBlendOp eqA = att->alphaBlendOp;
749 VkBlendFactor srcA = att->srcAlphaBlendFactor;
750 VkBlendFactor dstA = att->dstAlphaBlendFactor;
751
752 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
753
754 if (!att->colorWriteMask)
755 continue;
756
757 blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
758 blend.cb_target_enabled_4bit |= 0xf << (4 * i);
759 if (!att->blendEnable) {
760 blend.cb_blend_control[i] = blend_cntl;
761 continue;
762 }
763
764 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
765 if (i == 0)
766 blend.mrt0_is_dual_src = true;
767
768 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
769 srcRGB = VK_BLEND_FACTOR_ONE;
770 dstRGB = VK_BLEND_FACTOR_ONE;
771 }
772 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
773 srcA = VK_BLEND_FACTOR_ONE;
774 dstA = VK_BLEND_FACTOR_ONE;
775 }
776
777 radv_blend_check_commutativity(&blend, eqRGB, srcRGB, dstRGB,
778 0x7 << (4 * i));
779 radv_blend_check_commutativity(&blend, eqA, srcA, dstA,
780 0x8 << (4 * i));
781
782 /* Blending optimizations for RB+.
783 * These transformations don't change the behavior.
784 *
785 * First, get rid of DST in the blend factors:
786 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
787 */
788 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
789 VK_BLEND_FACTOR_DST_COLOR,
790 VK_BLEND_FACTOR_SRC_COLOR);
791
792 si_blend_remove_dst(&eqA, &srcA, &dstA,
793 VK_BLEND_FACTOR_DST_COLOR,
794 VK_BLEND_FACTOR_SRC_COLOR);
795
796 si_blend_remove_dst(&eqA, &srcA, &dstA,
797 VK_BLEND_FACTOR_DST_ALPHA,
798 VK_BLEND_FACTOR_SRC_ALPHA);
799
800 /* Look up the ideal settings from tables. */
801 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
802 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
803 srcA_opt = si_translate_blend_opt_factor(srcA, true);
804 dstA_opt = si_translate_blend_opt_factor(dstA, true);
805
806 /* Handle interdependencies. */
807 if (si_blend_factor_uses_dst(srcRGB))
808 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
809 if (si_blend_factor_uses_dst(srcA))
810 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
811
812 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
813 (dstRGB == VK_BLEND_FACTOR_ZERO ||
814 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
815 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
816 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
817
818 /* Set the final value. */
819 blend.sx_mrt_blend_opt[i] =
820 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
821 S_028760_COLOR_DST_OPT(dstRGB_opt) |
822 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
823 S_028760_ALPHA_SRC_OPT(srcA_opt) |
824 S_028760_ALPHA_DST_OPT(dstA_opt) |
825 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
826 blend_cntl |= S_028780_ENABLE(1);
827
828 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
829 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
830 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
831 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
832 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
833 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
834 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
835 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
836 }
837 blend.cb_blend_control[i] = blend_cntl;
838
839 blend.blend_enable_4bit |= 0xfu << (i * 4);
840
841 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
842 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
843 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
844 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
845 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
846 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
847 blend.need_src_alpha |= 1 << i;
848 }
849 for (i = vkblend->attachmentCount; i < 8; i++) {
850 blend.cb_blend_control[i] = 0;
851 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
852 }
853
854 if (pipeline->device->physical_device->rad_info.has_rbplus) {
855 /* Disable RB+ blend optimizations for dual source blending. */
856 if (blend.mrt0_is_dual_src) {
857 for (i = 0; i < 8; i++) {
858 blend.sx_mrt_blend_opt[i] =
859 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
860 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
861 }
862 }
863
864 /* RB+ doesn't work with dual source blending, logic op and
865 * RESOLVE.
866 */
867 if (blend.mrt0_is_dual_src || vkblend->logicOpEnable ||
868 mode == V_028808_CB_RESOLVE)
869 blend.cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
870 }
871
872 if (blend.cb_target_mask)
873 blend.cb_color_control |= S_028808_MODE(mode);
874 else
875 blend.cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
876
877 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo, &blend);
878 return blend;
879 }
880
881 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
882 {
883 switch (op) {
884 case VK_STENCIL_OP_KEEP:
885 return V_02842C_STENCIL_KEEP;
886 case VK_STENCIL_OP_ZERO:
887 return V_02842C_STENCIL_ZERO;
888 case VK_STENCIL_OP_REPLACE:
889 return V_02842C_STENCIL_REPLACE_TEST;
890 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
891 return V_02842C_STENCIL_ADD_CLAMP;
892 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
893 return V_02842C_STENCIL_SUB_CLAMP;
894 case VK_STENCIL_OP_INVERT:
895 return V_02842C_STENCIL_INVERT;
896 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
897 return V_02842C_STENCIL_ADD_WRAP;
898 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
899 return V_02842C_STENCIL_SUB_WRAP;
900 default:
901 return 0;
902 }
903 }
904
905 static uint32_t si_translate_fill(VkPolygonMode func)
906 {
907 switch(func) {
908 case VK_POLYGON_MODE_FILL:
909 return V_028814_X_DRAW_TRIANGLES;
910 case VK_POLYGON_MODE_LINE:
911 return V_028814_X_DRAW_LINES;
912 case VK_POLYGON_MODE_POINT:
913 return V_028814_X_DRAW_POINTS;
914 default:
915 assert(0);
916 return V_028814_X_DRAW_POINTS;
917 }
918 }
919
920 static uint8_t radv_pipeline_get_ps_iter_samples(const VkPipelineMultisampleStateCreateInfo *vkms)
921 {
922 uint32_t num_samples = vkms->rasterizationSamples;
923 uint32_t ps_iter_samples = 1;
924
925 if (vkms->sampleShadingEnable) {
926 ps_iter_samples = ceil(vkms->minSampleShading * num_samples);
927 ps_iter_samples = util_next_power_of_two(ps_iter_samples);
928 }
929 return ps_iter_samples;
930 }
931
932 static bool
933 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
934 {
935 return pCreateInfo->depthTestEnable &&
936 pCreateInfo->depthWriteEnable &&
937 pCreateInfo->depthCompareOp != VK_COMPARE_OP_NEVER;
938 }
939
940 static bool
941 radv_writes_stencil(const VkStencilOpState *state)
942 {
943 return state->writeMask &&
944 (state->failOp != VK_STENCIL_OP_KEEP ||
945 state->passOp != VK_STENCIL_OP_KEEP ||
946 state->depthFailOp != VK_STENCIL_OP_KEEP);
947 }
948
949 static bool
950 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
951 {
952 return pCreateInfo->stencilTestEnable &&
953 (radv_writes_stencil(&pCreateInfo->front) ||
954 radv_writes_stencil(&pCreateInfo->back));
955 }
956
957 static bool
958 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
959 {
960 return radv_is_depth_write_enabled(pCreateInfo) ||
961 radv_is_stencil_write_enabled(pCreateInfo);
962 }
963
964 static bool
965 radv_order_invariant_stencil_op(VkStencilOp op)
966 {
967 /* REPLACE is normally order invariant, except when the stencil
968 * reference value is written by the fragment shader. Tracking this
969 * interaction does not seem worth the effort, so be conservative.
970 */
971 return op != VK_STENCIL_OP_INCREMENT_AND_CLAMP &&
972 op != VK_STENCIL_OP_DECREMENT_AND_CLAMP &&
973 op != VK_STENCIL_OP_REPLACE;
974 }
975
976 static bool
977 radv_order_invariant_stencil_state(const VkStencilOpState *state)
978 {
979 /* Compute whether, assuming Z writes are disabled, this stencil state
980 * is order invariant in the sense that the set of passing fragments as
981 * well as the final stencil buffer result does not depend on the order
982 * of fragments.
983 */
984 return !state->writeMask ||
985 /* The following assumes that Z writes are disabled. */
986 (state->compareOp == VK_COMPARE_OP_ALWAYS &&
987 radv_order_invariant_stencil_op(state->passOp) &&
988 radv_order_invariant_stencil_op(state->depthFailOp)) ||
989 (state->compareOp == VK_COMPARE_OP_NEVER &&
990 radv_order_invariant_stencil_op(state->failOp));
991 }
992
993 static bool
994 radv_pipeline_out_of_order_rast(struct radv_pipeline *pipeline,
995 struct radv_blend_state *blend,
996 const VkGraphicsPipelineCreateInfo *pCreateInfo)
997 {
998 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
999 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
1000 unsigned colormask = blend->cb_target_enabled_4bit;
1001
1002 if (!pipeline->device->physical_device->out_of_order_rast_allowed)
1003 return false;
1004
1005 /* Be conservative if a logic operation is enabled with color buffers. */
1006 if (colormask && pCreateInfo->pColorBlendState->logicOpEnable)
1007 return false;
1008
1009 /* Default depth/stencil invariance when no attachment is bound. */
1010 struct radv_dsa_order_invariance dsa_order_invariant = {
1011 .zs = true, .pass_set = true
1012 };
1013
1014 if (pCreateInfo->pDepthStencilState &&
1015 subpass->depth_stencil_attachment) {
1016 const VkPipelineDepthStencilStateCreateInfo *vkds =
1017 pCreateInfo->pDepthStencilState;
1018 struct radv_render_pass_attachment *attachment =
1019 pass->attachments + subpass->depth_stencil_attachment->attachment;
1020 bool has_stencil = vk_format_is_stencil(attachment->format);
1021 struct radv_dsa_order_invariance order_invariance[2];
1022 struct radv_shader_variant *ps =
1023 pipeline->shaders[MESA_SHADER_FRAGMENT];
1024
1025 /* Compute depth/stencil order invariance in order to know if
1026 * it's safe to enable out-of-order.
1027 */
1028 bool zfunc_is_ordered =
1029 vkds->depthCompareOp == VK_COMPARE_OP_NEVER ||
1030 vkds->depthCompareOp == VK_COMPARE_OP_LESS ||
1031 vkds->depthCompareOp == VK_COMPARE_OP_LESS_OR_EQUAL ||
1032 vkds->depthCompareOp == VK_COMPARE_OP_GREATER ||
1033 vkds->depthCompareOp == VK_COMPARE_OP_GREATER_OR_EQUAL;
1034
1035 bool nozwrite_and_order_invariant_stencil =
1036 !radv_is_ds_write_enabled(vkds) ||
1037 (!radv_is_depth_write_enabled(vkds) &&
1038 radv_order_invariant_stencil_state(&vkds->front) &&
1039 radv_order_invariant_stencil_state(&vkds->back));
1040
1041 order_invariance[1].zs =
1042 nozwrite_and_order_invariant_stencil ||
1043 (!radv_is_stencil_write_enabled(vkds) &&
1044 zfunc_is_ordered);
1045 order_invariance[0].zs =
1046 !radv_is_depth_write_enabled(vkds) || zfunc_is_ordered;
1047
1048 order_invariance[1].pass_set =
1049 nozwrite_and_order_invariant_stencil ||
1050 (!radv_is_stencil_write_enabled(vkds) &&
1051 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1052 vkds->depthCompareOp == VK_COMPARE_OP_NEVER));
1053 order_invariance[0].pass_set =
1054 !radv_is_depth_write_enabled(vkds) ||
1055 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1056 vkds->depthCompareOp == VK_COMPARE_OP_NEVER);
1057
1058 dsa_order_invariant = order_invariance[has_stencil];
1059 if (!dsa_order_invariant.zs)
1060 return false;
1061
1062 /* The set of PS invocations is always order invariant,
1063 * except when early Z/S tests are requested.
1064 */
1065 if (ps &&
1066 ps->info.ps.writes_memory &&
1067 ps->info.ps.early_fragment_test &&
1068 !dsa_order_invariant.pass_set)
1069 return false;
1070
1071 /* Determine if out-of-order rasterization should be disabled
1072 * when occlusion queries are used.
1073 */
1074 pipeline->graphics.disable_out_of_order_rast_for_occlusion =
1075 !dsa_order_invariant.pass_set;
1076 }
1077
1078 /* No color buffers are enabled for writing. */
1079 if (!colormask)
1080 return true;
1081
1082 unsigned blendmask = colormask & blend->blend_enable_4bit;
1083
1084 if (blendmask) {
1085 /* Only commutative blending. */
1086 if (blendmask & ~blend->commutative_4bit)
1087 return false;
1088
1089 if (!dsa_order_invariant.pass_set)
1090 return false;
1091 }
1092
1093 if (colormask & ~blendmask)
1094 return false;
1095
1096 return true;
1097 }
1098
1099 static void
1100 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1101 struct radv_blend_state *blend,
1102 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1103 {
1104 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
1105 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1106 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1107 bool out_of_order_rast = false;
1108 int ps_iter_samples = 1;
1109 uint32_t mask = 0xffff;
1110
1111 if (vkms)
1112 ms->num_samples = vkms->rasterizationSamples;
1113 else
1114 ms->num_samples = 1;
1115
1116 if (vkms)
1117 ps_iter_samples = radv_pipeline_get_ps_iter_samples(vkms);
1118 if (vkms && !vkms->sampleShadingEnable && pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.force_persample) {
1119 ps_iter_samples = ms->num_samples;
1120 }
1121
1122 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
1123 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
1124 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
1125 /* Out-of-order rasterization is explicitly enabled by the
1126 * application.
1127 */
1128 out_of_order_rast = true;
1129 } else {
1130 /* Determine if the driver can enable out-of-order
1131 * rasterization internally.
1132 */
1133 out_of_order_rast =
1134 radv_pipeline_out_of_order_rast(pipeline, blend, pCreateInfo);
1135 }
1136
1137 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1138 ms->pa_sc_aa_config = 0;
1139 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1140 S_028804_INCOHERENT_EQAA_READS(1) |
1141 S_028804_INTERPOLATE_COMP_Z(1) |
1142 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1143 ms->pa_sc_mode_cntl_1 =
1144 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1145 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1146 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
1147 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1148 /* always 1: */
1149 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1150 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1151 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1152 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1153 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1154 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1155 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9) |
1156 S_028A48_VPORT_SCISSOR_ENABLE(1);
1157
1158 if (ms->num_samples > 1) {
1159 unsigned log_samples = util_logbase2(ms->num_samples);
1160 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
1161 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
1162 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1163 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1164 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1165 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1166 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1167 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1168 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples)) |
1169 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1170 ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1171 if (ps_iter_samples > 1)
1172 pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1173 }
1174
1175 if (vkms && vkms->pSampleMask) {
1176 mask = vkms->pSampleMask[0] & 0xffff;
1177 }
1178
1179 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1180 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1181 }
1182
1183 static bool
1184 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1185 {
1186 switch (topology) {
1187 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1188 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1189 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1190 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1191 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1192 return false;
1193 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1194 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1195 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1196 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1197 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1198 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1199 return true;
1200 default:
1201 unreachable("unhandled primitive type");
1202 }
1203 }
1204
1205 static uint32_t
1206 si_translate_prim(enum VkPrimitiveTopology topology)
1207 {
1208 switch (topology) {
1209 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1210 return V_008958_DI_PT_POINTLIST;
1211 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1212 return V_008958_DI_PT_LINELIST;
1213 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1214 return V_008958_DI_PT_LINESTRIP;
1215 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1216 return V_008958_DI_PT_TRILIST;
1217 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1218 return V_008958_DI_PT_TRISTRIP;
1219 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1220 return V_008958_DI_PT_TRIFAN;
1221 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1222 return V_008958_DI_PT_LINELIST_ADJ;
1223 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1224 return V_008958_DI_PT_LINESTRIP_ADJ;
1225 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1226 return V_008958_DI_PT_TRILIST_ADJ;
1227 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1228 return V_008958_DI_PT_TRISTRIP_ADJ;
1229 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1230 return V_008958_DI_PT_PATCH;
1231 default:
1232 assert(0);
1233 return 0;
1234 }
1235 }
1236
1237 static uint32_t
1238 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1239 {
1240 switch (gl_prim) {
1241 case 0: /* GL_POINTS */
1242 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1243 case 1: /* GL_LINES */
1244 case 3: /* GL_LINE_STRIP */
1245 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1246 case 0x8E7A: /* GL_ISOLINES */
1247 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1248
1249 case 4: /* GL_TRIANGLES */
1250 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1251 case 5: /* GL_TRIANGLE_STRIP */
1252 case 7: /* GL_QUADS */
1253 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1254 default:
1255 assert(0);
1256 return 0;
1257 }
1258 }
1259
1260 static uint32_t
1261 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1262 {
1263 switch (topology) {
1264 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1265 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1266 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1267 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1268 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1269 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1270 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1271 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1272 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1273 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1274 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1275 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1276 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1277 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1278 default:
1279 assert(0);
1280 return 0;
1281 }
1282 }
1283
1284 static unsigned radv_dynamic_state_mask(VkDynamicState state)
1285 {
1286 switch(state) {
1287 case VK_DYNAMIC_STATE_VIEWPORT:
1288 return RADV_DYNAMIC_VIEWPORT;
1289 case VK_DYNAMIC_STATE_SCISSOR:
1290 return RADV_DYNAMIC_SCISSOR;
1291 case VK_DYNAMIC_STATE_LINE_WIDTH:
1292 return RADV_DYNAMIC_LINE_WIDTH;
1293 case VK_DYNAMIC_STATE_DEPTH_BIAS:
1294 return RADV_DYNAMIC_DEPTH_BIAS;
1295 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
1296 return RADV_DYNAMIC_BLEND_CONSTANTS;
1297 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
1298 return RADV_DYNAMIC_DEPTH_BOUNDS;
1299 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
1300 return RADV_DYNAMIC_STENCIL_COMPARE_MASK;
1301 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
1302 return RADV_DYNAMIC_STENCIL_WRITE_MASK;
1303 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
1304 return RADV_DYNAMIC_STENCIL_REFERENCE;
1305 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT:
1306 return RADV_DYNAMIC_DISCARD_RECTANGLE;
1307 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT:
1308 return RADV_DYNAMIC_SAMPLE_LOCATIONS;
1309 default:
1310 unreachable("Unhandled dynamic state");
1311 }
1312 }
1313
1314 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
1315 {
1316 uint32_t states = RADV_DYNAMIC_ALL;
1317
1318 /* If rasterization is disabled we do not care about any of the dynamic states,
1319 * since they are all rasterization related only. */
1320 if (pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
1321 return 0;
1322
1323 if (!pCreateInfo->pRasterizationState->depthBiasEnable)
1324 states &= ~RADV_DYNAMIC_DEPTH_BIAS;
1325
1326 if (!pCreateInfo->pDepthStencilState ||
1327 !pCreateInfo->pDepthStencilState->depthBoundsTestEnable)
1328 states &= ~RADV_DYNAMIC_DEPTH_BOUNDS;
1329
1330 if (!pCreateInfo->pDepthStencilState ||
1331 !pCreateInfo->pDepthStencilState->stencilTestEnable)
1332 states &= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK |
1333 RADV_DYNAMIC_STENCIL_WRITE_MASK |
1334 RADV_DYNAMIC_STENCIL_REFERENCE);
1335
1336 if (!vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT))
1337 states &= ~RADV_DYNAMIC_DISCARD_RECTANGLE;
1338
1339 if (!pCreateInfo->pMultisampleState ||
1340 !vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1341 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT))
1342 states &= ~RADV_DYNAMIC_SAMPLE_LOCATIONS;
1343
1344 /* TODO: blend constants & line width. */
1345
1346 return states;
1347 }
1348
1349
1350 static void
1351 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1352 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1353 {
1354 uint32_t needed_states = radv_pipeline_needed_dynamic_state(pCreateInfo);
1355 uint32_t states = needed_states;
1356 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1357 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1358
1359 pipeline->dynamic_state = default_dynamic_state;
1360 pipeline->graphics.needed_dynamic_state = needed_states;
1361
1362 if (pCreateInfo->pDynamicState) {
1363 /* Remove all of the states that are marked as dynamic */
1364 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1365 for (uint32_t s = 0; s < count; s++)
1366 states &= ~radv_dynamic_state_mask(pCreateInfo->pDynamicState->pDynamicStates[s]);
1367 }
1368
1369 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1370
1371 if (needed_states & RADV_DYNAMIC_VIEWPORT) {
1372 assert(pCreateInfo->pViewportState);
1373
1374 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1375 if (states & RADV_DYNAMIC_VIEWPORT) {
1376 typed_memcpy(dynamic->viewport.viewports,
1377 pCreateInfo->pViewportState->pViewports,
1378 pCreateInfo->pViewportState->viewportCount);
1379 }
1380 }
1381
1382 if (needed_states & RADV_DYNAMIC_SCISSOR) {
1383 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1384 if (states & RADV_DYNAMIC_SCISSOR) {
1385 typed_memcpy(dynamic->scissor.scissors,
1386 pCreateInfo->pViewportState->pScissors,
1387 pCreateInfo->pViewportState->scissorCount);
1388 }
1389 }
1390
1391 if (states & RADV_DYNAMIC_LINE_WIDTH) {
1392 assert(pCreateInfo->pRasterizationState);
1393 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1394 }
1395
1396 if (states & RADV_DYNAMIC_DEPTH_BIAS) {
1397 assert(pCreateInfo->pRasterizationState);
1398 dynamic->depth_bias.bias =
1399 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1400 dynamic->depth_bias.clamp =
1401 pCreateInfo->pRasterizationState->depthBiasClamp;
1402 dynamic->depth_bias.slope =
1403 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1404 }
1405
1406 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1407 *
1408 * pColorBlendState is [...] NULL if the pipeline has rasterization
1409 * disabled or if the subpass of the render pass the pipeline is
1410 * created against does not use any color attachments.
1411 */
1412 if (subpass->has_color_att && states & RADV_DYNAMIC_BLEND_CONSTANTS) {
1413 assert(pCreateInfo->pColorBlendState);
1414 typed_memcpy(dynamic->blend_constants,
1415 pCreateInfo->pColorBlendState->blendConstants, 4);
1416 }
1417
1418 /* If there is no depthstencil attachment, then don't read
1419 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1420 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1421 * no need to override the depthstencil defaults in
1422 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1423 *
1424 * Section 9.2 of the Vulkan 1.0.15 spec says:
1425 *
1426 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1427 * disabled or if the subpass of the render pass the pipeline is created
1428 * against does not use a depth/stencil attachment.
1429 */
1430 if (needed_states && subpass->depth_stencil_attachment) {
1431 assert(pCreateInfo->pDepthStencilState);
1432
1433 if (states & RADV_DYNAMIC_DEPTH_BOUNDS) {
1434 dynamic->depth_bounds.min =
1435 pCreateInfo->pDepthStencilState->minDepthBounds;
1436 dynamic->depth_bounds.max =
1437 pCreateInfo->pDepthStencilState->maxDepthBounds;
1438 }
1439
1440 if (states & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
1441 dynamic->stencil_compare_mask.front =
1442 pCreateInfo->pDepthStencilState->front.compareMask;
1443 dynamic->stencil_compare_mask.back =
1444 pCreateInfo->pDepthStencilState->back.compareMask;
1445 }
1446
1447 if (states & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
1448 dynamic->stencil_write_mask.front =
1449 pCreateInfo->pDepthStencilState->front.writeMask;
1450 dynamic->stencil_write_mask.back =
1451 pCreateInfo->pDepthStencilState->back.writeMask;
1452 }
1453
1454 if (states & RADV_DYNAMIC_STENCIL_REFERENCE) {
1455 dynamic->stencil_reference.front =
1456 pCreateInfo->pDepthStencilState->front.reference;
1457 dynamic->stencil_reference.back =
1458 pCreateInfo->pDepthStencilState->back.reference;
1459 }
1460 }
1461
1462 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
1463 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
1464 if (needed_states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1465 dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount;
1466 if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1467 typed_memcpy(dynamic->discard_rectangle.rectangles,
1468 discard_rectangle_info->pDiscardRectangles,
1469 discard_rectangle_info->discardRectangleCount);
1470 }
1471 }
1472
1473 if (needed_states & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
1474 const VkPipelineSampleLocationsStateCreateInfoEXT *sample_location_info =
1475 vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1476 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
1477 /* If sampleLocationsEnable is VK_FALSE, the default sample
1478 * locations are used and the values specified in
1479 * sampleLocationsInfo are ignored.
1480 */
1481 if (sample_location_info->sampleLocationsEnable) {
1482 const VkSampleLocationsInfoEXT *pSampleLocationsInfo =
1483 &sample_location_info->sampleLocationsInfo;
1484
1485 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
1486
1487 dynamic->sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
1488 dynamic->sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
1489 dynamic->sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
1490 typed_memcpy(&dynamic->sample_location.locations[0],
1491 pSampleLocationsInfo->pSampleLocations,
1492 pSampleLocationsInfo->sampleLocationsCount);
1493 }
1494 }
1495
1496 pipeline->dynamic_state.mask = states;
1497 }
1498
1499 static void
1500 gfx9_get_gs_info(const struct radv_pipeline_key *key,
1501 const struct radv_pipeline *pipeline,
1502 nir_shader **nir,
1503 struct radv_shader_info *infos,
1504 struct gfx9_gs_info *out)
1505 {
1506 struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY];
1507 struct radv_es_output_info *es_info;
1508 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
1509 es_info = nir[MESA_SHADER_TESS_CTRL] ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1510 else
1511 es_info = nir[MESA_SHADER_TESS_CTRL] ?
1512 &infos[MESA_SHADER_TESS_EVAL].tes.es_info :
1513 &infos[MESA_SHADER_VERTEX].vs.es_info;
1514
1515 unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
1516 bool uses_adjacency;
1517 switch(key->topology) {
1518 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1519 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1520 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1521 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1522 uses_adjacency = true;
1523 break;
1524 default:
1525 uses_adjacency = false;
1526 break;
1527 }
1528
1529 /* All these are in dwords: */
1530 /* We can't allow using the whole LDS, because GS waves compete with
1531 * other shader stages for LDS space. */
1532 const unsigned max_lds_size = 8 * 1024;
1533 const unsigned esgs_itemsize = es_info->esgs_itemsize / 4;
1534 unsigned esgs_lds_size;
1535
1536 /* All these are per subgroup: */
1537 const unsigned max_out_prims = 32 * 1024;
1538 const unsigned max_es_verts = 255;
1539 const unsigned ideal_gs_prims = 64;
1540 unsigned max_gs_prims, gs_prims;
1541 unsigned min_es_verts, es_verts, worst_case_es_verts;
1542
1543 if (uses_adjacency || gs_num_invocations > 1)
1544 max_gs_prims = 127 / gs_num_invocations;
1545 else
1546 max_gs_prims = 255;
1547
1548 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1549 * Make sure we don't go over the maximum value.
1550 */
1551 if (gs_info->gs.vertices_out > 0) {
1552 max_gs_prims = MIN2(max_gs_prims,
1553 max_out_prims /
1554 (gs_info->gs.vertices_out * gs_num_invocations));
1555 }
1556 assert(max_gs_prims > 0);
1557
1558 /* If the primitive has adjacency, halve the number of vertices
1559 * that will be reused in multiple primitives.
1560 */
1561 min_es_verts = gs_info->gs.vertices_in / (uses_adjacency ? 2 : 1);
1562
1563 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
1564 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
1565
1566 /* Compute ESGS LDS size based on the worst case number of ES vertices
1567 * needed to create the target number of GS prims per subgroup.
1568 */
1569 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1570
1571 /* If total LDS usage is too big, refactor partitions based on ratio
1572 * of ESGS item sizes.
1573 */
1574 if (esgs_lds_size > max_lds_size) {
1575 /* Our target GS Prims Per Subgroup was too large. Calculate
1576 * the maximum number of GS Prims Per Subgroup that will fit
1577 * into LDS, capped by the maximum that the hardware can support.
1578 */
1579 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
1580 max_gs_prims);
1581 assert(gs_prims > 0);
1582 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
1583 max_es_verts);
1584
1585 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1586 assert(esgs_lds_size <= max_lds_size);
1587 }
1588
1589 /* Now calculate remaining ESGS information. */
1590 if (esgs_lds_size)
1591 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
1592 else
1593 es_verts = max_es_verts;
1594
1595 /* Vertices for adjacency primitives are not always reused, so restore
1596 * it for ES_VERTS_PER_SUBGRP.
1597 */
1598 min_es_verts = gs_info->gs.vertices_in;
1599
1600 /* For normal primitives, the VGT only checks if they are past the ES
1601 * verts per subgroup after allocating a full GS primitive and if they
1602 * are, kick off a new subgroup. But if those additional ES verts are
1603 * unique (e.g. not reused) we need to make sure there is enough LDS
1604 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1605 */
1606 es_verts -= min_es_verts - 1;
1607
1608 uint32_t es_verts_per_subgroup = es_verts;
1609 uint32_t gs_prims_per_subgroup = gs_prims;
1610 uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
1611 uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out;
1612 out->lds_size = align(esgs_lds_size, 128) / 128;
1613 out->vgt_gs_onchip_cntl = S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) |
1614 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) |
1615 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup);
1616 out->vgt_gs_max_prims_per_subgroup = S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup);
1617 out->vgt_esgs_ring_itemsize = esgs_itemsize;
1618 assert(max_prims_per_subgroup <= max_out_prims);
1619 }
1620
1621 static void clamp_gsprims_to_esverts(unsigned *max_gsprims, unsigned max_esverts,
1622 unsigned min_verts_per_prim, bool use_adjacency)
1623 {
1624 unsigned max_reuse = max_esverts - min_verts_per_prim;
1625 if (use_adjacency)
1626 max_reuse /= 2;
1627 *max_gsprims = MIN2(*max_gsprims, 1 + max_reuse);
1628 }
1629
1630 static unsigned
1631 radv_get_num_input_vertices(nir_shader **nir)
1632 {
1633 if (nir[MESA_SHADER_GEOMETRY]) {
1634 nir_shader *gs = nir[MESA_SHADER_GEOMETRY];
1635
1636 return gs->info.gs.vertices_in;
1637 }
1638
1639 if (nir[MESA_SHADER_TESS_CTRL]) {
1640 nir_shader *tes = nir[MESA_SHADER_TESS_EVAL];
1641
1642 if (tes->info.tess.point_mode)
1643 return 1;
1644 if (tes->info.tess.primitive_mode == GL_ISOLINES)
1645 return 2;
1646 return 3;
1647 }
1648
1649 return 3;
1650 }
1651
1652 static void
1653 gfx10_get_ngg_info(const struct radv_pipeline_key *key,
1654 struct radv_pipeline *pipeline,
1655 nir_shader **nir,
1656 struct radv_shader_info *infos,
1657 struct gfx10_ngg_info *ngg)
1658 {
1659 struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY];
1660 struct radv_es_output_info *es_info =
1661 nir[MESA_SHADER_TESS_CTRL] ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1662 unsigned gs_type = nir[MESA_SHADER_GEOMETRY] ? MESA_SHADER_GEOMETRY : MESA_SHADER_VERTEX;
1663 unsigned max_verts_per_prim = radv_get_num_input_vertices(nir);
1664 unsigned min_verts_per_prim =
1665 gs_type == MESA_SHADER_GEOMETRY ? max_verts_per_prim : 1;
1666 unsigned gs_num_invocations = nir[MESA_SHADER_GEOMETRY] ? MAX2(gs_info->gs.invocations, 1) : 1;
1667 bool uses_adjacency;
1668 switch(key->topology) {
1669 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1670 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1671 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1672 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1673 uses_adjacency = true;
1674 break;
1675 default:
1676 uses_adjacency = false;
1677 break;
1678 }
1679
1680 /* All these are in dwords: */
1681 /* We can't allow using the whole LDS, because GS waves compete with
1682 * other shader stages for LDS space.
1683 *
1684 * TODO: We should really take the shader's internal LDS use into
1685 * account. The linker will fail if the size is greater than
1686 * 8K dwords.
1687 */
1688 const unsigned max_lds_size = 8 * 1024 - 768;
1689 const unsigned target_lds_size = max_lds_size;
1690 unsigned esvert_lds_size = 0;
1691 unsigned gsprim_lds_size = 0;
1692
1693 /* All these are per subgroup: */
1694 bool max_vert_out_per_gs_instance = false;
1695 unsigned max_esverts_base = 256;
1696 unsigned max_gsprims_base = 128; /* default prim group size clamp */
1697
1698 /* Hardware has the following non-natural restrictions on the value
1699 * of GE_CNTL.VERT_GRP_SIZE based on based on the primitive type of
1700 * the draw:
1701 * - at most 252 for any line input primitive type
1702 * - at most 251 for any quad input primitive type
1703 * - at most 251 for triangle strips with adjacency (this happens to
1704 * be the natural limit for triangle *lists* with adjacency)
1705 */
1706 max_esverts_base = MIN2(max_esverts_base, 251 + max_verts_per_prim - 1);
1707
1708 if (gs_type == MESA_SHADER_GEOMETRY) {
1709 unsigned max_out_verts_per_gsprim =
1710 gs_info->gs.vertices_out * gs_num_invocations;
1711
1712 if (max_out_verts_per_gsprim <= 256) {
1713 if (max_out_verts_per_gsprim) {
1714 max_gsprims_base = MIN2(max_gsprims_base,
1715 256 / max_out_verts_per_gsprim);
1716 }
1717 } else {
1718 /* Use special multi-cycling mode in which each GS
1719 * instance gets its own subgroup. Does not work with
1720 * tessellation. */
1721 max_vert_out_per_gs_instance = true;
1722 max_gsprims_base = 1;
1723 max_out_verts_per_gsprim = gs_info->gs.vertices_out;
1724 }
1725
1726 esvert_lds_size = es_info->esgs_itemsize / 4;
1727 gsprim_lds_size = (gs_info->gs.gsvs_vertex_size / 4 + 1) * max_out_verts_per_gsprim;
1728 } else {
1729 /* VS and TES. */
1730 /* LDS size for passing data from GS to ES. */
1731 struct radv_streamout_info *so_info = nir[MESA_SHADER_TESS_CTRL]
1732 ? &infos[MESA_SHADER_TESS_EVAL].so
1733 : &infos[MESA_SHADER_VERTEX].so;
1734
1735 if (so_info->num_outputs)
1736 esvert_lds_size = 4 * so_info->num_outputs + 1;
1737
1738 /* GS stores Primitive IDs (one DWORD) into LDS at the address
1739 * corresponding to the ES thread of the provoking vertex. All
1740 * ES threads load and export PrimitiveID for their thread.
1741 */
1742 if (!nir[MESA_SHADER_TESS_CTRL] &&
1743 infos[MESA_SHADER_VERTEX].vs.outinfo.export_prim_id)
1744 esvert_lds_size = MAX2(esvert_lds_size, 1);
1745 }
1746
1747 unsigned max_gsprims = max_gsprims_base;
1748 unsigned max_esverts = max_esverts_base;
1749
1750 if (esvert_lds_size)
1751 max_esverts = MIN2(max_esverts, target_lds_size / esvert_lds_size);
1752 if (gsprim_lds_size)
1753 max_gsprims = MIN2(max_gsprims, target_lds_size / gsprim_lds_size);
1754
1755 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1756 clamp_gsprims_to_esverts(&max_gsprims, max_esverts, min_verts_per_prim, uses_adjacency);
1757 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1758
1759 if (esvert_lds_size || gsprim_lds_size) {
1760 /* Now that we have a rough proportionality between esverts
1761 * and gsprims based on the primitive type, scale both of them
1762 * down simultaneously based on required LDS space.
1763 *
1764 * We could be smarter about this if we knew how much vertex
1765 * reuse to expect.
1766 */
1767 unsigned lds_total = max_esverts * esvert_lds_size +
1768 max_gsprims * gsprim_lds_size;
1769 if (lds_total > target_lds_size) {
1770 max_esverts = max_esverts * target_lds_size / lds_total;
1771 max_gsprims = max_gsprims * target_lds_size / lds_total;
1772
1773 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1774 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1775 min_verts_per_prim, uses_adjacency);
1776 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1777 }
1778 }
1779
1780 /* Round up towards full wave sizes for better ALU utilization. */
1781 if (!max_vert_out_per_gs_instance) {
1782 unsigned orig_max_esverts;
1783 unsigned orig_max_gsprims;
1784 unsigned wavesize;
1785
1786 if (gs_type == MESA_SHADER_GEOMETRY) {
1787 wavesize = gs_info->wave_size;
1788 } else {
1789 wavesize = nir[MESA_SHADER_TESS_CTRL]
1790 ? infos[MESA_SHADER_TESS_EVAL].wave_size
1791 : infos[MESA_SHADER_VERTEX].wave_size;
1792 }
1793
1794 do {
1795 orig_max_esverts = max_esverts;
1796 orig_max_gsprims = max_gsprims;
1797
1798 max_esverts = align(max_esverts, wavesize);
1799 max_esverts = MIN2(max_esverts, max_esverts_base);
1800 if (esvert_lds_size)
1801 max_esverts = MIN2(max_esverts,
1802 (max_lds_size - max_gsprims * gsprim_lds_size) /
1803 esvert_lds_size);
1804 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1805
1806 max_gsprims = align(max_gsprims, wavesize);
1807 max_gsprims = MIN2(max_gsprims, max_gsprims_base);
1808 if (gsprim_lds_size)
1809 max_gsprims = MIN2(max_gsprims,
1810 (max_lds_size - max_esverts * esvert_lds_size) /
1811 gsprim_lds_size);
1812 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1813 min_verts_per_prim, uses_adjacency);
1814 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1815 } while (orig_max_esverts != max_esverts || orig_max_gsprims != max_gsprims);
1816 }
1817
1818 /* Hardware restriction: minimum value of max_esverts */
1819 max_esverts = MAX2(max_esverts, 23 + max_verts_per_prim);
1820
1821 unsigned max_out_vertices =
1822 max_vert_out_per_gs_instance ? gs_info->gs.vertices_out :
1823 gs_type == MESA_SHADER_GEOMETRY ?
1824 max_gsprims * gs_num_invocations * gs_info->gs.vertices_out :
1825 max_esverts;
1826 assert(max_out_vertices <= 256);
1827
1828 unsigned prim_amp_factor = 1;
1829 if (gs_type == MESA_SHADER_GEOMETRY) {
1830 /* Number of output primitives per GS input primitive after
1831 * GS instancing. */
1832 prim_amp_factor = gs_info->gs.vertices_out;
1833 }
1834
1835 /* The GE only checks against the maximum number of ES verts after
1836 * allocating a full GS primitive. So we need to ensure that whenever
1837 * this check passes, there is enough space for a full primitive without
1838 * vertex reuse.
1839 */
1840 ngg->hw_max_esverts = max_esverts - max_verts_per_prim + 1;
1841 ngg->max_gsprims = max_gsprims;
1842 ngg->max_out_verts = max_out_vertices;
1843 ngg->prim_amp_factor = prim_amp_factor;
1844 ngg->max_vert_out_per_gs_instance = max_vert_out_per_gs_instance;
1845 ngg->ngg_emit_size = max_gsprims * gsprim_lds_size;
1846 ngg->esgs_ring_size = 4 * max_esverts * esvert_lds_size;
1847
1848 if (gs_type == MESA_SHADER_GEOMETRY) {
1849 ngg->vgt_esgs_ring_itemsize = es_info->esgs_itemsize / 4;
1850 } else {
1851 ngg->vgt_esgs_ring_itemsize = 1;
1852 }
1853
1854 pipeline->graphics.esgs_ring_size = ngg->esgs_ring_size;
1855
1856 assert(ngg->hw_max_esverts >= 24); /* HW limitation */
1857 }
1858
1859 static void
1860 calculate_gs_ring_sizes(struct radv_pipeline *pipeline,
1861 const struct gfx9_gs_info *gs)
1862 {
1863 struct radv_device *device = pipeline->device;
1864 unsigned num_se = device->physical_device->rad_info.max_se;
1865 unsigned wave_size = 64;
1866 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1867 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
1868 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
1869 */
1870 unsigned gs_vertex_reuse =
1871 (device->physical_device->rad_info.chip_class >= GFX8 ? 32 : 16) * num_se;
1872 unsigned alignment = 256 * num_se;
1873 /* The maximum size is 63.999 MB per SE. */
1874 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1875 struct radv_shader_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1876
1877 /* Calculate the minimum size. */
1878 unsigned min_esgs_ring_size = align(gs->vgt_esgs_ring_itemsize * 4 * gs_vertex_reuse *
1879 wave_size, alignment);
1880 /* These are recommended sizes, not minimum sizes. */
1881 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1882 gs->vgt_esgs_ring_itemsize * 4 * gs_info->gs.vertices_in;
1883 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1884 gs_info->gs.max_gsvs_emit_size;
1885
1886 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1887 esgs_ring_size = align(esgs_ring_size, alignment);
1888 gsvs_ring_size = align(gsvs_ring_size, alignment);
1889
1890 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
1891 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1892
1893 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1894 }
1895
1896 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1897 unsigned *lds_size)
1898 {
1899 /* If tessellation is all offchip and on-chip GS isn't used, this
1900 * workaround is not needed.
1901 */
1902 return;
1903
1904 /* SPI barrier management bug:
1905 * Make sure we have at least 4k of LDS in use to avoid the bug.
1906 * It applies to workgroup sizes of more than one wavefront.
1907 */
1908 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1909 device->physical_device->rad_info.family == CHIP_KABINI)
1910 *lds_size = MAX2(*lds_size, 8);
1911 }
1912
1913 struct radv_shader_variant *
1914 radv_get_shader(struct radv_pipeline *pipeline,
1915 gl_shader_stage stage)
1916 {
1917 if (stage == MESA_SHADER_VERTEX) {
1918 if (pipeline->shaders[MESA_SHADER_VERTEX])
1919 return pipeline->shaders[MESA_SHADER_VERTEX];
1920 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
1921 return pipeline->shaders[MESA_SHADER_TESS_CTRL];
1922 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1923 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1924 } else if (stage == MESA_SHADER_TESS_EVAL) {
1925 if (!radv_pipeline_has_tess(pipeline))
1926 return NULL;
1927 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
1928 return pipeline->shaders[MESA_SHADER_TESS_EVAL];
1929 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1930 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1931 }
1932 return pipeline->shaders[stage];
1933 }
1934
1935 static struct radv_tessellation_state
1936 calculate_tess_state(struct radv_pipeline *pipeline,
1937 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1938 {
1939 unsigned num_tcs_input_cp;
1940 unsigned num_tcs_output_cp;
1941 unsigned lds_size;
1942 unsigned num_patches;
1943 struct radv_tessellation_state tess = {0};
1944
1945 num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1946 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1947 num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
1948
1949 lds_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.lds_size;
1950
1951 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
1952 assert(lds_size <= 65536);
1953 lds_size = align(lds_size, 512) / 512;
1954 } else {
1955 assert(lds_size <= 32768);
1956 lds_size = align(lds_size, 256) / 256;
1957 }
1958 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1959
1960 tess.lds_size = lds_size;
1961
1962 tess.ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1963 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1964 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1965 tess.num_patches = num_patches;
1966
1967 struct radv_shader_variant *tes = radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL);
1968 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1969
1970 switch (tes->info.tes.primitive_mode) {
1971 case GL_TRIANGLES:
1972 type = V_028B6C_TESS_TRIANGLE;
1973 break;
1974 case GL_QUADS:
1975 type = V_028B6C_TESS_QUAD;
1976 break;
1977 case GL_ISOLINES:
1978 type = V_028B6C_TESS_ISOLINE;
1979 break;
1980 }
1981
1982 switch (tes->info.tes.spacing) {
1983 case TESS_SPACING_EQUAL:
1984 partitioning = V_028B6C_PART_INTEGER;
1985 break;
1986 case TESS_SPACING_FRACTIONAL_ODD:
1987 partitioning = V_028B6C_PART_FRAC_ODD;
1988 break;
1989 case TESS_SPACING_FRACTIONAL_EVEN:
1990 partitioning = V_028B6C_PART_FRAC_EVEN;
1991 break;
1992 default:
1993 break;
1994 }
1995
1996 bool ccw = tes->info.tes.ccw;
1997 const VkPipelineTessellationDomainOriginStateCreateInfo *domain_origin_state =
1998 vk_find_struct_const(pCreateInfo->pTessellationState,
1999 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO);
2000
2001 if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT)
2002 ccw = !ccw;
2003
2004 if (tes->info.tes.point_mode)
2005 topology = V_028B6C_OUTPUT_POINT;
2006 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
2007 topology = V_028B6C_OUTPUT_LINE;
2008 else if (ccw)
2009 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
2010 else
2011 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
2012
2013 if (pipeline->device->physical_device->rad_info.has_distributed_tess) {
2014 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
2015 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
2016 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
2017 else
2018 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
2019 } else
2020 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
2021
2022 tess.tf_param = S_028B6C_TYPE(type) |
2023 S_028B6C_PARTITIONING(partitioning) |
2024 S_028B6C_TOPOLOGY(topology) |
2025 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
2026
2027 return tess;
2028 }
2029
2030 static const struct radv_prim_vertex_count prim_size_table[] = {
2031 [V_008958_DI_PT_NONE] = {0, 0},
2032 [V_008958_DI_PT_POINTLIST] = {1, 1},
2033 [V_008958_DI_PT_LINELIST] = {2, 2},
2034 [V_008958_DI_PT_LINESTRIP] = {2, 1},
2035 [V_008958_DI_PT_TRILIST] = {3, 3},
2036 [V_008958_DI_PT_TRIFAN] = {3, 1},
2037 [V_008958_DI_PT_TRISTRIP] = {3, 1},
2038 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
2039 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
2040 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
2041 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
2042 [V_008958_DI_PT_RECTLIST] = {3, 3},
2043 [V_008958_DI_PT_LINELOOP] = {2, 1},
2044 [V_008958_DI_PT_POLYGON] = {3, 1},
2045 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
2046 };
2047
2048 static const struct radv_vs_output_info *get_vs_output_info(const struct radv_pipeline *pipeline)
2049 {
2050 if (radv_pipeline_has_gs(pipeline))
2051 if (radv_pipeline_has_ngg(pipeline))
2052 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.vs.outinfo;
2053 else
2054 return &pipeline->gs_copy_shader->info.vs.outinfo;
2055 else if (radv_pipeline_has_tess(pipeline))
2056 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
2057 else
2058 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
2059 }
2060
2061 static void
2062 radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
2063 {
2064 nir_shader* ordered_shaders[MESA_SHADER_STAGES];
2065 int shader_count = 0;
2066
2067 if(shaders[MESA_SHADER_FRAGMENT]) {
2068 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
2069 }
2070 if(shaders[MESA_SHADER_GEOMETRY]) {
2071 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
2072 }
2073 if(shaders[MESA_SHADER_TESS_EVAL]) {
2074 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
2075 }
2076 if(shaders[MESA_SHADER_TESS_CTRL]) {
2077 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
2078 }
2079 if(shaders[MESA_SHADER_VERTEX]) {
2080 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
2081 }
2082
2083 if (shader_count > 1) {
2084 unsigned first = ordered_shaders[shader_count - 1]->info.stage;
2085 unsigned last = ordered_shaders[0]->info.stage;
2086
2087 if (ordered_shaders[0]->info.stage == MESA_SHADER_FRAGMENT &&
2088 ordered_shaders[1]->info.has_transform_feedback_varyings)
2089 nir_link_xfb_varyings(ordered_shaders[1], ordered_shaders[0]);
2090
2091 for (int i = 0; i < shader_count; ++i) {
2092 nir_variable_mode mask = 0;
2093
2094 if (ordered_shaders[i]->info.stage != first)
2095 mask = mask | nir_var_shader_in;
2096
2097 if (ordered_shaders[i]->info.stage != last)
2098 mask = mask | nir_var_shader_out;
2099
2100 nir_lower_io_to_scalar_early(ordered_shaders[i], mask);
2101 radv_optimize_nir(ordered_shaders[i], false, false);
2102 }
2103 }
2104
2105 for (int i = 1; i < shader_count; ++i) {
2106 nir_lower_io_arrays_to_elements(ordered_shaders[i],
2107 ordered_shaders[i - 1]);
2108
2109 if (nir_link_opt_varyings(ordered_shaders[i],
2110 ordered_shaders[i - 1]))
2111 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2112
2113 nir_remove_dead_variables(ordered_shaders[i],
2114 nir_var_shader_out);
2115 nir_remove_dead_variables(ordered_shaders[i - 1],
2116 nir_var_shader_in);
2117
2118 bool progress = nir_remove_unused_varyings(ordered_shaders[i],
2119 ordered_shaders[i - 1]);
2120
2121 nir_compact_varyings(ordered_shaders[i],
2122 ordered_shaders[i - 1], true);
2123
2124 if (progress) {
2125 if (nir_lower_global_vars_to_local(ordered_shaders[i])) {
2126 ac_lower_indirect_derefs(ordered_shaders[i],
2127 pipeline->device->physical_device->rad_info.chip_class);
2128 }
2129 radv_optimize_nir(ordered_shaders[i], false, false);
2130
2131 if (nir_lower_global_vars_to_local(ordered_shaders[i - 1])) {
2132 ac_lower_indirect_derefs(ordered_shaders[i - 1],
2133 pipeline->device->physical_device->rad_info.chip_class);
2134 }
2135 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2136 }
2137 }
2138 }
2139
2140 static uint32_t
2141 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo *input_state,
2142 uint32_t attrib_binding)
2143 {
2144 for (uint32_t i = 0; i < input_state->vertexBindingDescriptionCount; i++) {
2145 const VkVertexInputBindingDescription *input_binding =
2146 &input_state->pVertexBindingDescriptions[i];
2147
2148 if (input_binding->binding == attrib_binding)
2149 return input_binding->stride;
2150 }
2151
2152 return 0;
2153 }
2154
2155 static struct radv_pipeline_key
2156 radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
2157 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2158 const struct radv_blend_state *blend,
2159 bool has_view_index)
2160 {
2161 const VkPipelineVertexInputStateCreateInfo *input_state =
2162 pCreateInfo->pVertexInputState;
2163 const VkPipelineVertexInputDivisorStateCreateInfoEXT *divisor_state =
2164 vk_find_struct_const(input_state->pNext, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT);
2165
2166 struct radv_pipeline_key key;
2167 memset(&key, 0, sizeof(key));
2168
2169 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
2170 key.optimisations_disabled = 1;
2171
2172 key.has_multiview_view_index = has_view_index;
2173
2174 uint32_t binding_input_rate = 0;
2175 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
2176 for (unsigned i = 0; i < input_state->vertexBindingDescriptionCount; ++i) {
2177 if (input_state->pVertexBindingDescriptions[i].inputRate) {
2178 unsigned binding = input_state->pVertexBindingDescriptions[i].binding;
2179 binding_input_rate |= 1u << binding;
2180 instance_rate_divisors[binding] = 1;
2181 }
2182 }
2183 if (divisor_state) {
2184 for (unsigned i = 0; i < divisor_state->vertexBindingDivisorCount; ++i) {
2185 instance_rate_divisors[divisor_state->pVertexBindingDivisors[i].binding] =
2186 divisor_state->pVertexBindingDivisors[i].divisor;
2187 }
2188 }
2189
2190 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
2191 const VkVertexInputAttributeDescription *desc =
2192 &input_state->pVertexAttributeDescriptions[i];
2193 const struct vk_format_description *format_desc;
2194 unsigned location = desc->location;
2195 unsigned binding = desc->binding;
2196 unsigned num_format, data_format;
2197 int first_non_void;
2198
2199 if (binding_input_rate & (1u << binding)) {
2200 key.instance_rate_inputs |= 1u << location;
2201 key.instance_rate_divisors[location] = instance_rate_divisors[binding];
2202 }
2203
2204 format_desc = vk_format_description(desc->format);
2205 first_non_void = vk_format_get_first_non_void_channel(desc->format);
2206
2207 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
2208 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
2209
2210 key.vertex_attribute_formats[location] = data_format | (num_format << 4);
2211 key.vertex_attribute_bindings[location] = desc->binding;
2212 key.vertex_attribute_offsets[location] = desc->offset;
2213 key.vertex_attribute_strides[location] = radv_get_attrib_stride(input_state, desc->binding);
2214
2215 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8 &&
2216 pipeline->device->physical_device->rad_info.family != CHIP_STONEY) {
2217 VkFormat format = input_state->pVertexAttributeDescriptions[i].format;
2218 uint64_t adjust;
2219 switch(format) {
2220 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2221 case VK_FORMAT_A2B10G10R10_SNORM_PACK32:
2222 adjust = RADV_ALPHA_ADJUST_SNORM;
2223 break;
2224 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2225 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32:
2226 adjust = RADV_ALPHA_ADJUST_SSCALED;
2227 break;
2228 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2229 case VK_FORMAT_A2B10G10R10_SINT_PACK32:
2230 adjust = RADV_ALPHA_ADJUST_SINT;
2231 break;
2232 default:
2233 adjust = 0;
2234 break;
2235 }
2236 key.vertex_alpha_adjust |= adjust << (2 * location);
2237 }
2238
2239 switch (desc->format) {
2240 case VK_FORMAT_B8G8R8A8_UNORM:
2241 case VK_FORMAT_B8G8R8A8_SNORM:
2242 case VK_FORMAT_B8G8R8A8_USCALED:
2243 case VK_FORMAT_B8G8R8A8_SSCALED:
2244 case VK_FORMAT_B8G8R8A8_UINT:
2245 case VK_FORMAT_B8G8R8A8_SINT:
2246 case VK_FORMAT_B8G8R8A8_SRGB:
2247 case VK_FORMAT_A2R10G10B10_UNORM_PACK32:
2248 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2249 case VK_FORMAT_A2R10G10B10_USCALED_PACK32:
2250 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2251 case VK_FORMAT_A2R10G10B10_UINT_PACK32:
2252 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2253 key.vertex_post_shuffle |= 1 << location;
2254 break;
2255 default:
2256 break;
2257 }
2258 }
2259
2260 if (pCreateInfo->pTessellationState)
2261 key.tess_input_vertices = pCreateInfo->pTessellationState->patchControlPoints;
2262
2263
2264 if (pCreateInfo->pMultisampleState &&
2265 pCreateInfo->pMultisampleState->rasterizationSamples > 1) {
2266 uint32_t num_samples = pCreateInfo->pMultisampleState->rasterizationSamples;
2267 uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo->pMultisampleState);
2268 key.num_samples = num_samples;
2269 key.log2_ps_iter_samples = util_logbase2(ps_iter_samples);
2270 }
2271
2272 key.col_format = blend->spi_shader_col_format;
2273 if (pipeline->device->physical_device->rad_info.chip_class < GFX8)
2274 radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.is_int8, &key.is_int10);
2275
2276 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10)
2277 key.topology = pCreateInfo->pInputAssemblyState->topology;
2278
2279 return key;
2280 }
2281
2282 static bool
2283 radv_nir_stage_uses_xfb(const nir_shader *nir)
2284 {
2285 nir_xfb_info *xfb = nir_gather_xfb_info(nir, NULL);
2286 bool uses_xfb = !!xfb;
2287
2288 ralloc_free(xfb);
2289 return uses_xfb;
2290 }
2291
2292 static void
2293 radv_fill_shader_keys(struct radv_device *device,
2294 struct radv_shader_variant_key *keys,
2295 const struct radv_pipeline_key *key,
2296 nir_shader **nir)
2297 {
2298 keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
2299 keys[MESA_SHADER_VERTEX].vs.alpha_adjust = key->vertex_alpha_adjust;
2300 keys[MESA_SHADER_VERTEX].vs.post_shuffle = key->vertex_post_shuffle;
2301 for (unsigned i = 0; i < MAX_VERTEX_ATTRIBS; ++i) {
2302 keys[MESA_SHADER_VERTEX].vs.instance_rate_divisors[i] = key->instance_rate_divisors[i];
2303 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_formats[i] = key->vertex_attribute_formats[i];
2304 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_bindings[i] = key->vertex_attribute_bindings[i];
2305 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_offsets[i] = key->vertex_attribute_offsets[i];
2306 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_strides[i] = key->vertex_attribute_strides[i];
2307 }
2308 keys[MESA_SHADER_VERTEX].vs.outprim = si_conv_prim_to_gs_out(key->topology);
2309
2310 if (nir[MESA_SHADER_TESS_CTRL]) {
2311 keys[MESA_SHADER_VERTEX].vs_common_out.as_ls = true;
2312 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = 0;
2313 keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices;
2314 keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
2315
2316 keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
2317 }
2318
2319 if (nir[MESA_SHADER_GEOMETRY]) {
2320 if (nir[MESA_SHADER_TESS_CTRL])
2321 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_es = true;
2322 else
2323 keys[MESA_SHADER_VERTEX].vs_common_out.as_es = true;
2324 }
2325
2326 if (device->physical_device->use_ngg) {
2327 if (nir[MESA_SHADER_TESS_CTRL]) {
2328 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = true;
2329 } else {
2330 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = true;
2331 }
2332
2333 if (nir[MESA_SHADER_TESS_CTRL] &&
2334 nir[MESA_SHADER_GEOMETRY] &&
2335 nir[MESA_SHADER_GEOMETRY]->info.gs.invocations *
2336 nir[MESA_SHADER_GEOMETRY]->info.gs.vertices_out > 256) {
2337 /* Fallback to the legacy path if tessellation is
2338 * enabled with extreme geometry because
2339 * EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it
2340 * might hang.
2341 */
2342 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2343 }
2344
2345 /*
2346 * Disable NGG with geometry shaders. There are a bunch of
2347 * issues still:
2348 * * GS primitives in pipeline statistic queries do not get
2349 * updates. See dEQP-VK.query_pool.statistics_query.geometry_shader_primitives
2350 *
2351 * Furthermore, XGL/AMDVLK also disables this as of 9b632ef.
2352 */
2353 if (nir[MESA_SHADER_GEOMETRY]) {
2354 if (nir[MESA_SHADER_TESS_CTRL])
2355 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2356 else
2357 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2358 }
2359
2360 if (!device->physical_device->use_ngg_streamout) {
2361 gl_shader_stage last_xfb_stage = MESA_SHADER_VERTEX;
2362
2363 for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
2364 if (nir[i])
2365 last_xfb_stage = i;
2366 }
2367
2368 if (nir[last_xfb_stage] &&
2369 radv_nir_stage_uses_xfb(nir[last_xfb_stage])) {
2370 if (nir[MESA_SHADER_TESS_CTRL])
2371 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2372 else
2373 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2374 }
2375 }
2376 }
2377
2378 for(int i = 0; i < MESA_SHADER_STAGES; ++i)
2379 keys[i].has_multiview_view_index = key->has_multiview_view_index;
2380
2381 keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format;
2382 keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8;
2383 keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
2384 keys[MESA_SHADER_FRAGMENT].fs.log2_ps_iter_samples = key->log2_ps_iter_samples;
2385 keys[MESA_SHADER_FRAGMENT].fs.num_samples = key->num_samples;
2386
2387 if (nir[MESA_SHADER_COMPUTE]) {
2388 keys[MESA_SHADER_COMPUTE].cs.subgroup_size = key->compute_subgroup_size;
2389 }
2390 }
2391
2392 static uint8_t
2393 radv_get_wave_size(struct radv_device *device,
2394 const VkPipelineShaderStageCreateInfo *pStage,
2395 gl_shader_stage stage,
2396 const struct radv_shader_variant_key *key)
2397 {
2398 if (stage == MESA_SHADER_GEOMETRY && !key->vs_common_out.as_ngg)
2399 return 64;
2400 else if (stage == MESA_SHADER_COMPUTE) {
2401 if (key->cs.subgroup_size) {
2402 /* Return the required subgroup size if specified. */
2403 return key->cs.subgroup_size;
2404 }
2405 return device->physical_device->cs_wave_size;
2406 }
2407 else if (stage == MESA_SHADER_FRAGMENT)
2408 return device->physical_device->ps_wave_size;
2409 else
2410 return device->physical_device->ge_wave_size;
2411 }
2412
2413 static void
2414 radv_fill_shader_info(struct radv_pipeline *pipeline,
2415 const VkPipelineShaderStageCreateInfo **pStages,
2416 struct radv_shader_variant_key *keys,
2417 struct radv_shader_info *infos,
2418 nir_shader **nir)
2419 {
2420 unsigned active_stages = 0;
2421 unsigned filled_stages = 0;
2422
2423 for (int i = 0; i < MESA_SHADER_STAGES; i++) {
2424 if (nir[i])
2425 active_stages |= (1 << i);
2426 }
2427
2428 if (nir[MESA_SHADER_FRAGMENT]) {
2429 radv_nir_shader_info_init(&infos[MESA_SHADER_FRAGMENT]);
2430 radv_nir_shader_info_pass(nir[MESA_SHADER_FRAGMENT],
2431 pipeline->layout,
2432 &keys[MESA_SHADER_FRAGMENT],
2433 &infos[MESA_SHADER_FRAGMENT]);
2434
2435 /* TODO: These are no longer used as keys we should refactor this */
2436 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id =
2437 infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
2438 keys[MESA_SHADER_VERTEX].vs_common_out.export_layer_id =
2439 infos[MESA_SHADER_FRAGMENT].ps.layer_input;
2440 keys[MESA_SHADER_VERTEX].vs_common_out.export_clip_dists =
2441 !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
2442 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_prim_id =
2443 infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
2444 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_layer_id =
2445 infos[MESA_SHADER_FRAGMENT].ps.layer_input;
2446 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_clip_dists =
2447 !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
2448
2449 filled_stages |= (1 << MESA_SHADER_FRAGMENT);
2450 }
2451
2452 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
2453 nir[MESA_SHADER_TESS_CTRL]) {
2454 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2455 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2456 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2457
2458 radv_nir_shader_info_init(&infos[MESA_SHADER_TESS_CTRL]);
2459
2460 for (int i = 0; i < 2; i++) {
2461 radv_nir_shader_info_pass(combined_nir[i],
2462 pipeline->layout, &key,
2463 &infos[MESA_SHADER_TESS_CTRL]);
2464 }
2465
2466 keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
2467 infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
2468 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs =
2469 util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written);
2470
2471 filled_stages |= (1 << MESA_SHADER_VERTEX);
2472 filled_stages |= (1 << MESA_SHADER_TESS_CTRL);
2473 }
2474
2475 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
2476 nir[MESA_SHADER_GEOMETRY]) {
2477 gl_shader_stage pre_stage = nir[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2478 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2479
2480 radv_nir_shader_info_init(&infos[MESA_SHADER_GEOMETRY]);
2481
2482 for (int i = 0; i < 2; i++) {
2483 radv_nir_shader_info_pass(combined_nir[i],
2484 pipeline->layout,
2485 &keys[pre_stage],
2486 &infos[MESA_SHADER_GEOMETRY]);
2487 }
2488
2489 filled_stages |= (1 << pre_stage);
2490 filled_stages |= (1 << MESA_SHADER_GEOMETRY);
2491 }
2492
2493 active_stages ^= filled_stages;
2494 while (active_stages) {
2495 int i = u_bit_scan(&active_stages);
2496
2497 if (i == MESA_SHADER_TESS_CTRL) {
2498 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs =
2499 util_last_bit64(infos[MESA_SHADER_VERTEX].vs.ls_outputs_written);
2500 }
2501
2502 if (i == MESA_SHADER_TESS_EVAL) {
2503 keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
2504 infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
2505 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs =
2506 util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written);
2507 }
2508
2509 radv_nir_shader_info_init(&infos[i]);
2510 radv_nir_shader_info_pass(nir[i], pipeline->layout,
2511 &keys[i], &infos[i]);
2512 }
2513
2514 for (int i = 0; i < MESA_SHADER_STAGES; i++) {
2515 if (nir[i])
2516 infos[i].wave_size =
2517 radv_get_wave_size(pipeline->device, pStages[i],
2518 i, &keys[i]);
2519 }
2520 }
2521
2522 static void
2523 merge_tess_info(struct shader_info *tes_info,
2524 const struct shader_info *tcs_info)
2525 {
2526 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2527 *
2528 * "PointMode. Controls generation of points rather than triangles
2529 * or lines. This functionality defaults to disabled, and is
2530 * enabled if either shader stage includes the execution mode.
2531 *
2532 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2533 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2534 * and OutputVertices, it says:
2535 *
2536 * "One mode must be set in at least one of the tessellation
2537 * shader stages."
2538 *
2539 * So, the fields can be set in either the TCS or TES, but they must
2540 * agree if set in both. Our backend looks at TES, so bitwise-or in
2541 * the values from the TCS.
2542 */
2543 assert(tcs_info->tess.tcs_vertices_out == 0 ||
2544 tes_info->tess.tcs_vertices_out == 0 ||
2545 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
2546 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
2547
2548 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2549 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2550 tcs_info->tess.spacing == tes_info->tess.spacing);
2551 tes_info->tess.spacing |= tcs_info->tess.spacing;
2552
2553 assert(tcs_info->tess.primitive_mode == 0 ||
2554 tes_info->tess.primitive_mode == 0 ||
2555 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
2556 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
2557 tes_info->tess.ccw |= tcs_info->tess.ccw;
2558 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
2559 }
2560
2561 static
2562 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT *ext)
2563 {
2564 if (!ext)
2565 return;
2566
2567 if (ext->pPipelineCreationFeedback) {
2568 ext->pPipelineCreationFeedback->flags = 0;
2569 ext->pPipelineCreationFeedback->duration = 0;
2570 }
2571
2572 for (unsigned i = 0; i < ext->pipelineStageCreationFeedbackCount; ++i) {
2573 ext->pPipelineStageCreationFeedbacks[i].flags = 0;
2574 ext->pPipelineStageCreationFeedbacks[i].duration = 0;
2575 }
2576 }
2577
2578 static
2579 void radv_start_feedback(VkPipelineCreationFeedbackEXT *feedback)
2580 {
2581 if (!feedback)
2582 return;
2583
2584 feedback->duration -= radv_get_current_time();
2585 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT;
2586 }
2587
2588 static
2589 void radv_stop_feedback(VkPipelineCreationFeedbackEXT *feedback, bool cache_hit)
2590 {
2591 if (!feedback)
2592 return;
2593
2594 feedback->duration += radv_get_current_time();
2595 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT |
2596 (cache_hit ? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT : 0);
2597 }
2598
2599 static
2600 bool radv_aco_supported_stage(gl_shader_stage stage, bool has_gs, bool has_ts)
2601 {
2602 return (stage == MESA_SHADER_VERTEX && !has_gs && !has_ts) ||
2603 stage == MESA_SHADER_FRAGMENT ||
2604 stage == MESA_SHADER_COMPUTE;
2605 }
2606
2607 void radv_create_shaders(struct radv_pipeline *pipeline,
2608 struct radv_device *device,
2609 struct radv_pipeline_cache *cache,
2610 const struct radv_pipeline_key *key,
2611 const VkPipelineShaderStageCreateInfo **pStages,
2612 const VkPipelineCreateFlags flags,
2613 VkPipelineCreationFeedbackEXT *pipeline_feedback,
2614 VkPipelineCreationFeedbackEXT **stage_feedbacks)
2615 {
2616 struct radv_shader_module fs_m = {0};
2617 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
2618 nir_shader *nir[MESA_SHADER_STAGES] = {0};
2619 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2620 struct radv_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{{0}}}}};
2621 struct radv_shader_info infos[MESA_SHADER_STAGES] = {0};
2622 unsigned char hash[20], gs_copy_hash[20];
2623 bool keep_executable_info = (flags & VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR) || device->keep_shader_info;
2624
2625 radv_start_feedback(pipeline_feedback);
2626
2627 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2628 if (pStages[i]) {
2629 modules[i] = radv_shader_module_from_handle(pStages[i]->module);
2630 if (modules[i]->nir)
2631 _mesa_sha1_compute(modules[i]->nir->info.name,
2632 strlen(modules[i]->nir->info.name),
2633 modules[i]->sha1);
2634
2635 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
2636 }
2637 }
2638
2639 radv_hash_shaders(hash, pStages, pipeline->layout, key, get_hash_flags(device));
2640 memcpy(gs_copy_hash, hash, 20);
2641 gs_copy_hash[0] ^= 1;
2642
2643 bool found_in_application_cache = true;
2644 if (modules[MESA_SHADER_GEOMETRY] && !keep_executable_info) {
2645 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2646 radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants,
2647 &found_in_application_cache);
2648 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
2649 }
2650
2651 if (!keep_executable_info &&
2652 radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders,
2653 &found_in_application_cache) &&
2654 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
2655 radv_stop_feedback(pipeline_feedback, found_in_application_cache);
2656 return;
2657 }
2658
2659 if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
2660 nir_builder fs_b;
2661 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
2662 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
2663 fs_m.nir = fs_b.shader;
2664 modules[MESA_SHADER_FRAGMENT] = &fs_m;
2665 }
2666
2667 bool has_gs = modules[MESA_SHADER_GEOMETRY];
2668 bool has_ts = modules[MESA_SHADER_TESS_CTRL] || modules[MESA_SHADER_TESS_EVAL];
2669 bool use_aco = device->physical_device->use_aco;
2670
2671 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2672 const VkPipelineShaderStageCreateInfo *stage = pStages[i];
2673
2674 if (!modules[i])
2675 continue;
2676
2677 radv_start_feedback(stage_feedbacks[i]);
2678
2679 bool aco = use_aco && radv_aco_supported_stage(i, has_gs, has_ts);
2680 nir[i] = radv_shader_compile_to_nir(device, modules[i],
2681 stage ? stage->pName : "main", i,
2682 stage ? stage->pSpecializationInfo : NULL,
2683 flags, pipeline->layout, aco);
2684
2685 /* We don't want to alter meta shaders IR directly so clone it
2686 * first.
2687 */
2688 if (nir[i]->info.name) {
2689 nir[i] = nir_shader_clone(NULL, nir[i]);
2690 }
2691
2692 radv_stop_feedback(stage_feedbacks[i], false);
2693 }
2694
2695 if (nir[MESA_SHADER_TESS_CTRL]) {
2696 nir_lower_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out, NULL);
2697 merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
2698 }
2699
2700 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
2701 radv_link_shaders(pipeline, nir);
2702
2703 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2704 if (nir[i]) {
2705 NIR_PASS_V(nir[i], nir_lower_non_uniform_access,
2706 nir_lower_non_uniform_ubo_access |
2707 nir_lower_non_uniform_ssbo_access |
2708 nir_lower_non_uniform_texture_access |
2709 nir_lower_non_uniform_image_access);
2710
2711 bool aco = use_aco && radv_aco_supported_stage(i, has_gs, has_ts);
2712 if (!aco)
2713 NIR_PASS_V(nir[i], nir_lower_bool_to_int32);
2714 }
2715
2716 if (radv_can_dump_shader(device, modules[i], false))
2717 nir_print_shader(nir[i], stderr);
2718 }
2719
2720 if (nir[MESA_SHADER_FRAGMENT])
2721 radv_lower_fs_io(nir[MESA_SHADER_FRAGMENT]);
2722
2723 radv_fill_shader_keys(device, keys, key, nir);
2724
2725 radv_fill_shader_info(pipeline, pStages, keys, infos, nir);
2726
2727 if ((nir[MESA_SHADER_VERTEX] &&
2728 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg) ||
2729 (nir[MESA_SHADER_TESS_EVAL] &&
2730 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg)) {
2731 struct gfx10_ngg_info *ngg_info;
2732
2733 if (nir[MESA_SHADER_GEOMETRY])
2734 ngg_info = &infos[MESA_SHADER_GEOMETRY].ngg_info;
2735 else if (nir[MESA_SHADER_TESS_CTRL])
2736 ngg_info = &infos[MESA_SHADER_TESS_EVAL].ngg_info;
2737 else
2738 ngg_info = &infos[MESA_SHADER_VERTEX].ngg_info;
2739
2740 gfx10_get_ngg_info(key, pipeline, nir, infos, ngg_info);
2741 } else if (nir[MESA_SHADER_GEOMETRY]) {
2742 struct gfx9_gs_info *gs_info =
2743 &infos[MESA_SHADER_GEOMETRY].gs_ring_info;
2744
2745 gfx9_get_gs_info(key, pipeline, nir, infos, gs_info);
2746 }
2747
2748 if (nir[MESA_SHADER_FRAGMENT]) {
2749 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
2750 radv_start_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT]);
2751
2752 bool aco = use_aco && radv_aco_supported_stage(MESA_SHADER_FRAGMENT, has_gs, has_ts);
2753 pipeline->shaders[MESA_SHADER_FRAGMENT] =
2754 radv_shader_variant_compile(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
2755 pipeline->layout, keys + MESA_SHADER_FRAGMENT,
2756 infos + MESA_SHADER_FRAGMENT,
2757 keep_executable_info, aco,
2758 &binaries[MESA_SHADER_FRAGMENT]);
2759
2760 radv_stop_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT], false);
2761 }
2762
2763 /* TODO: These are no longer used as keys we should refactor this */
2764 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id =
2765 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.prim_id_input;
2766 keys[MESA_SHADER_VERTEX].vs_common_out.export_layer_id =
2767 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.layer_input;
2768 keys[MESA_SHADER_VERTEX].vs_common_out.export_clip_dists =
2769 !!pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.num_input_clips_culls;
2770 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_prim_id =
2771 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.prim_id_input;
2772 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_layer_id =
2773 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.layer_input;
2774 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_clip_dists =
2775 !!pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.num_input_clips_culls;
2776 }
2777
2778 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
2779 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
2780 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2781 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2782 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2783
2784 radv_start_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL]);
2785
2786 pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_compile(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
2787 pipeline->layout,
2788 &key, &infos[MESA_SHADER_TESS_CTRL], keep_executable_info,
2789 false, &binaries[MESA_SHADER_TESS_CTRL]);
2790
2791 radv_stop_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL], false);
2792 }
2793 modules[MESA_SHADER_VERTEX] = NULL;
2794 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2795 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written);
2796 }
2797
2798 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
2799 gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2800 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
2801 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2802
2803 radv_start_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY]);
2804
2805 pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_compile(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
2806 pipeline->layout,
2807 &keys[pre_stage], &infos[MESA_SHADER_GEOMETRY], keep_executable_info,
2808 false, &binaries[MESA_SHADER_GEOMETRY]);
2809
2810 radv_stop_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY], false);
2811 }
2812 modules[pre_stage] = NULL;
2813 }
2814
2815 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2816 if(modules[i] && !pipeline->shaders[i]) {
2817 if (i == MESA_SHADER_TESS_CTRL) {
2818 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.ls_outputs_written);
2819 }
2820 if (i == MESA_SHADER_TESS_EVAL) {
2821 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2822 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written);
2823 }
2824
2825 radv_start_feedback(stage_feedbacks[i]);
2826
2827 bool aco = use_aco && radv_aco_supported_stage(i, has_gs, has_ts);
2828 pipeline->shaders[i] = radv_shader_variant_compile(device, modules[i], &nir[i], 1,
2829 pipeline->layout,
2830 keys + i, infos + i,keep_executable_info,
2831 aco, &binaries[i]);
2832
2833 radv_stop_feedback(stage_feedbacks[i], false);
2834 }
2835 }
2836
2837 if(modules[MESA_SHADER_GEOMETRY]) {
2838 struct radv_shader_binary *gs_copy_binary = NULL;
2839 if (!pipeline->gs_copy_shader &&
2840 !radv_pipeline_has_ngg(pipeline)) {
2841 struct radv_shader_info info = {};
2842 struct radv_shader_variant_key key = {};
2843
2844 key.has_multiview_view_index =
2845 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index;
2846
2847 radv_nir_shader_info_pass(nir[MESA_SHADER_GEOMETRY],
2848 pipeline->layout, &key,
2849 &info);
2850 info.wave_size = 64; /* Wave32 not supported. */
2851
2852 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
2853 device, nir[MESA_SHADER_GEOMETRY], &info,
2854 &gs_copy_binary, keep_executable_info,
2855 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
2856 }
2857
2858 if (!keep_executable_info && pipeline->gs_copy_shader) {
2859 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2860 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2861
2862 binaries[MESA_SHADER_GEOMETRY] = gs_copy_binary;
2863 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
2864
2865 radv_pipeline_cache_insert_shaders(device, cache,
2866 gs_copy_hash,
2867 variants,
2868 binaries);
2869 }
2870 free(gs_copy_binary);
2871 }
2872
2873 if (!keep_executable_info) {
2874 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
2875 binaries);
2876 }
2877
2878 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2879 free(binaries[i]);
2880 if (nir[i]) {
2881 ralloc_free(nir[i]);
2882
2883 if (radv_can_dump_shader_stats(device, modules[i]))
2884 radv_shader_dump_stats(device,
2885 pipeline->shaders[i],
2886 i, stderr);
2887 }
2888 }
2889
2890 if (fs_m.nir)
2891 ralloc_free(fs_m.nir);
2892
2893 radv_stop_feedback(pipeline_feedback, false);
2894 }
2895
2896 static uint32_t
2897 radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
2898 gl_shader_stage stage, enum chip_class chip_class)
2899 {
2900 bool has_gs = radv_pipeline_has_gs(pipeline);
2901 bool has_tess = radv_pipeline_has_tess(pipeline);
2902 bool has_ngg = radv_pipeline_has_ngg(pipeline);
2903
2904 switch (stage) {
2905 case MESA_SHADER_FRAGMENT:
2906 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
2907 case MESA_SHADER_VERTEX:
2908 if (has_tess) {
2909 if (chip_class >= GFX10) {
2910 return R_00B430_SPI_SHADER_USER_DATA_HS_0;
2911 } else if (chip_class == GFX9) {
2912 return R_00B430_SPI_SHADER_USER_DATA_LS_0;
2913 } else {
2914 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
2915 }
2916
2917 }
2918
2919 if (has_gs) {
2920 if (chip_class >= GFX10) {
2921 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
2922 } else {
2923 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
2924 }
2925 }
2926
2927 if (has_ngg)
2928 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
2929
2930 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
2931 case MESA_SHADER_GEOMETRY:
2932 return chip_class == GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
2933 R_00B230_SPI_SHADER_USER_DATA_GS_0;
2934 case MESA_SHADER_COMPUTE:
2935 return R_00B900_COMPUTE_USER_DATA_0;
2936 case MESA_SHADER_TESS_CTRL:
2937 return chip_class == GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
2938 R_00B430_SPI_SHADER_USER_DATA_HS_0;
2939 case MESA_SHADER_TESS_EVAL:
2940 if (has_gs) {
2941 return chip_class >= GFX10 ? R_00B230_SPI_SHADER_USER_DATA_GS_0 :
2942 R_00B330_SPI_SHADER_USER_DATA_ES_0;
2943 } else if (has_ngg) {
2944 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
2945 } else {
2946 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
2947 }
2948 default:
2949 unreachable("unknown shader");
2950 }
2951 }
2952
2953 struct radv_bin_size_entry {
2954 unsigned bpp;
2955 VkExtent2D extent;
2956 };
2957
2958 static VkExtent2D
2959 radv_gfx9_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
2960 {
2961 static const struct radv_bin_size_entry color_size_table[][3][9] = {
2962 {
2963 /* One RB / SE */
2964 {
2965 /* One shader engine */
2966 { 0, {128, 128}},
2967 { 1, { 64, 128}},
2968 { 2, { 32, 128}},
2969 { 3, { 16, 128}},
2970 { 17, { 0, 0}},
2971 { UINT_MAX, { 0, 0}},
2972 },
2973 {
2974 /* Two shader engines */
2975 { 0, {128, 128}},
2976 { 2, { 64, 128}},
2977 { 3, { 32, 128}},
2978 { 5, { 16, 128}},
2979 { 17, { 0, 0}},
2980 { UINT_MAX, { 0, 0}},
2981 },
2982 {
2983 /* Four shader engines */
2984 { 0, {128, 128}},
2985 { 3, { 64, 128}},
2986 { 5, { 16, 128}},
2987 { 17, { 0, 0}},
2988 { UINT_MAX, { 0, 0}},
2989 },
2990 },
2991 {
2992 /* Two RB / SE */
2993 {
2994 /* One shader engine */
2995 { 0, {128, 128}},
2996 { 2, { 64, 128}},
2997 { 3, { 32, 128}},
2998 { 5, { 16, 128}},
2999 { 33, { 0, 0}},
3000 { UINT_MAX, { 0, 0}},
3001 },
3002 {
3003 /* Two shader engines */
3004 { 0, {128, 128}},
3005 { 3, { 64, 128}},
3006 { 5, { 32, 128}},
3007 { 9, { 16, 128}},
3008 { 33, { 0, 0}},
3009 { UINT_MAX, { 0, 0}},
3010 },
3011 {
3012 /* Four shader engines */
3013 { 0, {256, 256}},
3014 { 2, {128, 256}},
3015 { 3, {128, 128}},
3016 { 5, { 64, 128}},
3017 { 9, { 16, 128}},
3018 { 33, { 0, 0}},
3019 { UINT_MAX, { 0, 0}},
3020 },
3021 },
3022 {
3023 /* Four RB / SE */
3024 {
3025 /* One shader engine */
3026 { 0, {128, 256}},
3027 { 2, {128, 128}},
3028 { 3, { 64, 128}},
3029 { 5, { 32, 128}},
3030 { 9, { 16, 128}},
3031 { 33, { 0, 0}},
3032 { UINT_MAX, { 0, 0}},
3033 },
3034 {
3035 /* Two shader engines */
3036 { 0, {256, 256}},
3037 { 2, {128, 256}},
3038 { 3, {128, 128}},
3039 { 5, { 64, 128}},
3040 { 9, { 32, 128}},
3041 { 17, { 16, 128}},
3042 { 33, { 0, 0}},
3043 { UINT_MAX, { 0, 0}},
3044 },
3045 {
3046 /* Four shader engines */
3047 { 0, {256, 512}},
3048 { 2, {256, 256}},
3049 { 3, {128, 256}},
3050 { 5, {128, 128}},
3051 { 9, { 64, 128}},
3052 { 17, { 16, 128}},
3053 { 33, { 0, 0}},
3054 { UINT_MAX, { 0, 0}},
3055 },
3056 },
3057 };
3058 static const struct radv_bin_size_entry ds_size_table[][3][9] = {
3059 {
3060 // One RB / SE
3061 {
3062 // One shader engine
3063 { 0, {128, 256}},
3064 { 2, {128, 128}},
3065 { 4, { 64, 128}},
3066 { 7, { 32, 128}},
3067 { 13, { 16, 128}},
3068 { 49, { 0, 0}},
3069 { UINT_MAX, { 0, 0}},
3070 },
3071 {
3072 // Two shader engines
3073 { 0, {256, 256}},
3074 { 2, {128, 256}},
3075 { 4, {128, 128}},
3076 { 7, { 64, 128}},
3077 { 13, { 32, 128}},
3078 { 25, { 16, 128}},
3079 { 49, { 0, 0}},
3080 { UINT_MAX, { 0, 0}},
3081 },
3082 {
3083 // Four shader engines
3084 { 0, {256, 512}},
3085 { 2, {256, 256}},
3086 { 4, {128, 256}},
3087 { 7, {128, 128}},
3088 { 13, { 64, 128}},
3089 { 25, { 16, 128}},
3090 { 49, { 0, 0}},
3091 { UINT_MAX, { 0, 0}},
3092 },
3093 },
3094 {
3095 // Two RB / SE
3096 {
3097 // One shader engine
3098 { 0, {256, 256}},
3099 { 2, {128, 256}},
3100 { 4, {128, 128}},
3101 { 7, { 64, 128}},
3102 { 13, { 32, 128}},
3103 { 25, { 16, 128}},
3104 { 97, { 0, 0}},
3105 { UINT_MAX, { 0, 0}},
3106 },
3107 {
3108 // Two shader engines
3109 { 0, {256, 512}},
3110 { 2, {256, 256}},
3111 { 4, {128, 256}},
3112 { 7, {128, 128}},
3113 { 13, { 64, 128}},
3114 { 25, { 32, 128}},
3115 { 49, { 16, 128}},
3116 { 97, { 0, 0}},
3117 { UINT_MAX, { 0, 0}},
3118 },
3119 {
3120 // Four shader engines
3121 { 0, {512, 512}},
3122 { 2, {256, 512}},
3123 { 4, {256, 256}},
3124 { 7, {128, 256}},
3125 { 13, {128, 128}},
3126 { 25, { 64, 128}},
3127 { 49, { 16, 128}},
3128 { 97, { 0, 0}},
3129 { UINT_MAX, { 0, 0}},
3130 },
3131 },
3132 {
3133 // Four RB / SE
3134 {
3135 // One shader engine
3136 { 0, {256, 512}},
3137 { 2, {256, 256}},
3138 { 4, {128, 256}},
3139 { 7, {128, 128}},
3140 { 13, { 64, 128}},
3141 { 25, { 32, 128}},
3142 { 49, { 16, 128}},
3143 { UINT_MAX, { 0, 0}},
3144 },
3145 {
3146 // Two shader engines
3147 { 0, {512, 512}},
3148 { 2, {256, 512}},
3149 { 4, {256, 256}},
3150 { 7, {128, 256}},
3151 { 13, {128, 128}},
3152 { 25, { 64, 128}},
3153 { 49, { 32, 128}},
3154 { 97, { 16, 128}},
3155 { UINT_MAX, { 0, 0}},
3156 },
3157 {
3158 // Four shader engines
3159 { 0, {512, 512}},
3160 { 4, {256, 512}},
3161 { 7, {256, 256}},
3162 { 13, {128, 256}},
3163 { 25, {128, 128}},
3164 { 49, { 64, 128}},
3165 { 97, { 16, 128}},
3166 { UINT_MAX, { 0, 0}},
3167 },
3168 },
3169 };
3170
3171 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3172 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3173 VkExtent2D extent = {512, 512};
3174
3175 unsigned log_num_rb_per_se =
3176 util_logbase2_ceil(pipeline->device->physical_device->rad_info.num_render_backends /
3177 pipeline->device->physical_device->rad_info.max_se);
3178 unsigned log_num_se = util_logbase2_ceil(pipeline->device->physical_device->rad_info.max_se);
3179
3180 unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
3181 unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->graphics.ms.db_eqaa);
3182 unsigned effective_samples = total_samples;
3183 unsigned color_bytes_per_pixel = 0;
3184
3185 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
3186 if (vkblend) {
3187 for (unsigned i = 0; i < subpass->color_count; i++) {
3188 if (!vkblend->pAttachments[i].colorWriteMask)
3189 continue;
3190
3191 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3192 continue;
3193
3194 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3195 color_bytes_per_pixel += vk_format_get_blocksize(format);
3196 }
3197
3198 /* MSAA images typically don't use all samples all the time. */
3199 if (effective_samples >= 2 && ps_iter_samples <= 1)
3200 effective_samples = 2;
3201 color_bytes_per_pixel *= effective_samples;
3202 }
3203
3204 const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se];
3205 while(color_entry[1].bpp <= color_bytes_per_pixel)
3206 ++color_entry;
3207
3208 extent = color_entry->extent;
3209
3210 if (subpass->depth_stencil_attachment) {
3211 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3212
3213 /* Coefficients taken from AMDVLK */
3214 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
3215 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
3216 unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples;
3217
3218 const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se];
3219 while(ds_entry[1].bpp <= ds_bytes_per_pixel)
3220 ++ds_entry;
3221
3222 if (ds_entry->extent.width * ds_entry->extent.height < extent.width * extent.height)
3223 extent = ds_entry->extent;
3224 }
3225
3226 return extent;
3227 }
3228
3229 static VkExtent2D
3230 radv_gfx10_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
3231 {
3232 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3233 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3234 VkExtent2D extent = {512, 512};
3235
3236 const unsigned db_tag_size = 64;
3237 const unsigned db_tag_count = 312;
3238 const unsigned color_tag_size = 1024;
3239 const unsigned color_tag_count = 31;
3240 const unsigned fmask_tag_size = 256;
3241 const unsigned fmask_tag_count = 44;
3242
3243 const unsigned rb_count = pipeline->device->physical_device->rad_info.num_render_backends;
3244 const unsigned pipe_count = MAX2(rb_count, pipeline->device->physical_device->rad_info.num_sdp_interfaces);
3245
3246 const unsigned db_tag_part = (db_tag_count * rb_count / pipe_count) * db_tag_size * pipe_count;
3247 const unsigned color_tag_part = (color_tag_count * rb_count / pipe_count) * color_tag_size * pipe_count;
3248 const unsigned fmask_tag_part = (fmask_tag_count * rb_count / pipe_count) * fmask_tag_size * pipe_count;
3249
3250 const unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
3251 const unsigned samples_log = util_logbase2_ceil(total_samples);
3252
3253 unsigned color_bytes_per_pixel = 0;
3254 unsigned fmask_bytes_per_pixel = 0;
3255
3256 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
3257 if (vkblend) {
3258 for (unsigned i = 0; i < subpass->color_count; i++) {
3259 if (!vkblend->pAttachments[i].colorWriteMask)
3260 continue;
3261
3262 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3263 continue;
3264
3265 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3266 color_bytes_per_pixel += vk_format_get_blocksize(format);
3267
3268 if (total_samples > 1) {
3269 assert(samples_log <= 3);
3270 const unsigned fmask_array[] = {0, 1, 1, 4};
3271 fmask_bytes_per_pixel += fmask_array[samples_log];
3272 }
3273 }
3274
3275 color_bytes_per_pixel *= total_samples;
3276 }
3277 color_bytes_per_pixel = MAX2(color_bytes_per_pixel, 1);
3278
3279 const unsigned color_pixel_count_log = util_logbase2(color_tag_part / color_bytes_per_pixel);
3280 extent.width = 1ull << ((color_pixel_count_log + 1) / 2);
3281 extent.height = 1ull << (color_pixel_count_log / 2);
3282
3283 if (fmask_bytes_per_pixel) {
3284 const unsigned fmask_pixel_count_log = util_logbase2(fmask_tag_part / fmask_bytes_per_pixel);
3285
3286 const VkExtent2D fmask_extent = (VkExtent2D){
3287 .width = 1ull << ((fmask_pixel_count_log + 1) / 2),
3288 .height = 1ull << (color_pixel_count_log / 2)
3289 };
3290
3291 if (fmask_extent.width * fmask_extent.height < extent.width * extent.height)
3292 extent = fmask_extent;
3293 }
3294
3295 if (subpass->depth_stencil_attachment) {
3296 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3297
3298 /* Coefficients taken from AMDVLK */
3299 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
3300 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
3301 unsigned db_bytes_per_pixel = (depth_coeff + stencil_coeff) * total_samples;
3302
3303 const unsigned db_pixel_count_log = util_logbase2(db_tag_part / db_bytes_per_pixel);
3304
3305 const VkExtent2D db_extent = (VkExtent2D){
3306 .width = 1ull << ((db_pixel_count_log + 1) / 2),
3307 .height = 1ull << (color_pixel_count_log / 2)
3308 };
3309
3310 if (db_extent.width * db_extent.height < extent.width * extent.height)
3311 extent = db_extent;
3312 }
3313
3314 extent.width = MAX2(extent.width, 128);
3315 extent.height = MAX2(extent.width, 64);
3316
3317 return extent;
3318 }
3319
3320 static void
3321 radv_pipeline_generate_disabled_binning_state(struct radeon_cmdbuf *ctx_cs,
3322 struct radv_pipeline *pipeline,
3323 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3324 {
3325 uint32_t pa_sc_binner_cntl_0 =
3326 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
3327 S_028C44_DISABLE_START_OF_PRIM(1);
3328 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
3329
3330 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3331 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3332 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3333 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
3334 unsigned min_bytes_per_pixel = 0;
3335
3336 if (vkblend) {
3337 for (unsigned i = 0; i < subpass->color_count; i++) {
3338 if (!vkblend->pAttachments[i].colorWriteMask)
3339 continue;
3340
3341 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3342 continue;
3343
3344 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3345 unsigned bytes = vk_format_get_blocksize(format);
3346 if (!min_bytes_per_pixel || bytes < min_bytes_per_pixel)
3347 min_bytes_per_pixel = bytes;
3348 }
3349 }
3350
3351 pa_sc_binner_cntl_0 =
3352 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC) |
3353 S_028C44_BIN_SIZE_X(0) |
3354 S_028C44_BIN_SIZE_Y(0) |
3355 S_028C44_BIN_SIZE_X_EXTEND(2) | /* 128 */
3356 S_028C44_BIN_SIZE_Y_EXTEND(min_bytes_per_pixel <= 4 ? 2 : 1) | /* 128 or 64 */
3357 S_028C44_DISABLE_START_OF_PRIM(1);
3358 }
3359
3360 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
3361 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
3362 }
3363
3364 static void
3365 radv_pipeline_generate_binning_state(struct radeon_cmdbuf *ctx_cs,
3366 struct radv_pipeline *pipeline,
3367 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3368 const struct radv_blend_state *blend)
3369 {
3370 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
3371 return;
3372
3373 VkExtent2D bin_size;
3374 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3375 bin_size = radv_gfx10_compute_bin_size(pipeline, pCreateInfo);
3376 } else if (pipeline->device->physical_device->rad_info.chip_class == GFX9) {
3377 bin_size = radv_gfx9_compute_bin_size(pipeline, pCreateInfo);
3378 } else
3379 unreachable("Unhandled generation for binning bin size calculation");
3380
3381 if (pipeline->device->pbb_allowed && bin_size.width && bin_size.height) {
3382 unsigned context_states_per_bin; /* allowed range: [1, 6] */
3383 unsigned persistent_states_per_bin; /* allowed range: [1, 32] */
3384 unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */
3385
3386 if (pipeline->device->physical_device->rad_info.has_dedicated_vram) {
3387 context_states_per_bin = 1;
3388 persistent_states_per_bin = 1;
3389 fpovs_per_batch = 63;
3390 } else {
3391 /* The context states are affected by the scissor bug. */
3392 context_states_per_bin = pipeline->device->physical_device->rad_info.has_gfx9_scissor_bug ? 1 : 6;
3393 /* 32 causes hangs for RAVEN. */
3394 persistent_states_per_bin = 16;
3395 fpovs_per_batch = 63;
3396 }
3397
3398 bool disable_start_of_prim = true;
3399 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
3400
3401 const struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3402
3403 if (pipeline->device->dfsm_allowed && ps &&
3404 !ps->info.ps.can_discard &&
3405 !ps->info.ps.writes_memory &&
3406 blend->cb_target_enabled_4bit) {
3407 db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_AUTO);
3408 disable_start_of_prim = (blend->blend_enable_4bit & blend->cb_target_enabled_4bit) != 0;
3409 }
3410
3411 const uint32_t pa_sc_binner_cntl_0 =
3412 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
3413 S_028C44_BIN_SIZE_X(bin_size.width == 16) |
3414 S_028C44_BIN_SIZE_Y(bin_size.height == 16) |
3415 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size.width, 32)) - 5) |
3416 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size.height, 32)) - 5) |
3417 S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin - 1) |
3418 S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin - 1) |
3419 S_028C44_DISABLE_START_OF_PRIM(disable_start_of_prim) |
3420 S_028C44_FPOVS_PER_BATCH(fpovs_per_batch) |
3421 S_028C44_OPTIMAL_BIN_SELECTION(1);
3422
3423 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
3424 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
3425 } else
3426 radv_pipeline_generate_disabled_binning_state(ctx_cs, pipeline, pCreateInfo);
3427 }
3428
3429
3430 static void
3431 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf *ctx_cs,
3432 struct radv_pipeline *pipeline,
3433 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3434 const struct radv_graphics_pipeline_create_info *extra)
3435 {
3436 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
3437 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3438 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3439 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3440 struct radv_render_pass_attachment *attachment = NULL;
3441 uint32_t db_depth_control = 0, db_stencil_control = 0;
3442 uint32_t db_render_control = 0, db_render_override2 = 0;
3443 uint32_t db_render_override = 0;
3444
3445 if (subpass->depth_stencil_attachment)
3446 attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3447
3448 bool has_depth_attachment = attachment && vk_format_is_depth(attachment->format);
3449 bool has_stencil_attachment = attachment && vk_format_is_stencil(attachment->format);
3450
3451 if (vkds && has_depth_attachment) {
3452 db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
3453 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
3454 S_028800_ZFUNC(vkds->depthCompareOp) |
3455 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
3456
3457 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
3458 db_render_override2 |= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment->samples > 2);
3459 }
3460
3461 if (has_stencil_attachment && vkds && vkds->stencilTestEnable) {
3462 db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
3463 db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
3464 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
3465 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
3466 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
3467
3468 db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
3469 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
3470 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
3471 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
3472 }
3473
3474 if (attachment && extra) {
3475 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
3476 db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
3477
3478 db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
3479 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
3480 db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
3481 db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
3482 db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
3483 }
3484
3485 db_render_override |= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3486 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
3487
3488 if (!pCreateInfo->pRasterizationState->depthClampEnable &&
3489 ps->info.ps.writes_z) {
3490 /* From VK_EXT_depth_range_unrestricted spec:
3491 *
3492 * "The behavior described in Primitive Clipping still applies.
3493 * If depth clamping is disabled the depth values are still
3494 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
3495 * depth clamping is enabled the above equation is ignored and
3496 * the depth values are instead clamped to the VkViewport
3497 * minDepth and maxDepth values, which in the case of this
3498 * extension can be outside of the 0.0 to 1.0 range."
3499 */
3500 db_render_override |= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
3501 }
3502
3503 radeon_set_context_reg(ctx_cs, R_028800_DB_DEPTH_CONTROL, db_depth_control);
3504 radeon_set_context_reg(ctx_cs, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
3505
3506 radeon_set_context_reg(ctx_cs, R_028000_DB_RENDER_CONTROL, db_render_control);
3507 radeon_set_context_reg(ctx_cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
3508 radeon_set_context_reg(ctx_cs, R_028010_DB_RENDER_OVERRIDE2, db_render_override2);
3509 }
3510
3511 static void
3512 radv_pipeline_generate_blend_state(struct radeon_cmdbuf *ctx_cs,
3513 struct radv_pipeline *pipeline,
3514 const struct radv_blend_state *blend)
3515 {
3516 radeon_set_context_reg_seq(ctx_cs, R_028780_CB_BLEND0_CONTROL, 8);
3517 radeon_emit_array(ctx_cs, blend->cb_blend_control,
3518 8);
3519 radeon_set_context_reg(ctx_cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control);
3520 radeon_set_context_reg(ctx_cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask);
3521
3522 if (pipeline->device->physical_device->rad_info.has_rbplus) {
3523
3524 radeon_set_context_reg_seq(ctx_cs, R_028760_SX_MRT0_BLEND_OPT, 8);
3525 radeon_emit_array(ctx_cs, blend->sx_mrt_blend_opt, 8);
3526 }
3527
3528 radeon_set_context_reg(ctx_cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
3529
3530 radeon_set_context_reg(ctx_cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
3531 radeon_set_context_reg(ctx_cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
3532
3533 pipeline->graphics.col_format = blend->spi_shader_col_format;
3534 pipeline->graphics.cb_target_mask = blend->cb_target_mask;
3535 }
3536
3537 static const VkConservativeRasterizationModeEXT
3538 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo *pCreateInfo)
3539 {
3540 const VkPipelineRasterizationConservativeStateCreateInfoEXT *conservative_raster =
3541 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT);
3542
3543 if (!conservative_raster)
3544 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT;
3545 return conservative_raster->conservativeRasterizationMode;
3546 }
3547
3548 static void
3549 radv_pipeline_generate_raster_state(struct radeon_cmdbuf *ctx_cs,
3550 struct radv_pipeline *pipeline,
3551 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3552 {
3553 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
3554 const VkConservativeRasterizationModeEXT mode =
3555 radv_get_conservative_raster_mode(vkraster);
3556 uint32_t pa_sc_conservative_rast = S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
3557 bool depth_clip_disable = vkraster->depthClampEnable;
3558
3559 const VkPipelineRasterizationDepthClipStateCreateInfoEXT *depth_clip_state =
3560 vk_find_struct_const(vkraster->pNext, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT);
3561 if (depth_clip_state) {
3562 depth_clip_disable = !depth_clip_state->depthClipEnable;
3563 }
3564
3565 radeon_set_context_reg(ctx_cs, R_028810_PA_CL_CLIP_CNTL,
3566 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
3567 S_028810_ZCLIP_NEAR_DISABLE(depth_clip_disable ? 1 : 0) |
3568 S_028810_ZCLIP_FAR_DISABLE(depth_clip_disable ? 1 : 0) |
3569 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
3570 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
3571
3572 radeon_set_context_reg(ctx_cs, R_0286D4_SPI_INTERP_CONTROL_0,
3573 S_0286D4_FLAT_SHADE_ENA(1) |
3574 S_0286D4_PNT_SPRITE_ENA(1) |
3575 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
3576 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
3577 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
3578 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
3579 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
3580
3581 radeon_set_context_reg(ctx_cs, R_028BE4_PA_SU_VTX_CNTL,
3582 S_028BE4_PIX_CENTER(1) | // TODO verify
3583 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
3584 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
3585
3586 radeon_set_context_reg(ctx_cs, R_028814_PA_SU_SC_MODE_CNTL,
3587 S_028814_FACE(vkraster->frontFace) |
3588 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
3589 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
3590 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
3591 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
3592 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
3593 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
3594 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
3595 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0));
3596
3597 /* Conservative rasterization. */
3598 if (mode != VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT) {
3599 struct radv_multisample_state *ms = &pipeline->graphics.ms;
3600
3601 ms->pa_sc_aa_config |= S_028BE0_AA_MASK_CENTROID_DTMN(1);
3602 ms->db_eqaa |= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
3603 S_028804_OVERRASTERIZATION_AMOUNT(4);
3604
3605 pa_sc_conservative_rast = S_028C4C_PREZ_AA_MASK_ENABLE(1) |
3606 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
3607 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
3608
3609 if (mode == VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT) {
3610 pa_sc_conservative_rast |=
3611 S_028C4C_OVER_RAST_ENABLE(1) |
3612 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
3613 S_028C4C_UNDER_RAST_ENABLE(0) |
3614 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
3615 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
3616 } else {
3617 assert(mode == VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT);
3618 pa_sc_conservative_rast |=
3619 S_028C4C_OVER_RAST_ENABLE(0) |
3620 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
3621 S_028C4C_UNDER_RAST_ENABLE(1) |
3622 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
3623 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
3624 }
3625 }
3626
3627 radeon_set_context_reg(ctx_cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
3628 pa_sc_conservative_rast);
3629 }
3630
3631
3632 static void
3633 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf *ctx_cs,
3634 struct radv_pipeline *pipeline)
3635 {
3636 struct radv_multisample_state *ms = &pipeline->graphics.ms;
3637
3638 radeon_set_context_reg_seq(ctx_cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3639 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[0]);
3640 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[1]);
3641
3642 radeon_set_context_reg(ctx_cs, R_028804_DB_EQAA, ms->db_eqaa);
3643 radeon_set_context_reg(ctx_cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
3644
3645 /* The exclusion bits can be set to improve rasterization efficiency
3646 * if no sample lies on the pixel boundary (-8 sample offset). It's
3647 * currently always TRUE because the driver doesn't support 16 samples.
3648 */
3649 bool exclusion = pipeline->device->physical_device->rad_info.chip_class >= GFX7;
3650 radeon_set_context_reg(ctx_cs, R_02882C_PA_SU_PRIM_FILTER_CNTL,
3651 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
3652 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
3653 }
3654
3655 static void
3656 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf *ctx_cs,
3657 struct radv_pipeline *pipeline)
3658 {
3659 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3660 const struct radv_shader_variant *vs =
3661 pipeline->shaders[MESA_SHADER_TESS_EVAL] ?
3662 pipeline->shaders[MESA_SHADER_TESS_EVAL] :
3663 pipeline->shaders[MESA_SHADER_VERTEX];
3664 unsigned vgt_primitiveid_en = 0;
3665 uint32_t vgt_gs_mode = 0;
3666
3667 if (radv_pipeline_has_ngg(pipeline))
3668 return;
3669
3670 if (radv_pipeline_has_gs(pipeline)) {
3671 const struct radv_shader_variant *gs =
3672 pipeline->shaders[MESA_SHADER_GEOMETRY];
3673
3674 vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out,
3675 pipeline->device->physical_device->rad_info.chip_class);
3676 } else if (outinfo->export_prim_id || vs->info.uses_prim_id) {
3677 vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
3678 vgt_primitiveid_en |= S_028A84_PRIMITIVEID_EN(1);
3679 }
3680
3681 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN, vgt_primitiveid_en);
3682 radeon_set_context_reg(ctx_cs, R_028A40_VGT_GS_MODE, vgt_gs_mode);
3683 }
3684
3685 static void
3686 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs,
3687 struct radeon_cmdbuf *cs,
3688 struct radv_pipeline *pipeline,
3689 struct radv_shader_variant *shader)
3690 {
3691 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3692
3693 radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
3694 radeon_emit(cs, va >> 8);
3695 radeon_emit(cs, S_00B124_MEM_BASE(va >> 40));
3696 radeon_emit(cs, shader->config.rsrc1);
3697 radeon_emit(cs, shader->config.rsrc2);
3698
3699 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3700 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3701 clip_dist_mask = outinfo->clip_dist_mask;
3702 cull_dist_mask = outinfo->cull_dist_mask;
3703 total_mask = clip_dist_mask | cull_dist_mask;
3704 bool misc_vec_ena = outinfo->writes_pointsize ||
3705 outinfo->writes_layer ||
3706 outinfo->writes_viewport_index;
3707 unsigned spi_vs_out_config, nparams;
3708
3709 /* VS is required to export at least one param. */
3710 nparams = MAX2(outinfo->param_exports, 1);
3711 spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
3712
3713 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3714 spi_vs_out_config |= S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0);
3715 }
3716
3717 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG, spi_vs_out_config);
3718
3719 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
3720 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
3721 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
3722 V_02870C_SPI_SHADER_4COMP :
3723 V_02870C_SPI_SHADER_NONE) |
3724 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
3725 V_02870C_SPI_SHADER_4COMP :
3726 V_02870C_SPI_SHADER_NONE) |
3727 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
3728 V_02870C_SPI_SHADER_4COMP :
3729 V_02870C_SPI_SHADER_NONE));
3730
3731 radeon_set_context_reg(ctx_cs, R_028818_PA_CL_VTE_CNTL,
3732 S_028818_VTX_W0_FMT(1) |
3733 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3734 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3735 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3736
3737 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
3738 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
3739 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
3740 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
3741 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
3742 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
3743 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
3744 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
3745 cull_dist_mask << 8 |
3746 clip_dist_mask);
3747
3748 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
3749 radeon_set_context_reg(ctx_cs, R_028AB4_VGT_REUSE_OFF,
3750 outinfo->writes_viewport_index);
3751 }
3752
3753 static void
3754 radv_pipeline_generate_hw_es(struct radeon_cmdbuf *cs,
3755 struct radv_pipeline *pipeline,
3756 struct radv_shader_variant *shader)
3757 {
3758 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3759
3760 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
3761 radeon_emit(cs, va >> 8);
3762 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3763 radeon_emit(cs, shader->config.rsrc1);
3764 radeon_emit(cs, shader->config.rsrc2);
3765 }
3766
3767 static void
3768 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf *cs,
3769 struct radv_pipeline *pipeline,
3770 struct radv_shader_variant *shader,
3771 const struct radv_tessellation_state *tess)
3772 {
3773 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3774 uint32_t rsrc2 = shader->config.rsrc2;
3775
3776 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
3777 radeon_emit(cs, va >> 8);
3778 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
3779
3780 rsrc2 |= S_00B52C_LDS_SIZE(tess->lds_size);
3781 if (pipeline->device->physical_device->rad_info.chip_class == GFX7 &&
3782 pipeline->device->physical_device->rad_info.family != CHIP_HAWAII)
3783 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
3784
3785 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
3786 radeon_emit(cs, shader->config.rsrc1);
3787 radeon_emit(cs, rsrc2);
3788 }
3789
3790 static void
3791 radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs,
3792 struct radeon_cmdbuf *cs,
3793 struct radv_pipeline *pipeline,
3794 struct radv_shader_variant *shader)
3795 {
3796 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3797 gl_shader_stage es_type =
3798 radv_pipeline_has_tess(pipeline) ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
3799 struct radv_shader_variant *es =
3800 es_type == MESA_SHADER_TESS_EVAL ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX];
3801 const struct gfx10_ngg_info *ngg_state = &shader->info.ngg_info;
3802
3803 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
3804 radeon_emit(cs, va >> 8);
3805 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3806 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
3807 radeon_emit(cs, shader->config.rsrc1);
3808 radeon_emit(cs, shader->config.rsrc2);
3809
3810 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3811 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3812 clip_dist_mask = outinfo->clip_dist_mask;
3813 cull_dist_mask = outinfo->cull_dist_mask;
3814 total_mask = clip_dist_mask | cull_dist_mask;
3815 bool misc_vec_ena = outinfo->writes_pointsize ||
3816 outinfo->writes_layer ||
3817 outinfo->writes_viewport_index;
3818 bool es_enable_prim_id = outinfo->export_prim_id ||
3819 (es && es->info.uses_prim_id);
3820 bool break_wave_at_eoi = false;
3821 unsigned ge_cntl;
3822 unsigned nparams;
3823
3824 if (es_type == MESA_SHADER_TESS_EVAL) {
3825 struct radv_shader_variant *gs =
3826 pipeline->shaders[MESA_SHADER_GEOMETRY];
3827
3828 if (es_enable_prim_id || (gs && gs->info.uses_prim_id))
3829 break_wave_at_eoi = true;
3830 }
3831
3832 nparams = MAX2(outinfo->param_exports, 1);
3833 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG,
3834 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
3835 S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0));
3836
3837 radeon_set_context_reg(ctx_cs, R_028708_SPI_SHADER_IDX_FORMAT,
3838 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP));
3839 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
3840 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
3841 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
3842 V_02870C_SPI_SHADER_4COMP :
3843 V_02870C_SPI_SHADER_NONE) |
3844 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
3845 V_02870C_SPI_SHADER_4COMP :
3846 V_02870C_SPI_SHADER_NONE) |
3847 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
3848 V_02870C_SPI_SHADER_4COMP :
3849 V_02870C_SPI_SHADER_NONE));
3850
3851 radeon_set_context_reg(ctx_cs, R_028818_PA_CL_VTE_CNTL,
3852 S_028818_VTX_W0_FMT(1) |
3853 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3854 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3855 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3856 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
3857 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
3858 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
3859 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
3860 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
3861 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
3862 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
3863 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
3864 cull_dist_mask << 8 |
3865 clip_dist_mask);
3866
3867 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN,
3868 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
3869 S_028A84_NGG_DISABLE_PROVOK_REUSE(es_enable_prim_id));
3870
3871 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
3872 ngg_state->vgt_esgs_ring_itemsize);
3873
3874 /* NGG specific registers. */
3875 struct radv_shader_variant *gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
3876 uint32_t gs_num_invocations = gs ? gs->info.gs.invocations : 1;
3877
3878 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
3879 S_028A44_ES_VERTS_PER_SUBGRP(ngg_state->hw_max_esverts) |
3880 S_028A44_GS_PRIMS_PER_SUBGRP(ngg_state->max_gsprims) |
3881 S_028A44_GS_INST_PRIMS_IN_SUBGRP(ngg_state->max_gsprims * gs_num_invocations));
3882 radeon_set_context_reg(ctx_cs, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
3883 S_0287FC_MAX_VERTS_PER_SUBGROUP(ngg_state->max_out_verts));
3884 radeon_set_context_reg(ctx_cs, R_028B4C_GE_NGG_SUBGRP_CNTL,
3885 S_028B4C_PRIM_AMP_FACTOR(ngg_state->prim_amp_factor) |
3886 S_028B4C_THDS_PER_SUBGRP(0)); /* for fast launch */
3887 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
3888 S_028B90_CNT(gs_num_invocations) |
3889 S_028B90_ENABLE(gs_num_invocations > 1) |
3890 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(ngg_state->max_vert_out_per_gs_instance));
3891
3892 /* User edge flags are set by the pos exports. If user edge flags are
3893 * not used, we must use hw-generated edge flags and pass them via
3894 * the prim export to prevent drawing lines on internal edges of
3895 * decomposed primitives (such as quads) with polygon mode = lines.
3896 *
3897 * TODO: We should combine hw-generated edge flags with user edge
3898 * flags in the shader.
3899 */
3900 radeon_set_context_reg(ctx_cs, R_028838_PA_CL_NGG_CNTL,
3901 S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline) &&
3902 !radv_pipeline_has_gs(pipeline)));
3903
3904 ge_cntl = S_03096C_PRIM_GRP_SIZE(ngg_state->max_gsprims) |
3905 S_03096C_VERT_GRP_SIZE(ngg_state->hw_max_esverts) |
3906 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
3907
3908 /* Bug workaround for a possible hang with non-tessellation cases.
3909 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
3910 *
3911 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
3912 */
3913 if ((pipeline->device->physical_device->rad_info.family == CHIP_NAVI10 ||
3914 pipeline->device->physical_device->rad_info.family == CHIP_NAVI12 ||
3915 pipeline->device->physical_device->rad_info.family == CHIP_NAVI14) &&
3916 !radv_pipeline_has_tess(pipeline) &&
3917 ngg_state->hw_max_esverts != 256) {
3918 ge_cntl &= C_03096C_VERT_GRP_SIZE;
3919
3920 if (ngg_state->hw_max_esverts > 5) {
3921 ge_cntl |= S_03096C_VERT_GRP_SIZE(ngg_state->hw_max_esverts - 5);
3922 }
3923 }
3924
3925 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL, ge_cntl);
3926 }
3927
3928 static void
3929 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf *cs,
3930 struct radv_pipeline *pipeline,
3931 struct radv_shader_variant *shader,
3932 const struct radv_tessellation_state *tess)
3933 {
3934 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3935
3936 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
3937 unsigned hs_rsrc2 = shader->config.rsrc2;
3938
3939 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3940 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX10(tess->lds_size);
3941 } else {
3942 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX9(tess->lds_size);
3943 }
3944
3945 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3946 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
3947 radeon_emit(cs, va >> 8);
3948 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
3949 } else {
3950 radeon_set_sh_reg_seq(cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
3951 radeon_emit(cs, va >> 8);
3952 radeon_emit(cs, S_00B414_MEM_BASE(va >> 40));
3953 }
3954
3955 radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
3956 radeon_emit(cs, shader->config.rsrc1);
3957 radeon_emit(cs, hs_rsrc2);
3958 } else {
3959 radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
3960 radeon_emit(cs, va >> 8);
3961 radeon_emit(cs, S_00B424_MEM_BASE(va >> 40));
3962 radeon_emit(cs, shader->config.rsrc1);
3963 radeon_emit(cs, shader->config.rsrc2);
3964 }
3965 }
3966
3967 static void
3968 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf *ctx_cs,
3969 struct radeon_cmdbuf *cs,
3970 struct radv_pipeline *pipeline,
3971 const struct radv_tessellation_state *tess)
3972 {
3973 struct radv_shader_variant *vs;
3974
3975 /* Skip shaders merged into HS/GS */
3976 vs = pipeline->shaders[MESA_SHADER_VERTEX];
3977 if (!vs)
3978 return;
3979
3980 if (vs->info.vs.as_ls)
3981 radv_pipeline_generate_hw_ls(cs, pipeline, vs, tess);
3982 else if (vs->info.vs.as_es)
3983 radv_pipeline_generate_hw_es(cs, pipeline, vs);
3984 else if (vs->info.is_ngg)
3985 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, vs);
3986 else
3987 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, vs);
3988 }
3989
3990 static void
3991 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf *ctx_cs,
3992 struct radeon_cmdbuf *cs,
3993 struct radv_pipeline *pipeline,
3994 const struct radv_tessellation_state *tess)
3995 {
3996 if (!radv_pipeline_has_tess(pipeline))
3997 return;
3998
3999 struct radv_shader_variant *tes, *tcs;
4000
4001 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
4002 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
4003
4004 if (tes) {
4005 if (tes->info.is_ngg) {
4006 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, tes);
4007 } else if (tes->info.tes.as_es)
4008 radv_pipeline_generate_hw_es(cs, pipeline, tes);
4009 else
4010 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, tes);
4011 }
4012
4013 radv_pipeline_generate_hw_hs(cs, pipeline, tcs, tess);
4014
4015 radeon_set_context_reg(ctx_cs, R_028B6C_VGT_TF_PARAM,
4016 tess->tf_param);
4017
4018 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7)
4019 radeon_set_context_reg_idx(ctx_cs, R_028B58_VGT_LS_HS_CONFIG, 2,
4020 tess->ls_hs_config);
4021 else
4022 radeon_set_context_reg(ctx_cs, R_028B58_VGT_LS_HS_CONFIG,
4023 tess->ls_hs_config);
4024
4025 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 &&
4026 !radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) {
4027 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
4028 S_028A44_ES_VERTS_PER_SUBGRP(250) |
4029 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
4030 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
4031 }
4032 }
4033
4034 static void
4035 radv_pipeline_generate_hw_gs(struct radeon_cmdbuf *ctx_cs,
4036 struct radeon_cmdbuf *cs,
4037 struct radv_pipeline *pipeline,
4038 struct radv_shader_variant *gs)
4039 {
4040 const struct gfx9_gs_info *gs_state = &gs->info.gs_ring_info;
4041 unsigned gs_max_out_vertices;
4042 uint8_t *num_components;
4043 uint8_t max_stream;
4044 unsigned offset;
4045 uint64_t va;
4046
4047 gs_max_out_vertices = gs->info.gs.vertices_out;
4048 max_stream = gs->info.gs.max_stream;
4049 num_components = gs->info.gs.num_stream_output_components;
4050
4051 offset = num_components[0] * gs_max_out_vertices;
4052
4053 radeon_set_context_reg_seq(ctx_cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
4054 radeon_emit(ctx_cs, offset);
4055 if (max_stream >= 1)
4056 offset += num_components[1] * gs_max_out_vertices;
4057 radeon_emit(ctx_cs, offset);
4058 if (max_stream >= 2)
4059 offset += num_components[2] * gs_max_out_vertices;
4060 radeon_emit(ctx_cs, offset);
4061 if (max_stream >= 3)
4062 offset += num_components[3] * gs_max_out_vertices;
4063 radeon_set_context_reg(ctx_cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
4064
4065 radeon_set_context_reg_seq(ctx_cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
4066 radeon_emit(ctx_cs, num_components[0]);
4067 radeon_emit(ctx_cs, (max_stream >= 1) ? num_components[1] : 0);
4068 radeon_emit(ctx_cs, (max_stream >= 2) ? num_components[2] : 0);
4069 radeon_emit(ctx_cs, (max_stream >= 3) ? num_components[3] : 0);
4070
4071 uint32_t gs_num_invocations = gs->info.gs.invocations;
4072 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
4073 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
4074 S_028B90_ENABLE(gs_num_invocations > 0));
4075
4076 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
4077 gs_state->vgt_esgs_ring_itemsize);
4078
4079 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
4080
4081 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
4082 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4083 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
4084 radeon_emit(cs, va >> 8);
4085 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
4086 } else {
4087 radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
4088 radeon_emit(cs, va >> 8);
4089 radeon_emit(cs, S_00B214_MEM_BASE(va >> 40));
4090 }
4091
4092 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
4093 radeon_emit(cs, gs->config.rsrc1);
4094 radeon_emit(cs, gs->config.rsrc2 | S_00B22C_LDS_SIZE(gs_state->lds_size));
4095
4096 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL, gs_state->vgt_gs_onchip_cntl);
4097 radeon_set_context_reg(ctx_cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, gs_state->vgt_gs_max_prims_per_subgroup);
4098 } else {
4099 radeon_set_sh_reg_seq(cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
4100 radeon_emit(cs, va >> 8);
4101 radeon_emit(cs, S_00B224_MEM_BASE(va >> 40));
4102 radeon_emit(cs, gs->config.rsrc1);
4103 radeon_emit(cs, gs->config.rsrc2);
4104 }
4105
4106 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, pipeline->gs_copy_shader);
4107 }
4108
4109 static void
4110 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf *ctx_cs,
4111 struct radeon_cmdbuf *cs,
4112 struct radv_pipeline *pipeline)
4113 {
4114 struct radv_shader_variant *gs;
4115
4116 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
4117 if (!gs)
4118 return;
4119
4120 if (gs->info.is_ngg)
4121 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, gs);
4122 else
4123 radv_pipeline_generate_hw_gs(ctx_cs, cs, pipeline, gs);
4124
4125 radeon_set_context_reg(ctx_cs, R_028B38_VGT_GS_MAX_VERT_OUT,
4126 gs->info.gs.vertices_out);
4127 }
4128
4129 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade, bool float16)
4130 {
4131 uint32_t ps_input_cntl;
4132 if (offset <= AC_EXP_PARAM_OFFSET_31) {
4133 ps_input_cntl = S_028644_OFFSET(offset);
4134 if (flat_shade)
4135 ps_input_cntl |= S_028644_FLAT_SHADE(1);
4136 if (float16) {
4137 ps_input_cntl |= S_028644_FP16_INTERP_MODE(1) |
4138 S_028644_ATTR0_VALID(1);
4139 }
4140 } else {
4141 /* The input is a DEFAULT_VAL constant. */
4142 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
4143 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
4144 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
4145 ps_input_cntl = S_028644_OFFSET(0x20) |
4146 S_028644_DEFAULT_VAL(offset);
4147 }
4148 return ps_input_cntl;
4149 }
4150
4151 static void
4152 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf *ctx_cs,
4153 struct radv_pipeline *pipeline)
4154 {
4155 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4156 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
4157 uint32_t ps_input_cntl[32];
4158
4159 unsigned ps_offset = 0;
4160
4161 if (ps->info.ps.prim_id_input) {
4162 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
4163 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
4164 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false);
4165 ++ps_offset;
4166 }
4167 }
4168
4169 if (ps->info.ps.layer_input ||
4170 ps->info.needs_multiview_view_index) {
4171 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
4172 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
4173 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false);
4174 else
4175 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true, false);
4176 ++ps_offset;
4177 }
4178
4179 if (ps->info.ps.has_pcoord) {
4180 unsigned val;
4181 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
4182 ps_input_cntl[ps_offset] = val;
4183 ps_offset++;
4184 }
4185
4186 if (ps->info.ps.num_input_clips_culls) {
4187 unsigned vs_offset;
4188
4189 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST0];
4190 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
4191 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false);
4192 ++ps_offset;
4193 }
4194
4195 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST1];
4196 if (vs_offset != AC_EXP_PARAM_UNDEFINED &&
4197 ps->info.ps.num_input_clips_culls > 4) {
4198 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false);
4199 ++ps_offset;
4200 }
4201 }
4202
4203 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.ps.input_mask; ++i) {
4204 unsigned vs_offset;
4205 bool flat_shade;
4206 bool float16;
4207 if (!(ps->info.ps.input_mask & (1u << i)))
4208 continue;
4209
4210 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
4211 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
4212 ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
4213 ++ps_offset;
4214 continue;
4215 }
4216
4217 flat_shade = !!(ps->info.ps.flat_shaded_mask & (1u << ps_offset));
4218 float16 = !!(ps->info.ps.float16_shaded_mask & (1u << ps_offset));
4219
4220 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade, float16);
4221 ++ps_offset;
4222 }
4223
4224 if (ps_offset) {
4225 radeon_set_context_reg_seq(ctx_cs, R_028644_SPI_PS_INPUT_CNTL_0, ps_offset);
4226 for (unsigned i = 0; i < ps_offset; i++) {
4227 radeon_emit(ctx_cs, ps_input_cntl[i]);
4228 }
4229 }
4230 }
4231
4232 static uint32_t
4233 radv_compute_db_shader_control(const struct radv_device *device,
4234 const struct radv_pipeline *pipeline,
4235 const struct radv_shader_variant *ps)
4236 {
4237 unsigned z_order;
4238 if (ps->info.ps.early_fragment_test || !ps->info.ps.writes_memory)
4239 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
4240 else
4241 z_order = V_02880C_LATE_Z;
4242
4243 bool disable_rbplus = device->physical_device->rad_info.has_rbplus &&
4244 !device->physical_device->rad_info.rbplus_allowed;
4245
4246 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
4247 * but this appears to break Project Cars (DXVK). See
4248 * https://bugs.freedesktop.org/show_bug.cgi?id=109401
4249 */
4250 bool mask_export_enable = ps->info.ps.writes_sample_mask;
4251
4252 return S_02880C_Z_EXPORT_ENABLE(ps->info.ps.writes_z) |
4253 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.ps.writes_stencil) |
4254 S_02880C_KILL_ENABLE(!!ps->info.ps.can_discard) |
4255 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable) |
4256 S_02880C_Z_ORDER(z_order) |
4257 S_02880C_DEPTH_BEFORE_SHADER(ps->info.ps.early_fragment_test) |
4258 S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps->info.ps.post_depth_coverage) |
4259 S_02880C_EXEC_ON_HIER_FAIL(ps->info.ps.writes_memory) |
4260 S_02880C_EXEC_ON_NOOP(ps->info.ps.writes_memory) |
4261 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus);
4262 }
4263
4264 static void
4265 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf *ctx_cs,
4266 struct radeon_cmdbuf *cs,
4267 struct radv_pipeline *pipeline)
4268 {
4269 struct radv_shader_variant *ps;
4270 uint64_t va;
4271 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
4272
4273 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4274 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
4275
4276 radeon_set_sh_reg_seq(cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
4277 radeon_emit(cs, va >> 8);
4278 radeon_emit(cs, S_00B024_MEM_BASE(va >> 40));
4279 radeon_emit(cs, ps->config.rsrc1);
4280 radeon_emit(cs, ps->config.rsrc2);
4281
4282 radeon_set_context_reg(ctx_cs, R_02880C_DB_SHADER_CONTROL,
4283 radv_compute_db_shader_control(pipeline->device,
4284 pipeline, ps));
4285
4286 radeon_set_context_reg(ctx_cs, R_0286CC_SPI_PS_INPUT_ENA,
4287 ps->config.spi_ps_input_ena);
4288
4289 radeon_set_context_reg(ctx_cs, R_0286D0_SPI_PS_INPUT_ADDR,
4290 ps->config.spi_ps_input_addr);
4291
4292 radeon_set_context_reg(ctx_cs, R_0286D8_SPI_PS_IN_CONTROL,
4293 S_0286D8_NUM_INTERP(ps->info.ps.num_interp) |
4294 S_0286D8_PS_W32_EN(ps->info.wave_size == 32));
4295
4296 radeon_set_context_reg(ctx_cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl);
4297
4298 radeon_set_context_reg(ctx_cs, R_028710_SPI_SHADER_Z_FORMAT,
4299 ac_get_spi_shader_z_format(ps->info.ps.writes_z,
4300 ps->info.ps.writes_stencil,
4301 ps->info.ps.writes_sample_mask));
4302
4303 if (pipeline->device->dfsm_allowed) {
4304 /* optimise this? */
4305 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
4306 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
4307 }
4308 }
4309
4310 static void
4311 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf *ctx_cs,
4312 struct radv_pipeline *pipeline)
4313 {
4314 if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10 ||
4315 pipeline->device->physical_device->rad_info.chip_class >= GFX10)
4316 return;
4317
4318 unsigned vtx_reuse_depth = 30;
4319 if (radv_pipeline_has_tess(pipeline) &&
4320 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
4321 vtx_reuse_depth = 14;
4322 }
4323 radeon_set_context_reg(ctx_cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
4324 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth));
4325 }
4326
4327 static uint32_t
4328 radv_compute_vgt_shader_stages_en(const struct radv_pipeline *pipeline)
4329 {
4330 uint32_t stages = 0;
4331 if (radv_pipeline_has_tess(pipeline)) {
4332 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
4333 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
4334
4335 if (radv_pipeline_has_gs(pipeline))
4336 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
4337 S_028B54_GS_EN(1);
4338 else if (radv_pipeline_has_ngg(pipeline))
4339 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
4340 else
4341 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
4342 } else if (radv_pipeline_has_gs(pipeline)) {
4343 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
4344 S_028B54_GS_EN(1);
4345 } else if (radv_pipeline_has_ngg(pipeline)) {
4346 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
4347 }
4348
4349 if (radv_pipeline_has_ngg(pipeline)) {
4350 stages |= S_028B54_PRIMGEN_EN(1);
4351 if (pipeline->streamout_shader)
4352 stages |= S_028B54_NGG_WAVE_ID_EN(1);
4353 } else if (radv_pipeline_has_gs(pipeline)) {
4354 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
4355 }
4356
4357 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
4358 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
4359
4360 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4361 uint8_t hs_size = 64, gs_size = 64, vs_size = 64;
4362
4363 if (radv_pipeline_has_tess(pipeline))
4364 hs_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.wave_size;
4365
4366 if (pipeline->shaders[MESA_SHADER_GEOMETRY]) {
4367 vs_size = gs_size = pipeline->shaders[MESA_SHADER_GEOMETRY]->info.wave_size;
4368 if (pipeline->gs_copy_shader)
4369 vs_size = pipeline->gs_copy_shader->info.wave_size;
4370 } else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
4371 vs_size = pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.wave_size;
4372 else if (pipeline->shaders[MESA_SHADER_VERTEX])
4373 vs_size = pipeline->shaders[MESA_SHADER_VERTEX]->info.wave_size;
4374
4375 if (radv_pipeline_has_ngg(pipeline))
4376 gs_size = vs_size;
4377
4378 /* legacy GS only supports Wave64 */
4379 stages |= S_028B54_HS_W32_EN(hs_size == 32 ? 1 : 0) |
4380 S_028B54_GS_W32_EN(gs_size == 32 ? 1 : 0) |
4381 S_028B54_VS_W32_EN(vs_size == 32 ? 1 : 0);
4382 }
4383
4384 return stages;
4385 }
4386
4387 static uint32_t
4388 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo *pCreateInfo)
4389 {
4390 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
4391 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
4392
4393 if (!discard_rectangle_info)
4394 return 0xffff;
4395
4396 unsigned mask = 0;
4397
4398 for (unsigned i = 0; i < (1u << MAX_DISCARD_RECTANGLES); ++i) {
4399 /* Interpret i as a bitmask, and then set the bit in the mask if
4400 * that combination of rectangles in which the pixel is contained
4401 * should pass the cliprect test. */
4402 unsigned relevant_subset = i & ((1u << discard_rectangle_info->discardRectangleCount) - 1);
4403
4404 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT &&
4405 !relevant_subset)
4406 continue;
4407
4408 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT &&
4409 relevant_subset)
4410 continue;
4411
4412 mask |= 1u << i;
4413 }
4414
4415 return mask;
4416 }
4417
4418 static void
4419 gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf *ctx_cs,
4420 struct radv_pipeline *pipeline,
4421 const struct radv_tessellation_state *tess)
4422 {
4423 bool break_wave_at_eoi = false;
4424 unsigned primgroup_size;
4425 unsigned vertgroup_size;
4426
4427 if (radv_pipeline_has_tess(pipeline)) {
4428 primgroup_size = tess->num_patches; /* must be a multiple of NUM_PATCHES */
4429 vertgroup_size = 0;
4430 } else if (radv_pipeline_has_gs(pipeline)) {
4431 const struct gfx9_gs_info *gs_state =
4432 &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs_ring_info;
4433 unsigned vgt_gs_onchip_cntl = gs_state->vgt_gs_onchip_cntl;
4434 primgroup_size = G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl);
4435 vertgroup_size = G_028A44_ES_VERTS_PER_SUBGRP(vgt_gs_onchip_cntl);
4436 } else {
4437 primgroup_size = 128; /* recommended without a GS and tess */
4438 vertgroup_size = 0;
4439 }
4440
4441 if (radv_pipeline_has_tess(pipeline)) {
4442 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
4443 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.uses_prim_id)
4444 break_wave_at_eoi = true;
4445 }
4446
4447 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL,
4448 S_03096C_PRIM_GRP_SIZE(primgroup_size) |
4449 S_03096C_VERT_GRP_SIZE(vertgroup_size) |
4450 S_03096C_PACKET_TO_ONE_PA(0) /* line stipple */ |
4451 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi));
4452 }
4453
4454 static void
4455 radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
4456 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4457 const struct radv_graphics_pipeline_create_info *extra,
4458 const struct radv_blend_state *blend,
4459 const struct radv_tessellation_state *tess,
4460 unsigned prim, unsigned gs_out)
4461 {
4462 struct radeon_cmdbuf *ctx_cs = &pipeline->ctx_cs;
4463 struct radeon_cmdbuf *cs = &pipeline->cs;
4464
4465 cs->max_dw = 64;
4466 ctx_cs->max_dw = 256;
4467 cs->buf = malloc(4 * (cs->max_dw + ctx_cs->max_dw));
4468 ctx_cs->buf = cs->buf + cs->max_dw;
4469
4470 radv_pipeline_generate_depth_stencil_state(ctx_cs, pipeline, pCreateInfo, extra);
4471 radv_pipeline_generate_blend_state(ctx_cs, pipeline, blend);
4472 radv_pipeline_generate_raster_state(ctx_cs, pipeline, pCreateInfo);
4473 radv_pipeline_generate_multisample_state(ctx_cs, pipeline);
4474 radv_pipeline_generate_vgt_gs_mode(ctx_cs, pipeline);
4475 radv_pipeline_generate_vertex_shader(ctx_cs, cs, pipeline, tess);
4476 radv_pipeline_generate_tess_shaders(ctx_cs, cs, pipeline, tess);
4477 radv_pipeline_generate_geometry_shader(ctx_cs, cs, pipeline);
4478 radv_pipeline_generate_fragment_shader(ctx_cs, cs, pipeline);
4479 radv_pipeline_generate_ps_inputs(ctx_cs, pipeline);
4480 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs, pipeline);
4481 radv_pipeline_generate_binning_state(ctx_cs, pipeline, pCreateInfo, blend);
4482
4483 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 && !radv_pipeline_has_ngg(pipeline))
4484 gfx10_pipeline_generate_ge_cntl(ctx_cs, pipeline, tess);
4485
4486 radeon_set_context_reg(ctx_cs, R_0286E8_SPI_TMPRING_SIZE,
4487 S_0286E8_WAVES(pipeline->max_waves) |
4488 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
4489
4490 radeon_set_context_reg(ctx_cs, R_028B54_VGT_SHADER_STAGES_EN, radv_compute_vgt_shader_stages_en(pipeline));
4491
4492 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
4493 radeon_set_uconfig_reg_idx(pipeline->device->physical_device,
4494 cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
4495 } else {
4496 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
4497 }
4498 radeon_set_context_reg(ctx_cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out);
4499
4500 radeon_set_context_reg(ctx_cs, R_02820C_PA_SC_CLIPRECT_RULE, radv_compute_cliprect_rule(pCreateInfo));
4501
4502 pipeline->ctx_cs_hash = _mesa_hash_data(ctx_cs->buf, ctx_cs->cdw * 4);
4503
4504 assert(ctx_cs->cdw <= ctx_cs->max_dw);
4505 assert(cs->cdw <= cs->max_dw);
4506 }
4507
4508 static struct radv_ia_multi_vgt_param_helpers
4509 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
4510 const struct radv_tessellation_state *tess,
4511 uint32_t prim)
4512 {
4513 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param = {0};
4514 const struct radv_device *device = pipeline->device;
4515
4516 if (radv_pipeline_has_tess(pipeline))
4517 ia_multi_vgt_param.primgroup_size = tess->num_patches;
4518 else if (radv_pipeline_has_gs(pipeline))
4519 ia_multi_vgt_param.primgroup_size = 64;
4520 else
4521 ia_multi_vgt_param.primgroup_size = 128; /* recommended without a GS */
4522
4523 /* GS requirement. */
4524 ia_multi_vgt_param.partial_es_wave = false;
4525 if (radv_pipeline_has_gs(pipeline) && device->physical_device->rad_info.chip_class <= GFX8)
4526 if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3)
4527 ia_multi_vgt_param.partial_es_wave = true;
4528
4529 ia_multi_vgt_param.wd_switch_on_eop = false;
4530 if (device->physical_device->rad_info.chip_class >= GFX7) {
4531 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
4532 * 4 shader engines. Set 1 to pass the assertion below.
4533 * The other cases are hardware requirements. */
4534 if (device->physical_device->rad_info.max_se < 4 ||
4535 prim == V_008958_DI_PT_POLYGON ||
4536 prim == V_008958_DI_PT_LINELOOP ||
4537 prim == V_008958_DI_PT_TRIFAN ||
4538 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
4539 (pipeline->graphics.prim_restart_enable &&
4540 (device->physical_device->rad_info.family < CHIP_POLARIS10 ||
4541 (prim != V_008958_DI_PT_POINTLIST &&
4542 prim != V_008958_DI_PT_LINESTRIP))))
4543 ia_multi_vgt_param.wd_switch_on_eop = true;
4544 }
4545
4546 ia_multi_vgt_param.ia_switch_on_eoi = false;
4547 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.prim_id_input)
4548 ia_multi_vgt_param.ia_switch_on_eoi = true;
4549 if (radv_pipeline_has_gs(pipeline) &&
4550 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.uses_prim_id)
4551 ia_multi_vgt_param.ia_switch_on_eoi = true;
4552 if (radv_pipeline_has_tess(pipeline)) {
4553 /* SWITCH_ON_EOI must be set if PrimID is used. */
4554 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
4555 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.uses_prim_id)
4556 ia_multi_vgt_param.ia_switch_on_eoi = true;
4557 }
4558
4559 ia_multi_vgt_param.partial_vs_wave = false;
4560 if (radv_pipeline_has_tess(pipeline)) {
4561 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
4562 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
4563 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
4564 device->physical_device->rad_info.family == CHIP_BONAIRE) &&
4565 radv_pipeline_has_gs(pipeline))
4566 ia_multi_vgt_param.partial_vs_wave = true;
4567 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
4568 if (device->physical_device->rad_info.has_distributed_tess) {
4569 if (radv_pipeline_has_gs(pipeline)) {
4570 if (device->physical_device->rad_info.chip_class <= GFX8)
4571 ia_multi_vgt_param.partial_es_wave = true;
4572 } else {
4573 ia_multi_vgt_param.partial_vs_wave = true;
4574 }
4575 }
4576 }
4577
4578 /* Workaround for a VGT hang when strip primitive types are used with
4579 * primitive restart.
4580 */
4581 if (pipeline->graphics.prim_restart_enable &&
4582 (prim == V_008958_DI_PT_LINESTRIP ||
4583 prim == V_008958_DI_PT_TRISTRIP ||
4584 prim == V_008958_DI_PT_LINESTRIP_ADJ ||
4585 prim == V_008958_DI_PT_TRISTRIP_ADJ)) {
4586 ia_multi_vgt_param.partial_vs_wave = true;
4587 }
4588
4589 if (radv_pipeline_has_gs(pipeline)) {
4590 /* On these chips there is the possibility of a hang if the
4591 * pipeline uses a GS and partial_vs_wave is not set.
4592 *
4593 * This mostly does not hit 4-SE chips, as those typically set
4594 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
4595 * with GS due to another workaround.
4596 *
4597 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
4598 */
4599 if (device->physical_device->rad_info.family == CHIP_TONGA ||
4600 device->physical_device->rad_info.family == CHIP_FIJI ||
4601 device->physical_device->rad_info.family == CHIP_POLARIS10 ||
4602 device->physical_device->rad_info.family == CHIP_POLARIS11 ||
4603 device->physical_device->rad_info.family == CHIP_POLARIS12 ||
4604 device->physical_device->rad_info.family == CHIP_VEGAM) {
4605 ia_multi_vgt_param.partial_vs_wave = true;
4606 }
4607 }
4608
4609 ia_multi_vgt_param.base =
4610 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param.primgroup_size - 1) |
4611 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
4612 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == GFX8 ? 2 : 0) |
4613 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
4614 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
4615
4616 return ia_multi_vgt_param;
4617 }
4618
4619
4620 static void
4621 radv_compute_vertex_input_state(struct radv_pipeline *pipeline,
4622 const VkGraphicsPipelineCreateInfo *pCreateInfo)
4623 {
4624 const VkPipelineVertexInputStateCreateInfo *vi_info =
4625 pCreateInfo->pVertexInputState;
4626 struct radv_vertex_elements_info *velems = &pipeline->vertex_elements;
4627
4628 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
4629 const VkVertexInputAttributeDescription *desc =
4630 &vi_info->pVertexAttributeDescriptions[i];
4631 unsigned loc = desc->location;
4632 const struct vk_format_description *format_desc;
4633
4634 format_desc = vk_format_description(desc->format);
4635
4636 velems->format_size[loc] = format_desc->block.bits / 8;
4637 }
4638
4639 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
4640 const VkVertexInputBindingDescription *desc =
4641 &vi_info->pVertexBindingDescriptions[i];
4642
4643 pipeline->binding_stride[desc->binding] = desc->stride;
4644 pipeline->num_vertex_bindings =
4645 MAX2(pipeline->num_vertex_bindings, desc->binding + 1);
4646 }
4647 }
4648
4649 static struct radv_shader_variant *
4650 radv_pipeline_get_streamout_shader(struct radv_pipeline *pipeline)
4651 {
4652 int i;
4653
4654 for (i = MESA_SHADER_GEOMETRY; i >= MESA_SHADER_VERTEX; i--) {
4655 struct radv_shader_variant *shader =
4656 radv_get_shader(pipeline, i);
4657
4658 if (shader && shader->info.so.num_outputs > 0)
4659 return shader;
4660 }
4661
4662 return NULL;
4663 }
4664
4665 static VkResult
4666 radv_secure_compile(struct radv_pipeline *pipeline,
4667 struct radv_device *device,
4668 const struct radv_pipeline_key *key,
4669 const VkPipelineShaderStageCreateInfo **pStages,
4670 const VkPipelineCreateFlags flags,
4671 unsigned num_stages)
4672 {
4673 uint8_t allowed_pipeline_hashes[2][20];
4674 radv_hash_shaders(allowed_pipeline_hashes[0], pStages,
4675 pipeline->layout, key, get_hash_flags(device));
4676
4677 /* Generate the GC copy hash */
4678 memcpy(allowed_pipeline_hashes[1], allowed_pipeline_hashes[0], 20);
4679 allowed_pipeline_hashes[1][0] ^= 1;
4680
4681 uint8_t allowed_hashes[2][20];
4682 for (unsigned i = 0; i < 2; ++i) {
4683 disk_cache_compute_key(device->physical_device->disk_cache,
4684 allowed_pipeline_hashes[i], 20,
4685 allowed_hashes[i]);
4686 }
4687
4688 /* Do an early exit if all cache entries are already there. */
4689 bool may_need_copy_shader = pStages[MESA_SHADER_GEOMETRY];
4690 void *main_entry = disk_cache_get(device->physical_device->disk_cache, allowed_hashes[0], NULL);
4691 void *copy_entry = NULL;
4692 if (may_need_copy_shader)
4693 copy_entry = disk_cache_get(device->physical_device->disk_cache, allowed_hashes[1], NULL);
4694
4695 bool has_all_cache_entries = main_entry && (!may_need_copy_shader || copy_entry);
4696 free(main_entry);
4697 free(copy_entry);
4698
4699 if(has_all_cache_entries)
4700 return VK_SUCCESS;
4701
4702 unsigned process = 0;
4703 uint8_t sc_threads = device->instance->num_sc_threads;
4704 while (true) {
4705 mtx_lock(&device->sc_state->secure_compile_mutex);
4706 if (device->sc_state->secure_compile_thread_counter < sc_threads) {
4707 device->sc_state->secure_compile_thread_counter++;
4708 for (unsigned i = 0; i < sc_threads; i++) {
4709 if (!device->sc_state->secure_compile_processes[i].in_use) {
4710 device->sc_state->secure_compile_processes[i].in_use = true;
4711 process = i;
4712 break;
4713 }
4714 }
4715 mtx_unlock(&device->sc_state->secure_compile_mutex);
4716 break;
4717 }
4718 mtx_unlock(&device->sc_state->secure_compile_mutex);
4719 }
4720
4721 int fd_secure_input = device->sc_state->secure_compile_processes[process].fd_secure_input;
4722 int fd_secure_output = device->sc_state->secure_compile_processes[process].fd_secure_output;
4723
4724 /* Write pipeline / shader module out to secure process via pipe */
4725 enum radv_secure_compile_type sc_type = RADV_SC_TYPE_COMPILE_PIPELINE;
4726 write(fd_secure_input, &sc_type, sizeof(sc_type));
4727
4728 /* Write pipeline layout out to secure process */
4729 struct radv_pipeline_layout *layout = pipeline->layout;
4730 write(fd_secure_input, layout, sizeof(struct radv_pipeline_layout));
4731 write(fd_secure_input, &layout->num_sets, sizeof(uint32_t));
4732 for (uint32_t set = 0; set < layout->num_sets; set++) {
4733 write(fd_secure_input, &layout->set[set].layout->layout_size, sizeof(uint32_t));
4734 write(fd_secure_input, layout->set[set].layout, layout->set[set].layout->layout_size);
4735 }
4736
4737 /* Write pipeline key out to secure process */
4738 write(fd_secure_input, key, sizeof(struct radv_pipeline_key));
4739
4740 /* Write pipeline create flags out to secure process */
4741 write(fd_secure_input, &flags, sizeof(VkPipelineCreateFlags));
4742
4743 /* Write stage and shader information out to secure process */
4744 write(fd_secure_input, &num_stages, sizeof(uint32_t));
4745 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
4746 if (!pStages[i])
4747 continue;
4748
4749 /* Write stage out to secure process */
4750 gl_shader_stage stage = ffs(pStages[i]->stage) - 1;
4751 write(fd_secure_input, &stage, sizeof(gl_shader_stage));
4752
4753 /* Write entry point name out to secure process */
4754 size_t name_size = strlen(pStages[i]->pName) + 1;
4755 write(fd_secure_input, &name_size, sizeof(size_t));
4756 write(fd_secure_input, pStages[i]->pName, name_size);
4757
4758 /* Write shader module out to secure process */
4759 struct radv_shader_module *module = radv_shader_module_from_handle(pStages[i]->module);
4760 assert(!module->nir);
4761 size_t module_size = sizeof(struct radv_shader_module) + module->size;
4762 write(fd_secure_input, &module_size, sizeof(size_t));
4763 write(fd_secure_input, module, module_size);
4764
4765 /* Write specialization info out to secure process */
4766 const VkSpecializationInfo *specInfo = pStages[i]->pSpecializationInfo;
4767 bool has_spec_info = specInfo ? true : false;
4768 write(fd_secure_input, &has_spec_info, sizeof(bool));
4769 if (specInfo) {
4770 write(fd_secure_input, &specInfo->dataSize, sizeof(size_t));
4771 write(fd_secure_input, specInfo->pData, specInfo->dataSize);
4772
4773 write(fd_secure_input, &specInfo->mapEntryCount, sizeof(uint32_t));
4774 for (uint32_t j = 0; j < specInfo->mapEntryCount; j++)
4775 write(fd_secure_input, &specInfo->pMapEntries[j], sizeof(VkSpecializationMapEntry));
4776 }
4777 }
4778
4779 /* Read the data returned from the secure process */
4780 while (sc_type != RADV_SC_TYPE_COMPILE_PIPELINE_FINISHED) {
4781 if (!radv_sc_read(fd_secure_output, &sc_type, sizeof(sc_type), true))
4782 return VK_ERROR_DEVICE_LOST;
4783
4784 if (sc_type == RADV_SC_TYPE_WRITE_DISK_CACHE) {
4785 assert(device->physical_device->disk_cache);
4786
4787 uint8_t disk_sha1[20];
4788 if (!radv_sc_read(fd_secure_output, disk_sha1, sizeof(uint8_t) * 20, true))
4789 return VK_ERROR_DEVICE_LOST;
4790
4791 if (memcmp(disk_sha1, allowed_hashes[0], 20) &&
4792 memcmp(disk_sha1, allowed_hashes[1], 20))
4793 return VK_ERROR_DEVICE_LOST;
4794
4795 uint32_t entry_size;
4796 if (!radv_sc_read(fd_secure_output, &entry_size, sizeof(uint32_t), true))
4797 return VK_ERROR_DEVICE_LOST;
4798
4799 struct cache_entry *entry = malloc(entry_size);
4800 if (!radv_sc_read(fd_secure_output, entry, entry_size, true))
4801 return VK_ERROR_DEVICE_LOST;
4802
4803 disk_cache_put(device->physical_device->disk_cache,
4804 disk_sha1, entry, entry_size,
4805 NULL);
4806
4807 free(entry);
4808 } else if (sc_type == RADV_SC_TYPE_READ_DISK_CACHE) {
4809 uint8_t disk_sha1[20];
4810 if (!radv_sc_read(fd_secure_output, disk_sha1, sizeof(uint8_t) * 20, true))
4811 return VK_ERROR_DEVICE_LOST;
4812
4813 if (memcmp(disk_sha1, allowed_hashes[0], 20) &&
4814 memcmp(disk_sha1, allowed_hashes[1], 20))
4815 return VK_ERROR_DEVICE_LOST;
4816
4817 size_t size;
4818 struct cache_entry *entry = (struct cache_entry *)
4819 disk_cache_get(device->physical_device->disk_cache,
4820 disk_sha1, &size);
4821
4822 uint8_t found = entry ? 1 : 0;
4823 write(fd_secure_input, &found, sizeof(uint8_t));
4824
4825 if (found) {
4826 write(fd_secure_input, &size, sizeof(size_t));
4827 write(fd_secure_input, entry, size);
4828 }
4829
4830 free(entry);
4831 }
4832 }
4833
4834 mtx_lock(&device->sc_state->secure_compile_mutex);
4835 device->sc_state->secure_compile_thread_counter--;
4836 device->sc_state->secure_compile_processes[process].in_use = false;
4837 mtx_unlock(&device->sc_state->secure_compile_mutex);
4838
4839 return VK_SUCCESS;
4840 }
4841
4842 static VkResult
4843 radv_pipeline_init(struct radv_pipeline *pipeline,
4844 struct radv_device *device,
4845 struct radv_pipeline_cache *cache,
4846 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4847 const struct radv_graphics_pipeline_create_info *extra)
4848 {
4849 VkResult result;
4850 bool has_view_index = false;
4851
4852 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
4853 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
4854 if (subpass->view_mask)
4855 has_view_index = true;
4856
4857 pipeline->device = device;
4858 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
4859 assert(pipeline->layout);
4860
4861 struct radv_blend_state blend = radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
4862
4863 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
4864 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
4865 radv_init_feedback(creation_feedback);
4866
4867 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
4868
4869 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
4870 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
4871 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
4872 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
4873 pStages[stage] = &pCreateInfo->pStages[i];
4874 if(creation_feedback)
4875 stage_feedbacks[stage] = &creation_feedback->pPipelineStageCreationFeedbacks[i];
4876 }
4877
4878 struct radv_pipeline_key key = radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &blend, has_view_index);
4879 if (radv_device_use_secure_compile(device->instance)) {
4880 return radv_secure_compile(pipeline, device, &key, pStages, pCreateInfo->flags, pCreateInfo->stageCount);
4881 } else {
4882 radv_create_shaders(pipeline, device, cache, &key, pStages, pCreateInfo->flags, pipeline_feedback, stage_feedbacks);
4883 }
4884
4885 pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
4886 radv_pipeline_init_multisample_state(pipeline, &blend, pCreateInfo);
4887 uint32_t gs_out;
4888 uint32_t prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
4889
4890 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
4891
4892 if (radv_pipeline_has_gs(pipeline)) {
4893 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
4894 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
4895 } else if (radv_pipeline_has_tess(pipeline)) {
4896 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.point_mode)
4897 gs_out = V_028A6C_OUTPRIM_TYPE_POINTLIST;
4898 else
4899 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.primitive_mode);
4900 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
4901 } else {
4902 gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
4903 }
4904 if (extra && extra->use_rectlist) {
4905 prim = V_008958_DI_PT_RECTLIST;
4906 gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
4907 pipeline->graphics.can_use_guardband = true;
4908 if (radv_pipeline_has_ngg(pipeline))
4909 gs_out = V_028A6C_VGT_OUT_RECT_V0;
4910 }
4911 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
4912 /* prim vertex count will need TESS changes */
4913 pipeline->graphics.prim_vertex_count = prim_size_table[prim];
4914
4915 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
4916
4917 /* Ensure that some export memory is always allocated, for two reasons:
4918 *
4919 * 1) Correctness: The hardware ignores the EXEC mask if no export
4920 * memory is allocated, so KILL and alpha test do not work correctly
4921 * without this.
4922 * 2) Performance: Every shader needs at least a NULL export, even when
4923 * it writes no color/depth output. The NULL export instruction
4924 * stalls without this setting.
4925 *
4926 * Don't add this to CB_SHADER_MASK.
4927 *
4928 * GFX10 supports pixel shaders without exports by setting both the
4929 * color and Z formats to SPI_SHADER_ZERO. The hw will skip export
4930 * instructions if any are present.
4931 */
4932 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4933 if ((pipeline->device->physical_device->rad_info.chip_class <= GFX9 ||
4934 ps->info.ps.can_discard) &&
4935 !blend.spi_shader_col_format) {
4936 if (!ps->info.ps.writes_z &&
4937 !ps->info.ps.writes_stencil &&
4938 !ps->info.ps.writes_sample_mask)
4939 blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
4940 }
4941
4942 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
4943 if (pipeline->shaders[i]) {
4944 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
4945 }
4946 }
4947
4948 if (radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) {
4949 struct radv_shader_variant *gs =
4950 pipeline->shaders[MESA_SHADER_GEOMETRY];
4951
4952 calculate_gs_ring_sizes(pipeline, &gs->info.gs_ring_info);
4953 }
4954
4955 struct radv_tessellation_state tess = {0};
4956 if (radv_pipeline_has_tess(pipeline)) {
4957 if (prim == V_008958_DI_PT_PATCH) {
4958 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
4959 pipeline->graphics.prim_vertex_count.incr = 1;
4960 }
4961 tess = calculate_tess_state(pipeline, pCreateInfo);
4962 }
4963
4964 pipeline->graphics.ia_multi_vgt_param = radv_compute_ia_multi_vgt_param_helpers(pipeline, &tess, prim);
4965
4966 radv_compute_vertex_input_state(pipeline, pCreateInfo);
4967
4968 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
4969 pipeline->user_data_0[i] = radv_pipeline_stage_to_user_data_0(pipeline, i, device->physical_device->rad_info.chip_class);
4970
4971 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
4972 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
4973 if (loc->sgpr_idx != -1) {
4974 pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX];
4975 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
4976 if (radv_get_shader(pipeline, MESA_SHADER_VERTEX)->info.vs.needs_draw_id)
4977 pipeline->graphics.vtx_emit_num = 3;
4978 else
4979 pipeline->graphics.vtx_emit_num = 2;
4980 }
4981
4982 /* Find the last vertex shader stage that eventually uses streamout. */
4983 pipeline->streamout_shader = radv_pipeline_get_streamout_shader(pipeline);
4984
4985 result = radv_pipeline_scratch_init(device, pipeline);
4986 radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend, &tess, prim, gs_out);
4987
4988 return result;
4989 }
4990
4991 VkResult
4992 radv_graphics_pipeline_create(
4993 VkDevice _device,
4994 VkPipelineCache _cache,
4995 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4996 const struct radv_graphics_pipeline_create_info *extra,
4997 const VkAllocationCallbacks *pAllocator,
4998 VkPipeline *pPipeline)
4999 {
5000 RADV_FROM_HANDLE(radv_device, device, _device);
5001 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
5002 struct radv_pipeline *pipeline;
5003 VkResult result;
5004
5005 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
5006 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5007 if (pipeline == NULL)
5008 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5009
5010 result = radv_pipeline_init(pipeline, device, cache,
5011 pCreateInfo, extra);
5012 if (result != VK_SUCCESS) {
5013 radv_pipeline_destroy(device, pipeline, pAllocator);
5014 return result;
5015 }
5016
5017 *pPipeline = radv_pipeline_to_handle(pipeline);
5018
5019 return VK_SUCCESS;
5020 }
5021
5022 VkResult radv_CreateGraphicsPipelines(
5023 VkDevice _device,
5024 VkPipelineCache pipelineCache,
5025 uint32_t count,
5026 const VkGraphicsPipelineCreateInfo* pCreateInfos,
5027 const VkAllocationCallbacks* pAllocator,
5028 VkPipeline* pPipelines)
5029 {
5030 VkResult result = VK_SUCCESS;
5031 unsigned i = 0;
5032
5033 for (; i < count; i++) {
5034 VkResult r;
5035 r = radv_graphics_pipeline_create(_device,
5036 pipelineCache,
5037 &pCreateInfos[i],
5038 NULL, pAllocator, &pPipelines[i]);
5039 if (r != VK_SUCCESS) {
5040 result = r;
5041 pPipelines[i] = VK_NULL_HANDLE;
5042 }
5043 }
5044
5045 return result;
5046 }
5047
5048
5049 static void
5050 radv_compute_generate_pm4(struct radv_pipeline *pipeline)
5051 {
5052 struct radv_shader_variant *compute_shader;
5053 struct radv_device *device = pipeline->device;
5054 unsigned threads_per_threadgroup;
5055 unsigned threadgroups_per_cu = 1;
5056 unsigned waves_per_threadgroup;
5057 unsigned max_waves_per_sh = 0;
5058 uint64_t va;
5059
5060 pipeline->cs.max_dw = device->physical_device->rad_info.chip_class >= GFX10 ? 22 : 20;
5061 pipeline->cs.buf = malloc(pipeline->cs.max_dw * 4);
5062
5063 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
5064 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
5065
5066 radeon_set_sh_reg_seq(&pipeline->cs, R_00B830_COMPUTE_PGM_LO, 2);
5067 radeon_emit(&pipeline->cs, va >> 8);
5068 radeon_emit(&pipeline->cs, S_00B834_DATA(va >> 40));
5069
5070 radeon_set_sh_reg_seq(&pipeline->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
5071 radeon_emit(&pipeline->cs, compute_shader->config.rsrc1);
5072 radeon_emit(&pipeline->cs, compute_shader->config.rsrc2);
5073 if (device->physical_device->rad_info.chip_class >= GFX10) {
5074 radeon_set_sh_reg(&pipeline->cs, R_00B8A0_COMPUTE_PGM_RSRC3, compute_shader->config.rsrc3);
5075 }
5076
5077 radeon_set_sh_reg(&pipeline->cs, R_00B860_COMPUTE_TMPRING_SIZE,
5078 S_00B860_WAVES(pipeline->max_waves) |
5079 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
5080
5081 /* Calculate best compute resource limits. */
5082 threads_per_threadgroup = compute_shader->info.cs.block_size[0] *
5083 compute_shader->info.cs.block_size[1] *
5084 compute_shader->info.cs.block_size[2];
5085 waves_per_threadgroup = DIV_ROUND_UP(threads_per_threadgroup,
5086 compute_shader->info.wave_size);
5087
5088 if (device->physical_device->rad_info.chip_class >= GFX10 &&
5089 waves_per_threadgroup == 1)
5090 threadgroups_per_cu = 2;
5091
5092 radeon_set_sh_reg(&pipeline->cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
5093 ac_get_compute_resource_limits(&device->physical_device->rad_info,
5094 waves_per_threadgroup,
5095 max_waves_per_sh,
5096 threadgroups_per_cu));
5097
5098 radeon_set_sh_reg_seq(&pipeline->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
5099 radeon_emit(&pipeline->cs,
5100 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
5101 radeon_emit(&pipeline->cs,
5102 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
5103 radeon_emit(&pipeline->cs,
5104 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
5105
5106 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
5107 }
5108
5109 static struct radv_pipeline_key
5110 radv_generate_compute_pipeline_key(struct radv_pipeline *pipeline,
5111 const VkComputePipelineCreateInfo *pCreateInfo)
5112 {
5113 const VkPipelineShaderStageCreateInfo *stage = &pCreateInfo->stage;
5114 struct radv_pipeline_key key;
5115 memset(&key, 0, sizeof(key));
5116
5117 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
5118 key.optimisations_disabled = 1;
5119
5120 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT *subgroup_size =
5121 vk_find_struct_const(stage->pNext,
5122 PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT);
5123
5124 if (subgroup_size) {
5125 assert(subgroup_size->requiredSubgroupSize == 32 ||
5126 subgroup_size->requiredSubgroupSize == 64);
5127 key.compute_subgroup_size = subgroup_size->requiredSubgroupSize;
5128 }
5129
5130 return key;
5131 }
5132
5133 static VkResult radv_compute_pipeline_create(
5134 VkDevice _device,
5135 VkPipelineCache _cache,
5136 const VkComputePipelineCreateInfo* pCreateInfo,
5137 const VkAllocationCallbacks* pAllocator,
5138 VkPipeline* pPipeline)
5139 {
5140 RADV_FROM_HANDLE(radv_device, device, _device);
5141 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
5142 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
5143 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
5144 struct radv_pipeline *pipeline;
5145 VkResult result;
5146
5147 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
5148 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5149 if (pipeline == NULL)
5150 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5151
5152 pipeline->device = device;
5153 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
5154 assert(pipeline->layout);
5155
5156 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
5157 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
5158 radv_init_feedback(creation_feedback);
5159
5160 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
5161 if (creation_feedback)
5162 stage_feedbacks[MESA_SHADER_COMPUTE] = &creation_feedback->pPipelineStageCreationFeedbacks[0];
5163
5164 pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
5165
5166 struct radv_pipeline_key key =
5167 radv_generate_compute_pipeline_key(pipeline, pCreateInfo);
5168
5169 if (radv_device_use_secure_compile(device->instance)) {
5170 result = radv_secure_compile(pipeline, device, &key, pStages, pCreateInfo->flags, 1);
5171 *pPipeline = radv_pipeline_to_handle(pipeline);
5172
5173 return result;
5174 } else {
5175 radv_create_shaders(pipeline, device, cache, &key, pStages, pCreateInfo->flags, pipeline_feedback, stage_feedbacks);
5176 }
5177
5178 pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
5179 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
5180 result = radv_pipeline_scratch_init(device, pipeline);
5181 if (result != VK_SUCCESS) {
5182 radv_pipeline_destroy(device, pipeline, pAllocator);
5183 return result;
5184 }
5185
5186 radv_compute_generate_pm4(pipeline);
5187
5188 *pPipeline = radv_pipeline_to_handle(pipeline);
5189
5190 return VK_SUCCESS;
5191 }
5192
5193 VkResult radv_CreateComputePipelines(
5194 VkDevice _device,
5195 VkPipelineCache pipelineCache,
5196 uint32_t count,
5197 const VkComputePipelineCreateInfo* pCreateInfos,
5198 const VkAllocationCallbacks* pAllocator,
5199 VkPipeline* pPipelines)
5200 {
5201 VkResult result = VK_SUCCESS;
5202
5203 unsigned i = 0;
5204 for (; i < count; i++) {
5205 VkResult r;
5206 r = radv_compute_pipeline_create(_device, pipelineCache,
5207 &pCreateInfos[i],
5208 pAllocator, &pPipelines[i]);
5209 if (r != VK_SUCCESS) {
5210 result = r;
5211 pPipelines[i] = VK_NULL_HANDLE;
5212 }
5213 }
5214
5215 return result;
5216 }
5217
5218
5219 static uint32_t radv_get_executable_count(const struct radv_pipeline *pipeline)
5220 {
5221 uint32_t ret = 0;
5222 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
5223 if (!pipeline->shaders[i])
5224 continue;
5225
5226 if (i == MESA_SHADER_GEOMETRY &&
5227 !radv_pipeline_has_ngg(pipeline)) {
5228 ret += 2u;
5229 } else {
5230 ret += 1u;
5231 }
5232
5233 }
5234 return ret;
5235 }
5236
5237 static struct radv_shader_variant *
5238 radv_get_shader_from_executable_index(const struct radv_pipeline *pipeline, int index, gl_shader_stage *stage)
5239 {
5240 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
5241 if (!pipeline->shaders[i])
5242 continue;
5243 if (!index) {
5244 *stage = i;
5245 return pipeline->shaders[i];
5246 }
5247
5248 --index;
5249
5250 if (i == MESA_SHADER_GEOMETRY &&
5251 !radv_pipeline_has_ngg(pipeline)) {
5252 if (!index) {
5253 *stage = i;
5254 return pipeline->gs_copy_shader;
5255 }
5256 --index;
5257 }
5258 }
5259
5260 *stage = -1;
5261 return NULL;
5262 }
5263
5264 /* Basically strlcpy (which does not exist on linux) specialized for
5265 * descriptions. */
5266 static void desc_copy(char *desc, const char *src) {
5267 int len = strlen(src);
5268 assert(len < VK_MAX_DESCRIPTION_SIZE);
5269 memcpy(desc, src, len);
5270 memset(desc + len, 0, VK_MAX_DESCRIPTION_SIZE - len);
5271 }
5272
5273 VkResult radv_GetPipelineExecutablePropertiesKHR(
5274 VkDevice _device,
5275 const VkPipelineInfoKHR* pPipelineInfo,
5276 uint32_t* pExecutableCount,
5277 VkPipelineExecutablePropertiesKHR* pProperties)
5278 {
5279 RADV_FROM_HANDLE(radv_pipeline, pipeline, pPipelineInfo->pipeline);
5280 const uint32_t total_count = radv_get_executable_count(pipeline);
5281
5282 if (!pProperties) {
5283 *pExecutableCount = total_count;
5284 return VK_SUCCESS;
5285 }
5286
5287 const uint32_t count = MIN2(total_count, *pExecutableCount);
5288 for (unsigned i = 0, executable_idx = 0;
5289 i < MESA_SHADER_STAGES && executable_idx < count; ++i) {
5290 if (!pipeline->shaders[i])
5291 continue;
5292 pProperties[executable_idx].stages = mesa_to_vk_shader_stage(i);
5293 const char *name = NULL;
5294 const char *description = NULL;
5295 switch(i) {
5296 case MESA_SHADER_VERTEX:
5297 name = "Vertex Shader";
5298 description = "Vulkan Vertex Shader";
5299 break;
5300 case MESA_SHADER_TESS_CTRL:
5301 if (!pipeline->shaders[MESA_SHADER_VERTEX]) {
5302 pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT;
5303 name = "Vertex + Tessellation Control Shaders";
5304 description = "Combined Vulkan Vertex and Tessellation Control Shaders";
5305 } else {
5306 name = "Tessellation Control Shader";
5307 description = "Vulkan Tessellation Control Shader";
5308 }
5309 break;
5310 case MESA_SHADER_TESS_EVAL:
5311 name = "Tessellation Evaluation Shader";
5312 description = "Vulkan Tessellation Evaluation Shader";
5313 break;
5314 case MESA_SHADER_GEOMETRY:
5315 if (radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_TESS_EVAL]) {
5316 pProperties[executable_idx].stages |= VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT;
5317 name = "Tessellation Evaluation + Geometry Shaders";
5318 description = "Combined Vulkan Tessellation Evaluation and Geometry Shaders";
5319 } else if (!radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_VERTEX]) {
5320 pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT;
5321 name = "Vertex + Geometry Shader";
5322 description = "Combined Vulkan Vertex and Geometry Shaders";
5323 } else {
5324 name = "Geometry Shader";
5325 description = "Vulkan Geometry Shader";
5326 }
5327 break;
5328 case MESA_SHADER_FRAGMENT:
5329 name = "Fragment Shader";
5330 description = "Vulkan Fragment Shader";
5331 break;
5332 case MESA_SHADER_COMPUTE:
5333 name = "Compute Shader";
5334 description = "Vulkan Compute Shader";
5335 break;
5336 }
5337
5338 desc_copy(pProperties[executable_idx].name, name);
5339 desc_copy(pProperties[executable_idx].description, description);
5340
5341 ++executable_idx;
5342 if (i == MESA_SHADER_GEOMETRY &&
5343 !radv_pipeline_has_ngg(pipeline)) {
5344 assert(pipeline->gs_copy_shader);
5345 if (executable_idx >= count)
5346 break;
5347
5348 pProperties[executable_idx].stages = VK_SHADER_STAGE_GEOMETRY_BIT;
5349 desc_copy(pProperties[executable_idx].name, "GS Copy Shader");
5350 desc_copy(pProperties[executable_idx].description,
5351 "Extra shader stage that loads the GS output ringbuffer into the rasterizer");
5352
5353 ++executable_idx;
5354 }
5355 }
5356
5357 for (unsigned i = 0; i < count; ++i)
5358 pProperties[i].subgroupSize = 64;
5359
5360 VkResult result = *pExecutableCount < total_count ? VK_INCOMPLETE : VK_SUCCESS;
5361 *pExecutableCount = count;
5362 return result;
5363 }
5364
5365 VkResult radv_GetPipelineExecutableStatisticsKHR(
5366 VkDevice _device,
5367 const VkPipelineExecutableInfoKHR* pExecutableInfo,
5368 uint32_t* pStatisticCount,
5369 VkPipelineExecutableStatisticKHR* pStatistics)
5370 {
5371 RADV_FROM_HANDLE(radv_device, device, _device);
5372 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
5373 gl_shader_stage stage;
5374 struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
5375
5376 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
5377 unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
5378 unsigned max_waves = radv_get_max_waves(device, shader, stage);
5379
5380 VkPipelineExecutableStatisticKHR *s = pStatistics;
5381 VkPipelineExecutableStatisticKHR *end = s + (pStatistics ? *pStatisticCount : 0);
5382 VkResult result = VK_SUCCESS;
5383
5384 if (s < end) {
5385 desc_copy(s->name, "SGPRs");
5386 desc_copy(s->description, "Number of SGPR registers allocated per subgroup");
5387 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5388 s->value.u64 = shader->config.num_sgprs;
5389 }
5390 ++s;
5391
5392 if (s < end) {
5393 desc_copy(s->name, "VGPRs");
5394 desc_copy(s->description, "Number of VGPR registers allocated per subgroup");
5395 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5396 s->value.u64 = shader->config.num_vgprs;
5397 }
5398 ++s;
5399
5400 if (s < end) {
5401 desc_copy(s->name, "Spilled SGPRs");
5402 desc_copy(s->description, "Number of SGPR registers spilled per subgroup");
5403 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5404 s->value.u64 = shader->config.spilled_sgprs;
5405 }
5406 ++s;
5407
5408 if (s < end) {
5409 desc_copy(s->name, "Spilled VGPRs");
5410 desc_copy(s->description, "Number of VGPR registers spilled per subgroup");
5411 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5412 s->value.u64 = shader->config.spilled_vgprs;
5413 }
5414 ++s;
5415
5416 if (s < end) {
5417 desc_copy(s->name, "PrivMem VGPRs");
5418 desc_copy(s->description, "Number of VGPRs stored in private memory per subgroup");
5419 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5420 s->value.u64 = shader->info.private_mem_vgprs;
5421 }
5422 ++s;
5423
5424 if (s < end) {
5425 desc_copy(s->name, "Code size");
5426 desc_copy(s->description, "Code size in bytes");
5427 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5428 s->value.u64 = shader->exec_size;
5429 }
5430 ++s;
5431
5432 if (s < end) {
5433 desc_copy(s->name, "LDS size");
5434 desc_copy(s->description, "LDS size in bytes per workgroup");
5435 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5436 s->value.u64 = shader->config.lds_size * lds_increment;
5437 }
5438 ++s;
5439
5440 if (s < end) {
5441 desc_copy(s->name, "Scratch size");
5442 desc_copy(s->description, "Private memory in bytes per subgroup");
5443 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5444 s->value.u64 = shader->config.scratch_bytes_per_wave;
5445 }
5446 ++s;
5447
5448 if (s < end) {
5449 desc_copy(s->name, "Subgroups per SIMD");
5450 desc_copy(s->description, "The maximum number of subgroups in flight on a SIMD unit");
5451 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5452 s->value.u64 = max_waves;
5453 }
5454 ++s;
5455
5456 if (!pStatistics)
5457 *pStatisticCount = s - pStatistics;
5458 else if (s > end) {
5459 *pStatisticCount = end - pStatistics;
5460 result = VK_INCOMPLETE;
5461 } else {
5462 *pStatisticCount = s - pStatistics;
5463 }
5464
5465 return result;
5466 }
5467
5468 static VkResult radv_copy_representation(void *data, size_t *data_size, const char *src)
5469 {
5470 size_t total_size = strlen(src) + 1;
5471
5472 if (!data) {
5473 *data_size = total_size;
5474 return VK_SUCCESS;
5475 }
5476
5477 size_t size = MIN2(total_size, *data_size);
5478
5479 memcpy(data, src, size);
5480 if (size)
5481 *((char*)data + size - 1) = 0;
5482 return size < total_size ? VK_INCOMPLETE : VK_SUCCESS;
5483 }
5484
5485 VkResult radv_GetPipelineExecutableInternalRepresentationsKHR(
5486 VkDevice device,
5487 const VkPipelineExecutableInfoKHR* pExecutableInfo,
5488 uint32_t* pInternalRepresentationCount,
5489 VkPipelineExecutableInternalRepresentationKHR* pInternalRepresentations)
5490 {
5491 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
5492 gl_shader_stage stage;
5493 struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
5494
5495 VkPipelineExecutableInternalRepresentationKHR *p = pInternalRepresentations;
5496 VkPipelineExecutableInternalRepresentationKHR *end = p + (pInternalRepresentations ? *pInternalRepresentationCount : 0);
5497 VkResult result = VK_SUCCESS;
5498 /* optimized NIR */
5499 if (p < end) {
5500 p->isText = true;
5501 desc_copy(p->name, "NIR Shader(s)");
5502 desc_copy(p->description, "The optimized NIR shader(s)");
5503 if (radv_copy_representation(p->pData, &p->dataSize, shader->nir_string) != VK_SUCCESS)
5504 result = VK_INCOMPLETE;
5505 }
5506 ++p;
5507
5508 /* backend IR */
5509 if (p < end) {
5510 p->isText = true;
5511 if (shader->aco_used) {
5512 desc_copy(p->name, "ACO IR");
5513 desc_copy(p->description, "The ACO IR after some optimizations");
5514 } else {
5515 desc_copy(p->name, "LLVM IR");
5516 desc_copy(p->description, "The LLVM IR after some optimizations");
5517 }
5518 if (radv_copy_representation(p->pData, &p->dataSize, shader->ir_string) != VK_SUCCESS)
5519 result = VK_INCOMPLETE;
5520 }
5521 ++p;
5522
5523 /* Disassembler */
5524 if (p < end) {
5525 p->isText = true;
5526 desc_copy(p->name, "Assembly");
5527 desc_copy(p->description, "Final Assembly");
5528 if (radv_copy_representation(p->pData, &p->dataSize, shader->disasm_string) != VK_SUCCESS)
5529 result = VK_INCOMPLETE;
5530 }
5531 ++p;
5532
5533 if (!pInternalRepresentations)
5534 *pInternalRepresentationCount = p - pInternalRepresentations;
5535 else if(p > end) {
5536 result = VK_INCOMPLETE;
5537 *pInternalRepresentationCount = end - pInternalRepresentations;
5538 } else {
5539 *pInternalRepresentationCount = p - pInternalRepresentations;
5540 }
5541
5542 return result;
5543 }