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radv: Set VGT_GS_MODE properly for gfx9
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
33 #include "nir/nir.h"
34 #include "nir/nir_builder.h"
35 #include "spirv/nir_spirv.h"
36 #include "vk_util.h"
37
38 #include <llvm-c/Core.h>
39 #include <llvm-c/TargetMachine.h>
40
41 #include "sid.h"
42 #include "gfx9d.h"
43 #include "ac_binary.h"
44 #include "ac_llvm_util.h"
45 #include "ac_nir_to_llvm.h"
46 #include "vk_format.h"
47 #include "util/debug.h"
48 #include "ac_exp_param.h"
49
50 static void
51 radv_pipeline_destroy(struct radv_device *device,
52 struct radv_pipeline *pipeline,
53 const VkAllocationCallbacks* allocator)
54 {
55 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
56 if (pipeline->shaders[i])
57 radv_shader_variant_destroy(device, pipeline->shaders[i]);
58
59 if (pipeline->gs_copy_shader)
60 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
61
62 vk_free2(&device->alloc, allocator, pipeline);
63 }
64
65 void radv_DestroyPipeline(
66 VkDevice _device,
67 VkPipeline _pipeline,
68 const VkAllocationCallbacks* pAllocator)
69 {
70 RADV_FROM_HANDLE(radv_device, device, _device);
71 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
72
73 if (!_pipeline)
74 return;
75
76 radv_pipeline_destroy(device, pipeline, pAllocator);
77 }
78
79 static void radv_dump_pipeline_stats(struct radv_device *device, struct radv_pipeline *pipeline)
80 {
81 int i;
82
83 for (i = 0; i < MESA_SHADER_STAGES; i++) {
84 if (!pipeline->shaders[i])
85 continue;
86
87 radv_shader_dump_stats(device, pipeline->shaders[i], i, stderr);
88 }
89 }
90
91 static uint32_t get_hash_flags(struct radv_device *device)
92 {
93 uint32_t hash_flags = 0;
94
95 if (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH)
96 hash_flags |= RADV_HASH_SHADER_UNSAFE_MATH;
97 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
98 hash_flags |= RADV_HASH_SHADER_SISCHED;
99 return hash_flags;
100 }
101
102 static VkResult
103 radv_pipeline_scratch_init(struct radv_device *device,
104 struct radv_pipeline *pipeline)
105 {
106 unsigned scratch_bytes_per_wave = 0;
107 unsigned max_waves = 0;
108 unsigned min_waves = 1;
109
110 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
111 if (pipeline->shaders[i]) {
112 unsigned max_stage_waves = device->scratch_waves;
113
114 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
115 pipeline->shaders[i]->config.scratch_bytes_per_wave);
116
117 max_stage_waves = MIN2(max_stage_waves,
118 4 * device->physical_device->rad_info.num_good_compute_units *
119 (256 / pipeline->shaders[i]->config.num_vgprs));
120 max_waves = MAX2(max_waves, max_stage_waves);
121 }
122 }
123
124 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
125 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
126 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
127 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
128 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
129 }
130
131 if (scratch_bytes_per_wave)
132 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
133
134 if (scratch_bytes_per_wave && max_waves < min_waves) {
135 /* Not really true at this moment, but will be true on first
136 * execution. Avoid having hanging shaders. */
137 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
138 }
139 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
140 pipeline->max_waves = max_waves;
141 return VK_SUCCESS;
142 }
143
144 static uint32_t si_translate_blend_function(VkBlendOp op)
145 {
146 switch (op) {
147 case VK_BLEND_OP_ADD:
148 return V_028780_COMB_DST_PLUS_SRC;
149 case VK_BLEND_OP_SUBTRACT:
150 return V_028780_COMB_SRC_MINUS_DST;
151 case VK_BLEND_OP_REVERSE_SUBTRACT:
152 return V_028780_COMB_DST_MINUS_SRC;
153 case VK_BLEND_OP_MIN:
154 return V_028780_COMB_MIN_DST_SRC;
155 case VK_BLEND_OP_MAX:
156 return V_028780_COMB_MAX_DST_SRC;
157 default:
158 return 0;
159 }
160 }
161
162 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
163 {
164 switch (factor) {
165 case VK_BLEND_FACTOR_ZERO:
166 return V_028780_BLEND_ZERO;
167 case VK_BLEND_FACTOR_ONE:
168 return V_028780_BLEND_ONE;
169 case VK_BLEND_FACTOR_SRC_COLOR:
170 return V_028780_BLEND_SRC_COLOR;
171 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
172 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
173 case VK_BLEND_FACTOR_DST_COLOR:
174 return V_028780_BLEND_DST_COLOR;
175 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
176 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
177 case VK_BLEND_FACTOR_SRC_ALPHA:
178 return V_028780_BLEND_SRC_ALPHA;
179 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
180 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
181 case VK_BLEND_FACTOR_DST_ALPHA:
182 return V_028780_BLEND_DST_ALPHA;
183 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
184 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
185 case VK_BLEND_FACTOR_CONSTANT_COLOR:
186 return V_028780_BLEND_CONSTANT_COLOR;
187 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
188 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
189 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
190 return V_028780_BLEND_CONSTANT_ALPHA;
191 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
192 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
193 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
194 return V_028780_BLEND_SRC_ALPHA_SATURATE;
195 case VK_BLEND_FACTOR_SRC1_COLOR:
196 return V_028780_BLEND_SRC1_COLOR;
197 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
198 return V_028780_BLEND_INV_SRC1_COLOR;
199 case VK_BLEND_FACTOR_SRC1_ALPHA:
200 return V_028780_BLEND_SRC1_ALPHA;
201 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
202 return V_028780_BLEND_INV_SRC1_ALPHA;
203 default:
204 return 0;
205 }
206 }
207
208 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
209 {
210 switch (op) {
211 case VK_BLEND_OP_ADD:
212 return V_028760_OPT_COMB_ADD;
213 case VK_BLEND_OP_SUBTRACT:
214 return V_028760_OPT_COMB_SUBTRACT;
215 case VK_BLEND_OP_REVERSE_SUBTRACT:
216 return V_028760_OPT_COMB_REVSUBTRACT;
217 case VK_BLEND_OP_MIN:
218 return V_028760_OPT_COMB_MIN;
219 case VK_BLEND_OP_MAX:
220 return V_028760_OPT_COMB_MAX;
221 default:
222 return V_028760_OPT_COMB_BLEND_DISABLED;
223 }
224 }
225
226 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
227 {
228 switch (factor) {
229 case VK_BLEND_FACTOR_ZERO:
230 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
231 case VK_BLEND_FACTOR_ONE:
232 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
233 case VK_BLEND_FACTOR_SRC_COLOR:
234 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
235 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
236 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
237 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
238 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
239 case VK_BLEND_FACTOR_SRC_ALPHA:
240 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
241 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
242 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
243 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
244 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
245 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
246 default:
247 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
248 }
249 }
250
251 /**
252 * Get rid of DST in the blend factors by commuting the operands:
253 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
254 */
255 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
256 unsigned *dst_factor, unsigned expected_dst,
257 unsigned replacement_src)
258 {
259 if (*src_factor == expected_dst &&
260 *dst_factor == VK_BLEND_FACTOR_ZERO) {
261 *src_factor = VK_BLEND_FACTOR_ZERO;
262 *dst_factor = replacement_src;
263
264 /* Commuting the operands requires reversing subtractions. */
265 if (*func == VK_BLEND_OP_SUBTRACT)
266 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
267 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
268 *func = VK_BLEND_OP_SUBTRACT;
269 }
270 }
271
272 static bool si_blend_factor_uses_dst(unsigned factor)
273 {
274 return factor == VK_BLEND_FACTOR_DST_COLOR ||
275 factor == VK_BLEND_FACTOR_DST_ALPHA ||
276 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
277 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
278 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
279 }
280
281 static bool is_dual_src(VkBlendFactor factor)
282 {
283 switch (factor) {
284 case VK_BLEND_FACTOR_SRC1_COLOR:
285 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
286 case VK_BLEND_FACTOR_SRC1_ALPHA:
287 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
288 return true;
289 default:
290 return false;
291 }
292 }
293
294 static unsigned si_choose_spi_color_format(VkFormat vk_format,
295 bool blend_enable,
296 bool blend_need_alpha)
297 {
298 const struct vk_format_description *desc = vk_format_description(vk_format);
299 unsigned format, ntype, swap;
300
301 /* Alpha is needed for alpha-to-coverage.
302 * Blending may be with or without alpha.
303 */
304 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
305 unsigned alpha = 0; /* exports alpha, but may not support blending */
306 unsigned blend = 0; /* supports blending, but may not export alpha */
307 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
308
309 format = radv_translate_colorformat(vk_format);
310 ntype = radv_translate_color_numformat(vk_format, desc,
311 vk_format_get_first_non_void_channel(vk_format));
312 swap = radv_translate_colorswap(vk_format, false);
313
314 /* Choose the SPI color formats. These are required values for Stoney/RB+.
315 * Other chips have multiple choices, though they are not necessarily better.
316 */
317 switch (format) {
318 case V_028C70_COLOR_5_6_5:
319 case V_028C70_COLOR_1_5_5_5:
320 case V_028C70_COLOR_5_5_5_1:
321 case V_028C70_COLOR_4_4_4_4:
322 case V_028C70_COLOR_10_11_11:
323 case V_028C70_COLOR_11_11_10:
324 case V_028C70_COLOR_8:
325 case V_028C70_COLOR_8_8:
326 case V_028C70_COLOR_8_8_8_8:
327 case V_028C70_COLOR_10_10_10_2:
328 case V_028C70_COLOR_2_10_10_10:
329 if (ntype == V_028C70_NUMBER_UINT)
330 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
331 else if (ntype == V_028C70_NUMBER_SINT)
332 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
333 else
334 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
335 break;
336
337 case V_028C70_COLOR_16:
338 case V_028C70_COLOR_16_16:
339 case V_028C70_COLOR_16_16_16_16:
340 if (ntype == V_028C70_NUMBER_UNORM ||
341 ntype == V_028C70_NUMBER_SNORM) {
342 /* UNORM16 and SNORM16 don't support blending */
343 if (ntype == V_028C70_NUMBER_UNORM)
344 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
345 else
346 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
347
348 /* Use 32 bits per channel for blending. */
349 if (format == V_028C70_COLOR_16) {
350 if (swap == V_028C70_SWAP_STD) { /* R */
351 blend = V_028714_SPI_SHADER_32_R;
352 blend_alpha = V_028714_SPI_SHADER_32_AR;
353 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
354 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
355 else
356 assert(0);
357 } else if (format == V_028C70_COLOR_16_16) {
358 if (swap == V_028C70_SWAP_STD) { /* RG */
359 blend = V_028714_SPI_SHADER_32_GR;
360 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
361 } else if (swap == V_028C70_SWAP_ALT) /* RA */
362 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
363 else
364 assert(0);
365 } else /* 16_16_16_16 */
366 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
367 } else if (ntype == V_028C70_NUMBER_UINT)
368 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
369 else if (ntype == V_028C70_NUMBER_SINT)
370 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
371 else if (ntype == V_028C70_NUMBER_FLOAT)
372 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
373 else
374 assert(0);
375 break;
376
377 case V_028C70_COLOR_32:
378 if (swap == V_028C70_SWAP_STD) { /* R */
379 blend = normal = V_028714_SPI_SHADER_32_R;
380 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
381 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
382 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
383 else
384 assert(0);
385 break;
386
387 case V_028C70_COLOR_32_32:
388 if (swap == V_028C70_SWAP_STD) { /* RG */
389 blend = normal = V_028714_SPI_SHADER_32_GR;
390 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
391 } else if (swap == V_028C70_SWAP_ALT) /* RA */
392 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
393 else
394 assert(0);
395 break;
396
397 case V_028C70_COLOR_32_32_32_32:
398 case V_028C70_COLOR_8_24:
399 case V_028C70_COLOR_24_8:
400 case V_028C70_COLOR_X24_8_32_FLOAT:
401 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
402 break;
403
404 default:
405 unreachable("unhandled blend format");
406 }
407
408 if (blend_enable && blend_need_alpha)
409 return blend_alpha;
410 else if(blend_need_alpha)
411 return alpha;
412 else if(blend_enable)
413 return blend;
414 else
415 return normal;
416 }
417
418 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
419 {
420 unsigned i, cb_shader_mask = 0;
421
422 for (i = 0; i < 8; i++) {
423 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
424 case V_028714_SPI_SHADER_ZERO:
425 break;
426 case V_028714_SPI_SHADER_32_R:
427 cb_shader_mask |= 0x1 << (i * 4);
428 break;
429 case V_028714_SPI_SHADER_32_GR:
430 cb_shader_mask |= 0x3 << (i * 4);
431 break;
432 case V_028714_SPI_SHADER_32_AR:
433 cb_shader_mask |= 0x9 << (i * 4);
434 break;
435 case V_028714_SPI_SHADER_FP16_ABGR:
436 case V_028714_SPI_SHADER_UNORM16_ABGR:
437 case V_028714_SPI_SHADER_SNORM16_ABGR:
438 case V_028714_SPI_SHADER_UINT16_ABGR:
439 case V_028714_SPI_SHADER_SINT16_ABGR:
440 case V_028714_SPI_SHADER_32_ABGR:
441 cb_shader_mask |= 0xf << (i * 4);
442 break;
443 default:
444 assert(0);
445 }
446 }
447 return cb_shader_mask;
448 }
449
450 static void
451 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
452 const VkGraphicsPipelineCreateInfo *pCreateInfo,
453 uint32_t blend_enable,
454 uint32_t blend_need_alpha,
455 bool single_cb_enable,
456 bool blend_mrt0_is_dual_src)
457 {
458 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
459 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
460 struct radv_blend_state *blend = &pipeline->graphics.blend;
461 unsigned col_format = 0;
462
463 for (unsigned i = 0; i < (single_cb_enable ? 1 : subpass->color_count); ++i) {
464 unsigned cf;
465
466 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
467 cf = V_028714_SPI_SHADER_ZERO;
468 } else {
469 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
470
471 cf = si_choose_spi_color_format(attachment->format,
472 blend_enable & (1 << i),
473 blend_need_alpha & (1 << i));
474 }
475
476 col_format |= cf << (4 * i);
477 }
478
479 blend->cb_shader_mask = si_get_cb_shader_mask(col_format);
480
481 if (blend_mrt0_is_dual_src)
482 col_format |= (col_format & 0xf) << 4;
483 blend->spi_shader_col_format = col_format;
484 }
485
486 static bool
487 format_is_int8(VkFormat format)
488 {
489 const struct vk_format_description *desc = vk_format_description(format);
490 int channel = vk_format_get_first_non_void_channel(format);
491
492 return channel >= 0 && desc->channel[channel].pure_integer &&
493 desc->channel[channel].size == 8;
494 }
495
496 static bool
497 format_is_int10(VkFormat format)
498 {
499 const struct vk_format_description *desc = vk_format_description(format);
500
501 if (desc->nr_channels != 4)
502 return false;
503 for (unsigned i = 0; i < 4; i++) {
504 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
505 return true;
506 }
507 return false;
508 }
509
510 unsigned radv_format_meta_fs_key(VkFormat format)
511 {
512 unsigned col_format = si_choose_spi_color_format(format, false, false) - 1;
513 bool is_int8 = format_is_int8(format);
514 bool is_int10 = format_is_int10(format);
515
516 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
517 }
518
519 static void
520 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo *pCreateInfo,
521 unsigned *is_int8, unsigned *is_int10)
522 {
523 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
524 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
525 *is_int8 = 0;
526 *is_int10 = 0;
527
528 for (unsigned i = 0; i < subpass->color_count; ++i) {
529 struct radv_render_pass_attachment *attachment;
530
531 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
532 continue;
533
534 attachment = pass->attachments + subpass->color_attachments[i].attachment;
535
536 if (format_is_int8(attachment->format))
537 *is_int8 |= 1 << i;
538 if (format_is_int10(attachment->format))
539 *is_int10 |= 1 << i;
540 }
541 }
542
543 static void
544 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
545 const VkGraphicsPipelineCreateInfo *pCreateInfo,
546 const struct radv_graphics_pipeline_create_info *extra)
547 {
548 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
549 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
550 struct radv_blend_state *blend = &pipeline->graphics.blend;
551 unsigned mode = V_028808_CB_NORMAL;
552 uint32_t blend_enable = 0, blend_need_alpha = 0;
553 bool blend_mrt0_is_dual_src = false;
554 int i;
555 bool single_cb_enable = false;
556
557 if (!vkblend)
558 return;
559
560 if (extra && extra->custom_blend_mode) {
561 single_cb_enable = true;
562 mode = extra->custom_blend_mode;
563 }
564 blend->cb_color_control = 0;
565 if (vkblend->logicOpEnable)
566 blend->cb_color_control |= S_028808_ROP3(vkblend->logicOp | (vkblend->logicOp << 4));
567 else
568 blend->cb_color_control |= S_028808_ROP3(0xcc);
569
570 blend->db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
571 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
572 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
573 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
574
575 if (vkms && vkms->alphaToCoverageEnable) {
576 blend->db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
577 }
578
579 blend->cb_target_mask = 0;
580 for (i = 0; i < vkblend->attachmentCount; i++) {
581 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
582 unsigned blend_cntl = 0;
583 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
584 VkBlendOp eqRGB = att->colorBlendOp;
585 VkBlendFactor srcRGB = att->srcColorBlendFactor;
586 VkBlendFactor dstRGB = att->dstColorBlendFactor;
587 VkBlendOp eqA = att->alphaBlendOp;
588 VkBlendFactor srcA = att->srcAlphaBlendFactor;
589 VkBlendFactor dstA = att->dstAlphaBlendFactor;
590
591 blend->sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
592
593 if (!att->colorWriteMask)
594 continue;
595
596 blend->cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
597 if (!att->blendEnable) {
598 blend->cb_blend_control[i] = blend_cntl;
599 continue;
600 }
601
602 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
603 if (i == 0)
604 blend_mrt0_is_dual_src = true;
605
606 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
607 srcRGB = VK_BLEND_FACTOR_ONE;
608 dstRGB = VK_BLEND_FACTOR_ONE;
609 }
610 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
611 srcA = VK_BLEND_FACTOR_ONE;
612 dstA = VK_BLEND_FACTOR_ONE;
613 }
614
615 /* Blending optimizations for RB+.
616 * These transformations don't change the behavior.
617 *
618 * First, get rid of DST in the blend factors:
619 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
620 */
621 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
622 VK_BLEND_FACTOR_DST_COLOR,
623 VK_BLEND_FACTOR_SRC_COLOR);
624
625 si_blend_remove_dst(&eqA, &srcA, &dstA,
626 VK_BLEND_FACTOR_DST_COLOR,
627 VK_BLEND_FACTOR_SRC_COLOR);
628
629 si_blend_remove_dst(&eqA, &srcA, &dstA,
630 VK_BLEND_FACTOR_DST_ALPHA,
631 VK_BLEND_FACTOR_SRC_ALPHA);
632
633 /* Look up the ideal settings from tables. */
634 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
635 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
636 srcA_opt = si_translate_blend_opt_factor(srcA, true);
637 dstA_opt = si_translate_blend_opt_factor(dstA, true);
638
639 /* Handle interdependencies. */
640 if (si_blend_factor_uses_dst(srcRGB))
641 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
642 if (si_blend_factor_uses_dst(srcA))
643 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
644
645 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
646 (dstRGB == VK_BLEND_FACTOR_ZERO ||
647 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
648 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
649 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
650
651 /* Set the final value. */
652 blend->sx_mrt_blend_opt[i] =
653 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
654 S_028760_COLOR_DST_OPT(dstRGB_opt) |
655 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
656 S_028760_ALPHA_SRC_OPT(srcA_opt) |
657 S_028760_ALPHA_DST_OPT(dstA_opt) |
658 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
659 blend_cntl |= S_028780_ENABLE(1);
660
661 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
662 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
663 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
664 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
665 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
666 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
667 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
668 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
669 }
670 blend->cb_blend_control[i] = blend_cntl;
671
672 blend_enable |= 1 << i;
673
674 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
675 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
676 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
677 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
678 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
679 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
680 blend_need_alpha |= 1 << i;
681 }
682 for (i = vkblend->attachmentCount; i < 8; i++) {
683 blend->cb_blend_control[i] = 0;
684 blend->sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
685 }
686
687 /* disable RB+ for now */
688 if (pipeline->device->physical_device->has_rbplus)
689 blend->cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
690
691 if (blend->cb_target_mask)
692 blend->cb_color_control |= S_028808_MODE(mode);
693 else
694 blend->cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
695
696 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo,
697 blend_enable, blend_need_alpha, single_cb_enable, blend_mrt0_is_dual_src);
698 }
699
700 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
701 {
702 switch (op) {
703 case VK_STENCIL_OP_KEEP:
704 return V_02842C_STENCIL_KEEP;
705 case VK_STENCIL_OP_ZERO:
706 return V_02842C_STENCIL_ZERO;
707 case VK_STENCIL_OP_REPLACE:
708 return V_02842C_STENCIL_REPLACE_TEST;
709 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
710 return V_02842C_STENCIL_ADD_CLAMP;
711 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
712 return V_02842C_STENCIL_SUB_CLAMP;
713 case VK_STENCIL_OP_INVERT:
714 return V_02842C_STENCIL_INVERT;
715 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
716 return V_02842C_STENCIL_ADD_WRAP;
717 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
718 return V_02842C_STENCIL_SUB_WRAP;
719 default:
720 return 0;
721 }
722 }
723 static void
724 radv_pipeline_init_depth_stencil_state(struct radv_pipeline *pipeline,
725 const VkGraphicsPipelineCreateInfo *pCreateInfo,
726 const struct radv_graphics_pipeline_create_info *extra)
727 {
728 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
729 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
730
731 if (!vkds)
732 return;
733
734 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
735 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
736 if (subpass->depth_stencil_attachment.attachment == VK_ATTACHMENT_UNUSED)
737 return;
738
739 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment.attachment;
740 bool has_depth_attachment = vk_format_is_depth(attachment->format);
741 bool has_stencil_attachment = vk_format_is_stencil(attachment->format);
742
743 if (has_depth_attachment) {
744 ds->db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
745 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
746 S_028800_ZFUNC(vkds->depthCompareOp) |
747 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
748 }
749
750 if (has_stencil_attachment && vkds->stencilTestEnable) {
751 ds->db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
752 ds->db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
753 ds->db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
754 ds->db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
755 ds->db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
756
757 ds->db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
758 ds->db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
759 ds->db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
760 ds->db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
761 }
762
763 if (extra) {
764
765 ds->db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
766 ds->db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
767
768 ds->db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
769 ds->db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
770 ds->db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
771 ds->db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
772 ds->db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
773 }
774 }
775
776 static uint32_t si_translate_fill(VkPolygonMode func)
777 {
778 switch(func) {
779 case VK_POLYGON_MODE_FILL:
780 return V_028814_X_DRAW_TRIANGLES;
781 case VK_POLYGON_MODE_LINE:
782 return V_028814_X_DRAW_LINES;
783 case VK_POLYGON_MODE_POINT:
784 return V_028814_X_DRAW_POINTS;
785 default:
786 assert(0);
787 return V_028814_X_DRAW_POINTS;
788 }
789 }
790 static void
791 radv_pipeline_init_raster_state(struct radv_pipeline *pipeline,
792 const VkGraphicsPipelineCreateInfo *pCreateInfo)
793 {
794 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
795 struct radv_raster_state *raster = &pipeline->graphics.raster;
796
797 raster->spi_interp_control =
798 S_0286D4_FLAT_SHADE_ENA(1) |
799 S_0286D4_PNT_SPRITE_ENA(1) |
800 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
801 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
802 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
803 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
804 S_0286D4_PNT_SPRITE_TOP_1(0); // vulkan is top to bottom - 1.0 at bottom
805
806
807 raster->pa_cl_clip_cntl = S_028810_PS_UCP_MODE(3) |
808 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
809 S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
810 S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
811 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
812 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
813
814 raster->pa_su_vtx_cntl =
815 S_028BE4_PIX_CENTER(1) | // TODO verify
816 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
817 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH);
818
819 raster->pa_su_sc_mode_cntl =
820 S_028814_FACE(vkraster->frontFace) |
821 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
822 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
823 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
824 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
825 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
826 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
827 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
828 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0);
829
830 }
831
832 static void
833 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
834 const VkGraphicsPipelineCreateInfo *pCreateInfo)
835 {
836 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
837 struct radv_multisample_state *ms = &pipeline->graphics.ms;
838 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
839 int ps_iter_samples = 1;
840 uint32_t mask = 0xffff;
841
842 if (vkms)
843 ms->num_samples = vkms->rasterizationSamples;
844 else
845 ms->num_samples = 1;
846
847 if (vkms && vkms->sampleShadingEnable) {
848 ps_iter_samples = ceil(vkms->minSampleShading * ms->num_samples);
849 } else if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.force_persample) {
850 ps_iter_samples = ms->num_samples;
851 }
852
853 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
854 ms->pa_sc_aa_config = 0;
855 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
856 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
857 ms->pa_sc_mode_cntl_1 =
858 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
859 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
860 /* always 1: */
861 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
862 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
863 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
864 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
865 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
866 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
867 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9);
868
869 if (ms->num_samples > 1) {
870 unsigned log_samples = util_logbase2(ms->num_samples);
871 unsigned log_ps_iter_samples = util_logbase2(util_next_power_of_two(ps_iter_samples));
872 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
873 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
874 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
875 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
876 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
877 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
878 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
879 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
880 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
881 ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
882 }
883
884 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
885 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
886 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
887 ms->pa_sc_mode_cntl_1 |= S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(1) |
888 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7);
889 }
890
891 if (vkms && vkms->pSampleMask) {
892 mask = vkms->pSampleMask[0] & 0xffff;
893 }
894
895 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
896 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
897 }
898
899 static bool
900 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
901 {
902 switch (topology) {
903 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
904 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
905 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
906 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
907 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
908 return false;
909 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
910 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
911 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
912 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
913 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
914 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
915 return true;
916 default:
917 unreachable("unhandled primitive type");
918 }
919 }
920
921 static uint32_t
922 si_translate_prim(enum VkPrimitiveTopology topology)
923 {
924 switch (topology) {
925 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
926 return V_008958_DI_PT_POINTLIST;
927 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
928 return V_008958_DI_PT_LINELIST;
929 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
930 return V_008958_DI_PT_LINESTRIP;
931 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
932 return V_008958_DI_PT_TRILIST;
933 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
934 return V_008958_DI_PT_TRISTRIP;
935 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
936 return V_008958_DI_PT_TRIFAN;
937 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
938 return V_008958_DI_PT_LINELIST_ADJ;
939 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
940 return V_008958_DI_PT_LINESTRIP_ADJ;
941 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
942 return V_008958_DI_PT_TRILIST_ADJ;
943 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
944 return V_008958_DI_PT_TRISTRIP_ADJ;
945 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
946 return V_008958_DI_PT_PATCH;
947 default:
948 assert(0);
949 return 0;
950 }
951 }
952
953 static uint32_t
954 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
955 {
956 switch (gl_prim) {
957 case 0: /* GL_POINTS */
958 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
959 case 1: /* GL_LINES */
960 case 3: /* GL_LINE_STRIP */
961 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
962 case 0x8E7A: /* GL_ISOLINES */
963 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
964
965 case 4: /* GL_TRIANGLES */
966 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
967 case 5: /* GL_TRIANGLE_STRIP */
968 case 7: /* GL_QUADS */
969 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
970 default:
971 assert(0);
972 return 0;
973 }
974 }
975
976 static uint32_t
977 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
978 {
979 switch (topology) {
980 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
981 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
982 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
983 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
984 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
985 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
986 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
987 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
988 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
989 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
990 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
991 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
992 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
993 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
994 default:
995 assert(0);
996 return 0;
997 }
998 }
999
1000 static unsigned si_map_swizzle(unsigned swizzle)
1001 {
1002 switch (swizzle) {
1003 case VK_SWIZZLE_Y:
1004 return V_008F0C_SQ_SEL_Y;
1005 case VK_SWIZZLE_Z:
1006 return V_008F0C_SQ_SEL_Z;
1007 case VK_SWIZZLE_W:
1008 return V_008F0C_SQ_SEL_W;
1009 case VK_SWIZZLE_0:
1010 return V_008F0C_SQ_SEL_0;
1011 case VK_SWIZZLE_1:
1012 return V_008F0C_SQ_SEL_1;
1013 default: /* VK_SWIZZLE_X */
1014 return V_008F0C_SQ_SEL_X;
1015 }
1016 }
1017
1018 static void
1019 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1020 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1021 {
1022 radv_cmd_dirty_mask_t states = RADV_CMD_DIRTY_DYNAMIC_ALL;
1023 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1024 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1025
1026 pipeline->dynamic_state = default_dynamic_state;
1027
1028 if (pCreateInfo->pDynamicState) {
1029 /* Remove all of the states that are marked as dynamic */
1030 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1031 for (uint32_t s = 0; s < count; s++)
1032 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
1033 }
1034
1035 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1036
1037 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1038 *
1039 * pViewportState is [...] NULL if the pipeline
1040 * has rasterization disabled.
1041 */
1042 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1043 assert(pCreateInfo->pViewportState);
1044
1045 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1046 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
1047 typed_memcpy(dynamic->viewport.viewports,
1048 pCreateInfo->pViewportState->pViewports,
1049 pCreateInfo->pViewportState->viewportCount);
1050 }
1051
1052 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1053 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
1054 typed_memcpy(dynamic->scissor.scissors,
1055 pCreateInfo->pViewportState->pScissors,
1056 pCreateInfo->pViewportState->scissorCount);
1057 }
1058 }
1059
1060 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
1061 assert(pCreateInfo->pRasterizationState);
1062 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1063 }
1064
1065 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
1066 assert(pCreateInfo->pRasterizationState);
1067 dynamic->depth_bias.bias =
1068 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1069 dynamic->depth_bias.clamp =
1070 pCreateInfo->pRasterizationState->depthBiasClamp;
1071 dynamic->depth_bias.slope =
1072 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1073 }
1074
1075 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1076 *
1077 * pColorBlendState is [...] NULL if the pipeline has rasterization
1078 * disabled or if the subpass of the render pass the pipeline is
1079 * created against does not use any color attachments.
1080 */
1081 bool uses_color_att = false;
1082 for (unsigned i = 0; i < subpass->color_count; ++i) {
1083 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1084 uses_color_att = true;
1085 break;
1086 }
1087 }
1088
1089 if (uses_color_att && states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
1090 assert(pCreateInfo->pColorBlendState);
1091 typed_memcpy(dynamic->blend_constants,
1092 pCreateInfo->pColorBlendState->blendConstants, 4);
1093 }
1094
1095 /* If there is no depthstencil attachment, then don't read
1096 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1097 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1098 * no need to override the depthstencil defaults in
1099 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1100 *
1101 * Section 9.2 of the Vulkan 1.0.15 spec says:
1102 *
1103 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1104 * disabled or if the subpass of the render pass the pipeline is created
1105 * against does not use a depth/stencil attachment.
1106 */
1107 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
1108 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1109 assert(pCreateInfo->pDepthStencilState);
1110
1111 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
1112 dynamic->depth_bounds.min =
1113 pCreateInfo->pDepthStencilState->minDepthBounds;
1114 dynamic->depth_bounds.max =
1115 pCreateInfo->pDepthStencilState->maxDepthBounds;
1116 }
1117
1118 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
1119 dynamic->stencil_compare_mask.front =
1120 pCreateInfo->pDepthStencilState->front.compareMask;
1121 dynamic->stencil_compare_mask.back =
1122 pCreateInfo->pDepthStencilState->back.compareMask;
1123 }
1124
1125 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
1126 dynamic->stencil_write_mask.front =
1127 pCreateInfo->pDepthStencilState->front.writeMask;
1128 dynamic->stencil_write_mask.back =
1129 pCreateInfo->pDepthStencilState->back.writeMask;
1130 }
1131
1132 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
1133 dynamic->stencil_reference.front =
1134 pCreateInfo->pDepthStencilState->front.reference;
1135 dynamic->stencil_reference.back =
1136 pCreateInfo->pDepthStencilState->back.reference;
1137 }
1138 }
1139
1140 pipeline->dynamic_state_mask = states;
1141 }
1142
1143 static struct ac_shader_variant_key
1144 radv_compute_vs_key(const VkGraphicsPipelineCreateInfo *pCreateInfo, bool as_es, bool as_ls)
1145 {
1146 struct ac_shader_variant_key key;
1147 const VkPipelineVertexInputStateCreateInfo *input_state =
1148 pCreateInfo->pVertexInputState;
1149
1150 memset(&key, 0, sizeof(key));
1151 key.vs.instance_rate_inputs = 0;
1152 key.vs.as_es = as_es;
1153 key.vs.as_ls = as_ls;
1154
1155 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
1156 unsigned binding;
1157 binding = input_state->pVertexAttributeDescriptions[i].binding;
1158 if (input_state->pVertexBindingDescriptions[binding].inputRate)
1159 key.vs.instance_rate_inputs |= 1u << input_state->pVertexAttributeDescriptions[i].location;
1160 }
1161 return key;
1162 }
1163
1164 static void
1165 calculate_gs_ring_sizes(struct radv_pipeline *pipeline)
1166 {
1167 struct radv_device *device = pipeline->device;
1168 unsigned num_se = device->physical_device->rad_info.max_se;
1169 unsigned wave_size = 64;
1170 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1171 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1172 unsigned alignment = 256 * num_se;
1173 /* The maximum size is 63.999 MB per SE. */
1174 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1175 struct ac_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1176 struct ac_es_output_info *es_info = radv_pipeline_has_tess(pipeline) ?
1177 &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.es_info :
1178 &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info;
1179
1180 /* Calculate the minimum size. */
1181 unsigned min_esgs_ring_size = align(es_info->esgs_itemsize * gs_vertex_reuse *
1182 wave_size, alignment);
1183 /* These are recommended sizes, not minimum sizes. */
1184 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1185 es_info->esgs_itemsize * gs_info->gs.vertices_in;
1186 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1187 gs_info->gs.max_gsvs_emit_size * 1; // no streams in VK (gs->max_gs_stream + 1);
1188
1189 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1190 esgs_ring_size = align(esgs_ring_size, alignment);
1191 gsvs_ring_size = align(gsvs_ring_size, alignment);
1192
1193 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1194 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1195 }
1196
1197 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1198 unsigned *lds_size)
1199 {
1200 /* SPI barrier management bug:
1201 * Make sure we have at least 4k of LDS in use to avoid the bug.
1202 * It applies to workgroup sizes of more than one wavefront.
1203 */
1204 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1205 device->physical_device->rad_info.family == CHIP_KABINI ||
1206 device->physical_device->rad_info.family == CHIP_MULLINS)
1207 *lds_size = MAX2(*lds_size, 8);
1208 }
1209
1210 struct radv_shader_variant *
1211 radv_get_vertex_shader(struct radv_pipeline *pipeline)
1212 {
1213 if (pipeline->shaders[MESA_SHADER_VERTEX])
1214 return pipeline->shaders[MESA_SHADER_VERTEX];
1215 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
1216 return pipeline->shaders[MESA_SHADER_TESS_CTRL];
1217 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1218 }
1219
1220 static void
1221 calculate_tess_state(struct radv_pipeline *pipeline,
1222 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1223 {
1224 unsigned num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1225 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
1226 unsigned num_tcs_patch_outputs;
1227 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
1228 unsigned input_patch_size, output_patch_size, output_patch0_offset;
1229 unsigned lds_size, hardware_lds_size;
1230 unsigned perpatch_output_offset;
1231 unsigned num_patches;
1232 struct radv_tessellation_state *tess = &pipeline->graphics.tess;
1233
1234 /* This calculates how shader inputs and outputs among VS, TCS, and TES
1235 * are laid out in LDS. */
1236 num_tcs_inputs = util_last_bit64(radv_get_vertex_shader(pipeline)->info.vs.outputs_written);
1237
1238 num_tcs_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written); //tcs->outputs_written
1239 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1240 num_tcs_patch_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.patch_outputs_written);
1241
1242 /* Ensure that we only need one wave per SIMD so we don't need to check
1243 * resource usage. Also ensures that the number of tcs in and out
1244 * vertices per threadgroup are at most 256.
1245 */
1246 input_vertex_size = num_tcs_inputs * 16;
1247 output_vertex_size = num_tcs_outputs * 16;
1248
1249 input_patch_size = num_tcs_input_cp * input_vertex_size;
1250
1251 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
1252 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
1253 /* Ensure that we only need one wave per SIMD so we don't need to check
1254 * resource usage. Also ensures that the number of tcs in and out
1255 * vertices per threadgroup are at most 256.
1256 */
1257 num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
1258
1259 /* Make sure that the data fits in LDS. This assumes the shaders only
1260 * use LDS for the inputs and outputs.
1261 */
1262 hardware_lds_size = pipeline->device->physical_device->rad_info.chip_class >= CIK ? 65536 : 32768;
1263 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
1264
1265 /* Make sure the output data fits in the offchip buffer */
1266 num_patches = MIN2(num_patches,
1267 (pipeline->device->tess_offchip_block_dw_size * 4) /
1268 output_patch_size);
1269
1270 /* Not necessary for correctness, but improves performance. The
1271 * specific value is taken from the proprietary driver.
1272 */
1273 num_patches = MIN2(num_patches, 40);
1274
1275 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
1276 if (pipeline->device->physical_device->rad_info.chip_class == SI) {
1277 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
1278 num_patches = MIN2(num_patches, one_wave);
1279 }
1280
1281 output_patch0_offset = input_patch_size * num_patches;
1282 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
1283
1284 lds_size = output_patch0_offset + output_patch_size * num_patches;
1285
1286 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
1287 assert(lds_size <= 65536);
1288 lds_size = align(lds_size, 512) / 512;
1289 } else {
1290 assert(lds_size <= 32768);
1291 lds_size = align(lds_size, 256) / 256;
1292 }
1293 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1294
1295 tess->lds_size = lds_size;
1296
1297 tess->tcs_in_layout = (input_patch_size / 4) |
1298 ((input_vertex_size / 4) << 13);
1299 tess->tcs_out_layout = (output_patch_size / 4) |
1300 ((output_vertex_size / 4) << 13);
1301 tess->tcs_out_offsets = (output_patch0_offset / 16) |
1302 ((perpatch_output_offset / 16) << 16);
1303 tess->offchip_layout = (pervertex_output_patch_size * num_patches << 16) |
1304 (num_tcs_output_cp << 9) | num_patches;
1305
1306 tess->ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1307 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1308 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1309 tess->num_patches = num_patches;
1310 tess->num_tcs_input_cp = num_tcs_input_cp;
1311
1312 struct radv_shader_variant *tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
1313 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1314
1315 switch (tes->info.tes.primitive_mode) {
1316 case GL_TRIANGLES:
1317 type = V_028B6C_TESS_TRIANGLE;
1318 break;
1319 case GL_QUADS:
1320 type = V_028B6C_TESS_QUAD;
1321 break;
1322 case GL_ISOLINES:
1323 type = V_028B6C_TESS_ISOLINE;
1324 break;
1325 }
1326
1327 switch (tes->info.tes.spacing) {
1328 case TESS_SPACING_EQUAL:
1329 partitioning = V_028B6C_PART_INTEGER;
1330 break;
1331 case TESS_SPACING_FRACTIONAL_ODD:
1332 partitioning = V_028B6C_PART_FRAC_ODD;
1333 break;
1334 case TESS_SPACING_FRACTIONAL_EVEN:
1335 partitioning = V_028B6C_PART_FRAC_EVEN;
1336 break;
1337 default:
1338 break;
1339 }
1340
1341 bool ccw = tes->info.tes.ccw;
1342 const VkPipelineTessellationDomainOriginStateCreateInfoKHR *domain_origin_state =
1343 vk_find_struct_const(pCreateInfo->pTessellationState,
1344 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO_KHR);
1345
1346 if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT_KHR)
1347 ccw = !ccw;
1348
1349 if (tes->info.tes.point_mode)
1350 topology = V_028B6C_OUTPUT_POINT;
1351 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
1352 topology = V_028B6C_OUTPUT_LINE;
1353 else if (ccw)
1354 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
1355 else
1356 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
1357
1358 if (pipeline->device->has_distributed_tess) {
1359 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
1360 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
1361 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
1362 else
1363 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
1364 } else
1365 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
1366
1367 tess->tf_param = S_028B6C_TYPE(type) |
1368 S_028B6C_PARTITIONING(partitioning) |
1369 S_028B6C_TOPOLOGY(topology) |
1370 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
1371 }
1372
1373 static const struct radv_prim_vertex_count prim_size_table[] = {
1374 [V_008958_DI_PT_NONE] = {0, 0},
1375 [V_008958_DI_PT_POINTLIST] = {1, 1},
1376 [V_008958_DI_PT_LINELIST] = {2, 2},
1377 [V_008958_DI_PT_LINESTRIP] = {2, 1},
1378 [V_008958_DI_PT_TRILIST] = {3, 3},
1379 [V_008958_DI_PT_TRIFAN] = {3, 1},
1380 [V_008958_DI_PT_TRISTRIP] = {3, 1},
1381 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
1382 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
1383 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
1384 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
1385 [V_008958_DI_PT_RECTLIST] = {3, 3},
1386 [V_008958_DI_PT_LINELOOP] = {2, 1},
1387 [V_008958_DI_PT_POLYGON] = {3, 1},
1388 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
1389 };
1390
1391 static uint32_t si_vgt_gs_mode(struct radv_shader_variant *gs,
1392 enum chip_class chip_class)
1393 {
1394 unsigned gs_max_vert_out = gs->info.gs.vertices_out;
1395 unsigned cut_mode;
1396
1397 if (gs_max_vert_out <= 128) {
1398 cut_mode = V_028A40_GS_CUT_128;
1399 } else if (gs_max_vert_out <= 256) {
1400 cut_mode = V_028A40_GS_CUT_256;
1401 } else if (gs_max_vert_out <= 512) {
1402 cut_mode = V_028A40_GS_CUT_512;
1403 } else {
1404 assert(gs_max_vert_out <= 1024);
1405 cut_mode = V_028A40_GS_CUT_1024;
1406 }
1407
1408 return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
1409 S_028A40_CUT_MODE(cut_mode)|
1410 S_028A40_ES_WRITE_OPTIMIZE(chip_class <= VI) |
1411 S_028A40_GS_WRITE_OPTIMIZE(1) |
1412 S_028A40_ONCHIP(chip_class >= GFX9 ? 1 : 0);
1413 }
1414
1415 static struct ac_vs_output_info *get_vs_output_info(struct radv_pipeline *pipeline)
1416 {
1417 if (radv_pipeline_has_gs(pipeline))
1418 return &pipeline->gs_copy_shader->info.vs.outinfo;
1419 else if (radv_pipeline_has_tess(pipeline))
1420 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
1421 else
1422 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
1423 }
1424
1425 static void calculate_vgt_gs_mode(struct radv_pipeline *pipeline)
1426 {
1427 struct ac_vs_output_info *outinfo = get_vs_output_info(pipeline);
1428
1429 pipeline->graphics.vgt_primitiveid_en = false;
1430 pipeline->graphics.vgt_gs_mode = 0;
1431
1432 if (radv_pipeline_has_gs(pipeline)) {
1433 pipeline->graphics.vgt_gs_mode = si_vgt_gs_mode(pipeline->shaders[MESA_SHADER_GEOMETRY],
1434 pipeline->device->physical_device->rad_info.chip_class);
1435 } else if (outinfo->export_prim_id) {
1436 pipeline->graphics.vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
1437 pipeline->graphics.vgt_primitiveid_en = true;
1438 }
1439 }
1440
1441 static void calculate_pa_cl_vs_out_cntl(struct radv_pipeline *pipeline)
1442 {
1443 struct ac_vs_output_info *outinfo = get_vs_output_info(pipeline);
1444
1445 unsigned clip_dist_mask, cull_dist_mask, total_mask;
1446 clip_dist_mask = outinfo->clip_dist_mask;
1447 cull_dist_mask = outinfo->cull_dist_mask;
1448 total_mask = clip_dist_mask | cull_dist_mask;
1449
1450 bool misc_vec_ena = outinfo->writes_pointsize ||
1451 outinfo->writes_layer ||
1452 outinfo->writes_viewport_index;
1453 pipeline->graphics.pa_cl_vs_out_cntl =
1454 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
1455 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
1456 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
1457 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
1458 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
1459 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
1460 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
1461 cull_dist_mask << 8 |
1462 clip_dist_mask;
1463
1464 }
1465
1466 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade)
1467 {
1468 uint32_t ps_input_cntl;
1469 if (offset <= AC_EXP_PARAM_OFFSET_31) {
1470 ps_input_cntl = S_028644_OFFSET(offset);
1471 if (flat_shade)
1472 ps_input_cntl |= S_028644_FLAT_SHADE(1);
1473 } else {
1474 /* The input is a DEFAULT_VAL constant. */
1475 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
1476 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
1477 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
1478 ps_input_cntl = S_028644_OFFSET(0x20) |
1479 S_028644_DEFAULT_VAL(offset);
1480 }
1481 return ps_input_cntl;
1482 }
1483
1484 static void calculate_ps_inputs(struct radv_pipeline *pipeline)
1485 {
1486 struct radv_shader_variant *ps;
1487 struct ac_vs_output_info *outinfo = get_vs_output_info(pipeline);
1488
1489 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
1490
1491 unsigned ps_offset = 0;
1492
1493 if (ps->info.fs.prim_id_input) {
1494 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
1495 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
1496 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
1497 ++ps_offset;
1498 }
1499 }
1500
1501 if (ps->info.fs.layer_input) {
1502 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
1503 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
1504 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
1505 else
1506 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true);
1507 ++ps_offset;
1508 }
1509
1510 if (ps->info.fs.has_pcoord) {
1511 unsigned val;
1512 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
1513 pipeline->graphics.ps_input_cntl[ps_offset] = val;
1514 ps_offset++;
1515 }
1516
1517 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
1518 unsigned vs_offset;
1519 bool flat_shade;
1520 if (!(ps->info.fs.input_mask & (1u << i)))
1521 continue;
1522
1523 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
1524 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
1525 pipeline->graphics.ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
1526 ++ps_offset;
1527 continue;
1528 }
1529
1530 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
1531
1532 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade);
1533 ++ps_offset;
1534 }
1535
1536 pipeline->graphics.ps_input_cntl_num = ps_offset;
1537 }
1538
1539 static void
1540 radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
1541 {
1542 nir_shader* ordered_shaders[MESA_SHADER_STAGES];
1543 int shader_count = 0;
1544
1545 if(shaders[MESA_SHADER_FRAGMENT]) {
1546 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
1547 }
1548 if(shaders[MESA_SHADER_GEOMETRY]) {
1549 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
1550 }
1551 if(shaders[MESA_SHADER_TESS_EVAL]) {
1552 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
1553 }
1554 if(shaders[MESA_SHADER_TESS_CTRL]) {
1555 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
1556 }
1557 if(shaders[MESA_SHADER_VERTEX]) {
1558 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
1559 }
1560
1561 for (int i = 1; i < shader_count; ++i) {
1562 nir_remove_dead_variables(ordered_shaders[i],
1563 nir_var_shader_out);
1564 nir_remove_dead_variables(ordered_shaders[i - 1],
1565 nir_var_shader_in);
1566
1567 bool progress = nir_remove_unused_varyings(ordered_shaders[i],
1568 ordered_shaders[i - 1]);
1569
1570 if (progress) {
1571 nir_lower_global_vars_to_local(ordered_shaders[i]);
1572 radv_optimize_nir(ordered_shaders[i]);
1573 nir_lower_global_vars_to_local(ordered_shaders[i - 1]);
1574 radv_optimize_nir(ordered_shaders[i - 1]);
1575 }
1576 }
1577 }
1578
1579 static
1580 void radv_create_shaders(struct radv_pipeline *pipeline,
1581 struct radv_device *device,
1582 struct radv_pipeline_cache *cache,
1583 struct ac_shader_variant_key *keys,
1584 const VkPipelineShaderStageCreateInfo **pStages)
1585 {
1586 struct radv_shader_module fs_m = {0};
1587 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
1588 nir_shader *nir[MESA_SHADER_STAGES] = {0};
1589 void *codes[MESA_SHADER_STAGES] = {0};
1590 unsigned code_sizes[MESA_SHADER_STAGES] = {0};
1591 unsigned char hash[20], gs_copy_hash[20];
1592
1593 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
1594 if (pStages[i]) {
1595 modules[i] = radv_shader_module_from_handle(pStages[i]->module);
1596 if (modules[i]->nir)
1597 _mesa_sha1_compute(modules[i]->nir->info.name,
1598 strlen(modules[i]->nir->info.name),
1599 modules[i]->sha1);
1600 }
1601 }
1602
1603 radv_hash_shaders(hash, pStages, pipeline->layout, keys, get_hash_flags(device));
1604 memcpy(gs_copy_hash, hash, 20);
1605 gs_copy_hash[0] ^= 1;
1606
1607 if (modules[MESA_SHADER_GEOMETRY]) {
1608 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
1609 radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants);
1610 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
1611 }
1612
1613 if (radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders) &&
1614 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
1615 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
1616 if (pipeline->shaders[i])
1617 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
1618 }
1619 return;
1620 }
1621
1622 if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
1623 nir_builder fs_b;
1624 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
1625 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
1626 fs_m.nir = fs_b.shader;
1627 modules[MESA_SHADER_FRAGMENT] = &fs_m;
1628 }
1629
1630 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
1631 const VkPipelineShaderStageCreateInfo *stage = pStages[i];
1632
1633 if (!modules[i])
1634 continue;
1635
1636 nir[i] = radv_shader_compile_to_nir(device, modules[i],
1637 stage ? stage->pName : "main", i,
1638 stage ? stage->pSpecializationInfo : NULL);
1639 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
1640 }
1641
1642 if (nir[MESA_SHADER_TESS_CTRL]) {
1643 /* TODO: This is no longer used as a key we should refactor this */
1644 if (keys)
1645 keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
1646
1647 nir_lower_tes_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out);
1648 }
1649
1650 radv_link_shaders(pipeline, nir);
1651
1652 if (nir[MESA_SHADER_FRAGMENT]) {
1653 pipeline->shaders[MESA_SHADER_FRAGMENT] =
1654 radv_shader_variant_create(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
1655 pipeline->layout, keys ? keys + MESA_SHADER_FRAGMENT : 0,
1656 &codes[MESA_SHADER_FRAGMENT], &code_sizes[MESA_SHADER_FRAGMENT]);
1657
1658 /* TODO: These are no longer used as keys we should refactor this */
1659 if (keys) {
1660 keys[MESA_SHADER_VERTEX].vs.export_prim_id =
1661 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input;
1662 keys[MESA_SHADER_TESS_EVAL].tes.export_prim_id =
1663 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input;
1664 }
1665 }
1666
1667 if (device->physical_device->rad_info.chip_class >= GFX9 &&
1668 modules[MESA_SHADER_TESS_CTRL] && !pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
1669 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
1670 struct ac_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
1671 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
1672 pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_create(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
1673 pipeline->layout,
1674 &key, &codes[MESA_SHADER_TESS_CTRL],
1675 &code_sizes[MESA_SHADER_TESS_CTRL]);
1676 modules[MESA_SHADER_VERTEX] = NULL;
1677 }
1678
1679 if (device->physical_device->rad_info.chip_class >= GFX9 &&
1680 modules[MESA_SHADER_GEOMETRY] && !pipeline->shaders[MESA_SHADER_GEOMETRY]) {
1681 gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
1682 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
1683 pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_create(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
1684 pipeline->layout,
1685 &keys[pre_stage] , &codes[MESA_SHADER_GEOMETRY],
1686 &code_sizes[MESA_SHADER_GEOMETRY]);
1687 modules[pre_stage] = NULL;
1688 }
1689
1690 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
1691 if(modules[i] && !pipeline->shaders[i]) {
1692 pipeline->shaders[i] = radv_shader_variant_create(device, modules[i], &nir[i], 1,
1693 pipeline->layout,
1694 keys ? keys + i : 0, &codes[i],
1695 &code_sizes[i]);
1696 }
1697 }
1698
1699 if(modules[MESA_SHADER_GEOMETRY]) {
1700 void *gs_copy_code = NULL;
1701 unsigned gs_copy_code_size = 0;
1702 if (!pipeline->gs_copy_shader) {
1703 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
1704 device, nir[MESA_SHADER_GEOMETRY], &gs_copy_code,
1705 &gs_copy_code_size,
1706 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
1707 }
1708
1709 if (pipeline->gs_copy_shader) {
1710 void *code[MESA_SHADER_STAGES] = {0};
1711 unsigned code_size[MESA_SHADER_STAGES] = {0};
1712 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
1713
1714 code[MESA_SHADER_GEOMETRY] = gs_copy_code;
1715 code_size[MESA_SHADER_GEOMETRY] = gs_copy_code_size;
1716 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
1717
1718 radv_pipeline_cache_insert_shaders(device, cache,
1719 gs_copy_hash,
1720 variants,
1721 (const void**)code,
1722 code_size);
1723 }
1724 free(gs_copy_code);
1725 }
1726
1727 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
1728 (const void**)codes, code_sizes);
1729
1730 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
1731 free(codes[i]);
1732 if (modules[i] && !modules[i]->nir && !pipeline->device->trace_bo)
1733 ralloc_free(nir[i]);
1734 }
1735
1736 if (fs_m.nir)
1737 ralloc_free(fs_m.nir);
1738 }
1739
1740 static VkResult
1741 radv_pipeline_init(struct radv_pipeline *pipeline,
1742 struct radv_device *device,
1743 struct radv_pipeline_cache *cache,
1744 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1745 const struct radv_graphics_pipeline_create_info *extra,
1746 const VkAllocationCallbacks *alloc)
1747 {
1748 VkResult result;
1749 bool has_view_index = false;
1750
1751 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1752 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
1753 if (subpass->view_mask)
1754 has_view_index = true;
1755 if (alloc == NULL)
1756 alloc = &device->alloc;
1757
1758 pipeline->device = device;
1759 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
1760
1761 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
1762 radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
1763
1764 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
1765 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
1766 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
1767 pStages[stage] = &pCreateInfo->pStages[i];
1768 }
1769
1770 struct ac_shader_variant_key keys[MESA_SHADER_STAGES];
1771 memset(keys, 0, sizeof(keys));
1772
1773 if (pStages[MESA_SHADER_VERTEX]) {
1774 bool as_es = false;
1775 bool as_ls = false;
1776 if (pStages[MESA_SHADER_TESS_CTRL])
1777 as_ls = true;
1778 else if (pStages[MESA_SHADER_GEOMETRY])
1779 as_es = true;
1780
1781 keys[MESA_SHADER_VERTEX] = radv_compute_vs_key(pCreateInfo, as_es, as_ls);
1782 keys[MESA_SHADER_VERTEX].has_multiview_view_index = has_view_index;
1783 }
1784
1785 if (pStages[MESA_SHADER_TESS_EVAL]) {
1786 keys[MESA_SHADER_TESS_EVAL].has_multiview_view_index = has_view_index;
1787 if (pStages[MESA_SHADER_GEOMETRY])
1788 keys[MESA_SHADER_TESS_EVAL].tes.as_es = true;
1789 }
1790
1791 if (pCreateInfo->pTessellationState)
1792 keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = pCreateInfo->pTessellationState->patchControlPoints;
1793
1794 if (pStages[MESA_SHADER_GEOMETRY]) {
1795 keys[MESA_SHADER_GEOMETRY] = radv_compute_vs_key(pCreateInfo, false, false);
1796 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index = has_view_index;
1797 }
1798
1799 if (pCreateInfo->pMultisampleState &&
1800 pCreateInfo->pMultisampleState->rasterizationSamples > 1)
1801 keys[MESA_SHADER_FRAGMENT].fs.multisample = true;
1802
1803 keys[MESA_SHADER_FRAGMENT].fs.col_format = pipeline->graphics.blend.spi_shader_col_format;
1804 if (pipeline->device->physical_device->rad_info.chip_class < VI)
1805 radv_pipeline_compute_get_int_clamp(pCreateInfo, &keys[MESA_SHADER_FRAGMENT].fs.is_int8, &keys[MESA_SHADER_FRAGMENT].fs.is_int10);
1806
1807 radv_create_shaders(pipeline, device, cache, keys, pStages);
1808
1809 radv_pipeline_init_depth_stencil_state(pipeline, pCreateInfo, extra);
1810 radv_pipeline_init_raster_state(pipeline, pCreateInfo);
1811 radv_pipeline_init_multisample_state(pipeline, pCreateInfo);
1812 pipeline->graphics.prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
1813 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
1814
1815 if (radv_pipeline_has_gs(pipeline)) {
1816 pipeline->graphics.gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
1817 pipeline->graphics.can_use_guardband = pipeline->graphics.gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1818 } else {
1819 pipeline->graphics.gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
1820 }
1821 if (extra && extra->use_rectlist) {
1822 pipeline->graphics.prim = V_008958_DI_PT_RECTLIST;
1823 pipeline->graphics.gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1824 pipeline->graphics.can_use_guardband = true;
1825 }
1826 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
1827 /* prim vertex count will need TESS changes */
1828 pipeline->graphics.prim_vertex_count = prim_size_table[pipeline->graphics.prim];
1829
1830 /* Ensure that some export memory is always allocated, for two reasons:
1831 *
1832 * 1) Correctness: The hardware ignores the EXEC mask if no export
1833 * memory is allocated, so KILL and alpha test do not work correctly
1834 * without this.
1835 * 2) Performance: Every shader needs at least a NULL export, even when
1836 * it writes no color/depth output. The NULL export instruction
1837 * stalls without this setting.
1838 *
1839 * Don't add this to CB_SHADER_MASK.
1840 */
1841 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
1842 if (!pipeline->graphics.blend.spi_shader_col_format) {
1843 if (!ps->info.fs.writes_z &&
1844 !ps->info.fs.writes_stencil &&
1845 !ps->info.fs.writes_sample_mask)
1846 pipeline->graphics.blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1847 }
1848
1849 unsigned z_order;
1850 pipeline->graphics.db_shader_control = 0;
1851 if (ps->info.fs.early_fragment_test || !ps->info.fs.writes_memory)
1852 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
1853 else
1854 z_order = V_02880C_LATE_Z;
1855
1856 pipeline->graphics.db_shader_control =
1857 S_02880C_Z_EXPORT_ENABLE(ps->info.fs.writes_z) |
1858 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.fs.writes_stencil) |
1859 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
1860 S_02880C_MASK_EXPORT_ENABLE(ps->info.fs.writes_sample_mask) |
1861 S_02880C_Z_ORDER(z_order) |
1862 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
1863 S_02880C_EXEC_ON_HIER_FAIL(ps->info.fs.writes_memory) |
1864 S_02880C_EXEC_ON_NOOP(ps->info.fs.writes_memory);
1865
1866 if (pipeline->device->physical_device->has_rbplus)
1867 pipeline->graphics.db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1868
1869 pipeline->graphics.shader_z_format =
1870 ps->info.fs.writes_sample_mask ? V_028710_SPI_SHADER_32_ABGR :
1871 ps->info.fs.writes_stencil ? V_028710_SPI_SHADER_32_GR :
1872 ps->info.fs.writes_z ? V_028710_SPI_SHADER_32_R :
1873 V_028710_SPI_SHADER_ZERO;
1874
1875 calculate_vgt_gs_mode(pipeline);
1876 calculate_pa_cl_vs_out_cntl(pipeline);
1877 calculate_ps_inputs(pipeline);
1878
1879 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
1880 if (pipeline->shaders[i]) {
1881 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
1882 }
1883 }
1884
1885 uint32_t stages = 0;
1886 if (radv_pipeline_has_tess(pipeline)) {
1887 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
1888 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
1889
1890 if (radv_pipeline_has_gs(pipeline))
1891 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
1892 S_028B54_GS_EN(1) |
1893 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1894 else
1895 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
1896
1897 } else if (radv_pipeline_has_gs(pipeline))
1898 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
1899 S_028B54_GS_EN(1) |
1900 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1901
1902 if (device->physical_device->rad_info.chip_class >= GFX9)
1903 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
1904
1905 pipeline->graphics.vgt_shader_stages_en = stages;
1906
1907 if (radv_pipeline_has_gs(pipeline))
1908 calculate_gs_ring_sizes(pipeline);
1909
1910 if (radv_pipeline_has_tess(pipeline)) {
1911 if (pipeline->graphics.prim == V_008958_DI_PT_PATCH) {
1912 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
1913 pipeline->graphics.prim_vertex_count.incr = 1;
1914 }
1915 calculate_tess_state(pipeline, pCreateInfo);
1916 }
1917
1918 if (radv_pipeline_has_tess(pipeline))
1919 pipeline->graphics.primgroup_size = pipeline->graphics.tess.num_patches;
1920 else if (radv_pipeline_has_gs(pipeline))
1921 pipeline->graphics.primgroup_size = 64;
1922 else
1923 pipeline->graphics.primgroup_size = 128; /* recommended without a GS */
1924
1925 pipeline->graphics.partial_es_wave = false;
1926 if (pipeline->device->has_distributed_tess) {
1927 if (radv_pipeline_has_gs(pipeline)) {
1928 if (device->physical_device->rad_info.chip_class <= VI)
1929 pipeline->graphics.partial_es_wave = true;
1930 }
1931 }
1932 /* GS requirement. */
1933 if (SI_GS_PER_ES / pipeline->graphics.primgroup_size >= pipeline->device->gs_table_depth - 3)
1934 pipeline->graphics.partial_es_wave = true;
1935
1936 pipeline->graphics.wd_switch_on_eop = false;
1937 if (device->physical_device->rad_info.chip_class >= CIK) {
1938 unsigned prim = pipeline->graphics.prim;
1939 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
1940 * 4 shader engines. Set 1 to pass the assertion below.
1941 * The other cases are hardware requirements. */
1942 if (device->physical_device->rad_info.max_se < 4 ||
1943 prim == V_008958_DI_PT_POLYGON ||
1944 prim == V_008958_DI_PT_LINELOOP ||
1945 prim == V_008958_DI_PT_TRIFAN ||
1946 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
1947 (pipeline->graphics.prim_restart_enable &&
1948 (device->physical_device->rad_info.family < CHIP_POLARIS10 ||
1949 (prim != V_008958_DI_PT_POINTLIST &&
1950 prim != V_008958_DI_PT_LINESTRIP &&
1951 prim != V_008958_DI_PT_TRISTRIP))))
1952 pipeline->graphics.wd_switch_on_eop = true;
1953 }
1954
1955 pipeline->graphics.ia_switch_on_eoi = false;
1956 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input)
1957 pipeline->graphics.ia_switch_on_eoi = true;
1958 if (radv_pipeline_has_gs(pipeline) &&
1959 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.uses_prim_id)
1960 pipeline->graphics.ia_switch_on_eoi = true;
1961 if (radv_pipeline_has_tess(pipeline)) {
1962 /* SWITCH_ON_EOI must be set if PrimID is used. */
1963 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.uses_prim_id ||
1964 pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.uses_prim_id)
1965 pipeline->graphics.ia_switch_on_eoi = true;
1966 }
1967
1968 pipeline->graphics.partial_vs_wave = false;
1969 if (radv_pipeline_has_tess(pipeline)) {
1970 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
1971 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
1972 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
1973 device->physical_device->rad_info.family == CHIP_BONAIRE) &&
1974 radv_pipeline_has_gs(pipeline))
1975 pipeline->graphics.partial_vs_wave = true;
1976 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
1977 if (device->has_distributed_tess) {
1978 if (radv_pipeline_has_gs(pipeline)) {
1979 if (device->physical_device->rad_info.family == CHIP_TONGA ||
1980 device->physical_device->rad_info.family == CHIP_FIJI ||
1981 device->physical_device->rad_info.family == CHIP_POLARIS10 ||
1982 device->physical_device->rad_info.family == CHIP_POLARIS11 ||
1983 device->physical_device->rad_info.family == CHIP_POLARIS12)
1984 pipeline->graphics.partial_vs_wave = true;
1985 } else {
1986 pipeline->graphics.partial_vs_wave = true;
1987 }
1988 }
1989 }
1990
1991 pipeline->graphics.base_ia_multi_vgt_param =
1992 S_028AA8_PRIMGROUP_SIZE(pipeline->graphics.primgroup_size - 1) |
1993 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
1994 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == VI ? 2 : 0) |
1995 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
1996 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
1997
1998 const VkPipelineVertexInputStateCreateInfo *vi_info =
1999 pCreateInfo->pVertexInputState;
2000 struct radv_vertex_elements_info *velems = &pipeline->vertex_elements;
2001
2002 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
2003 const VkVertexInputAttributeDescription *desc =
2004 &vi_info->pVertexAttributeDescriptions[i];
2005 unsigned loc = desc->location;
2006 const struct vk_format_description *format_desc;
2007 int first_non_void;
2008 uint32_t num_format, data_format;
2009 format_desc = vk_format_description(desc->format);
2010 first_non_void = vk_format_get_first_non_void_channel(desc->format);
2011
2012 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
2013 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
2014
2015 velems->rsrc_word3[loc] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc->swizzle[0])) |
2016 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc->swizzle[1])) |
2017 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc->swizzle[2])) |
2018 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc->swizzle[3])) |
2019 S_008F0C_NUM_FORMAT(num_format) |
2020 S_008F0C_DATA_FORMAT(data_format);
2021 velems->format_size[loc] = format_desc->block.bits / 8;
2022 velems->offset[loc] = desc->offset;
2023 velems->binding[loc] = desc->binding;
2024 velems->count = MAX2(velems->count, loc + 1);
2025 }
2026
2027 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
2028 const VkVertexInputBindingDescription *desc =
2029 &vi_info->pVertexBindingDescriptions[i];
2030
2031 pipeline->binding_stride[desc->binding] = desc->stride;
2032 }
2033
2034 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
2035 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2036 if (loc->sgpr_idx != -1) {
2037 pipeline->graphics.vtx_base_sgpr = radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
2038 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
2039 if (radv_get_vertex_shader(pipeline)->info.info.vs.needs_draw_id)
2040 pipeline->graphics.vtx_emit_num = 3;
2041 else
2042 pipeline->graphics.vtx_emit_num = 2;
2043 }
2044
2045 pipeline->graphics.vtx_reuse_depth = 30;
2046 if (radv_pipeline_has_tess(pipeline) &&
2047 pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
2048 pipeline->graphics.vtx_reuse_depth = 14;
2049 }
2050
2051 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
2052 radv_dump_pipeline_stats(device, pipeline);
2053 }
2054
2055 result = radv_pipeline_scratch_init(device, pipeline);
2056 return result;
2057 }
2058
2059 VkResult
2060 radv_graphics_pipeline_create(
2061 VkDevice _device,
2062 VkPipelineCache _cache,
2063 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2064 const struct radv_graphics_pipeline_create_info *extra,
2065 const VkAllocationCallbacks *pAllocator,
2066 VkPipeline *pPipeline)
2067 {
2068 RADV_FROM_HANDLE(radv_device, device, _device);
2069 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
2070 struct radv_pipeline *pipeline;
2071 VkResult result;
2072
2073 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
2074 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2075 if (pipeline == NULL)
2076 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2077
2078 memset(pipeline, 0, sizeof(*pipeline));
2079 result = radv_pipeline_init(pipeline, device, cache,
2080 pCreateInfo, extra, pAllocator);
2081 if (result != VK_SUCCESS) {
2082 radv_pipeline_destroy(device, pipeline, pAllocator);
2083 return result;
2084 }
2085
2086 *pPipeline = radv_pipeline_to_handle(pipeline);
2087
2088 return VK_SUCCESS;
2089 }
2090
2091 VkResult radv_CreateGraphicsPipelines(
2092 VkDevice _device,
2093 VkPipelineCache pipelineCache,
2094 uint32_t count,
2095 const VkGraphicsPipelineCreateInfo* pCreateInfos,
2096 const VkAllocationCallbacks* pAllocator,
2097 VkPipeline* pPipelines)
2098 {
2099 VkResult result = VK_SUCCESS;
2100 unsigned i = 0;
2101
2102 for (; i < count; i++) {
2103 VkResult r;
2104 r = radv_graphics_pipeline_create(_device,
2105 pipelineCache,
2106 &pCreateInfos[i],
2107 NULL, pAllocator, &pPipelines[i]);
2108 if (r != VK_SUCCESS) {
2109 result = r;
2110 pPipelines[i] = VK_NULL_HANDLE;
2111 }
2112 }
2113
2114 return result;
2115 }
2116
2117 static VkResult radv_compute_pipeline_create(
2118 VkDevice _device,
2119 VkPipelineCache _cache,
2120 const VkComputePipelineCreateInfo* pCreateInfo,
2121 const VkAllocationCallbacks* pAllocator,
2122 VkPipeline* pPipeline)
2123 {
2124 RADV_FROM_HANDLE(radv_device, device, _device);
2125 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
2126 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
2127 struct radv_pipeline *pipeline;
2128 VkResult result;
2129
2130 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
2131 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2132 if (pipeline == NULL)
2133 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2134
2135 memset(pipeline, 0, sizeof(*pipeline));
2136 pipeline->device = device;
2137 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
2138
2139 pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
2140 radv_create_shaders(pipeline, device, cache, NULL, pStages);
2141
2142
2143 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
2144 result = radv_pipeline_scratch_init(device, pipeline);
2145 if (result != VK_SUCCESS) {
2146 radv_pipeline_destroy(device, pipeline, pAllocator);
2147 return result;
2148 }
2149
2150 *pPipeline = radv_pipeline_to_handle(pipeline);
2151
2152 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
2153 radv_dump_pipeline_stats(device, pipeline);
2154 }
2155 return VK_SUCCESS;
2156 }
2157 VkResult radv_CreateComputePipelines(
2158 VkDevice _device,
2159 VkPipelineCache pipelineCache,
2160 uint32_t count,
2161 const VkComputePipelineCreateInfo* pCreateInfos,
2162 const VkAllocationCallbacks* pAllocator,
2163 VkPipeline* pPipelines)
2164 {
2165 VkResult result = VK_SUCCESS;
2166
2167 unsigned i = 0;
2168 for (; i < count; i++) {
2169 VkResult r;
2170 r = radv_compute_pipeline_create(_device, pipelineCache,
2171 &pCreateInfos[i],
2172 pAllocator, &pPipelines[i]);
2173 if (r != VK_SUCCESS) {
2174 result = r;
2175 pPipelines[i] = VK_NULL_HANDLE;
2176 }
2177 }
2178
2179 return result;
2180 }