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radv: disassemble SPIR-V binaries with RADV_DEBUG=spirv
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "nir/nir.h"
33 #include "nir/nir_builder.h"
34 #include "spirv/nir_spirv.h"
35
36 #include <llvm-c/Core.h>
37 #include <llvm-c/TargetMachine.h>
38
39 #include "sid.h"
40 #include "gfx9d.h"
41 #include "r600d_common.h"
42 #include "ac_binary.h"
43 #include "ac_llvm_util.h"
44 #include "ac_nir_to_llvm.h"
45 #include "vk_format.h"
46 #include "util/debug.h"
47 #include "ac_exp_param.h"
48
49 void radv_shader_variant_destroy(struct radv_device *device,
50 struct radv_shader_variant *variant);
51
52 static const struct nir_shader_compiler_options nir_options = {
53 .vertex_id_zero_based = true,
54 .lower_scmp = true,
55 .lower_flrp32 = true,
56 .lower_fsat = true,
57 .lower_fdiv = true,
58 .lower_sub = true,
59 .lower_pack_snorm_2x16 = true,
60 .lower_pack_snorm_4x8 = true,
61 .lower_pack_unorm_2x16 = true,
62 .lower_pack_unorm_4x8 = true,
63 .lower_unpack_snorm_2x16 = true,
64 .lower_unpack_snorm_4x8 = true,
65 .lower_unpack_unorm_2x16 = true,
66 .lower_unpack_unorm_4x8 = true,
67 .lower_extract_byte = true,
68 .lower_extract_word = true,
69 .max_unroll_iterations = 32
70 };
71
72 VkResult radv_CreateShaderModule(
73 VkDevice _device,
74 const VkShaderModuleCreateInfo* pCreateInfo,
75 const VkAllocationCallbacks* pAllocator,
76 VkShaderModule* pShaderModule)
77 {
78 RADV_FROM_HANDLE(radv_device, device, _device);
79 struct radv_shader_module *module;
80
81 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
82 assert(pCreateInfo->flags == 0);
83
84 module = vk_alloc2(&device->alloc, pAllocator,
85 sizeof(*module) + pCreateInfo->codeSize, 8,
86 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
87 if (module == NULL)
88 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
89
90 module->nir = NULL;
91 module->size = pCreateInfo->codeSize;
92 memcpy(module->data, pCreateInfo->pCode, module->size);
93
94 _mesa_sha1_compute(module->data, module->size, module->sha1);
95
96 *pShaderModule = radv_shader_module_to_handle(module);
97
98 return VK_SUCCESS;
99 }
100
101 void radv_DestroyShaderModule(
102 VkDevice _device,
103 VkShaderModule _module,
104 const VkAllocationCallbacks* pAllocator)
105 {
106 RADV_FROM_HANDLE(radv_device, device, _device);
107 RADV_FROM_HANDLE(radv_shader_module, module, _module);
108
109 if (!module)
110 return;
111
112 vk_free2(&device->alloc, pAllocator, module);
113 }
114
115
116 static void
117 radv_pipeline_destroy(struct radv_device *device,
118 struct radv_pipeline *pipeline,
119 const VkAllocationCallbacks* allocator)
120 {
121 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
122 if (pipeline->shaders[i])
123 radv_shader_variant_destroy(device, pipeline->shaders[i]);
124
125 if (pipeline->gs_copy_shader)
126 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
127
128 vk_free2(&device->alloc, allocator, pipeline);
129 }
130
131 void radv_DestroyPipeline(
132 VkDevice _device,
133 VkPipeline _pipeline,
134 const VkAllocationCallbacks* pAllocator)
135 {
136 RADV_FROM_HANDLE(radv_device, device, _device);
137 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
138
139 if (!_pipeline)
140 return;
141
142 radv_pipeline_destroy(device, pipeline, pAllocator);
143 }
144
145
146 static void
147 radv_optimize_nir(struct nir_shader *shader)
148 {
149 bool progress;
150
151 do {
152 progress = false;
153
154 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
155 NIR_PASS_V(shader, nir_lower_64bit_pack);
156 NIR_PASS_V(shader, nir_lower_alu_to_scalar);
157 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
158
159 NIR_PASS(progress, shader, nir_copy_prop);
160 NIR_PASS(progress, shader, nir_opt_remove_phis);
161 NIR_PASS(progress, shader, nir_opt_dce);
162 if (nir_opt_trivial_continues(shader)) {
163 progress = true;
164 NIR_PASS(progress, shader, nir_copy_prop);
165 NIR_PASS(progress, shader, nir_opt_dce);
166 }
167 NIR_PASS(progress, shader, nir_opt_if);
168 NIR_PASS(progress, shader, nir_opt_dead_cf);
169 NIR_PASS(progress, shader, nir_opt_cse);
170 NIR_PASS(progress, shader, nir_opt_peephole_select, 8);
171 NIR_PASS(progress, shader, nir_opt_algebraic);
172 NIR_PASS(progress, shader, nir_opt_constant_folding);
173 NIR_PASS(progress, shader, nir_opt_undef);
174 NIR_PASS(progress, shader, nir_opt_conditional_discard);
175 if (shader->options->max_unroll_iterations) {
176 NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
177 }
178 } while (progress);
179 }
180
181 static nir_shader *
182 radv_shader_compile_to_nir(struct radv_device *device,
183 struct radv_shader_module *module,
184 const char *entrypoint_name,
185 gl_shader_stage stage,
186 const VkSpecializationInfo *spec_info,
187 bool dump)
188 {
189 if (strcmp(entrypoint_name, "main") != 0) {
190 radv_finishme("Multiple shaders per module not really supported");
191 }
192
193 nir_shader *nir;
194 nir_function *entry_point;
195 if (module->nir) {
196 /* Some things such as our meta clear/blit code will give us a NIR
197 * shader directly. In that case, we just ignore the SPIR-V entirely
198 * and just use the NIR shader */
199 nir = module->nir;
200 nir->options = &nir_options;
201 nir_validate_shader(nir);
202
203 assert(exec_list_length(&nir->functions) == 1);
204 struct exec_node *node = exec_list_get_head(&nir->functions);
205 entry_point = exec_node_data(nir_function, node, node);
206 } else {
207 uint32_t *spirv = (uint32_t *) module->data;
208 assert(module->size % 4 == 0);
209
210 if (device->debug_flags & RADV_DEBUG_DUMP_SPIRV)
211 radv_print_spirv(module, stderr);
212
213 uint32_t num_spec_entries = 0;
214 struct nir_spirv_specialization *spec_entries = NULL;
215 if (spec_info && spec_info->mapEntryCount > 0) {
216 num_spec_entries = spec_info->mapEntryCount;
217 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
218 for (uint32_t i = 0; i < num_spec_entries; i++) {
219 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
220 const void *data = spec_info->pData + entry.offset;
221 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
222
223 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
224 if (spec_info->dataSize == 8)
225 spec_entries[i].data64 = *(const uint64_t *)data;
226 else
227 spec_entries[i].data32 = *(const uint32_t *)data;
228 }
229 }
230 const struct nir_spirv_supported_extensions supported_ext = {
231 .draw_parameters = true,
232 .float64 = true,
233 .image_read_without_format = true,
234 .image_write_without_format = true,
235 .tessellation = true,
236 .int64 = true,
237 .multiview = true,
238 .variable_pointers = true,
239 };
240 entry_point = spirv_to_nir(spirv, module->size / 4,
241 spec_entries, num_spec_entries,
242 stage, entrypoint_name, &supported_ext, &nir_options);
243 nir = entry_point->shader;
244 assert(nir->stage == stage);
245 nir_validate_shader(nir);
246
247 free(spec_entries);
248
249 /* We have to lower away local constant initializers right before we
250 * inline functions. That way they get properly initialized at the top
251 * of the function and not at the top of its caller.
252 */
253 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_local);
254 NIR_PASS_V(nir, nir_lower_returns);
255 NIR_PASS_V(nir, nir_inline_functions);
256
257 /* Pick off the single entrypoint that we want */
258 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
259 if (func != entry_point)
260 exec_node_remove(&func->node);
261 }
262 assert(exec_list_length(&nir->functions) == 1);
263 entry_point->name = ralloc_strdup(entry_point, "main");
264
265 NIR_PASS_V(nir, nir_remove_dead_variables,
266 nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
267
268 /* Now that we've deleted all but the main function, we can go ahead and
269 * lower the rest of the constant initializers.
270 */
271 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
272 NIR_PASS_V(nir, nir_lower_system_values);
273 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
274 }
275
276 /* Vulkan uses the separate-shader linking model */
277 nir->info.separate_shader = true;
278
279 nir_shader_gather_info(nir, entry_point->impl);
280
281 nir_variable_mode indirect_mask = 0;
282 indirect_mask |= nir_var_shader_in;
283 indirect_mask |= nir_var_local;
284
285 nir_lower_indirect_derefs(nir, indirect_mask);
286
287 static const nir_lower_tex_options tex_options = {
288 .lower_txp = ~0,
289 };
290
291 nir_lower_tex(nir, &tex_options);
292
293 nir_lower_vars_to_ssa(nir);
294 nir_lower_var_copies(nir);
295 nir_lower_global_vars_to_local(nir);
296 nir_remove_dead_variables(nir, nir_var_local);
297 radv_optimize_nir(nir);
298
299 if (dump)
300 nir_print_shader(nir, stderr);
301
302 return nir;
303 }
304
305 static const char *radv_get_shader_name(struct radv_shader_variant *var,
306 gl_shader_stage stage)
307 {
308 switch (stage) {
309 case MESA_SHADER_VERTEX: return var->info.vs.as_ls ? "Vertex Shader as LS" : var->info.vs.as_es ? "Vertex Shader as ES" : "Vertex Shader as VS";
310 case MESA_SHADER_GEOMETRY: return "Geometry Shader";
311 case MESA_SHADER_FRAGMENT: return "Pixel Shader";
312 case MESA_SHADER_COMPUTE: return "Compute Shader";
313 case MESA_SHADER_TESS_CTRL: return "Tessellation Control Shader";
314 case MESA_SHADER_TESS_EVAL: return var->info.tes.as_es ? "Tessellation Evaluation Shader as ES" : "Tessellation Evaluation Shader as VS";
315 default:
316 return "Unknown shader";
317 };
318
319 }
320 static void radv_dump_pipeline_stats(struct radv_device *device, struct radv_pipeline *pipeline)
321 {
322 unsigned lds_increment = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
323 struct radv_shader_variant *var;
324 struct ac_shader_config *conf;
325 int i;
326 FILE *file = stderr;
327 unsigned max_simd_waves;
328 unsigned lds_per_wave = 0;
329
330 switch (device->physical_device->rad_info.family) {
331 /* These always have 8 waves: */
332 case CHIP_POLARIS10:
333 case CHIP_POLARIS11:
334 case CHIP_POLARIS12:
335 max_simd_waves = 8;
336 break;
337 default:
338 max_simd_waves = 10;
339 }
340
341 for (i = 0; i < MESA_SHADER_STAGES; i++) {
342 if (!pipeline->shaders[i])
343 continue;
344 var = pipeline->shaders[i];
345
346 conf = &var->config;
347
348 if (i == MESA_SHADER_FRAGMENT) {
349 lds_per_wave = conf->lds_size * lds_increment +
350 align(var->info.fs.num_interp * 48, lds_increment);
351 }
352
353 if (conf->num_sgprs) {
354 if (device->physical_device->rad_info.chip_class >= VI)
355 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
356 else
357 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
358 }
359
360 if (conf->num_vgprs)
361 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
362
363 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
364 * that PS can use.
365 */
366 if (lds_per_wave)
367 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
368
369 fprintf(file, "\n%s:\n",
370 radv_get_shader_name(var, i));
371 if (i == MESA_SHADER_FRAGMENT) {
372 fprintf(file, "*** SHADER CONFIG ***\n"
373 "SPI_PS_INPUT_ADDR = 0x%04x\n"
374 "SPI_PS_INPUT_ENA = 0x%04x\n",
375 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
376 }
377 fprintf(file, "*** SHADER STATS ***\n"
378 "SGPRS: %d\n"
379 "VGPRS: %d\n"
380 "Spilled SGPRs: %d\n"
381 "Spilled VGPRs: %d\n"
382 "Code Size: %d bytes\n"
383 "LDS: %d blocks\n"
384 "Scratch: %d bytes per wave\n"
385 "Max Waves: %d\n"
386 "********************\n\n\n",
387 conf->num_sgprs, conf->num_vgprs,
388 conf->spilled_sgprs, conf->spilled_vgprs, var->code_size,
389 conf->lds_size, conf->scratch_bytes_per_wave,
390 max_simd_waves);
391 }
392 }
393
394 void radv_shader_variant_destroy(struct radv_device *device,
395 struct radv_shader_variant *variant)
396 {
397 if (!p_atomic_dec_zero(&variant->ref_count))
398 return;
399
400 mtx_lock(&device->shader_slab_mutex);
401 list_del(&variant->slab_list);
402 mtx_unlock(&device->shader_slab_mutex);
403
404 free(variant);
405 }
406
407 static void radv_fill_shader_variant(struct radv_device *device,
408 struct radv_shader_variant *variant,
409 struct ac_shader_binary *binary,
410 gl_shader_stage stage)
411 {
412 bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0;
413 unsigned vgpr_comp_cnt = 0;
414
415 if (scratch_enabled && !device->llvm_supports_spill)
416 radv_finishme("shader scratch support only available with LLVM 4.0");
417
418 variant->code_size = binary->code_size;
419 variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
420 S_00B12C_SCRATCH_EN(scratch_enabled);
421
422 switch (stage) {
423 case MESA_SHADER_TESS_EVAL:
424 vgpr_comp_cnt = 3;
425 /* fallthrough */
426 case MESA_SHADER_TESS_CTRL:
427 variant->rsrc2 |= S_00B42C_OC_LDS_EN(1);
428 break;
429 case MESA_SHADER_VERTEX:
430 case MESA_SHADER_GEOMETRY:
431 vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
432 break;
433 case MESA_SHADER_FRAGMENT:
434 break;
435 case MESA_SHADER_COMPUTE:
436 variant->rsrc2 |=
437 S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) |
438 S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) |
439 S_00B84C_TG_SIZE_EN(1) |
440 S_00B84C_LDS_SIZE(variant->config.lds_size);
441 break;
442 default:
443 unreachable("unsupported shader type");
444 break;
445 }
446
447 variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
448 S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) |
449 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
450 S_00B848_DX10_CLAMP(1) |
451 S_00B848_FLOAT_MODE(variant->config.float_mode);
452
453 void *ptr = radv_alloc_shader_memory(device, variant);
454 memcpy(ptr, binary->code, binary->code_size);
455 }
456
457 static struct radv_shader_variant *radv_shader_variant_create(struct radv_device *device,
458 struct nir_shader *shader,
459 struct radv_pipeline_layout *layout,
460 const struct ac_shader_variant_key *key,
461 void** code_out,
462 unsigned *code_size_out,
463 bool dump)
464 {
465 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
466 enum radeon_family chip_family = device->physical_device->rad_info.family;
467 LLVMTargetMachineRef tm;
468 if (!variant)
469 return NULL;
470
471 struct ac_nir_compiler_options options = {0};
472 options.layout = layout;
473 if (key)
474 options.key = *key;
475
476 struct ac_shader_binary binary;
477 enum ac_target_machine_options tm_options = 0;
478 options.unsafe_math = !!(device->debug_flags & RADV_DEBUG_UNSAFE_MATH);
479 options.family = chip_family;
480 options.chip_class = device->physical_device->rad_info.chip_class;
481 options.supports_spill = device->llvm_supports_spill;
482 if (options.supports_spill)
483 tm_options |= AC_TM_SUPPORTS_SPILL;
484 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
485 tm_options |= AC_TM_SISCHED;
486 tm = ac_create_target_machine(chip_family, tm_options);
487 ac_compile_nir_shader(tm, &binary, &variant->config,
488 &variant->info, shader, &options, dump);
489 LLVMDisposeTargetMachine(tm);
490
491 radv_fill_shader_variant(device, variant, &binary, shader->stage);
492
493 if (code_out) {
494 *code_out = binary.code;
495 *code_size_out = binary.code_size;
496 } else
497 free(binary.code);
498 free(binary.config);
499 free(binary.rodata);
500 free(binary.global_symbol_offsets);
501 free(binary.relocs);
502 free(binary.disasm_string);
503 variant->ref_count = 1;
504 return variant;
505 }
506
507 static struct radv_shader_variant *
508 radv_pipeline_create_gs_copy_shader(struct radv_pipeline *pipeline,
509 struct nir_shader *nir,
510 void** code_out,
511 unsigned *code_size_out,
512 bool dump_shader,
513 bool multiview)
514 {
515 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
516 enum radeon_family chip_family = pipeline->device->physical_device->rad_info.family;
517 LLVMTargetMachineRef tm;
518 if (!variant)
519 return NULL;
520
521 struct ac_nir_compiler_options options = {0};
522 struct ac_shader_binary binary;
523 enum ac_target_machine_options tm_options = 0;
524 options.family = chip_family;
525 options.chip_class = pipeline->device->physical_device->rad_info.chip_class;
526 options.key.has_multiview_view_index = multiview;
527 if (options.supports_spill)
528 tm_options |= AC_TM_SUPPORTS_SPILL;
529 if (pipeline->device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
530 tm_options |= AC_TM_SISCHED;
531 tm = ac_create_target_machine(chip_family, tm_options);
532 ac_create_gs_copy_shader(tm, nir, &binary, &variant->config, &variant->info, &options, dump_shader);
533 LLVMDisposeTargetMachine(tm);
534
535 radv_fill_shader_variant(pipeline->device, variant, &binary, MESA_SHADER_VERTEX);
536
537 if (code_out) {
538 *code_out = binary.code;
539 *code_size_out = binary.code_size;
540 } else
541 free(binary.code);
542 free(binary.config);
543 free(binary.rodata);
544 free(binary.global_symbol_offsets);
545 free(binary.relocs);
546 free(binary.disasm_string);
547 variant->ref_count = 1;
548 return variant;
549 }
550
551 static struct radv_shader_variant *
552 radv_pipeline_compile(struct radv_pipeline *pipeline,
553 struct radv_pipeline_cache *cache,
554 struct radv_shader_module *module,
555 const char *entrypoint,
556 gl_shader_stage stage,
557 const VkSpecializationInfo *spec_info,
558 struct radv_pipeline_layout *layout,
559 const struct ac_shader_variant_key *key)
560 {
561 unsigned char sha1[20];
562 unsigned char gs_copy_sha1[20];
563 struct radv_shader_variant *variant;
564 nir_shader *nir;
565 void *code = NULL;
566 unsigned code_size = 0;
567 bool dump = (pipeline->device->debug_flags & RADV_DEBUG_DUMP_SHADERS);
568
569 if (module->nir)
570 _mesa_sha1_compute(module->nir->info.name,
571 strlen(module->nir->info.name),
572 module->sha1);
573
574 radv_hash_shader(sha1, module, entrypoint, spec_info, layout, key, 0);
575 if (stage == MESA_SHADER_GEOMETRY)
576 radv_hash_shader(gs_copy_sha1, module, entrypoint, spec_info,
577 layout, key, 1);
578
579 variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
580 cache,
581 sha1);
582
583 if (stage == MESA_SHADER_GEOMETRY) {
584 pipeline->gs_copy_shader =
585 radv_create_shader_variant_from_pipeline_cache(
586 pipeline->device,
587 cache,
588 gs_copy_sha1);
589 }
590
591 if (variant &&
592 (stage != MESA_SHADER_GEOMETRY || pipeline->gs_copy_shader))
593 return variant;
594
595 nir = radv_shader_compile_to_nir(pipeline->device,
596 module, entrypoint, stage,
597 spec_info, dump);
598 if (nir == NULL)
599 return NULL;
600
601 if (!variant) {
602 variant = radv_shader_variant_create(pipeline->device, nir,
603 layout, key, &code,
604 &code_size, dump);
605 }
606
607 if (stage == MESA_SHADER_GEOMETRY && !pipeline->gs_copy_shader) {
608 void *gs_copy_code = NULL;
609 unsigned gs_copy_code_size = 0;
610 pipeline->gs_copy_shader = radv_pipeline_create_gs_copy_shader(
611 pipeline, nir, &gs_copy_code, &gs_copy_code_size, dump, key->has_multiview_view_index);
612
613 if (pipeline->gs_copy_shader) {
614 pipeline->gs_copy_shader =
615 radv_pipeline_cache_insert_shader(cache,
616 gs_copy_sha1,
617 pipeline->gs_copy_shader,
618 gs_copy_code,
619 gs_copy_code_size);
620 }
621 }
622 if (!module->nir)
623 ralloc_free(nir);
624
625 if (variant)
626 variant = radv_pipeline_cache_insert_shader(cache, sha1, variant,
627 code, code_size);
628
629 if (code)
630 free(code);
631 return variant;
632 }
633
634 static struct ac_shader_variant_key
635 radv_compute_tes_key(bool as_es, bool export_prim_id)
636 {
637 struct ac_shader_variant_key key;
638 memset(&key, 0, sizeof(key));
639 key.tes.as_es = as_es;
640 /* export prim id only happens when no geom shader */
641 if (!as_es)
642 key.tes.export_prim_id = export_prim_id;
643 return key;
644 }
645
646 static struct ac_shader_variant_key
647 radv_compute_tcs_key(unsigned primitive_mode, unsigned input_vertices)
648 {
649 struct ac_shader_variant_key key;
650 memset(&key, 0, sizeof(key));
651 key.tcs.primitive_mode = primitive_mode;
652 key.tcs.input_vertices = input_vertices;
653 return key;
654 }
655
656 static void
657 radv_tess_pipeline_compile(struct radv_pipeline *pipeline,
658 struct radv_pipeline_cache *cache,
659 struct radv_shader_module *tcs_module,
660 struct radv_shader_module *tes_module,
661 const char *tcs_entrypoint,
662 const char *tes_entrypoint,
663 const VkSpecializationInfo *tcs_spec_info,
664 const VkSpecializationInfo *tes_spec_info,
665 struct radv_pipeline_layout *layout,
666 unsigned input_vertices,
667 bool has_view_index)
668 {
669 unsigned char tcs_sha1[20], tes_sha1[20];
670 struct radv_shader_variant *tes_variant = NULL, *tcs_variant = NULL;
671 nir_shader *tes_nir, *tcs_nir;
672 void *tes_code = NULL, *tcs_code = NULL;
673 unsigned tes_code_size = 0, tcs_code_size = 0;
674 struct ac_shader_variant_key tes_key;
675 struct ac_shader_variant_key tcs_key;
676 bool dump = (pipeline->device->debug_flags & RADV_DEBUG_DUMP_SHADERS);
677
678 tes_key = radv_compute_tes_key(radv_pipeline_has_gs(pipeline),
679 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input);
680 tes_key.has_multiview_view_index = has_view_index;
681 if (tes_module->nir)
682 _mesa_sha1_compute(tes_module->nir->info.name,
683 strlen(tes_module->nir->info.name),
684 tes_module->sha1);
685 radv_hash_shader(tes_sha1, tes_module, tes_entrypoint, tes_spec_info, layout, &tes_key, 0);
686
687 tes_variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
688 cache,
689 tes_sha1);
690
691 if (tes_variant) {
692 tcs_key = radv_compute_tcs_key(tes_variant->info.tes.primitive_mode, input_vertices);
693
694 if (tcs_module->nir)
695 _mesa_sha1_compute(tcs_module->nir->info.name,
696 strlen(tcs_module->nir->info.name),
697 tcs_module->sha1);
698
699 radv_hash_shader(tcs_sha1, tcs_module, tcs_entrypoint, tcs_spec_info, layout, &tcs_key, 0);
700
701 tcs_variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
702 cache,
703 tcs_sha1);
704 }
705
706 if (tcs_variant && tes_variant) {
707 pipeline->shaders[MESA_SHADER_TESS_CTRL] = tcs_variant;
708 pipeline->shaders[MESA_SHADER_TESS_EVAL] = tes_variant;
709 return;
710 }
711
712 tes_nir = radv_shader_compile_to_nir(pipeline->device,
713 tes_module, tes_entrypoint, MESA_SHADER_TESS_EVAL,
714 tes_spec_info, dump);
715 if (tes_nir == NULL)
716 return;
717
718 tcs_nir = radv_shader_compile_to_nir(pipeline->device,
719 tcs_module, tcs_entrypoint, MESA_SHADER_TESS_CTRL,
720 tcs_spec_info, dump);
721 if (tcs_nir == NULL)
722 return;
723
724 nir_lower_tes_patch_vertices(tes_nir,
725 tcs_nir->info.tess.tcs_vertices_out);
726
727 tes_variant = radv_shader_variant_create(pipeline->device, tes_nir,
728 layout, &tes_key, &tes_code,
729 &tes_code_size, dump);
730
731 tcs_key = radv_compute_tcs_key(tes_nir->info.tess.primitive_mode, input_vertices);
732 if (tcs_module->nir)
733 _mesa_sha1_compute(tcs_module->nir->info.name,
734 strlen(tcs_module->nir->info.name),
735 tcs_module->sha1);
736
737 radv_hash_shader(tcs_sha1, tcs_module, tcs_entrypoint, tcs_spec_info, layout, &tcs_key, 0);
738
739 tcs_variant = radv_shader_variant_create(pipeline->device, tcs_nir,
740 layout, &tcs_key, &tcs_code,
741 &tcs_code_size, dump);
742
743 if (!tes_module->nir)
744 ralloc_free(tes_nir);
745
746 if (!tcs_module->nir)
747 ralloc_free(tcs_nir);
748
749 if (tes_variant)
750 tes_variant = radv_pipeline_cache_insert_shader(cache, tes_sha1, tes_variant,
751 tes_code, tes_code_size);
752
753 if (tcs_variant)
754 tcs_variant = radv_pipeline_cache_insert_shader(cache, tcs_sha1, tcs_variant,
755 tcs_code, tcs_code_size);
756
757 if (tes_code)
758 free(tes_code);
759 if (tcs_code)
760 free(tcs_code);
761 pipeline->shaders[MESA_SHADER_TESS_CTRL] = tcs_variant;
762 pipeline->shaders[MESA_SHADER_TESS_EVAL] = tes_variant;
763 return;
764 }
765
766 static VkResult
767 radv_pipeline_scratch_init(struct radv_device *device,
768 struct radv_pipeline *pipeline)
769 {
770 unsigned scratch_bytes_per_wave = 0;
771 unsigned max_waves = 0;
772 unsigned min_waves = 1;
773
774 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
775 if (pipeline->shaders[i]) {
776 unsigned max_stage_waves = device->scratch_waves;
777
778 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
779 pipeline->shaders[i]->config.scratch_bytes_per_wave);
780
781 max_stage_waves = MIN2(max_stage_waves,
782 4 * device->physical_device->rad_info.num_good_compute_units *
783 (256 / pipeline->shaders[i]->config.num_vgprs));
784 max_waves = MAX2(max_waves, max_stage_waves);
785 }
786 }
787
788 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
789 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
790 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
791 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
792 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
793 }
794
795 if (scratch_bytes_per_wave)
796 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
797
798 if (scratch_bytes_per_wave && max_waves < min_waves) {
799 /* Not really true at this moment, but will be true on first
800 * execution. Avoid having hanging shaders. */
801 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
802 }
803 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
804 pipeline->max_waves = max_waves;
805 return VK_SUCCESS;
806 }
807
808 static uint32_t si_translate_blend_function(VkBlendOp op)
809 {
810 switch (op) {
811 case VK_BLEND_OP_ADD:
812 return V_028780_COMB_DST_PLUS_SRC;
813 case VK_BLEND_OP_SUBTRACT:
814 return V_028780_COMB_SRC_MINUS_DST;
815 case VK_BLEND_OP_REVERSE_SUBTRACT:
816 return V_028780_COMB_DST_MINUS_SRC;
817 case VK_BLEND_OP_MIN:
818 return V_028780_COMB_MIN_DST_SRC;
819 case VK_BLEND_OP_MAX:
820 return V_028780_COMB_MAX_DST_SRC;
821 default:
822 return 0;
823 }
824 }
825
826 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
827 {
828 switch (factor) {
829 case VK_BLEND_FACTOR_ZERO:
830 return V_028780_BLEND_ZERO;
831 case VK_BLEND_FACTOR_ONE:
832 return V_028780_BLEND_ONE;
833 case VK_BLEND_FACTOR_SRC_COLOR:
834 return V_028780_BLEND_SRC_COLOR;
835 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
836 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
837 case VK_BLEND_FACTOR_DST_COLOR:
838 return V_028780_BLEND_DST_COLOR;
839 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
840 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
841 case VK_BLEND_FACTOR_SRC_ALPHA:
842 return V_028780_BLEND_SRC_ALPHA;
843 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
844 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
845 case VK_BLEND_FACTOR_DST_ALPHA:
846 return V_028780_BLEND_DST_ALPHA;
847 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
848 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
849 case VK_BLEND_FACTOR_CONSTANT_COLOR:
850 return V_028780_BLEND_CONSTANT_COLOR;
851 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
852 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
853 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
854 return V_028780_BLEND_CONSTANT_ALPHA;
855 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
856 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
857 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
858 return V_028780_BLEND_SRC_ALPHA_SATURATE;
859 case VK_BLEND_FACTOR_SRC1_COLOR:
860 return V_028780_BLEND_SRC1_COLOR;
861 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
862 return V_028780_BLEND_INV_SRC1_COLOR;
863 case VK_BLEND_FACTOR_SRC1_ALPHA:
864 return V_028780_BLEND_SRC1_ALPHA;
865 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
866 return V_028780_BLEND_INV_SRC1_ALPHA;
867 default:
868 return 0;
869 }
870 }
871
872 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
873 {
874 switch (op) {
875 case VK_BLEND_OP_ADD:
876 return V_028760_OPT_COMB_ADD;
877 case VK_BLEND_OP_SUBTRACT:
878 return V_028760_OPT_COMB_SUBTRACT;
879 case VK_BLEND_OP_REVERSE_SUBTRACT:
880 return V_028760_OPT_COMB_REVSUBTRACT;
881 case VK_BLEND_OP_MIN:
882 return V_028760_OPT_COMB_MIN;
883 case VK_BLEND_OP_MAX:
884 return V_028760_OPT_COMB_MAX;
885 default:
886 return V_028760_OPT_COMB_BLEND_DISABLED;
887 }
888 }
889
890 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
891 {
892 switch (factor) {
893 case VK_BLEND_FACTOR_ZERO:
894 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
895 case VK_BLEND_FACTOR_ONE:
896 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
897 case VK_BLEND_FACTOR_SRC_COLOR:
898 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
899 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
900 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
901 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
902 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
903 case VK_BLEND_FACTOR_SRC_ALPHA:
904 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
905 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
906 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
907 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
908 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
909 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
910 default:
911 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
912 }
913 }
914
915 /**
916 * Get rid of DST in the blend factors by commuting the operands:
917 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
918 */
919 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
920 unsigned *dst_factor, unsigned expected_dst,
921 unsigned replacement_src)
922 {
923 if (*src_factor == expected_dst &&
924 *dst_factor == VK_BLEND_FACTOR_ZERO) {
925 *src_factor = VK_BLEND_FACTOR_ZERO;
926 *dst_factor = replacement_src;
927
928 /* Commuting the operands requires reversing subtractions. */
929 if (*func == VK_BLEND_OP_SUBTRACT)
930 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
931 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
932 *func = VK_BLEND_OP_SUBTRACT;
933 }
934 }
935
936 static bool si_blend_factor_uses_dst(unsigned factor)
937 {
938 return factor == VK_BLEND_FACTOR_DST_COLOR ||
939 factor == VK_BLEND_FACTOR_DST_ALPHA ||
940 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
941 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
942 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
943 }
944
945 static bool is_dual_src(VkBlendFactor factor)
946 {
947 switch (factor) {
948 case VK_BLEND_FACTOR_SRC1_COLOR:
949 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
950 case VK_BLEND_FACTOR_SRC1_ALPHA:
951 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
952 return true;
953 default:
954 return false;
955 }
956 }
957
958 static unsigned si_choose_spi_color_format(VkFormat vk_format,
959 bool blend_enable,
960 bool blend_need_alpha)
961 {
962 const struct vk_format_description *desc = vk_format_description(vk_format);
963 unsigned format, ntype, swap;
964
965 /* Alpha is needed for alpha-to-coverage.
966 * Blending may be with or without alpha.
967 */
968 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
969 unsigned alpha = 0; /* exports alpha, but may not support blending */
970 unsigned blend = 0; /* supports blending, but may not export alpha */
971 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
972
973 format = radv_translate_colorformat(vk_format);
974 ntype = radv_translate_color_numformat(vk_format, desc,
975 vk_format_get_first_non_void_channel(vk_format));
976 swap = radv_translate_colorswap(vk_format, false);
977
978 /* Choose the SPI color formats. These are required values for Stoney/RB+.
979 * Other chips have multiple choices, though they are not necessarily better.
980 */
981 switch (format) {
982 case V_028C70_COLOR_5_6_5:
983 case V_028C70_COLOR_1_5_5_5:
984 case V_028C70_COLOR_5_5_5_1:
985 case V_028C70_COLOR_4_4_4_4:
986 case V_028C70_COLOR_10_11_11:
987 case V_028C70_COLOR_11_11_10:
988 case V_028C70_COLOR_8:
989 case V_028C70_COLOR_8_8:
990 case V_028C70_COLOR_8_8_8_8:
991 case V_028C70_COLOR_10_10_10_2:
992 case V_028C70_COLOR_2_10_10_10:
993 if (ntype == V_028C70_NUMBER_UINT)
994 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
995 else if (ntype == V_028C70_NUMBER_SINT)
996 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
997 else
998 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
999 break;
1000
1001 case V_028C70_COLOR_16:
1002 case V_028C70_COLOR_16_16:
1003 case V_028C70_COLOR_16_16_16_16:
1004 if (ntype == V_028C70_NUMBER_UNORM ||
1005 ntype == V_028C70_NUMBER_SNORM) {
1006 /* UNORM16 and SNORM16 don't support blending */
1007 if (ntype == V_028C70_NUMBER_UNORM)
1008 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
1009 else
1010 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
1011
1012 /* Use 32 bits per channel for blending. */
1013 if (format == V_028C70_COLOR_16) {
1014 if (swap == V_028C70_SWAP_STD) { /* R */
1015 blend = V_028714_SPI_SHADER_32_R;
1016 blend_alpha = V_028714_SPI_SHADER_32_AR;
1017 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
1018 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
1019 else
1020 assert(0);
1021 } else if (format == V_028C70_COLOR_16_16) {
1022 if (swap == V_028C70_SWAP_STD) { /* RG */
1023 blend = V_028714_SPI_SHADER_32_GR;
1024 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1025 } else if (swap == V_028C70_SWAP_ALT) /* RA */
1026 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
1027 else
1028 assert(0);
1029 } else /* 16_16_16_16 */
1030 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1031 } else if (ntype == V_028C70_NUMBER_UINT)
1032 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
1033 else if (ntype == V_028C70_NUMBER_SINT)
1034 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
1035 else if (ntype == V_028C70_NUMBER_FLOAT)
1036 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
1037 else
1038 assert(0);
1039 break;
1040
1041 case V_028C70_COLOR_32:
1042 if (swap == V_028C70_SWAP_STD) { /* R */
1043 blend = normal = V_028714_SPI_SHADER_32_R;
1044 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
1045 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
1046 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
1047 else
1048 assert(0);
1049 break;
1050
1051 case V_028C70_COLOR_32_32:
1052 if (swap == V_028C70_SWAP_STD) { /* RG */
1053 blend = normal = V_028714_SPI_SHADER_32_GR;
1054 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1055 } else if (swap == V_028C70_SWAP_ALT) /* RA */
1056 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
1057 else
1058 assert(0);
1059 break;
1060
1061 case V_028C70_COLOR_32_32_32_32:
1062 case V_028C70_COLOR_8_24:
1063 case V_028C70_COLOR_24_8:
1064 case V_028C70_COLOR_X24_8_32_FLOAT:
1065 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
1066 break;
1067
1068 default:
1069 unreachable("unhandled blend format");
1070 }
1071
1072 if (blend_enable && blend_need_alpha)
1073 return blend_alpha;
1074 else if(blend_need_alpha)
1075 return alpha;
1076 else if(blend_enable)
1077 return blend;
1078 else
1079 return normal;
1080 }
1081
1082 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
1083 {
1084 unsigned i, cb_shader_mask = 0;
1085
1086 for (i = 0; i < 8; i++) {
1087 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
1088 case V_028714_SPI_SHADER_ZERO:
1089 break;
1090 case V_028714_SPI_SHADER_32_R:
1091 cb_shader_mask |= 0x1 << (i * 4);
1092 break;
1093 case V_028714_SPI_SHADER_32_GR:
1094 cb_shader_mask |= 0x3 << (i * 4);
1095 break;
1096 case V_028714_SPI_SHADER_32_AR:
1097 cb_shader_mask |= 0x9 << (i * 4);
1098 break;
1099 case V_028714_SPI_SHADER_FP16_ABGR:
1100 case V_028714_SPI_SHADER_UNORM16_ABGR:
1101 case V_028714_SPI_SHADER_SNORM16_ABGR:
1102 case V_028714_SPI_SHADER_UINT16_ABGR:
1103 case V_028714_SPI_SHADER_SINT16_ABGR:
1104 case V_028714_SPI_SHADER_32_ABGR:
1105 cb_shader_mask |= 0xf << (i * 4);
1106 break;
1107 default:
1108 assert(0);
1109 }
1110 }
1111 return cb_shader_mask;
1112 }
1113
1114 static void
1115 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
1116 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1117 uint32_t blend_enable,
1118 uint32_t blend_need_alpha,
1119 bool single_cb_enable,
1120 bool blend_mrt0_is_dual_src)
1121 {
1122 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1123 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
1124 struct radv_blend_state *blend = &pipeline->graphics.blend;
1125 unsigned col_format = 0;
1126
1127 for (unsigned i = 0; i < (single_cb_enable ? 1 : subpass->color_count); ++i) {
1128 unsigned cf;
1129
1130 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1131 cf = V_028714_SPI_SHADER_ZERO;
1132 } else {
1133 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
1134
1135 cf = si_choose_spi_color_format(attachment->format,
1136 blend_enable & (1 << i),
1137 blend_need_alpha & (1 << i));
1138 }
1139
1140 col_format |= cf << (4 * i);
1141 }
1142
1143 blend->cb_shader_mask = si_get_cb_shader_mask(col_format);
1144
1145 if (blend_mrt0_is_dual_src)
1146 col_format |= (col_format & 0xf) << 4;
1147 blend->spi_shader_col_format = col_format;
1148 }
1149
1150 static bool
1151 format_is_int8(VkFormat format)
1152 {
1153 const struct vk_format_description *desc = vk_format_description(format);
1154 int channel = vk_format_get_first_non_void_channel(format);
1155
1156 return channel >= 0 && desc->channel[channel].pure_integer &&
1157 desc->channel[channel].size == 8;
1158 }
1159
1160 static bool
1161 format_is_int10(VkFormat format)
1162 {
1163 const struct vk_format_description *desc = vk_format_description(format);
1164
1165 if (desc->nr_channels != 4)
1166 return false;
1167 for (unsigned i = 0; i < 4; i++) {
1168 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
1169 return true;
1170 }
1171 return false;
1172 }
1173
1174 unsigned radv_format_meta_fs_key(VkFormat format)
1175 {
1176 unsigned col_format = si_choose_spi_color_format(format, false, false) - 1;
1177 bool is_int8 = format_is_int8(format);
1178 bool is_int10 = format_is_int10(format);
1179
1180 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
1181 }
1182
1183 static void
1184 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo *pCreateInfo,
1185 unsigned *is_int8, unsigned *is_int10)
1186 {
1187 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1188 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
1189 *is_int8 = 0;
1190 *is_int10 = 0;
1191
1192 for (unsigned i = 0; i < subpass->color_count; ++i) {
1193 struct radv_render_pass_attachment *attachment;
1194
1195 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
1196 continue;
1197
1198 attachment = pass->attachments + subpass->color_attachments[i].attachment;
1199
1200 if (format_is_int8(attachment->format))
1201 *is_int8 |= 1 << i;
1202 if (format_is_int10(attachment->format))
1203 *is_int10 |= 1 << i;
1204 }
1205 }
1206
1207 static void
1208 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
1209 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1210 const struct radv_graphics_pipeline_create_info *extra)
1211 {
1212 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
1213 struct radv_blend_state *blend = &pipeline->graphics.blend;
1214 unsigned mode = V_028808_CB_NORMAL;
1215 uint32_t blend_enable = 0, blend_need_alpha = 0;
1216 bool blend_mrt0_is_dual_src = false;
1217 int i;
1218 bool single_cb_enable = false;
1219
1220 if (!vkblend)
1221 return;
1222
1223 if (extra && extra->custom_blend_mode) {
1224 single_cb_enable = true;
1225 mode = extra->custom_blend_mode;
1226 }
1227 blend->cb_color_control = 0;
1228 if (vkblend->logicOpEnable)
1229 blend->cb_color_control |= S_028808_ROP3(vkblend->logicOp | (vkblend->logicOp << 4));
1230 else
1231 blend->cb_color_control |= S_028808_ROP3(0xcc);
1232
1233 blend->db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
1234 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
1235 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
1236 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
1237
1238 blend->cb_target_mask = 0;
1239 for (i = 0; i < vkblend->attachmentCount; i++) {
1240 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
1241 unsigned blend_cntl = 0;
1242 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
1243 VkBlendOp eqRGB = att->colorBlendOp;
1244 VkBlendFactor srcRGB = att->srcColorBlendFactor;
1245 VkBlendFactor dstRGB = att->dstColorBlendFactor;
1246 VkBlendOp eqA = att->alphaBlendOp;
1247 VkBlendFactor srcA = att->srcAlphaBlendFactor;
1248 VkBlendFactor dstA = att->dstAlphaBlendFactor;
1249
1250 blend->sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
1251
1252 if (!att->colorWriteMask)
1253 continue;
1254
1255 blend->cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
1256 if (!att->blendEnable) {
1257 blend->cb_blend_control[i] = blend_cntl;
1258 continue;
1259 }
1260
1261 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
1262 if (i == 0)
1263 blend_mrt0_is_dual_src = true;
1264
1265 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
1266 srcRGB = VK_BLEND_FACTOR_ONE;
1267 dstRGB = VK_BLEND_FACTOR_ONE;
1268 }
1269 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
1270 srcA = VK_BLEND_FACTOR_ONE;
1271 dstA = VK_BLEND_FACTOR_ONE;
1272 }
1273
1274 /* Blending optimizations for RB+.
1275 * These transformations don't change the behavior.
1276 *
1277 * First, get rid of DST in the blend factors:
1278 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
1279 */
1280 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
1281 VK_BLEND_FACTOR_DST_COLOR,
1282 VK_BLEND_FACTOR_SRC_COLOR);
1283
1284 si_blend_remove_dst(&eqA, &srcA, &dstA,
1285 VK_BLEND_FACTOR_DST_COLOR,
1286 VK_BLEND_FACTOR_SRC_COLOR);
1287
1288 si_blend_remove_dst(&eqA, &srcA, &dstA,
1289 VK_BLEND_FACTOR_DST_ALPHA,
1290 VK_BLEND_FACTOR_SRC_ALPHA);
1291
1292 /* Look up the ideal settings from tables. */
1293 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
1294 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
1295 srcA_opt = si_translate_blend_opt_factor(srcA, true);
1296 dstA_opt = si_translate_blend_opt_factor(dstA, true);
1297
1298 /* Handle interdependencies. */
1299 if (si_blend_factor_uses_dst(srcRGB))
1300 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
1301 if (si_blend_factor_uses_dst(srcA))
1302 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
1303
1304 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
1305 (dstRGB == VK_BLEND_FACTOR_ZERO ||
1306 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
1307 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
1308 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
1309
1310 /* Set the final value. */
1311 blend->sx_mrt_blend_opt[i] =
1312 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
1313 S_028760_COLOR_DST_OPT(dstRGB_opt) |
1314 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
1315 S_028760_ALPHA_SRC_OPT(srcA_opt) |
1316 S_028760_ALPHA_DST_OPT(dstA_opt) |
1317 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
1318 blend_cntl |= S_028780_ENABLE(1);
1319
1320 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
1321 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
1322 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
1323 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
1324 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
1325 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
1326 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
1327 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
1328 }
1329 blend->cb_blend_control[i] = blend_cntl;
1330
1331 blend_enable |= 1 << i;
1332
1333 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
1334 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
1335 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
1336 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
1337 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
1338 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
1339 blend_need_alpha |= 1 << i;
1340 }
1341 for (i = vkblend->attachmentCount; i < 8; i++) {
1342 blend->cb_blend_control[i] = 0;
1343 blend->sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
1344 }
1345
1346 /* disable RB+ for now */
1347 if (pipeline->device->physical_device->has_rbplus)
1348 blend->cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
1349
1350 if (blend->cb_target_mask)
1351 blend->cb_color_control |= S_028808_MODE(mode);
1352 else
1353 blend->cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
1354
1355 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo,
1356 blend_enable, blend_need_alpha, single_cb_enable, blend_mrt0_is_dual_src);
1357 }
1358
1359 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
1360 {
1361 switch (op) {
1362 case VK_STENCIL_OP_KEEP:
1363 return V_02842C_STENCIL_KEEP;
1364 case VK_STENCIL_OP_ZERO:
1365 return V_02842C_STENCIL_ZERO;
1366 case VK_STENCIL_OP_REPLACE:
1367 return V_02842C_STENCIL_REPLACE_TEST;
1368 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
1369 return V_02842C_STENCIL_ADD_CLAMP;
1370 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
1371 return V_02842C_STENCIL_SUB_CLAMP;
1372 case VK_STENCIL_OP_INVERT:
1373 return V_02842C_STENCIL_INVERT;
1374 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
1375 return V_02842C_STENCIL_ADD_WRAP;
1376 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
1377 return V_02842C_STENCIL_SUB_WRAP;
1378 default:
1379 return 0;
1380 }
1381 }
1382 static void
1383 radv_pipeline_init_depth_stencil_state(struct radv_pipeline *pipeline,
1384 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1385 const struct radv_graphics_pipeline_create_info *extra)
1386 {
1387 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
1388 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
1389
1390 memset(ds, 0, sizeof(*ds));
1391 if (!vkds)
1392 return;
1393
1394 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1395 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
1396 if (subpass->depth_stencil_attachment.attachment == VK_ATTACHMENT_UNUSED)
1397 return;
1398
1399 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment.attachment;
1400 bool has_depth_attachment = vk_format_is_depth(attachment->format);
1401 bool has_stencil_attachment = vk_format_is_stencil(attachment->format);
1402
1403 if (has_depth_attachment) {
1404 ds->db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
1405 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
1406 S_028800_ZFUNC(vkds->depthCompareOp) |
1407 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
1408 }
1409
1410 if (has_stencil_attachment && vkds->stencilTestEnable) {
1411 ds->db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
1412 ds->db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
1413 ds->db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
1414 ds->db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
1415 ds->db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
1416
1417 ds->db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
1418 ds->db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
1419 ds->db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
1420 ds->db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
1421 }
1422
1423 if (extra) {
1424
1425 ds->db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
1426 ds->db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
1427
1428 ds->db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
1429 ds->db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
1430 ds->db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
1431 ds->db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
1432 ds->db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
1433 }
1434 }
1435
1436 static uint32_t si_translate_fill(VkPolygonMode func)
1437 {
1438 switch(func) {
1439 case VK_POLYGON_MODE_FILL:
1440 return V_028814_X_DRAW_TRIANGLES;
1441 case VK_POLYGON_MODE_LINE:
1442 return V_028814_X_DRAW_LINES;
1443 case VK_POLYGON_MODE_POINT:
1444 return V_028814_X_DRAW_POINTS;
1445 default:
1446 assert(0);
1447 return V_028814_X_DRAW_POINTS;
1448 }
1449 }
1450 static void
1451 radv_pipeline_init_raster_state(struct radv_pipeline *pipeline,
1452 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1453 {
1454 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
1455 struct radv_raster_state *raster = &pipeline->graphics.raster;
1456
1457 memset(raster, 0, sizeof(*raster));
1458
1459 raster->spi_interp_control =
1460 S_0286D4_FLAT_SHADE_ENA(1) |
1461 S_0286D4_PNT_SPRITE_ENA(1) |
1462 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
1463 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
1464 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
1465 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
1466 S_0286D4_PNT_SPRITE_TOP_1(0); // vulkan is top to bottom - 1.0 at bottom
1467
1468
1469 raster->pa_cl_clip_cntl = S_028810_PS_UCP_MODE(3) |
1470 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
1471 S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1472 S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1473 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
1474 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
1475
1476 raster->pa_su_vtx_cntl =
1477 S_028BE4_PIX_CENTER(1) | // TODO verify
1478 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
1479 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH);
1480
1481 raster->pa_su_sc_mode_cntl =
1482 S_028814_FACE(vkraster->frontFace) |
1483 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
1484 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
1485 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
1486 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1487 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1488 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1489 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1490 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0);
1491
1492 }
1493
1494 static void
1495 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1496 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1497 {
1498 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
1499 struct radv_blend_state *blend = &pipeline->graphics.blend;
1500 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1501 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1502 int ps_iter_samples = 1;
1503 uint32_t mask = 0xffff;
1504
1505 if (vkms)
1506 ms->num_samples = vkms->rasterizationSamples;
1507 else
1508 ms->num_samples = 1;
1509
1510 if (vkms && vkms->sampleShadingEnable) {
1511 ps_iter_samples = ceil(vkms->minSampleShading * ms->num_samples);
1512 } else if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.force_persample) {
1513 ps_iter_samples = ms->num_samples;
1514 }
1515
1516 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1517 ms->pa_sc_aa_config = 0;
1518 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1519 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1520 ms->pa_sc_mode_cntl_1 =
1521 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1522 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1523 /* always 1: */
1524 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1525 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1526 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1527 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1528 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1529 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1530 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9);
1531
1532 if (ms->num_samples > 1) {
1533 unsigned log_samples = util_logbase2(ms->num_samples);
1534 unsigned log_ps_iter_samples = util_logbase2(util_next_power_of_two(ps_iter_samples));
1535 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
1536 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1537 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1538 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1539 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1540 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1541 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1542 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
1543 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1544 ms->pa_sc_mode_cntl_1 |= EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1545 }
1546
1547 if (vkms) {
1548 if (vkms->alphaToCoverageEnable)
1549 blend->db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
1550
1551 if (vkms->pSampleMask)
1552 mask = vkms->pSampleMask[0] & 0xffff;
1553 }
1554
1555 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1556 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1557 }
1558
1559 static bool
1560 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1561 {
1562 switch (topology) {
1563 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1564 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1565 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1566 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1567 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1568 return false;
1569 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1570 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1571 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1572 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1573 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1574 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1575 return true;
1576 default:
1577 unreachable("unhandled primitive type");
1578 }
1579 }
1580
1581 static uint32_t
1582 si_translate_prim(enum VkPrimitiveTopology topology)
1583 {
1584 switch (topology) {
1585 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1586 return V_008958_DI_PT_POINTLIST;
1587 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1588 return V_008958_DI_PT_LINELIST;
1589 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1590 return V_008958_DI_PT_LINESTRIP;
1591 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1592 return V_008958_DI_PT_TRILIST;
1593 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1594 return V_008958_DI_PT_TRISTRIP;
1595 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1596 return V_008958_DI_PT_TRIFAN;
1597 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1598 return V_008958_DI_PT_LINELIST_ADJ;
1599 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1600 return V_008958_DI_PT_LINESTRIP_ADJ;
1601 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1602 return V_008958_DI_PT_TRILIST_ADJ;
1603 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1604 return V_008958_DI_PT_TRISTRIP_ADJ;
1605 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1606 return V_008958_DI_PT_PATCH;
1607 default:
1608 assert(0);
1609 return 0;
1610 }
1611 }
1612
1613 static uint32_t
1614 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1615 {
1616 switch (gl_prim) {
1617 case 0: /* GL_POINTS */
1618 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1619 case 1: /* GL_LINES */
1620 case 3: /* GL_LINE_STRIP */
1621 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1622 case 0x8E7A: /* GL_ISOLINES */
1623 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1624
1625 case 4: /* GL_TRIANGLES */
1626 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1627 case 5: /* GL_TRIANGLE_STRIP */
1628 case 7: /* GL_QUADS */
1629 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1630 default:
1631 assert(0);
1632 return 0;
1633 }
1634 }
1635
1636 static uint32_t
1637 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1638 {
1639 switch (topology) {
1640 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1641 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1642 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1643 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1644 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1645 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1646 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1647 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1648 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1649 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1650 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1651 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1652 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1653 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1654 default:
1655 assert(0);
1656 return 0;
1657 }
1658 }
1659
1660 static unsigned si_map_swizzle(unsigned swizzle)
1661 {
1662 switch (swizzle) {
1663 case VK_SWIZZLE_Y:
1664 return V_008F0C_SQ_SEL_Y;
1665 case VK_SWIZZLE_Z:
1666 return V_008F0C_SQ_SEL_Z;
1667 case VK_SWIZZLE_W:
1668 return V_008F0C_SQ_SEL_W;
1669 case VK_SWIZZLE_0:
1670 return V_008F0C_SQ_SEL_0;
1671 case VK_SWIZZLE_1:
1672 return V_008F0C_SQ_SEL_1;
1673 default: /* VK_SWIZZLE_X */
1674 return V_008F0C_SQ_SEL_X;
1675 }
1676 }
1677
1678 static void
1679 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1680 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1681 {
1682 radv_cmd_dirty_mask_t states = RADV_CMD_DIRTY_DYNAMIC_ALL;
1683 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1684 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1685
1686 pipeline->dynamic_state = default_dynamic_state;
1687
1688 if (pCreateInfo->pDynamicState) {
1689 /* Remove all of the states that are marked as dynamic */
1690 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1691 for (uint32_t s = 0; s < count; s++)
1692 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
1693 }
1694
1695 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1696
1697 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1698 *
1699 * pViewportState is [...] NULL if the pipeline
1700 * has rasterization disabled.
1701 */
1702 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1703 assert(pCreateInfo->pViewportState);
1704
1705 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1706 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
1707 typed_memcpy(dynamic->viewport.viewports,
1708 pCreateInfo->pViewportState->pViewports,
1709 pCreateInfo->pViewportState->viewportCount);
1710 }
1711
1712 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1713 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
1714 typed_memcpy(dynamic->scissor.scissors,
1715 pCreateInfo->pViewportState->pScissors,
1716 pCreateInfo->pViewportState->scissorCount);
1717 }
1718 }
1719
1720 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
1721 assert(pCreateInfo->pRasterizationState);
1722 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1723 }
1724
1725 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
1726 assert(pCreateInfo->pRasterizationState);
1727 dynamic->depth_bias.bias =
1728 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1729 dynamic->depth_bias.clamp =
1730 pCreateInfo->pRasterizationState->depthBiasClamp;
1731 dynamic->depth_bias.slope =
1732 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1733 }
1734
1735 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1736 *
1737 * pColorBlendState is [...] NULL if the pipeline has rasterization
1738 * disabled or if the subpass of the render pass the pipeline is
1739 * created against does not use any color attachments.
1740 */
1741 bool uses_color_att = false;
1742 for (unsigned i = 0; i < subpass->color_count; ++i) {
1743 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1744 uses_color_att = true;
1745 break;
1746 }
1747 }
1748
1749 if (uses_color_att && states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
1750 assert(pCreateInfo->pColorBlendState);
1751 typed_memcpy(dynamic->blend_constants,
1752 pCreateInfo->pColorBlendState->blendConstants, 4);
1753 }
1754
1755 /* If there is no depthstencil attachment, then don't read
1756 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1757 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1758 * no need to override the depthstencil defaults in
1759 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1760 *
1761 * Section 9.2 of the Vulkan 1.0.15 spec says:
1762 *
1763 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1764 * disabled or if the subpass of the render pass the pipeline is created
1765 * against does not use a depth/stencil attachment.
1766 */
1767 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
1768 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1769 assert(pCreateInfo->pDepthStencilState);
1770
1771 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
1772 dynamic->depth_bounds.min =
1773 pCreateInfo->pDepthStencilState->minDepthBounds;
1774 dynamic->depth_bounds.max =
1775 pCreateInfo->pDepthStencilState->maxDepthBounds;
1776 }
1777
1778 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
1779 dynamic->stencil_compare_mask.front =
1780 pCreateInfo->pDepthStencilState->front.compareMask;
1781 dynamic->stencil_compare_mask.back =
1782 pCreateInfo->pDepthStencilState->back.compareMask;
1783 }
1784
1785 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
1786 dynamic->stencil_write_mask.front =
1787 pCreateInfo->pDepthStencilState->front.writeMask;
1788 dynamic->stencil_write_mask.back =
1789 pCreateInfo->pDepthStencilState->back.writeMask;
1790 }
1791
1792 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
1793 dynamic->stencil_reference.front =
1794 pCreateInfo->pDepthStencilState->front.reference;
1795 dynamic->stencil_reference.back =
1796 pCreateInfo->pDepthStencilState->back.reference;
1797 }
1798 }
1799
1800 pipeline->dynamic_state_mask = states;
1801 }
1802
1803 static struct ac_shader_variant_key
1804 radv_compute_vs_key(const VkGraphicsPipelineCreateInfo *pCreateInfo, bool as_es, bool as_ls, bool export_prim_id)
1805 {
1806 struct ac_shader_variant_key key;
1807 const VkPipelineVertexInputStateCreateInfo *input_state =
1808 pCreateInfo->pVertexInputState;
1809
1810 memset(&key, 0, sizeof(key));
1811 key.vs.instance_rate_inputs = 0;
1812 key.vs.as_es = as_es;
1813 key.vs.as_ls = as_ls;
1814 key.vs.export_prim_id = export_prim_id;
1815
1816 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
1817 unsigned binding;
1818 binding = input_state->pVertexAttributeDescriptions[i].binding;
1819 if (input_state->pVertexBindingDescriptions[binding].inputRate)
1820 key.vs.instance_rate_inputs |= 1u << input_state->pVertexAttributeDescriptions[i].location;
1821 }
1822 return key;
1823 }
1824
1825 static void
1826 calculate_gs_ring_sizes(struct radv_pipeline *pipeline)
1827 {
1828 struct radv_device *device = pipeline->device;
1829 unsigned num_se = device->physical_device->rad_info.max_se;
1830 unsigned wave_size = 64;
1831 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1832 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1833 unsigned alignment = 256 * num_se;
1834 /* The maximum size is 63.999 MB per SE. */
1835 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1836 struct ac_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1837 struct ac_es_output_info *es_info = radv_pipeline_has_tess(pipeline) ?
1838 &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.es_info :
1839 &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info;
1840
1841 /* Calculate the minimum size. */
1842 unsigned min_esgs_ring_size = align(es_info->esgs_itemsize * gs_vertex_reuse *
1843 wave_size, alignment);
1844 /* These are recommended sizes, not minimum sizes. */
1845 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1846 es_info->esgs_itemsize * gs_info->gs.vertices_in;
1847 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1848 gs_info->gs.max_gsvs_emit_size * 1; // no streams in VK (gs->max_gs_stream + 1);
1849
1850 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1851 esgs_ring_size = align(esgs_ring_size, alignment);
1852 gsvs_ring_size = align(gsvs_ring_size, alignment);
1853
1854 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1855 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1856 }
1857
1858 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1859 unsigned *lds_size)
1860 {
1861 /* SPI barrier management bug:
1862 * Make sure we have at least 4k of LDS in use to avoid the bug.
1863 * It applies to workgroup sizes of more than one wavefront.
1864 */
1865 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1866 device->physical_device->rad_info.family == CHIP_KABINI ||
1867 device->physical_device->rad_info.family == CHIP_MULLINS)
1868 *lds_size = MAX2(*lds_size, 8);
1869 }
1870
1871 static void
1872 calculate_tess_state(struct radv_pipeline *pipeline,
1873 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1874 {
1875 unsigned num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1876 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
1877 unsigned num_tcs_patch_outputs;
1878 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
1879 unsigned input_patch_size, output_patch_size, output_patch0_offset;
1880 unsigned lds_size, hardware_lds_size;
1881 unsigned perpatch_output_offset;
1882 unsigned num_patches;
1883 struct radv_tessellation_state *tess = &pipeline->graphics.tess;
1884
1885 /* This calculates how shader inputs and outputs among VS, TCS, and TES
1886 * are laid out in LDS. */
1887 num_tcs_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outputs_written);
1888
1889 num_tcs_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written); //tcs->outputs_written
1890 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1891 num_tcs_patch_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.patch_outputs_written);
1892
1893 /* Ensure that we only need one wave per SIMD so we don't need to check
1894 * resource usage. Also ensures that the number of tcs in and out
1895 * vertices per threadgroup are at most 256.
1896 */
1897 input_vertex_size = num_tcs_inputs * 16;
1898 output_vertex_size = num_tcs_outputs * 16;
1899
1900 input_patch_size = num_tcs_input_cp * input_vertex_size;
1901
1902 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
1903 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
1904 /* Ensure that we only need one wave per SIMD so we don't need to check
1905 * resource usage. Also ensures that the number of tcs in and out
1906 * vertices per threadgroup are at most 256.
1907 */
1908 num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
1909
1910 /* Make sure that the data fits in LDS. This assumes the shaders only
1911 * use LDS for the inputs and outputs.
1912 */
1913 hardware_lds_size = pipeline->device->physical_device->rad_info.chip_class >= CIK ? 65536 : 32768;
1914 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
1915
1916 /* Make sure the output data fits in the offchip buffer */
1917 num_patches = MIN2(num_patches,
1918 (pipeline->device->tess_offchip_block_dw_size * 4) /
1919 output_patch_size);
1920
1921 /* Not necessary for correctness, but improves performance. The
1922 * specific value is taken from the proprietary driver.
1923 */
1924 num_patches = MIN2(num_patches, 40);
1925
1926 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
1927 if (pipeline->device->physical_device->rad_info.chip_class == SI) {
1928 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
1929 num_patches = MIN2(num_patches, one_wave);
1930 }
1931
1932 output_patch0_offset = input_patch_size * num_patches;
1933 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
1934
1935 lds_size = output_patch0_offset + output_patch_size * num_patches;
1936
1937 if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
1938 assert(lds_size <= 65536);
1939 lds_size = align(lds_size, 512) / 512;
1940 } else {
1941 assert(lds_size <= 32768);
1942 lds_size = align(lds_size, 256) / 256;
1943 }
1944 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1945
1946 tess->lds_size = lds_size;
1947
1948 tess->tcs_in_layout = (input_patch_size / 4) |
1949 ((input_vertex_size / 4) << 13);
1950 tess->tcs_out_layout = (output_patch_size / 4) |
1951 ((output_vertex_size / 4) << 13);
1952 tess->tcs_out_offsets = (output_patch0_offset / 16) |
1953 ((perpatch_output_offset / 16) << 16);
1954 tess->offchip_layout = (pervertex_output_patch_size * num_patches << 16) |
1955 (num_tcs_output_cp << 9) | num_patches;
1956
1957 tess->ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1958 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1959 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1960 tess->num_patches = num_patches;
1961 tess->num_tcs_input_cp = num_tcs_input_cp;
1962
1963 struct radv_shader_variant *tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
1964 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1965
1966 switch (tes->info.tes.primitive_mode) {
1967 case GL_TRIANGLES:
1968 type = V_028B6C_TESS_TRIANGLE;
1969 break;
1970 case GL_QUADS:
1971 type = V_028B6C_TESS_QUAD;
1972 break;
1973 case GL_ISOLINES:
1974 type = V_028B6C_TESS_ISOLINE;
1975 break;
1976 }
1977
1978 switch (tes->info.tes.spacing) {
1979 case TESS_SPACING_EQUAL:
1980 partitioning = V_028B6C_PART_INTEGER;
1981 break;
1982 case TESS_SPACING_FRACTIONAL_ODD:
1983 partitioning = V_028B6C_PART_FRAC_ODD;
1984 break;
1985 case TESS_SPACING_FRACTIONAL_EVEN:
1986 partitioning = V_028B6C_PART_FRAC_EVEN;
1987 break;
1988 default:
1989 break;
1990 }
1991
1992 if (tes->info.tes.point_mode)
1993 topology = V_028B6C_OUTPUT_POINT;
1994 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
1995 topology = V_028B6C_OUTPUT_LINE;
1996 else if (tes->info.tes.ccw)
1997 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
1998 else
1999 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
2000
2001 if (pipeline->device->has_distributed_tess) {
2002 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
2003 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
2004 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
2005 else
2006 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
2007 } else
2008 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
2009
2010 tess->tf_param = S_028B6C_TYPE(type) |
2011 S_028B6C_PARTITIONING(partitioning) |
2012 S_028B6C_TOPOLOGY(topology) |
2013 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
2014 }
2015
2016 static const struct radv_prim_vertex_count prim_size_table[] = {
2017 [V_008958_DI_PT_NONE] = {0, 0},
2018 [V_008958_DI_PT_POINTLIST] = {1, 1},
2019 [V_008958_DI_PT_LINELIST] = {2, 2},
2020 [V_008958_DI_PT_LINESTRIP] = {2, 1},
2021 [V_008958_DI_PT_TRILIST] = {3, 3},
2022 [V_008958_DI_PT_TRIFAN] = {3, 1},
2023 [V_008958_DI_PT_TRISTRIP] = {3, 1},
2024 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
2025 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
2026 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
2027 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
2028 [V_008958_DI_PT_RECTLIST] = {3, 3},
2029 [V_008958_DI_PT_LINELOOP] = {2, 1},
2030 [V_008958_DI_PT_POLYGON] = {3, 1},
2031 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
2032 };
2033
2034 static uint32_t si_vgt_gs_mode(struct radv_shader_variant *gs)
2035 {
2036 unsigned gs_max_vert_out = gs->info.gs.vertices_out;
2037 unsigned cut_mode;
2038
2039 if (gs_max_vert_out <= 128) {
2040 cut_mode = V_028A40_GS_CUT_128;
2041 } else if (gs_max_vert_out <= 256) {
2042 cut_mode = V_028A40_GS_CUT_256;
2043 } else if (gs_max_vert_out <= 512) {
2044 cut_mode = V_028A40_GS_CUT_512;
2045 } else {
2046 assert(gs_max_vert_out <= 1024);
2047 cut_mode = V_028A40_GS_CUT_1024;
2048 }
2049
2050 return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
2051 S_028A40_CUT_MODE(cut_mode)|
2052 S_028A40_ES_WRITE_OPTIMIZE(1) |
2053 S_028A40_GS_WRITE_OPTIMIZE(1);
2054 }
2055
2056 static void calculate_vgt_gs_mode(struct radv_pipeline *pipeline)
2057 {
2058 struct radv_shader_variant *vs;
2059 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : (radv_pipeline_has_tess(pipeline) ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX]);
2060
2061 struct ac_vs_output_info *outinfo = &vs->info.vs.outinfo;
2062
2063 pipeline->graphics.vgt_primitiveid_en = false;
2064 pipeline->graphics.vgt_gs_mode = 0;
2065
2066 if (radv_pipeline_has_gs(pipeline)) {
2067 pipeline->graphics.vgt_gs_mode = si_vgt_gs_mode(pipeline->shaders[MESA_SHADER_GEOMETRY]);
2068 } else if (outinfo->export_prim_id) {
2069 pipeline->graphics.vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
2070 pipeline->graphics.vgt_primitiveid_en = true;
2071 }
2072 }
2073
2074 static void calculate_pa_cl_vs_out_cntl(struct radv_pipeline *pipeline)
2075 {
2076 struct radv_shader_variant *vs;
2077 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : (radv_pipeline_has_tess(pipeline) ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX]);
2078
2079 struct ac_vs_output_info *outinfo = &vs->info.vs.outinfo;
2080
2081 unsigned clip_dist_mask, cull_dist_mask, total_mask;
2082 clip_dist_mask = outinfo->clip_dist_mask;
2083 cull_dist_mask = outinfo->cull_dist_mask;
2084 total_mask = clip_dist_mask | cull_dist_mask;
2085
2086 bool misc_vec_ena = outinfo->writes_pointsize ||
2087 outinfo->writes_layer ||
2088 outinfo->writes_viewport_index;
2089 pipeline->graphics.pa_cl_vs_out_cntl =
2090 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
2091 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
2092 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
2093 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2094 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
2095 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
2096 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
2097 cull_dist_mask << 8 |
2098 clip_dist_mask;
2099
2100 }
2101
2102 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade)
2103 {
2104 uint32_t ps_input_cntl;
2105 if (offset <= AC_EXP_PARAM_OFFSET_31) {
2106 ps_input_cntl = S_028644_OFFSET(offset);
2107 if (flat_shade)
2108 ps_input_cntl |= S_028644_FLAT_SHADE(1);
2109 } else {
2110 /* The input is a DEFAULT_VAL constant. */
2111 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
2112 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
2113 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
2114 ps_input_cntl = S_028644_OFFSET(0x20) |
2115 S_028644_DEFAULT_VAL(offset);
2116 }
2117 return ps_input_cntl;
2118 }
2119
2120 static void calculate_ps_inputs(struct radv_pipeline *pipeline)
2121 {
2122 struct radv_shader_variant *ps, *vs;
2123 struct ac_vs_output_info *outinfo;
2124
2125 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
2126 vs = radv_pipeline_has_gs(pipeline) ? pipeline->gs_copy_shader : (radv_pipeline_has_tess(pipeline) ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX]);
2127
2128 outinfo = &vs->info.vs.outinfo;
2129
2130 unsigned ps_offset = 0;
2131
2132 if (ps->info.fs.prim_id_input) {
2133 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
2134 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
2135 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
2136 ++ps_offset;
2137 }
2138 }
2139
2140 if (ps->info.fs.layer_input) {
2141 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
2142 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
2143 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
2144 else
2145 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true);
2146 ++ps_offset;
2147 }
2148
2149 if (ps->info.fs.has_pcoord) {
2150 unsigned val;
2151 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
2152 pipeline->graphics.ps_input_cntl[ps_offset] = val;
2153 ps_offset++;
2154 }
2155
2156 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
2157 unsigned vs_offset;
2158 bool flat_shade;
2159 if (!(ps->info.fs.input_mask & (1u << i)))
2160 continue;
2161
2162 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
2163 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
2164 pipeline->graphics.ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
2165 ++ps_offset;
2166 continue;
2167 }
2168
2169 flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset));
2170
2171 pipeline->graphics.ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade);
2172 ++ps_offset;
2173 }
2174
2175 pipeline->graphics.ps_input_cntl_num = ps_offset;
2176 }
2177
2178 VkResult
2179 radv_pipeline_init(struct radv_pipeline *pipeline,
2180 struct radv_device *device,
2181 struct radv_pipeline_cache *cache,
2182 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2183 const struct radv_graphics_pipeline_create_info *extra,
2184 const VkAllocationCallbacks *alloc)
2185 {
2186 struct radv_shader_module fs_m = {0};
2187 VkResult result;
2188 bool has_view_index = false;
2189
2190 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2191 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2192 if (subpass->view_mask)
2193 has_view_index = true;
2194 if (alloc == NULL)
2195 alloc = &device->alloc;
2196
2197 pipeline->device = device;
2198 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
2199
2200 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
2201 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
2202 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
2203 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
2204 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
2205 pStages[stage] = &pCreateInfo->pStages[i];
2206 modules[stage] = radv_shader_module_from_handle(pStages[stage]->module);
2207 }
2208
2209 radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
2210
2211 if (!modules[MESA_SHADER_FRAGMENT]) {
2212 nir_builder fs_b;
2213 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
2214 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
2215 fs_m.nir = fs_b.shader;
2216 modules[MESA_SHADER_FRAGMENT] = &fs_m;
2217 }
2218
2219 if (modules[MESA_SHADER_FRAGMENT]) {
2220 struct ac_shader_variant_key key = {0};
2221 key.fs.col_format = pipeline->graphics.blend.spi_shader_col_format;
2222 if (pCreateInfo->pMultisampleState &&
2223 pCreateInfo->pMultisampleState->rasterizationSamples > 1)
2224 key.fs.multisample = true;
2225
2226 if (pipeline->device->physical_device->rad_info.chip_class < VI)
2227 radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.fs.is_int8, &key.fs.is_int10);
2228
2229 const VkPipelineShaderStageCreateInfo *stage = pStages[MESA_SHADER_FRAGMENT];
2230
2231 pipeline->shaders[MESA_SHADER_FRAGMENT] =
2232 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_FRAGMENT],
2233 stage ? stage->pName : "main",
2234 MESA_SHADER_FRAGMENT,
2235 stage ? stage->pSpecializationInfo : NULL,
2236 pipeline->layout, &key);
2237 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_FRAGMENT);
2238 }
2239
2240 if (fs_m.nir)
2241 ralloc_free(fs_m.nir);
2242
2243 if (modules[MESA_SHADER_VERTEX]) {
2244 bool as_es = false;
2245 bool as_ls = false;
2246 bool export_prim_id = false;
2247 if (modules[MESA_SHADER_TESS_CTRL])
2248 as_ls = true;
2249 else if (modules[MESA_SHADER_GEOMETRY])
2250 as_es = true;
2251 else if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input)
2252 export_prim_id = true;
2253 struct ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo, as_es, as_ls, export_prim_id);
2254 key.has_multiview_view_index = has_view_index;
2255
2256 pipeline->shaders[MESA_SHADER_VERTEX] =
2257 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_VERTEX],
2258 pStages[MESA_SHADER_VERTEX]->pName,
2259 MESA_SHADER_VERTEX,
2260 pStages[MESA_SHADER_VERTEX]->pSpecializationInfo,
2261 pipeline->layout, &key);
2262
2263 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_VERTEX);
2264 }
2265
2266 if (modules[MESA_SHADER_GEOMETRY]) {
2267 struct ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo, false, false, false);
2268 key.has_multiview_view_index = has_view_index;
2269
2270 pipeline->shaders[MESA_SHADER_GEOMETRY] =
2271 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_GEOMETRY],
2272 pStages[MESA_SHADER_GEOMETRY]->pName,
2273 MESA_SHADER_GEOMETRY,
2274 pStages[MESA_SHADER_GEOMETRY]->pSpecializationInfo,
2275 pipeline->layout, &key);
2276
2277 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_GEOMETRY);
2278 }
2279
2280 if (modules[MESA_SHADER_TESS_EVAL]) {
2281 assert(modules[MESA_SHADER_TESS_CTRL]);
2282
2283 radv_tess_pipeline_compile(pipeline,
2284 cache,
2285 modules[MESA_SHADER_TESS_CTRL],
2286 modules[MESA_SHADER_TESS_EVAL],
2287 pStages[MESA_SHADER_TESS_CTRL]->pName,
2288 pStages[MESA_SHADER_TESS_EVAL]->pName,
2289 pStages[MESA_SHADER_TESS_CTRL]->pSpecializationInfo,
2290 pStages[MESA_SHADER_TESS_EVAL]->pSpecializationInfo,
2291 pipeline->layout,
2292 pCreateInfo->pTessellationState->patchControlPoints,
2293 has_view_index);
2294 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_TESS_EVAL) |
2295 mesa_to_vk_shader_stage(MESA_SHADER_TESS_CTRL);
2296 }
2297
2298 radv_pipeline_init_depth_stencil_state(pipeline, pCreateInfo, extra);
2299 radv_pipeline_init_raster_state(pipeline, pCreateInfo);
2300 radv_pipeline_init_multisample_state(pipeline, pCreateInfo);
2301 pipeline->graphics.prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
2302 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
2303
2304 if (radv_pipeline_has_gs(pipeline)) {
2305 pipeline->graphics.gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
2306 pipeline->graphics.can_use_guardband = pipeline->graphics.gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
2307 } else {
2308 pipeline->graphics.gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
2309 }
2310 if (extra && extra->use_rectlist) {
2311 pipeline->graphics.prim = V_008958_DI_PT_RECTLIST;
2312 pipeline->graphics.gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
2313 pipeline->graphics.can_use_guardband = true;
2314 }
2315 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
2316 /* prim vertex count will need TESS changes */
2317 pipeline->graphics.prim_vertex_count = prim_size_table[pipeline->graphics.prim];
2318
2319 /* Ensure that some export memory is always allocated, for two reasons:
2320 *
2321 * 1) Correctness: The hardware ignores the EXEC mask if no export
2322 * memory is allocated, so KILL and alpha test do not work correctly
2323 * without this.
2324 * 2) Performance: Every shader needs at least a NULL export, even when
2325 * it writes no color/depth output. The NULL export instruction
2326 * stalls without this setting.
2327 *
2328 * Don't add this to CB_SHADER_MASK.
2329 */
2330 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
2331 if (!pipeline->graphics.blend.spi_shader_col_format) {
2332 if (!ps->info.fs.writes_z &&
2333 !ps->info.fs.writes_stencil &&
2334 !ps->info.fs.writes_sample_mask)
2335 pipeline->graphics.blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
2336 }
2337
2338 unsigned z_order;
2339 pipeline->graphics.db_shader_control = 0;
2340 if (ps->info.fs.early_fragment_test || !ps->info.fs.writes_memory)
2341 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
2342 else
2343 z_order = V_02880C_LATE_Z;
2344
2345 pipeline->graphics.db_shader_control =
2346 S_02880C_Z_EXPORT_ENABLE(ps->info.fs.writes_z) |
2347 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.fs.writes_stencil) |
2348 S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) |
2349 S_02880C_MASK_EXPORT_ENABLE(ps->info.fs.writes_sample_mask) |
2350 S_02880C_Z_ORDER(z_order) |
2351 S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) |
2352 S_02880C_EXEC_ON_HIER_FAIL(ps->info.fs.writes_memory) |
2353 S_02880C_EXEC_ON_NOOP(ps->info.fs.writes_memory);
2354
2355 if (pipeline->device->physical_device->has_rbplus)
2356 pipeline->graphics.db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
2357
2358 pipeline->graphics.shader_z_format =
2359 ps->info.fs.writes_sample_mask ? V_028710_SPI_SHADER_32_ABGR :
2360 ps->info.fs.writes_stencil ? V_028710_SPI_SHADER_32_GR :
2361 ps->info.fs.writes_z ? V_028710_SPI_SHADER_32_R :
2362 V_028710_SPI_SHADER_ZERO;
2363
2364 calculate_vgt_gs_mode(pipeline);
2365 calculate_pa_cl_vs_out_cntl(pipeline);
2366 calculate_ps_inputs(pipeline);
2367
2368 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
2369 if (pipeline->shaders[i]) {
2370 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
2371 }
2372 }
2373
2374 uint32_t stages = 0;
2375 if (radv_pipeline_has_tess(pipeline)) {
2376 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2377 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
2378
2379 if (radv_pipeline_has_gs(pipeline))
2380 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
2381 S_028B54_GS_EN(1) |
2382 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2383 else
2384 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2385
2386 } else if (radv_pipeline_has_gs(pipeline))
2387 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
2388 S_028B54_GS_EN(1) |
2389 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2390
2391 if (device->physical_device->rad_info.chip_class >= GFX9)
2392 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
2393
2394 pipeline->graphics.vgt_shader_stages_en = stages;
2395
2396 if (radv_pipeline_has_gs(pipeline))
2397 calculate_gs_ring_sizes(pipeline);
2398
2399 if (radv_pipeline_has_tess(pipeline)) {
2400 if (pipeline->graphics.prim == V_008958_DI_PT_PATCH) {
2401 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
2402 pipeline->graphics.prim_vertex_count.incr = 1;
2403 }
2404 calculate_tess_state(pipeline, pCreateInfo);
2405 }
2406
2407 const VkPipelineVertexInputStateCreateInfo *vi_info =
2408 pCreateInfo->pVertexInputState;
2409 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
2410 const VkVertexInputAttributeDescription *desc =
2411 &vi_info->pVertexAttributeDescriptions[i];
2412 unsigned loc = desc->location;
2413 const struct vk_format_description *format_desc;
2414 int first_non_void;
2415 uint32_t num_format, data_format;
2416 format_desc = vk_format_description(desc->format);
2417 first_non_void = vk_format_get_first_non_void_channel(desc->format);
2418
2419 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
2420 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
2421
2422 pipeline->va_rsrc_word3[loc] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc->swizzle[0])) |
2423 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc->swizzle[1])) |
2424 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc->swizzle[2])) |
2425 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc->swizzle[3])) |
2426 S_008F0C_NUM_FORMAT(num_format) |
2427 S_008F0C_DATA_FORMAT(data_format);
2428 pipeline->va_format_size[loc] = format_desc->block.bits / 8;
2429 pipeline->va_offset[loc] = desc->offset;
2430 pipeline->va_binding[loc] = desc->binding;
2431 pipeline->num_vertex_attribs = MAX2(pipeline->num_vertex_attribs, loc + 1);
2432 }
2433
2434 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
2435 const VkVertexInputBindingDescription *desc =
2436 &vi_info->pVertexBindingDescriptions[i];
2437
2438 pipeline->binding_stride[desc->binding] = desc->stride;
2439 }
2440
2441 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
2442 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
2443 if (loc->sgpr_idx != -1) {
2444 pipeline->graphics.vtx_base_sgpr = radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
2445 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
2446 if (pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id)
2447 pipeline->graphics.vtx_emit_num = 3;
2448 else
2449 pipeline->graphics.vtx_emit_num = 2;
2450 }
2451 if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
2452 radv_dump_pipeline_stats(device, pipeline);
2453 }
2454
2455 result = radv_pipeline_scratch_init(device, pipeline);
2456 return result;
2457 }
2458
2459 VkResult
2460 radv_graphics_pipeline_create(
2461 VkDevice _device,
2462 VkPipelineCache _cache,
2463 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2464 const struct radv_graphics_pipeline_create_info *extra,
2465 const VkAllocationCallbacks *pAllocator,
2466 VkPipeline *pPipeline)
2467 {
2468 RADV_FROM_HANDLE(radv_device, device, _device);
2469 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
2470 struct radv_pipeline *pipeline;
2471 VkResult result;
2472
2473 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
2474 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2475 if (pipeline == NULL)
2476 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2477
2478 memset(pipeline, 0, sizeof(*pipeline));
2479 result = radv_pipeline_init(pipeline, device, cache,
2480 pCreateInfo, extra, pAllocator);
2481 if (result != VK_SUCCESS) {
2482 radv_pipeline_destroy(device, pipeline, pAllocator);
2483 return result;
2484 }
2485
2486 *pPipeline = radv_pipeline_to_handle(pipeline);
2487
2488 return VK_SUCCESS;
2489 }
2490
2491 VkResult radv_CreateGraphicsPipelines(
2492 VkDevice _device,
2493 VkPipelineCache pipelineCache,
2494 uint32_t count,
2495 const VkGraphicsPipelineCreateInfo* pCreateInfos,
2496 const VkAllocationCallbacks* pAllocator,
2497 VkPipeline* pPipelines)
2498 {
2499 VkResult result = VK_SUCCESS;
2500 unsigned i = 0;
2501
2502 for (; i < count; i++) {
2503 VkResult r;
2504 r = radv_graphics_pipeline_create(_device,
2505 pipelineCache,
2506 &pCreateInfos[i],
2507 NULL, pAllocator, &pPipelines[i]);
2508 if (r != VK_SUCCESS) {
2509 result = r;
2510 pPipelines[i] = VK_NULL_HANDLE;
2511 }
2512 }
2513
2514 return result;
2515 }
2516
2517 static VkResult radv_compute_pipeline_create(
2518 VkDevice _device,
2519 VkPipelineCache _cache,
2520 const VkComputePipelineCreateInfo* pCreateInfo,
2521 const VkAllocationCallbacks* pAllocator,
2522 VkPipeline* pPipeline)
2523 {
2524 RADV_FROM_HANDLE(radv_device, device, _device);
2525 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
2526 RADV_FROM_HANDLE(radv_shader_module, module, pCreateInfo->stage.module);
2527 struct radv_pipeline *pipeline;
2528 VkResult result;
2529
2530 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
2531 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2532 if (pipeline == NULL)
2533 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2534
2535 memset(pipeline, 0, sizeof(*pipeline));
2536 pipeline->device = device;
2537 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
2538
2539 pipeline->shaders[MESA_SHADER_COMPUTE] =
2540 radv_pipeline_compile(pipeline, cache, module,
2541 pCreateInfo->stage.pName,
2542 MESA_SHADER_COMPUTE,
2543 pCreateInfo->stage.pSpecializationInfo,
2544 pipeline->layout, NULL);
2545
2546
2547 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
2548 result = radv_pipeline_scratch_init(device, pipeline);
2549 if (result != VK_SUCCESS) {
2550 radv_pipeline_destroy(device, pipeline, pAllocator);
2551 return result;
2552 }
2553
2554 *pPipeline = radv_pipeline_to_handle(pipeline);
2555
2556 if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
2557 radv_dump_pipeline_stats(device, pipeline);
2558 }
2559 return VK_SUCCESS;
2560 }
2561 VkResult radv_CreateComputePipelines(
2562 VkDevice _device,
2563 VkPipelineCache pipelineCache,
2564 uint32_t count,
2565 const VkComputePipelineCreateInfo* pCreateInfos,
2566 const VkAllocationCallbacks* pAllocator,
2567 VkPipeline* pPipelines)
2568 {
2569 VkResult result = VK_SUCCESS;
2570
2571 unsigned i = 0;
2572 for (; i < count; i++) {
2573 VkResult r;
2574 r = radv_compute_pipeline_create(_device, pipelineCache,
2575 &pCreateInfos[i],
2576 pAllocator, &pPipelines[i]);
2577 if (r != VK_SUCCESS) {
2578 result = r;
2579 pPipelines[i] = VK_NULL_HANDLE;
2580 }
2581 }
2582
2583 return result;
2584 }
2585
2586 void *radv_alloc_shader_memory(struct radv_device *device,
2587 struct radv_shader_variant *shader)
2588 {
2589 mtx_lock(&device->shader_slab_mutex);
2590 list_for_each_entry(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
2591 uint64_t offset = 0;
2592 list_for_each_entry(struct radv_shader_variant, s, &slab->shaders, slab_list) {
2593 if (s->bo_offset - offset >= shader->code_size) {
2594 shader->bo = slab->bo;
2595 shader->bo_offset = offset;
2596 list_addtail(&shader->slab_list, &s->slab_list);
2597 mtx_unlock(&device->shader_slab_mutex);
2598 return slab->ptr + offset;
2599 }
2600 offset = align_u64(s->bo_offset + s->code_size, 256);
2601 }
2602 if (slab->size - offset >= shader->code_size) {
2603 shader->bo = slab->bo;
2604 shader->bo_offset = offset;
2605 list_addtail(&shader->slab_list, &slab->shaders);
2606 mtx_unlock(&device->shader_slab_mutex);
2607 return slab->ptr + offset;
2608 }
2609 }
2610
2611 mtx_unlock(&device->shader_slab_mutex);
2612 struct radv_shader_slab *slab = calloc(1, sizeof(struct radv_shader_slab));
2613
2614 slab->size = 256 * 1024;
2615 slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
2616 RADEON_DOMAIN_VRAM, 0);
2617 slab->ptr = (char*)device->ws->buffer_map(slab->bo);
2618 list_inithead(&slab->shaders);
2619
2620 mtx_lock(&device->shader_slab_mutex);
2621 list_add(&slab->slabs, &device->shader_slabs);
2622
2623 shader->bo = slab->bo;
2624 shader->bo_offset = 0;
2625 list_add(&shader->slab_list, &slab->shaders);
2626 mtx_unlock(&device->shader_slab_mutex);
2627 return slab->ptr;
2628 }
2629
2630 void radv_destroy_shader_slabs(struct radv_device *device)
2631 {
2632 list_for_each_entry_safe(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
2633 device->ws->buffer_destroy(slab->bo);
2634 free(slab);
2635 }
2636 mtx_destroy(&device->shader_slab_mutex);
2637 }