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radv: Enable VK_KHR_shader_draw_parameters.
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "radv_private.h"
30 #include "nir/nir.h"
31 #include "nir/nir_builder.h"
32 #include "spirv/nir_spirv.h"
33
34 #include <llvm-c/Core.h>
35 #include <llvm-c/TargetMachine.h>
36
37 #include "sid.h"
38 #include "r600d_common.h"
39 #include "ac_binary.h"
40 #include "ac_llvm_util.h"
41 #include "ac_nir_to_llvm.h"
42 #include "vk_format.h"
43 #include "util/debug.h"
44 void radv_shader_variant_destroy(struct radv_device *device,
45 struct radv_shader_variant *variant);
46
47 static const struct nir_shader_compiler_options nir_options = {
48 .vertex_id_zero_based = true,
49 .lower_scmp = true,
50 .lower_flrp32 = true,
51 .lower_fsat = true,
52 .lower_pack_snorm_2x16 = true,
53 .lower_pack_snorm_4x8 = true,
54 .lower_pack_unorm_2x16 = true,
55 .lower_pack_unorm_4x8 = true,
56 .lower_unpack_snorm_2x16 = true,
57 .lower_unpack_snorm_4x8 = true,
58 .lower_unpack_unorm_2x16 = true,
59 .lower_unpack_unorm_4x8 = true,
60 .lower_extract_byte = true,
61 .lower_extract_word = true,
62 };
63
64 VkResult radv_CreateShaderModule(
65 VkDevice _device,
66 const VkShaderModuleCreateInfo* pCreateInfo,
67 const VkAllocationCallbacks* pAllocator,
68 VkShaderModule* pShaderModule)
69 {
70 RADV_FROM_HANDLE(radv_device, device, _device);
71 struct radv_shader_module *module;
72
73 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
74 assert(pCreateInfo->flags == 0);
75
76 module = vk_alloc2(&device->alloc, pAllocator,
77 sizeof(*module) + pCreateInfo->codeSize, 8,
78 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
79 if (module == NULL)
80 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
81
82 module->nir = NULL;
83 module->size = pCreateInfo->codeSize;
84 memcpy(module->data, pCreateInfo->pCode, module->size);
85
86 _mesa_sha1_compute(module->data, module->size, module->sha1);
87
88 *pShaderModule = radv_shader_module_to_handle(module);
89
90 return VK_SUCCESS;
91 }
92
93 void radv_DestroyShaderModule(
94 VkDevice _device,
95 VkShaderModule _module,
96 const VkAllocationCallbacks* pAllocator)
97 {
98 RADV_FROM_HANDLE(radv_device, device, _device);
99 RADV_FROM_HANDLE(radv_shader_module, module, _module);
100
101 if (!module)
102 return;
103
104 vk_free2(&device->alloc, pAllocator, module);
105 }
106
107
108 static void
109 radv_pipeline_destroy(struct radv_device *device,
110 struct radv_pipeline *pipeline,
111 const VkAllocationCallbacks* allocator)
112 {
113 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
114 if (pipeline->shaders[i])
115 radv_shader_variant_destroy(device, pipeline->shaders[i]);
116
117 if (pipeline->gs_copy_shader)
118 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
119
120 vk_free2(&device->alloc, allocator, pipeline);
121 }
122
123 void radv_DestroyPipeline(
124 VkDevice _device,
125 VkPipeline _pipeline,
126 const VkAllocationCallbacks* pAllocator)
127 {
128 RADV_FROM_HANDLE(radv_device, device, _device);
129 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
130
131 if (!_pipeline)
132 return;
133
134 radv_pipeline_destroy(device, pipeline, pAllocator);
135 }
136
137
138 static void
139 radv_optimize_nir(struct nir_shader *shader)
140 {
141 bool progress;
142
143 do {
144 progress = false;
145
146 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
147 NIR_PASS_V(shader, nir_lower_alu_to_scalar);
148 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
149
150 NIR_PASS(progress, shader, nir_copy_prop);
151 NIR_PASS(progress, shader, nir_opt_remove_phis);
152 NIR_PASS(progress, shader, nir_opt_dce);
153 NIR_PASS(progress, shader, nir_opt_dead_cf);
154 NIR_PASS(progress, shader, nir_opt_cse);
155 NIR_PASS(progress, shader, nir_opt_peephole_select, 8);
156 NIR_PASS(progress, shader, nir_opt_algebraic);
157 NIR_PASS(progress, shader, nir_opt_constant_folding);
158 NIR_PASS(progress, shader, nir_opt_undef);
159 NIR_PASS(progress, shader, nir_opt_conditional_discard);
160 } while (progress);
161 }
162
163 static nir_shader *
164 radv_shader_compile_to_nir(struct radv_device *device,
165 struct radv_shader_module *module,
166 const char *entrypoint_name,
167 gl_shader_stage stage,
168 const VkSpecializationInfo *spec_info,
169 bool dump)
170 {
171 if (strcmp(entrypoint_name, "main") != 0) {
172 radv_finishme("Multiple shaders per module not really supported");
173 }
174
175 nir_shader *nir;
176 nir_function *entry_point;
177 if (module->nir) {
178 /* Some things such as our meta clear/blit code will give us a NIR
179 * shader directly. In that case, we just ignore the SPIR-V entirely
180 * and just use the NIR shader */
181 nir = module->nir;
182 nir->options = &nir_options;
183 nir_validate_shader(nir);
184
185 assert(exec_list_length(&nir->functions) == 1);
186 struct exec_node *node = exec_list_get_head(&nir->functions);
187 entry_point = exec_node_data(nir_function, node, node);
188 } else {
189 uint32_t *spirv = (uint32_t *) module->data;
190 assert(module->size % 4 == 0);
191
192 uint32_t num_spec_entries = 0;
193 struct nir_spirv_specialization *spec_entries = NULL;
194 if (spec_info && spec_info->mapEntryCount > 0) {
195 num_spec_entries = spec_info->mapEntryCount;
196 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
197 for (uint32_t i = 0; i < num_spec_entries; i++) {
198 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
199 const void *data = spec_info->pData + entry.offset;
200 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
201
202 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
203 if (spec_info->dataSize == 8)
204 spec_entries[i].data64 = *(const uint64_t *)data;
205 else
206 spec_entries[i].data32 = *(const uint32_t *)data;
207 }
208 }
209 const struct nir_spirv_supported_extensions supported_ext = {
210 .draw_parameters = true,
211 .float64 = true
212 };
213 entry_point = spirv_to_nir(spirv, module->size / 4,
214 spec_entries, num_spec_entries,
215 stage, entrypoint_name, &supported_ext, &nir_options);
216 nir = entry_point->shader;
217 assert(nir->stage == stage);
218 nir_validate_shader(nir);
219
220 free(spec_entries);
221
222 /* We have to lower away local constant initializers right before we
223 * inline functions. That way they get properly initialized at the top
224 * of the function and not at the top of its caller.
225 */
226 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_local);
227 NIR_PASS_V(nir, nir_lower_returns);
228 NIR_PASS_V(nir, nir_inline_functions);
229
230 /* Pick off the single entrypoint that we want */
231 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
232 if (func != entry_point)
233 exec_node_remove(&func->node);
234 }
235 assert(exec_list_length(&nir->functions) == 1);
236 entry_point->name = ralloc_strdup(entry_point, "main");
237
238 NIR_PASS_V(nir, nir_remove_dead_variables,
239 nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
240
241 /* Now that we've deleted all but the main function, we can go ahead and
242 * lower the rest of the constant initializers.
243 */
244 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
245 NIR_PASS_V(nir, nir_lower_system_values);
246 }
247
248 /* Vulkan uses the separate-shader linking model */
249 nir->info->separate_shader = true;
250
251 // nir = brw_preprocess_nir(compiler, nir);
252
253 nir_shader_gather_info(nir, entry_point->impl);
254
255 nir_variable_mode indirect_mask = 0;
256 // if (compiler->glsl_compiler_options[stage].EmitNoIndirectInput)
257 indirect_mask |= nir_var_shader_in;
258 // if (compiler->glsl_compiler_options[stage].EmitNoIndirectTemp)
259 indirect_mask |= nir_var_local;
260
261 nir_lower_indirect_derefs(nir, indirect_mask);
262
263 static const nir_lower_tex_options tex_options = {
264 .lower_txp = ~0,
265 };
266
267 nir_lower_tex(nir, &tex_options);
268
269 nir_lower_vars_to_ssa(nir);
270 nir_lower_var_copies(nir);
271 nir_lower_global_vars_to_local(nir);
272 nir_remove_dead_variables(nir, nir_var_local);
273 radv_optimize_nir(nir);
274
275 if (dump)
276 nir_print_shader(nir, stderr);
277
278 return nir;
279 }
280
281 static const char *radv_get_shader_name(struct radv_shader_variant *var,
282 gl_shader_stage stage)
283 {
284 switch (stage) {
285 case MESA_SHADER_VERTEX: return var->info.vs.as_es ? "Vertex Shader as ES" : "Vertex Shader as VS";
286 case MESA_SHADER_GEOMETRY: return "Geometry Shader";
287 case MESA_SHADER_FRAGMENT: return "Pixel Shader";
288 case MESA_SHADER_COMPUTE: return "Compute Shader";
289 default:
290 return "Unknown shader";
291 };
292
293 }
294 static void radv_dump_pipeline_stats(struct radv_device *device, struct radv_pipeline *pipeline)
295 {
296 unsigned lds_increment = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
297 struct radv_shader_variant *var;
298 struct ac_shader_config *conf;
299 int i;
300 FILE *file = stderr;
301 unsigned max_simd_waves = 10;
302 unsigned lds_per_wave = 0;
303
304 for (i = 0; i < MESA_SHADER_STAGES; i++) {
305 if (!pipeline->shaders[i])
306 continue;
307 var = pipeline->shaders[i];
308
309 conf = &var->config;
310
311 if (i == MESA_SHADER_FRAGMENT) {
312 lds_per_wave = conf->lds_size * lds_increment +
313 align(var->info.fs.num_interp * 48, lds_increment);
314 }
315
316 if (conf->num_sgprs) {
317 if (device->physical_device->rad_info.chip_class >= VI)
318 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
319 else
320 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
321 }
322
323 if (conf->num_vgprs)
324 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
325
326 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
327 * that PS can use.
328 */
329 if (lds_per_wave)
330 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
331
332 fprintf(file, "\n%s:\n",
333 radv_get_shader_name(var, i));
334 if (i == MESA_SHADER_FRAGMENT) {
335 fprintf(file, "*** SHADER CONFIG ***\n"
336 "SPI_PS_INPUT_ADDR = 0x%04x\n"
337 "SPI_PS_INPUT_ENA = 0x%04x\n",
338 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
339 }
340 fprintf(file, "*** SHADER STATS ***\n"
341 "SGPRS: %d\n"
342 "VGPRS: %d\n"
343 "Spilled SGPRs: %d\n"
344 "Spilled VGPRs: %d\n"
345 "Code Size: %d bytes\n"
346 "LDS: %d blocks\n"
347 "Scratch: %d bytes per wave\n"
348 "Max Waves: %d\n"
349 "********************\n\n\n",
350 conf->num_sgprs, conf->num_vgprs,
351 conf->spilled_sgprs, conf->spilled_vgprs, var->code_size,
352 conf->lds_size, conf->scratch_bytes_per_wave,
353 max_simd_waves);
354 }
355 }
356
357 void radv_shader_variant_destroy(struct radv_device *device,
358 struct radv_shader_variant *variant)
359 {
360 if (__sync_fetch_and_sub(&variant->ref_count, 1) != 1)
361 return;
362
363 device->ws->buffer_destroy(variant->bo);
364 free(variant);
365 }
366
367 static void radv_fill_shader_variant(struct radv_device *device,
368 struct radv_shader_variant *variant,
369 struct ac_shader_binary *binary,
370 gl_shader_stage stage)
371 {
372 bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0;
373 unsigned vgpr_comp_cnt = 0;
374
375 if (scratch_enabled && !device->llvm_supports_spill)
376 radv_finishme("shader scratch support only available with LLVM 4.0");
377
378 variant->code_size = binary->code_size;
379
380 switch (stage) {
381 case MESA_SHADER_VERTEX:
382 case MESA_SHADER_GEOMETRY:
383 variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
384 S_00B12C_SCRATCH_EN(scratch_enabled);
385 vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
386 break;
387 case MESA_SHADER_FRAGMENT:
388 variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
389 S_00B12C_SCRATCH_EN(scratch_enabled);
390 break;
391 case MESA_SHADER_COMPUTE:
392 variant->rsrc2 = S_00B84C_USER_SGPR(variant->info.num_user_sgprs) |
393 S_00B84C_SCRATCH_EN(scratch_enabled) |
394 S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) |
395 S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) |
396 S_00B84C_TG_SIZE_EN(1) |
397 S_00B84C_LDS_SIZE(variant->config.lds_size);
398 break;
399 default:
400 unreachable("unsupported shader type");
401 break;
402 }
403
404 variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
405 S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) |
406 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
407 S_00B848_DX10_CLAMP(1) |
408 S_00B848_FLOAT_MODE(variant->config.float_mode);
409
410 variant->bo = device->ws->buffer_create(device->ws, binary->code_size, 256,
411 RADEON_DOMAIN_GTT, RADEON_FLAG_CPU_ACCESS);
412
413 void *ptr = device->ws->buffer_map(variant->bo);
414 memcpy(ptr, binary->code, binary->code_size);
415 device->ws->buffer_unmap(variant->bo);
416
417
418 }
419
420 static struct radv_shader_variant *radv_shader_variant_create(struct radv_device *device,
421 struct nir_shader *shader,
422 struct radv_pipeline_layout *layout,
423 const union ac_shader_variant_key *key,
424 void** code_out,
425 unsigned *code_size_out,
426 bool dump)
427 {
428 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
429 enum radeon_family chip_family = device->physical_device->rad_info.family;
430 LLVMTargetMachineRef tm;
431 if (!variant)
432 return NULL;
433
434 struct ac_nir_compiler_options options = {0};
435 options.layout = layout;
436 if (key)
437 options.key = *key;
438
439 struct ac_shader_binary binary;
440
441 options.unsafe_math = !!(device->debug_flags & RADV_DEBUG_UNSAFE_MATH);
442 options.family = chip_family;
443 options.chip_class = device->physical_device->rad_info.chip_class;
444 options.supports_spill = device->llvm_supports_spill;
445 tm = ac_create_target_machine(chip_family, options.supports_spill);
446 ac_compile_nir_shader(tm, &binary, &variant->config,
447 &variant->info, shader, &options, dump);
448 LLVMDisposeTargetMachine(tm);
449
450 radv_fill_shader_variant(device, variant, &binary, shader->stage);
451
452 if (code_out) {
453 *code_out = binary.code;
454 *code_size_out = binary.code_size;
455 } else
456 free(binary.code);
457 free(binary.config);
458 free(binary.rodata);
459 free(binary.global_symbol_offsets);
460 free(binary.relocs);
461 free(binary.disasm_string);
462 variant->ref_count = 1;
463 return variant;
464 }
465
466 static struct radv_shader_variant *
467 radv_pipeline_create_gs_copy_shader(struct radv_pipeline *pipeline,
468 struct nir_shader *nir,
469 void** code_out,
470 unsigned *code_size_out,
471 bool dump_shader)
472 {
473 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
474 enum radeon_family chip_family = pipeline->device->physical_device->rad_info.family;
475 LLVMTargetMachineRef tm;
476 if (!variant)
477 return NULL;
478
479 struct ac_nir_compiler_options options = {0};
480 struct ac_shader_binary binary;
481 options.family = chip_family;
482 options.chip_class = pipeline->device->physical_device->rad_info.chip_class;
483 options.supports_spill = pipeline->device->llvm_supports_spill;
484 tm = ac_create_target_machine(chip_family, options.supports_spill);
485 ac_create_gs_copy_shader(tm, nir, &binary, &variant->config, &variant->info, &options, dump_shader);
486 LLVMDisposeTargetMachine(tm);
487
488 radv_fill_shader_variant(pipeline->device, variant, &binary, MESA_SHADER_VERTEX);
489
490 if (code_out) {
491 *code_out = binary.code;
492 *code_size_out = binary.code_size;
493 } else
494 free(binary.code);
495 free(binary.config);
496 free(binary.rodata);
497 free(binary.global_symbol_offsets);
498 free(binary.relocs);
499 free(binary.disasm_string);
500 variant->ref_count = 1;
501 return variant;
502 }
503
504 static struct radv_shader_variant *
505 radv_pipeline_compile(struct radv_pipeline *pipeline,
506 struct radv_pipeline_cache *cache,
507 struct radv_shader_module *module,
508 const char *entrypoint,
509 gl_shader_stage stage,
510 const VkSpecializationInfo *spec_info,
511 struct radv_pipeline_layout *layout,
512 const union ac_shader_variant_key *key)
513 {
514 unsigned char sha1[20];
515 unsigned char gs_copy_sha1[20];
516 struct radv_shader_variant *variant;
517 nir_shader *nir;
518 void *code = NULL;
519 unsigned code_size = 0;
520 bool dump = (pipeline->device->debug_flags & RADV_DEBUG_DUMP_SHADERS);
521
522 if (module->nir)
523 _mesa_sha1_compute(module->nir->info->name,
524 strlen(module->nir->info->name),
525 module->sha1);
526
527 radv_hash_shader(sha1, module, entrypoint, spec_info, layout, key, 0);
528 if (stage == MESA_SHADER_GEOMETRY)
529 radv_hash_shader(gs_copy_sha1, module, entrypoint, spec_info,
530 layout, key, 1);
531
532 if (cache) {
533 variant = radv_create_shader_variant_from_pipeline_cache(pipeline->device,
534 cache,
535 sha1);
536
537 if (stage == MESA_SHADER_GEOMETRY) {
538 pipeline->gs_copy_shader =
539 radv_create_shader_variant_from_pipeline_cache(
540 pipeline->device,
541 cache,
542 gs_copy_sha1);
543 }
544 if (variant)
545 return variant;
546 }
547
548 nir = radv_shader_compile_to_nir(pipeline->device,
549 module, entrypoint, stage,
550 spec_info, dump);
551 if (nir == NULL)
552 return NULL;
553
554 variant = radv_shader_variant_create(pipeline->device, nir, layout, key,
555 &code, &code_size, dump);
556
557 if (stage == MESA_SHADER_GEOMETRY) {
558 void *gs_copy_code = NULL;
559 unsigned gs_copy_code_size = 0;
560 pipeline->gs_copy_shader = radv_pipeline_create_gs_copy_shader(
561 pipeline, nir, &gs_copy_code, &gs_copy_code_size, dump);
562
563 if (pipeline->gs_copy_shader && cache) {
564 pipeline->gs_copy_shader =
565 radv_pipeline_cache_insert_shader(cache,
566 gs_copy_sha1,
567 pipeline->gs_copy_shader,
568 gs_copy_code,
569 gs_copy_code_size);
570 }
571 }
572 if (!module->nir)
573 ralloc_free(nir);
574
575 if (variant && cache)
576 variant = radv_pipeline_cache_insert_shader(cache, sha1, variant,
577 code, code_size);
578
579 if (code)
580 free(code);
581 return variant;
582 }
583
584 static VkResult
585 radv_pipeline_scratch_init(struct radv_device *device,
586 struct radv_pipeline *pipeline)
587 {
588 unsigned scratch_bytes_per_wave = 0;
589 unsigned max_waves = 0;
590 unsigned min_waves = 1;
591
592 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
593 if (pipeline->shaders[i]) {
594 unsigned max_stage_waves = device->scratch_waves;
595
596 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
597 pipeline->shaders[i]->config.scratch_bytes_per_wave);
598
599 max_stage_waves = MIN2(max_stage_waves,
600 4 * device->physical_device->rad_info.num_good_compute_units *
601 (256 / pipeline->shaders[i]->config.num_vgprs));
602 max_waves = MAX2(max_waves, max_stage_waves);
603 }
604 }
605
606 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
607 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
608 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
609 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
610 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
611 }
612
613 if (scratch_bytes_per_wave)
614 max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave);
615
616 if (scratch_bytes_per_wave && max_waves < min_waves) {
617 /* Not really true at this moment, but will be true on first
618 * execution. Avoid having hanging shaders. */
619 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
620 }
621 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
622 pipeline->max_waves = max_waves;
623 return VK_SUCCESS;
624 }
625
626 static uint32_t si_translate_blend_function(VkBlendOp op)
627 {
628 switch (op) {
629 case VK_BLEND_OP_ADD:
630 return V_028780_COMB_DST_PLUS_SRC;
631 case VK_BLEND_OP_SUBTRACT:
632 return V_028780_COMB_SRC_MINUS_DST;
633 case VK_BLEND_OP_REVERSE_SUBTRACT:
634 return V_028780_COMB_DST_MINUS_SRC;
635 case VK_BLEND_OP_MIN:
636 return V_028780_COMB_MIN_DST_SRC;
637 case VK_BLEND_OP_MAX:
638 return V_028780_COMB_MAX_DST_SRC;
639 default:
640 return 0;
641 }
642 }
643
644 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
645 {
646 switch (factor) {
647 case VK_BLEND_FACTOR_ZERO:
648 return V_028780_BLEND_ZERO;
649 case VK_BLEND_FACTOR_ONE:
650 return V_028780_BLEND_ONE;
651 case VK_BLEND_FACTOR_SRC_COLOR:
652 return V_028780_BLEND_SRC_COLOR;
653 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
654 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
655 case VK_BLEND_FACTOR_DST_COLOR:
656 return V_028780_BLEND_DST_COLOR;
657 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
658 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
659 case VK_BLEND_FACTOR_SRC_ALPHA:
660 return V_028780_BLEND_SRC_ALPHA;
661 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
662 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
663 case VK_BLEND_FACTOR_DST_ALPHA:
664 return V_028780_BLEND_DST_ALPHA;
665 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
666 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
667 case VK_BLEND_FACTOR_CONSTANT_COLOR:
668 return V_028780_BLEND_CONSTANT_COLOR;
669 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
670 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
671 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
672 return V_028780_BLEND_CONSTANT_ALPHA;
673 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
674 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
675 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
676 return V_028780_BLEND_SRC_ALPHA_SATURATE;
677 case VK_BLEND_FACTOR_SRC1_COLOR:
678 return V_028780_BLEND_SRC1_COLOR;
679 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
680 return V_028780_BLEND_INV_SRC1_COLOR;
681 case VK_BLEND_FACTOR_SRC1_ALPHA:
682 return V_028780_BLEND_SRC1_ALPHA;
683 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
684 return V_028780_BLEND_INV_SRC1_ALPHA;
685 default:
686 return 0;
687 }
688 }
689
690 static bool is_dual_src(VkBlendFactor factor)
691 {
692 switch (factor) {
693 case VK_BLEND_FACTOR_SRC1_COLOR:
694 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
695 case VK_BLEND_FACTOR_SRC1_ALPHA:
696 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
697 return true;
698 default:
699 return false;
700 }
701 }
702
703 static unsigned si_choose_spi_color_format(VkFormat vk_format,
704 bool blend_enable,
705 bool blend_need_alpha)
706 {
707 const struct vk_format_description *desc = vk_format_description(vk_format);
708 unsigned format, ntype, swap;
709
710 /* Alpha is needed for alpha-to-coverage.
711 * Blending may be with or without alpha.
712 */
713 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
714 unsigned alpha = 0; /* exports alpha, but may not support blending */
715 unsigned blend = 0; /* supports blending, but may not export alpha */
716 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
717
718 format = radv_translate_colorformat(vk_format);
719 ntype = radv_translate_color_numformat(vk_format, desc,
720 vk_format_get_first_non_void_channel(vk_format));
721 swap = radv_translate_colorswap(vk_format, false);
722
723 /* Choose the SPI color formats. These are required values for Stoney/RB+.
724 * Other chips have multiple choices, though they are not necessarily better.
725 */
726 switch (format) {
727 case V_028C70_COLOR_5_6_5:
728 case V_028C70_COLOR_1_5_5_5:
729 case V_028C70_COLOR_5_5_5_1:
730 case V_028C70_COLOR_4_4_4_4:
731 case V_028C70_COLOR_10_11_11:
732 case V_028C70_COLOR_11_11_10:
733 case V_028C70_COLOR_8:
734 case V_028C70_COLOR_8_8:
735 case V_028C70_COLOR_8_8_8_8:
736 case V_028C70_COLOR_10_10_10_2:
737 case V_028C70_COLOR_2_10_10_10:
738 if (ntype == V_028C70_NUMBER_UINT)
739 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
740 else if (ntype == V_028C70_NUMBER_SINT)
741 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
742 else
743 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
744 break;
745
746 case V_028C70_COLOR_16:
747 case V_028C70_COLOR_16_16:
748 case V_028C70_COLOR_16_16_16_16:
749 if (ntype == V_028C70_NUMBER_UNORM ||
750 ntype == V_028C70_NUMBER_SNORM) {
751 /* UNORM16 and SNORM16 don't support blending */
752 if (ntype == V_028C70_NUMBER_UNORM)
753 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
754 else
755 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
756
757 /* Use 32 bits per channel for blending. */
758 if (format == V_028C70_COLOR_16) {
759 if (swap == V_028C70_SWAP_STD) { /* R */
760 blend = V_028714_SPI_SHADER_32_R;
761 blend_alpha = V_028714_SPI_SHADER_32_AR;
762 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
763 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
764 else
765 assert(0);
766 } else if (format == V_028C70_COLOR_16_16) {
767 if (swap == V_028C70_SWAP_STD) { /* RG */
768 blend = V_028714_SPI_SHADER_32_GR;
769 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
770 } else if (swap == V_028C70_SWAP_ALT) /* RA */
771 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
772 else
773 assert(0);
774 } else /* 16_16_16_16 */
775 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
776 } else if (ntype == V_028C70_NUMBER_UINT)
777 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
778 else if (ntype == V_028C70_NUMBER_SINT)
779 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
780 else if (ntype == V_028C70_NUMBER_FLOAT)
781 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
782 else
783 assert(0);
784 break;
785
786 case V_028C70_COLOR_32:
787 if (swap == V_028C70_SWAP_STD) { /* R */
788 blend = normal = V_028714_SPI_SHADER_32_R;
789 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
790 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
791 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
792 else
793 assert(0);
794 break;
795
796 case V_028C70_COLOR_32_32:
797 if (swap == V_028C70_SWAP_STD) { /* RG */
798 blend = normal = V_028714_SPI_SHADER_32_GR;
799 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
800 } else if (swap == V_028C70_SWAP_ALT) /* RA */
801 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
802 else
803 assert(0);
804 break;
805
806 case V_028C70_COLOR_32_32_32_32:
807 case V_028C70_COLOR_8_24:
808 case V_028C70_COLOR_24_8:
809 case V_028C70_COLOR_X24_8_32_FLOAT:
810 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
811 break;
812
813 default:
814 unreachable("unhandled blend format");
815 }
816
817 if (blend_enable && blend_need_alpha)
818 return blend_alpha;
819 else if(blend_need_alpha)
820 return alpha;
821 else if(blend_enable)
822 return blend;
823 else
824 return normal;
825 }
826
827 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
828 {
829 unsigned i, cb_shader_mask = 0;
830
831 for (i = 0; i < 8; i++) {
832 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
833 case V_028714_SPI_SHADER_ZERO:
834 break;
835 case V_028714_SPI_SHADER_32_R:
836 cb_shader_mask |= 0x1 << (i * 4);
837 break;
838 case V_028714_SPI_SHADER_32_GR:
839 cb_shader_mask |= 0x3 << (i * 4);
840 break;
841 case V_028714_SPI_SHADER_32_AR:
842 cb_shader_mask |= 0x9 << (i * 4);
843 break;
844 case V_028714_SPI_SHADER_FP16_ABGR:
845 case V_028714_SPI_SHADER_UNORM16_ABGR:
846 case V_028714_SPI_SHADER_SNORM16_ABGR:
847 case V_028714_SPI_SHADER_UINT16_ABGR:
848 case V_028714_SPI_SHADER_SINT16_ABGR:
849 case V_028714_SPI_SHADER_32_ABGR:
850 cb_shader_mask |= 0xf << (i * 4);
851 break;
852 default:
853 assert(0);
854 }
855 }
856 return cb_shader_mask;
857 }
858
859 static void
860 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
861 const VkGraphicsPipelineCreateInfo *pCreateInfo,
862 uint32_t blend_enable,
863 uint32_t blend_need_alpha,
864 bool single_cb_enable,
865 bool blend_mrt0_is_dual_src)
866 {
867 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
868 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
869 struct radv_blend_state *blend = &pipeline->graphics.blend;
870 unsigned col_format = 0;
871
872 for (unsigned i = 0; i < (single_cb_enable ? 1 : subpass->color_count); ++i) {
873 struct radv_render_pass_attachment *attachment;
874 unsigned cf;
875
876 attachment = pass->attachments + subpass->color_attachments[i].attachment;
877
878 cf = si_choose_spi_color_format(attachment->format,
879 blend_enable & (1 << i),
880 blend_need_alpha & (1 << i));
881
882 col_format |= cf << (4 * i);
883 }
884
885 blend->cb_shader_mask = si_get_cb_shader_mask(col_format);
886
887 if (blend_mrt0_is_dual_src)
888 col_format |= (col_format & 0xf) << 4;
889 if (!col_format)
890 col_format |= V_028714_SPI_SHADER_32_R;
891 blend->spi_shader_col_format = col_format;
892 }
893
894 static bool
895 format_is_int8(VkFormat format)
896 {
897 const struct vk_format_description *desc = vk_format_description(format);
898 int channel = vk_format_get_first_non_void_channel(format);
899
900 return channel >= 0 && desc->channel[channel].pure_integer &&
901 desc->channel[channel].size == 8;
902 }
903
904 unsigned radv_format_meta_fs_key(VkFormat format)
905 {
906 unsigned col_format = si_choose_spi_color_format(format, false, false) - 1;
907 bool is_int8 = format_is_int8(format);
908
909 return col_format + (is_int8 ? 3 : 0);
910 }
911
912 static unsigned
913 radv_pipeline_compute_is_int8(const VkGraphicsPipelineCreateInfo *pCreateInfo)
914 {
915 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
916 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
917 unsigned is_int8 = 0;
918
919 for (unsigned i = 0; i < subpass->color_count; ++i) {
920 struct radv_render_pass_attachment *attachment;
921
922 attachment = pass->attachments + subpass->color_attachments[i].attachment;
923
924 if (format_is_int8(attachment->format))
925 is_int8 |= 1 << i;
926 }
927
928 return is_int8;
929 }
930
931 static void
932 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
933 const VkGraphicsPipelineCreateInfo *pCreateInfo,
934 const struct radv_graphics_pipeline_create_info *extra)
935 {
936 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
937 struct radv_blend_state *blend = &pipeline->graphics.blend;
938 unsigned mode = V_028808_CB_NORMAL;
939 uint32_t blend_enable = 0, blend_need_alpha = 0;
940 bool blend_mrt0_is_dual_src = false;
941 int i;
942 bool single_cb_enable = false;
943
944 if (!vkblend)
945 return;
946
947 if (extra && extra->custom_blend_mode) {
948 single_cb_enable = true;
949 mode = extra->custom_blend_mode;
950 }
951 blend->cb_color_control = 0;
952 if (vkblend->logicOpEnable)
953 blend->cb_color_control |= S_028808_ROP3(vkblend->logicOp | (vkblend->logicOp << 4));
954 else
955 blend->cb_color_control |= S_028808_ROP3(0xcc);
956
957 blend->db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
958 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
959 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
960 S_028B70_ALPHA_TO_MASK_OFFSET3(2);
961
962 blend->cb_target_mask = 0;
963 for (i = 0; i < vkblend->attachmentCount; i++) {
964 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
965 unsigned blend_cntl = 0;
966 VkBlendOp eqRGB = att->colorBlendOp;
967 VkBlendFactor srcRGB = att->srcColorBlendFactor;
968 VkBlendFactor dstRGB = att->dstColorBlendFactor;
969 VkBlendOp eqA = att->alphaBlendOp;
970 VkBlendFactor srcA = att->srcAlphaBlendFactor;
971 VkBlendFactor dstA = att->dstAlphaBlendFactor;
972
973 blend->sx_mrt0_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
974
975 if (!att->colorWriteMask)
976 continue;
977
978 blend->cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
979 if (!att->blendEnable) {
980 blend->cb_blend_control[i] = blend_cntl;
981 continue;
982 }
983
984 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
985 if (i == 0)
986 blend_mrt0_is_dual_src = true;
987
988 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
989 srcRGB = VK_BLEND_FACTOR_ONE;
990 dstRGB = VK_BLEND_FACTOR_ONE;
991 }
992 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
993 srcA = VK_BLEND_FACTOR_ONE;
994 dstA = VK_BLEND_FACTOR_ONE;
995 }
996
997 blend_cntl |= S_028780_ENABLE(1);
998
999 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
1000 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
1001 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
1002 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
1003 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
1004 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
1005 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
1006 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
1007 }
1008 blend->cb_blend_control[i] = blend_cntl;
1009
1010 blend_enable |= 1 << i;
1011
1012 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
1013 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
1014 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
1015 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
1016 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
1017 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
1018 blend_need_alpha |= 1 << i;
1019 }
1020 for (i = vkblend->attachmentCount; i < 8; i++)
1021 blend->cb_blend_control[i] = 0;
1022
1023 if (blend->cb_target_mask)
1024 blend->cb_color_control |= S_028808_MODE(mode);
1025 else
1026 blend->cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
1027
1028 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo,
1029 blend_enable, blend_need_alpha, single_cb_enable, blend_mrt0_is_dual_src);
1030 }
1031
1032 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
1033 {
1034 switch (op) {
1035 case VK_STENCIL_OP_KEEP:
1036 return V_02842C_STENCIL_KEEP;
1037 case VK_STENCIL_OP_ZERO:
1038 return V_02842C_STENCIL_ZERO;
1039 case VK_STENCIL_OP_REPLACE:
1040 return V_02842C_STENCIL_REPLACE_TEST;
1041 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
1042 return V_02842C_STENCIL_ADD_CLAMP;
1043 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
1044 return V_02842C_STENCIL_SUB_CLAMP;
1045 case VK_STENCIL_OP_INVERT:
1046 return V_02842C_STENCIL_INVERT;
1047 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
1048 return V_02842C_STENCIL_ADD_WRAP;
1049 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
1050 return V_02842C_STENCIL_SUB_WRAP;
1051 default:
1052 return 0;
1053 }
1054 }
1055 static void
1056 radv_pipeline_init_depth_stencil_state(struct radv_pipeline *pipeline,
1057 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1058 const struct radv_graphics_pipeline_create_info *extra)
1059 {
1060 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
1061 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
1062
1063 memset(ds, 0, sizeof(*ds));
1064 if (!vkds)
1065 return;
1066 ds->db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
1067 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
1068 S_028800_ZFUNC(vkds->depthCompareOp) |
1069 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
1070
1071 if (vkds->stencilTestEnable) {
1072 ds->db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
1073 ds->db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
1074 ds->db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
1075 ds->db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
1076 ds->db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
1077
1078 ds->db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
1079 ds->db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
1080 ds->db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
1081 ds->db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
1082 }
1083
1084 if (extra) {
1085
1086 ds->db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
1087 ds->db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
1088
1089 ds->db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
1090 ds->db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
1091 ds->db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
1092 ds->db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
1093 ds->db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
1094 }
1095 }
1096
1097 static uint32_t si_translate_fill(VkPolygonMode func)
1098 {
1099 switch(func) {
1100 case VK_POLYGON_MODE_FILL:
1101 return V_028814_X_DRAW_TRIANGLES;
1102 case VK_POLYGON_MODE_LINE:
1103 return V_028814_X_DRAW_LINES;
1104 case VK_POLYGON_MODE_POINT:
1105 return V_028814_X_DRAW_POINTS;
1106 default:
1107 assert(0);
1108 return V_028814_X_DRAW_POINTS;
1109 }
1110 }
1111 static void
1112 radv_pipeline_init_raster_state(struct radv_pipeline *pipeline,
1113 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1114 {
1115 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
1116 struct radv_raster_state *raster = &pipeline->graphics.raster;
1117
1118 memset(raster, 0, sizeof(*raster));
1119
1120 raster->spi_interp_control =
1121 S_0286D4_FLAT_SHADE_ENA(1) |
1122 S_0286D4_PNT_SPRITE_ENA(1) |
1123 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
1124 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
1125 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
1126 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
1127 S_0286D4_PNT_SPRITE_TOP_1(0); // vulkan is top to bottom - 1.0 at bottom
1128
1129 raster->pa_cl_vs_out_cntl = S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1);
1130 raster->pa_cl_clip_cntl = S_028810_PS_UCP_MODE(3) |
1131 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
1132 S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1133 S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
1134 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
1135 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
1136
1137 raster->pa_su_vtx_cntl =
1138 S_028BE4_PIX_CENTER(1) | // TODO verify
1139 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
1140 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH);
1141
1142 raster->pa_su_sc_mode_cntl =
1143 S_028814_FACE(vkraster->frontFace) |
1144 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
1145 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
1146 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
1147 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1148 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
1149 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1150 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
1151 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0);
1152
1153 }
1154
1155 static void
1156 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1157 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1158 {
1159 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
1160 struct radv_blend_state *blend = &pipeline->graphics.blend;
1161 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1162 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1163 int ps_iter_samples = 1;
1164 uint32_t mask = 0xffff;
1165
1166 ms->num_samples = vkms->rasterizationSamples;
1167
1168 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.force_persample) {
1169 ps_iter_samples = vkms->rasterizationSamples;
1170 }
1171
1172 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1173 ms->pa_sc_aa_config = 0;
1174 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1175 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1176 ms->pa_sc_mode_cntl_1 =
1177 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1178 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1179 /* always 1: */
1180 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1181 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1182 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1183 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1184 EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1185 EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1186
1187 if (vkms->rasterizationSamples > 1) {
1188 unsigned log_samples = util_logbase2(vkms->rasterizationSamples);
1189 unsigned log_ps_iter_samples = util_logbase2(util_next_power_of_two(ps_iter_samples));
1190 ms->pa_sc_mode_cntl_0 = S_028A48_MSAA_ENABLE(1);
1191 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1192 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1193 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1194 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1195 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1196 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1197 S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
1198 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1199 ms->pa_sc_mode_cntl_1 |= EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1200 }
1201
1202 if (vkms->alphaToCoverageEnable)
1203 blend->db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
1204
1205 if (vkms->pSampleMask) {
1206 mask = vkms->pSampleMask[0] & 0xffff;
1207 }
1208
1209 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1210 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1211 }
1212
1213 static uint32_t
1214 si_translate_prim(enum VkPrimitiveTopology topology)
1215 {
1216 switch (topology) {
1217 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1218 return V_008958_DI_PT_POINTLIST;
1219 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1220 return V_008958_DI_PT_LINELIST;
1221 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1222 return V_008958_DI_PT_LINESTRIP;
1223 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1224 return V_008958_DI_PT_TRILIST;
1225 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1226 return V_008958_DI_PT_TRISTRIP;
1227 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1228 return V_008958_DI_PT_TRIFAN;
1229 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1230 return V_008958_DI_PT_LINELIST_ADJ;
1231 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1232 return V_008958_DI_PT_LINESTRIP_ADJ;
1233 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1234 return V_008958_DI_PT_TRILIST_ADJ;
1235 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1236 return V_008958_DI_PT_TRISTRIP_ADJ;
1237 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1238 return V_008958_DI_PT_PATCH;
1239 default:
1240 assert(0);
1241 return 0;
1242 }
1243 }
1244
1245 static uint32_t
1246 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1247 {
1248 switch (gl_prim) {
1249 case 0: /* GL_POINTS */
1250 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1251 case 1: /* GL_LINES */
1252 case 3: /* GL_LINE_STRIP */
1253 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1254 case 0x8E7A: /* GL_ISOLINES */
1255 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1256
1257 case 4: /* GL_TRIANGLES */
1258 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1259 case 5: /* GL_TRIANGLE_STRIP */
1260 case 7: /* GL_QUADS */
1261 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1262 default:
1263 assert(0);
1264 return 0;
1265 }
1266 }
1267
1268 static uint32_t
1269 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1270 {
1271 switch (topology) {
1272 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1273 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1274 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1275 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1276 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1277 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1278 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1279 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1280 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1281 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1282 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1283 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1284 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1285 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1286 default:
1287 assert(0);
1288 return 0;
1289 }
1290 }
1291
1292 static unsigned si_map_swizzle(unsigned swizzle)
1293 {
1294 switch (swizzle) {
1295 case VK_SWIZZLE_Y:
1296 return V_008F0C_SQ_SEL_Y;
1297 case VK_SWIZZLE_Z:
1298 return V_008F0C_SQ_SEL_Z;
1299 case VK_SWIZZLE_W:
1300 return V_008F0C_SQ_SEL_W;
1301 case VK_SWIZZLE_0:
1302 return V_008F0C_SQ_SEL_0;
1303 case VK_SWIZZLE_1:
1304 return V_008F0C_SQ_SEL_1;
1305 default: /* VK_SWIZZLE_X */
1306 return V_008F0C_SQ_SEL_X;
1307 }
1308 }
1309
1310 static void
1311 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1312 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1313 {
1314 radv_cmd_dirty_mask_t states = RADV_CMD_DIRTY_DYNAMIC_ALL;
1315 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1316 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1317
1318 pipeline->dynamic_state = default_dynamic_state;
1319
1320 if (pCreateInfo->pDynamicState) {
1321 /* Remove all of the states that are marked as dynamic */
1322 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1323 for (uint32_t s = 0; s < count; s++)
1324 states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
1325 }
1326
1327 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1328
1329 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1330 *
1331 * pViewportState is [...] NULL if the pipeline
1332 * has rasterization disabled.
1333 */
1334 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
1335 assert(pCreateInfo->pViewportState);
1336
1337 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1338 if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
1339 typed_memcpy(dynamic->viewport.viewports,
1340 pCreateInfo->pViewportState->pViewports,
1341 pCreateInfo->pViewportState->viewportCount);
1342 }
1343
1344 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1345 if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
1346 typed_memcpy(dynamic->scissor.scissors,
1347 pCreateInfo->pViewportState->pScissors,
1348 pCreateInfo->pViewportState->scissorCount);
1349 }
1350 }
1351
1352 if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
1353 assert(pCreateInfo->pRasterizationState);
1354 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1355 }
1356
1357 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
1358 assert(pCreateInfo->pRasterizationState);
1359 dynamic->depth_bias.bias =
1360 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1361 dynamic->depth_bias.clamp =
1362 pCreateInfo->pRasterizationState->depthBiasClamp;
1363 dynamic->depth_bias.slope =
1364 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1365 }
1366
1367 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1368 *
1369 * pColorBlendState is [...] NULL if the pipeline has rasterization
1370 * disabled or if the subpass of the render pass the pipeline is
1371 * created against does not use any color attachments.
1372 */
1373 bool uses_color_att = false;
1374 for (unsigned i = 0; i < subpass->color_count; ++i) {
1375 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
1376 uses_color_att = true;
1377 break;
1378 }
1379 }
1380
1381 if (uses_color_att && states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
1382 assert(pCreateInfo->pColorBlendState);
1383 typed_memcpy(dynamic->blend_constants,
1384 pCreateInfo->pColorBlendState->blendConstants, 4);
1385 }
1386
1387 /* If there is no depthstencil attachment, then don't read
1388 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1389 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1390 * no need to override the depthstencil defaults in
1391 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1392 *
1393 * Section 9.2 of the Vulkan 1.0.15 spec says:
1394 *
1395 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1396 * disabled or if the subpass of the render pass the pipeline is created
1397 * against does not use a depth/stencil attachment.
1398 */
1399 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
1400 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1401 assert(pCreateInfo->pDepthStencilState);
1402
1403 if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
1404 dynamic->depth_bounds.min =
1405 pCreateInfo->pDepthStencilState->minDepthBounds;
1406 dynamic->depth_bounds.max =
1407 pCreateInfo->pDepthStencilState->maxDepthBounds;
1408 }
1409
1410 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
1411 dynamic->stencil_compare_mask.front =
1412 pCreateInfo->pDepthStencilState->front.compareMask;
1413 dynamic->stencil_compare_mask.back =
1414 pCreateInfo->pDepthStencilState->back.compareMask;
1415 }
1416
1417 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
1418 dynamic->stencil_write_mask.front =
1419 pCreateInfo->pDepthStencilState->front.writeMask;
1420 dynamic->stencil_write_mask.back =
1421 pCreateInfo->pDepthStencilState->back.writeMask;
1422 }
1423
1424 if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
1425 dynamic->stencil_reference.front =
1426 pCreateInfo->pDepthStencilState->front.reference;
1427 dynamic->stencil_reference.back =
1428 pCreateInfo->pDepthStencilState->back.reference;
1429 }
1430 }
1431
1432 pipeline->dynamic_state_mask = states;
1433 }
1434
1435 static union ac_shader_variant_key
1436 radv_compute_vs_key(const VkGraphicsPipelineCreateInfo *pCreateInfo, bool as_es)
1437 {
1438 union ac_shader_variant_key key;
1439 const VkPipelineVertexInputStateCreateInfo *input_state =
1440 pCreateInfo->pVertexInputState;
1441
1442 memset(&key, 0, sizeof(key));
1443 key.vs.instance_rate_inputs = 0;
1444 key.vs.as_es = as_es;
1445
1446 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
1447 unsigned binding;
1448 binding = input_state->pVertexAttributeDescriptions[i].binding;
1449 if (input_state->pVertexBindingDescriptions[binding].inputRate)
1450 key.vs.instance_rate_inputs |= 1u << input_state->pVertexAttributeDescriptions[i].location;
1451 }
1452 return key;
1453 }
1454
1455 static void
1456 calculate_gs_ring_sizes(struct radv_pipeline *pipeline)
1457 {
1458 struct radv_device *device = pipeline->device;
1459 unsigned num_se = device->physical_device->rad_info.max_se;
1460 unsigned wave_size = 64;
1461 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1462 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1463 unsigned alignment = 256 * num_se;
1464 /* The maximum size is 63.999 MB per SE. */
1465 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1466
1467 struct ac_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1468 struct ac_shader_variant_info *es_info = &pipeline->shaders[MESA_SHADER_VERTEX]->info;
1469 /* Calculate the minimum size. */
1470 unsigned min_esgs_ring_size = align(es_info->vs.esgs_itemsize * gs_vertex_reuse *
1471 wave_size, alignment);
1472 /* These are recommended sizes, not minimum sizes. */
1473 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1474 es_info->vs.esgs_itemsize * gs_info->gs.vertices_in;
1475 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1476 gs_info->gs.max_gsvs_emit_size * 1; // no streams in VK (gs->max_gs_stream + 1);
1477
1478 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1479 esgs_ring_size = align(esgs_ring_size, alignment);
1480 gsvs_ring_size = align(gsvs_ring_size, alignment);
1481
1482 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1483 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1484 }
1485
1486 VkResult
1487 radv_pipeline_init(struct radv_pipeline *pipeline,
1488 struct radv_device *device,
1489 struct radv_pipeline_cache *cache,
1490 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1491 const struct radv_graphics_pipeline_create_info *extra,
1492 const VkAllocationCallbacks *alloc)
1493 {
1494 struct radv_shader_module fs_m = {0};
1495 VkResult result;
1496
1497 if (alloc == NULL)
1498 alloc = &device->alloc;
1499
1500 pipeline->device = device;
1501 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
1502
1503 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
1504 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
1505 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
1506 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
1507 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
1508 pStages[stage] = &pCreateInfo->pStages[i];
1509 modules[stage] = radv_shader_module_from_handle(pStages[stage]->module);
1510 }
1511
1512 radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
1513
1514 /* */
1515 if (modules[MESA_SHADER_VERTEX]) {
1516 bool as_es = modules[MESA_SHADER_GEOMETRY] != NULL;
1517 union ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo, as_es);
1518
1519 pipeline->shaders[MESA_SHADER_VERTEX] =
1520 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_VERTEX],
1521 pStages[MESA_SHADER_VERTEX]->pName,
1522 MESA_SHADER_VERTEX,
1523 pStages[MESA_SHADER_VERTEX]->pSpecializationInfo,
1524 pipeline->layout, &key);
1525
1526 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_VERTEX);
1527 }
1528
1529 if (modules[MESA_SHADER_GEOMETRY]) {
1530 union ac_shader_variant_key key = radv_compute_vs_key(pCreateInfo, false);
1531
1532 pipeline->shaders[MESA_SHADER_GEOMETRY] =
1533 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_GEOMETRY],
1534 pStages[MESA_SHADER_GEOMETRY]->pName,
1535 MESA_SHADER_GEOMETRY,
1536 pStages[MESA_SHADER_GEOMETRY]->pSpecializationInfo,
1537 pipeline->layout, &key);
1538
1539 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_GEOMETRY);
1540 calculate_gs_ring_sizes(pipeline);
1541 }
1542
1543 if (!modules[MESA_SHADER_FRAGMENT]) {
1544 nir_builder fs_b;
1545 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
1546 fs_b.shader->info->name = ralloc_strdup(fs_b.shader, "noop_fs");
1547 fs_m.nir = fs_b.shader;
1548 modules[MESA_SHADER_FRAGMENT] = &fs_m;
1549 }
1550
1551 if (modules[MESA_SHADER_FRAGMENT]) {
1552 union ac_shader_variant_key key;
1553 key.fs.col_format = pipeline->graphics.blend.spi_shader_col_format;
1554 key.fs.is_int8 = radv_pipeline_compute_is_int8(pCreateInfo);
1555
1556 const VkPipelineShaderStageCreateInfo *stage = pStages[MESA_SHADER_FRAGMENT];
1557
1558 pipeline->shaders[MESA_SHADER_FRAGMENT] =
1559 radv_pipeline_compile(pipeline, cache, modules[MESA_SHADER_FRAGMENT],
1560 stage ? stage->pName : "main",
1561 MESA_SHADER_FRAGMENT,
1562 stage ? stage->pSpecializationInfo : NULL,
1563 pipeline->layout, &key);
1564 pipeline->active_stages |= mesa_to_vk_shader_stage(MESA_SHADER_FRAGMENT);
1565 }
1566
1567 if (fs_m.nir)
1568 ralloc_free(fs_m.nir);
1569
1570 radv_pipeline_init_depth_stencil_state(pipeline, pCreateInfo, extra);
1571 radv_pipeline_init_raster_state(pipeline, pCreateInfo);
1572 radv_pipeline_init_multisample_state(pipeline, pCreateInfo);
1573 pipeline->graphics.prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
1574 if (radv_pipeline_has_gs(pipeline)) {
1575 pipeline->graphics.gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
1576 } else {
1577 pipeline->graphics.gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
1578 }
1579 if (extra && extra->use_rectlist) {
1580 pipeline->graphics.prim = V_008958_DI_PT_RECTLIST;
1581 pipeline->graphics.gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1582 }
1583 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
1584
1585 const VkPipelineVertexInputStateCreateInfo *vi_info =
1586 pCreateInfo->pVertexInputState;
1587 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
1588 const VkVertexInputAttributeDescription *desc =
1589 &vi_info->pVertexAttributeDescriptions[i];
1590 unsigned loc = desc->location;
1591 const struct vk_format_description *format_desc;
1592 int first_non_void;
1593 uint32_t num_format, data_format;
1594 format_desc = vk_format_description(desc->format);
1595 first_non_void = vk_format_get_first_non_void_channel(desc->format);
1596
1597 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
1598 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
1599
1600 pipeline->va_rsrc_word3[loc] = S_008F0C_DST_SEL_X(si_map_swizzle(format_desc->swizzle[0])) |
1601 S_008F0C_DST_SEL_Y(si_map_swizzle(format_desc->swizzle[1])) |
1602 S_008F0C_DST_SEL_Z(si_map_swizzle(format_desc->swizzle[2])) |
1603 S_008F0C_DST_SEL_W(si_map_swizzle(format_desc->swizzle[3])) |
1604 S_008F0C_NUM_FORMAT(num_format) |
1605 S_008F0C_DATA_FORMAT(data_format);
1606 pipeline->va_format_size[loc] = format_desc->block.bits / 8;
1607 pipeline->va_offset[loc] = desc->offset;
1608 pipeline->va_binding[loc] = desc->binding;
1609 pipeline->num_vertex_attribs = MAX2(pipeline->num_vertex_attribs, loc + 1);
1610 }
1611
1612 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
1613 const VkVertexInputBindingDescription *desc =
1614 &vi_info->pVertexBindingDescriptions[i];
1615
1616 pipeline->binding_stride[desc->binding] = desc->stride;
1617 }
1618
1619 if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
1620 radv_dump_pipeline_stats(device, pipeline);
1621 }
1622
1623 result = radv_pipeline_scratch_init(device, pipeline);
1624 return result;
1625 }
1626
1627 VkResult
1628 radv_graphics_pipeline_create(
1629 VkDevice _device,
1630 VkPipelineCache _cache,
1631 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1632 const struct radv_graphics_pipeline_create_info *extra,
1633 const VkAllocationCallbacks *pAllocator,
1634 VkPipeline *pPipeline)
1635 {
1636 RADV_FROM_HANDLE(radv_device, device, _device);
1637 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
1638 struct radv_pipeline *pipeline;
1639 VkResult result;
1640
1641 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
1642 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1643 if (pipeline == NULL)
1644 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1645
1646 memset(pipeline, 0, sizeof(*pipeline));
1647 result = radv_pipeline_init(pipeline, device, cache,
1648 pCreateInfo, extra, pAllocator);
1649 if (result != VK_SUCCESS) {
1650 radv_pipeline_destroy(device, pipeline, pAllocator);
1651 return result;
1652 }
1653
1654 *pPipeline = radv_pipeline_to_handle(pipeline);
1655
1656 return VK_SUCCESS;
1657 }
1658
1659 VkResult radv_CreateGraphicsPipelines(
1660 VkDevice _device,
1661 VkPipelineCache pipelineCache,
1662 uint32_t count,
1663 const VkGraphicsPipelineCreateInfo* pCreateInfos,
1664 const VkAllocationCallbacks* pAllocator,
1665 VkPipeline* pPipelines)
1666 {
1667 VkResult result = VK_SUCCESS;
1668 unsigned i = 0;
1669
1670 for (; i < count; i++) {
1671 VkResult r;
1672 r = radv_graphics_pipeline_create(_device,
1673 pipelineCache,
1674 &pCreateInfos[i],
1675 NULL, pAllocator, &pPipelines[i]);
1676 if (r != VK_SUCCESS) {
1677 result = r;
1678 pPipelines[i] = VK_NULL_HANDLE;
1679 }
1680 }
1681
1682 return result;
1683 }
1684
1685 static VkResult radv_compute_pipeline_create(
1686 VkDevice _device,
1687 VkPipelineCache _cache,
1688 const VkComputePipelineCreateInfo* pCreateInfo,
1689 const VkAllocationCallbacks* pAllocator,
1690 VkPipeline* pPipeline)
1691 {
1692 RADV_FROM_HANDLE(radv_device, device, _device);
1693 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
1694 RADV_FROM_HANDLE(radv_shader_module, module, pCreateInfo->stage.module);
1695 struct radv_pipeline *pipeline;
1696 VkResult result;
1697
1698 pipeline = vk_alloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
1699 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1700 if (pipeline == NULL)
1701 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1702
1703 memset(pipeline, 0, sizeof(*pipeline));
1704 pipeline->device = device;
1705 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
1706
1707 pipeline->shaders[MESA_SHADER_COMPUTE] =
1708 radv_pipeline_compile(pipeline, cache, module,
1709 pCreateInfo->stage.pName,
1710 MESA_SHADER_COMPUTE,
1711 pCreateInfo->stage.pSpecializationInfo,
1712 pipeline->layout, NULL);
1713
1714
1715 result = radv_pipeline_scratch_init(device, pipeline);
1716 if (result != VK_SUCCESS) {
1717 radv_pipeline_destroy(device, pipeline, pAllocator);
1718 return result;
1719 }
1720
1721 *pPipeline = radv_pipeline_to_handle(pipeline);
1722
1723 if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
1724 radv_dump_pipeline_stats(device, pipeline);
1725 }
1726 return VK_SUCCESS;
1727 }
1728 VkResult radv_CreateComputePipelines(
1729 VkDevice _device,
1730 VkPipelineCache pipelineCache,
1731 uint32_t count,
1732 const VkComputePipelineCreateInfo* pCreateInfos,
1733 const VkAllocationCallbacks* pAllocator,
1734 VkPipeline* pPipelines)
1735 {
1736 VkResult result = VK_SUCCESS;
1737
1738 unsigned i = 0;
1739 for (; i < count; i++) {
1740 VkResult r;
1741 r = radv_compute_pipeline_create(_device, pipelineCache,
1742 &pCreateInfos[i],
1743 pAllocator, &pPipelines[i]);
1744 if (r != VK_SUCCESS) {
1745 result = r;
1746 pPipelines[i] = VK_NULL_HANDLE;
1747 }
1748 }
1749
1750 return result;
1751 }