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radv: Implement VK_EXT_discard_rectangles.
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include <amdgpu.h>
47 #include "compiler/shader_enums.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "main/macros.h"
51 #include "vk_alloc.h"
52
53 #include "radv_radeon_winsys.h"
54 #include "ac_binary.h"
55 #include "ac_nir_to_llvm.h"
56 #include "ac_gpu_info.h"
57 #include "ac_surface.h"
58 #include "radv_descriptor_set.h"
59
60 #include <llvm-c/TargetMachine.h>
61
62 /* Pre-declarations needed for WSI entrypoints */
63 struct wl_surface;
64 struct wl_display;
65 typedef struct xcb_connection_t xcb_connection_t;
66 typedef uint32_t xcb_visualid_t;
67 typedef uint32_t xcb_window_t;
68
69 #include <vulkan/vulkan.h>
70 #include <vulkan/vulkan_intel.h>
71 #include <vulkan/vk_icd.h>
72
73 #include "radv_entrypoints.h"
74
75 #include "wsi_common.h"
76
77 #define ATI_VENDOR_ID 0x1002
78
79 #define MAX_VBS 32
80 #define MAX_VERTEX_ATTRIBS 32
81 #define MAX_RTS 8
82 #define MAX_VIEWPORTS 16
83 #define MAX_SCISSORS 16
84 #define MAX_DISCARD_RECTANGLES 4
85 #define MAX_PUSH_CONSTANTS_SIZE 128
86 #define MAX_PUSH_DESCRIPTORS 32
87 #define MAX_DYNAMIC_BUFFERS 16
88 #define MAX_SAMPLES_LOG2 4
89 #define NUM_META_FS_KEYS 13
90 #define RADV_MAX_DRM_DEVICES 8
91 #define MAX_VIEWS 8
92
93 #define NUM_DEPTH_CLEAR_PIPELINES 3
94
95 enum radv_mem_heap {
96 RADV_MEM_HEAP_VRAM,
97 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
98 RADV_MEM_HEAP_GTT,
99 RADV_MEM_HEAP_COUNT
100 };
101
102 enum radv_mem_type {
103 RADV_MEM_TYPE_VRAM,
104 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
105 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
106 RADV_MEM_TYPE_GTT_CACHED,
107 RADV_MEM_TYPE_COUNT
108 };
109
110 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
111
112 static inline uint32_t
113 align_u32(uint32_t v, uint32_t a)
114 {
115 assert(a != 0 && a == (a & -a));
116 return (v + a - 1) & ~(a - 1);
117 }
118
119 static inline uint32_t
120 align_u32_npot(uint32_t v, uint32_t a)
121 {
122 return (v + a - 1) / a * a;
123 }
124
125 static inline uint64_t
126 align_u64(uint64_t v, uint64_t a)
127 {
128 assert(a != 0 && a == (a & -a));
129 return (v + a - 1) & ~(a - 1);
130 }
131
132 static inline int32_t
133 align_i32(int32_t v, int32_t a)
134 {
135 assert(a != 0 && a == (a & -a));
136 return (v + a - 1) & ~(a - 1);
137 }
138
139 /** Alignment must be a power of 2. */
140 static inline bool
141 radv_is_aligned(uintmax_t n, uintmax_t a)
142 {
143 assert(a == (a & -a));
144 return (n & (a - 1)) == 0;
145 }
146
147 static inline uint32_t
148 round_up_u32(uint32_t v, uint32_t a)
149 {
150 return (v + a - 1) / a;
151 }
152
153 static inline uint64_t
154 round_up_u64(uint64_t v, uint64_t a)
155 {
156 return (v + a - 1) / a;
157 }
158
159 static inline uint32_t
160 radv_minify(uint32_t n, uint32_t levels)
161 {
162 if (unlikely(n == 0))
163 return 0;
164 else
165 return MAX2(n >> levels, 1);
166 }
167 static inline float
168 radv_clamp_f(float f, float min, float max)
169 {
170 assert(min < max);
171
172 if (f > max)
173 return max;
174 else if (f < min)
175 return min;
176 else
177 return f;
178 }
179
180 static inline bool
181 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
182 {
183 if (*inout_mask & clear_mask) {
184 *inout_mask &= ~clear_mask;
185 return true;
186 } else {
187 return false;
188 }
189 }
190
191 #define for_each_bit(b, dword) \
192 for (uint32_t __dword = (dword); \
193 (b) = __builtin_ffs(__dword) - 1, __dword; \
194 __dword &= ~(1 << (b)))
195
196 #define typed_memcpy(dest, src, count) ({ \
197 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
198 memcpy((dest), (src), (count) * sizeof(*(src))); \
199 })
200
201 /* Whenever we generate an error, pass it through this function. Useful for
202 * debugging, where we can break on it. Only call at error site, not when
203 * propagating errors. Might be useful to plug in a stack trace here.
204 */
205
206 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
207
208 #ifdef DEBUG
209 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
210 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
211 #else
212 #define vk_error(error) error
213 #define vk_errorf(error, format, ...) error
214 #endif
215
216 void __radv_finishme(const char *file, int line, const char *format, ...)
217 radv_printflike(3, 4);
218 void radv_loge(const char *format, ...) radv_printflike(1, 2);
219 void radv_loge_v(const char *format, va_list va);
220
221 /**
222 * Print a FINISHME message, including its source location.
223 */
224 #define radv_finishme(format, ...) \
225 do { \
226 static bool reported = false; \
227 if (!reported) { \
228 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
229 reported = true; \
230 } \
231 } while (0)
232
233 /* A non-fatal assert. Useful for debugging. */
234 #ifdef DEBUG
235 #define radv_assert(x) ({ \
236 if (unlikely(!(x))) \
237 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
238 })
239 #else
240 #define radv_assert(x)
241 #endif
242
243 #define stub_return(v) \
244 do { \
245 radv_finishme("stub %s", __func__); \
246 return (v); \
247 } while (0)
248
249 #define stub() \
250 do { \
251 radv_finishme("stub %s", __func__); \
252 return; \
253 } while (0)
254
255 void *radv_lookup_entrypoint(const char *name);
256
257 struct radv_physical_device {
258 VK_LOADER_DATA _loader_data;
259
260 struct radv_instance * instance;
261
262 struct radeon_winsys *ws;
263 struct radeon_info rad_info;
264 char path[20];
265 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
266 uint8_t driver_uuid[VK_UUID_SIZE];
267 uint8_t device_uuid[VK_UUID_SIZE];
268 uint8_t cache_uuid[VK_UUID_SIZE];
269
270 int local_fd;
271 struct wsi_device wsi_device;
272
273 bool has_rbplus; /* if RB+ register exist */
274 bool rbplus_allowed; /* if RB+ is allowed */
275 bool has_clear_state;
276 bool cpdma_prefetch_writes_memory;
277 bool has_scissor_bug;
278
279 /* This is the drivers on-disk cache used as a fallback as opposed to
280 * the pipeline cache defined by apps.
281 */
282 struct disk_cache * disk_cache;
283
284 VkPhysicalDeviceMemoryProperties memory_properties;
285 enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
286 };
287
288 struct radv_instance {
289 VK_LOADER_DATA _loader_data;
290
291 VkAllocationCallbacks alloc;
292
293 uint32_t apiVersion;
294 int physicalDeviceCount;
295 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
296
297 uint64_t debug_flags;
298 uint64_t perftest_flags;
299 };
300
301 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
302 void radv_finish_wsi(struct radv_physical_device *physical_device);
303
304 bool radv_instance_extension_supported(const char *name);
305 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
306 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
307 const char *name);
308
309 struct cache_entry;
310
311 struct radv_pipeline_cache {
312 struct radv_device * device;
313 pthread_mutex_t mutex;
314
315 uint32_t total_size;
316 uint32_t table_size;
317 uint32_t kernel_count;
318 struct cache_entry ** hash_table;
319 bool modified;
320
321 VkAllocationCallbacks alloc;
322 };
323
324 struct radv_pipeline_key {
325 uint32_t instance_rate_inputs;
326 unsigned tess_input_vertices;
327 uint32_t col_format;
328 uint32_t is_int8;
329 uint32_t is_int10;
330 uint32_t multisample : 1;
331 uint32_t has_multiview_view_index : 1;
332 };
333
334 void
335 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
336 struct radv_device *device);
337 void
338 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
339 void
340 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
341 const void *data, size_t size);
342
343 struct radv_shader_variant;
344
345 bool
346 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
347 struct radv_pipeline_cache *cache,
348 const unsigned char *sha1,
349 struct radv_shader_variant **variants);
350
351 void
352 radv_pipeline_cache_insert_shaders(struct radv_device *device,
353 struct radv_pipeline_cache *cache,
354 const unsigned char *sha1,
355 struct radv_shader_variant **variants,
356 const void *const *codes,
357 const unsigned *code_sizes);
358
359 enum radv_blit_ds_layout {
360 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
361 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
362 RADV_BLIT_DS_LAYOUT_COUNT,
363 };
364
365 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
366 {
367 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
368 }
369
370 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
371 {
372 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
373 }
374
375 enum radv_meta_dst_layout {
376 RADV_META_DST_LAYOUT_GENERAL,
377 RADV_META_DST_LAYOUT_OPTIMAL,
378 RADV_META_DST_LAYOUT_COUNT,
379 };
380
381 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
382 {
383 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
384 }
385
386 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
387 {
388 return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
389 }
390
391 struct radv_meta_state {
392 VkAllocationCallbacks alloc;
393
394 struct radv_pipeline_cache cache;
395
396 /**
397 * Use array element `i` for images with `2^i` samples.
398 */
399 struct {
400 VkRenderPass render_pass[NUM_META_FS_KEYS];
401 VkPipeline color_pipelines[NUM_META_FS_KEYS];
402
403 VkRenderPass depthstencil_rp;
404 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
405 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
406 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
407 } clear[1 + MAX_SAMPLES_LOG2];
408
409 VkPipelineLayout clear_color_p_layout;
410 VkPipelineLayout clear_depth_p_layout;
411 struct {
412 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
413
414 /** Pipeline that blits from a 1D image. */
415 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
416
417 /** Pipeline that blits from a 2D image. */
418 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
419
420 /** Pipeline that blits from a 3D image. */
421 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
422
423 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
424 VkPipeline depth_only_1d_pipeline;
425 VkPipeline depth_only_2d_pipeline;
426 VkPipeline depth_only_3d_pipeline;
427
428 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
429 VkPipeline stencil_only_1d_pipeline;
430 VkPipeline stencil_only_2d_pipeline;
431 VkPipeline stencil_only_3d_pipeline;
432 VkPipelineLayout pipeline_layout;
433 VkDescriptorSetLayout ds_layout;
434 } blit;
435
436 struct {
437 VkRenderPass render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
438
439 VkPipelineLayout p_layouts[3];
440 VkDescriptorSetLayout ds_layouts[3];
441 VkPipeline pipelines[3][NUM_META_FS_KEYS];
442
443 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
444 VkPipeline depth_only_pipeline[3];
445
446 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
447 VkPipeline stencil_only_pipeline[3];
448 } blit2d;
449
450 struct {
451 VkPipelineLayout img_p_layout;
452 VkDescriptorSetLayout img_ds_layout;
453 VkPipeline pipeline;
454 VkPipeline pipeline_3d;
455 } itob;
456 struct {
457 VkPipelineLayout img_p_layout;
458 VkDescriptorSetLayout img_ds_layout;
459 VkPipeline pipeline;
460 VkPipeline pipeline_3d;
461 } btoi;
462 struct {
463 VkPipelineLayout img_p_layout;
464 VkDescriptorSetLayout img_ds_layout;
465 VkPipeline pipeline;
466 VkPipeline pipeline_3d;
467 } itoi;
468 struct {
469 VkPipelineLayout img_p_layout;
470 VkDescriptorSetLayout img_ds_layout;
471 VkPipeline pipeline;
472 VkPipeline pipeline_3d;
473 } cleari;
474
475 struct {
476 VkPipelineLayout p_layout;
477 VkPipeline pipeline;
478 VkRenderPass pass;
479 } resolve;
480
481 struct {
482 VkDescriptorSetLayout ds_layout;
483 VkPipelineLayout p_layout;
484 struct {
485 VkPipeline pipeline;
486 VkPipeline i_pipeline;
487 VkPipeline srgb_pipeline;
488 } rc[MAX_SAMPLES_LOG2];
489 } resolve_compute;
490
491 struct {
492 VkDescriptorSetLayout ds_layout;
493 VkPipelineLayout p_layout;
494
495 struct {
496 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
497 VkPipeline pipeline[NUM_META_FS_KEYS];
498 } rc[MAX_SAMPLES_LOG2];
499 } resolve_fragment;
500
501 struct {
502 VkPipelineLayout p_layout;
503 VkPipeline decompress_pipeline;
504 VkPipeline resummarize_pipeline;
505 VkRenderPass pass;
506 } depth_decomp[1 + MAX_SAMPLES_LOG2];
507
508 struct {
509 VkPipelineLayout p_layout;
510 VkPipeline cmask_eliminate_pipeline;
511 VkPipeline fmask_decompress_pipeline;
512 VkPipeline dcc_decompress_pipeline;
513 VkRenderPass pass;
514
515 VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
516 VkPipelineLayout dcc_decompress_compute_p_layout;
517 VkPipeline dcc_decompress_compute_pipeline;
518 } fast_clear_flush;
519
520 struct {
521 VkPipelineLayout fill_p_layout;
522 VkPipelineLayout copy_p_layout;
523 VkDescriptorSetLayout fill_ds_layout;
524 VkDescriptorSetLayout copy_ds_layout;
525 VkPipeline fill_pipeline;
526 VkPipeline copy_pipeline;
527 } buffer;
528
529 struct {
530 VkDescriptorSetLayout ds_layout;
531 VkPipelineLayout p_layout;
532 VkPipeline occlusion_query_pipeline;
533 VkPipeline pipeline_statistics_query_pipeline;
534 } query;
535 };
536
537 /* queue types */
538 #define RADV_QUEUE_GENERAL 0
539 #define RADV_QUEUE_COMPUTE 1
540 #define RADV_QUEUE_TRANSFER 2
541
542 #define RADV_MAX_QUEUE_FAMILIES 3
543
544 enum ring_type radv_queue_family_to_ring(int f);
545
546 struct radv_queue {
547 VK_LOADER_DATA _loader_data;
548 struct radv_device * device;
549 struct radeon_winsys_ctx *hw_ctx;
550 enum radeon_ctx_priority priority;
551 uint32_t queue_family_index;
552 int queue_idx;
553
554 uint32_t scratch_size;
555 uint32_t compute_scratch_size;
556 uint32_t esgs_ring_size;
557 uint32_t gsvs_ring_size;
558 bool has_tess_rings;
559 bool has_sample_positions;
560
561 struct radeon_winsys_bo *scratch_bo;
562 struct radeon_winsys_bo *descriptor_bo;
563 struct radeon_winsys_bo *compute_scratch_bo;
564 struct radeon_winsys_bo *esgs_ring_bo;
565 struct radeon_winsys_bo *gsvs_ring_bo;
566 struct radeon_winsys_bo *tess_factor_ring_bo;
567 struct radeon_winsys_bo *tess_offchip_ring_bo;
568 struct radeon_winsys_cs *initial_preamble_cs;
569 struct radeon_winsys_cs *initial_full_flush_preamble_cs;
570 struct radeon_winsys_cs *continue_preamble_cs;
571 };
572
573 struct radv_device {
574 VK_LOADER_DATA _loader_data;
575
576 VkAllocationCallbacks alloc;
577
578 struct radv_instance * instance;
579 struct radeon_winsys *ws;
580
581 struct radv_meta_state meta_state;
582
583 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
584 int queue_count[RADV_MAX_QUEUE_FAMILIES];
585 struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
586
587 bool llvm_supports_spill;
588 bool has_distributed_tess;
589 bool pbb_allowed;
590 bool dfsm_allowed;
591 uint32_t tess_offchip_block_dw_size;
592 uint32_t scratch_waves;
593 uint32_t dispatch_initiator;
594
595 uint32_t gs_table_depth;
596
597 /* MSAA sample locations.
598 * The first index is the sample index.
599 * The second index is the coordinate: X, Y. */
600 float sample_locations_1x[1][2];
601 float sample_locations_2x[2][2];
602 float sample_locations_4x[4][2];
603 float sample_locations_8x[8][2];
604 float sample_locations_16x[16][2];
605
606 /* CIK and later */
607 uint32_t gfx_init_size_dw;
608 struct radeon_winsys_bo *gfx_init;
609
610 struct radeon_winsys_bo *trace_bo;
611 uint32_t *trace_id_ptr;
612
613 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
614 bool keep_shader_info;
615
616 struct radv_physical_device *physical_device;
617
618 /* Backup in-memory cache to be used if the app doesn't provide one */
619 struct radv_pipeline_cache * mem_cache;
620
621 /*
622 * use different counters so MSAA MRTs get consecutive surface indices,
623 * even if MASK is allocated in between.
624 */
625 uint32_t image_mrt_offset_counter;
626 uint32_t fmask_mrt_offset_counter;
627 struct list_head shader_slabs;
628 mtx_t shader_slab_mutex;
629
630 /* For detecting VM faults reported by dmesg. */
631 uint64_t dmesg_timestamp;
632 };
633
634 struct radv_device_memory {
635 struct radeon_winsys_bo *bo;
636 /* for dedicated allocations */
637 struct radv_image *image;
638 struct radv_buffer *buffer;
639 uint32_t type_index;
640 VkDeviceSize map_size;
641 void * map;
642 };
643
644
645 struct radv_descriptor_range {
646 uint64_t va;
647 uint32_t size;
648 };
649
650 struct radv_descriptor_set {
651 const struct radv_descriptor_set_layout *layout;
652 uint32_t size;
653
654 struct radeon_winsys_bo *bo;
655 uint64_t va;
656 uint32_t *mapped_ptr;
657 struct radv_descriptor_range *dynamic_descriptors;
658
659 struct radeon_winsys_bo *descriptors[0];
660 };
661
662 struct radv_push_descriptor_set
663 {
664 struct radv_descriptor_set set;
665 uint32_t capacity;
666 };
667
668 struct radv_descriptor_pool_entry {
669 uint32_t offset;
670 uint32_t size;
671 struct radv_descriptor_set *set;
672 };
673
674 struct radv_descriptor_pool {
675 struct radeon_winsys_bo *bo;
676 uint8_t *mapped_ptr;
677 uint64_t current_offset;
678 uint64_t size;
679
680 uint8_t *host_memory_base;
681 uint8_t *host_memory_ptr;
682 uint8_t *host_memory_end;
683
684 uint32_t entry_count;
685 uint32_t max_entry_count;
686 struct radv_descriptor_pool_entry entries[0];
687 };
688
689 struct radv_descriptor_update_template_entry {
690 VkDescriptorType descriptor_type;
691
692 /* The number of descriptors to update */
693 uint32_t descriptor_count;
694
695 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
696 uint32_t dst_offset;
697
698 /* In dwords. Not valid/used for dynamic descriptors */
699 uint32_t dst_stride;
700
701 uint32_t buffer_offset;
702
703 /* Only valid for combined image samplers and samplers */
704 uint16_t has_sampler;
705
706 /* In bytes */
707 size_t src_offset;
708 size_t src_stride;
709
710 /* For push descriptors */
711 const uint32_t *immutable_samplers;
712 };
713
714 struct radv_descriptor_update_template {
715 uint32_t entry_count;
716 struct radv_descriptor_update_template_entry entry[0];
717 };
718
719 struct radv_buffer {
720 struct radv_device * device;
721 VkDeviceSize size;
722
723 VkBufferUsageFlags usage;
724 VkBufferCreateFlags flags;
725
726 /* Set when bound */
727 struct radeon_winsys_bo * bo;
728 VkDeviceSize offset;
729
730 bool shareable;
731 };
732
733 enum radv_dynamic_state_bits {
734 RADV_DYNAMIC_VIEWPORT = 1 << 0,
735 RADV_DYNAMIC_SCISSOR = 1 << 1,
736 RADV_DYNAMIC_LINE_WIDTH = 1 << 2,
737 RADV_DYNAMIC_DEPTH_BIAS = 1 << 3,
738 RADV_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
739 RADV_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
740 RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
741 RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
742 RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
743 RADV_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
744 RADV_DYNAMIC_ALL = (1 << 10) - 1,
745 };
746
747 enum radv_cmd_dirty_bits {
748 /* Keep the dynamic state dirty bits in sync with
749 * enum radv_dynamic_state_bits */
750 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0,
751 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1,
752 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2,
753 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3,
754 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
755 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
756 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
757 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
758 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
759 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
760 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 10) - 1,
761 RADV_CMD_DIRTY_PIPELINE = 1 << 10,
762 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 11,
763 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 12,
764 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 13,
765 };
766
767 enum radv_cmd_flush_bits {
768 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
769 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
770 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
771 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
772 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
773 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
774 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
775 /* Same as above, but only writes back and doesn't invalidate */
776 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
777 /* Framebuffer caches */
778 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
779 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
780 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
781 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
782 /* Engine synchronization. */
783 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
784 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
785 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
786 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
787
788 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
789 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
790 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
791 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
792 };
793
794 struct radv_vertex_binding {
795 struct radv_buffer * buffer;
796 VkDeviceSize offset;
797 };
798
799 struct radv_viewport_state {
800 uint32_t count;
801 VkViewport viewports[MAX_VIEWPORTS];
802 };
803
804 struct radv_scissor_state {
805 uint32_t count;
806 VkRect2D scissors[MAX_SCISSORS];
807 };
808
809 struct radv_discard_rectangle_state {
810 uint32_t count;
811 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
812 };
813
814 struct radv_dynamic_state {
815 /**
816 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
817 * Defines the set of saved dynamic state.
818 */
819 uint32_t mask;
820
821 struct radv_viewport_state viewport;
822
823 struct radv_scissor_state scissor;
824
825 float line_width;
826
827 struct {
828 float bias;
829 float clamp;
830 float slope;
831 } depth_bias;
832
833 float blend_constants[4];
834
835 struct {
836 float min;
837 float max;
838 } depth_bounds;
839
840 struct {
841 uint32_t front;
842 uint32_t back;
843 } stencil_compare_mask;
844
845 struct {
846 uint32_t front;
847 uint32_t back;
848 } stencil_write_mask;
849
850 struct {
851 uint32_t front;
852 uint32_t back;
853 } stencil_reference;
854
855 struct radv_discard_rectangle_state discard_rectangle;
856 };
857
858 extern const struct radv_dynamic_state default_dynamic_state;
859
860 const char *
861 radv_get_debug_option_name(int id);
862
863 const char *
864 radv_get_perftest_option_name(int id);
865
866 /**
867 * Attachment state when recording a renderpass instance.
868 *
869 * The clear value is valid only if there exists a pending clear.
870 */
871 struct radv_attachment_state {
872 VkImageAspectFlags pending_clear_aspects;
873 uint32_t cleared_views;
874 VkClearValue clear_value;
875 VkImageLayout current_layout;
876 };
877
878 struct radv_cmd_state {
879 /* Vertex descriptors */
880 bool vb_prefetch_dirty;
881 uint64_t vb_va;
882 unsigned vb_size;
883
884 bool push_descriptors_dirty;
885 bool predicating;
886 uint32_t dirty;
887
888 struct radv_pipeline * pipeline;
889 struct radv_pipeline * emitted_pipeline;
890 struct radv_pipeline * compute_pipeline;
891 struct radv_pipeline * emitted_compute_pipeline;
892 struct radv_framebuffer * framebuffer;
893 struct radv_render_pass * pass;
894 const struct radv_subpass * subpass;
895 struct radv_dynamic_state dynamic;
896 struct radv_attachment_state * attachments;
897 VkRect2D render_area;
898
899 /* Index buffer */
900 struct radv_buffer *index_buffer;
901 uint64_t index_offset;
902 uint32_t index_type;
903 uint32_t max_index_count;
904 uint64_t index_va;
905 int32_t last_index_type;
906
907 int32_t last_primitive_reset_en;
908 uint32_t last_primitive_reset_index;
909 enum radv_cmd_flush_bits flush_bits;
910 unsigned active_occlusion_queries;
911 float offset_scale;
912 uint32_t descriptors_dirty;
913 uint32_t valid_descriptors;
914 uint32_t trace_id;
915 uint32_t last_ia_multi_vgt_param;
916 };
917
918 struct radv_cmd_pool {
919 VkAllocationCallbacks alloc;
920 struct list_head cmd_buffers;
921 struct list_head free_cmd_buffers;
922 uint32_t queue_family_index;
923 };
924
925 struct radv_cmd_buffer_upload {
926 uint8_t *map;
927 unsigned offset;
928 uint64_t size;
929 struct radeon_winsys_bo *upload_bo;
930 struct list_head list;
931 };
932
933 enum radv_cmd_buffer_status {
934 RADV_CMD_BUFFER_STATUS_INVALID,
935 RADV_CMD_BUFFER_STATUS_INITIAL,
936 RADV_CMD_BUFFER_STATUS_RECORDING,
937 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
938 RADV_CMD_BUFFER_STATUS_PENDING,
939 };
940
941 struct radv_cmd_buffer {
942 VK_LOADER_DATA _loader_data;
943
944 struct radv_device * device;
945
946 struct radv_cmd_pool * pool;
947 struct list_head pool_link;
948
949 VkCommandBufferUsageFlags usage_flags;
950 VkCommandBufferLevel level;
951 enum radv_cmd_buffer_status status;
952 struct radeon_winsys_cs *cs;
953 struct radv_cmd_state state;
954 struct radv_vertex_binding vertex_bindings[MAX_VBS];
955 uint32_t queue_family_index;
956
957 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
958 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
959 VkShaderStageFlags push_constant_stages;
960 struct radv_push_descriptor_set push_descriptors;
961 struct radv_descriptor_set meta_push_descriptors;
962 struct radv_descriptor_set *descriptors[MAX_SETS];
963
964 struct radv_cmd_buffer_upload upload;
965
966 uint32_t scratch_size_needed;
967 uint32_t compute_scratch_size_needed;
968 uint32_t esgs_ring_size_needed;
969 uint32_t gsvs_ring_size_needed;
970 bool tess_rings_needed;
971 bool sample_positions_needed;
972
973 VkResult record_result;
974
975 int ring_offsets_idx; /* just used for verification */
976 uint32_t gfx9_fence_offset;
977 struct radeon_winsys_bo *gfx9_fence_bo;
978 uint32_t gfx9_fence_idx;
979 };
980
981 struct radv_image;
982
983 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
984
985 void si_init_compute(struct radv_cmd_buffer *cmd_buffer);
986 void si_init_config(struct radv_cmd_buffer *cmd_buffer);
987
988 void cik_create_gfx_config(struct radv_device *device);
989
990 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
991 int count, const VkViewport *viewports);
992 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
993 int count, const VkRect2D *scissors,
994 const VkViewport *viewports, bool can_use_guardband);
995 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
996 bool instanced_draw, bool indirect_draw,
997 uint32_t draw_vertex_count);
998 void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
999 bool predicated,
1000 enum chip_class chip_class,
1001 bool is_mec,
1002 unsigned event, unsigned event_flags,
1003 unsigned data_sel,
1004 uint64_t va,
1005 uint32_t old_fence,
1006 uint32_t new_fence);
1007
1008 void si_emit_wait_fence(struct radeon_winsys_cs *cs,
1009 bool predicated,
1010 uint64_t va, uint32_t ref,
1011 uint32_t mask);
1012 void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
1013 bool predicated,
1014 enum chip_class chip_class,
1015 uint32_t *fence_ptr, uint64_t va,
1016 bool is_mec,
1017 enum radv_cmd_flush_bits flush_bits);
1018 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
1019 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va);
1020 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1021 uint64_t src_va, uint64_t dest_va,
1022 uint64_t size);
1023 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1024 unsigned size);
1025 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1026 uint64_t size, unsigned value);
1027 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1028 bool
1029 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1030 unsigned size,
1031 unsigned alignment,
1032 unsigned *out_offset,
1033 void **ptr);
1034 void
1035 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1036 const struct radv_subpass *subpass,
1037 bool transitions);
1038 bool
1039 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1040 unsigned size, unsigned alignmnet,
1041 const void *data, unsigned *out_offset);
1042
1043 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1044 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1045 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1046 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1047 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
1048 unsigned radv_cayman_get_maxdist(int log_samples);
1049 void radv_device_init_msaa(struct radv_device *device);
1050 void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1051 struct radv_image *image,
1052 VkClearDepthStencilValue ds_clear_value,
1053 VkImageAspectFlags aspects);
1054 void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1055 struct radv_image *image,
1056 int idx,
1057 uint32_t color_values[2]);
1058 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1059 struct radv_image *image,
1060 bool value);
1061 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1062 struct radeon_winsys_bo *bo,
1063 uint64_t offset, uint64_t size, uint32_t value);
1064 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1065 bool radv_get_memory_fd(struct radv_device *device,
1066 struct radv_device_memory *memory,
1067 int *pFD);
1068
1069 /*
1070 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1071 *
1072 * Limitations: Can't call normal dispatch functions without binding or rebinding
1073 * the compute pipeline.
1074 */
1075 void radv_unaligned_dispatch(
1076 struct radv_cmd_buffer *cmd_buffer,
1077 uint32_t x,
1078 uint32_t y,
1079 uint32_t z);
1080
1081 struct radv_event {
1082 struct radeon_winsys_bo *bo;
1083 uint64_t *map;
1084 };
1085
1086 struct radv_shader_module;
1087
1088 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1089 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1090 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1091 void
1092 radv_hash_shaders(unsigned char *hash,
1093 const VkPipelineShaderStageCreateInfo **stages,
1094 const struct radv_pipeline_layout *layout,
1095 const struct radv_pipeline_key *key,
1096 uint32_t flags);
1097
1098 static inline gl_shader_stage
1099 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1100 {
1101 assert(__builtin_popcount(vk_stage) == 1);
1102 return ffs(vk_stage) - 1;
1103 }
1104
1105 static inline VkShaderStageFlagBits
1106 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1107 {
1108 return (1 << mesa_stage);
1109 }
1110
1111 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1112
1113 #define radv_foreach_stage(stage, stage_bits) \
1114 for (gl_shader_stage stage, \
1115 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1116 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1117 __tmp &= ~(1 << (stage)))
1118
1119 struct radv_depth_stencil_state {
1120 uint32_t db_depth_control;
1121 uint32_t db_stencil_control;
1122 uint32_t db_render_control;
1123 uint32_t db_render_override2;
1124 };
1125
1126 struct radv_blend_state {
1127 uint32_t cb_color_control;
1128 uint32_t cb_target_mask;
1129 uint32_t sx_mrt_blend_opt[8];
1130 uint32_t cb_blend_control[8];
1131
1132 uint32_t spi_shader_col_format;
1133 uint32_t cb_shader_mask;
1134 uint32_t db_alpha_to_mask;
1135 };
1136
1137 unsigned radv_format_meta_fs_key(VkFormat format);
1138
1139 struct radv_raster_state {
1140 uint32_t pa_cl_clip_cntl;
1141 uint32_t spi_interp_control;
1142 uint32_t pa_su_vtx_cntl;
1143 uint32_t pa_su_sc_mode_cntl;
1144 };
1145
1146 struct radv_multisample_state {
1147 uint32_t db_eqaa;
1148 uint32_t pa_sc_line_cntl;
1149 uint32_t pa_sc_mode_cntl_0;
1150 uint32_t pa_sc_mode_cntl_1;
1151 uint32_t pa_sc_aa_config;
1152 uint32_t pa_sc_aa_mask[2];
1153 unsigned num_samples;
1154 };
1155
1156 struct radv_prim_vertex_count {
1157 uint8_t min;
1158 uint8_t incr;
1159 };
1160
1161 struct radv_tessellation_state {
1162 uint32_t ls_hs_config;
1163 uint32_t tcs_in_layout;
1164 uint32_t tcs_out_layout;
1165 uint32_t tcs_out_offsets;
1166 uint32_t offchip_layout;
1167 unsigned num_patches;
1168 unsigned lds_size;
1169 unsigned num_tcs_input_cp;
1170 uint32_t tf_param;
1171 };
1172
1173 struct radv_gs_state {
1174 uint32_t vgt_gs_onchip_cntl;
1175 uint32_t vgt_gs_max_prims_per_subgroup;
1176 uint32_t vgt_esgs_ring_itemsize;
1177 uint32_t lds_size;
1178 };
1179
1180 struct radv_vertex_elements_info {
1181 uint32_t rsrc_word3[MAX_VERTEX_ATTRIBS];
1182 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1183 uint32_t binding[MAX_VERTEX_ATTRIBS];
1184 uint32_t offset[MAX_VERTEX_ATTRIBS];
1185 uint32_t count;
1186 };
1187
1188 struct radv_vs_state {
1189 uint32_t pa_cl_vs_out_cntl;
1190 uint32_t spi_shader_pos_format;
1191 uint32_t spi_vs_out_config;
1192 uint32_t vgt_reuse_off;
1193 };
1194
1195 struct radv_binning_state {
1196 uint32_t pa_sc_binner_cntl_0;
1197 uint32_t db_dfsm_control;
1198 };
1199
1200 #define SI_GS_PER_ES 128
1201
1202 struct radv_pipeline {
1203 struct radv_device * device;
1204 struct radv_dynamic_state dynamic_state;
1205
1206 struct radv_pipeline_layout * layout;
1207
1208 bool needs_data_cache;
1209 bool need_indirect_descriptor_sets;
1210 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1211 struct radv_shader_variant *gs_copy_shader;
1212 VkShaderStageFlags active_stages;
1213
1214 struct radv_vertex_elements_info vertex_elements;
1215
1216 uint32_t binding_stride[MAX_VBS];
1217
1218 uint32_t user_data_0[MESA_SHADER_STAGES];
1219 union {
1220 struct {
1221 struct radv_blend_state blend;
1222 struct radv_depth_stencil_state ds;
1223 struct radv_raster_state raster;
1224 struct radv_multisample_state ms;
1225 struct radv_tessellation_state tess;
1226 struct radv_gs_state gs;
1227 struct radv_vs_state vs;
1228 struct radv_binning_state bin;
1229 uint32_t db_shader_control;
1230 uint32_t shader_z_format;
1231 unsigned prim;
1232 unsigned gs_out;
1233 uint32_t vgt_gs_mode;
1234 bool vgt_primitiveid_en;
1235 bool prim_restart_enable;
1236 bool partial_es_wave;
1237 uint8_t primgroup_size;
1238 unsigned esgs_ring_size;
1239 unsigned gsvs_ring_size;
1240 uint32_t ps_input_cntl[32];
1241 uint32_t ps_input_cntl_num;
1242 uint32_t vgt_shader_stages_en;
1243 uint32_t vtx_base_sgpr;
1244 uint32_t base_ia_multi_vgt_param;
1245 bool wd_switch_on_eop;
1246 bool ia_switch_on_eoi;
1247 bool partial_vs_wave;
1248 uint8_t vtx_emit_num;
1249 uint32_t vtx_reuse_depth;
1250 struct radv_prim_vertex_count prim_vertex_count;
1251 bool can_use_guardband;
1252 uint32_t pa_sc_cliprect_rule;
1253 } graphics;
1254 };
1255
1256 unsigned max_waves;
1257 unsigned scratch_bytes_per_wave;
1258 };
1259
1260 static inline bool radv_pipeline_has_gs(struct radv_pipeline *pipeline)
1261 {
1262 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1263 }
1264
1265 static inline bool radv_pipeline_has_tess(struct radv_pipeline *pipeline)
1266 {
1267 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1268 }
1269
1270 struct ac_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1271 gl_shader_stage stage,
1272 int idx);
1273
1274 struct radv_shader_variant *radv_get_vertex_shader(struct radv_pipeline *pipeline);
1275
1276 struct radv_graphics_pipeline_create_info {
1277 bool use_rectlist;
1278 bool db_depth_clear;
1279 bool db_stencil_clear;
1280 bool db_depth_disable_expclear;
1281 bool db_stencil_disable_expclear;
1282 bool db_flush_depth_inplace;
1283 bool db_flush_stencil_inplace;
1284 bool db_resummarize;
1285 uint32_t custom_blend_mode;
1286 };
1287
1288 VkResult
1289 radv_graphics_pipeline_create(VkDevice device,
1290 VkPipelineCache cache,
1291 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1292 const struct radv_graphics_pipeline_create_info *extra,
1293 const VkAllocationCallbacks *alloc,
1294 VkPipeline *pPipeline);
1295
1296 struct vk_format_description;
1297 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1298 int first_non_void);
1299 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1300 int first_non_void);
1301 uint32_t radv_translate_colorformat(VkFormat format);
1302 uint32_t radv_translate_color_numformat(VkFormat format,
1303 const struct vk_format_description *desc,
1304 int first_non_void);
1305 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1306 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1307 uint32_t radv_translate_dbformat(VkFormat format);
1308 uint32_t radv_translate_tex_dataformat(VkFormat format,
1309 const struct vk_format_description *desc,
1310 int first_non_void);
1311 uint32_t radv_translate_tex_numformat(VkFormat format,
1312 const struct vk_format_description *desc,
1313 int first_non_void);
1314 bool radv_format_pack_clear_color(VkFormat format,
1315 uint32_t clear_vals[2],
1316 VkClearColorValue *value);
1317 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1318 bool radv_dcc_formats_compatible(VkFormat format1,
1319 VkFormat format2);
1320
1321 struct radv_fmask_info {
1322 uint64_t offset;
1323 uint64_t size;
1324 unsigned alignment;
1325 unsigned pitch_in_pixels;
1326 unsigned bank_height;
1327 unsigned slice_tile_max;
1328 unsigned tile_mode_index;
1329 unsigned tile_swizzle;
1330 };
1331
1332 struct radv_cmask_info {
1333 uint64_t offset;
1334 uint64_t size;
1335 unsigned alignment;
1336 unsigned slice_tile_max;
1337 };
1338
1339 struct radv_image {
1340 VkImageType type;
1341 /* The original VkFormat provided by the client. This may not match any
1342 * of the actual surface formats.
1343 */
1344 VkFormat vk_format;
1345 VkImageAspectFlags aspects;
1346 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1347 struct ac_surf_info info;
1348 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1349 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1350
1351 VkDeviceSize size;
1352 uint32_t alignment;
1353
1354 unsigned queue_family_mask;
1355 bool exclusive;
1356 bool shareable;
1357
1358 /* Set when bound */
1359 struct radeon_winsys_bo *bo;
1360 VkDeviceSize offset;
1361 uint64_t dcc_offset;
1362 uint64_t htile_offset;
1363 bool tc_compatible_htile;
1364 struct radeon_surf surface;
1365
1366 struct radv_fmask_info fmask;
1367 struct radv_cmask_info cmask;
1368 uint64_t clear_value_offset;
1369 uint64_t dcc_pred_offset;
1370 };
1371
1372 /* Whether the image has a htile that is known consistent with the contents of
1373 * the image. */
1374 bool radv_layout_has_htile(const struct radv_image *image,
1375 VkImageLayout layout,
1376 unsigned queue_mask);
1377
1378 /* Whether the image has a htile that is known consistent with the contents of
1379 * the image and is allowed to be in compressed form.
1380 *
1381 * If this is false reads that don't use the htile should be able to return
1382 * correct results.
1383 */
1384 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1385 VkImageLayout layout,
1386 unsigned queue_mask);
1387
1388 bool radv_layout_can_fast_clear(const struct radv_image *image,
1389 VkImageLayout layout,
1390 unsigned queue_mask);
1391
1392 bool radv_layout_dcc_compressed(const struct radv_image *image,
1393 VkImageLayout layout,
1394 unsigned queue_mask);
1395
1396 static inline bool
1397 radv_vi_dcc_enabled(const struct radv_image *image, unsigned level)
1398 {
1399 return image->surface.dcc_size && level < image->surface.num_dcc_levels;
1400 }
1401
1402 static inline bool
1403 radv_htile_enabled(const struct radv_image *image, unsigned level)
1404 {
1405 return image->surface.htile_size && level == 0;
1406 }
1407
1408 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1409
1410 static inline uint32_t
1411 radv_get_layerCount(const struct radv_image *image,
1412 const VkImageSubresourceRange *range)
1413 {
1414 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1415 image->info.array_size - range->baseArrayLayer : range->layerCount;
1416 }
1417
1418 static inline uint32_t
1419 radv_get_levelCount(const struct radv_image *image,
1420 const VkImageSubresourceRange *range)
1421 {
1422 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1423 image->info.levels - range->baseMipLevel : range->levelCount;
1424 }
1425
1426 struct radeon_bo_metadata;
1427 void
1428 radv_init_metadata(struct radv_device *device,
1429 struct radv_image *image,
1430 struct radeon_bo_metadata *metadata);
1431
1432 struct radv_image_view {
1433 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1434 struct radeon_winsys_bo *bo;
1435
1436 VkImageViewType type;
1437 VkImageAspectFlags aspect_mask;
1438 VkFormat vk_format;
1439 uint32_t base_layer;
1440 uint32_t layer_count;
1441 uint32_t base_mip;
1442 uint32_t level_count;
1443 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1444
1445 uint32_t descriptor[16];
1446
1447 /* Descriptor for use as a storage image as opposed to a sampled image.
1448 * This has a few differences for cube maps (e.g. type).
1449 */
1450 uint32_t storage_descriptor[16];
1451 };
1452
1453 struct radv_image_create_info {
1454 const VkImageCreateInfo *vk_info;
1455 bool scanout;
1456 };
1457
1458 VkResult radv_image_create(VkDevice _device,
1459 const struct radv_image_create_info *info,
1460 const VkAllocationCallbacks* alloc,
1461 VkImage *pImage);
1462
1463 void radv_image_view_init(struct radv_image_view *view,
1464 struct radv_device *device,
1465 const VkImageViewCreateInfo* pCreateInfo);
1466
1467 struct radv_buffer_view {
1468 struct radeon_winsys_bo *bo;
1469 VkFormat vk_format;
1470 uint64_t range; /**< VkBufferViewCreateInfo::range */
1471 uint32_t state[4];
1472 };
1473 void radv_buffer_view_init(struct radv_buffer_view *view,
1474 struct radv_device *device,
1475 const VkBufferViewCreateInfo* pCreateInfo);
1476
1477 static inline struct VkExtent3D
1478 radv_sanitize_image_extent(const VkImageType imageType,
1479 const struct VkExtent3D imageExtent)
1480 {
1481 switch (imageType) {
1482 case VK_IMAGE_TYPE_1D:
1483 return (VkExtent3D) { imageExtent.width, 1, 1 };
1484 case VK_IMAGE_TYPE_2D:
1485 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1486 case VK_IMAGE_TYPE_3D:
1487 return imageExtent;
1488 default:
1489 unreachable("invalid image type");
1490 }
1491 }
1492
1493 static inline struct VkOffset3D
1494 radv_sanitize_image_offset(const VkImageType imageType,
1495 const struct VkOffset3D imageOffset)
1496 {
1497 switch (imageType) {
1498 case VK_IMAGE_TYPE_1D:
1499 return (VkOffset3D) { imageOffset.x, 0, 0 };
1500 case VK_IMAGE_TYPE_2D:
1501 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1502 case VK_IMAGE_TYPE_3D:
1503 return imageOffset;
1504 default:
1505 unreachable("invalid image type");
1506 }
1507 }
1508
1509 static inline bool
1510 radv_image_extent_compare(const struct radv_image *image,
1511 const VkExtent3D *extent)
1512 {
1513 if (extent->width != image->info.width ||
1514 extent->height != image->info.height ||
1515 extent->depth != image->info.depth)
1516 return false;
1517 return true;
1518 }
1519
1520 struct radv_sampler {
1521 uint32_t state[4];
1522 };
1523
1524 struct radv_color_buffer_info {
1525 uint64_t cb_color_base;
1526 uint64_t cb_color_cmask;
1527 uint64_t cb_color_fmask;
1528 uint64_t cb_dcc_base;
1529 uint32_t cb_color_pitch;
1530 uint32_t cb_color_slice;
1531 uint32_t cb_color_view;
1532 uint32_t cb_color_info;
1533 uint32_t cb_color_attrib;
1534 uint32_t cb_color_attrib2;
1535 uint32_t cb_dcc_control;
1536 uint32_t cb_color_cmask_slice;
1537 uint32_t cb_color_fmask_slice;
1538 };
1539
1540 struct radv_ds_buffer_info {
1541 uint64_t db_z_read_base;
1542 uint64_t db_stencil_read_base;
1543 uint64_t db_z_write_base;
1544 uint64_t db_stencil_write_base;
1545 uint64_t db_htile_data_base;
1546 uint32_t db_depth_info;
1547 uint32_t db_z_info;
1548 uint32_t db_stencil_info;
1549 uint32_t db_depth_view;
1550 uint32_t db_depth_size;
1551 uint32_t db_depth_slice;
1552 uint32_t db_htile_surface;
1553 uint32_t pa_su_poly_offset_db_fmt_cntl;
1554 uint32_t db_z_info2;
1555 uint32_t db_stencil_info2;
1556 float offset_scale;
1557 };
1558
1559 struct radv_attachment_info {
1560 union {
1561 struct radv_color_buffer_info cb;
1562 struct radv_ds_buffer_info ds;
1563 };
1564 struct radv_image_view *attachment;
1565 };
1566
1567 struct radv_framebuffer {
1568 uint32_t width;
1569 uint32_t height;
1570 uint32_t layers;
1571
1572 uint32_t attachment_count;
1573 struct radv_attachment_info attachments[0];
1574 };
1575
1576 struct radv_subpass_barrier {
1577 VkPipelineStageFlags src_stage_mask;
1578 VkAccessFlags src_access_mask;
1579 VkAccessFlags dst_access_mask;
1580 };
1581
1582 struct radv_subpass {
1583 uint32_t input_count;
1584 uint32_t color_count;
1585 VkAttachmentReference * input_attachments;
1586 VkAttachmentReference * color_attachments;
1587 VkAttachmentReference * resolve_attachments;
1588 VkAttachmentReference depth_stencil_attachment;
1589
1590 /** Subpass has at least one resolve attachment */
1591 bool has_resolve;
1592
1593 struct radv_subpass_barrier start_barrier;
1594
1595 uint32_t view_mask;
1596 };
1597
1598 struct radv_render_pass_attachment {
1599 VkFormat format;
1600 uint32_t samples;
1601 VkAttachmentLoadOp load_op;
1602 VkAttachmentLoadOp stencil_load_op;
1603 VkImageLayout initial_layout;
1604 VkImageLayout final_layout;
1605 uint32_t view_mask;
1606 };
1607
1608 struct radv_render_pass {
1609 uint32_t attachment_count;
1610 uint32_t subpass_count;
1611 VkAttachmentReference * subpass_attachments;
1612 struct radv_render_pass_attachment * attachments;
1613 struct radv_subpass_barrier end_barrier;
1614 struct radv_subpass subpasses[0];
1615 };
1616
1617 VkResult radv_device_init_meta(struct radv_device *device);
1618 void radv_device_finish_meta(struct radv_device *device);
1619
1620 struct radv_query_pool {
1621 struct radeon_winsys_bo *bo;
1622 uint32_t stride;
1623 uint32_t availability_offset;
1624 char *ptr;
1625 VkQueryType type;
1626 uint32_t pipeline_stats_mask;
1627 };
1628
1629 struct radv_semaphore {
1630 /* use a winsys sem for non-exportable */
1631 struct radeon_winsys_sem *sem;
1632 uint32_t syncobj;
1633 uint32_t temp_syncobj;
1634 };
1635
1636 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
1637 int num_wait_sems,
1638 const VkSemaphore *wait_sems,
1639 int num_signal_sems,
1640 const VkSemaphore *signal_sems,
1641 VkFence fence);
1642 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info);
1643
1644 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1645 struct radv_descriptor_set *set,
1646 unsigned idx);
1647
1648 void
1649 radv_update_descriptor_sets(struct radv_device *device,
1650 struct radv_cmd_buffer *cmd_buffer,
1651 VkDescriptorSet overrideSet,
1652 uint32_t descriptorWriteCount,
1653 const VkWriteDescriptorSet *pDescriptorWrites,
1654 uint32_t descriptorCopyCount,
1655 const VkCopyDescriptorSet *pDescriptorCopies);
1656
1657 void
1658 radv_update_descriptor_set_with_template(struct radv_device *device,
1659 struct radv_cmd_buffer *cmd_buffer,
1660 struct radv_descriptor_set *set,
1661 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
1662 const void *pData);
1663
1664 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1665 VkPipelineBindPoint pipelineBindPoint,
1666 VkPipelineLayout _layout,
1667 uint32_t set,
1668 uint32_t descriptorWriteCount,
1669 const VkWriteDescriptorSet *pDescriptorWrites);
1670
1671 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
1672 struct radv_image *image, uint32_t value);
1673 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1674 struct radv_image *image, uint32_t value);
1675
1676 struct radv_fence {
1677 struct radeon_winsys_fence *fence;
1678 bool submitted;
1679 bool signalled;
1680
1681 uint32_t syncobj;
1682 uint32_t temp_syncobj;
1683 };
1684
1685 struct radeon_winsys_sem;
1686
1687 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1688 \
1689 static inline struct __radv_type * \
1690 __radv_type ## _from_handle(__VkType _handle) \
1691 { \
1692 return (struct __radv_type *) _handle; \
1693 } \
1694 \
1695 static inline __VkType \
1696 __radv_type ## _to_handle(struct __radv_type *_obj) \
1697 { \
1698 return (__VkType) _obj; \
1699 }
1700
1701 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1702 \
1703 static inline struct __radv_type * \
1704 __radv_type ## _from_handle(__VkType _handle) \
1705 { \
1706 return (struct __radv_type *)(uintptr_t) _handle; \
1707 } \
1708 \
1709 static inline __VkType \
1710 __radv_type ## _to_handle(struct __radv_type *_obj) \
1711 { \
1712 return (__VkType)(uintptr_t) _obj; \
1713 }
1714
1715 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1716 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1717
1718 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1719 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1720 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1721 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1722 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1723
1724 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1725 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1726 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1727 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1728 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1729 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1730 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
1731 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1732 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1733 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1734 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1735 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1736 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1737 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1738 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1739 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1740 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1741 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1742 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1743 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1744 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
1745
1746 #endif /* RADV_PRIVATE_H */