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radv/meta: add resolve pass using fragment/vertex shaders
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include <amdgpu.h>
47 #include "compiler/shader_enums.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "util/vk_alloc.h"
51 #include "main/macros.h"
52
53 #include "radv_radeon_winsys.h"
54 #include "ac_binary.h"
55 #include "ac_nir_to_llvm.h"
56 #include "radv_debug.h"
57 #include "radv_descriptor_set.h"
58
59 #include <llvm-c/TargetMachine.h>
60
61 /* Pre-declarations needed for WSI entrypoints */
62 struct wl_surface;
63 struct wl_display;
64 typedef struct xcb_connection_t xcb_connection_t;
65 typedef uint32_t xcb_visualid_t;
66 typedef uint32_t xcb_window_t;
67
68 #include <vulkan/vulkan.h>
69 #include <vulkan/vulkan_intel.h>
70 #include <vulkan/vk_icd.h>
71
72 #include "radv_entrypoints.h"
73
74 #include "wsi_common.h"
75
76 #define MAX_VBS 32
77 #define MAX_VERTEX_ATTRIBS 32
78 #define MAX_RTS 8
79 #define MAX_VIEWPORTS 16
80 #define MAX_SCISSORS 16
81 #define MAX_PUSH_CONSTANTS_SIZE 128
82 #define MAX_PUSH_DESCRIPTORS 32
83 #define MAX_DYNAMIC_BUFFERS 16
84 #define MAX_SAMPLES_LOG2 4
85 #define NUM_META_FS_KEYS 11
86 #define RADV_MAX_DRM_DEVICES 8
87
88 #define NUM_DEPTH_CLEAR_PIPELINES 3
89
90 enum radv_mem_heap {
91 RADV_MEM_HEAP_VRAM,
92 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
93 RADV_MEM_HEAP_GTT,
94 RADV_MEM_HEAP_COUNT
95 };
96
97 enum radv_mem_type {
98 RADV_MEM_TYPE_VRAM,
99 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
100 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
101 RADV_MEM_TYPE_GTT_CACHED,
102 RADV_MEM_TYPE_COUNT
103 };
104
105 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
106
107 static inline uint32_t
108 align_u32(uint32_t v, uint32_t a)
109 {
110 assert(a != 0 && a == (a & -a));
111 return (v + a - 1) & ~(a - 1);
112 }
113
114 static inline uint32_t
115 align_u32_npot(uint32_t v, uint32_t a)
116 {
117 return (v + a - 1) / a * a;
118 }
119
120 static inline uint64_t
121 align_u64(uint64_t v, uint64_t a)
122 {
123 assert(a != 0 && a == (a & -a));
124 return (v + a - 1) & ~(a - 1);
125 }
126
127 static inline int32_t
128 align_i32(int32_t v, int32_t a)
129 {
130 assert(a != 0 && a == (a & -a));
131 return (v + a - 1) & ~(a - 1);
132 }
133
134 /** Alignment must be a power of 2. */
135 static inline bool
136 radv_is_aligned(uintmax_t n, uintmax_t a)
137 {
138 assert(a == (a & -a));
139 return (n & (a - 1)) == 0;
140 }
141
142 static inline uint32_t
143 round_up_u32(uint32_t v, uint32_t a)
144 {
145 return (v + a - 1) / a;
146 }
147
148 static inline uint64_t
149 round_up_u64(uint64_t v, uint64_t a)
150 {
151 return (v + a - 1) / a;
152 }
153
154 static inline uint32_t
155 radv_minify(uint32_t n, uint32_t levels)
156 {
157 if (unlikely(n == 0))
158 return 0;
159 else
160 return MAX2(n >> levels, 1);
161 }
162 static inline float
163 radv_clamp_f(float f, float min, float max)
164 {
165 assert(min < max);
166
167 if (f > max)
168 return max;
169 else if (f < min)
170 return min;
171 else
172 return f;
173 }
174
175 static inline bool
176 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
177 {
178 if (*inout_mask & clear_mask) {
179 *inout_mask &= ~clear_mask;
180 return true;
181 } else {
182 return false;
183 }
184 }
185
186 #define for_each_bit(b, dword) \
187 for (uint32_t __dword = (dword); \
188 (b) = __builtin_ffs(__dword) - 1, __dword; \
189 __dword &= ~(1 << (b)))
190
191 #define typed_memcpy(dest, src, count) ({ \
192 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
193 memcpy((dest), (src), (count) * sizeof(*(src))); \
194 })
195
196 #define zero(x) (memset(&(x), 0, sizeof(x)))
197
198 /* Whenever we generate an error, pass it through this function. Useful for
199 * debugging, where we can break on it. Only call at error site, not when
200 * propagating errors. Might be useful to plug in a stack trace here.
201 */
202
203 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
204
205 #ifdef DEBUG
206 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
207 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
208 #else
209 #define vk_error(error) error
210 #define vk_errorf(error, format, ...) error
211 #endif
212
213 void __radv_finishme(const char *file, int line, const char *format, ...)
214 radv_printflike(3, 4);
215 void radv_loge(const char *format, ...) radv_printflike(1, 2);
216 void radv_loge_v(const char *format, va_list va);
217
218 /**
219 * Print a FINISHME message, including its source location.
220 */
221 #define radv_finishme(format, ...) \
222 do { \
223 static bool reported = false; \
224 if (!reported) { \
225 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
226 reported = true; \
227 } \
228 } while (0)
229
230 /* A non-fatal assert. Useful for debugging. */
231 #ifdef DEBUG
232 #define radv_assert(x) ({ \
233 if (unlikely(!(x))) \
234 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
235 })
236 #else
237 #define radv_assert(x)
238 #endif
239
240 #define stub_return(v) \
241 do { \
242 radv_finishme("stub %s", __func__); \
243 return (v); \
244 } while (0)
245
246 #define stub() \
247 do { \
248 radv_finishme("stub %s", __func__); \
249 return; \
250 } while (0)
251
252 void *radv_lookup_entrypoint(const char *name);
253
254 struct radv_extensions {
255 VkExtensionProperties *ext_array;
256 uint32_t num_ext;
257 };
258
259 struct radv_physical_device {
260 VK_LOADER_DATA _loader_data;
261
262 struct radv_instance * instance;
263
264 struct radeon_winsys *ws;
265 struct radeon_info rad_info;
266 char path[20];
267 const char * name;
268 uint8_t uuid[VK_UUID_SIZE];
269
270 int local_fd;
271 struct wsi_device wsi_device;
272 struct radv_extensions extensions;
273 };
274
275 struct radv_instance {
276 VK_LOADER_DATA _loader_data;
277
278 VkAllocationCallbacks alloc;
279
280 uint32_t apiVersion;
281 int physicalDeviceCount;
282 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
283
284 uint64_t debug_flags;
285 };
286
287 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
288 void radv_finish_wsi(struct radv_physical_device *physical_device);
289
290 struct cache_entry;
291
292 struct radv_pipeline_cache {
293 struct radv_device * device;
294 pthread_mutex_t mutex;
295
296 uint32_t total_size;
297 uint32_t table_size;
298 uint32_t kernel_count;
299 struct cache_entry ** hash_table;
300 bool modified;
301
302 VkAllocationCallbacks alloc;
303 };
304
305 void
306 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
307 struct radv_device *device);
308 void
309 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
310 void
311 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
312 const void *data, size_t size);
313
314 struct radv_shader_variant *
315 radv_create_shader_variant_from_pipeline_cache(struct radv_device *device,
316 struct radv_pipeline_cache *cache,
317 const unsigned char *sha1);
318
319 struct radv_shader_variant *
320 radv_pipeline_cache_insert_shader(struct radv_pipeline_cache *cache,
321 const unsigned char *sha1,
322 struct radv_shader_variant *variant,
323 const void *code, unsigned code_size);
324
325 void radv_shader_variant_destroy(struct radv_device *device,
326 struct radv_shader_variant *variant);
327
328 struct radv_meta_state {
329 VkAllocationCallbacks alloc;
330
331 struct radv_pipeline_cache cache;
332
333 /**
334 * Use array element `i` for images with `2^i` samples.
335 */
336 struct {
337 VkRenderPass render_pass[NUM_META_FS_KEYS];
338 struct radv_pipeline *color_pipelines[NUM_META_FS_KEYS];
339
340 VkRenderPass depthstencil_rp;
341 struct radv_pipeline *depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
342 struct radv_pipeline *stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
343 struct radv_pipeline *depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
344 } clear[1 + MAX_SAMPLES_LOG2];
345
346 struct {
347 VkRenderPass render_pass[NUM_META_FS_KEYS];
348
349 /** Pipeline that blits from a 1D image. */
350 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
351
352 /** Pipeline that blits from a 2D image. */
353 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
354
355 /** Pipeline that blits from a 3D image. */
356 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
357
358 VkRenderPass depth_only_rp;
359 VkPipeline depth_only_1d_pipeline;
360 VkPipeline depth_only_2d_pipeline;
361 VkPipeline depth_only_3d_pipeline;
362
363 VkRenderPass stencil_only_rp;
364 VkPipeline stencil_only_1d_pipeline;
365 VkPipeline stencil_only_2d_pipeline;
366 VkPipeline stencil_only_3d_pipeline;
367 VkPipelineLayout pipeline_layout;
368 VkDescriptorSetLayout ds_layout;
369 } blit;
370
371 struct {
372 VkRenderPass render_passes[NUM_META_FS_KEYS];
373
374 VkPipelineLayout p_layouts[2];
375 VkDescriptorSetLayout ds_layouts[2];
376 VkPipeline pipelines[2][NUM_META_FS_KEYS];
377
378 VkRenderPass depth_only_rp;
379 VkPipeline depth_only_pipeline[2];
380
381 VkRenderPass stencil_only_rp;
382 VkPipeline stencil_only_pipeline[2];
383 } blit2d;
384
385 struct {
386 VkPipelineLayout img_p_layout;
387 VkDescriptorSetLayout img_ds_layout;
388 VkPipeline pipeline;
389 } itob;
390 struct {
391 VkRenderPass render_pass;
392 VkPipelineLayout img_p_layout;
393 VkDescriptorSetLayout img_ds_layout;
394 VkPipeline pipeline;
395 } btoi;
396 struct {
397 VkPipelineLayout img_p_layout;
398 VkDescriptorSetLayout img_ds_layout;
399 VkPipeline pipeline;
400 } itoi;
401 struct {
402 VkPipelineLayout img_p_layout;
403 VkDescriptorSetLayout img_ds_layout;
404 VkPipeline pipeline;
405 } cleari;
406
407 struct {
408 VkPipeline pipeline;
409 VkRenderPass pass;
410 } resolve;
411
412 struct {
413 VkDescriptorSetLayout ds_layout;
414 VkPipelineLayout p_layout;
415 struct {
416 VkPipeline pipeline;
417 VkPipeline i_pipeline;
418 VkPipeline srgb_pipeline;
419 } rc[MAX_SAMPLES_LOG2];
420 } resolve_compute;
421
422 struct {
423 VkDescriptorSetLayout ds_layout;
424 VkPipelineLayout p_layout;
425
426 struct {
427 VkRenderPass render_pass[NUM_META_FS_KEYS];
428 VkPipeline pipeline[NUM_META_FS_KEYS];
429 } rc[MAX_SAMPLES_LOG2];
430 } resolve_fragment;
431
432 struct {
433 VkPipeline decompress_pipeline;
434 VkPipeline resummarize_pipeline;
435 VkRenderPass pass;
436 } depth_decomp;
437
438 struct {
439 VkPipeline cmask_eliminate_pipeline;
440 VkPipeline fmask_decompress_pipeline;
441 VkRenderPass pass;
442 } fast_clear_flush;
443
444 struct {
445 VkPipelineLayout fill_p_layout;
446 VkPipelineLayout copy_p_layout;
447 VkDescriptorSetLayout fill_ds_layout;
448 VkDescriptorSetLayout copy_ds_layout;
449 VkPipeline fill_pipeline;
450 VkPipeline copy_pipeline;
451 } buffer;
452
453 struct {
454 VkDescriptorSetLayout ds_layout;
455 VkPipelineLayout p_layout;
456 VkPipeline occlusion_query_pipeline;
457 VkPipeline pipeline_statistics_query_pipeline;
458 } query;
459 };
460
461 /* queue types */
462 #define RADV_QUEUE_GENERAL 0
463 #define RADV_QUEUE_COMPUTE 1
464 #define RADV_QUEUE_TRANSFER 2
465
466 #define RADV_MAX_QUEUE_FAMILIES 3
467
468 enum ring_type radv_queue_family_to_ring(int f);
469
470 struct radv_queue {
471 VK_LOADER_DATA _loader_data;
472 struct radv_device * device;
473 struct radeon_winsys_ctx *hw_ctx;
474 int queue_family_index;
475 int queue_idx;
476
477 uint32_t scratch_size;
478 uint32_t compute_scratch_size;
479 uint32_t esgs_ring_size;
480 uint32_t gsvs_ring_size;
481 bool has_tess_rings;
482 bool has_sample_positions;
483
484 struct radeon_winsys_bo *scratch_bo;
485 struct radeon_winsys_bo *descriptor_bo;
486 struct radeon_winsys_bo *compute_scratch_bo;
487 struct radeon_winsys_bo *esgs_ring_bo;
488 struct radeon_winsys_bo *gsvs_ring_bo;
489 struct radeon_winsys_bo *tess_factor_ring_bo;
490 struct radeon_winsys_bo *tess_offchip_ring_bo;
491 struct radeon_winsys_cs *initial_preamble_cs;
492 struct radeon_winsys_cs *continue_preamble_cs;
493 };
494
495 struct radv_device {
496 VK_LOADER_DATA _loader_data;
497
498 VkAllocationCallbacks alloc;
499
500 struct radv_instance * instance;
501 struct radeon_winsys *ws;
502
503 struct radv_meta_state meta_state;
504
505 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
506 int queue_count[RADV_MAX_QUEUE_FAMILIES];
507 struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
508 struct radeon_winsys_cs *flush_cs[RADV_MAX_QUEUE_FAMILIES];
509 struct radeon_winsys_cs *flush_shader_cs[RADV_MAX_QUEUE_FAMILIES];
510 uint64_t debug_flags;
511
512 bool llvm_supports_spill;
513 bool has_distributed_tess;
514 uint32_t tess_offchip_block_dw_size;
515 uint32_t scratch_waves;
516
517 uint32_t gs_table_depth;
518
519 /* MSAA sample locations.
520 * The first index is the sample index.
521 * The second index is the coordinate: X, Y. */
522 float sample_locations_1x[1][2];
523 float sample_locations_2x[2][2];
524 float sample_locations_4x[4][2];
525 float sample_locations_8x[8][2];
526 float sample_locations_16x[16][2];
527
528 /* CIK and later */
529 uint32_t gfx_init_size_dw;
530 struct radeon_winsys_bo *gfx_init;
531
532 struct radeon_winsys_bo *trace_bo;
533 uint32_t *trace_id_ptr;
534
535 struct radv_physical_device *physical_device;
536
537 /* Backup in-memory cache to be used if the app doesn't provide one */
538 struct radv_pipeline_cache * mem_cache;
539 };
540
541 struct radv_device_memory {
542 struct radeon_winsys_bo *bo;
543 /* for dedicated allocations */
544 struct radv_image *image;
545 struct radv_buffer *buffer;
546 uint32_t type_index;
547 VkDeviceSize map_size;
548 void * map;
549 };
550
551
552 struct radv_descriptor_range {
553 uint64_t va;
554 uint32_t size;
555 };
556
557 struct radv_descriptor_set {
558 const struct radv_descriptor_set_layout *layout;
559 uint32_t size;
560
561 struct radeon_winsys_bo *bo;
562 uint64_t va;
563 uint32_t *mapped_ptr;
564 struct radv_descriptor_range *dynamic_descriptors;
565
566 struct list_head vram_list;
567
568 struct radeon_winsys_bo *descriptors[0];
569 };
570
571 struct radv_push_descriptor_set
572 {
573 struct radv_descriptor_set set;
574 uint32_t capacity;
575 };
576
577 struct radv_descriptor_pool {
578 struct radeon_winsys_bo *bo;
579 uint8_t *mapped_ptr;
580 uint64_t current_offset;
581 uint64_t size;
582
583 struct list_head vram_list;
584
585 uint8_t *host_memory_base;
586 uint8_t *host_memory_ptr;
587 uint8_t *host_memory_end;
588 };
589
590 struct radv_descriptor_update_template_entry {
591 VkDescriptorType descriptor_type;
592
593 /* The number of descriptors to update */
594 uint32_t descriptor_count;
595
596 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
597 uint32_t dst_offset;
598
599 /* In dwords. Not valid/used for dynamic descriptors */
600 uint32_t dst_stride;
601
602 uint32_t buffer_offset;
603
604 /* Only valid for combined image samplers and samplers */
605 uint16_t has_sampler;
606
607 /* In bytes */
608 size_t src_offset;
609 size_t src_stride;
610
611 /* For push descriptors */
612 const uint32_t *immutable_samplers;
613 };
614
615 struct radv_descriptor_update_template {
616 uint32_t entry_count;
617 struct radv_descriptor_update_template_entry entry[0];
618 };
619
620 struct radv_buffer {
621 struct radv_device * device;
622 VkDeviceSize size;
623
624 VkBufferUsageFlags usage;
625 VkBufferCreateFlags flags;
626
627 /* Set when bound */
628 struct radeon_winsys_bo * bo;
629 VkDeviceSize offset;
630 };
631
632
633 enum radv_cmd_dirty_bits {
634 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
635 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
636 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
637 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
638 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
639 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
640 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
641 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
642 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
643 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
644 RADV_CMD_DIRTY_PIPELINE = 1 << 9,
645 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
646 RADV_CMD_DIRTY_RENDER_TARGETS = 1 << 11,
647 };
648 typedef uint32_t radv_cmd_dirty_mask_t;
649
650 enum radv_cmd_flush_bits {
651 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
652 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
653 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
654 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
655 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
656 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
657 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
658 /* Same as above, but only writes back and doesn't invalidate */
659 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
660 /* Framebuffer caches */
661 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
662 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
663 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
664 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
665 /* Engine synchronization. */
666 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
667 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
668 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
669 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
670
671 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
672 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
673 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
674 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
675 };
676
677 struct radv_vertex_binding {
678 struct radv_buffer * buffer;
679 VkDeviceSize offset;
680 };
681
682 struct radv_dynamic_state {
683 struct {
684 uint32_t count;
685 VkViewport viewports[MAX_VIEWPORTS];
686 } viewport;
687
688 struct {
689 uint32_t count;
690 VkRect2D scissors[MAX_SCISSORS];
691 } scissor;
692
693 float line_width;
694
695 struct {
696 float bias;
697 float clamp;
698 float slope;
699 } depth_bias;
700
701 float blend_constants[4];
702
703 struct {
704 float min;
705 float max;
706 } depth_bounds;
707
708 struct {
709 uint32_t front;
710 uint32_t back;
711 } stencil_compare_mask;
712
713 struct {
714 uint32_t front;
715 uint32_t back;
716 } stencil_write_mask;
717
718 struct {
719 uint32_t front;
720 uint32_t back;
721 } stencil_reference;
722 };
723
724 extern const struct radv_dynamic_state default_dynamic_state;
725
726 void radv_dynamic_state_copy(struct radv_dynamic_state *dest,
727 const struct radv_dynamic_state *src,
728 uint32_t copy_mask);
729 /**
730 * Attachment state when recording a renderpass instance.
731 *
732 * The clear value is valid only if there exists a pending clear.
733 */
734 struct radv_attachment_state {
735 VkImageAspectFlags pending_clear_aspects;
736 VkClearValue clear_value;
737 VkImageLayout current_layout;
738 };
739
740 struct radv_cmd_state {
741 uint32_t vb_dirty;
742 radv_cmd_dirty_mask_t dirty;
743 bool vertex_descriptors_dirty;
744 bool push_descriptors_dirty;
745
746 struct radv_pipeline * pipeline;
747 struct radv_pipeline * emitted_pipeline;
748 struct radv_pipeline * compute_pipeline;
749 struct radv_pipeline * emitted_compute_pipeline;
750 struct radv_framebuffer * framebuffer;
751 struct radv_render_pass * pass;
752 const struct radv_subpass * subpass;
753 struct radv_dynamic_state dynamic;
754 struct radv_vertex_binding vertex_bindings[MAX_VBS];
755 struct radv_descriptor_set * descriptors[MAX_SETS];
756 struct radv_attachment_state * attachments;
757 VkRect2D render_area;
758 struct radv_buffer * index_buffer;
759 uint32_t index_type;
760 uint32_t index_offset;
761 int32_t last_primitive_reset_en;
762 uint32_t last_primitive_reset_index;
763 enum radv_cmd_flush_bits flush_bits;
764 unsigned active_occlusion_queries;
765 float offset_scale;
766 uint32_t descriptors_dirty;
767 uint32_t trace_id;
768 uint32_t last_ia_multi_vgt_param;
769 };
770
771 struct radv_cmd_pool {
772 VkAllocationCallbacks alloc;
773 struct list_head cmd_buffers;
774 struct list_head free_cmd_buffers;
775 uint32_t queue_family_index;
776 };
777
778 struct radv_cmd_buffer_upload {
779 uint8_t *map;
780 unsigned offset;
781 uint64_t size;
782 struct radeon_winsys_bo *upload_bo;
783 struct list_head list;
784 };
785
786 struct radv_cmd_buffer {
787 VK_LOADER_DATA _loader_data;
788
789 struct radv_device * device;
790
791 struct radv_cmd_pool * pool;
792 struct list_head pool_link;
793
794 VkCommandBufferUsageFlags usage_flags;
795 VkCommandBufferLevel level;
796 struct radeon_winsys_cs *cs;
797 struct radv_cmd_state state;
798 uint32_t queue_family_index;
799
800 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
801 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
802 VkShaderStageFlags push_constant_stages;
803 struct radv_push_descriptor_set push_descriptors;
804 struct radv_descriptor_set meta_push_descriptors;
805
806 struct radv_cmd_buffer_upload upload;
807
808 uint32_t scratch_size_needed;
809 uint32_t compute_scratch_size_needed;
810 uint32_t esgs_ring_size_needed;
811 uint32_t gsvs_ring_size_needed;
812 bool tess_rings_needed;
813 bool sample_positions_needed;
814
815 bool record_fail;
816
817 int ring_offsets_idx; /* just used for verification */
818 };
819
820 struct radv_image;
821
822 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
823
824 void si_init_compute(struct radv_cmd_buffer *cmd_buffer);
825 void si_init_config(struct radv_cmd_buffer *cmd_buffer);
826
827 void cik_create_gfx_config(struct radv_device *device);
828
829 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
830 int count, const VkViewport *viewports);
831 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
832 int count, const VkRect2D *scissors,
833 const VkViewport *viewports, bool can_use_guardband);
834 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
835 bool instanced_draw, bool indirect_draw,
836 uint32_t draw_vertex_count);
837 void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
838 enum chip_class chip_class,
839 bool is_mec,
840 enum radv_cmd_flush_bits flush_bits);
841 void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
842 enum chip_class chip_class,
843 bool is_mec,
844 enum radv_cmd_flush_bits flush_bits);
845 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
846 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
847 uint64_t src_va, uint64_t dest_va,
848 uint64_t size);
849 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
850 unsigned size);
851 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
852 uint64_t size, unsigned value);
853 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
854 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
855 struct radv_descriptor_set *set,
856 unsigned idx);
857 bool
858 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
859 unsigned size,
860 unsigned alignment,
861 unsigned *out_offset,
862 void **ptr);
863 void
864 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
865 const struct radv_subpass *subpass,
866 bool transitions);
867 bool
868 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
869 unsigned size, unsigned alignmnet,
870 const void *data, unsigned *out_offset);
871 void
872 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer);
873 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
874 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
875 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
876 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
877 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
878 unsigned radv_cayman_get_maxdist(int log_samples);
879 void radv_device_init_msaa(struct radv_device *device);
880 void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
881 struct radv_image *image,
882 VkClearDepthStencilValue ds_clear_value,
883 VkImageAspectFlags aspects);
884 void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
885 struct radv_image *image,
886 int idx,
887 uint32_t color_values[2]);
888 void radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
889 struct radeon_winsys_bo *bo,
890 uint64_t offset, uint64_t size, uint32_t value);
891 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
892 bool radv_get_memory_fd(struct radv_device *device,
893 struct radv_device_memory *memory,
894 int *pFD);
895 /*
896 * Takes x,y,z as exact numbers of invocations, instead of blocks.
897 *
898 * Limitations: Can't call normal dispatch functions without binding or rebinding
899 * the compute pipeline.
900 */
901 void radv_unaligned_dispatch(
902 struct radv_cmd_buffer *cmd_buffer,
903 uint32_t x,
904 uint32_t y,
905 uint32_t z);
906
907 struct radv_event {
908 struct radeon_winsys_bo *bo;
909 uint64_t *map;
910 };
911
912 struct nir_shader;
913
914 struct radv_shader_module {
915 struct nir_shader * nir;
916 unsigned char sha1[20];
917 uint32_t size;
918 char data[0];
919 };
920
921 union ac_shader_variant_key;
922
923 void
924 radv_hash_shader(unsigned char *hash, struct radv_shader_module *module,
925 const char *entrypoint,
926 const VkSpecializationInfo *spec_info,
927 const struct radv_pipeline_layout *layout,
928 const union ac_shader_variant_key *key,
929 uint32_t is_geom_copy_shader);
930
931 static inline gl_shader_stage
932 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
933 {
934 assert(__builtin_popcount(vk_stage) == 1);
935 return ffs(vk_stage) - 1;
936 }
937
938 static inline VkShaderStageFlagBits
939 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
940 {
941 return (1 << mesa_stage);
942 }
943
944 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
945
946 #define radv_foreach_stage(stage, stage_bits) \
947 for (gl_shader_stage stage, \
948 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
949 stage = __builtin_ffs(__tmp) - 1, __tmp; \
950 __tmp &= ~(1 << (stage)))
951
952 struct radv_shader_variant {
953 uint32_t ref_count;
954
955 struct radeon_winsys_bo *bo;
956 struct ac_shader_config config;
957 struct ac_shader_variant_info info;
958 unsigned rsrc1;
959 unsigned rsrc2;
960 uint32_t code_size;
961 };
962
963 struct radv_depth_stencil_state {
964 uint32_t db_depth_control;
965 uint32_t db_stencil_control;
966 uint32_t db_render_control;
967 uint32_t db_render_override2;
968 };
969
970 struct radv_blend_state {
971 uint32_t cb_color_control;
972 uint32_t cb_target_mask;
973 uint32_t sx_mrt0_blend_opt[8];
974 uint32_t cb_blend_control[8];
975
976 uint32_t spi_shader_col_format;
977 uint32_t cb_shader_mask;
978 uint32_t db_alpha_to_mask;
979 };
980
981 unsigned radv_format_meta_fs_key(VkFormat format);
982
983 struct radv_raster_state {
984 uint32_t pa_cl_clip_cntl;
985 uint32_t spi_interp_control;
986 uint32_t pa_su_point_size;
987 uint32_t pa_su_point_minmax;
988 uint32_t pa_su_line_cntl;
989 uint32_t pa_su_vtx_cntl;
990 uint32_t pa_su_sc_mode_cntl;
991 };
992
993 struct radv_multisample_state {
994 uint32_t db_eqaa;
995 uint32_t pa_sc_line_cntl;
996 uint32_t pa_sc_mode_cntl_0;
997 uint32_t pa_sc_mode_cntl_1;
998 uint32_t pa_sc_aa_config;
999 uint32_t pa_sc_aa_mask[2];
1000 unsigned num_samples;
1001 };
1002
1003 struct radv_prim_vertex_count {
1004 uint8_t min;
1005 uint8_t incr;
1006 };
1007
1008 struct radv_tessellation_state {
1009 uint32_t ls_hs_config;
1010 uint32_t tcs_in_layout;
1011 uint32_t tcs_out_layout;
1012 uint32_t tcs_out_offsets;
1013 uint32_t offchip_layout;
1014 unsigned num_patches;
1015 unsigned lds_size;
1016 unsigned num_tcs_input_cp;
1017 uint32_t tf_param;
1018 };
1019
1020 struct radv_pipeline {
1021 struct radv_device * device;
1022 uint32_t dynamic_state_mask;
1023 struct radv_dynamic_state dynamic_state;
1024
1025 struct radv_pipeline_layout * layout;
1026
1027 bool needs_data_cache;
1028 bool need_indirect_descriptor_sets;
1029 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1030 struct radv_shader_variant *gs_copy_shader;
1031 VkShaderStageFlags active_stages;
1032
1033 uint32_t va_rsrc_word3[MAX_VERTEX_ATTRIBS];
1034 uint32_t va_format_size[MAX_VERTEX_ATTRIBS];
1035 uint32_t va_binding[MAX_VERTEX_ATTRIBS];
1036 uint32_t va_offset[MAX_VERTEX_ATTRIBS];
1037 uint32_t num_vertex_attribs;
1038 uint32_t binding_stride[MAX_VBS];
1039
1040 union {
1041 struct {
1042 struct radv_blend_state blend;
1043 struct radv_depth_stencil_state ds;
1044 struct radv_raster_state raster;
1045 struct radv_multisample_state ms;
1046 struct radv_tessellation_state tess;
1047 uint32_t db_shader_control;
1048 uint32_t shader_z_format;
1049 unsigned prim;
1050 unsigned gs_out;
1051 uint32_t vgt_gs_mode;
1052 bool prim_restart_enable;
1053 unsigned esgs_ring_size;
1054 unsigned gsvs_ring_size;
1055 uint32_t ps_input_cntl[32];
1056 uint32_t ps_input_cntl_num;
1057 uint32_t pa_cl_vs_out_cntl;
1058 uint32_t vgt_shader_stages_en;
1059 struct radv_prim_vertex_count prim_vertex_count;
1060 bool can_use_guardband;
1061 } graphics;
1062 };
1063
1064 unsigned max_waves;
1065 unsigned scratch_bytes_per_wave;
1066 };
1067
1068 static inline bool radv_pipeline_has_gs(struct radv_pipeline *pipeline)
1069 {
1070 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1071 }
1072
1073 static inline bool radv_pipeline_has_tess(struct radv_pipeline *pipeline)
1074 {
1075 return pipeline->shaders[MESA_SHADER_TESS_EVAL] ? true : false;
1076 }
1077
1078 struct radv_graphics_pipeline_create_info {
1079 bool use_rectlist;
1080 bool db_depth_clear;
1081 bool db_stencil_clear;
1082 bool db_depth_disable_expclear;
1083 bool db_stencil_disable_expclear;
1084 bool db_flush_depth_inplace;
1085 bool db_flush_stencil_inplace;
1086 bool db_resummarize;
1087 uint32_t custom_blend_mode;
1088 };
1089
1090 VkResult
1091 radv_pipeline_init(struct radv_pipeline *pipeline, struct radv_device *device,
1092 struct radv_pipeline_cache *cache,
1093 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1094 const struct radv_graphics_pipeline_create_info *extra,
1095 const VkAllocationCallbacks *alloc);
1096
1097 VkResult
1098 radv_graphics_pipeline_create(VkDevice device,
1099 VkPipelineCache cache,
1100 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1101 const struct radv_graphics_pipeline_create_info *extra,
1102 const VkAllocationCallbacks *alloc,
1103 VkPipeline *pPipeline);
1104
1105 struct vk_format_description;
1106 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1107 int first_non_void);
1108 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1109 int first_non_void);
1110 uint32_t radv_translate_colorformat(VkFormat format);
1111 uint32_t radv_translate_color_numformat(VkFormat format,
1112 const struct vk_format_description *desc,
1113 int first_non_void);
1114 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1115 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1116 uint32_t radv_translate_dbformat(VkFormat format);
1117 uint32_t radv_translate_tex_dataformat(VkFormat format,
1118 const struct vk_format_description *desc,
1119 int first_non_void);
1120 uint32_t radv_translate_tex_numformat(VkFormat format,
1121 const struct vk_format_description *desc,
1122 int first_non_void);
1123 bool radv_format_pack_clear_color(VkFormat format,
1124 uint32_t clear_vals[2],
1125 VkClearColorValue *value);
1126 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1127
1128 struct radv_fmask_info {
1129 uint64_t offset;
1130 uint64_t size;
1131 unsigned alignment;
1132 unsigned pitch_in_pixels;
1133 unsigned bank_height;
1134 unsigned slice_tile_max;
1135 unsigned tile_mode_index;
1136 };
1137
1138 struct radv_cmask_info {
1139 uint64_t offset;
1140 uint64_t size;
1141 unsigned alignment;
1142 unsigned slice_tile_max;
1143 unsigned base_address_reg;
1144 };
1145
1146 struct r600_htile_info {
1147 uint64_t offset;
1148 uint64_t size;
1149 unsigned pitch;
1150 unsigned height;
1151 unsigned xalign;
1152 unsigned yalign;
1153 };
1154
1155 struct radv_image {
1156 VkImageType type;
1157 /* The original VkFormat provided by the client. This may not match any
1158 * of the actual surface formats.
1159 */
1160 VkFormat vk_format;
1161 VkImageAspectFlags aspects;
1162 struct radeon_surf_info info;
1163 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1164 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1165 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1166
1167 VkDeviceSize size;
1168 uint32_t alignment;
1169
1170 bool exclusive;
1171 unsigned queue_family_mask;
1172
1173 /* Set when bound */
1174 struct radeon_winsys_bo *bo;
1175 VkDeviceSize offset;
1176 uint32_t dcc_offset;
1177 uint32_t htile_offset;
1178 struct radeon_surf surface;
1179
1180 struct radv_fmask_info fmask;
1181 struct radv_cmask_info cmask;
1182 uint32_t clear_value_offset;
1183 };
1184
1185 bool radv_layout_has_htile(const struct radv_image *image,
1186 VkImageLayout layout);
1187 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1188 VkImageLayout layout);
1189 bool radv_layout_can_expclear(const struct radv_image *image,
1190 VkImageLayout layout);
1191 bool radv_layout_can_fast_clear(const struct radv_image *image,
1192 VkImageLayout layout,
1193 unsigned queue_mask);
1194
1195
1196 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1197
1198 static inline uint32_t
1199 radv_get_layerCount(const struct radv_image *image,
1200 const VkImageSubresourceRange *range)
1201 {
1202 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1203 image->info.array_size - range->baseArrayLayer : range->layerCount;
1204 }
1205
1206 static inline uint32_t
1207 radv_get_levelCount(const struct radv_image *image,
1208 const VkImageSubresourceRange *range)
1209 {
1210 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1211 image->info.levels - range->baseMipLevel : range->levelCount;
1212 }
1213
1214 struct radeon_bo_metadata;
1215 void
1216 radv_init_metadata(struct radv_device *device,
1217 struct radv_image *image,
1218 struct radeon_bo_metadata *metadata);
1219
1220 struct radv_image_view {
1221 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1222 struct radeon_winsys_bo *bo;
1223
1224 VkImageViewType type;
1225 VkImageAspectFlags aspect_mask;
1226 VkFormat vk_format;
1227 uint32_t base_layer;
1228 uint32_t layer_count;
1229 uint32_t base_mip;
1230 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1231
1232 uint32_t descriptor[8];
1233 uint32_t fmask_descriptor[8];
1234 };
1235
1236 struct radv_image_create_info {
1237 const VkImageCreateInfo *vk_info;
1238 uint32_t stride;
1239 bool scanout;
1240 };
1241
1242 VkResult radv_image_create(VkDevice _device,
1243 const struct radv_image_create_info *info,
1244 const VkAllocationCallbacks* alloc,
1245 VkImage *pImage);
1246
1247 void radv_image_view_init(struct radv_image_view *view,
1248 struct radv_device *device,
1249 const VkImageViewCreateInfo* pCreateInfo,
1250 struct radv_cmd_buffer *cmd_buffer,
1251 VkImageUsageFlags usage_mask);
1252 void radv_image_set_optimal_micro_tile_mode(struct radv_device *device,
1253 struct radv_image *image, uint32_t micro_tile_mode);
1254 struct radv_buffer_view {
1255 struct radeon_winsys_bo *bo;
1256 VkFormat vk_format;
1257 uint64_t range; /**< VkBufferViewCreateInfo::range */
1258 uint32_t state[4];
1259 };
1260 void radv_buffer_view_init(struct radv_buffer_view *view,
1261 struct radv_device *device,
1262 const VkBufferViewCreateInfo* pCreateInfo,
1263 struct radv_cmd_buffer *cmd_buffer);
1264
1265 static inline struct VkExtent3D
1266 radv_sanitize_image_extent(const VkImageType imageType,
1267 const struct VkExtent3D imageExtent)
1268 {
1269 switch (imageType) {
1270 case VK_IMAGE_TYPE_1D:
1271 return (VkExtent3D) { imageExtent.width, 1, 1 };
1272 case VK_IMAGE_TYPE_2D:
1273 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1274 case VK_IMAGE_TYPE_3D:
1275 return imageExtent;
1276 default:
1277 unreachable("invalid image type");
1278 }
1279 }
1280
1281 static inline struct VkOffset3D
1282 radv_sanitize_image_offset(const VkImageType imageType,
1283 const struct VkOffset3D imageOffset)
1284 {
1285 switch (imageType) {
1286 case VK_IMAGE_TYPE_1D:
1287 return (VkOffset3D) { imageOffset.x, 0, 0 };
1288 case VK_IMAGE_TYPE_2D:
1289 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1290 case VK_IMAGE_TYPE_3D:
1291 return imageOffset;
1292 default:
1293 unreachable("invalid image type");
1294 }
1295 }
1296
1297 static inline bool
1298 radv_image_extent_compare(const struct radv_image *image,
1299 const VkExtent3D *extent)
1300 {
1301 if (extent->width != image->info.width ||
1302 extent->height != image->info.height ||
1303 extent->depth != image->info.depth)
1304 return false;
1305 return true;
1306 }
1307
1308 struct radv_sampler {
1309 uint32_t state[4];
1310 };
1311
1312 struct radv_color_buffer_info {
1313 uint32_t cb_color_base;
1314 uint32_t cb_color_pitch;
1315 uint32_t cb_color_slice;
1316 uint32_t cb_color_view;
1317 uint32_t cb_color_info;
1318 uint32_t cb_color_attrib;
1319 uint32_t cb_dcc_control;
1320 uint32_t cb_color_cmask;
1321 uint32_t cb_color_cmask_slice;
1322 uint32_t cb_color_fmask;
1323 uint32_t cb_color_fmask_slice;
1324 uint32_t cb_clear_value0;
1325 uint32_t cb_clear_value1;
1326 uint32_t cb_dcc_base;
1327 uint32_t micro_tile_mode;
1328 };
1329
1330 struct radv_ds_buffer_info {
1331 uint32_t db_depth_info;
1332 uint32_t db_z_info;
1333 uint32_t db_stencil_info;
1334 uint32_t db_z_read_base;
1335 uint32_t db_stencil_read_base;
1336 uint32_t db_z_write_base;
1337 uint32_t db_stencil_write_base;
1338 uint32_t db_depth_view;
1339 uint32_t db_depth_size;
1340 uint32_t db_depth_slice;
1341 uint32_t db_htile_surface;
1342 uint32_t db_htile_data_base;
1343 uint32_t pa_su_poly_offset_db_fmt_cntl;
1344 float offset_scale;
1345 };
1346
1347 struct radv_attachment_info {
1348 union {
1349 struct radv_color_buffer_info cb;
1350 struct radv_ds_buffer_info ds;
1351 };
1352 struct radv_image_view *attachment;
1353 };
1354
1355 struct radv_framebuffer {
1356 uint32_t width;
1357 uint32_t height;
1358 uint32_t layers;
1359
1360 uint32_t attachment_count;
1361 struct radv_attachment_info attachments[0];
1362 };
1363
1364 struct radv_subpass_barrier {
1365 VkPipelineStageFlags src_stage_mask;
1366 VkAccessFlags src_access_mask;
1367 VkAccessFlags dst_access_mask;
1368 };
1369
1370 struct radv_subpass {
1371 uint32_t input_count;
1372 uint32_t color_count;
1373 VkAttachmentReference * input_attachments;
1374 VkAttachmentReference * color_attachments;
1375 VkAttachmentReference * resolve_attachments;
1376 VkAttachmentReference depth_stencil_attachment;
1377
1378 /** Subpass has at least one resolve attachment */
1379 bool has_resolve;
1380
1381 struct radv_subpass_barrier start_barrier;
1382 };
1383
1384 struct radv_render_pass_attachment {
1385 VkFormat format;
1386 uint32_t samples;
1387 VkAttachmentLoadOp load_op;
1388 VkAttachmentLoadOp stencil_load_op;
1389 VkImageLayout initial_layout;
1390 VkImageLayout final_layout;
1391 };
1392
1393 struct radv_render_pass {
1394 uint32_t attachment_count;
1395 uint32_t subpass_count;
1396 VkAttachmentReference * subpass_attachments;
1397 struct radv_render_pass_attachment * attachments;
1398 struct radv_subpass_barrier end_barrier;
1399 struct radv_subpass subpasses[0];
1400 };
1401
1402 VkResult radv_device_init_meta(struct radv_device *device);
1403 void radv_device_finish_meta(struct radv_device *device);
1404
1405 struct radv_query_pool {
1406 struct radeon_winsys_bo *bo;
1407 uint32_t stride;
1408 uint32_t availability_offset;
1409 char *ptr;
1410 VkQueryType type;
1411 uint32_t pipeline_stats_mask;
1412 };
1413
1414 void
1415 radv_update_descriptor_sets(struct radv_device *device,
1416 struct radv_cmd_buffer *cmd_buffer,
1417 VkDescriptorSet overrideSet,
1418 uint32_t descriptorWriteCount,
1419 const VkWriteDescriptorSet *pDescriptorWrites,
1420 uint32_t descriptorCopyCount,
1421 const VkCopyDescriptorSet *pDescriptorCopies);
1422
1423 void
1424 radv_update_descriptor_set_with_template(struct radv_device *device,
1425 struct radv_cmd_buffer *cmd_buffer,
1426 struct radv_descriptor_set *set,
1427 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
1428 const void *pData);
1429
1430 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1431 VkPipelineBindPoint pipelineBindPoint,
1432 VkPipelineLayout _layout,
1433 uint32_t set,
1434 uint32_t descriptorWriteCount,
1435 const VkWriteDescriptorSet *pDescriptorWrites);
1436
1437 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
1438 struct radv_image *image, uint32_t value);
1439 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1440 struct radv_image *image, uint32_t value);
1441
1442 struct radv_fence {
1443 struct radeon_winsys_fence *fence;
1444 bool submitted;
1445 bool signalled;
1446 };
1447
1448 struct radeon_winsys_sem;
1449
1450 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1451 \
1452 static inline struct __radv_type * \
1453 __radv_type ## _from_handle(__VkType _handle) \
1454 { \
1455 return (struct __radv_type *) _handle; \
1456 } \
1457 \
1458 static inline __VkType \
1459 __radv_type ## _to_handle(struct __radv_type *_obj) \
1460 { \
1461 return (__VkType) _obj; \
1462 }
1463
1464 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1465 \
1466 static inline struct __radv_type * \
1467 __radv_type ## _from_handle(__VkType _handle) \
1468 { \
1469 return (struct __radv_type *)(uintptr_t) _handle; \
1470 } \
1471 \
1472 static inline __VkType \
1473 __radv_type ## _to_handle(struct __radv_type *_obj) \
1474 { \
1475 return (__VkType)(uintptr_t) _obj; \
1476 }
1477
1478 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1479 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1480
1481 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1482 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1483 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1484 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1485 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1486
1487 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1488 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1489 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1490 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1491 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1492 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1493 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
1494 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1495 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1496 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1497 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1498 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1499 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1500 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1501 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1502 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1503 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1504 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1505 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1506 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1507 RADV_DEFINE_NONDISP_HANDLE_CASTS(radeon_winsys_sem, VkSemaphore)
1508
1509 #endif /* RADV_PRIVATE_H */