projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
amd,radeonsi: rename radeon_winsys_cs -> radeon_cmdbuf
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include "c11/threads.h"
47 #include <amdgpu.h>
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "main/macros.h"
52 #include "vk_alloc.h"
53 #include "vk_debug_report.h"
54
55 #include "radv_radeon_winsys.h"
56 #include "ac_binary.h"
57 #include "ac_nir_to_llvm.h"
58 #include "ac_gpu_info.h"
59 #include "ac_surface.h"
60 #include "ac_llvm_build.h"
61 #include "radv_descriptor_set.h"
62 #include "radv_extensions.h"
63 #include "radv_cs.h"
64
65 #include <llvm-c/TargetMachine.h>
66
67 /* Pre-declarations needed for WSI entrypoints */
68 struct wl_surface;
69 struct wl_display;
70 typedef struct xcb_connection_t xcb_connection_t;
71 typedef uint32_t xcb_visualid_t;
72 typedef uint32_t xcb_window_t;
73
74 #include <vulkan/vulkan.h>
75 #include <vulkan/vulkan_intel.h>
76 #include <vulkan/vk_icd.h>
77 #include <vulkan/vk_android_native_buffer.h>
78
79 #include "radv_entrypoints.h"
80
81 #include "wsi_common.h"
82
83 #define ATI_VENDOR_ID 0x1002
84
85 #define MAX_VBS 32
86 #define MAX_VERTEX_ATTRIBS 32
87 #define MAX_RTS 8
88 #define MAX_VIEWPORTS 16
89 #define MAX_SCISSORS 16
90 #define MAX_DISCARD_RECTANGLES 4
91 #define MAX_PUSH_CONSTANTS_SIZE 128
92 #define MAX_PUSH_DESCRIPTORS 32
93 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
94 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
95 #define MAX_DYNAMIC_BUFFERS (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
96 #define MAX_SAMPLES_LOG2 4
97 #define NUM_META_FS_KEYS 13
98 #define RADV_MAX_DRM_DEVICES 8
99 #define MAX_VIEWS 8
100
101 #define NUM_DEPTH_CLEAR_PIPELINES 3
102
103 /*
104 * This is the point we switch from using CP to compute shader
105 * for certain buffer operations.
106 */
107 #define RADV_BUFFER_OPS_CS_THRESHOLD 4096
108
109 enum radv_mem_heap {
110 RADV_MEM_HEAP_VRAM,
111 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
112 RADV_MEM_HEAP_GTT,
113 RADV_MEM_HEAP_COUNT
114 };
115
116 enum radv_mem_type {
117 RADV_MEM_TYPE_VRAM,
118 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
119 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
120 RADV_MEM_TYPE_GTT_CACHED,
121 RADV_MEM_TYPE_COUNT
122 };
123
124 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
125
126 static inline uint32_t
127 align_u32(uint32_t v, uint32_t a)
128 {
129 assert(a != 0 && a == (a & -a));
130 return (v + a - 1) & ~(a - 1);
131 }
132
133 static inline uint32_t
134 align_u32_npot(uint32_t v, uint32_t a)
135 {
136 return (v + a - 1) / a * a;
137 }
138
139 static inline uint64_t
140 align_u64(uint64_t v, uint64_t a)
141 {
142 assert(a != 0 && a == (a & -a));
143 return (v + a - 1) & ~(a - 1);
144 }
145
146 static inline int32_t
147 align_i32(int32_t v, int32_t a)
148 {
149 assert(a != 0 && a == (a & -a));
150 return (v + a - 1) & ~(a - 1);
151 }
152
153 /** Alignment must be a power of 2. */
154 static inline bool
155 radv_is_aligned(uintmax_t n, uintmax_t a)
156 {
157 assert(a == (a & -a));
158 return (n & (a - 1)) == 0;
159 }
160
161 static inline uint32_t
162 round_up_u32(uint32_t v, uint32_t a)
163 {
164 return (v + a - 1) / a;
165 }
166
167 static inline uint64_t
168 round_up_u64(uint64_t v, uint64_t a)
169 {
170 return (v + a - 1) / a;
171 }
172
173 static inline uint32_t
174 radv_minify(uint32_t n, uint32_t levels)
175 {
176 if (unlikely(n == 0))
177 return 0;
178 else
179 return MAX2(n >> levels, 1);
180 }
181 static inline float
182 radv_clamp_f(float f, float min, float max)
183 {
184 assert(min < max);
185
186 if (f > max)
187 return max;
188 else if (f < min)
189 return min;
190 else
191 return f;
192 }
193
194 static inline bool
195 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
196 {
197 if (*inout_mask & clear_mask) {
198 *inout_mask &= ~clear_mask;
199 return true;
200 } else {
201 return false;
202 }
203 }
204
205 #define for_each_bit(b, dword) \
206 for (uint32_t __dword = (dword); \
207 (b) = __builtin_ffs(__dword) - 1, __dword; \
208 __dword &= ~(1 << (b)))
209
210 #define typed_memcpy(dest, src, count) ({ \
211 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
212 memcpy((dest), (src), (count) * sizeof(*(src))); \
213 })
214
215 /* Whenever we generate an error, pass it through this function. Useful for
216 * debugging, where we can break on it. Only call at error site, not when
217 * propagating errors. Might be useful to plug in a stack trace here.
218 */
219
220 struct radv_instance;
221
222 VkResult __vk_errorf(struct radv_instance *instance, VkResult error, const char *file, int line, const char *format, ...);
223
224 #define vk_error(instance, error) __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
225 #define vk_errorf(instance, error, format, ...) __vk_errorf(instance, error, __FILE__, __LINE__, format, ## __VA_ARGS__);
226
227 void __radv_finishme(const char *file, int line, const char *format, ...)
228 radv_printflike(3, 4);
229 void radv_loge(const char *format, ...) radv_printflike(1, 2);
230 void radv_loge_v(const char *format, va_list va);
231 void radv_logi(const char *format, ...) radv_printflike(1, 2);
232 void radv_logi_v(const char *format, va_list va);
233
234 /**
235 * Print a FINISHME message, including its source location.
236 */
237 #define radv_finishme(format, ...) \
238 do { \
239 static bool reported = false; \
240 if (!reported) { \
241 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
242 reported = true; \
243 } \
244 } while (0)
245
246 /* A non-fatal assert. Useful for debugging. */
247 #ifdef DEBUG
248 #define radv_assert(x) ({ \
249 if (unlikely(!(x))) \
250 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
251 })
252 #else
253 #define radv_assert(x)
254 #endif
255
256 #define stub_return(v) \
257 do { \
258 radv_finishme("stub %s", __func__); \
259 return (v); \
260 } while (0)
261
262 #define stub() \
263 do { \
264 radv_finishme("stub %s", __func__); \
265 return; \
266 } while (0)
267
268 void *radv_lookup_entrypoint_unchecked(const char *name);
269 void *radv_lookup_entrypoint_checked(const char *name,
270 uint32_t core_version,
271 const struct radv_instance_extension_table *instance,
272 const struct radv_device_extension_table *device);
273
274 struct radv_physical_device {
275 VK_LOADER_DATA _loader_data;
276
277 struct radv_instance * instance;
278
279 struct radeon_winsys *ws;
280 struct radeon_info rad_info;
281 char path[20];
282 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
283 uint8_t driver_uuid[VK_UUID_SIZE];
284 uint8_t device_uuid[VK_UUID_SIZE];
285 uint8_t cache_uuid[VK_UUID_SIZE];
286
287 int local_fd;
288 struct wsi_device wsi_device;
289
290 bool has_rbplus; /* if RB+ register exist */
291 bool rbplus_allowed; /* if RB+ is allowed */
292 bool has_clear_state;
293 bool cpdma_prefetch_writes_memory;
294 bool has_scissor_bug;
295
296 bool has_out_of_order_rast;
297 bool out_of_order_rast_allowed;
298
299 /* Whether DCC should be enabled for MSAA textures. */
300 bool dcc_msaa_allowed;
301
302 /* This is the drivers on-disk cache used as a fallback as opposed to
303 * the pipeline cache defined by apps.
304 */
305 struct disk_cache * disk_cache;
306
307 VkPhysicalDeviceMemoryProperties memory_properties;
308 enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
309
310 struct radv_device_extension_table supported_extensions;
311 };
312
313 struct radv_instance {
314 VK_LOADER_DATA _loader_data;
315
316 VkAllocationCallbacks alloc;
317
318 uint32_t apiVersion;
319 int physicalDeviceCount;
320 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
321
322 uint64_t debug_flags;
323 uint64_t perftest_flags;
324
325 struct vk_debug_report_instance debug_report_callbacks;
326
327 struct radv_instance_extension_table enabled_extensions;
328 };
329
330 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
331 void radv_finish_wsi(struct radv_physical_device *physical_device);
332
333 bool radv_instance_extension_supported(const char *name);
334 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
335 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
336 const char *name);
337
338 struct cache_entry;
339
340 struct radv_pipeline_cache {
341 struct radv_device * device;
342 pthread_mutex_t mutex;
343
344 uint32_t total_size;
345 uint32_t table_size;
346 uint32_t kernel_count;
347 struct cache_entry ** hash_table;
348 bool modified;
349
350 VkAllocationCallbacks alloc;
351 };
352
353 struct radv_pipeline_key {
354 uint32_t instance_rate_inputs;
355 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
356 uint64_t vertex_alpha_adjust;
357 unsigned tess_input_vertices;
358 uint32_t col_format;
359 uint32_t is_int8;
360 uint32_t is_int10;
361 uint8_t log2_ps_iter_samples;
362 uint8_t log2_num_samples;
363 uint32_t has_multiview_view_index : 1;
364 uint32_t optimisations_disabled : 1;
365 };
366
367 void
368 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
369 struct radv_device *device);
370 void
371 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
372 void
373 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
374 const void *data, size_t size);
375
376 struct radv_shader_variant;
377
378 bool
379 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
380 struct radv_pipeline_cache *cache,
381 const unsigned char *sha1,
382 struct radv_shader_variant **variants);
383
384 void
385 radv_pipeline_cache_insert_shaders(struct radv_device *device,
386 struct radv_pipeline_cache *cache,
387 const unsigned char *sha1,
388 struct radv_shader_variant **variants,
389 const void *const *codes,
390 const unsigned *code_sizes);
391
392 enum radv_blit_ds_layout {
393 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
394 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
395 RADV_BLIT_DS_LAYOUT_COUNT,
396 };
397
398 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
399 {
400 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
401 }
402
403 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
404 {
405 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
406 }
407
408 enum radv_meta_dst_layout {
409 RADV_META_DST_LAYOUT_GENERAL,
410 RADV_META_DST_LAYOUT_OPTIMAL,
411 RADV_META_DST_LAYOUT_COUNT,
412 };
413
414 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
415 {
416 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
417 }
418
419 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
420 {
421 return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
422 }
423
424 struct radv_meta_state {
425 VkAllocationCallbacks alloc;
426
427 struct radv_pipeline_cache cache;
428
429 /**
430 * Use array element `i` for images with `2^i` samples.
431 */
432 struct {
433 VkRenderPass render_pass[NUM_META_FS_KEYS];
434 VkPipeline color_pipelines[NUM_META_FS_KEYS];
435
436 VkRenderPass depthstencil_rp;
437 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
438 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
439 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
440 } clear[1 + MAX_SAMPLES_LOG2];
441
442 VkPipelineLayout clear_color_p_layout;
443 VkPipelineLayout clear_depth_p_layout;
444 struct {
445 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
446
447 /** Pipeline that blits from a 1D image. */
448 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
449
450 /** Pipeline that blits from a 2D image. */
451 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
452
453 /** Pipeline that blits from a 3D image. */
454 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
455
456 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
457 VkPipeline depth_only_1d_pipeline;
458 VkPipeline depth_only_2d_pipeline;
459 VkPipeline depth_only_3d_pipeline;
460
461 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
462 VkPipeline stencil_only_1d_pipeline;
463 VkPipeline stencil_only_2d_pipeline;
464 VkPipeline stencil_only_3d_pipeline;
465 VkPipelineLayout pipeline_layout;
466 VkDescriptorSetLayout ds_layout;
467 } blit;
468
469 struct {
470 VkPipelineLayout p_layouts[5];
471 VkDescriptorSetLayout ds_layouts[5];
472 VkPipeline pipelines[5][NUM_META_FS_KEYS];
473
474 VkPipeline depth_only_pipeline[5];
475
476 VkPipeline stencil_only_pipeline[5];
477 } blit2d[1 + MAX_SAMPLES_LOG2];
478
479 VkRenderPass blit2d_render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
480 VkRenderPass blit2d_depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
481 VkRenderPass blit2d_stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
482
483 struct {
484 VkPipelineLayout img_p_layout;
485 VkDescriptorSetLayout img_ds_layout;
486 VkPipeline pipeline;
487 VkPipeline pipeline_3d;
488 } itob;
489 struct {
490 VkPipelineLayout img_p_layout;
491 VkDescriptorSetLayout img_ds_layout;
492 VkPipeline pipeline;
493 VkPipeline pipeline_3d;
494 } btoi;
495 struct {
496 VkPipelineLayout img_p_layout;
497 VkDescriptorSetLayout img_ds_layout;
498 VkPipeline pipeline;
499 VkPipeline pipeline_3d;
500 } itoi;
501 struct {
502 VkPipelineLayout img_p_layout;
503 VkDescriptorSetLayout img_ds_layout;
504 VkPipeline pipeline;
505 VkPipeline pipeline_3d;
506 } cleari;
507
508 struct {
509 VkPipelineLayout p_layout;
510 VkPipeline pipeline[NUM_META_FS_KEYS];
511 VkRenderPass pass[NUM_META_FS_KEYS];
512 } resolve;
513
514 struct {
515 VkDescriptorSetLayout ds_layout;
516 VkPipelineLayout p_layout;
517 struct {
518 VkPipeline pipeline;
519 VkPipeline i_pipeline;
520 VkPipeline srgb_pipeline;
521 } rc[MAX_SAMPLES_LOG2];
522 } resolve_compute;
523
524 struct {
525 VkDescriptorSetLayout ds_layout;
526 VkPipelineLayout p_layout;
527
528 struct {
529 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
530 VkPipeline pipeline[NUM_META_FS_KEYS];
531 } rc[MAX_SAMPLES_LOG2];
532 } resolve_fragment;
533
534 struct {
535 VkPipelineLayout p_layout;
536 VkPipeline decompress_pipeline;
537 VkPipeline resummarize_pipeline;
538 VkRenderPass pass;
539 } depth_decomp[1 + MAX_SAMPLES_LOG2];
540
541 struct {
542 VkPipelineLayout p_layout;
543 VkPipeline cmask_eliminate_pipeline;
544 VkPipeline fmask_decompress_pipeline;
545 VkPipeline dcc_decompress_pipeline;
546 VkRenderPass pass;
547
548 VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
549 VkPipelineLayout dcc_decompress_compute_p_layout;
550 VkPipeline dcc_decompress_compute_pipeline;
551 } fast_clear_flush;
552
553 struct {
554 VkPipelineLayout fill_p_layout;
555 VkPipelineLayout copy_p_layout;
556 VkDescriptorSetLayout fill_ds_layout;
557 VkDescriptorSetLayout copy_ds_layout;
558 VkPipeline fill_pipeline;
559 VkPipeline copy_pipeline;
560 } buffer;
561
562 struct {
563 VkDescriptorSetLayout ds_layout;
564 VkPipelineLayout p_layout;
565 VkPipeline occlusion_query_pipeline;
566 VkPipeline pipeline_statistics_query_pipeline;
567 } query;
568 };
569
570 /* queue types */
571 #define RADV_QUEUE_GENERAL 0
572 #define RADV_QUEUE_COMPUTE 1
573 #define RADV_QUEUE_TRANSFER 2
574
575 #define RADV_MAX_QUEUE_FAMILIES 3
576
577 enum ring_type radv_queue_family_to_ring(int f);
578
579 struct radv_queue {
580 VK_LOADER_DATA _loader_data;
581 struct radv_device * device;
582 struct radeon_winsys_ctx *hw_ctx;
583 enum radeon_ctx_priority priority;
584 uint32_t queue_family_index;
585 int queue_idx;
586 VkDeviceQueueCreateFlags flags;
587
588 uint32_t scratch_size;
589 uint32_t compute_scratch_size;
590 uint32_t esgs_ring_size;
591 uint32_t gsvs_ring_size;
592 bool has_tess_rings;
593 bool has_sample_positions;
594
595 struct radeon_winsys_bo *scratch_bo;
596 struct radeon_winsys_bo *descriptor_bo;
597 struct radeon_winsys_bo *compute_scratch_bo;
598 struct radeon_winsys_bo *esgs_ring_bo;
599 struct radeon_winsys_bo *gsvs_ring_bo;
600 struct radeon_winsys_bo *tess_rings_bo;
601 struct radeon_cmdbuf *initial_preamble_cs;
602 struct radeon_cmdbuf *initial_full_flush_preamble_cs;
603 struct radeon_cmdbuf *continue_preamble_cs;
604 };
605
606 struct radv_bo_list {
607 struct radv_winsys_bo_list list;
608 unsigned capacity;
609 pthread_mutex_t mutex;
610 };
611
612 struct radv_device {
613 VK_LOADER_DATA _loader_data;
614
615 VkAllocationCallbacks alloc;
616
617 struct radv_instance * instance;
618 struct radeon_winsys *ws;
619
620 struct radv_meta_state meta_state;
621
622 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
623 int queue_count[RADV_MAX_QUEUE_FAMILIES];
624 struct radeon_cmdbuf *empty_cs[RADV_MAX_QUEUE_FAMILIES];
625
626 bool always_use_syncobj;
627 bool has_distributed_tess;
628 bool pbb_allowed;
629 bool dfsm_allowed;
630 uint32_t tess_offchip_block_dw_size;
631 uint32_t scratch_waves;
632 uint32_t dispatch_initiator;
633
634 uint32_t gs_table_depth;
635
636 /* MSAA sample locations.
637 * The first index is the sample index.
638 * The second index is the coordinate: X, Y. */
639 float sample_locations_1x[1][2];
640 float sample_locations_2x[2][2];
641 float sample_locations_4x[4][2];
642 float sample_locations_8x[8][2];
643 float sample_locations_16x[16][2];
644
645 /* CIK and later */
646 uint32_t gfx_init_size_dw;
647 struct radeon_winsys_bo *gfx_init;
648
649 struct radeon_winsys_bo *trace_bo;
650 uint32_t *trace_id_ptr;
651
652 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
653 bool keep_shader_info;
654
655 struct radv_physical_device *physical_device;
656
657 /* Backup in-memory cache to be used if the app doesn't provide one */
658 struct radv_pipeline_cache * mem_cache;
659
660 /*
661 * use different counters so MSAA MRTs get consecutive surface indices,
662 * even if MASK is allocated in between.
663 */
664 uint32_t image_mrt_offset_counter;
665 uint32_t fmask_mrt_offset_counter;
666 struct list_head shader_slabs;
667 mtx_t shader_slab_mutex;
668
669 /* For detecting VM faults reported by dmesg. */
670 uint64_t dmesg_timestamp;
671
672 struct radv_device_extension_table enabled_extensions;
673
674 /* Whether the driver uses a global BO list. */
675 bool use_global_bo_list;
676
677 struct radv_bo_list bo_list;
678 };
679
680 struct radv_device_memory {
681 struct radeon_winsys_bo *bo;
682 /* for dedicated allocations */
683 struct radv_image *image;
684 struct radv_buffer *buffer;
685 uint32_t type_index;
686 VkDeviceSize map_size;
687 void * map;
688 void * user_ptr;
689 };
690
691
692 struct radv_descriptor_range {
693 uint64_t va;
694 uint32_t size;
695 };
696
697 struct radv_descriptor_set {
698 const struct radv_descriptor_set_layout *layout;
699 uint32_t size;
700
701 struct radeon_winsys_bo *bo;
702 uint64_t va;
703 uint32_t *mapped_ptr;
704 struct radv_descriptor_range *dynamic_descriptors;
705
706 struct radeon_winsys_bo *descriptors[0];
707 };
708
709 struct radv_push_descriptor_set
710 {
711 struct radv_descriptor_set set;
712 uint32_t capacity;
713 };
714
715 struct radv_descriptor_pool_entry {
716 uint32_t offset;
717 uint32_t size;
718 struct radv_descriptor_set *set;
719 };
720
721 struct radv_descriptor_pool {
722 struct radeon_winsys_bo *bo;
723 uint8_t *mapped_ptr;
724 uint64_t current_offset;
725 uint64_t size;
726
727 uint8_t *host_memory_base;
728 uint8_t *host_memory_ptr;
729 uint8_t *host_memory_end;
730
731 uint32_t entry_count;
732 uint32_t max_entry_count;
733 struct radv_descriptor_pool_entry entries[0];
734 };
735
736 struct radv_descriptor_update_template_entry {
737 VkDescriptorType descriptor_type;
738
739 /* The number of descriptors to update */
740 uint32_t descriptor_count;
741
742 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
743 uint32_t dst_offset;
744
745 /* In dwords. Not valid/used for dynamic descriptors */
746 uint32_t dst_stride;
747
748 uint32_t buffer_offset;
749
750 /* Only valid for combined image samplers and samplers */
751 uint16_t has_sampler;
752
753 /* In bytes */
754 size_t src_offset;
755 size_t src_stride;
756
757 /* For push descriptors */
758 const uint32_t *immutable_samplers;
759 };
760
761 struct radv_descriptor_update_template {
762 uint32_t entry_count;
763 VkPipelineBindPoint bind_point;
764 struct radv_descriptor_update_template_entry entry[0];
765 };
766
767 struct radv_buffer {
768 VkDeviceSize size;
769
770 VkBufferUsageFlags usage;
771 VkBufferCreateFlags flags;
772
773 /* Set when bound */
774 struct radeon_winsys_bo * bo;
775 VkDeviceSize offset;
776
777 bool shareable;
778 };
779
780 enum radv_dynamic_state_bits {
781 RADV_DYNAMIC_VIEWPORT = 1 << 0,
782 RADV_DYNAMIC_SCISSOR = 1 << 1,
783 RADV_DYNAMIC_LINE_WIDTH = 1 << 2,
784 RADV_DYNAMIC_DEPTH_BIAS = 1 << 3,
785 RADV_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
786 RADV_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
787 RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
788 RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
789 RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
790 RADV_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
791 RADV_DYNAMIC_ALL = (1 << 10) - 1,
792 };
793
794 enum radv_cmd_dirty_bits {
795 /* Keep the dynamic state dirty bits in sync with
796 * enum radv_dynamic_state_bits */
797 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0,
798 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1,
799 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2,
800 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3,
801 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
802 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
803 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
804 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
805 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
806 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
807 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 10) - 1,
808 RADV_CMD_DIRTY_PIPELINE = 1 << 10,
809 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 11,
810 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 12,
811 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 13,
812 };
813
814 enum radv_cmd_flush_bits {
815 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
816 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
817 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
818 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
819 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
820 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
821 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
822 /* Same as above, but only writes back and doesn't invalidate */
823 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
824 /* Framebuffer caches */
825 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
826 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
827 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
828 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
829 /* Engine synchronization. */
830 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
831 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
832 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
833 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
834
835 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
836 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
837 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
838 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
839 };
840
841 struct radv_vertex_binding {
842 struct radv_buffer * buffer;
843 VkDeviceSize offset;
844 };
845
846 struct radv_viewport_state {
847 uint32_t count;
848 VkViewport viewports[MAX_VIEWPORTS];
849 };
850
851 struct radv_scissor_state {
852 uint32_t count;
853 VkRect2D scissors[MAX_SCISSORS];
854 };
855
856 struct radv_discard_rectangle_state {
857 uint32_t count;
858 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
859 };
860
861 struct radv_dynamic_state {
862 /**
863 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
864 * Defines the set of saved dynamic state.
865 */
866 uint32_t mask;
867
868 struct radv_viewport_state viewport;
869
870 struct radv_scissor_state scissor;
871
872 float line_width;
873
874 struct {
875 float bias;
876 float clamp;
877 float slope;
878 } depth_bias;
879
880 float blend_constants[4];
881
882 struct {
883 float min;
884 float max;
885 } depth_bounds;
886
887 struct {
888 uint32_t front;
889 uint32_t back;
890 } stencil_compare_mask;
891
892 struct {
893 uint32_t front;
894 uint32_t back;
895 } stencil_write_mask;
896
897 struct {
898 uint32_t front;
899 uint32_t back;
900 } stencil_reference;
901
902 struct radv_discard_rectangle_state discard_rectangle;
903 };
904
905 extern const struct radv_dynamic_state default_dynamic_state;
906
907 const char *
908 radv_get_debug_option_name(int id);
909
910 const char *
911 radv_get_perftest_option_name(int id);
912
913 /**
914 * Attachment state when recording a renderpass instance.
915 *
916 * The clear value is valid only if there exists a pending clear.
917 */
918 struct radv_attachment_state {
919 VkImageAspectFlags pending_clear_aspects;
920 uint32_t cleared_views;
921 VkClearValue clear_value;
922 VkImageLayout current_layout;
923 };
924
925 struct radv_descriptor_state {
926 struct radv_descriptor_set *sets[MAX_SETS];
927 uint32_t dirty;
928 uint32_t valid;
929 struct radv_push_descriptor_set push_set;
930 bool push_dirty;
931 };
932
933 struct radv_cmd_state {
934 /* Vertex descriptors */
935 uint64_t vb_va;
936 unsigned vb_size;
937
938 bool predicating;
939 uint32_t dirty;
940
941 uint32_t prefetch_L2_mask;
942
943 struct radv_pipeline * pipeline;
944 struct radv_pipeline * emitted_pipeline;
945 struct radv_pipeline * compute_pipeline;
946 struct radv_pipeline * emitted_compute_pipeline;
947 struct radv_framebuffer * framebuffer;
948 struct radv_render_pass * pass;
949 const struct radv_subpass * subpass;
950 struct radv_dynamic_state dynamic;
951 struct radv_attachment_state * attachments;
952 VkRect2D render_area;
953
954 /* Index buffer */
955 struct radv_buffer *index_buffer;
956 uint64_t index_offset;
957 uint32_t index_type;
958 uint32_t max_index_count;
959 uint64_t index_va;
960 int32_t last_index_type;
961
962 int32_t last_primitive_reset_en;
963 uint32_t last_primitive_reset_index;
964 enum radv_cmd_flush_bits flush_bits;
965 unsigned active_occlusion_queries;
966 bool perfect_occlusion_queries_enabled;
967 float offset_scale;
968 uint32_t trace_id;
969 uint32_t last_ia_multi_vgt_param;
970
971 uint32_t last_num_instances;
972 uint32_t last_first_instance;
973 uint32_t last_vertex_offset;
974 };
975
976 struct radv_cmd_pool {
977 VkAllocationCallbacks alloc;
978 struct list_head cmd_buffers;
979 struct list_head free_cmd_buffers;
980 uint32_t queue_family_index;
981 };
982
983 struct radv_cmd_buffer_upload {
984 uint8_t *map;
985 unsigned offset;
986 uint64_t size;
987 struct radeon_winsys_bo *upload_bo;
988 struct list_head list;
989 };
990
991 enum radv_cmd_buffer_status {
992 RADV_CMD_BUFFER_STATUS_INVALID,
993 RADV_CMD_BUFFER_STATUS_INITIAL,
994 RADV_CMD_BUFFER_STATUS_RECORDING,
995 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
996 RADV_CMD_BUFFER_STATUS_PENDING,
997 };
998
999 struct radv_cmd_buffer {
1000 VK_LOADER_DATA _loader_data;
1001
1002 struct radv_device * device;
1003
1004 struct radv_cmd_pool * pool;
1005 struct list_head pool_link;
1006
1007 VkCommandBufferUsageFlags usage_flags;
1008 VkCommandBufferLevel level;
1009 enum radv_cmd_buffer_status status;
1010 struct radeon_cmdbuf *cs;
1011 struct radv_cmd_state state;
1012 struct radv_vertex_binding vertex_bindings[MAX_VBS];
1013 uint32_t queue_family_index;
1014
1015 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
1016 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
1017 VkShaderStageFlags push_constant_stages;
1018 struct radv_descriptor_set meta_push_descriptors;
1019
1020 struct radv_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
1021
1022 struct radv_cmd_buffer_upload upload;
1023
1024 uint32_t scratch_size_needed;
1025 uint32_t compute_scratch_size_needed;
1026 uint32_t esgs_ring_size_needed;
1027 uint32_t gsvs_ring_size_needed;
1028 bool tess_rings_needed;
1029 bool sample_positions_needed;
1030
1031 VkResult record_result;
1032
1033 int ring_offsets_idx; /* just used for verification */
1034 uint32_t gfx9_fence_offset;
1035 struct radeon_winsys_bo *gfx9_fence_bo;
1036 uint32_t gfx9_fence_idx;
1037
1038 /**
1039 * Whether a query pool has been resetted and we have to flush caches.
1040 */
1041 bool pending_reset_query;
1042 };
1043
1044 struct radv_image;
1045
1046 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
1047
1048 void si_init_compute(struct radv_cmd_buffer *cmd_buffer);
1049 void si_init_config(struct radv_cmd_buffer *cmd_buffer);
1050
1051 void cik_create_gfx_config(struct radv_device *device);
1052
1053 void si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
1054 int count, const VkViewport *viewports);
1055 void si_write_scissors(struct radeon_cmdbuf *cs, int first,
1056 int count, const VkRect2D *scissors,
1057 const VkViewport *viewports, bool can_use_guardband);
1058 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
1059 bool instanced_draw, bool indirect_draw,
1060 uint32_t draw_vertex_count);
1061 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
1062 bool predicated,
1063 enum chip_class chip_class,
1064 bool is_mec,
1065 unsigned event, unsigned event_flags,
1066 unsigned data_sel,
1067 uint64_t va,
1068 uint32_t old_fence,
1069 uint32_t new_fence);
1070
1071 void si_emit_wait_fence(struct radeon_cmdbuf *cs,
1072 bool predicated,
1073 uint64_t va, uint32_t ref,
1074 uint32_t mask);
1075 void si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
1076 enum chip_class chip_class,
1077 uint32_t *fence_ptr, uint64_t va,
1078 bool is_mec,
1079 enum radv_cmd_flush_bits flush_bits);
1080 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
1081 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va);
1082 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1083 uint64_t src_va, uint64_t dest_va,
1084 uint64_t size);
1085 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1086 unsigned size);
1087 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1088 uint64_t size, unsigned value);
1089 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1090 bool
1091 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1092 unsigned size,
1093 unsigned alignment,
1094 unsigned *out_offset,
1095 void **ptr);
1096 void
1097 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1098 const struct radv_subpass *subpass,
1099 bool transitions);
1100 bool
1101 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1102 unsigned size, unsigned alignmnet,
1103 const void *data, unsigned *out_offset);
1104
1105 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1106 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1107 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1108 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1109 void radv_cayman_emit_msaa_sample_locs(struct radeon_cmdbuf *cs, int nr_samples);
1110 unsigned radv_cayman_get_maxdist(int log_samples);
1111 void radv_device_init_msaa(struct radv_device *device);
1112
1113 void radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1114 struct radv_image *image,
1115 VkClearDepthStencilValue ds_clear_value,
1116 VkImageAspectFlags aspects);
1117
1118 void radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1119 struct radv_image *image,
1120 int cb_idx,
1121 uint32_t color_values[2]);
1122
1123 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1124 struct radv_image *image,
1125 bool value);
1126 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1127 struct radeon_winsys_bo *bo,
1128 uint64_t offset, uint64_t size, uint32_t value);
1129 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1130 bool radv_get_memory_fd(struct radv_device *device,
1131 struct radv_device_memory *memory,
1132 int *pFD);
1133
1134 static inline void
1135 radv_emit_shader_pointer_head(struct radeon_cmdbuf *cs,
1136 unsigned sh_offset, unsigned pointer_count,
1137 bool use_32bit_pointers)
1138 {
1139 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, pointer_count * (use_32bit_pointers ? 1 : 2), 0));
1140 radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2);
1141 }
1142
1143 static inline void
1144 radv_emit_shader_pointer_body(struct radv_device *device,
1145 struct radeon_cmdbuf *cs,
1146 uint64_t va, bool use_32bit_pointers)
1147 {
1148 radeon_emit(cs, va);
1149
1150 if (use_32bit_pointers) {
1151 assert(va == 0 ||
1152 (va >> 32) == device->physical_device->rad_info.address32_hi);
1153 } else {
1154 radeon_emit(cs, va >> 32);
1155 }
1156 }
1157
1158 static inline void
1159 radv_emit_shader_pointer(struct radv_device *device,
1160 struct radeon_cmdbuf *cs,
1161 uint32_t sh_offset, uint64_t va, bool global)
1162 {
1163 bool use_32bit_pointers = HAVE_32BIT_POINTERS && !global;
1164
1165 radv_emit_shader_pointer_head(cs, sh_offset, 1, use_32bit_pointers);
1166 radv_emit_shader_pointer_body(device, cs, va, use_32bit_pointers);
1167 }
1168
1169 static inline struct radv_descriptor_state *
1170 radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
1171 VkPipelineBindPoint bind_point)
1172 {
1173 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS ||
1174 bind_point == VK_PIPELINE_BIND_POINT_COMPUTE);
1175 return &cmd_buffer->descriptors[bind_point];
1176 }
1177
1178 /*
1179 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1180 *
1181 * Limitations: Can't call normal dispatch functions without binding or rebinding
1182 * the compute pipeline.
1183 */
1184 void radv_unaligned_dispatch(
1185 struct radv_cmd_buffer *cmd_buffer,
1186 uint32_t x,
1187 uint32_t y,
1188 uint32_t z);
1189
1190 struct radv_event {
1191 struct radeon_winsys_bo *bo;
1192 uint64_t *map;
1193 };
1194
1195 struct radv_shader_module;
1196
1197 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1198 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1199 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1200 void
1201 radv_hash_shaders(unsigned char *hash,
1202 const VkPipelineShaderStageCreateInfo **stages,
1203 const struct radv_pipeline_layout *layout,
1204 const struct radv_pipeline_key *key,
1205 uint32_t flags);
1206
1207 static inline gl_shader_stage
1208 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1209 {
1210 assert(__builtin_popcount(vk_stage) == 1);
1211 return ffs(vk_stage) - 1;
1212 }
1213
1214 static inline VkShaderStageFlagBits
1215 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1216 {
1217 return (1 << mesa_stage);
1218 }
1219
1220 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1221
1222 #define radv_foreach_stage(stage, stage_bits) \
1223 for (gl_shader_stage stage, \
1224 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1225 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1226 __tmp &= ~(1 << (stage)))
1227
1228 unsigned radv_format_meta_fs_key(VkFormat format);
1229
1230 struct radv_multisample_state {
1231 uint32_t db_eqaa;
1232 uint32_t pa_sc_line_cntl;
1233 uint32_t pa_sc_mode_cntl_0;
1234 uint32_t pa_sc_mode_cntl_1;
1235 uint32_t pa_sc_aa_config;
1236 uint32_t pa_sc_aa_mask[2];
1237 unsigned num_samples;
1238 };
1239
1240 struct radv_prim_vertex_count {
1241 uint8_t min;
1242 uint8_t incr;
1243 };
1244
1245 struct radv_vertex_elements_info {
1246 uint32_t rsrc_word3[MAX_VERTEX_ATTRIBS];
1247 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1248 uint32_t binding[MAX_VERTEX_ATTRIBS];
1249 uint32_t offset[MAX_VERTEX_ATTRIBS];
1250 uint32_t count;
1251 };
1252
1253 struct radv_ia_multi_vgt_param_helpers {
1254 uint32_t base;
1255 bool partial_es_wave;
1256 uint8_t primgroup_size;
1257 bool wd_switch_on_eop;
1258 bool ia_switch_on_eoi;
1259 bool partial_vs_wave;
1260 };
1261
1262 #define SI_GS_PER_ES 128
1263
1264 struct radv_pipeline {
1265 struct radv_device * device;
1266 struct radv_dynamic_state dynamic_state;
1267
1268 struct radv_pipeline_layout * layout;
1269
1270 bool need_indirect_descriptor_sets;
1271 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1272 struct radv_shader_variant *gs_copy_shader;
1273 VkShaderStageFlags active_stages;
1274
1275 struct radeon_cmdbuf cs;
1276
1277 struct radv_vertex_elements_info vertex_elements;
1278
1279 uint32_t binding_stride[MAX_VBS];
1280
1281 uint32_t user_data_0[MESA_SHADER_STAGES];
1282 union {
1283 struct {
1284 struct radv_multisample_state ms;
1285 uint32_t spi_baryc_cntl;
1286 bool prim_restart_enable;
1287 unsigned esgs_ring_size;
1288 unsigned gsvs_ring_size;
1289 uint32_t vtx_base_sgpr;
1290 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
1291 uint8_t vtx_emit_num;
1292 struct radv_prim_vertex_count prim_vertex_count;
1293 bool can_use_guardband;
1294 uint32_t needed_dynamic_state;
1295 bool disable_out_of_order_rast_for_occlusion;
1296
1297 /* Used for rbplus */
1298 uint32_t col_format;
1299 uint32_t cb_target_mask;
1300 } graphics;
1301 };
1302
1303 unsigned max_waves;
1304 unsigned scratch_bytes_per_wave;
1305 };
1306
1307 static inline bool radv_pipeline_has_gs(const struct radv_pipeline *pipeline)
1308 {
1309 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1310 }
1311
1312 static inline bool radv_pipeline_has_tess(const struct radv_pipeline *pipeline)
1313 {
1314 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1315 }
1316
1317 struct radv_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1318 gl_shader_stage stage,
1319 int idx);
1320
1321 struct radv_shader_variant *radv_get_shader(struct radv_pipeline *pipeline,
1322 gl_shader_stage stage);
1323
1324 struct radv_graphics_pipeline_create_info {
1325 bool use_rectlist;
1326 bool db_depth_clear;
1327 bool db_stencil_clear;
1328 bool db_depth_disable_expclear;
1329 bool db_stencil_disable_expclear;
1330 bool db_flush_depth_inplace;
1331 bool db_flush_stencil_inplace;
1332 bool db_resummarize;
1333 uint32_t custom_blend_mode;
1334 };
1335
1336 VkResult
1337 radv_graphics_pipeline_create(VkDevice device,
1338 VkPipelineCache cache,
1339 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1340 const struct radv_graphics_pipeline_create_info *extra,
1341 const VkAllocationCallbacks *alloc,
1342 VkPipeline *pPipeline);
1343
1344 struct vk_format_description;
1345 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1346 int first_non_void);
1347 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1348 int first_non_void);
1349 uint32_t radv_translate_colorformat(VkFormat format);
1350 uint32_t radv_translate_color_numformat(VkFormat format,
1351 const struct vk_format_description *desc,
1352 int first_non_void);
1353 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1354 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1355 uint32_t radv_translate_dbformat(VkFormat format);
1356 uint32_t radv_translate_tex_dataformat(VkFormat format,
1357 const struct vk_format_description *desc,
1358 int first_non_void);
1359 uint32_t radv_translate_tex_numformat(VkFormat format,
1360 const struct vk_format_description *desc,
1361 int first_non_void);
1362 bool radv_format_pack_clear_color(VkFormat format,
1363 uint32_t clear_vals[2],
1364 VkClearColorValue *value);
1365 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1366 bool radv_dcc_formats_compatible(VkFormat format1,
1367 VkFormat format2);
1368
1369 struct radv_fmask_info {
1370 uint64_t offset;
1371 uint64_t size;
1372 unsigned alignment;
1373 unsigned pitch_in_pixels;
1374 unsigned bank_height;
1375 unsigned slice_tile_max;
1376 unsigned tile_mode_index;
1377 unsigned tile_swizzle;
1378 };
1379
1380 struct radv_cmask_info {
1381 uint64_t offset;
1382 uint64_t size;
1383 unsigned alignment;
1384 unsigned slice_tile_max;
1385 };
1386
1387 struct radv_image {
1388 VkImageType type;
1389 /* The original VkFormat provided by the client. This may not match any
1390 * of the actual surface formats.
1391 */
1392 VkFormat vk_format;
1393 VkImageAspectFlags aspects;
1394 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1395 struct ac_surf_info info;
1396 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1397 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1398
1399 VkDeviceSize size;
1400 uint32_t alignment;
1401
1402 unsigned queue_family_mask;
1403 bool exclusive;
1404 bool shareable;
1405
1406 /* Set when bound */
1407 struct radeon_winsys_bo *bo;
1408 VkDeviceSize offset;
1409 uint64_t dcc_offset;
1410 uint64_t htile_offset;
1411 bool tc_compatible_htile;
1412 struct radeon_surf surface;
1413
1414 struct radv_fmask_info fmask;
1415 struct radv_cmask_info cmask;
1416 uint64_t clear_value_offset;
1417 uint64_t dcc_pred_offset;
1418
1419 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1420 VkDeviceMemory owned_memory;
1421 };
1422
1423 /* Whether the image has a htile that is known consistent with the contents of
1424 * the image. */
1425 bool radv_layout_has_htile(const struct radv_image *image,
1426 VkImageLayout layout,
1427 unsigned queue_mask);
1428
1429 /* Whether the image has a htile that is known consistent with the contents of
1430 * the image and is allowed to be in compressed form.
1431 *
1432 * If this is false reads that don't use the htile should be able to return
1433 * correct results.
1434 */
1435 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1436 VkImageLayout layout,
1437 unsigned queue_mask);
1438
1439 bool radv_layout_can_fast_clear(const struct radv_image *image,
1440 VkImageLayout layout,
1441 unsigned queue_mask);
1442
1443 bool radv_layout_dcc_compressed(const struct radv_image *image,
1444 VkImageLayout layout,
1445 unsigned queue_mask);
1446
1447 /**
1448 * Return whether the image has CMASK metadata for color surfaces.
1449 */
1450 static inline bool
1451 radv_image_has_cmask(const struct radv_image *image)
1452 {
1453 return image->cmask.size;
1454 }
1455
1456 /**
1457 * Return whether the image has FMASK metadata for color surfaces.
1458 */
1459 static inline bool
1460 radv_image_has_fmask(const struct radv_image *image)
1461 {
1462 return image->fmask.size;
1463 }
1464
1465 /**
1466 * Return whether the image has DCC metadata for color surfaces.
1467 */
1468 static inline bool
1469 radv_image_has_dcc(const struct radv_image *image)
1470 {
1471 return image->surface.dcc_size;
1472 }
1473
1474 /**
1475 * Return whether DCC metadata is enabled for a level.
1476 */
1477 static inline bool
1478 radv_dcc_enabled(const struct radv_image *image, unsigned level)
1479 {
1480 return radv_image_has_dcc(image) &&
1481 level < image->surface.num_dcc_levels;
1482 }
1483
1484 /**
1485 * Return whether the image has HTILE metadata for depth surfaces.
1486 */
1487 static inline bool
1488 radv_image_has_htile(const struct radv_image *image)
1489 {
1490 return image->surface.htile_size;
1491 }
1492
1493 /**
1494 * Return whether HTILE metadata is enabled for a level.
1495 */
1496 static inline bool
1497 radv_htile_enabled(const struct radv_image *image, unsigned level)
1498 {
1499 return radv_image_has_htile(image) && level == 0;
1500 }
1501
1502 /**
1503 * Return whether the image is TC-compatible HTILE.
1504 */
1505 static inline bool
1506 radv_image_is_tc_compat_htile(const struct radv_image *image)
1507 {
1508 return radv_image_has_htile(image) && image->tc_compatible_htile;
1509 }
1510
1511 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1512
1513 static inline uint32_t
1514 radv_get_layerCount(const struct radv_image *image,
1515 const VkImageSubresourceRange *range)
1516 {
1517 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1518 image->info.array_size - range->baseArrayLayer : range->layerCount;
1519 }
1520
1521 static inline uint32_t
1522 radv_get_levelCount(const struct radv_image *image,
1523 const VkImageSubresourceRange *range)
1524 {
1525 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1526 image->info.levels - range->baseMipLevel : range->levelCount;
1527 }
1528
1529 struct radeon_bo_metadata;
1530 void
1531 radv_init_metadata(struct radv_device *device,
1532 struct radv_image *image,
1533 struct radeon_bo_metadata *metadata);
1534
1535 struct radv_image_view {
1536 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1537 struct radeon_winsys_bo *bo;
1538
1539 VkImageViewType type;
1540 VkImageAspectFlags aspect_mask;
1541 VkFormat vk_format;
1542 uint32_t base_layer;
1543 uint32_t layer_count;
1544 uint32_t base_mip;
1545 uint32_t level_count;
1546 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1547
1548 uint32_t descriptor[16];
1549
1550 /* Descriptor for use as a storage image as opposed to a sampled image.
1551 * This has a few differences for cube maps (e.g. type).
1552 */
1553 uint32_t storage_descriptor[16];
1554 };
1555
1556 struct radv_image_create_info {
1557 const VkImageCreateInfo *vk_info;
1558 bool scanout;
1559 bool no_metadata_planes;
1560 };
1561
1562 VkResult radv_image_create(VkDevice _device,
1563 const struct radv_image_create_info *info,
1564 const VkAllocationCallbacks* alloc,
1565 VkImage *pImage);
1566
1567 VkResult
1568 radv_image_from_gralloc(VkDevice device_h,
1569 const VkImageCreateInfo *base_info,
1570 const VkNativeBufferANDROID *gralloc_info,
1571 const VkAllocationCallbacks *alloc,
1572 VkImage *out_image_h);
1573
1574 void radv_image_view_init(struct radv_image_view *view,
1575 struct radv_device *device,
1576 const VkImageViewCreateInfo* pCreateInfo);
1577
1578 struct radv_buffer_view {
1579 struct radeon_winsys_bo *bo;
1580 VkFormat vk_format;
1581 uint64_t range; /**< VkBufferViewCreateInfo::range */
1582 uint32_t state[4];
1583 };
1584 void radv_buffer_view_init(struct radv_buffer_view *view,
1585 struct radv_device *device,
1586 const VkBufferViewCreateInfo* pCreateInfo);
1587
1588 static inline struct VkExtent3D
1589 radv_sanitize_image_extent(const VkImageType imageType,
1590 const struct VkExtent3D imageExtent)
1591 {
1592 switch (imageType) {
1593 case VK_IMAGE_TYPE_1D:
1594 return (VkExtent3D) { imageExtent.width, 1, 1 };
1595 case VK_IMAGE_TYPE_2D:
1596 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1597 case VK_IMAGE_TYPE_3D:
1598 return imageExtent;
1599 default:
1600 unreachable("invalid image type");
1601 }
1602 }
1603
1604 static inline struct VkOffset3D
1605 radv_sanitize_image_offset(const VkImageType imageType,
1606 const struct VkOffset3D imageOffset)
1607 {
1608 switch (imageType) {
1609 case VK_IMAGE_TYPE_1D:
1610 return (VkOffset3D) { imageOffset.x, 0, 0 };
1611 case VK_IMAGE_TYPE_2D:
1612 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1613 case VK_IMAGE_TYPE_3D:
1614 return imageOffset;
1615 default:
1616 unreachable("invalid image type");
1617 }
1618 }
1619
1620 static inline bool
1621 radv_image_extent_compare(const struct radv_image *image,
1622 const VkExtent3D *extent)
1623 {
1624 if (extent->width != image->info.width ||
1625 extent->height != image->info.height ||
1626 extent->depth != image->info.depth)
1627 return false;
1628 return true;
1629 }
1630
1631 struct radv_sampler {
1632 uint32_t state[4];
1633 };
1634
1635 struct radv_color_buffer_info {
1636 uint64_t cb_color_base;
1637 uint64_t cb_color_cmask;
1638 uint64_t cb_color_fmask;
1639 uint64_t cb_dcc_base;
1640 uint32_t cb_color_pitch;
1641 uint32_t cb_color_slice;
1642 uint32_t cb_color_view;
1643 uint32_t cb_color_info;
1644 uint32_t cb_color_attrib;
1645 uint32_t cb_color_attrib2;
1646 uint32_t cb_dcc_control;
1647 uint32_t cb_color_cmask_slice;
1648 uint32_t cb_color_fmask_slice;
1649 };
1650
1651 struct radv_ds_buffer_info {
1652 uint64_t db_z_read_base;
1653 uint64_t db_stencil_read_base;
1654 uint64_t db_z_write_base;
1655 uint64_t db_stencil_write_base;
1656 uint64_t db_htile_data_base;
1657 uint32_t db_depth_info;
1658 uint32_t db_z_info;
1659 uint32_t db_stencil_info;
1660 uint32_t db_depth_view;
1661 uint32_t db_depth_size;
1662 uint32_t db_depth_slice;
1663 uint32_t db_htile_surface;
1664 uint32_t pa_su_poly_offset_db_fmt_cntl;
1665 uint32_t db_z_info2;
1666 uint32_t db_stencil_info2;
1667 float offset_scale;
1668 };
1669
1670 struct radv_attachment_info {
1671 union {
1672 struct radv_color_buffer_info cb;
1673 struct radv_ds_buffer_info ds;
1674 };
1675 struct radv_image_view *attachment;
1676 };
1677
1678 struct radv_framebuffer {
1679 uint32_t width;
1680 uint32_t height;
1681 uint32_t layers;
1682
1683 uint32_t attachment_count;
1684 struct radv_attachment_info attachments[0];
1685 };
1686
1687 struct radv_subpass_barrier {
1688 VkPipelineStageFlags src_stage_mask;
1689 VkAccessFlags src_access_mask;
1690 VkAccessFlags dst_access_mask;
1691 };
1692
1693 struct radv_subpass {
1694 uint32_t input_count;
1695 uint32_t color_count;
1696 VkAttachmentReference * input_attachments;
1697 VkAttachmentReference * color_attachments;
1698 VkAttachmentReference * resolve_attachments;
1699 VkAttachmentReference depth_stencil_attachment;
1700
1701 /** Subpass has at least one resolve attachment */
1702 bool has_resolve;
1703
1704 struct radv_subpass_barrier start_barrier;
1705
1706 uint32_t view_mask;
1707 VkSampleCountFlagBits max_sample_count;
1708 };
1709
1710 struct radv_render_pass_attachment {
1711 VkFormat format;
1712 uint32_t samples;
1713 VkAttachmentLoadOp load_op;
1714 VkAttachmentLoadOp stencil_load_op;
1715 VkImageLayout initial_layout;
1716 VkImageLayout final_layout;
1717 uint32_t view_mask;
1718 };
1719
1720 struct radv_render_pass {
1721 uint32_t attachment_count;
1722 uint32_t subpass_count;
1723 VkAttachmentReference * subpass_attachments;
1724 struct radv_render_pass_attachment * attachments;
1725 struct radv_subpass_barrier end_barrier;
1726 struct radv_subpass subpasses[0];
1727 };
1728
1729 VkResult radv_device_init_meta(struct radv_device *device);
1730 void radv_device_finish_meta(struct radv_device *device);
1731
1732 struct radv_query_pool {
1733 struct radeon_winsys_bo *bo;
1734 uint32_t stride;
1735 uint32_t availability_offset;
1736 uint64_t size;
1737 char *ptr;
1738 VkQueryType type;
1739 uint32_t pipeline_stats_mask;
1740 };
1741
1742 struct radv_semaphore {
1743 /* use a winsys sem for non-exportable */
1744 struct radeon_winsys_sem *sem;
1745 uint32_t syncobj;
1746 uint32_t temp_syncobj;
1747 };
1748
1749 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1750 VkPipelineBindPoint bind_point,
1751 struct radv_descriptor_set *set,
1752 unsigned idx);
1753
1754 void
1755 radv_update_descriptor_sets(struct radv_device *device,
1756 struct radv_cmd_buffer *cmd_buffer,
1757 VkDescriptorSet overrideSet,
1758 uint32_t descriptorWriteCount,
1759 const VkWriteDescriptorSet *pDescriptorWrites,
1760 uint32_t descriptorCopyCount,
1761 const VkCopyDescriptorSet *pDescriptorCopies);
1762
1763 void
1764 radv_update_descriptor_set_with_template(struct radv_device *device,
1765 struct radv_cmd_buffer *cmd_buffer,
1766 struct radv_descriptor_set *set,
1767 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
1768 const void *pData);
1769
1770 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1771 VkPipelineBindPoint pipelineBindPoint,
1772 VkPipelineLayout _layout,
1773 uint32_t set,
1774 uint32_t descriptorWriteCount,
1775 const VkWriteDescriptorSet *pDescriptorWrites);
1776
1777 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1778 struct radv_image *image, uint32_t value);
1779
1780 struct radv_fence {
1781 struct radeon_winsys_fence *fence;
1782 bool submitted;
1783 bool signalled;
1784
1785 uint32_t syncobj;
1786 uint32_t temp_syncobj;
1787 };
1788
1789 /* radv_nir_to_llvm.c */
1790 struct radv_shader_variant_info;
1791 struct radv_nir_compiler_options;
1792
1793 void radv_compile_gs_copy_shader(LLVMTargetMachineRef tm,
1794 struct nir_shader *geom_shader,
1795 struct ac_shader_binary *binary,
1796 struct ac_shader_config *config,
1797 struct radv_shader_variant_info *shader_info,
1798 const struct radv_nir_compiler_options *option);
1799
1800 void radv_compile_nir_shader(LLVMTargetMachineRef tm,
1801 struct ac_shader_binary *binary,
1802 struct ac_shader_config *config,
1803 struct radv_shader_variant_info *shader_info,
1804 struct nir_shader *const *nir,
1805 int nir_count,
1806 const struct radv_nir_compiler_options *options);
1807
1808 /* radv_shader_info.h */
1809 struct radv_shader_info;
1810
1811 void radv_nir_shader_info_pass(const struct nir_shader *nir,
1812 const struct radv_nir_compiler_options *options,
1813 struct radv_shader_info *info);
1814
1815 struct radeon_winsys_sem;
1816
1817 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1818 \
1819 static inline struct __radv_type * \
1820 __radv_type ## _from_handle(__VkType _handle) \
1821 { \
1822 return (struct __radv_type *) _handle; \
1823 } \
1824 \
1825 static inline __VkType \
1826 __radv_type ## _to_handle(struct __radv_type *_obj) \
1827 { \
1828 return (__VkType) _obj; \
1829 }
1830
1831 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1832 \
1833 static inline struct __radv_type * \
1834 __radv_type ## _from_handle(__VkType _handle) \
1835 { \
1836 return (struct __radv_type *)(uintptr_t) _handle; \
1837 } \
1838 \
1839 static inline __VkType \
1840 __radv_type ## _to_handle(struct __radv_type *_obj) \
1841 { \
1842 return (__VkType)(uintptr_t) _obj; \
1843 }
1844
1845 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1846 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1847
1848 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1849 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1850 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1851 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1852 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1853
1854 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1855 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1856 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1857 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1858 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1859 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1860 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
1861 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1862 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1863 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1864 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1865 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1866 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1867 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1868 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1869 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1870 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1871 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1872 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1873 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1874 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
1875
1876 #endif /* RADV_PRIVATE_H */