2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
47 #include "compiler/shader_enums.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "main/macros.h"
53 #include "radv_radeon_winsys.h"
54 #include "ac_binary.h"
55 #include "ac_nir_to_llvm.h"
56 #include "ac_gpu_info.h"
57 #include "ac_surface.h"
58 #include "radv_descriptor_set.h"
60 #include <llvm-c/TargetMachine.h>
62 /* Pre-declarations needed for WSI entrypoints */
65 typedef struct xcb_connection_t xcb_connection_t
;
66 typedef uint32_t xcb_visualid_t
;
67 typedef uint32_t xcb_window_t
;
69 #include <vulkan/vulkan.h>
70 #include <vulkan/vulkan_intel.h>
71 #include <vulkan/vk_icd.h>
73 #include "radv_entrypoints.h"
75 #include "wsi_common.h"
77 #define ATI_VENDOR_ID 0x1002
80 #define MAX_VERTEX_ATTRIBS 32
82 #define MAX_VIEWPORTS 16
83 #define MAX_SCISSORS 16
84 #define MAX_PUSH_CONSTANTS_SIZE 128
85 #define MAX_PUSH_DESCRIPTORS 32
86 #define MAX_DYNAMIC_BUFFERS 16
87 #define MAX_SAMPLES_LOG2 4
88 #define NUM_META_FS_KEYS 13
89 #define RADV_MAX_DRM_DEVICES 8
92 #define NUM_DEPTH_CLEAR_PIPELINES 3
96 RADV_MEM_HEAP_VRAM_CPU_ACCESS
,
103 RADV_MEM_TYPE_GTT_WRITE_COMBINE
,
104 RADV_MEM_TYPE_VRAM_CPU_ACCESS
,
105 RADV_MEM_TYPE_GTT_CACHED
,
109 enum radv_mem_flags_bits
{
110 /* enable implicit synchronization when accessing the underlying bo */
111 RADV_MEM_IMPLICIT_SYNC
= 1 << 0,
114 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
116 static inline uint32_t
117 align_u32(uint32_t v
, uint32_t a
)
119 assert(a
!= 0 && a
== (a
& -a
));
120 return (v
+ a
- 1) & ~(a
- 1);
123 static inline uint32_t
124 align_u32_npot(uint32_t v
, uint32_t a
)
126 return (v
+ a
- 1) / a
* a
;
129 static inline uint64_t
130 align_u64(uint64_t v
, uint64_t a
)
132 assert(a
!= 0 && a
== (a
& -a
));
133 return (v
+ a
- 1) & ~(a
- 1);
136 static inline int32_t
137 align_i32(int32_t v
, int32_t a
)
139 assert(a
!= 0 && a
== (a
& -a
));
140 return (v
+ a
- 1) & ~(a
- 1);
143 /** Alignment must be a power of 2. */
145 radv_is_aligned(uintmax_t n
, uintmax_t a
)
147 assert(a
== (a
& -a
));
148 return (n
& (a
- 1)) == 0;
151 static inline uint32_t
152 round_up_u32(uint32_t v
, uint32_t a
)
154 return (v
+ a
- 1) / a
;
157 static inline uint64_t
158 round_up_u64(uint64_t v
, uint64_t a
)
160 return (v
+ a
- 1) / a
;
163 static inline uint32_t
164 radv_minify(uint32_t n
, uint32_t levels
)
166 if (unlikely(n
== 0))
169 return MAX2(n
>> levels
, 1);
172 radv_clamp_f(float f
, float min
, float max
)
185 radv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
187 if (*inout_mask
& clear_mask
) {
188 *inout_mask
&= ~clear_mask
;
195 #define for_each_bit(b, dword) \
196 for (uint32_t __dword = (dword); \
197 (b) = __builtin_ffs(__dword) - 1, __dword; \
198 __dword &= ~(1 << (b)))
200 #define typed_memcpy(dest, src, count) ({ \
201 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
202 memcpy((dest), (src), (count) * sizeof(*(src))); \
205 /* Whenever we generate an error, pass it through this function. Useful for
206 * debugging, where we can break on it. Only call at error site, not when
207 * propagating errors. Might be useful to plug in a stack trace here.
210 VkResult
__vk_errorf(VkResult error
, const char *file
, int line
, const char *format
, ...);
213 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
214 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
216 #define vk_error(error) error
217 #define vk_errorf(error, format, ...) error
220 void __radv_finishme(const char *file
, int line
, const char *format
, ...)
221 radv_printflike(3, 4);
222 void radv_loge(const char *format
, ...) radv_printflike(1, 2);
223 void radv_loge_v(const char *format
, va_list va
);
226 * Print a FINISHME message, including its source location.
228 #define radv_finishme(format, ...) \
230 static bool reported = false; \
232 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
237 /* A non-fatal assert. Useful for debugging. */
239 #define radv_assert(x) ({ \
240 if (unlikely(!(x))) \
241 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
244 #define radv_assert(x)
247 #define stub_return(v) \
249 radv_finishme("stub %s", __func__); \
255 radv_finishme("stub %s", __func__); \
259 void *radv_lookup_entrypoint(const char *name
);
261 struct radv_physical_device
{
262 VK_LOADER_DATA _loader_data
;
264 struct radv_instance
* instance
;
266 struct radeon_winsys
*ws
;
267 struct radeon_info rad_info
;
270 uint8_t driver_uuid
[VK_UUID_SIZE
];
271 uint8_t device_uuid
[VK_UUID_SIZE
];
272 uint8_t cache_uuid
[VK_UUID_SIZE
];
275 struct wsi_device wsi_device
;
277 bool has_rbplus
; /* if RB+ register exist */
278 bool rbplus_allowed
; /* if RB+ is allowed */
279 bool has_clear_state
;
281 /* This is the drivers on-disk cache used as a fallback as opposed to
282 * the pipeline cache defined by apps.
284 struct disk_cache
* disk_cache
;
286 VkPhysicalDeviceMemoryProperties memory_properties
;
287 enum radv_mem_type mem_type_indices
[RADV_MEM_TYPE_COUNT
];
290 struct radv_instance
{
291 VK_LOADER_DATA _loader_data
;
293 VkAllocationCallbacks alloc
;
296 int physicalDeviceCount
;
297 struct radv_physical_device physicalDevices
[RADV_MAX_DRM_DEVICES
];
299 uint64_t debug_flags
;
300 uint64_t perftest_flags
;
303 VkResult
radv_init_wsi(struct radv_physical_device
*physical_device
);
304 void radv_finish_wsi(struct radv_physical_device
*physical_device
);
306 bool radv_instance_extension_supported(const char *name
);
307 uint32_t radv_physical_device_api_version(struct radv_physical_device
*dev
);
308 bool radv_physical_device_extension_supported(struct radv_physical_device
*dev
,
313 struct radv_pipeline_cache
{
314 struct radv_device
* device
;
315 pthread_mutex_t mutex
;
319 uint32_t kernel_count
;
320 struct cache_entry
** hash_table
;
323 VkAllocationCallbacks alloc
;
326 struct radv_pipeline_key
{
327 uint32_t instance_rate_inputs
;
328 unsigned tess_input_vertices
;
332 uint32_t multisample
: 1;
333 uint32_t has_multiview_view_index
: 1;
337 radv_pipeline_cache_init(struct radv_pipeline_cache
*cache
,
338 struct radv_device
*device
);
340 radv_pipeline_cache_finish(struct radv_pipeline_cache
*cache
);
342 radv_pipeline_cache_load(struct radv_pipeline_cache
*cache
,
343 const void *data
, size_t size
);
345 struct radv_shader_variant
;
348 radv_create_shader_variants_from_pipeline_cache(struct radv_device
*device
,
349 struct radv_pipeline_cache
*cache
,
350 const unsigned char *sha1
,
351 struct radv_shader_variant
**variants
);
354 radv_pipeline_cache_insert_shaders(struct radv_device
*device
,
355 struct radv_pipeline_cache
*cache
,
356 const unsigned char *sha1
,
357 struct radv_shader_variant
**variants
,
358 const void *const *codes
,
359 const unsigned *code_sizes
);
361 struct radv_meta_state
{
362 VkAllocationCallbacks alloc
;
364 struct radv_pipeline_cache cache
;
367 * Use array element `i` for images with `2^i` samples.
370 VkRenderPass render_pass
[NUM_META_FS_KEYS
];
371 VkPipeline color_pipelines
[NUM_META_FS_KEYS
];
373 VkRenderPass depthstencil_rp
;
374 VkPipeline depth_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
375 VkPipeline stencil_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
376 VkPipeline depthstencil_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
377 } clear
[1 + MAX_SAMPLES_LOG2
];
379 VkPipelineLayout clear_color_p_layout
;
380 VkPipelineLayout clear_depth_p_layout
;
382 VkRenderPass render_pass
[NUM_META_FS_KEYS
];
384 /** Pipeline that blits from a 1D image. */
385 VkPipeline pipeline_1d_src
[NUM_META_FS_KEYS
];
387 /** Pipeline that blits from a 2D image. */
388 VkPipeline pipeline_2d_src
[NUM_META_FS_KEYS
];
390 /** Pipeline that blits from a 3D image. */
391 VkPipeline pipeline_3d_src
[NUM_META_FS_KEYS
];
393 VkRenderPass depth_only_rp
;
394 VkPipeline depth_only_1d_pipeline
;
395 VkPipeline depth_only_2d_pipeline
;
396 VkPipeline depth_only_3d_pipeline
;
398 VkRenderPass stencil_only_rp
;
399 VkPipeline stencil_only_1d_pipeline
;
400 VkPipeline stencil_only_2d_pipeline
;
401 VkPipeline stencil_only_3d_pipeline
;
402 VkPipelineLayout pipeline_layout
;
403 VkDescriptorSetLayout ds_layout
;
407 VkRenderPass render_passes
[NUM_META_FS_KEYS
];
409 VkPipelineLayout p_layouts
[2];
410 VkDescriptorSetLayout ds_layouts
[2];
411 VkPipeline pipelines
[2][NUM_META_FS_KEYS
];
413 VkRenderPass depth_only_rp
;
414 VkPipeline depth_only_pipeline
[2];
416 VkRenderPass stencil_only_rp
;
417 VkPipeline stencil_only_pipeline
[2];
421 VkPipelineLayout img_p_layout
;
422 VkDescriptorSetLayout img_ds_layout
;
426 VkPipelineLayout img_p_layout
;
427 VkDescriptorSetLayout img_ds_layout
;
431 VkPipelineLayout img_p_layout
;
432 VkDescriptorSetLayout img_ds_layout
;
436 VkPipelineLayout img_p_layout
;
437 VkDescriptorSetLayout img_ds_layout
;
447 VkDescriptorSetLayout ds_layout
;
448 VkPipelineLayout p_layout
;
451 VkPipeline i_pipeline
;
452 VkPipeline srgb_pipeline
;
453 } rc
[MAX_SAMPLES_LOG2
];
457 VkDescriptorSetLayout ds_layout
;
458 VkPipelineLayout p_layout
;
461 VkRenderPass render_pass
[NUM_META_FS_KEYS
];
462 VkPipeline pipeline
[NUM_META_FS_KEYS
];
463 } rc
[MAX_SAMPLES_LOG2
];
467 VkPipeline decompress_pipeline
;
468 VkPipeline resummarize_pipeline
;
470 } depth_decomp
[1 + MAX_SAMPLES_LOG2
];
473 VkPipeline cmask_eliminate_pipeline
;
474 VkPipeline fmask_decompress_pipeline
;
479 VkPipelineLayout fill_p_layout
;
480 VkPipelineLayout copy_p_layout
;
481 VkDescriptorSetLayout fill_ds_layout
;
482 VkDescriptorSetLayout copy_ds_layout
;
483 VkPipeline fill_pipeline
;
484 VkPipeline copy_pipeline
;
488 VkDescriptorSetLayout ds_layout
;
489 VkPipelineLayout p_layout
;
490 VkPipeline occlusion_query_pipeline
;
491 VkPipeline pipeline_statistics_query_pipeline
;
496 #define RADV_QUEUE_GENERAL 0
497 #define RADV_QUEUE_COMPUTE 1
498 #define RADV_QUEUE_TRANSFER 2
500 #define RADV_MAX_QUEUE_FAMILIES 3
502 enum ring_type
radv_queue_family_to_ring(int f
);
505 VK_LOADER_DATA _loader_data
;
506 struct radv_device
* device
;
507 struct radeon_winsys_ctx
*hw_ctx
;
508 enum radeon_ctx_priority priority
;
509 int queue_family_index
;
512 uint32_t scratch_size
;
513 uint32_t compute_scratch_size
;
514 uint32_t esgs_ring_size
;
515 uint32_t gsvs_ring_size
;
517 bool has_sample_positions
;
519 struct radeon_winsys_bo
*scratch_bo
;
520 struct radeon_winsys_bo
*descriptor_bo
;
521 struct radeon_winsys_bo
*compute_scratch_bo
;
522 struct radeon_winsys_bo
*esgs_ring_bo
;
523 struct radeon_winsys_bo
*gsvs_ring_bo
;
524 struct radeon_winsys_bo
*tess_factor_ring_bo
;
525 struct radeon_winsys_bo
*tess_offchip_ring_bo
;
526 struct radeon_winsys_cs
*initial_preamble_cs
;
527 struct radeon_winsys_cs
*initial_full_flush_preamble_cs
;
528 struct radeon_winsys_cs
*continue_preamble_cs
;
532 VK_LOADER_DATA _loader_data
;
534 VkAllocationCallbacks alloc
;
536 struct radv_instance
* instance
;
537 struct radeon_winsys
*ws
;
539 struct radv_meta_state meta_state
;
541 struct radv_queue
*queues
[RADV_MAX_QUEUE_FAMILIES
];
542 int queue_count
[RADV_MAX_QUEUE_FAMILIES
];
543 struct radeon_winsys_cs
*empty_cs
[RADV_MAX_QUEUE_FAMILIES
];
545 bool llvm_supports_spill
;
546 bool has_distributed_tess
;
548 uint32_t tess_offchip_block_dw_size
;
549 uint32_t scratch_waves
;
551 uint32_t gs_table_depth
;
553 /* MSAA sample locations.
554 * The first index is the sample index.
555 * The second index is the coordinate: X, Y. */
556 float sample_locations_1x
[1][2];
557 float sample_locations_2x
[2][2];
558 float sample_locations_4x
[4][2];
559 float sample_locations_8x
[8][2];
560 float sample_locations_16x
[16][2];
563 uint32_t gfx_init_size_dw
;
564 struct radeon_winsys_bo
*gfx_init
;
566 struct radeon_winsys_bo
*trace_bo
;
567 uint32_t *trace_id_ptr
;
569 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
570 bool keep_shader_info
;
572 struct radv_physical_device
*physical_device
;
574 /* Backup in-memory cache to be used if the app doesn't provide one */
575 struct radv_pipeline_cache
* mem_cache
;
578 * use different counters so MSAA MRTs get consecutive surface indices,
579 * even if MASK is allocated in between.
581 uint32_t image_mrt_offset_counter
;
582 uint32_t fmask_mrt_offset_counter
;
583 struct list_head shader_slabs
;
584 mtx_t shader_slab_mutex
;
586 /* For detecting VM faults reported by dmesg. */
587 uint64_t dmesg_timestamp
;
590 struct radv_device_memory
{
591 struct radeon_winsys_bo
*bo
;
592 /* for dedicated allocations */
593 struct radv_image
*image
;
594 struct radv_buffer
*buffer
;
596 VkDeviceSize map_size
;
601 struct radv_descriptor_range
{
606 struct radv_descriptor_set
{
607 const struct radv_descriptor_set_layout
*layout
;
610 struct radeon_winsys_bo
*bo
;
612 uint32_t *mapped_ptr
;
613 struct radv_descriptor_range
*dynamic_descriptors
;
615 struct radeon_winsys_bo
*descriptors
[0];
618 struct radv_push_descriptor_set
620 struct radv_descriptor_set set
;
624 struct radv_descriptor_pool_entry
{
627 struct radv_descriptor_set
*set
;
630 struct radv_descriptor_pool
{
631 struct radeon_winsys_bo
*bo
;
633 uint64_t current_offset
;
636 uint8_t *host_memory_base
;
637 uint8_t *host_memory_ptr
;
638 uint8_t *host_memory_end
;
640 uint32_t entry_count
;
641 uint32_t max_entry_count
;
642 struct radv_descriptor_pool_entry entries
[0];
645 struct radv_descriptor_update_template_entry
{
646 VkDescriptorType descriptor_type
;
648 /* The number of descriptors to update */
649 uint32_t descriptor_count
;
651 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
654 /* In dwords. Not valid/used for dynamic descriptors */
657 uint32_t buffer_offset
;
659 /* Only valid for combined image samplers and samplers */
660 uint16_t has_sampler
;
666 /* For push descriptors */
667 const uint32_t *immutable_samplers
;
670 struct radv_descriptor_update_template
{
671 uint32_t entry_count
;
672 struct radv_descriptor_update_template_entry entry
[0];
676 struct radv_device
* device
;
679 VkBufferUsageFlags usage
;
680 VkBufferCreateFlags flags
;
683 struct radeon_winsys_bo
* bo
;
690 enum radv_cmd_dirty_bits
{
691 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
692 RADV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
693 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
694 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
695 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
696 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
697 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
698 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
699 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
700 RADV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 9) - 1,
701 RADV_CMD_DIRTY_PIPELINE
= 1 << 9,
702 RADV_CMD_DIRTY_INDEX_BUFFER
= 1 << 10,
703 RADV_CMD_DIRTY_FRAMEBUFFER
= 1 << 11,
705 typedef uint32_t radv_cmd_dirty_mask_t
;
707 enum radv_cmd_flush_bits
{
708 RADV_CMD_FLAG_INV_ICACHE
= 1 << 0,
709 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
710 RADV_CMD_FLAG_INV_SMEM_L1
= 1 << 1,
711 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
712 RADV_CMD_FLAG_INV_VMEM_L1
= 1 << 2,
713 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
714 RADV_CMD_FLAG_INV_GLOBAL_L2
= 1 << 3,
715 /* Same as above, but only writes back and doesn't invalidate */
716 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2
= 1 << 4,
717 /* Framebuffer caches */
718 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
= 1 << 5,
719 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
= 1 << 6,
720 RADV_CMD_FLAG_FLUSH_AND_INV_DB
= 1 << 7,
721 RADV_CMD_FLAG_FLUSH_AND_INV_CB
= 1 << 8,
722 /* Engine synchronization. */
723 RADV_CMD_FLAG_VS_PARTIAL_FLUSH
= 1 << 9,
724 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
= 1 << 10,
725 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
= 1 << 11,
726 RADV_CMD_FLAG_VGT_FLUSH
= 1 << 12,
728 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER
= (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
729 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
730 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
731 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
)
734 struct radv_vertex_binding
{
735 struct radv_buffer
* buffer
;
739 struct radv_viewport_state
{
741 VkViewport viewports
[MAX_VIEWPORTS
];
744 struct radv_scissor_state
{
746 VkRect2D scissors
[MAX_SCISSORS
];
749 struct radv_dynamic_state
{
751 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
752 * Defines the set of saved dynamic state.
756 struct radv_viewport_state viewport
;
758 struct radv_scissor_state scissor
;
768 float blend_constants
[4];
778 } stencil_compare_mask
;
783 } stencil_write_mask
;
791 extern const struct radv_dynamic_state default_dynamic_state
;
794 radv_get_debug_option_name(int id
);
797 radv_get_perftest_option_name(int id
);
800 * Attachment state when recording a renderpass instance.
802 * The clear value is valid only if there exists a pending clear.
804 struct radv_attachment_state
{
805 VkImageAspectFlags pending_clear_aspects
;
806 uint32_t cleared_views
;
807 VkClearValue clear_value
;
808 VkImageLayout current_layout
;
811 struct radv_cmd_state
{
813 bool push_descriptors_dirty
;
815 radv_cmd_dirty_mask_t dirty
;
817 struct radv_pipeline
* pipeline
;
818 struct radv_pipeline
* emitted_pipeline
;
819 struct radv_pipeline
* compute_pipeline
;
820 struct radv_pipeline
* emitted_compute_pipeline
;
821 struct radv_framebuffer
* framebuffer
;
822 struct radv_render_pass
* pass
;
823 const struct radv_subpass
* subpass
;
824 struct radv_dynamic_state dynamic
;
825 struct radv_attachment_state
* attachments
;
826 VkRect2D render_area
;
829 struct radv_buffer
*index_buffer
;
830 uint64_t index_offset
;
832 uint32_t max_index_count
;
835 int32_t last_primitive_reset_en
;
836 uint32_t last_primitive_reset_index
;
837 enum radv_cmd_flush_bits flush_bits
;
838 unsigned active_occlusion_queries
;
840 uint32_t descriptors_dirty
;
841 uint32_t valid_descriptors
;
843 uint32_t last_ia_multi_vgt_param
;
846 struct radv_cmd_pool
{
847 VkAllocationCallbacks alloc
;
848 struct list_head cmd_buffers
;
849 struct list_head free_cmd_buffers
;
850 uint32_t queue_family_index
;
853 struct radv_cmd_buffer_upload
{
857 struct radeon_winsys_bo
*upload_bo
;
858 struct list_head list
;
861 struct radv_cmd_buffer
{
862 VK_LOADER_DATA _loader_data
;
864 struct radv_device
* device
;
866 struct radv_cmd_pool
* pool
;
867 struct list_head pool_link
;
869 VkCommandBufferUsageFlags usage_flags
;
870 VkCommandBufferLevel level
;
871 struct radeon_winsys_cs
*cs
;
872 struct radv_cmd_state state
;
873 struct radv_vertex_binding vertex_bindings
[MAX_VBS
];
874 uint32_t queue_family_index
;
876 uint8_t push_constants
[MAX_PUSH_CONSTANTS_SIZE
];
877 uint32_t dynamic_buffers
[4 * MAX_DYNAMIC_BUFFERS
];
878 VkShaderStageFlags push_constant_stages
;
879 struct radv_push_descriptor_set push_descriptors
;
880 struct radv_descriptor_set meta_push_descriptors
;
881 struct radv_descriptor_set
*descriptors
[MAX_SETS
];
883 struct radv_cmd_buffer_upload upload
;
885 uint32_t scratch_size_needed
;
886 uint32_t compute_scratch_size_needed
;
887 uint32_t esgs_ring_size_needed
;
888 uint32_t gsvs_ring_size_needed
;
889 bool tess_rings_needed
;
890 bool sample_positions_needed
;
892 VkResult record_result
;
894 int ring_offsets_idx
; /* just used for verification */
895 uint32_t gfx9_fence_offset
;
896 struct radeon_winsys_bo
*gfx9_fence_bo
;
897 uint32_t gfx9_fence_idx
;
902 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
);
904 void si_init_compute(struct radv_cmd_buffer
*cmd_buffer
);
905 void si_init_config(struct radv_cmd_buffer
*cmd_buffer
);
907 void cik_create_gfx_config(struct radv_device
*device
);
909 void si_write_viewport(struct radeon_winsys_cs
*cs
, int first_vp
,
910 int count
, const VkViewport
*viewports
);
911 void si_write_scissors(struct radeon_winsys_cs
*cs
, int first
,
912 int count
, const VkRect2D
*scissors
,
913 const VkViewport
*viewports
, bool can_use_guardband
);
914 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer
*cmd_buffer
,
915 bool instanced_draw
, bool indirect_draw
,
916 uint32_t draw_vertex_count
);
917 void si_cs_emit_write_event_eop(struct radeon_winsys_cs
*cs
,
919 enum chip_class chip_class
,
921 unsigned event
, unsigned event_flags
,
927 void si_emit_wait_fence(struct radeon_winsys_cs
*cs
,
929 uint64_t va
, uint32_t ref
,
931 void si_cs_emit_cache_flush(struct radeon_winsys_cs
*cs
,
933 enum chip_class chip_class
,
934 uint32_t *fence_ptr
, uint64_t va
,
936 enum radv_cmd_flush_bits flush_bits
);
937 void si_emit_cache_flush(struct radv_cmd_buffer
*cmd_buffer
);
938 void si_emit_set_predication_state(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
);
939 void si_cp_dma_buffer_copy(struct radv_cmd_buffer
*cmd_buffer
,
940 uint64_t src_va
, uint64_t dest_va
,
942 void si_cp_dma_prefetch(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
944 void si_cp_dma_clear_buffer(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
945 uint64_t size
, unsigned value
);
946 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
);
948 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
951 unsigned *out_offset
,
954 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
955 const struct radv_subpass
*subpass
,
958 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
959 unsigned size
, unsigned alignmnet
,
960 const void *data
, unsigned *out_offset
);
962 radv_emit_framebuffer_state(struct radv_cmd_buffer
*cmd_buffer
);
963 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer
*cmd_buffer
);
964 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer
*cmd_buffer
);
965 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer
*cmd_buffer
);
966 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer
*cmd_buffer
);
967 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs
*cs
, int nr_samples
);
968 unsigned radv_cayman_get_maxdist(int log_samples
);
969 void radv_device_init_msaa(struct radv_device
*device
);
970 void radv_set_depth_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
971 struct radv_image
*image
,
972 VkClearDepthStencilValue ds_clear_value
,
973 VkImageAspectFlags aspects
);
974 void radv_set_color_clear_regs(struct radv_cmd_buffer
*cmd_buffer
,
975 struct radv_image
*image
,
977 uint32_t color_values
[2]);
978 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer
*cmd_buffer
,
979 struct radv_image
*image
,
981 uint32_t radv_fill_buffer(struct radv_cmd_buffer
*cmd_buffer
,
982 struct radeon_winsys_bo
*bo
,
983 uint64_t offset
, uint64_t size
, uint32_t value
);
984 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
);
985 bool radv_get_memory_fd(struct radv_device
*device
,
986 struct radv_device_memory
*memory
,
988 VkResult
radv_alloc_memory(VkDevice _device
,
989 const VkMemoryAllocateInfo
* pAllocateInfo
,
990 const VkAllocationCallbacks
* pAllocator
,
991 enum radv_mem_flags_bits flags
,
992 VkDeviceMemory
* pMem
);
995 * Takes x,y,z as exact numbers of invocations, instead of blocks.
997 * Limitations: Can't call normal dispatch functions without binding or rebinding
998 * the compute pipeline.
1000 void radv_unaligned_dispatch(
1001 struct radv_cmd_buffer
*cmd_buffer
,
1007 struct radeon_winsys_bo
*bo
;
1011 struct radv_shader_module
;
1013 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1014 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1015 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1017 radv_hash_shaders(unsigned char *hash
,
1018 const VkPipelineShaderStageCreateInfo
**stages
,
1019 const struct radv_pipeline_layout
*layout
,
1020 const struct radv_pipeline_key
*key
,
1023 static inline gl_shader_stage
1024 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
1026 assert(__builtin_popcount(vk_stage
) == 1);
1027 return ffs(vk_stage
) - 1;
1030 static inline VkShaderStageFlagBits
1031 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
1033 return (1 << mesa_stage
);
1036 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1038 #define radv_foreach_stage(stage, stage_bits) \
1039 for (gl_shader_stage stage, \
1040 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1041 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1042 __tmp &= ~(1 << (stage)))
1044 struct radv_depth_stencil_state
{
1045 uint32_t db_depth_control
;
1046 uint32_t db_stencil_control
;
1047 uint32_t db_render_control
;
1048 uint32_t db_render_override2
;
1051 struct radv_blend_state
{
1052 uint32_t cb_color_control
;
1053 uint32_t cb_target_mask
;
1054 uint32_t sx_mrt_blend_opt
[8];
1055 uint32_t cb_blend_control
[8];
1057 uint32_t spi_shader_col_format
;
1058 uint32_t cb_shader_mask
;
1059 uint32_t db_alpha_to_mask
;
1062 unsigned radv_format_meta_fs_key(VkFormat format
);
1064 struct radv_raster_state
{
1065 uint32_t pa_cl_clip_cntl
;
1066 uint32_t spi_interp_control
;
1067 uint32_t pa_su_vtx_cntl
;
1068 uint32_t pa_su_sc_mode_cntl
;
1071 struct radv_multisample_state
{
1073 uint32_t pa_sc_line_cntl
;
1074 uint32_t pa_sc_mode_cntl_0
;
1075 uint32_t pa_sc_mode_cntl_1
;
1076 uint32_t pa_sc_aa_config
;
1077 uint32_t pa_sc_aa_mask
[2];
1078 unsigned num_samples
;
1081 struct radv_prim_vertex_count
{
1086 struct radv_tessellation_state
{
1087 uint32_t ls_hs_config
;
1088 uint32_t tcs_in_layout
;
1089 uint32_t tcs_out_layout
;
1090 uint32_t tcs_out_offsets
;
1091 uint32_t offchip_layout
;
1092 unsigned num_patches
;
1094 unsigned num_tcs_input_cp
;
1098 struct radv_gs_state
{
1099 uint32_t vgt_gs_onchip_cntl
;
1100 uint32_t vgt_gs_max_prims_per_subgroup
;
1101 uint32_t vgt_esgs_ring_itemsize
;
1105 struct radv_vertex_elements_info
{
1106 uint32_t rsrc_word3
[MAX_VERTEX_ATTRIBS
];
1107 uint32_t format_size
[MAX_VERTEX_ATTRIBS
];
1108 uint32_t binding
[MAX_VERTEX_ATTRIBS
];
1109 uint32_t offset
[MAX_VERTEX_ATTRIBS
];
1113 #define SI_GS_PER_ES 128
1115 struct radv_pipeline
{
1116 struct radv_device
* device
;
1117 struct radv_dynamic_state dynamic_state
;
1119 struct radv_pipeline_layout
* layout
;
1121 bool needs_data_cache
;
1122 bool need_indirect_descriptor_sets
;
1123 struct radv_shader_variant
* shaders
[MESA_SHADER_STAGES
];
1124 struct radv_shader_variant
*gs_copy_shader
;
1125 VkShaderStageFlags active_stages
;
1127 struct radv_vertex_elements_info vertex_elements
;
1129 uint32_t binding_stride
[MAX_VBS
];
1131 uint32_t user_data_0
[MESA_SHADER_STAGES
];
1134 struct radv_blend_state blend
;
1135 struct radv_depth_stencil_state ds
;
1136 struct radv_raster_state raster
;
1137 struct radv_multisample_state ms
;
1138 struct radv_tessellation_state tess
;
1139 struct radv_gs_state gs
;
1140 uint32_t db_shader_control
;
1141 uint32_t shader_z_format
;
1144 uint32_t vgt_gs_mode
;
1145 bool vgt_primitiveid_en
;
1146 bool prim_restart_enable
;
1147 bool partial_es_wave
;
1148 uint8_t primgroup_size
;
1149 unsigned esgs_ring_size
;
1150 unsigned gsvs_ring_size
;
1151 uint32_t ps_input_cntl
[32];
1152 uint32_t ps_input_cntl_num
;
1153 uint32_t pa_cl_vs_out_cntl
;
1154 uint32_t vgt_shader_stages_en
;
1155 uint32_t vtx_base_sgpr
;
1156 uint32_t base_ia_multi_vgt_param
;
1157 bool wd_switch_on_eop
;
1158 bool ia_switch_on_eoi
;
1159 bool partial_vs_wave
;
1160 uint8_t vtx_emit_num
;
1161 uint32_t vtx_reuse_depth
;
1162 struct radv_prim_vertex_count prim_vertex_count
;
1163 bool can_use_guardband
;
1168 unsigned scratch_bytes_per_wave
;
1171 static inline bool radv_pipeline_has_gs(struct radv_pipeline
*pipeline
)
1173 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
] ? true : false;
1176 static inline bool radv_pipeline_has_tess(struct radv_pipeline
*pipeline
)
1178 return pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] ? true : false;
1181 struct ac_userdata_info
*radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
1182 gl_shader_stage stage
,
1185 struct radv_shader_variant
*radv_get_vertex_shader(struct radv_pipeline
*pipeline
);
1187 struct radv_graphics_pipeline_create_info
{
1189 bool db_depth_clear
;
1190 bool db_stencil_clear
;
1191 bool db_depth_disable_expclear
;
1192 bool db_stencil_disable_expclear
;
1193 bool db_flush_depth_inplace
;
1194 bool db_flush_stencil_inplace
;
1195 bool db_resummarize
;
1196 uint32_t custom_blend_mode
;
1200 radv_graphics_pipeline_create(VkDevice device
,
1201 VkPipelineCache cache
,
1202 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1203 const struct radv_graphics_pipeline_create_info
*extra
,
1204 const VkAllocationCallbacks
*alloc
,
1205 VkPipeline
*pPipeline
);
1207 struct vk_format_description
;
1208 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description
*desc
,
1209 int first_non_void
);
1210 uint32_t radv_translate_buffer_numformat(const struct vk_format_description
*desc
,
1211 int first_non_void
);
1212 uint32_t radv_translate_colorformat(VkFormat format
);
1213 uint32_t radv_translate_color_numformat(VkFormat format
,
1214 const struct vk_format_description
*desc
,
1215 int first_non_void
);
1216 uint32_t radv_colorformat_endian_swap(uint32_t colorformat
);
1217 unsigned radv_translate_colorswap(VkFormat format
, bool do_endian_swap
);
1218 uint32_t radv_translate_dbformat(VkFormat format
);
1219 uint32_t radv_translate_tex_dataformat(VkFormat format
,
1220 const struct vk_format_description
*desc
,
1221 int first_non_void
);
1222 uint32_t radv_translate_tex_numformat(VkFormat format
,
1223 const struct vk_format_description
*desc
,
1224 int first_non_void
);
1225 bool radv_format_pack_clear_color(VkFormat format
,
1226 uint32_t clear_vals
[2],
1227 VkClearColorValue
*value
);
1228 bool radv_is_colorbuffer_format_supported(VkFormat format
, bool *blendable
);
1229 bool radv_dcc_formats_compatible(VkFormat format1
,
1232 struct radv_fmask_info
{
1236 unsigned pitch_in_pixels
;
1237 unsigned bank_height
;
1238 unsigned slice_tile_max
;
1239 unsigned tile_mode_index
;
1240 unsigned tile_swizzle
;
1243 struct radv_cmask_info
{
1247 unsigned slice_tile_max
;
1248 unsigned base_address_reg
;
1253 /* The original VkFormat provided by the client. This may not match any
1254 * of the actual surface formats.
1257 VkImageAspectFlags aspects
;
1258 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
1259 struct ac_surf_info info
;
1260 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
1261 VkImageCreateFlags flags
; /** VkImageCreateInfo::flags */
1266 unsigned queue_family_mask
;
1270 /* Set when bound */
1271 struct radeon_winsys_bo
*bo
;
1272 VkDeviceSize offset
;
1273 uint64_t dcc_offset
;
1274 uint64_t htile_offset
;
1275 bool tc_compatible_htile
;
1276 struct radeon_surf surface
;
1278 struct radv_fmask_info fmask
;
1279 struct radv_cmask_info cmask
;
1280 uint64_t clear_value_offset
;
1281 uint64_t dcc_pred_offset
;
1284 /* Whether the image has a htile that is known consistent with the contents of
1286 bool radv_layout_has_htile(const struct radv_image
*image
,
1287 VkImageLayout layout
,
1288 unsigned queue_mask
);
1290 /* Whether the image has a htile that is known consistent with the contents of
1291 * the image and is allowed to be in compressed form.
1293 * If this is false reads that don't use the htile should be able to return
1296 bool radv_layout_is_htile_compressed(const struct radv_image
*image
,
1297 VkImageLayout layout
,
1298 unsigned queue_mask
);
1300 bool radv_layout_can_fast_clear(const struct radv_image
*image
,
1301 VkImageLayout layout
,
1302 unsigned queue_mask
);
1305 radv_vi_dcc_enabled(const struct radv_image
*image
, unsigned level
)
1307 return image
->surface
.dcc_size
&& level
< image
->surface
.num_dcc_levels
;
1311 radv_htile_enabled(const struct radv_image
*image
, unsigned level
)
1313 return image
->surface
.htile_size
&& level
== 0;
1316 unsigned radv_image_queue_family_mask(const struct radv_image
*image
, uint32_t family
, uint32_t queue_family
);
1318 static inline uint32_t
1319 radv_get_layerCount(const struct radv_image
*image
,
1320 const VkImageSubresourceRange
*range
)
1322 return range
->layerCount
== VK_REMAINING_ARRAY_LAYERS
?
1323 image
->info
.array_size
- range
->baseArrayLayer
: range
->layerCount
;
1326 static inline uint32_t
1327 radv_get_levelCount(const struct radv_image
*image
,
1328 const VkImageSubresourceRange
*range
)
1330 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
1331 image
->info
.levels
- range
->baseMipLevel
: range
->levelCount
;
1334 struct radeon_bo_metadata
;
1336 radv_init_metadata(struct radv_device
*device
,
1337 struct radv_image
*image
,
1338 struct radeon_bo_metadata
*metadata
);
1340 struct radv_image_view
{
1341 struct radv_image
*image
; /**< VkImageViewCreateInfo::image */
1342 struct radeon_winsys_bo
*bo
;
1344 VkImageViewType type
;
1345 VkImageAspectFlags aspect_mask
;
1347 uint32_t base_layer
;
1348 uint32_t layer_count
;
1350 uint32_t level_count
;
1351 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1353 uint32_t descriptor
[8];
1354 uint32_t fmask_descriptor
[8];
1356 /* Descriptor for use as a storage image as opposed to a sampled image.
1357 * This has a few differences for cube maps (e.g. type).
1359 uint32_t storage_descriptor
[8];
1360 uint32_t storage_fmask_descriptor
[8];
1363 struct radv_image_create_info
{
1364 const VkImageCreateInfo
*vk_info
;
1368 VkResult
radv_image_create(VkDevice _device
,
1369 const struct radv_image_create_info
*info
,
1370 const VkAllocationCallbacks
* alloc
,
1373 void radv_image_view_init(struct radv_image_view
*view
,
1374 struct radv_device
*device
,
1375 const VkImageViewCreateInfo
* pCreateInfo
);
1377 struct radv_buffer_view
{
1378 struct radeon_winsys_bo
*bo
;
1380 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1383 void radv_buffer_view_init(struct radv_buffer_view
*view
,
1384 struct radv_device
*device
,
1385 const VkBufferViewCreateInfo
* pCreateInfo
);
1387 static inline struct VkExtent3D
1388 radv_sanitize_image_extent(const VkImageType imageType
,
1389 const struct VkExtent3D imageExtent
)
1391 switch (imageType
) {
1392 case VK_IMAGE_TYPE_1D
:
1393 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
1394 case VK_IMAGE_TYPE_2D
:
1395 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
1396 case VK_IMAGE_TYPE_3D
:
1399 unreachable("invalid image type");
1403 static inline struct VkOffset3D
1404 radv_sanitize_image_offset(const VkImageType imageType
,
1405 const struct VkOffset3D imageOffset
)
1407 switch (imageType
) {
1408 case VK_IMAGE_TYPE_1D
:
1409 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
1410 case VK_IMAGE_TYPE_2D
:
1411 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
1412 case VK_IMAGE_TYPE_3D
:
1415 unreachable("invalid image type");
1420 radv_image_extent_compare(const struct radv_image
*image
,
1421 const VkExtent3D
*extent
)
1423 if (extent
->width
!= image
->info
.width
||
1424 extent
->height
!= image
->info
.height
||
1425 extent
->depth
!= image
->info
.depth
)
1430 struct radv_sampler
{
1434 struct radv_color_buffer_info
{
1435 uint64_t cb_color_base
;
1436 uint64_t cb_color_cmask
;
1437 uint64_t cb_color_fmask
;
1438 uint64_t cb_dcc_base
;
1439 uint32_t cb_color_pitch
;
1440 uint32_t cb_color_slice
;
1441 uint32_t cb_color_view
;
1442 uint32_t cb_color_info
;
1443 uint32_t cb_color_attrib
;
1444 uint32_t cb_color_attrib2
;
1445 uint32_t cb_dcc_control
;
1446 uint32_t cb_color_cmask_slice
;
1447 uint32_t cb_color_fmask_slice
;
1448 uint32_t cb_clear_value0
;
1449 uint32_t cb_clear_value1
;
1450 uint32_t micro_tile_mode
;
1451 uint32_t gfx9_epitch
;
1454 struct radv_ds_buffer_info
{
1455 uint64_t db_z_read_base
;
1456 uint64_t db_stencil_read_base
;
1457 uint64_t db_z_write_base
;
1458 uint64_t db_stencil_write_base
;
1459 uint64_t db_htile_data_base
;
1460 uint32_t db_depth_info
;
1462 uint32_t db_stencil_info
;
1463 uint32_t db_depth_view
;
1464 uint32_t db_depth_size
;
1465 uint32_t db_depth_slice
;
1466 uint32_t db_htile_surface
;
1467 uint32_t pa_su_poly_offset_db_fmt_cntl
;
1468 uint32_t db_z_info2
;
1469 uint32_t db_stencil_info2
;
1473 struct radv_attachment_info
{
1475 struct radv_color_buffer_info cb
;
1476 struct radv_ds_buffer_info ds
;
1478 struct radv_image_view
*attachment
;
1481 struct radv_framebuffer
{
1486 uint32_t attachment_count
;
1487 struct radv_attachment_info attachments
[0];
1490 struct radv_subpass_barrier
{
1491 VkPipelineStageFlags src_stage_mask
;
1492 VkAccessFlags src_access_mask
;
1493 VkAccessFlags dst_access_mask
;
1496 struct radv_subpass
{
1497 uint32_t input_count
;
1498 uint32_t color_count
;
1499 VkAttachmentReference
* input_attachments
;
1500 VkAttachmentReference
* color_attachments
;
1501 VkAttachmentReference
* resolve_attachments
;
1502 VkAttachmentReference depth_stencil_attachment
;
1504 /** Subpass has at least one resolve attachment */
1507 struct radv_subpass_barrier start_barrier
;
1512 struct radv_render_pass_attachment
{
1515 VkAttachmentLoadOp load_op
;
1516 VkAttachmentLoadOp stencil_load_op
;
1517 VkImageLayout initial_layout
;
1518 VkImageLayout final_layout
;
1522 struct radv_render_pass
{
1523 uint32_t attachment_count
;
1524 uint32_t subpass_count
;
1525 VkAttachmentReference
* subpass_attachments
;
1526 struct radv_render_pass_attachment
* attachments
;
1527 struct radv_subpass_barrier end_barrier
;
1528 struct radv_subpass subpasses
[0];
1531 VkResult
radv_device_init_meta(struct radv_device
*device
);
1532 void radv_device_finish_meta(struct radv_device
*device
);
1534 struct radv_query_pool
{
1535 struct radeon_winsys_bo
*bo
;
1537 uint32_t availability_offset
;
1540 uint32_t pipeline_stats_mask
;
1543 struct radv_semaphore
{
1544 /* use a winsys sem for non-exportable */
1545 struct radeon_winsys_sem
*sem
;
1547 uint32_t temp_syncobj
;
1550 VkResult
radv_alloc_sem_info(struct radv_winsys_sem_info
*sem_info
,
1552 const VkSemaphore
*wait_sems
,
1553 int num_signal_sems
,
1554 const VkSemaphore
*signal_sems
);
1555 void radv_free_sem_info(struct radv_winsys_sem_info
*sem_info
);
1557 void radv_set_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
1558 struct radv_descriptor_set
*set
,
1562 radv_update_descriptor_sets(struct radv_device
*device
,
1563 struct radv_cmd_buffer
*cmd_buffer
,
1564 VkDescriptorSet overrideSet
,
1565 uint32_t descriptorWriteCount
,
1566 const VkWriteDescriptorSet
*pDescriptorWrites
,
1567 uint32_t descriptorCopyCount
,
1568 const VkCopyDescriptorSet
*pDescriptorCopies
);
1571 radv_update_descriptor_set_with_template(struct radv_device
*device
,
1572 struct radv_cmd_buffer
*cmd_buffer
,
1573 struct radv_descriptor_set
*set
,
1574 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate
,
1577 void radv_meta_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
1578 VkPipelineBindPoint pipelineBindPoint
,
1579 VkPipelineLayout _layout
,
1581 uint32_t descriptorWriteCount
,
1582 const VkWriteDescriptorSet
*pDescriptorWrites
);
1584 void radv_initialise_cmask(struct radv_cmd_buffer
*cmd_buffer
,
1585 struct radv_image
*image
, uint32_t value
);
1586 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
1587 struct radv_image
*image
, uint32_t value
);
1590 struct radeon_winsys_fence
*fence
;
1595 struct radeon_winsys_sem
;
1597 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1599 static inline struct __radv_type * \
1600 __radv_type ## _from_handle(__VkType _handle) \
1602 return (struct __radv_type *) _handle; \
1605 static inline __VkType \
1606 __radv_type ## _to_handle(struct __radv_type *_obj) \
1608 return (__VkType) _obj; \
1611 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1613 static inline struct __radv_type * \
1614 __radv_type ## _from_handle(__VkType _handle) \
1616 return (struct __radv_type *)(uintptr_t) _handle; \
1619 static inline __VkType \
1620 __radv_type ## _to_handle(struct __radv_type *_obj) \
1622 return (__VkType)(uintptr_t) _obj; \
1625 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1626 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1628 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer
, VkCommandBuffer
)
1629 RADV_DEFINE_HANDLE_CASTS(radv_device
, VkDevice
)
1630 RADV_DEFINE_HANDLE_CASTS(radv_instance
, VkInstance
)
1631 RADV_DEFINE_HANDLE_CASTS(radv_physical_device
, VkPhysicalDevice
)
1632 RADV_DEFINE_HANDLE_CASTS(radv_queue
, VkQueue
)
1634 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool
, VkCommandPool
)
1635 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer
, VkBuffer
)
1636 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view
, VkBufferView
)
1637 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool
, VkDescriptorPool
)
1638 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set
, VkDescriptorSet
)
1639 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout
, VkDescriptorSetLayout
)
1640 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template
, VkDescriptorUpdateTemplateKHR
)
1641 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory
, VkDeviceMemory
)
1642 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence
, VkFence
)
1643 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event
, VkEvent
)
1644 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer
, VkFramebuffer
)
1645 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image
, VkImage
)
1646 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view
, VkImageView
);
1647 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache
, VkPipelineCache
)
1648 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline
, VkPipeline
)
1649 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout
, VkPipelineLayout
)
1650 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool
, VkQueryPool
)
1651 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass
, VkRenderPass
)
1652 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler
, VkSampler
)
1653 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module
, VkShaderModule
)
1654 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore
, VkSemaphore
)
1656 #endif /* RADV_PRIVATE_H */