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radv: Add the concept of radv shader binaries.
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x)
44 #endif
45
46 #include "c11/threads.h"
47 #include <amdgpu.h>
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "util/xmlconfig.h"
52 #include "main/macros.h"
53 #include "vk_alloc.h"
54 #include "vk_debug_report.h"
55
56 #include "radv_radeon_winsys.h"
57 #include "ac_binary.h"
58 #include "ac_nir_to_llvm.h"
59 #include "ac_gpu_info.h"
60 #include "ac_surface.h"
61 #include "ac_llvm_build.h"
62 #include "ac_llvm_util.h"
63 #include "radv_descriptor_set.h"
64 #include "radv_extensions.h"
65 #include "radv_cs.h"
66
67 #include <llvm-c/TargetMachine.h>
68
69 /* Pre-declarations needed for WSI entrypoints */
70 struct wl_surface;
71 struct wl_display;
72 typedef struct xcb_connection_t xcb_connection_t;
73 typedef uint32_t xcb_visualid_t;
74 typedef uint32_t xcb_window_t;
75
76 #include <vulkan/vulkan.h>
77 #include <vulkan/vulkan_intel.h>
78 #include <vulkan/vk_icd.h>
79 #include <vulkan/vk_android_native_buffer.h>
80
81 #include "radv_entrypoints.h"
82
83 #include "wsi_common.h"
84 #include "wsi_common_display.h"
85
86 #define ATI_VENDOR_ID 0x1002
87
88 #define MAX_VBS 32
89 #define MAX_VERTEX_ATTRIBS 32
90 #define MAX_RTS 8
91 #define MAX_VIEWPORTS 16
92 #define MAX_SCISSORS 16
93 #define MAX_DISCARD_RECTANGLES 4
94 #define MAX_SAMPLE_LOCATIONS 32
95 #define MAX_PUSH_CONSTANTS_SIZE 128
96 #define MAX_PUSH_DESCRIPTORS 32
97 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
98 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
99 #define MAX_DYNAMIC_BUFFERS (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
100 #define MAX_SAMPLES_LOG2 4
101 #define NUM_META_FS_KEYS 12
102 #define RADV_MAX_DRM_DEVICES 8
103 #define MAX_VIEWS 8
104 #define MAX_SO_STREAMS 4
105 #define MAX_SO_BUFFERS 4
106 #define MAX_SO_OUTPUTS 64
107 #define MAX_INLINE_UNIFORM_BLOCK_SIZE (4ull * 1024 * 1024)
108 #define MAX_INLINE_UNIFORM_BLOCK_COUNT 64
109
110 #define NUM_DEPTH_CLEAR_PIPELINES 3
111
112 /*
113 * This is the point we switch from using CP to compute shader
114 * for certain buffer operations.
115 */
116 #define RADV_BUFFER_OPS_CS_THRESHOLD 4096
117
118 #define RADV_BUFFER_UPDATE_THRESHOLD 1024
119
120 enum radv_mem_heap {
121 RADV_MEM_HEAP_VRAM,
122 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
123 RADV_MEM_HEAP_GTT,
124 RADV_MEM_HEAP_COUNT
125 };
126
127 enum radv_mem_type {
128 RADV_MEM_TYPE_VRAM,
129 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
130 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
131 RADV_MEM_TYPE_GTT_CACHED,
132 RADV_MEM_TYPE_COUNT
133 };
134
135 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
136
137 static inline uint32_t
138 align_u32(uint32_t v, uint32_t a)
139 {
140 assert(a != 0 && a == (a & -a));
141 return (v + a - 1) & ~(a - 1);
142 }
143
144 static inline uint32_t
145 align_u32_npot(uint32_t v, uint32_t a)
146 {
147 return (v + a - 1) / a * a;
148 }
149
150 static inline uint64_t
151 align_u64(uint64_t v, uint64_t a)
152 {
153 assert(a != 0 && a == (a & -a));
154 return (v + a - 1) & ~(a - 1);
155 }
156
157 static inline int32_t
158 align_i32(int32_t v, int32_t a)
159 {
160 assert(a != 0 && a == (a & -a));
161 return (v + a - 1) & ~(a - 1);
162 }
163
164 /** Alignment must be a power of 2. */
165 static inline bool
166 radv_is_aligned(uintmax_t n, uintmax_t a)
167 {
168 assert(a == (a & -a));
169 return (n & (a - 1)) == 0;
170 }
171
172 static inline uint32_t
173 round_up_u32(uint32_t v, uint32_t a)
174 {
175 return (v + a - 1) / a;
176 }
177
178 static inline uint64_t
179 round_up_u64(uint64_t v, uint64_t a)
180 {
181 return (v + a - 1) / a;
182 }
183
184 static inline uint32_t
185 radv_minify(uint32_t n, uint32_t levels)
186 {
187 if (unlikely(n == 0))
188 return 0;
189 else
190 return MAX2(n >> levels, 1);
191 }
192 static inline float
193 radv_clamp_f(float f, float min, float max)
194 {
195 assert(min < max);
196
197 if (f > max)
198 return max;
199 else if (f < min)
200 return min;
201 else
202 return f;
203 }
204
205 static inline bool
206 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
207 {
208 if (*inout_mask & clear_mask) {
209 *inout_mask &= ~clear_mask;
210 return true;
211 } else {
212 return false;
213 }
214 }
215
216 #define for_each_bit(b, dword) \
217 for (uint32_t __dword = (dword); \
218 (b) = __builtin_ffs(__dword) - 1, __dword; \
219 __dword &= ~(1 << (b)))
220
221 #define typed_memcpy(dest, src, count) ({ \
222 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
223 memcpy((dest), (src), (count) * sizeof(*(src))); \
224 })
225
226 /* Whenever we generate an error, pass it through this function. Useful for
227 * debugging, where we can break on it. Only call at error site, not when
228 * propagating errors. Might be useful to plug in a stack trace here.
229 */
230
231 struct radv_instance;
232
233 VkResult __vk_errorf(struct radv_instance *instance, VkResult error, const char *file, int line, const char *format, ...);
234
235 #define vk_error(instance, error) __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
236 #define vk_errorf(instance, error, format, ...) __vk_errorf(instance, error, __FILE__, __LINE__, format, ## __VA_ARGS__);
237
238 void __radv_finishme(const char *file, int line, const char *format, ...)
239 radv_printflike(3, 4);
240 void radv_loge(const char *format, ...) radv_printflike(1, 2);
241 void radv_loge_v(const char *format, va_list va);
242 void radv_logi(const char *format, ...) radv_printflike(1, 2);
243 void radv_logi_v(const char *format, va_list va);
244
245 /**
246 * Print a FINISHME message, including its source location.
247 */
248 #define radv_finishme(format, ...) \
249 do { \
250 static bool reported = false; \
251 if (!reported) { \
252 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
253 reported = true; \
254 } \
255 } while (0)
256
257 /* A non-fatal assert. Useful for debugging. */
258 #ifdef DEBUG
259 #define radv_assert(x) ({ \
260 if (unlikely(!(x))) \
261 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
262 })
263 #else
264 #define radv_assert(x)
265 #endif
266
267 #define stub_return(v) \
268 do { \
269 radv_finishme("stub %s", __func__); \
270 return (v); \
271 } while (0)
272
273 #define stub() \
274 do { \
275 radv_finishme("stub %s", __func__); \
276 return; \
277 } while (0)
278
279 void *radv_lookup_entrypoint_unchecked(const char *name);
280 void *radv_lookup_entrypoint_checked(const char *name,
281 uint32_t core_version,
282 const struct radv_instance_extension_table *instance,
283 const struct radv_device_extension_table *device);
284 void *radv_lookup_physical_device_entrypoint_checked(const char *name,
285 uint32_t core_version,
286 const struct radv_instance_extension_table *instance);
287
288 struct radv_physical_device {
289 VK_LOADER_DATA _loader_data;
290
291 struct radv_instance * instance;
292
293 struct radeon_winsys *ws;
294 struct radeon_info rad_info;
295 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
296 uint8_t driver_uuid[VK_UUID_SIZE];
297 uint8_t device_uuid[VK_UUID_SIZE];
298 uint8_t cache_uuid[VK_UUID_SIZE];
299
300 int local_fd;
301 int master_fd;
302 struct wsi_device wsi_device;
303
304 bool has_rbplus; /* if RB+ register exist */
305 bool rbplus_allowed; /* if RB+ is allowed */
306 bool has_clear_state;
307 bool cpdma_prefetch_writes_memory;
308 bool has_scissor_bug;
309
310 bool has_out_of_order_rast;
311 bool out_of_order_rast_allowed;
312
313 /* Whether DCC should be enabled for MSAA textures. */
314 bool dcc_msaa_allowed;
315
316 /* Whether LOAD_CONTEXT_REG packets are supported. */
317 bool has_load_ctx_reg_pkt;
318
319 /* Whether to enable the AMD_shader_ballot extension */
320 bool use_shader_ballot;
321
322 /* Whether DISABLE_CONSTANT_ENCODE_REG is supported. */
323 bool has_dcc_constant_encode;
324
325 /* This is the drivers on-disk cache used as a fallback as opposed to
326 * the pipeline cache defined by apps.
327 */
328 struct disk_cache * disk_cache;
329
330 VkPhysicalDeviceMemoryProperties memory_properties;
331 enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
332
333 drmPciBusInfo bus_info;
334
335 struct radv_device_extension_table supported_extensions;
336 };
337
338 struct radv_instance {
339 VK_LOADER_DATA _loader_data;
340
341 VkAllocationCallbacks alloc;
342
343 uint32_t apiVersion;
344 int physicalDeviceCount;
345 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
346
347 uint64_t debug_flags;
348 uint64_t perftest_flags;
349
350 struct vk_debug_report_instance debug_report_callbacks;
351
352 struct radv_instance_extension_table enabled_extensions;
353
354 struct driOptionCache dri_options;
355 struct driOptionCache available_dri_options;
356 };
357
358 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
359 void radv_finish_wsi(struct radv_physical_device *physical_device);
360
361 bool radv_instance_extension_supported(const char *name);
362 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
363 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
364 const char *name);
365
366 struct cache_entry;
367
368 struct radv_pipeline_cache {
369 struct radv_device * device;
370 pthread_mutex_t mutex;
371
372 uint32_t total_size;
373 uint32_t table_size;
374 uint32_t kernel_count;
375 struct cache_entry ** hash_table;
376 bool modified;
377
378 VkAllocationCallbacks alloc;
379 };
380
381 struct radv_pipeline_key {
382 uint32_t instance_rate_inputs;
383 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
384 uint8_t vertex_attribute_formats[MAX_VERTEX_ATTRIBS];
385 uint32_t vertex_attribute_bindings[MAX_VERTEX_ATTRIBS];
386 uint32_t vertex_attribute_offsets[MAX_VERTEX_ATTRIBS];
387 uint32_t vertex_attribute_strides[MAX_VERTEX_ATTRIBS];
388 uint64_t vertex_alpha_adjust;
389 uint32_t vertex_post_shuffle;
390 unsigned tess_input_vertices;
391 uint32_t col_format;
392 uint32_t is_int8;
393 uint32_t is_int10;
394 uint8_t log2_ps_iter_samples;
395 uint8_t num_samples;
396 uint32_t has_multiview_view_index : 1;
397 uint32_t optimisations_disabled : 1;
398 };
399
400 struct radv_shader_binary;
401 struct radv_shader_variant;
402
403 void
404 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
405 struct radv_device *device);
406 void
407 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
408 bool
409 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
410 const void *data, size_t size);
411
412 bool
413 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
414 struct radv_pipeline_cache *cache,
415 const unsigned char *sha1,
416 struct radv_shader_variant **variants,
417 bool *found_in_application_cache);
418
419 void
420 radv_pipeline_cache_insert_shaders(struct radv_device *device,
421 struct radv_pipeline_cache *cache,
422 const unsigned char *sha1,
423 struct radv_shader_variant **variants,
424 struct radv_shader_binary *const *binaries);
425
426 enum radv_blit_ds_layout {
427 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
428 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
429 RADV_BLIT_DS_LAYOUT_COUNT,
430 };
431
432 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
433 {
434 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
435 }
436
437 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
438 {
439 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
440 }
441
442 enum radv_meta_dst_layout {
443 RADV_META_DST_LAYOUT_GENERAL,
444 RADV_META_DST_LAYOUT_OPTIMAL,
445 RADV_META_DST_LAYOUT_COUNT,
446 };
447
448 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
449 {
450 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
451 }
452
453 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
454 {
455 return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
456 }
457
458 struct radv_meta_state {
459 VkAllocationCallbacks alloc;
460
461 struct radv_pipeline_cache cache;
462
463 /*
464 * For on-demand pipeline creation, makes sure that
465 * only one thread tries to build a pipeline at the same time.
466 */
467 mtx_t mtx;
468
469 /**
470 * Use array element `i` for images with `2^i` samples.
471 */
472 struct {
473 VkRenderPass render_pass[NUM_META_FS_KEYS];
474 VkPipeline color_pipelines[NUM_META_FS_KEYS];
475
476 VkRenderPass depthstencil_rp;
477 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
478 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
479 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
480 } clear[1 + MAX_SAMPLES_LOG2];
481
482 VkPipelineLayout clear_color_p_layout;
483 VkPipelineLayout clear_depth_p_layout;
484
485 /* Optimized compute fast HTILE clear for stencil or depth only. */
486 VkPipeline clear_htile_mask_pipeline;
487 VkPipelineLayout clear_htile_mask_p_layout;
488 VkDescriptorSetLayout clear_htile_mask_ds_layout;
489
490 struct {
491 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
492
493 /** Pipeline that blits from a 1D image. */
494 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
495
496 /** Pipeline that blits from a 2D image. */
497 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
498
499 /** Pipeline that blits from a 3D image. */
500 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
501
502 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
503 VkPipeline depth_only_1d_pipeline;
504 VkPipeline depth_only_2d_pipeline;
505 VkPipeline depth_only_3d_pipeline;
506
507 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
508 VkPipeline stencil_only_1d_pipeline;
509 VkPipeline stencil_only_2d_pipeline;
510 VkPipeline stencil_only_3d_pipeline;
511 VkPipelineLayout pipeline_layout;
512 VkDescriptorSetLayout ds_layout;
513 } blit;
514
515 struct {
516 VkPipelineLayout p_layouts[5];
517 VkDescriptorSetLayout ds_layouts[5];
518 VkPipeline pipelines[5][NUM_META_FS_KEYS];
519
520 VkPipeline depth_only_pipeline[5];
521
522 VkPipeline stencil_only_pipeline[5];
523 } blit2d[1 + MAX_SAMPLES_LOG2];
524
525 VkRenderPass blit2d_render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
526 VkRenderPass blit2d_depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
527 VkRenderPass blit2d_stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
528
529 struct {
530 VkPipelineLayout img_p_layout;
531 VkDescriptorSetLayout img_ds_layout;
532 VkPipeline pipeline;
533 VkPipeline pipeline_3d;
534 } itob;
535 struct {
536 VkPipelineLayout img_p_layout;
537 VkDescriptorSetLayout img_ds_layout;
538 VkPipeline pipeline;
539 VkPipeline pipeline_3d;
540 } btoi;
541 struct {
542 VkPipelineLayout img_p_layout;
543 VkDescriptorSetLayout img_ds_layout;
544 VkPipeline pipeline;
545 } btoi_r32g32b32;
546 struct {
547 VkPipelineLayout img_p_layout;
548 VkDescriptorSetLayout img_ds_layout;
549 VkPipeline pipeline;
550 VkPipeline pipeline_3d;
551 } itoi;
552 struct {
553 VkPipelineLayout img_p_layout;
554 VkDescriptorSetLayout img_ds_layout;
555 VkPipeline pipeline;
556 } itoi_r32g32b32;
557 struct {
558 VkPipelineLayout img_p_layout;
559 VkDescriptorSetLayout img_ds_layout;
560 VkPipeline pipeline;
561 VkPipeline pipeline_3d;
562 } cleari;
563 struct {
564 VkPipelineLayout img_p_layout;
565 VkDescriptorSetLayout img_ds_layout;
566 VkPipeline pipeline;
567 } cleari_r32g32b32;
568
569 struct {
570 VkPipelineLayout p_layout;
571 VkPipeline pipeline[NUM_META_FS_KEYS];
572 VkRenderPass pass[NUM_META_FS_KEYS];
573 } resolve;
574
575 struct {
576 VkDescriptorSetLayout ds_layout;
577 VkPipelineLayout p_layout;
578 struct {
579 VkPipeline pipeline;
580 VkPipeline i_pipeline;
581 VkPipeline srgb_pipeline;
582 } rc[MAX_SAMPLES_LOG2];
583
584 VkPipeline depth_zero_pipeline;
585 struct {
586 VkPipeline average_pipeline;
587 VkPipeline max_pipeline;
588 VkPipeline min_pipeline;
589 } depth[MAX_SAMPLES_LOG2];
590
591 VkPipeline stencil_zero_pipeline;
592 struct {
593 VkPipeline max_pipeline;
594 VkPipeline min_pipeline;
595 } stencil[MAX_SAMPLES_LOG2];
596 } resolve_compute;
597
598 struct {
599 VkDescriptorSetLayout ds_layout;
600 VkPipelineLayout p_layout;
601
602 struct {
603 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
604 VkPipeline pipeline[NUM_META_FS_KEYS];
605 } rc[MAX_SAMPLES_LOG2];
606
607 VkRenderPass depth_render_pass;
608 VkPipeline depth_zero_pipeline;
609 struct {
610 VkPipeline average_pipeline;
611 VkPipeline max_pipeline;
612 VkPipeline min_pipeline;
613 } depth[MAX_SAMPLES_LOG2];
614
615 VkRenderPass stencil_render_pass;
616 VkPipeline stencil_zero_pipeline;
617 struct {
618 VkPipeline max_pipeline;
619 VkPipeline min_pipeline;
620 } stencil[MAX_SAMPLES_LOG2];
621 } resolve_fragment;
622
623 struct {
624 VkPipelineLayout p_layout;
625 VkPipeline decompress_pipeline;
626 VkPipeline resummarize_pipeline;
627 VkRenderPass pass;
628 } depth_decomp[1 + MAX_SAMPLES_LOG2];
629
630 struct {
631 VkPipelineLayout p_layout;
632 VkPipeline cmask_eliminate_pipeline;
633 VkPipeline fmask_decompress_pipeline;
634 VkPipeline dcc_decompress_pipeline;
635 VkRenderPass pass;
636
637 VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
638 VkPipelineLayout dcc_decompress_compute_p_layout;
639 VkPipeline dcc_decompress_compute_pipeline;
640 } fast_clear_flush;
641
642 struct {
643 VkPipelineLayout fill_p_layout;
644 VkPipelineLayout copy_p_layout;
645 VkDescriptorSetLayout fill_ds_layout;
646 VkDescriptorSetLayout copy_ds_layout;
647 VkPipeline fill_pipeline;
648 VkPipeline copy_pipeline;
649 } buffer;
650
651 struct {
652 VkDescriptorSetLayout ds_layout;
653 VkPipelineLayout p_layout;
654 VkPipeline occlusion_query_pipeline;
655 VkPipeline pipeline_statistics_query_pipeline;
656 VkPipeline tfb_query_pipeline;
657 } query;
658
659 struct {
660 VkDescriptorSetLayout ds_layout;
661 VkPipelineLayout p_layout;
662 VkPipeline pipeline[MAX_SAMPLES_LOG2];
663 } fmask_expand;
664 };
665
666 /* queue types */
667 #define RADV_QUEUE_GENERAL 0
668 #define RADV_QUEUE_COMPUTE 1
669 #define RADV_QUEUE_TRANSFER 2
670
671 #define RADV_MAX_QUEUE_FAMILIES 3
672
673 enum ring_type radv_queue_family_to_ring(int f);
674
675 struct radv_queue {
676 VK_LOADER_DATA _loader_data;
677 struct radv_device * device;
678 struct radeon_winsys_ctx *hw_ctx;
679 enum radeon_ctx_priority priority;
680 uint32_t queue_family_index;
681 int queue_idx;
682 VkDeviceQueueCreateFlags flags;
683
684 uint32_t scratch_size;
685 uint32_t compute_scratch_size;
686 uint32_t esgs_ring_size;
687 uint32_t gsvs_ring_size;
688 bool has_tess_rings;
689 bool has_sample_positions;
690
691 struct radeon_winsys_bo *scratch_bo;
692 struct radeon_winsys_bo *descriptor_bo;
693 struct radeon_winsys_bo *compute_scratch_bo;
694 struct radeon_winsys_bo *esgs_ring_bo;
695 struct radeon_winsys_bo *gsvs_ring_bo;
696 struct radeon_winsys_bo *tess_rings_bo;
697 struct radeon_cmdbuf *initial_preamble_cs;
698 struct radeon_cmdbuf *initial_full_flush_preamble_cs;
699 struct radeon_cmdbuf *continue_preamble_cs;
700 };
701
702 struct radv_bo_list {
703 struct radv_winsys_bo_list list;
704 unsigned capacity;
705 pthread_mutex_t mutex;
706 };
707
708 struct radv_device {
709 VK_LOADER_DATA _loader_data;
710
711 VkAllocationCallbacks alloc;
712
713 struct radv_instance * instance;
714 struct radeon_winsys *ws;
715
716 struct radv_meta_state meta_state;
717
718 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
719 int queue_count[RADV_MAX_QUEUE_FAMILIES];
720 struct radeon_cmdbuf *empty_cs[RADV_MAX_QUEUE_FAMILIES];
721
722 bool always_use_syncobj;
723 bool has_distributed_tess;
724 bool pbb_allowed;
725 bool dfsm_allowed;
726 uint32_t tess_offchip_block_dw_size;
727 uint32_t scratch_waves;
728 uint32_t dispatch_initiator;
729
730 uint32_t gs_table_depth;
731
732 /* MSAA sample locations.
733 * The first index is the sample index.
734 * The second index is the coordinate: X, Y. */
735 float sample_locations_1x[1][2];
736 float sample_locations_2x[2][2];
737 float sample_locations_4x[4][2];
738 float sample_locations_8x[8][2];
739
740 /* GFX7 and later */
741 uint32_t gfx_init_size_dw;
742 struct radeon_winsys_bo *gfx_init;
743
744 struct radeon_winsys_bo *trace_bo;
745 uint32_t *trace_id_ptr;
746
747 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
748 bool keep_shader_info;
749
750 struct radv_physical_device *physical_device;
751
752 /* Backup in-memory cache to be used if the app doesn't provide one */
753 struct radv_pipeline_cache * mem_cache;
754
755 /*
756 * use different counters so MSAA MRTs get consecutive surface indices,
757 * even if MASK is allocated in between.
758 */
759 uint32_t image_mrt_offset_counter;
760 uint32_t fmask_mrt_offset_counter;
761 struct list_head shader_slabs;
762 mtx_t shader_slab_mutex;
763
764 /* For detecting VM faults reported by dmesg. */
765 uint64_t dmesg_timestamp;
766
767 struct radv_device_extension_table enabled_extensions;
768
769 /* Whether the driver uses a global BO list. */
770 bool use_global_bo_list;
771
772 struct radv_bo_list bo_list;
773
774 /* Whether anisotropy is forced with RADV_TEX_ANISO (-1 is disabled). */
775 int force_aniso;
776 };
777
778 struct radv_device_memory {
779 struct radeon_winsys_bo *bo;
780 /* for dedicated allocations */
781 struct radv_image *image;
782 struct radv_buffer *buffer;
783 uint32_t type_index;
784 VkDeviceSize map_size;
785 void * map;
786 void * user_ptr;
787 };
788
789
790 struct radv_descriptor_range {
791 uint64_t va;
792 uint32_t size;
793 };
794
795 struct radv_descriptor_set {
796 const struct radv_descriptor_set_layout *layout;
797 uint32_t size;
798
799 struct radeon_winsys_bo *bo;
800 uint64_t va;
801 uint32_t *mapped_ptr;
802 struct radv_descriptor_range *dynamic_descriptors;
803
804 struct radeon_winsys_bo *descriptors[0];
805 };
806
807 struct radv_push_descriptor_set
808 {
809 struct radv_descriptor_set set;
810 uint32_t capacity;
811 };
812
813 struct radv_descriptor_pool_entry {
814 uint32_t offset;
815 uint32_t size;
816 struct radv_descriptor_set *set;
817 };
818
819 struct radv_descriptor_pool {
820 struct radeon_winsys_bo *bo;
821 uint8_t *mapped_ptr;
822 uint64_t current_offset;
823 uint64_t size;
824
825 uint8_t *host_memory_base;
826 uint8_t *host_memory_ptr;
827 uint8_t *host_memory_end;
828
829 uint32_t entry_count;
830 uint32_t max_entry_count;
831 struct radv_descriptor_pool_entry entries[0];
832 };
833
834 struct radv_descriptor_update_template_entry {
835 VkDescriptorType descriptor_type;
836
837 /* The number of descriptors to update */
838 uint32_t descriptor_count;
839
840 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
841 uint32_t dst_offset;
842
843 /* In dwords. Not valid/used for dynamic descriptors */
844 uint32_t dst_stride;
845
846 uint32_t buffer_offset;
847
848 /* Only valid for combined image samplers and samplers */
849 uint8_t has_sampler;
850 uint8_t sampler_offset;
851
852 /* In bytes */
853 size_t src_offset;
854 size_t src_stride;
855
856 /* For push descriptors */
857 const uint32_t *immutable_samplers;
858 };
859
860 struct radv_descriptor_update_template {
861 uint32_t entry_count;
862 VkPipelineBindPoint bind_point;
863 struct radv_descriptor_update_template_entry entry[0];
864 };
865
866 struct radv_buffer {
867 VkDeviceSize size;
868
869 VkBufferUsageFlags usage;
870 VkBufferCreateFlags flags;
871
872 /* Set when bound */
873 struct radeon_winsys_bo * bo;
874 VkDeviceSize offset;
875
876 bool shareable;
877 };
878
879 enum radv_dynamic_state_bits {
880 RADV_DYNAMIC_VIEWPORT = 1 << 0,
881 RADV_DYNAMIC_SCISSOR = 1 << 1,
882 RADV_DYNAMIC_LINE_WIDTH = 1 << 2,
883 RADV_DYNAMIC_DEPTH_BIAS = 1 << 3,
884 RADV_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
885 RADV_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
886 RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
887 RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
888 RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
889 RADV_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
890 RADV_DYNAMIC_SAMPLE_LOCATIONS = 1 << 10,
891 RADV_DYNAMIC_ALL = (1 << 11) - 1,
892 };
893
894 enum radv_cmd_dirty_bits {
895 /* Keep the dynamic state dirty bits in sync with
896 * enum radv_dynamic_state_bits */
897 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0,
898 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1,
899 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2,
900 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3,
901 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
902 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
903 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
904 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
905 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
906 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
907 RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS = 1 << 10,
908 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 11) - 1,
909 RADV_CMD_DIRTY_PIPELINE = 1 << 11,
910 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 12,
911 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 13,
912 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 14,
913 RADV_CMD_DIRTY_STREAMOUT_BUFFER = 1 << 15,
914 };
915
916 enum radv_cmd_flush_bits {
917 /* Instruction cache. */
918 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
919 /* Scalar L1 cache. */
920 RADV_CMD_FLAG_INV_SCACHE = 1 << 1,
921 /* Vector L1 cache. */
922 RADV_CMD_FLAG_INV_VCACHE = 1 << 2,
923 /* L2 cache + L2 metadata cache writeback & invalidate.
924 * GFX6-8: Used by shaders only. GFX9-10: Used by everything. */
925 RADV_CMD_FLAG_INV_L2 = 1 << 3,
926 /* L2 writeback (write dirty L2 lines to memory for non-L2 clients).
927 * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8.
928 * GFX6-7 will do complete invalidation, because the writeback is unsupported. */
929 RADV_CMD_FLAG_WB_L2 = 1 << 4,
930 /* Framebuffer caches */
931 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
932 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
933 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
934 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
935 /* Engine synchronization. */
936 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
937 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
938 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
939 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
940 /* Pipeline query controls. */
941 RADV_CMD_FLAG_START_PIPELINE_STATS = 1 << 13,
942 RADV_CMD_FLAG_STOP_PIPELINE_STATS = 1 << 14,
943 RADV_CMD_FLAG_VGT_STREAMOUT_SYNC = 1 << 15,
944
945 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
946 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
947 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
948 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
949 };
950
951 struct radv_vertex_binding {
952 struct radv_buffer * buffer;
953 VkDeviceSize offset;
954 };
955
956 struct radv_streamout_binding {
957 struct radv_buffer *buffer;
958 VkDeviceSize offset;
959 VkDeviceSize size;
960 };
961
962 struct radv_streamout_state {
963 /* Mask of bound streamout buffers. */
964 uint8_t enabled_mask;
965
966 /* External state that comes from the last vertex stage, it must be
967 * set explicitely when binding a new graphics pipeline.
968 */
969 uint16_t stride_in_dw[MAX_SO_BUFFERS];
970 uint32_t enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
971
972 /* State of VGT_STRMOUT_BUFFER_(CONFIG|END) */
973 uint32_t hw_enabled_mask;
974
975 /* State of VGT_STRMOUT_(CONFIG|EN) */
976 bool streamout_enabled;
977 };
978
979 struct radv_viewport_state {
980 uint32_t count;
981 VkViewport viewports[MAX_VIEWPORTS];
982 };
983
984 struct radv_scissor_state {
985 uint32_t count;
986 VkRect2D scissors[MAX_SCISSORS];
987 };
988
989 struct radv_discard_rectangle_state {
990 uint32_t count;
991 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
992 };
993
994 struct radv_sample_locations_state {
995 VkSampleCountFlagBits per_pixel;
996 VkExtent2D grid_size;
997 uint32_t count;
998 VkSampleLocationEXT locations[MAX_SAMPLE_LOCATIONS];
999 };
1000
1001 struct radv_dynamic_state {
1002 /**
1003 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
1004 * Defines the set of saved dynamic state.
1005 */
1006 uint32_t mask;
1007
1008 struct radv_viewport_state viewport;
1009
1010 struct radv_scissor_state scissor;
1011
1012 float line_width;
1013
1014 struct {
1015 float bias;
1016 float clamp;
1017 float slope;
1018 } depth_bias;
1019
1020 float blend_constants[4];
1021
1022 struct {
1023 float min;
1024 float max;
1025 } depth_bounds;
1026
1027 struct {
1028 uint32_t front;
1029 uint32_t back;
1030 } stencil_compare_mask;
1031
1032 struct {
1033 uint32_t front;
1034 uint32_t back;
1035 } stencil_write_mask;
1036
1037 struct {
1038 uint32_t front;
1039 uint32_t back;
1040 } stencil_reference;
1041
1042 struct radv_discard_rectangle_state discard_rectangle;
1043
1044 struct radv_sample_locations_state sample_location;
1045 };
1046
1047 extern const struct radv_dynamic_state default_dynamic_state;
1048
1049 const char *
1050 radv_get_debug_option_name(int id);
1051
1052 const char *
1053 radv_get_perftest_option_name(int id);
1054
1055 /**
1056 * Attachment state when recording a renderpass instance.
1057 *
1058 * The clear value is valid only if there exists a pending clear.
1059 */
1060 struct radv_attachment_state {
1061 VkImageAspectFlags pending_clear_aspects;
1062 uint32_t cleared_views;
1063 VkClearValue clear_value;
1064 VkImageLayout current_layout;
1065 struct radv_sample_locations_state sample_location;
1066 };
1067
1068 struct radv_descriptor_state {
1069 struct radv_descriptor_set *sets[MAX_SETS];
1070 uint32_t dirty;
1071 uint32_t valid;
1072 struct radv_push_descriptor_set push_set;
1073 bool push_dirty;
1074 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
1075 };
1076
1077 struct radv_subpass_sample_locs_state {
1078 uint32_t subpass_idx;
1079 struct radv_sample_locations_state sample_location;
1080 };
1081
1082 struct radv_cmd_state {
1083 /* Vertex descriptors */
1084 uint64_t vb_va;
1085 unsigned vb_size;
1086
1087 bool predicating;
1088 uint32_t dirty;
1089
1090 uint32_t prefetch_L2_mask;
1091
1092 struct radv_pipeline * pipeline;
1093 struct radv_pipeline * emitted_pipeline;
1094 struct radv_pipeline * compute_pipeline;
1095 struct radv_pipeline * emitted_compute_pipeline;
1096 struct radv_framebuffer * framebuffer;
1097 struct radv_render_pass * pass;
1098 const struct radv_subpass * subpass;
1099 struct radv_dynamic_state dynamic;
1100 struct radv_attachment_state * attachments;
1101 struct radv_streamout_state streamout;
1102 VkRect2D render_area;
1103
1104 uint32_t num_subpass_sample_locs;
1105 struct radv_subpass_sample_locs_state * subpass_sample_locs;
1106
1107 /* Index buffer */
1108 struct radv_buffer *index_buffer;
1109 uint64_t index_offset;
1110 uint32_t index_type;
1111 uint32_t max_index_count;
1112 uint64_t index_va;
1113 int32_t last_index_type;
1114
1115 int32_t last_primitive_reset_en;
1116 uint32_t last_primitive_reset_index;
1117 enum radv_cmd_flush_bits flush_bits;
1118 unsigned active_occlusion_queries;
1119 bool perfect_occlusion_queries_enabled;
1120 unsigned active_pipeline_queries;
1121 float offset_scale;
1122 uint32_t trace_id;
1123 uint32_t last_ia_multi_vgt_param;
1124
1125 uint32_t last_num_instances;
1126 uint32_t last_first_instance;
1127 uint32_t last_vertex_offset;
1128
1129 /* Whether CP DMA is busy/idle. */
1130 bool dma_is_busy;
1131
1132 /* Conditional rendering info. */
1133 int predication_type; /* -1: disabled, 0: normal, 1: inverted */
1134 uint64_t predication_va;
1135
1136 bool context_roll_without_scissor_emitted;
1137 };
1138
1139 struct radv_cmd_pool {
1140 VkAllocationCallbacks alloc;
1141 struct list_head cmd_buffers;
1142 struct list_head free_cmd_buffers;
1143 uint32_t queue_family_index;
1144 };
1145
1146 struct radv_cmd_buffer_upload {
1147 uint8_t *map;
1148 unsigned offset;
1149 uint64_t size;
1150 struct radeon_winsys_bo *upload_bo;
1151 struct list_head list;
1152 };
1153
1154 enum radv_cmd_buffer_status {
1155 RADV_CMD_BUFFER_STATUS_INVALID,
1156 RADV_CMD_BUFFER_STATUS_INITIAL,
1157 RADV_CMD_BUFFER_STATUS_RECORDING,
1158 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
1159 RADV_CMD_BUFFER_STATUS_PENDING,
1160 };
1161
1162 struct radv_cmd_buffer {
1163 VK_LOADER_DATA _loader_data;
1164
1165 struct radv_device * device;
1166
1167 struct radv_cmd_pool * pool;
1168 struct list_head pool_link;
1169
1170 VkCommandBufferUsageFlags usage_flags;
1171 VkCommandBufferLevel level;
1172 enum radv_cmd_buffer_status status;
1173 struct radeon_cmdbuf *cs;
1174 struct radv_cmd_state state;
1175 struct radv_vertex_binding vertex_bindings[MAX_VBS];
1176 struct radv_streamout_binding streamout_bindings[MAX_SO_BUFFERS];
1177 uint32_t queue_family_index;
1178
1179 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
1180 VkShaderStageFlags push_constant_stages;
1181 struct radv_descriptor_set meta_push_descriptors;
1182
1183 struct radv_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
1184
1185 struct radv_cmd_buffer_upload upload;
1186
1187 uint32_t scratch_size_needed;
1188 uint32_t compute_scratch_size_needed;
1189 uint32_t esgs_ring_size_needed;
1190 uint32_t gsvs_ring_size_needed;
1191 bool tess_rings_needed;
1192 bool sample_positions_needed;
1193
1194 VkResult record_result;
1195
1196 uint64_t gfx9_fence_va;
1197 uint32_t gfx9_fence_idx;
1198 uint64_t gfx9_eop_bug_va;
1199
1200 /**
1201 * Whether a query pool has been resetted and we have to flush caches.
1202 */
1203 bool pending_reset_query;
1204
1205 /**
1206 * Bitmask of pending active query flushes.
1207 */
1208 enum radv_cmd_flush_bits active_query_flush_bits;
1209 };
1210
1211 struct radv_image;
1212 struct radv_image_view;
1213
1214 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
1215
1216 void si_emit_graphics(struct radv_physical_device *physical_device,
1217 struct radeon_cmdbuf *cs);
1218 void si_emit_compute(struct radv_physical_device *physical_device,
1219 struct radeon_cmdbuf *cs);
1220
1221 void cik_create_gfx_config(struct radv_device *device);
1222
1223 void si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
1224 int count, const VkViewport *viewports);
1225 void si_write_scissors(struct radeon_cmdbuf *cs, int first,
1226 int count, const VkRect2D *scissors,
1227 const VkViewport *viewports, bool can_use_guardband);
1228 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
1229 bool instanced_draw, bool indirect_draw,
1230 bool count_from_stream_output,
1231 uint32_t draw_vertex_count);
1232 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
1233 enum chip_class chip_class,
1234 bool is_mec,
1235 unsigned event, unsigned event_flags,
1236 unsigned data_sel,
1237 uint64_t va,
1238 uint32_t new_fence,
1239 uint64_t gfx9_eop_bug_va);
1240
1241 void radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va,
1242 uint32_t ref, uint32_t mask);
1243 void si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
1244 enum chip_class chip_class,
1245 uint32_t *fence_ptr, uint64_t va,
1246 bool is_mec,
1247 enum radv_cmd_flush_bits flush_bits,
1248 uint64_t gfx9_eop_bug_va);
1249 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
1250 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
1251 bool inverted, uint64_t va);
1252 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1253 uint64_t src_va, uint64_t dest_va,
1254 uint64_t size);
1255 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1256 unsigned size);
1257 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1258 uint64_t size, unsigned value);
1259 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer);
1260
1261 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1262 bool
1263 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1264 unsigned size,
1265 unsigned alignment,
1266 unsigned *out_offset,
1267 void **ptr);
1268 void
1269 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1270 const struct radv_subpass *subpass);
1271 bool
1272 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1273 unsigned size, unsigned alignmnet,
1274 const void *data, unsigned *out_offset);
1275
1276 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1277 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1278 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1279 void radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer,
1280 VkImageAspectFlags aspects,
1281 VkResolveModeFlagBitsKHR resolve_mode);
1282 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1283 void radv_depth_stencil_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer,
1284 VkImageAspectFlags aspects,
1285 VkResolveModeFlagBitsKHR resolve_mode);
1286 void radv_emit_default_sample_locations(struct radeon_cmdbuf *cs, int nr_samples);
1287 unsigned radv_get_default_max_sample_dist(int log_samples);
1288 void radv_device_init_msaa(struct radv_device *device);
1289
1290 void radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1291 struct radv_image *image,
1292 VkClearDepthStencilValue ds_clear_value,
1293 VkImageAspectFlags aspects);
1294
1295 void radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1296 const struct radv_image_view *iview,
1297 int cb_idx,
1298 uint32_t color_values[2]);
1299
1300 void radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1301 struct radv_image *image,
1302 const VkImageSubresourceRange *range, bool value);
1303
1304 void radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1305 struct radv_image *image,
1306 const VkImageSubresourceRange *range, bool value);
1307
1308 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1309 struct radeon_winsys_bo *bo,
1310 uint64_t offset, uint64_t size, uint32_t value);
1311 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1312 bool radv_get_memory_fd(struct radv_device *device,
1313 struct radv_device_memory *memory,
1314 int *pFD);
1315
1316 static inline void
1317 radv_emit_shader_pointer_head(struct radeon_cmdbuf *cs,
1318 unsigned sh_offset, unsigned pointer_count,
1319 bool use_32bit_pointers)
1320 {
1321 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, pointer_count * (use_32bit_pointers ? 1 : 2), 0));
1322 radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2);
1323 }
1324
1325 static inline void
1326 radv_emit_shader_pointer_body(struct radv_device *device,
1327 struct radeon_cmdbuf *cs,
1328 uint64_t va, bool use_32bit_pointers)
1329 {
1330 radeon_emit(cs, va);
1331
1332 if (use_32bit_pointers) {
1333 assert(va == 0 ||
1334 (va >> 32) == device->physical_device->rad_info.address32_hi);
1335 } else {
1336 radeon_emit(cs, va >> 32);
1337 }
1338 }
1339
1340 static inline void
1341 radv_emit_shader_pointer(struct radv_device *device,
1342 struct radeon_cmdbuf *cs,
1343 uint32_t sh_offset, uint64_t va, bool global)
1344 {
1345 bool use_32bit_pointers = !global;
1346
1347 radv_emit_shader_pointer_head(cs, sh_offset, 1, use_32bit_pointers);
1348 radv_emit_shader_pointer_body(device, cs, va, use_32bit_pointers);
1349 }
1350
1351 static inline struct radv_descriptor_state *
1352 radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
1353 VkPipelineBindPoint bind_point)
1354 {
1355 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS ||
1356 bind_point == VK_PIPELINE_BIND_POINT_COMPUTE);
1357 return &cmd_buffer->descriptors[bind_point];
1358 }
1359
1360 /*
1361 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1362 *
1363 * Limitations: Can't call normal dispatch functions without binding or rebinding
1364 * the compute pipeline.
1365 */
1366 void radv_unaligned_dispatch(
1367 struct radv_cmd_buffer *cmd_buffer,
1368 uint32_t x,
1369 uint32_t y,
1370 uint32_t z);
1371
1372 struct radv_event {
1373 struct radeon_winsys_bo *bo;
1374 uint64_t *map;
1375 };
1376
1377 struct radv_shader_module;
1378
1379 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1380 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1381 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1382 void
1383 radv_hash_shaders(unsigned char *hash,
1384 const VkPipelineShaderStageCreateInfo **stages,
1385 const struct radv_pipeline_layout *layout,
1386 const struct radv_pipeline_key *key,
1387 uint32_t flags);
1388
1389 static inline gl_shader_stage
1390 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1391 {
1392 assert(__builtin_popcount(vk_stage) == 1);
1393 return ffs(vk_stage) - 1;
1394 }
1395
1396 static inline VkShaderStageFlagBits
1397 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1398 {
1399 return (1 << mesa_stage);
1400 }
1401
1402 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1403
1404 #define radv_foreach_stage(stage, stage_bits) \
1405 for (gl_shader_stage stage, \
1406 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1407 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1408 __tmp &= ~(1 << (stage)))
1409
1410 extern const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS];
1411 unsigned radv_format_meta_fs_key(VkFormat format);
1412
1413 struct radv_multisample_state {
1414 uint32_t db_eqaa;
1415 uint32_t pa_sc_line_cntl;
1416 uint32_t pa_sc_mode_cntl_0;
1417 uint32_t pa_sc_mode_cntl_1;
1418 uint32_t pa_sc_aa_config;
1419 uint32_t pa_sc_aa_mask[2];
1420 unsigned num_samples;
1421 };
1422
1423 struct radv_prim_vertex_count {
1424 uint8_t min;
1425 uint8_t incr;
1426 };
1427
1428 struct radv_vertex_elements_info {
1429 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1430 };
1431
1432 struct radv_ia_multi_vgt_param_helpers {
1433 uint32_t base;
1434 bool partial_es_wave;
1435 uint8_t primgroup_size;
1436 bool wd_switch_on_eop;
1437 bool ia_switch_on_eoi;
1438 bool partial_vs_wave;
1439 };
1440
1441 #define SI_GS_PER_ES 128
1442
1443 struct radv_pipeline {
1444 struct radv_device * device;
1445 struct radv_dynamic_state dynamic_state;
1446
1447 struct radv_pipeline_layout * layout;
1448
1449 bool need_indirect_descriptor_sets;
1450 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1451 struct radv_shader_variant *gs_copy_shader;
1452 VkShaderStageFlags active_stages;
1453
1454 struct radeon_cmdbuf cs;
1455 uint32_t ctx_cs_hash;
1456 struct radeon_cmdbuf ctx_cs;
1457
1458 struct radv_vertex_elements_info vertex_elements;
1459
1460 uint32_t binding_stride[MAX_VBS];
1461 uint8_t num_vertex_bindings;
1462
1463 uint32_t user_data_0[MESA_SHADER_STAGES];
1464 union {
1465 struct {
1466 struct radv_multisample_state ms;
1467 uint32_t spi_baryc_cntl;
1468 bool prim_restart_enable;
1469 unsigned esgs_ring_size;
1470 unsigned gsvs_ring_size;
1471 uint32_t vtx_base_sgpr;
1472 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
1473 uint8_t vtx_emit_num;
1474 struct radv_prim_vertex_count prim_vertex_count;
1475 bool can_use_guardband;
1476 uint32_t needed_dynamic_state;
1477 bool disable_out_of_order_rast_for_occlusion;
1478
1479 /* Used for rbplus */
1480 uint32_t col_format;
1481 uint32_t cb_target_mask;
1482 } graphics;
1483 };
1484
1485 unsigned max_waves;
1486 unsigned scratch_bytes_per_wave;
1487
1488 /* Not NULL if graphics pipeline uses streamout. */
1489 struct radv_shader_variant *streamout_shader;
1490 };
1491
1492 static inline bool radv_pipeline_has_gs(const struct radv_pipeline *pipeline)
1493 {
1494 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1495 }
1496
1497 static inline bool radv_pipeline_has_tess(const struct radv_pipeline *pipeline)
1498 {
1499 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1500 }
1501
1502 struct radv_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1503 gl_shader_stage stage,
1504 int idx);
1505
1506 struct radv_shader_variant *radv_get_shader(struct radv_pipeline *pipeline,
1507 gl_shader_stage stage);
1508
1509 struct radv_graphics_pipeline_create_info {
1510 bool use_rectlist;
1511 bool db_depth_clear;
1512 bool db_stencil_clear;
1513 bool db_depth_disable_expclear;
1514 bool db_stencil_disable_expclear;
1515 bool db_flush_depth_inplace;
1516 bool db_flush_stencil_inplace;
1517 bool db_resummarize;
1518 uint32_t custom_blend_mode;
1519 };
1520
1521 VkResult
1522 radv_graphics_pipeline_create(VkDevice device,
1523 VkPipelineCache cache,
1524 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1525 const struct radv_graphics_pipeline_create_info *extra,
1526 const VkAllocationCallbacks *alloc,
1527 VkPipeline *pPipeline);
1528
1529 struct vk_format_description;
1530 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1531 int first_non_void);
1532 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1533 int first_non_void);
1534 bool radv_is_buffer_format_supported(VkFormat format, bool *scaled);
1535 uint32_t radv_translate_colorformat(VkFormat format);
1536 uint32_t radv_translate_color_numformat(VkFormat format,
1537 const struct vk_format_description *desc,
1538 int first_non_void);
1539 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1540 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1541 uint32_t radv_translate_dbformat(VkFormat format);
1542 uint32_t radv_translate_tex_dataformat(VkFormat format,
1543 const struct vk_format_description *desc,
1544 int first_non_void);
1545 uint32_t radv_translate_tex_numformat(VkFormat format,
1546 const struct vk_format_description *desc,
1547 int first_non_void);
1548 bool radv_format_pack_clear_color(VkFormat format,
1549 uint32_t clear_vals[2],
1550 VkClearColorValue *value);
1551 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1552 bool radv_dcc_formats_compatible(VkFormat format1,
1553 VkFormat format2);
1554 bool radv_device_supports_etc(struct radv_physical_device *physical_device);
1555
1556 struct radv_fmask_info {
1557 uint64_t offset;
1558 uint64_t size;
1559 unsigned alignment;
1560 unsigned pitch_in_pixels;
1561 unsigned bank_height;
1562 unsigned slice_tile_max;
1563 unsigned tile_mode_index;
1564 unsigned tile_swizzle;
1565 uint64_t slice_size;
1566 };
1567
1568 struct radv_cmask_info {
1569 uint64_t offset;
1570 uint64_t size;
1571 unsigned alignment;
1572 unsigned slice_tile_max;
1573 unsigned slice_size;
1574 };
1575
1576
1577 struct radv_image_plane {
1578 VkFormat format;
1579 struct radeon_surf surface;
1580 uint64_t offset;
1581 };
1582
1583 struct radv_image {
1584 VkImageType type;
1585 /* The original VkFormat provided by the client. This may not match any
1586 * of the actual surface formats.
1587 */
1588 VkFormat vk_format;
1589 VkImageAspectFlags aspects;
1590 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1591 struct ac_surf_info info;
1592 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1593 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1594
1595 VkDeviceSize size;
1596 uint32_t alignment;
1597
1598 unsigned queue_family_mask;
1599 bool exclusive;
1600 bool shareable;
1601
1602 /* Set when bound */
1603 struct radeon_winsys_bo *bo;
1604 VkDeviceSize offset;
1605 uint64_t dcc_offset;
1606 uint64_t htile_offset;
1607 bool tc_compatible_htile;
1608 bool tc_compatible_cmask;
1609
1610 struct radv_fmask_info fmask;
1611 struct radv_cmask_info cmask;
1612 uint64_t clear_value_offset;
1613 uint64_t fce_pred_offset;
1614 uint64_t dcc_pred_offset;
1615
1616 /*
1617 * Metadata for the TC-compat zrange workaround. If the 32-bit value
1618 * stored at this offset is UINT_MAX, the driver will emit
1619 * DB_Z_INFO.ZRANGE_PRECISION=0, otherwise it will skip the
1620 * SET_CONTEXT_REG packet.
1621 */
1622 uint64_t tc_compat_zrange_offset;
1623
1624 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1625 VkDeviceMemory owned_memory;
1626
1627 unsigned plane_count;
1628 struct radv_image_plane planes[0];
1629 };
1630
1631 /* Whether the image has a htile that is known consistent with the contents of
1632 * the image. */
1633 bool radv_layout_has_htile(const struct radv_image *image,
1634 VkImageLayout layout,
1635 unsigned queue_mask);
1636
1637 /* Whether the image has a htile that is known consistent with the contents of
1638 * the image and is allowed to be in compressed form.
1639 *
1640 * If this is false reads that don't use the htile should be able to return
1641 * correct results.
1642 */
1643 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1644 VkImageLayout layout,
1645 unsigned queue_mask);
1646
1647 bool radv_layout_can_fast_clear(const struct radv_image *image,
1648 VkImageLayout layout,
1649 unsigned queue_mask);
1650
1651 bool radv_layout_dcc_compressed(const struct radv_image *image,
1652 VkImageLayout layout,
1653 unsigned queue_mask);
1654
1655 /**
1656 * Return whether the image has CMASK metadata for color surfaces.
1657 */
1658 static inline bool
1659 radv_image_has_cmask(const struct radv_image *image)
1660 {
1661 return image->cmask.size;
1662 }
1663
1664 /**
1665 * Return whether the image has FMASK metadata for color surfaces.
1666 */
1667 static inline bool
1668 radv_image_has_fmask(const struct radv_image *image)
1669 {
1670 return image->fmask.size;
1671 }
1672
1673 /**
1674 * Return whether the image has DCC metadata for color surfaces.
1675 */
1676 static inline bool
1677 radv_image_has_dcc(const struct radv_image *image)
1678 {
1679 return image->planes[0].surface.dcc_size;
1680 }
1681
1682 /**
1683 * Return whether the image is TC-compatible CMASK.
1684 */
1685 static inline bool
1686 radv_image_is_tc_compat_cmask(const struct radv_image *image)
1687 {
1688 return radv_image_has_fmask(image) && image->tc_compatible_cmask;
1689 }
1690
1691 /**
1692 * Return whether DCC metadata is enabled for a level.
1693 */
1694 static inline bool
1695 radv_dcc_enabled(const struct radv_image *image, unsigned level)
1696 {
1697 return radv_image_has_dcc(image) &&
1698 level < image->planes[0].surface.num_dcc_levels;
1699 }
1700
1701 /**
1702 * Return whether the image has CB metadata.
1703 */
1704 static inline bool
1705 radv_image_has_CB_metadata(const struct radv_image *image)
1706 {
1707 return radv_image_has_cmask(image) ||
1708 radv_image_has_fmask(image) ||
1709 radv_image_has_dcc(image);
1710 }
1711
1712 /**
1713 * Return whether the image has HTILE metadata for depth surfaces.
1714 */
1715 static inline bool
1716 radv_image_has_htile(const struct radv_image *image)
1717 {
1718 return image->planes[0].surface.htile_size;
1719 }
1720
1721 /**
1722 * Return whether HTILE metadata is enabled for a level.
1723 */
1724 static inline bool
1725 radv_htile_enabled(const struct radv_image *image, unsigned level)
1726 {
1727 return radv_image_has_htile(image) && level == 0;
1728 }
1729
1730 /**
1731 * Return whether the image is TC-compatible HTILE.
1732 */
1733 static inline bool
1734 radv_image_is_tc_compat_htile(const struct radv_image *image)
1735 {
1736 return radv_image_has_htile(image) && image->tc_compatible_htile;
1737 }
1738
1739 static inline uint64_t
1740 radv_image_get_fast_clear_va(const struct radv_image *image,
1741 uint32_t base_level)
1742 {
1743 uint64_t va = radv_buffer_get_va(image->bo);
1744 va += image->offset + image->clear_value_offset + base_level * 8;
1745 return va;
1746 }
1747
1748 static inline uint64_t
1749 radv_image_get_fce_pred_va(const struct radv_image *image,
1750 uint32_t base_level)
1751 {
1752 uint64_t va = radv_buffer_get_va(image->bo);
1753 va += image->offset + image->fce_pred_offset + base_level * 8;
1754 return va;
1755 }
1756
1757 static inline uint64_t
1758 radv_image_get_dcc_pred_va(const struct radv_image *image,
1759 uint32_t base_level)
1760 {
1761 uint64_t va = radv_buffer_get_va(image->bo);
1762 va += image->offset + image->dcc_pred_offset + base_level * 8;
1763 return va;
1764 }
1765
1766 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1767
1768 static inline uint32_t
1769 radv_get_layerCount(const struct radv_image *image,
1770 const VkImageSubresourceRange *range)
1771 {
1772 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1773 image->info.array_size - range->baseArrayLayer : range->layerCount;
1774 }
1775
1776 static inline uint32_t
1777 radv_get_levelCount(const struct radv_image *image,
1778 const VkImageSubresourceRange *range)
1779 {
1780 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1781 image->info.levels - range->baseMipLevel : range->levelCount;
1782 }
1783
1784 struct radeon_bo_metadata;
1785 void
1786 radv_init_metadata(struct radv_device *device,
1787 struct radv_image *image,
1788 struct radeon_bo_metadata *metadata);
1789
1790 void
1791 radv_image_override_offset_stride(struct radv_device *device,
1792 struct radv_image *image,
1793 uint64_t offset, uint32_t stride);
1794
1795 union radv_descriptor {
1796 struct {
1797 uint32_t plane0_descriptor[8];
1798 uint32_t fmask_descriptor[8];
1799 };
1800 struct {
1801 uint32_t plane_descriptors[3][8];
1802 };
1803 };
1804
1805 struct radv_image_view {
1806 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1807 struct radeon_winsys_bo *bo;
1808
1809 VkImageViewType type;
1810 VkImageAspectFlags aspect_mask;
1811 VkFormat vk_format;
1812 unsigned plane_id;
1813 bool multiple_planes;
1814 uint32_t base_layer;
1815 uint32_t layer_count;
1816 uint32_t base_mip;
1817 uint32_t level_count;
1818 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1819
1820 union radv_descriptor descriptor;
1821
1822 /* Descriptor for use as a storage image as opposed to a sampled image.
1823 * This has a few differences for cube maps (e.g. type).
1824 */
1825 union radv_descriptor storage_descriptor;
1826 };
1827
1828 struct radv_image_create_info {
1829 const VkImageCreateInfo *vk_info;
1830 bool scanout;
1831 bool no_metadata_planes;
1832 const struct radeon_bo_metadata *bo_metadata;
1833 };
1834
1835 VkResult radv_image_create(VkDevice _device,
1836 const struct radv_image_create_info *info,
1837 const VkAllocationCallbacks* alloc,
1838 VkImage *pImage);
1839
1840 VkResult
1841 radv_image_from_gralloc(VkDevice device_h,
1842 const VkImageCreateInfo *base_info,
1843 const VkNativeBufferANDROID *gralloc_info,
1844 const VkAllocationCallbacks *alloc,
1845 VkImage *out_image_h);
1846
1847 void radv_image_view_init(struct radv_image_view *view,
1848 struct radv_device *device,
1849 const VkImageViewCreateInfo* pCreateInfo);
1850
1851 VkFormat radv_get_aspect_format(struct radv_image *image, VkImageAspectFlags mask);
1852
1853 struct radv_sampler_ycbcr_conversion {
1854 VkFormat format;
1855 VkSamplerYcbcrModelConversion ycbcr_model;
1856 VkSamplerYcbcrRange ycbcr_range;
1857 VkComponentMapping components;
1858 VkChromaLocation chroma_offsets[2];
1859 VkFilter chroma_filter;
1860 };
1861
1862 struct radv_buffer_view {
1863 struct radeon_winsys_bo *bo;
1864 VkFormat vk_format;
1865 uint64_t range; /**< VkBufferViewCreateInfo::range */
1866 uint32_t state[4];
1867 };
1868 void radv_buffer_view_init(struct radv_buffer_view *view,
1869 struct radv_device *device,
1870 const VkBufferViewCreateInfo* pCreateInfo);
1871
1872 static inline struct VkExtent3D
1873 radv_sanitize_image_extent(const VkImageType imageType,
1874 const struct VkExtent3D imageExtent)
1875 {
1876 switch (imageType) {
1877 case VK_IMAGE_TYPE_1D:
1878 return (VkExtent3D) { imageExtent.width, 1, 1 };
1879 case VK_IMAGE_TYPE_2D:
1880 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1881 case VK_IMAGE_TYPE_3D:
1882 return imageExtent;
1883 default:
1884 unreachable("invalid image type");
1885 }
1886 }
1887
1888 static inline struct VkOffset3D
1889 radv_sanitize_image_offset(const VkImageType imageType,
1890 const struct VkOffset3D imageOffset)
1891 {
1892 switch (imageType) {
1893 case VK_IMAGE_TYPE_1D:
1894 return (VkOffset3D) { imageOffset.x, 0, 0 };
1895 case VK_IMAGE_TYPE_2D:
1896 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1897 case VK_IMAGE_TYPE_3D:
1898 return imageOffset;
1899 default:
1900 unreachable("invalid image type");
1901 }
1902 }
1903
1904 static inline bool
1905 radv_image_extent_compare(const struct radv_image *image,
1906 const VkExtent3D *extent)
1907 {
1908 if (extent->width != image->info.width ||
1909 extent->height != image->info.height ||
1910 extent->depth != image->info.depth)
1911 return false;
1912 return true;
1913 }
1914
1915 struct radv_sampler {
1916 uint32_t state[4];
1917 struct radv_sampler_ycbcr_conversion *ycbcr_sampler;
1918 };
1919
1920 struct radv_color_buffer_info {
1921 uint64_t cb_color_base;
1922 uint64_t cb_color_cmask;
1923 uint64_t cb_color_fmask;
1924 uint64_t cb_dcc_base;
1925 uint32_t cb_color_slice;
1926 uint32_t cb_color_view;
1927 uint32_t cb_color_info;
1928 uint32_t cb_color_attrib;
1929 uint32_t cb_color_attrib2;
1930 uint32_t cb_dcc_control;
1931 uint32_t cb_color_cmask_slice;
1932 uint32_t cb_color_fmask_slice;
1933 union {
1934 uint32_t cb_color_pitch; // GFX6-GFX8
1935 uint32_t cb_mrt_epitch; // GFX9+
1936 };
1937 };
1938
1939 struct radv_ds_buffer_info {
1940 uint64_t db_z_read_base;
1941 uint64_t db_stencil_read_base;
1942 uint64_t db_z_write_base;
1943 uint64_t db_stencil_write_base;
1944 uint64_t db_htile_data_base;
1945 uint32_t db_depth_info;
1946 uint32_t db_z_info;
1947 uint32_t db_stencil_info;
1948 uint32_t db_depth_view;
1949 uint32_t db_depth_size;
1950 uint32_t db_depth_slice;
1951 uint32_t db_htile_surface;
1952 uint32_t pa_su_poly_offset_db_fmt_cntl;
1953 uint32_t db_z_info2;
1954 uint32_t db_stencil_info2;
1955 float offset_scale;
1956 };
1957
1958 struct radv_attachment_info {
1959 union {
1960 struct radv_color_buffer_info cb;
1961 struct radv_ds_buffer_info ds;
1962 };
1963 struct radv_image_view *attachment;
1964 };
1965
1966 struct radv_framebuffer {
1967 uint32_t width;
1968 uint32_t height;
1969 uint32_t layers;
1970
1971 uint32_t attachment_count;
1972 struct radv_attachment_info attachments[0];
1973 };
1974
1975 struct radv_subpass_barrier {
1976 VkPipelineStageFlags src_stage_mask;
1977 VkAccessFlags src_access_mask;
1978 VkAccessFlags dst_access_mask;
1979 };
1980
1981 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
1982 const struct radv_subpass_barrier *barrier);
1983
1984 struct radv_subpass_attachment {
1985 uint32_t attachment;
1986 VkImageLayout layout;
1987 };
1988
1989 struct radv_subpass {
1990 uint32_t attachment_count;
1991 struct radv_subpass_attachment * attachments;
1992
1993 uint32_t input_count;
1994 uint32_t color_count;
1995 struct radv_subpass_attachment * input_attachments;
1996 struct radv_subpass_attachment * color_attachments;
1997 struct radv_subpass_attachment * resolve_attachments;
1998 struct radv_subpass_attachment * depth_stencil_attachment;
1999 struct radv_subpass_attachment * ds_resolve_attachment;
2000 VkResolveModeFlagBitsKHR depth_resolve_mode;
2001 VkResolveModeFlagBitsKHR stencil_resolve_mode;
2002
2003 /** Subpass has at least one color resolve attachment */
2004 bool has_color_resolve;
2005
2006 /** Subpass has at least one color attachment */
2007 bool has_color_att;
2008
2009 struct radv_subpass_barrier start_barrier;
2010
2011 uint32_t view_mask;
2012 VkSampleCountFlagBits max_sample_count;
2013 };
2014
2015 uint32_t
2016 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer);
2017
2018 struct radv_render_pass_attachment {
2019 VkFormat format;
2020 uint32_t samples;
2021 VkAttachmentLoadOp load_op;
2022 VkAttachmentLoadOp stencil_load_op;
2023 VkImageLayout initial_layout;
2024 VkImageLayout final_layout;
2025
2026 /* The subpass id in which the attachment will be used first/last. */
2027 uint32_t first_subpass_idx;
2028 uint32_t last_subpass_idx;
2029 };
2030
2031 struct radv_render_pass {
2032 uint32_t attachment_count;
2033 uint32_t subpass_count;
2034 struct radv_subpass_attachment * subpass_attachments;
2035 struct radv_render_pass_attachment * attachments;
2036 struct radv_subpass_barrier end_barrier;
2037 struct radv_subpass subpasses[0];
2038 };
2039
2040 VkResult radv_device_init_meta(struct radv_device *device);
2041 void radv_device_finish_meta(struct radv_device *device);
2042
2043 struct radv_query_pool {
2044 struct radeon_winsys_bo *bo;
2045 uint32_t stride;
2046 uint32_t availability_offset;
2047 uint64_t size;
2048 char *ptr;
2049 VkQueryType type;
2050 uint32_t pipeline_stats_mask;
2051 };
2052
2053 struct radv_semaphore {
2054 /* use a winsys sem for non-exportable */
2055 struct radeon_winsys_sem *sem;
2056 uint32_t syncobj;
2057 uint32_t temp_syncobj;
2058 };
2059
2060 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2061 VkPipelineBindPoint bind_point,
2062 struct radv_descriptor_set *set,
2063 unsigned idx);
2064
2065 void
2066 radv_update_descriptor_sets(struct radv_device *device,
2067 struct radv_cmd_buffer *cmd_buffer,
2068 VkDescriptorSet overrideSet,
2069 uint32_t descriptorWriteCount,
2070 const VkWriteDescriptorSet *pDescriptorWrites,
2071 uint32_t descriptorCopyCount,
2072 const VkCopyDescriptorSet *pDescriptorCopies);
2073
2074 void
2075 radv_update_descriptor_set_with_template(struct radv_device *device,
2076 struct radv_cmd_buffer *cmd_buffer,
2077 struct radv_descriptor_set *set,
2078 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
2079 const void *pData);
2080
2081 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2082 VkPipelineBindPoint pipelineBindPoint,
2083 VkPipelineLayout _layout,
2084 uint32_t set,
2085 uint32_t descriptorWriteCount,
2086 const VkWriteDescriptorSet *pDescriptorWrites);
2087
2088 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
2089 struct radv_image *image,
2090 const VkImageSubresourceRange *range, uint32_t value);
2091
2092 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
2093 struct radv_image *image,
2094 const VkImageSubresourceRange *range);
2095
2096 struct radv_fence {
2097 struct radeon_winsys_fence *fence;
2098 struct wsi_fence *fence_wsi;
2099
2100 uint32_t syncobj;
2101 uint32_t temp_syncobj;
2102 };
2103
2104 /* radv_nir_to_llvm.c */
2105 struct radv_shader_variant_info;
2106 struct radv_nir_compiler_options;
2107
2108 void radv_compile_gs_copy_shader(struct ac_llvm_compiler *ac_llvm,
2109 struct nir_shader *geom_shader,
2110 struct radv_shader_binary **rbinary,
2111 struct radv_shader_variant_info *shader_info,
2112 const struct radv_nir_compiler_options *option);
2113
2114 void radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
2115 struct radv_shader_binary **rbinary,
2116 struct radv_shader_variant_info *shader_info,
2117 struct nir_shader *const *nir,
2118 int nir_count,
2119 const struct radv_nir_compiler_options *options);
2120
2121 unsigned radv_nir_get_max_workgroup_size(enum chip_class chip_class,
2122 const struct nir_shader *nir);
2123
2124 /* radv_shader_info.h */
2125 struct radv_shader_info;
2126
2127 void radv_nir_shader_info_pass(const struct nir_shader *nir,
2128 const struct radv_nir_compiler_options *options,
2129 struct radv_shader_info *info);
2130
2131 void radv_nir_shader_info_init(struct radv_shader_info *info);
2132
2133 struct radeon_winsys_sem;
2134
2135 uint64_t radv_get_current_time(void);
2136
2137 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
2138 \
2139 static inline struct __radv_type * \
2140 __radv_type ## _from_handle(__VkType _handle) \
2141 { \
2142 return (struct __radv_type *) _handle; \
2143 } \
2144 \
2145 static inline __VkType \
2146 __radv_type ## _to_handle(struct __radv_type *_obj) \
2147 { \
2148 return (__VkType) _obj; \
2149 }
2150
2151 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
2152 \
2153 static inline struct __radv_type * \
2154 __radv_type ## _from_handle(__VkType _handle) \
2155 { \
2156 return (struct __radv_type *)(uintptr_t) _handle; \
2157 } \
2158 \
2159 static inline __VkType \
2160 __radv_type ## _to_handle(struct __radv_type *_obj) \
2161 { \
2162 return (__VkType)(uintptr_t) _obj; \
2163 }
2164
2165 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
2166 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
2167
2168 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
2169 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
2170 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
2171 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
2172 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
2173
2174 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
2175 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
2176 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
2177 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
2178 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
2179 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
2180 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplate)
2181 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
2182 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
2183 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
2184 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
2185 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
2186 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
2187 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
2188 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
2189 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
2190 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
2191 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
2192 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
2193 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler_ycbcr_conversion, VkSamplerYcbcrConversion)
2194 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
2195 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
2196
2197 #endif /* RADV_PRIVATE_H */