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radv: add support for dynamic depth/stencil states
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x) ((void)0)
44 #endif
45
46 #include "c11/threads.h"
47 #include <amdgpu.h>
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "util/xmlconfig.h"
52 #include "vk_alloc.h"
53 #include "vk_debug_report.h"
54 #include "vk_object.h"
55
56 #include "radv_radeon_winsys.h"
57 #include "ac_binary.h"
58 #include "ac_nir_to_llvm.h"
59 #include "ac_gpu_info.h"
60 #include "ac_surface.h"
61 #include "ac_llvm_build.h"
62 #include "ac_llvm_util.h"
63 #include "radv_constants.h"
64 #include "radv_descriptor_set.h"
65 #include "radv_extensions.h"
66 #include "sid.h"
67
68 /* Pre-declarations needed for WSI entrypoints */
69 struct wl_surface;
70 struct wl_display;
71 typedef struct xcb_connection_t xcb_connection_t;
72 typedef uint32_t xcb_visualid_t;
73 typedef uint32_t xcb_window_t;
74
75 #include <vulkan/vulkan.h>
76 #include <vulkan/vulkan_intel.h>
77 #include <vulkan/vulkan_android.h>
78 #include <vulkan/vk_icd.h>
79 #include <vulkan/vk_android_native_buffer.h>
80
81 #include "radv_entrypoints.h"
82
83 #include "wsi_common.h"
84 #include "wsi_common_display.h"
85
86 /* Helper to determine if we should compile
87 * any of the Android AHB support.
88 *
89 * To actually enable the ext we also need
90 * the necessary kernel support.
91 */
92 #if defined(ANDROID) && ANDROID_API_LEVEL >= 26
93 #define RADV_SUPPORT_ANDROID_HARDWARE_BUFFER 1
94 #else
95 #define RADV_SUPPORT_ANDROID_HARDWARE_BUFFER 0
96 #endif
97
98 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
99
100 static inline uint32_t
101 align_u32(uint32_t v, uint32_t a)
102 {
103 assert(a != 0 && a == (a & -a));
104 return (v + a - 1) & ~(a - 1);
105 }
106
107 static inline uint32_t
108 align_u32_npot(uint32_t v, uint32_t a)
109 {
110 return (v + a - 1) / a * a;
111 }
112
113 static inline uint64_t
114 align_u64(uint64_t v, uint64_t a)
115 {
116 assert(a != 0 && a == (a & -a));
117 return (v + a - 1) & ~(a - 1);
118 }
119
120 static inline int32_t
121 align_i32(int32_t v, int32_t a)
122 {
123 assert(a != 0 && a == (a & -a));
124 return (v + a - 1) & ~(a - 1);
125 }
126
127 /** Alignment must be a power of 2. */
128 static inline bool
129 radv_is_aligned(uintmax_t n, uintmax_t a)
130 {
131 assert(a == (a & -a));
132 return (n & (a - 1)) == 0;
133 }
134
135 static inline uint32_t
136 round_up_u32(uint32_t v, uint32_t a)
137 {
138 return (v + a - 1) / a;
139 }
140
141 static inline uint64_t
142 round_up_u64(uint64_t v, uint64_t a)
143 {
144 return (v + a - 1) / a;
145 }
146
147 static inline uint32_t
148 radv_minify(uint32_t n, uint32_t levels)
149 {
150 if (unlikely(n == 0))
151 return 0;
152 else
153 return MAX2(n >> levels, 1);
154 }
155 static inline float
156 radv_clamp_f(float f, float min, float max)
157 {
158 assert(min < max);
159
160 if (f > max)
161 return max;
162 else if (f < min)
163 return min;
164 else
165 return f;
166 }
167
168 static inline bool
169 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
170 {
171 if (*inout_mask & clear_mask) {
172 *inout_mask &= ~clear_mask;
173 return true;
174 } else {
175 return false;
176 }
177 }
178
179 #define for_each_bit(b, dword) \
180 for (uint32_t __dword = (dword); \
181 (b) = __builtin_ffs(__dword) - 1, __dword; \
182 __dword &= ~(1 << (b)))
183
184 #define typed_memcpy(dest, src, count) ({ \
185 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
186 memcpy((dest), (src), (count) * sizeof(*(src))); \
187 })
188
189 /* Whenever we generate an error, pass it through this function. Useful for
190 * debugging, where we can break on it. Only call at error site, not when
191 * propagating errors. Might be useful to plug in a stack trace here.
192 */
193
194 struct radv_image_view;
195 struct radv_instance;
196
197 VkResult __vk_errorf(struct radv_instance *instance, VkResult error, const char *file, int line, const char *format, ...);
198
199 #define vk_error(instance, error) __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
200 #define vk_errorf(instance, error, format, ...) __vk_errorf(instance, error, __FILE__, __LINE__, format, ## __VA_ARGS__);
201
202 void __radv_finishme(const char *file, int line, const char *format, ...)
203 radv_printflike(3, 4);
204 void radv_loge(const char *format, ...) radv_printflike(1, 2);
205 void radv_loge_v(const char *format, va_list va);
206 void radv_logi(const char *format, ...) radv_printflike(1, 2);
207 void radv_logi_v(const char *format, va_list va);
208
209 /**
210 * Print a FINISHME message, including its source location.
211 */
212 #define radv_finishme(format, ...) \
213 do { \
214 static bool reported = false; \
215 if (!reported) { \
216 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
217 reported = true; \
218 } \
219 } while (0)
220
221 /* A non-fatal assert. Useful for debugging. */
222 #ifdef DEBUG
223 #define radv_assert(x) ({ \
224 if (unlikely(!(x))) \
225 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
226 })
227 #else
228 #define radv_assert(x) do {} while(0)
229 #endif
230
231 #define stub_return(v) \
232 do { \
233 radv_finishme("stub %s", __func__); \
234 return (v); \
235 } while (0)
236
237 #define stub() \
238 do { \
239 radv_finishme("stub %s", __func__); \
240 return; \
241 } while (0)
242
243 int radv_get_instance_entrypoint_index(const char *name);
244 int radv_get_device_entrypoint_index(const char *name);
245 int radv_get_physical_device_entrypoint_index(const char *name);
246
247 const char *radv_get_instance_entry_name(int index);
248 const char *radv_get_physical_device_entry_name(int index);
249 const char *radv_get_device_entry_name(int index);
250
251 bool radv_instance_entrypoint_is_enabled(int index, uint32_t core_version,
252 const struct radv_instance_extension_table *instance);
253 bool radv_physical_device_entrypoint_is_enabled(int index, uint32_t core_version,
254 const struct radv_instance_extension_table *instance);
255 bool radv_device_entrypoint_is_enabled(int index, uint32_t core_version,
256 const struct radv_instance_extension_table *instance,
257 const struct radv_device_extension_table *device);
258
259 void *radv_lookup_entrypoint(const char *name);
260
261 struct radv_physical_device {
262 VK_LOADER_DATA _loader_data;
263
264 /* Link in radv_instance::physical_devices */
265 struct list_head link;
266
267 struct radv_instance * instance;
268
269 struct radeon_winsys *ws;
270 struct radeon_info rad_info;
271 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
272 uint8_t driver_uuid[VK_UUID_SIZE];
273 uint8_t device_uuid[VK_UUID_SIZE];
274 uint8_t cache_uuid[VK_UUID_SIZE];
275
276 int local_fd;
277 int master_fd;
278 struct wsi_device wsi_device;
279
280 bool out_of_order_rast_allowed;
281
282 /* Whether DCC should be enabled for MSAA textures. */
283 bool dcc_msaa_allowed;
284
285 /* Whether to enable NGG. */
286 bool use_ngg;
287
288 /* Whether to enable NGG GS. */
289 bool use_ngg_gs;
290
291 /* Whether to enable NGG streamout. */
292 bool use_ngg_streamout;
293
294 /* Number of threads per wave. */
295 uint8_t ps_wave_size;
296 uint8_t cs_wave_size;
297 uint8_t ge_wave_size;
298
299 /* Whether to use the LLVM compiler backend */
300 bool use_llvm;
301
302 /* This is the drivers on-disk cache used as a fallback as opposed to
303 * the pipeline cache defined by apps.
304 */
305 struct disk_cache * disk_cache;
306
307 VkPhysicalDeviceMemoryProperties memory_properties;
308 enum radeon_bo_domain memory_domains[VK_MAX_MEMORY_TYPES];
309 enum radeon_bo_flag memory_flags[VK_MAX_MEMORY_TYPES];
310
311 drmPciBusInfo bus_info;
312
313 struct radv_device_extension_table supported_extensions;
314 };
315
316 struct radv_instance {
317 struct vk_object_base base;
318
319 VkAllocationCallbacks alloc;
320
321 uint32_t apiVersion;
322
323 char * engineName;
324 uint32_t engineVersion;
325
326 uint64_t debug_flags;
327 uint64_t perftest_flags;
328
329 struct vk_debug_report_instance debug_report_callbacks;
330
331 struct radv_instance_extension_table enabled_extensions;
332 struct radv_instance_dispatch_table dispatch;
333 struct radv_physical_device_dispatch_table physical_device_dispatch;
334 struct radv_device_dispatch_table device_dispatch;
335
336 bool physical_devices_enumerated;
337 struct list_head physical_devices;
338
339 struct driOptionCache dri_options;
340 struct driOptionCache available_dri_options;
341
342 /**
343 * Workarounds for game bugs.
344 */
345 bool enable_mrt_output_nan_fixup;
346 };
347
348 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
349 void radv_finish_wsi(struct radv_physical_device *physical_device);
350
351 bool radv_instance_extension_supported(const char *name);
352 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
353 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
354 const char *name);
355
356 struct cache_entry;
357
358 struct radv_pipeline_cache {
359 struct vk_object_base base;
360 struct radv_device * device;
361 pthread_mutex_t mutex;
362 VkPipelineCacheCreateFlags flags;
363
364 uint32_t total_size;
365 uint32_t table_size;
366 uint32_t kernel_count;
367 struct cache_entry ** hash_table;
368 bool modified;
369
370 VkAllocationCallbacks alloc;
371 };
372
373 struct radv_pipeline_key {
374 uint32_t instance_rate_inputs;
375 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
376 uint8_t vertex_attribute_formats[MAX_VERTEX_ATTRIBS];
377 uint32_t vertex_attribute_bindings[MAX_VERTEX_ATTRIBS];
378 uint32_t vertex_attribute_offsets[MAX_VERTEX_ATTRIBS];
379 uint32_t vertex_attribute_strides[MAX_VERTEX_ATTRIBS];
380 uint64_t vertex_alpha_adjust;
381 uint32_t vertex_post_shuffle;
382 unsigned tess_input_vertices;
383 uint32_t col_format;
384 uint32_t is_int8;
385 uint32_t is_int10;
386 uint8_t log2_ps_iter_samples;
387 uint8_t num_samples;
388 bool is_dual_src;
389 uint32_t has_multiview_view_index : 1;
390 uint32_t optimisations_disabled : 1;
391 uint8_t topology;
392
393 /* Non-zero if a required subgroup size is specified via
394 * VK_EXT_subgroup_size_control.
395 */
396 uint8_t compute_subgroup_size;
397 };
398
399 struct radv_shader_binary;
400 struct radv_shader_variant;
401
402 void
403 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
404 struct radv_device *device);
405 void
406 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
407 bool
408 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
409 const void *data, size_t size);
410
411 bool
412 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
413 struct radv_pipeline_cache *cache,
414 const unsigned char *sha1,
415 struct radv_shader_variant **variants,
416 bool *found_in_application_cache);
417
418 void
419 radv_pipeline_cache_insert_shaders(struct radv_device *device,
420 struct radv_pipeline_cache *cache,
421 const unsigned char *sha1,
422 struct radv_shader_variant **variants,
423 struct radv_shader_binary *const *binaries);
424
425 enum radv_blit_ds_layout {
426 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
427 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
428 RADV_BLIT_DS_LAYOUT_COUNT,
429 };
430
431 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
432 {
433 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
434 }
435
436 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
437 {
438 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
439 }
440
441 enum radv_meta_dst_layout {
442 RADV_META_DST_LAYOUT_GENERAL,
443 RADV_META_DST_LAYOUT_OPTIMAL,
444 RADV_META_DST_LAYOUT_COUNT,
445 };
446
447 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
448 {
449 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
450 }
451
452 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
453 {
454 return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
455 }
456
457 struct radv_meta_state {
458 VkAllocationCallbacks alloc;
459
460 struct radv_pipeline_cache cache;
461
462 /*
463 * For on-demand pipeline creation, makes sure that
464 * only one thread tries to build a pipeline at the same time.
465 */
466 mtx_t mtx;
467
468 /**
469 * Use array element `i` for images with `2^i` samples.
470 */
471 struct {
472 VkRenderPass render_pass[NUM_META_FS_KEYS];
473 VkPipeline color_pipelines[NUM_META_FS_KEYS];
474
475 VkRenderPass depthstencil_rp;
476 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
477 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
478 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
479
480 VkPipeline depth_only_unrestricted_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
481 VkPipeline stencil_only_unrestricted_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
482 VkPipeline depthstencil_unrestricted_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
483 } clear[MAX_SAMPLES_LOG2];
484
485 VkPipelineLayout clear_color_p_layout;
486 VkPipelineLayout clear_depth_p_layout;
487 VkPipelineLayout clear_depth_unrestricted_p_layout;
488
489 /* Optimized compute fast HTILE clear for stencil or depth only. */
490 VkPipeline clear_htile_mask_pipeline;
491 VkPipelineLayout clear_htile_mask_p_layout;
492 VkDescriptorSetLayout clear_htile_mask_ds_layout;
493
494 struct {
495 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
496
497 /** Pipeline that blits from a 1D image. */
498 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
499
500 /** Pipeline that blits from a 2D image. */
501 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
502
503 /** Pipeline that blits from a 3D image. */
504 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
505
506 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
507 VkPipeline depth_only_1d_pipeline;
508 VkPipeline depth_only_2d_pipeline;
509 VkPipeline depth_only_3d_pipeline;
510
511 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
512 VkPipeline stencil_only_1d_pipeline;
513 VkPipeline stencil_only_2d_pipeline;
514 VkPipeline stencil_only_3d_pipeline;
515 VkPipelineLayout pipeline_layout;
516 VkDescriptorSetLayout ds_layout;
517 } blit;
518
519 struct {
520 VkPipelineLayout p_layouts[5];
521 VkDescriptorSetLayout ds_layouts[5];
522 VkPipeline pipelines[5][NUM_META_FS_KEYS];
523
524 VkPipeline depth_only_pipeline[5];
525
526 VkPipeline stencil_only_pipeline[5];
527 } blit2d[MAX_SAMPLES_LOG2];
528
529 VkRenderPass blit2d_render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
530 VkRenderPass blit2d_depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
531 VkRenderPass blit2d_stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
532
533 struct {
534 VkPipelineLayout img_p_layout;
535 VkDescriptorSetLayout img_ds_layout;
536 VkPipeline pipeline;
537 VkPipeline pipeline_3d;
538 } itob;
539 struct {
540 VkPipelineLayout img_p_layout;
541 VkDescriptorSetLayout img_ds_layout;
542 VkPipeline pipeline;
543 VkPipeline pipeline_3d;
544 } btoi;
545 struct {
546 VkPipelineLayout img_p_layout;
547 VkDescriptorSetLayout img_ds_layout;
548 VkPipeline pipeline;
549 } btoi_r32g32b32;
550 struct {
551 VkPipelineLayout img_p_layout;
552 VkDescriptorSetLayout img_ds_layout;
553 VkPipeline pipeline;
554 VkPipeline pipeline_3d;
555 } itoi;
556 struct {
557 VkPipelineLayout img_p_layout;
558 VkDescriptorSetLayout img_ds_layout;
559 VkPipeline pipeline;
560 } itoi_r32g32b32;
561 struct {
562 VkPipelineLayout img_p_layout;
563 VkDescriptorSetLayout img_ds_layout;
564 VkPipeline pipeline;
565 VkPipeline pipeline_3d;
566 } cleari;
567 struct {
568 VkPipelineLayout img_p_layout;
569 VkDescriptorSetLayout img_ds_layout;
570 VkPipeline pipeline;
571 } cleari_r32g32b32;
572
573 struct {
574 VkPipelineLayout p_layout;
575 VkPipeline pipeline[NUM_META_FS_KEYS];
576 VkRenderPass pass[NUM_META_FS_KEYS];
577 } resolve;
578
579 struct {
580 VkDescriptorSetLayout ds_layout;
581 VkPipelineLayout p_layout;
582 struct {
583 VkPipeline pipeline;
584 VkPipeline i_pipeline;
585 VkPipeline srgb_pipeline;
586 } rc[MAX_SAMPLES_LOG2];
587
588 VkPipeline depth_zero_pipeline;
589 struct {
590 VkPipeline average_pipeline;
591 VkPipeline max_pipeline;
592 VkPipeline min_pipeline;
593 } depth[MAX_SAMPLES_LOG2];
594
595 VkPipeline stencil_zero_pipeline;
596 struct {
597 VkPipeline max_pipeline;
598 VkPipeline min_pipeline;
599 } stencil[MAX_SAMPLES_LOG2];
600 } resolve_compute;
601
602 struct {
603 VkDescriptorSetLayout ds_layout;
604 VkPipelineLayout p_layout;
605
606 struct {
607 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
608 VkPipeline pipeline[NUM_META_FS_KEYS];
609 } rc[MAX_SAMPLES_LOG2];
610
611 VkRenderPass depth_render_pass;
612 VkPipeline depth_zero_pipeline;
613 struct {
614 VkPipeline average_pipeline;
615 VkPipeline max_pipeline;
616 VkPipeline min_pipeline;
617 } depth[MAX_SAMPLES_LOG2];
618
619 VkRenderPass stencil_render_pass;
620 VkPipeline stencil_zero_pipeline;
621 struct {
622 VkPipeline max_pipeline;
623 VkPipeline min_pipeline;
624 } stencil[MAX_SAMPLES_LOG2];
625 } resolve_fragment;
626
627 struct {
628 VkPipelineLayout p_layout;
629 VkPipeline decompress_pipeline[NUM_DEPTH_DECOMPRESS_PIPELINES];
630 VkPipeline resummarize_pipeline;
631 VkRenderPass pass;
632 } depth_decomp[MAX_SAMPLES_LOG2];
633
634 struct {
635 VkPipelineLayout p_layout;
636 VkPipeline cmask_eliminate_pipeline;
637 VkPipeline fmask_decompress_pipeline;
638 VkPipeline dcc_decompress_pipeline;
639 VkRenderPass pass;
640
641 VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
642 VkPipelineLayout dcc_decompress_compute_p_layout;
643 VkPipeline dcc_decompress_compute_pipeline;
644 } fast_clear_flush;
645
646 struct {
647 VkPipelineLayout fill_p_layout;
648 VkPipelineLayout copy_p_layout;
649 VkDescriptorSetLayout fill_ds_layout;
650 VkDescriptorSetLayout copy_ds_layout;
651 VkPipeline fill_pipeline;
652 VkPipeline copy_pipeline;
653 } buffer;
654
655 struct {
656 VkDescriptorSetLayout ds_layout;
657 VkPipelineLayout p_layout;
658 VkPipeline occlusion_query_pipeline;
659 VkPipeline pipeline_statistics_query_pipeline;
660 VkPipeline tfb_query_pipeline;
661 VkPipeline timestamp_query_pipeline;
662 } query;
663
664 struct {
665 VkDescriptorSetLayout ds_layout;
666 VkPipelineLayout p_layout;
667 VkPipeline pipeline[MAX_SAMPLES_LOG2];
668 } fmask_expand;
669 };
670
671 /* queue types */
672 #define RADV_QUEUE_GENERAL 0
673 #define RADV_QUEUE_COMPUTE 1
674 #define RADV_QUEUE_TRANSFER 2
675
676 #define RADV_MAX_QUEUE_FAMILIES 3
677
678 enum ring_type radv_queue_family_to_ring(int f);
679
680 struct radv_queue {
681 VK_LOADER_DATA _loader_data;
682 struct radv_device * device;
683 struct radeon_winsys_ctx *hw_ctx;
684 enum radeon_ctx_priority priority;
685 uint32_t queue_family_index;
686 int queue_idx;
687 VkDeviceQueueCreateFlags flags;
688
689 uint32_t scratch_size_per_wave;
690 uint32_t scratch_waves;
691 uint32_t compute_scratch_size_per_wave;
692 uint32_t compute_scratch_waves;
693 uint32_t esgs_ring_size;
694 uint32_t gsvs_ring_size;
695 bool has_tess_rings;
696 bool has_gds;
697 bool has_gds_oa;
698 bool has_sample_positions;
699
700 struct radeon_winsys_bo *scratch_bo;
701 struct radeon_winsys_bo *descriptor_bo;
702 struct radeon_winsys_bo *compute_scratch_bo;
703 struct radeon_winsys_bo *esgs_ring_bo;
704 struct radeon_winsys_bo *gsvs_ring_bo;
705 struct radeon_winsys_bo *tess_rings_bo;
706 struct radeon_winsys_bo *gds_bo;
707 struct radeon_winsys_bo *gds_oa_bo;
708 struct radeon_cmdbuf *initial_preamble_cs;
709 struct radeon_cmdbuf *initial_full_flush_preamble_cs;
710 struct radeon_cmdbuf *continue_preamble_cs;
711
712 struct list_head pending_submissions;
713 pthread_mutex_t pending_mutex;
714 };
715
716 struct radv_bo_list {
717 struct radv_winsys_bo_list list;
718 unsigned capacity;
719 pthread_mutex_t mutex;
720 };
721
722 VkResult radv_bo_list_add(struct radv_device *device,
723 struct radeon_winsys_bo *bo);
724 void radv_bo_list_remove(struct radv_device *device,
725 struct radeon_winsys_bo *bo);
726
727 #define RADV_BORDER_COLOR_COUNT 4096
728 #define RADV_BORDER_COLOR_BUFFER_SIZE (sizeof(VkClearColorValue) * RADV_BORDER_COLOR_COUNT)
729
730 struct radv_device_border_color_data {
731 bool used[RADV_BORDER_COLOR_COUNT];
732
733 struct radeon_winsys_bo *bo;
734 VkClearColorValue *colors_gpu_ptr;
735
736 /* Mutex is required to guarantee vkCreateSampler thread safety
737 * given that we are writing to a buffer and checking color occupation */
738 pthread_mutex_t mutex;
739 };
740
741 struct radv_device {
742 struct vk_device vk;
743
744 struct radv_instance * instance;
745 struct radeon_winsys *ws;
746
747 struct radv_meta_state meta_state;
748
749 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
750 int queue_count[RADV_MAX_QUEUE_FAMILIES];
751 struct radeon_cmdbuf *empty_cs[RADV_MAX_QUEUE_FAMILIES];
752
753 bool always_use_syncobj;
754 bool pbb_allowed;
755 bool dfsm_allowed;
756 uint32_t tess_offchip_block_dw_size;
757 uint32_t scratch_waves;
758 uint32_t dispatch_initiator;
759
760 uint32_t gs_table_depth;
761
762 /* MSAA sample locations.
763 * The first index is the sample index.
764 * The second index is the coordinate: X, Y. */
765 float sample_locations_1x[1][2];
766 float sample_locations_2x[2][2];
767 float sample_locations_4x[4][2];
768 float sample_locations_8x[8][2];
769
770 /* GFX7 and later */
771 uint32_t gfx_init_size_dw;
772 struct radeon_winsys_bo *gfx_init;
773
774 struct radeon_winsys_bo *trace_bo;
775 uint32_t *trace_id_ptr;
776
777 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
778 bool keep_shader_info;
779
780 struct radv_physical_device *physical_device;
781
782 /* Backup in-memory cache to be used if the app doesn't provide one */
783 struct radv_pipeline_cache * mem_cache;
784
785 /*
786 * use different counters so MSAA MRTs get consecutive surface indices,
787 * even if MASK is allocated in between.
788 */
789 uint32_t image_mrt_offset_counter;
790 uint32_t fmask_mrt_offset_counter;
791 struct list_head shader_slabs;
792 mtx_t shader_slab_mutex;
793
794 /* For detecting VM faults reported by dmesg. */
795 uint64_t dmesg_timestamp;
796
797 struct radv_device_extension_table enabled_extensions;
798 struct radv_device_dispatch_table dispatch;
799
800 /* Whether the app has enabled the robustBufferAccess feature. */
801 bool robust_buffer_access;
802
803 /* Whether the driver uses a global BO list. */
804 bool use_global_bo_list;
805
806 struct radv_bo_list bo_list;
807
808 /* Whether anisotropy is forced with RADV_TEX_ANISO (-1 is disabled). */
809 int force_aniso;
810
811 struct radv_device_border_color_data border_color_data;
812
813 /* Condition variable for legacy timelines, to notify waiters when a
814 * new point gets submitted. */
815 pthread_cond_t timeline_cond;
816
817 /* Thread trace. */
818 struct radeon_cmdbuf *thread_trace_start_cs[2];
819 struct radeon_cmdbuf *thread_trace_stop_cs[2];
820 struct radeon_winsys_bo *thread_trace_bo;
821 void *thread_trace_ptr;
822 uint32_t thread_trace_buffer_size;
823 int thread_trace_start_frame;
824
825 /* Overallocation. */
826 bool overallocation_disallowed;
827 uint64_t allocated_memory_size[VK_MAX_MEMORY_HEAPS];
828 mtx_t overallocation_mutex;
829 };
830
831 struct radv_device_memory {
832 struct vk_object_base base;
833 struct radeon_winsys_bo *bo;
834 /* for dedicated allocations */
835 struct radv_image *image;
836 struct radv_buffer *buffer;
837 uint32_t heap_index;
838 uint64_t alloc_size;
839 void * map;
840 void * user_ptr;
841
842 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
843 struct AHardwareBuffer * android_hardware_buffer;
844 #endif
845 };
846
847
848 struct radv_descriptor_range {
849 uint64_t va;
850 uint32_t size;
851 };
852
853 struct radv_descriptor_set {
854 struct vk_object_base base;
855 const struct radv_descriptor_set_layout *layout;
856 uint32_t size;
857 uint32_t buffer_count;
858
859 struct radeon_winsys_bo *bo;
860 uint64_t va;
861 uint32_t *mapped_ptr;
862 struct radv_descriptor_range *dynamic_descriptors;
863
864 struct radeon_winsys_bo *descriptors[0];
865 };
866
867 struct radv_push_descriptor_set
868 {
869 struct radv_descriptor_set set;
870 uint32_t capacity;
871 };
872
873 struct radv_descriptor_pool_entry {
874 uint32_t offset;
875 uint32_t size;
876 struct radv_descriptor_set *set;
877 };
878
879 struct radv_descriptor_pool {
880 struct vk_object_base base;
881 struct radeon_winsys_bo *bo;
882 uint8_t *mapped_ptr;
883 uint64_t current_offset;
884 uint64_t size;
885
886 uint8_t *host_memory_base;
887 uint8_t *host_memory_ptr;
888 uint8_t *host_memory_end;
889
890 uint32_t entry_count;
891 uint32_t max_entry_count;
892 struct radv_descriptor_pool_entry entries[0];
893 };
894
895 struct radv_descriptor_update_template_entry {
896 VkDescriptorType descriptor_type;
897
898 /* The number of descriptors to update */
899 uint32_t descriptor_count;
900
901 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
902 uint32_t dst_offset;
903
904 /* In dwords. Not valid/used for dynamic descriptors */
905 uint32_t dst_stride;
906
907 uint32_t buffer_offset;
908
909 /* Only valid for combined image samplers and samplers */
910 uint8_t has_sampler;
911 uint8_t sampler_offset;
912
913 /* In bytes */
914 size_t src_offset;
915 size_t src_stride;
916
917 /* For push descriptors */
918 const uint32_t *immutable_samplers;
919 };
920
921 struct radv_descriptor_update_template {
922 struct vk_object_base base;
923 uint32_t entry_count;
924 VkPipelineBindPoint bind_point;
925 struct radv_descriptor_update_template_entry entry[0];
926 };
927
928 struct radv_buffer {
929 struct vk_object_base base;
930 VkDeviceSize size;
931
932 VkBufferUsageFlags usage;
933 VkBufferCreateFlags flags;
934
935 /* Set when bound */
936 struct radeon_winsys_bo * bo;
937 VkDeviceSize offset;
938
939 bool shareable;
940 };
941
942 enum radv_dynamic_state_bits {
943 RADV_DYNAMIC_VIEWPORT = 1 << 0,
944 RADV_DYNAMIC_SCISSOR = 1 << 1,
945 RADV_DYNAMIC_LINE_WIDTH = 1 << 2,
946 RADV_DYNAMIC_DEPTH_BIAS = 1 << 3,
947 RADV_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
948 RADV_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
949 RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
950 RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
951 RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
952 RADV_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
953 RADV_DYNAMIC_SAMPLE_LOCATIONS = 1 << 10,
954 RADV_DYNAMIC_LINE_STIPPLE = 1 << 11,
955 RADV_DYNAMIC_CULL_MODE = 1 << 12,
956 RADV_DYNAMIC_FRONT_FACE = 1 << 13,
957 RADV_DYNAMIC_PRIMITIVE_TOPOLOGY = 1 << 14,
958 RADV_DYNAMIC_DEPTH_TEST_ENABLE = 1 << 15,
959 RADV_DYNAMIC_DEPTH_WRITE_ENABLE = 1 << 16,
960 RADV_DYNAMIC_DEPTH_COMPARE_OP = 1 << 17,
961 RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE = 1 << 18,
962 RADV_DYNAMIC_STENCIL_TEST_ENABLE = 1 << 19,
963 RADV_DYNAMIC_STENCIL_OP = 1 << 20,
964 RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE = 1 << 21,
965 RADV_DYNAMIC_ALL = (1 << 22) - 1,
966 };
967
968 enum radv_cmd_dirty_bits {
969 /* Keep the dynamic state dirty bits in sync with
970 * enum radv_dynamic_state_bits */
971 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0,
972 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1,
973 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2,
974 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3,
975 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
976 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
977 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
978 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
979 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
980 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
981 RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS = 1 << 10,
982 RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE = 1 << 11,
983 RADV_CMD_DIRTY_DYNAMIC_CULL_MODE = 1 << 12,
984 RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE = 1 << 13,
985 RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY = 1 << 14,
986 RADV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE = 1 << 15,
987 RADV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE = 1 << 16,
988 RADV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP = 1 << 17,
989 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE = 1 << 18,
990 RADV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE = 1 << 19,
991 RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP = 1 << 20,
992 RADV_CMD_DIRTY_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE = 1 << 21,
993 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 22) - 1,
994 RADV_CMD_DIRTY_PIPELINE = 1 << 22,
995 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 23,
996 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 24,
997 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 25,
998 RADV_CMD_DIRTY_STREAMOUT_BUFFER = 1 << 26,
999 };
1000
1001 enum radv_cmd_flush_bits {
1002 /* Instruction cache. */
1003 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
1004 /* Scalar L1 cache. */
1005 RADV_CMD_FLAG_INV_SCACHE = 1 << 1,
1006 /* Vector L1 cache. */
1007 RADV_CMD_FLAG_INV_VCACHE = 1 << 2,
1008 /* L2 cache + L2 metadata cache writeback & invalidate.
1009 * GFX6-8: Used by shaders only. GFX9-10: Used by everything. */
1010 RADV_CMD_FLAG_INV_L2 = 1 << 3,
1011 /* L2 writeback (write dirty L2 lines to memory for non-L2 clients).
1012 * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8.
1013 * GFX6-7 will do complete invalidation, because the writeback is unsupported. */
1014 RADV_CMD_FLAG_WB_L2 = 1 << 4,
1015 /* Framebuffer caches */
1016 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
1017 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
1018 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
1019 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
1020 /* Engine synchronization. */
1021 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
1022 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
1023 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
1024 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
1025 /* Pipeline query controls. */
1026 RADV_CMD_FLAG_START_PIPELINE_STATS = 1 << 13,
1027 RADV_CMD_FLAG_STOP_PIPELINE_STATS = 1 << 14,
1028 RADV_CMD_FLAG_VGT_STREAMOUT_SYNC = 1 << 15,
1029
1030 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1031 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1032 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1033 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
1034 };
1035
1036 struct radv_vertex_binding {
1037 struct radv_buffer * buffer;
1038 VkDeviceSize offset;
1039 };
1040
1041 struct radv_streamout_binding {
1042 struct radv_buffer *buffer;
1043 VkDeviceSize offset;
1044 VkDeviceSize size;
1045 };
1046
1047 struct radv_streamout_state {
1048 /* Mask of bound streamout buffers. */
1049 uint8_t enabled_mask;
1050
1051 /* External state that comes from the last vertex stage, it must be
1052 * set explicitely when binding a new graphics pipeline.
1053 */
1054 uint16_t stride_in_dw[MAX_SO_BUFFERS];
1055 uint32_t enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
1056
1057 /* State of VGT_STRMOUT_BUFFER_(CONFIG|END) */
1058 uint32_t hw_enabled_mask;
1059
1060 /* State of VGT_STRMOUT_(CONFIG|EN) */
1061 bool streamout_enabled;
1062 };
1063
1064 struct radv_viewport_state {
1065 uint32_t count;
1066 VkViewport viewports[MAX_VIEWPORTS];
1067 };
1068
1069 struct radv_scissor_state {
1070 uint32_t count;
1071 VkRect2D scissors[MAX_SCISSORS];
1072 };
1073
1074 struct radv_discard_rectangle_state {
1075 uint32_t count;
1076 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
1077 };
1078
1079 struct radv_sample_locations_state {
1080 VkSampleCountFlagBits per_pixel;
1081 VkExtent2D grid_size;
1082 uint32_t count;
1083 VkSampleLocationEXT locations[MAX_SAMPLE_LOCATIONS];
1084 };
1085
1086 struct radv_dynamic_state {
1087 /**
1088 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
1089 * Defines the set of saved dynamic state.
1090 */
1091 uint32_t mask;
1092
1093 struct radv_viewport_state viewport;
1094
1095 struct radv_scissor_state scissor;
1096
1097 float line_width;
1098
1099 struct {
1100 float bias;
1101 float clamp;
1102 float slope;
1103 } depth_bias;
1104
1105 float blend_constants[4];
1106
1107 struct {
1108 float min;
1109 float max;
1110 } depth_bounds;
1111
1112 struct {
1113 uint32_t front;
1114 uint32_t back;
1115 } stencil_compare_mask;
1116
1117 struct {
1118 uint32_t front;
1119 uint32_t back;
1120 } stencil_write_mask;
1121
1122 struct {
1123 struct {
1124 VkStencilOp fail_op;
1125 VkStencilOp pass_op;
1126 VkStencilOp depth_fail_op;
1127 VkCompareOp compare_op;
1128 } front;
1129
1130 struct {
1131 VkStencilOp fail_op;
1132 VkStencilOp pass_op;
1133 VkStencilOp depth_fail_op;
1134 VkCompareOp compare_op;
1135 } back;
1136 } stencil_op;
1137
1138 struct {
1139 uint32_t front;
1140 uint32_t back;
1141 } stencil_reference;
1142
1143 struct radv_discard_rectangle_state discard_rectangle;
1144
1145 struct radv_sample_locations_state sample_location;
1146
1147 struct {
1148 uint32_t factor;
1149 uint16_t pattern;
1150 } line_stipple;
1151
1152 VkCullModeFlags cull_mode;
1153 VkFrontFace front_face;
1154 unsigned primitive_topology;
1155
1156 bool depth_test_enable;
1157 bool depth_write_enable;
1158 VkCompareOp depth_compare_op;
1159 bool depth_bounds_test_enable;
1160 bool stencil_test_enable;
1161 };
1162
1163 extern const struct radv_dynamic_state default_dynamic_state;
1164
1165 const char *
1166 radv_get_debug_option_name(int id);
1167
1168 const char *
1169 radv_get_perftest_option_name(int id);
1170
1171 struct radv_color_buffer_info {
1172 uint64_t cb_color_base;
1173 uint64_t cb_color_cmask;
1174 uint64_t cb_color_fmask;
1175 uint64_t cb_dcc_base;
1176 uint32_t cb_color_slice;
1177 uint32_t cb_color_view;
1178 uint32_t cb_color_info;
1179 uint32_t cb_color_attrib;
1180 uint32_t cb_color_attrib2; /* GFX9 and later */
1181 uint32_t cb_color_attrib3; /* GFX10 and later */
1182 uint32_t cb_dcc_control;
1183 uint32_t cb_color_cmask_slice;
1184 uint32_t cb_color_fmask_slice;
1185 union {
1186 uint32_t cb_color_pitch; // GFX6-GFX8
1187 uint32_t cb_mrt_epitch; // GFX9+
1188 };
1189 };
1190
1191 struct radv_ds_buffer_info {
1192 uint64_t db_z_read_base;
1193 uint64_t db_stencil_read_base;
1194 uint64_t db_z_write_base;
1195 uint64_t db_stencil_write_base;
1196 uint64_t db_htile_data_base;
1197 uint32_t db_depth_info;
1198 uint32_t db_z_info;
1199 uint32_t db_stencil_info;
1200 uint32_t db_depth_view;
1201 uint32_t db_depth_size;
1202 uint32_t db_depth_slice;
1203 uint32_t db_htile_surface;
1204 uint32_t pa_su_poly_offset_db_fmt_cntl;
1205 uint32_t db_z_info2; /* GFX9 only */
1206 uint32_t db_stencil_info2; /* GFX9 only */
1207 float offset_scale;
1208 };
1209
1210 void
1211 radv_initialise_color_surface(struct radv_device *device,
1212 struct radv_color_buffer_info *cb,
1213 struct radv_image_view *iview);
1214 void
1215 radv_initialise_ds_surface(struct radv_device *device,
1216 struct radv_ds_buffer_info *ds,
1217 struct radv_image_view *iview);
1218
1219 /**
1220 * Attachment state when recording a renderpass instance.
1221 *
1222 * The clear value is valid only if there exists a pending clear.
1223 */
1224 struct radv_attachment_state {
1225 VkImageAspectFlags pending_clear_aspects;
1226 uint32_t cleared_views;
1227 VkClearValue clear_value;
1228 VkImageLayout current_layout;
1229 VkImageLayout current_stencil_layout;
1230 bool current_in_render_loop;
1231 struct radv_sample_locations_state sample_location;
1232
1233 union {
1234 struct radv_color_buffer_info cb;
1235 struct radv_ds_buffer_info ds;
1236 };
1237 struct radv_image_view *iview;
1238 };
1239
1240 struct radv_descriptor_state {
1241 struct radv_descriptor_set *sets[MAX_SETS];
1242 uint32_t dirty;
1243 uint32_t valid;
1244 struct radv_push_descriptor_set push_set;
1245 bool push_dirty;
1246 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
1247 };
1248
1249 struct radv_subpass_sample_locs_state {
1250 uint32_t subpass_idx;
1251 struct radv_sample_locations_state sample_location;
1252 };
1253
1254 struct radv_cmd_state {
1255 /* Vertex descriptors */
1256 uint64_t vb_va;
1257 unsigned vb_size;
1258
1259 bool predicating;
1260 uint32_t dirty;
1261
1262 uint32_t prefetch_L2_mask;
1263
1264 struct radv_pipeline * pipeline;
1265 struct radv_pipeline * emitted_pipeline;
1266 struct radv_pipeline * compute_pipeline;
1267 struct radv_pipeline * emitted_compute_pipeline;
1268 struct radv_framebuffer * framebuffer;
1269 struct radv_render_pass * pass;
1270 const struct radv_subpass * subpass;
1271 struct radv_dynamic_state dynamic;
1272 struct radv_attachment_state * attachments;
1273 struct radv_streamout_state streamout;
1274 VkRect2D render_area;
1275
1276 uint32_t num_subpass_sample_locs;
1277 struct radv_subpass_sample_locs_state * subpass_sample_locs;
1278
1279 /* Index buffer */
1280 struct radv_buffer *index_buffer;
1281 uint64_t index_offset;
1282 uint32_t index_type;
1283 uint32_t max_index_count;
1284 uint64_t index_va;
1285 int32_t last_index_type;
1286
1287 int32_t last_primitive_reset_en;
1288 uint32_t last_primitive_reset_index;
1289 enum radv_cmd_flush_bits flush_bits;
1290 unsigned active_occlusion_queries;
1291 bool perfect_occlusion_queries_enabled;
1292 unsigned active_pipeline_queries;
1293 unsigned active_pipeline_gds_queries;
1294 float offset_scale;
1295 uint32_t trace_id;
1296 uint32_t last_ia_multi_vgt_param;
1297
1298 uint32_t last_num_instances;
1299 uint32_t last_first_instance;
1300 uint32_t last_vertex_offset;
1301
1302 uint32_t last_sx_ps_downconvert;
1303 uint32_t last_sx_blend_opt_epsilon;
1304 uint32_t last_sx_blend_opt_control;
1305
1306 /* Whether CP DMA is busy/idle. */
1307 bool dma_is_busy;
1308
1309 /* Conditional rendering info. */
1310 int predication_type; /* -1: disabled, 0: normal, 1: inverted */
1311 uint64_t predication_va;
1312
1313 /* Inheritance info. */
1314 VkQueryPipelineStatisticFlags inherited_pipeline_statistics;
1315
1316 bool context_roll_without_scissor_emitted;
1317
1318 /* SQTT related state. */
1319 uint32_t current_event_type;
1320 uint32_t num_events;
1321 uint32_t num_layout_transitions;
1322 };
1323
1324 struct radv_cmd_pool {
1325 struct vk_object_base base;
1326 VkAllocationCallbacks alloc;
1327 struct list_head cmd_buffers;
1328 struct list_head free_cmd_buffers;
1329 uint32_t queue_family_index;
1330 };
1331
1332 struct radv_cmd_buffer_upload {
1333 uint8_t *map;
1334 unsigned offset;
1335 uint64_t size;
1336 struct radeon_winsys_bo *upload_bo;
1337 struct list_head list;
1338 };
1339
1340 enum radv_cmd_buffer_status {
1341 RADV_CMD_BUFFER_STATUS_INVALID,
1342 RADV_CMD_BUFFER_STATUS_INITIAL,
1343 RADV_CMD_BUFFER_STATUS_RECORDING,
1344 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
1345 RADV_CMD_BUFFER_STATUS_PENDING,
1346 };
1347
1348 struct radv_cmd_buffer {
1349 struct vk_object_base base;
1350
1351 struct radv_device * device;
1352
1353 struct radv_cmd_pool * pool;
1354 struct list_head pool_link;
1355
1356 VkCommandBufferUsageFlags usage_flags;
1357 VkCommandBufferLevel level;
1358 enum radv_cmd_buffer_status status;
1359 struct radeon_cmdbuf *cs;
1360 struct radv_cmd_state state;
1361 struct radv_vertex_binding vertex_bindings[MAX_VBS];
1362 struct radv_streamout_binding streamout_bindings[MAX_SO_BUFFERS];
1363 uint32_t queue_family_index;
1364
1365 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
1366 VkShaderStageFlags push_constant_stages;
1367 struct radv_descriptor_set meta_push_descriptors;
1368
1369 struct radv_descriptor_state descriptors[MAX_BIND_POINTS];
1370
1371 struct radv_cmd_buffer_upload upload;
1372
1373 uint32_t scratch_size_per_wave_needed;
1374 uint32_t scratch_waves_wanted;
1375 uint32_t compute_scratch_size_per_wave_needed;
1376 uint32_t compute_scratch_waves_wanted;
1377 uint32_t esgs_ring_size_needed;
1378 uint32_t gsvs_ring_size_needed;
1379 bool tess_rings_needed;
1380 bool gds_needed; /* for GFX10 streamout and NGG GS queries */
1381 bool gds_oa_needed; /* for GFX10 streamout */
1382 bool sample_positions_needed;
1383
1384 VkResult record_result;
1385
1386 uint64_t gfx9_fence_va;
1387 uint32_t gfx9_fence_idx;
1388 uint64_t gfx9_eop_bug_va;
1389
1390 /**
1391 * Whether a query pool has been resetted and we have to flush caches.
1392 */
1393 bool pending_reset_query;
1394
1395 /**
1396 * Bitmask of pending active query flushes.
1397 */
1398 enum radv_cmd_flush_bits active_query_flush_bits;
1399 };
1400
1401 struct radv_image;
1402 struct radv_image_view;
1403
1404 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
1405
1406 void si_emit_graphics(struct radv_device *device,
1407 struct radeon_cmdbuf *cs);
1408 void si_emit_compute(struct radv_physical_device *physical_device,
1409 struct radeon_cmdbuf *cs);
1410
1411 void cik_create_gfx_config(struct radv_device *device);
1412
1413 void si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
1414 int count, const VkViewport *viewports);
1415 void si_write_scissors(struct radeon_cmdbuf *cs, int first,
1416 int count, const VkRect2D *scissors,
1417 const VkViewport *viewports, bool can_use_guardband);
1418 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
1419 bool instanced_draw, bool indirect_draw,
1420 bool count_from_stream_output,
1421 uint32_t draw_vertex_count,
1422 unsigned topology);
1423 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
1424 enum chip_class chip_class,
1425 bool is_mec,
1426 unsigned event, unsigned event_flags,
1427 unsigned dst_sel, unsigned data_sel,
1428 uint64_t va,
1429 uint32_t new_fence,
1430 uint64_t gfx9_eop_bug_va);
1431
1432 void radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va,
1433 uint32_t ref, uint32_t mask);
1434 void si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
1435 enum chip_class chip_class,
1436 uint32_t *fence_ptr, uint64_t va,
1437 bool is_mec,
1438 enum radv_cmd_flush_bits flush_bits,
1439 uint64_t gfx9_eop_bug_va);
1440 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
1441 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
1442 bool inverted, uint64_t va);
1443 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1444 uint64_t src_va, uint64_t dest_va,
1445 uint64_t size);
1446 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1447 unsigned size);
1448 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1449 uint64_t size, unsigned value);
1450 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer);
1451
1452 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1453 bool
1454 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1455 unsigned size,
1456 unsigned alignment,
1457 unsigned *out_offset,
1458 void **ptr);
1459 void
1460 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1461 const struct radv_subpass *subpass);
1462 bool
1463 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1464 unsigned size, unsigned alignmnet,
1465 const void *data, unsigned *out_offset);
1466
1467 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1468 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1469 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1470 void radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer,
1471 VkImageAspectFlags aspects,
1472 VkResolveModeFlagBits resolve_mode);
1473 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1474 void radv_depth_stencil_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer,
1475 VkImageAspectFlags aspects,
1476 VkResolveModeFlagBits resolve_mode);
1477 void radv_emit_default_sample_locations(struct radeon_cmdbuf *cs, int nr_samples);
1478 unsigned radv_get_default_max_sample_dist(int log_samples);
1479 void radv_device_init_msaa(struct radv_device *device);
1480
1481 void radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1482 const struct radv_image_view *iview,
1483 VkClearDepthStencilValue ds_clear_value,
1484 VkImageAspectFlags aspects);
1485
1486 void radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1487 const struct radv_image_view *iview,
1488 int cb_idx,
1489 uint32_t color_values[2]);
1490
1491 void radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1492 struct radv_image *image,
1493 const VkImageSubresourceRange *range, bool value);
1494
1495 void radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1496 struct radv_image *image,
1497 const VkImageSubresourceRange *range, bool value);
1498
1499 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1500 struct radeon_winsys_bo *bo,
1501 uint64_t offset, uint64_t size, uint32_t value);
1502 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1503 bool radv_get_memory_fd(struct radv_device *device,
1504 struct radv_device_memory *memory,
1505 int *pFD);
1506
1507 static inline void
1508 radv_emit_shader_pointer_head(struct radeon_cmdbuf *cs,
1509 unsigned sh_offset, unsigned pointer_count,
1510 bool use_32bit_pointers)
1511 {
1512 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, pointer_count * (use_32bit_pointers ? 1 : 2), 0));
1513 radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2);
1514 }
1515
1516 static inline void
1517 radv_emit_shader_pointer_body(struct radv_device *device,
1518 struct radeon_cmdbuf *cs,
1519 uint64_t va, bool use_32bit_pointers)
1520 {
1521 radeon_emit(cs, va);
1522
1523 if (use_32bit_pointers) {
1524 assert(va == 0 ||
1525 (va >> 32) == device->physical_device->rad_info.address32_hi);
1526 } else {
1527 radeon_emit(cs, va >> 32);
1528 }
1529 }
1530
1531 static inline void
1532 radv_emit_shader_pointer(struct radv_device *device,
1533 struct radeon_cmdbuf *cs,
1534 uint32_t sh_offset, uint64_t va, bool global)
1535 {
1536 bool use_32bit_pointers = !global;
1537
1538 radv_emit_shader_pointer_head(cs, sh_offset, 1, use_32bit_pointers);
1539 radv_emit_shader_pointer_body(device, cs, va, use_32bit_pointers);
1540 }
1541
1542 static inline struct radv_descriptor_state *
1543 radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
1544 VkPipelineBindPoint bind_point)
1545 {
1546 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS ||
1547 bind_point == VK_PIPELINE_BIND_POINT_COMPUTE);
1548 return &cmd_buffer->descriptors[bind_point];
1549 }
1550
1551 /*
1552 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1553 *
1554 * Limitations: Can't call normal dispatch functions without binding or rebinding
1555 * the compute pipeline.
1556 */
1557 void radv_unaligned_dispatch(
1558 struct radv_cmd_buffer *cmd_buffer,
1559 uint32_t x,
1560 uint32_t y,
1561 uint32_t z);
1562
1563 struct radv_event {
1564 struct vk_object_base base;
1565 struct radeon_winsys_bo *bo;
1566 uint64_t *map;
1567 };
1568
1569 struct radv_shader_module;
1570
1571 #define RADV_HASH_SHADER_NO_NGG (1 << 0)
1572 #define RADV_HASH_SHADER_CS_WAVE32 (1 << 1)
1573 #define RADV_HASH_SHADER_PS_WAVE32 (1 << 2)
1574 #define RADV_HASH_SHADER_GE_WAVE32 (1 << 3)
1575 #define RADV_HASH_SHADER_LLVM (1 << 4)
1576
1577 void
1578 radv_hash_shaders(unsigned char *hash,
1579 const VkPipelineShaderStageCreateInfo **stages,
1580 const struct radv_pipeline_layout *layout,
1581 const struct radv_pipeline_key *key,
1582 uint32_t flags);
1583
1584 static inline gl_shader_stage
1585 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1586 {
1587 assert(__builtin_popcount(vk_stage) == 1);
1588 return ffs(vk_stage) - 1;
1589 }
1590
1591 static inline VkShaderStageFlagBits
1592 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1593 {
1594 return (1 << mesa_stage);
1595 }
1596
1597 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1598
1599 #define radv_foreach_stage(stage, stage_bits) \
1600 for (gl_shader_stage stage, \
1601 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1602 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1603 __tmp &= ~(1 << (stage)))
1604
1605 extern const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS];
1606 unsigned radv_format_meta_fs_key(VkFormat format);
1607
1608 struct radv_multisample_state {
1609 uint32_t db_eqaa;
1610 uint32_t pa_sc_line_cntl;
1611 uint32_t pa_sc_mode_cntl_0;
1612 uint32_t pa_sc_mode_cntl_1;
1613 uint32_t pa_sc_aa_config;
1614 uint32_t pa_sc_aa_mask[2];
1615 unsigned num_samples;
1616 };
1617
1618 struct radv_prim_vertex_count {
1619 uint8_t min;
1620 uint8_t incr;
1621 };
1622
1623 struct radv_vertex_elements_info {
1624 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1625 };
1626
1627 struct radv_ia_multi_vgt_param_helpers {
1628 uint32_t base;
1629 bool partial_es_wave;
1630 uint8_t primgroup_size;
1631 bool ia_switch_on_eoi;
1632 bool partial_vs_wave;
1633 };
1634
1635 struct radv_binning_state {
1636 uint32_t pa_sc_binner_cntl_0;
1637 uint32_t db_dfsm_control;
1638 };
1639
1640 #define SI_GS_PER_ES 128
1641
1642 struct radv_pipeline {
1643 struct vk_object_base base;
1644 struct radv_device * device;
1645 struct radv_dynamic_state dynamic_state;
1646
1647 struct radv_pipeline_layout * layout;
1648
1649 bool need_indirect_descriptor_sets;
1650 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1651 struct radv_shader_variant *gs_copy_shader;
1652 VkShaderStageFlags active_stages;
1653
1654 struct radeon_cmdbuf cs;
1655 uint32_t ctx_cs_hash;
1656 struct radeon_cmdbuf ctx_cs;
1657
1658 struct radv_vertex_elements_info vertex_elements;
1659
1660 uint32_t binding_stride[MAX_VBS];
1661 uint8_t num_vertex_bindings;
1662
1663 uint32_t user_data_0[MESA_SHADER_STAGES];
1664 union {
1665 struct {
1666 struct radv_multisample_state ms;
1667 struct radv_binning_state binning;
1668 uint32_t spi_baryc_cntl;
1669 bool prim_restart_enable;
1670 unsigned esgs_ring_size;
1671 unsigned gsvs_ring_size;
1672 uint32_t vtx_base_sgpr;
1673 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
1674 uint8_t vtx_emit_num;
1675 bool can_use_guardband;
1676 uint32_t needed_dynamic_state;
1677 bool disable_out_of_order_rast_for_occlusion;
1678 unsigned tess_patch_control_points;
1679 unsigned pa_su_sc_mode_cntl;
1680 unsigned db_depth_control;
1681
1682 /* Used for rbplus */
1683 uint32_t col_format;
1684 uint32_t cb_target_mask;
1685 bool is_dual_src;
1686 } graphics;
1687 };
1688
1689 unsigned max_waves;
1690 unsigned scratch_bytes_per_wave;
1691
1692 /* Not NULL if graphics pipeline uses streamout. */
1693 struct radv_shader_variant *streamout_shader;
1694 };
1695
1696 static inline bool radv_pipeline_has_gs(const struct radv_pipeline *pipeline)
1697 {
1698 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1699 }
1700
1701 static inline bool radv_pipeline_has_tess(const struct radv_pipeline *pipeline)
1702 {
1703 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1704 }
1705
1706 bool radv_pipeline_has_ngg(const struct radv_pipeline *pipeline);
1707
1708 bool radv_pipeline_has_ngg_passthrough(const struct radv_pipeline *pipeline);
1709
1710 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline *pipeline);
1711
1712 struct radv_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1713 gl_shader_stage stage,
1714 int idx);
1715
1716 struct radv_shader_variant *radv_get_shader(struct radv_pipeline *pipeline,
1717 gl_shader_stage stage);
1718
1719 struct radv_graphics_pipeline_create_info {
1720 bool use_rectlist;
1721 bool db_depth_clear;
1722 bool db_stencil_clear;
1723 bool db_depth_disable_expclear;
1724 bool db_stencil_disable_expclear;
1725 bool depth_compress_disable;
1726 bool stencil_compress_disable;
1727 bool resummarize_enable;
1728 uint32_t custom_blend_mode;
1729 };
1730
1731 VkResult
1732 radv_graphics_pipeline_create(VkDevice device,
1733 VkPipelineCache cache,
1734 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1735 const struct radv_graphics_pipeline_create_info *extra,
1736 const VkAllocationCallbacks *alloc,
1737 VkPipeline *pPipeline);
1738
1739 struct radv_binning_settings {
1740 unsigned context_states_per_bin; /* allowed range: [1, 6] */
1741 unsigned persistent_states_per_bin; /* allowed range: [1, 32] */
1742 unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */
1743 };
1744
1745 struct radv_binning_settings
1746 radv_get_binning_settings(const struct radv_physical_device *pdev);
1747
1748 struct vk_format_description;
1749 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1750 int first_non_void);
1751 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1752 int first_non_void);
1753 bool radv_is_buffer_format_supported(VkFormat format, bool *scaled);
1754 uint32_t radv_translate_colorformat(VkFormat format);
1755 uint32_t radv_translate_color_numformat(VkFormat format,
1756 const struct vk_format_description *desc,
1757 int first_non_void);
1758 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1759 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1760 uint32_t radv_translate_dbformat(VkFormat format);
1761 uint32_t radv_translate_tex_dataformat(VkFormat format,
1762 const struct vk_format_description *desc,
1763 int first_non_void);
1764 uint32_t radv_translate_tex_numformat(VkFormat format,
1765 const struct vk_format_description *desc,
1766 int first_non_void);
1767 bool radv_format_pack_clear_color(VkFormat format,
1768 uint32_t clear_vals[2],
1769 VkClearColorValue *value);
1770 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1771 bool radv_dcc_formats_compatible(VkFormat format1,
1772 VkFormat format2);
1773 bool radv_device_supports_etc(struct radv_physical_device *physical_device);
1774
1775 struct radv_image_plane {
1776 VkFormat format;
1777 struct radeon_surf surface;
1778 uint64_t offset;
1779 };
1780
1781 struct radv_image {
1782 struct vk_object_base base;
1783 VkImageType type;
1784 /* The original VkFormat provided by the client. This may not match any
1785 * of the actual surface formats.
1786 */
1787 VkFormat vk_format;
1788 VkImageAspectFlags aspects;
1789 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1790 struct ac_surf_info info;
1791 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1792 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1793
1794 VkDeviceSize size;
1795 uint32_t alignment;
1796
1797 unsigned queue_family_mask;
1798 bool exclusive;
1799 bool shareable;
1800
1801 /* Set when bound */
1802 struct radeon_winsys_bo *bo;
1803 VkDeviceSize offset;
1804 bool tc_compatible_htile;
1805 bool tc_compatible_cmask;
1806
1807 uint64_t clear_value_offset;
1808 uint64_t fce_pred_offset;
1809 uint64_t dcc_pred_offset;
1810
1811 /*
1812 * Metadata for the TC-compat zrange workaround. If the 32-bit value
1813 * stored at this offset is UINT_MAX, the driver will emit
1814 * DB_Z_INFO.ZRANGE_PRECISION=0, otherwise it will skip the
1815 * SET_CONTEXT_REG packet.
1816 */
1817 uint64_t tc_compat_zrange_offset;
1818
1819 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1820 VkDeviceMemory owned_memory;
1821
1822 unsigned plane_count;
1823 struct radv_image_plane planes[0];
1824 };
1825
1826 /* Whether the image has a htile that is known consistent with the contents of
1827 * the image and is allowed to be in compressed form.
1828 *
1829 * If this is false reads that don't use the htile should be able to return
1830 * correct results.
1831 */
1832 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1833 VkImageLayout layout,
1834 bool in_render_loop,
1835 unsigned queue_mask);
1836
1837 bool radv_layout_can_fast_clear(const struct radv_image *image,
1838 VkImageLayout layout,
1839 bool in_render_loop,
1840 unsigned queue_mask);
1841
1842 bool radv_layout_dcc_compressed(const struct radv_device *device,
1843 const struct radv_image *image,
1844 VkImageLayout layout,
1845 bool in_render_loop,
1846 unsigned queue_mask);
1847
1848 /**
1849 * Return whether the image has CMASK metadata for color surfaces.
1850 */
1851 static inline bool
1852 radv_image_has_cmask(const struct radv_image *image)
1853 {
1854 return image->planes[0].surface.cmask_offset;
1855 }
1856
1857 /**
1858 * Return whether the image has FMASK metadata for color surfaces.
1859 */
1860 static inline bool
1861 radv_image_has_fmask(const struct radv_image *image)
1862 {
1863 return image->planes[0].surface.fmask_offset;
1864 }
1865
1866 /**
1867 * Return whether the image has DCC metadata for color surfaces.
1868 */
1869 static inline bool
1870 radv_image_has_dcc(const struct radv_image *image)
1871 {
1872 return image->planes[0].surface.dcc_size;
1873 }
1874
1875 /**
1876 * Return whether the image is TC-compatible CMASK.
1877 */
1878 static inline bool
1879 radv_image_is_tc_compat_cmask(const struct radv_image *image)
1880 {
1881 return radv_image_has_fmask(image) && image->tc_compatible_cmask;
1882 }
1883
1884 /**
1885 * Return whether DCC metadata is enabled for a level.
1886 */
1887 static inline bool
1888 radv_dcc_enabled(const struct radv_image *image, unsigned level)
1889 {
1890 return radv_image_has_dcc(image) &&
1891 level < image->planes[0].surface.num_dcc_levels;
1892 }
1893
1894 /**
1895 * Return whether the image has CB metadata.
1896 */
1897 static inline bool
1898 radv_image_has_CB_metadata(const struct radv_image *image)
1899 {
1900 return radv_image_has_cmask(image) ||
1901 radv_image_has_fmask(image) ||
1902 radv_image_has_dcc(image);
1903 }
1904
1905 /**
1906 * Return whether the image has HTILE metadata for depth surfaces.
1907 */
1908 static inline bool
1909 radv_image_has_htile(const struct radv_image *image)
1910 {
1911 return image->planes[0].surface.htile_size;
1912 }
1913
1914 /**
1915 * Return whether HTILE metadata is enabled for a level.
1916 */
1917 static inline bool
1918 radv_htile_enabled(const struct radv_image *image, unsigned level)
1919 {
1920 return radv_image_has_htile(image) && level == 0;
1921 }
1922
1923 /**
1924 * Return whether the image is TC-compatible HTILE.
1925 */
1926 static inline bool
1927 radv_image_is_tc_compat_htile(const struct radv_image *image)
1928 {
1929 return radv_image_has_htile(image) && image->tc_compatible_htile;
1930 }
1931
1932 static inline uint64_t
1933 radv_image_get_fast_clear_va(const struct radv_image *image,
1934 uint32_t base_level)
1935 {
1936 uint64_t va = radv_buffer_get_va(image->bo);
1937 va += image->offset + image->clear_value_offset + base_level * 8;
1938 return va;
1939 }
1940
1941 static inline uint64_t
1942 radv_image_get_fce_pred_va(const struct radv_image *image,
1943 uint32_t base_level)
1944 {
1945 uint64_t va = radv_buffer_get_va(image->bo);
1946 va += image->offset + image->fce_pred_offset + base_level * 8;
1947 return va;
1948 }
1949
1950 static inline uint64_t
1951 radv_image_get_dcc_pred_va(const struct radv_image *image,
1952 uint32_t base_level)
1953 {
1954 uint64_t va = radv_buffer_get_va(image->bo);
1955 va += image->offset + image->dcc_pred_offset + base_level * 8;
1956 return va;
1957 }
1958
1959 static inline uint64_t
1960 radv_get_tc_compat_zrange_va(const struct radv_image *image,
1961 uint32_t base_level)
1962 {
1963 uint64_t va = radv_buffer_get_va(image->bo);
1964 va += image->offset + image->tc_compat_zrange_offset + base_level * 4;
1965 return va;
1966 }
1967
1968 static inline uint64_t
1969 radv_get_ds_clear_value_va(const struct radv_image *image,
1970 uint32_t base_level)
1971 {
1972 uint64_t va = radv_buffer_get_va(image->bo);
1973 va += image->offset + image->clear_value_offset + base_level * 8;
1974 return va;
1975 }
1976
1977 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1978
1979 static inline uint32_t
1980 radv_get_layerCount(const struct radv_image *image,
1981 const VkImageSubresourceRange *range)
1982 {
1983 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1984 image->info.array_size - range->baseArrayLayer : range->layerCount;
1985 }
1986
1987 static inline uint32_t
1988 radv_get_levelCount(const struct radv_image *image,
1989 const VkImageSubresourceRange *range)
1990 {
1991 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1992 image->info.levels - range->baseMipLevel : range->levelCount;
1993 }
1994
1995 struct radeon_bo_metadata;
1996 void
1997 radv_init_metadata(struct radv_device *device,
1998 struct radv_image *image,
1999 struct radeon_bo_metadata *metadata);
2000
2001 void
2002 radv_image_override_offset_stride(struct radv_device *device,
2003 struct radv_image *image,
2004 uint64_t offset, uint32_t stride);
2005
2006 union radv_descriptor {
2007 struct {
2008 uint32_t plane0_descriptor[8];
2009 uint32_t fmask_descriptor[8];
2010 };
2011 struct {
2012 uint32_t plane_descriptors[3][8];
2013 };
2014 };
2015
2016 struct radv_image_view {
2017 struct vk_object_base base;
2018 struct radv_image *image; /**< VkImageViewCreateInfo::image */
2019 struct radeon_winsys_bo *bo;
2020
2021 VkImageViewType type;
2022 VkImageAspectFlags aspect_mask;
2023 VkFormat vk_format;
2024 unsigned plane_id;
2025 bool multiple_planes;
2026 uint32_t base_layer;
2027 uint32_t layer_count;
2028 uint32_t base_mip;
2029 uint32_t level_count;
2030 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
2031
2032 union radv_descriptor descriptor;
2033
2034 /* Descriptor for use as a storage image as opposed to a sampled image.
2035 * This has a few differences for cube maps (e.g. type).
2036 */
2037 union radv_descriptor storage_descriptor;
2038 };
2039
2040 struct radv_image_create_info {
2041 const VkImageCreateInfo *vk_info;
2042 bool scanout;
2043 bool no_metadata_planes;
2044 const struct radeon_bo_metadata *bo_metadata;
2045 };
2046
2047 VkResult
2048 radv_image_create_layout(struct radv_device *device,
2049 struct radv_image_create_info create_info,
2050 struct radv_image *image);
2051
2052 VkResult radv_image_create(VkDevice _device,
2053 const struct radv_image_create_info *info,
2054 const VkAllocationCallbacks* alloc,
2055 VkImage *pImage);
2056
2057 bool vi_alpha_is_on_msb(struct radv_device *device, VkFormat format);
2058
2059 VkResult
2060 radv_image_from_gralloc(VkDevice device_h,
2061 const VkImageCreateInfo *base_info,
2062 const VkNativeBufferANDROID *gralloc_info,
2063 const VkAllocationCallbacks *alloc,
2064 VkImage *out_image_h);
2065 uint64_t
2066 radv_ahb_usage_from_vk_usage(const VkImageCreateFlags vk_create,
2067 const VkImageUsageFlags vk_usage);
2068 VkResult
2069 radv_import_ahb_memory(struct radv_device *device,
2070 struct radv_device_memory *mem,
2071 unsigned priority,
2072 const VkImportAndroidHardwareBufferInfoANDROID *info);
2073 VkResult
2074 radv_create_ahb_memory(struct radv_device *device,
2075 struct radv_device_memory *mem,
2076 unsigned priority,
2077 const VkMemoryAllocateInfo *pAllocateInfo);
2078
2079 VkFormat
2080 radv_select_android_external_format(const void *next, VkFormat default_format);
2081
2082 bool radv_android_gralloc_supports_format(VkFormat format, VkImageUsageFlagBits usage);
2083
2084 struct radv_image_view_extra_create_info {
2085 bool disable_compression;
2086 };
2087
2088 void radv_image_view_init(struct radv_image_view *view,
2089 struct radv_device *device,
2090 const VkImageViewCreateInfo *pCreateInfo,
2091 const struct radv_image_view_extra_create_info* extra_create_info);
2092
2093 VkFormat radv_get_aspect_format(struct radv_image *image, VkImageAspectFlags mask);
2094
2095 struct radv_sampler_ycbcr_conversion {
2096 struct vk_object_base base;
2097 VkFormat format;
2098 VkSamplerYcbcrModelConversion ycbcr_model;
2099 VkSamplerYcbcrRange ycbcr_range;
2100 VkComponentMapping components;
2101 VkChromaLocation chroma_offsets[2];
2102 VkFilter chroma_filter;
2103 };
2104
2105 struct radv_buffer_view {
2106 struct vk_object_base base;
2107 struct radeon_winsys_bo *bo;
2108 VkFormat vk_format;
2109 uint64_t range; /**< VkBufferViewCreateInfo::range */
2110 uint32_t state[4];
2111 };
2112 void radv_buffer_view_init(struct radv_buffer_view *view,
2113 struct radv_device *device,
2114 const VkBufferViewCreateInfo* pCreateInfo);
2115
2116 static inline struct VkExtent3D
2117 radv_sanitize_image_extent(const VkImageType imageType,
2118 const struct VkExtent3D imageExtent)
2119 {
2120 switch (imageType) {
2121 case VK_IMAGE_TYPE_1D:
2122 return (VkExtent3D) { imageExtent.width, 1, 1 };
2123 case VK_IMAGE_TYPE_2D:
2124 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
2125 case VK_IMAGE_TYPE_3D:
2126 return imageExtent;
2127 default:
2128 unreachable("invalid image type");
2129 }
2130 }
2131
2132 static inline struct VkOffset3D
2133 radv_sanitize_image_offset(const VkImageType imageType,
2134 const struct VkOffset3D imageOffset)
2135 {
2136 switch (imageType) {
2137 case VK_IMAGE_TYPE_1D:
2138 return (VkOffset3D) { imageOffset.x, 0, 0 };
2139 case VK_IMAGE_TYPE_2D:
2140 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
2141 case VK_IMAGE_TYPE_3D:
2142 return imageOffset;
2143 default:
2144 unreachable("invalid image type");
2145 }
2146 }
2147
2148 static inline bool
2149 radv_image_extent_compare(const struct radv_image *image,
2150 const VkExtent3D *extent)
2151 {
2152 if (extent->width != image->info.width ||
2153 extent->height != image->info.height ||
2154 extent->depth != image->info.depth)
2155 return false;
2156 return true;
2157 }
2158
2159 struct radv_sampler {
2160 struct vk_object_base base;
2161 uint32_t state[4];
2162 struct radv_sampler_ycbcr_conversion *ycbcr_sampler;
2163 uint32_t border_color_slot;
2164 };
2165
2166 struct radv_framebuffer {
2167 struct vk_object_base base;
2168 uint32_t width;
2169 uint32_t height;
2170 uint32_t layers;
2171
2172 uint32_t attachment_count;
2173 struct radv_image_view *attachments[0];
2174 };
2175
2176 struct radv_subpass_barrier {
2177 VkPipelineStageFlags src_stage_mask;
2178 VkAccessFlags src_access_mask;
2179 VkAccessFlags dst_access_mask;
2180 };
2181
2182 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2183 const struct radv_subpass_barrier *barrier);
2184
2185 struct radv_subpass_attachment {
2186 uint32_t attachment;
2187 VkImageLayout layout;
2188 VkImageLayout stencil_layout;
2189 bool in_render_loop;
2190 };
2191
2192 struct radv_subpass {
2193 uint32_t attachment_count;
2194 struct radv_subpass_attachment * attachments;
2195
2196 uint32_t input_count;
2197 uint32_t color_count;
2198 struct radv_subpass_attachment * input_attachments;
2199 struct radv_subpass_attachment * color_attachments;
2200 struct radv_subpass_attachment * resolve_attachments;
2201 struct radv_subpass_attachment * depth_stencil_attachment;
2202 struct radv_subpass_attachment * ds_resolve_attachment;
2203 VkResolveModeFlagBits depth_resolve_mode;
2204 VkResolveModeFlagBits stencil_resolve_mode;
2205
2206 /** Subpass has at least one color resolve attachment */
2207 bool has_color_resolve;
2208
2209 /** Subpass has at least one color attachment */
2210 bool has_color_att;
2211
2212 struct radv_subpass_barrier start_barrier;
2213
2214 uint32_t view_mask;
2215
2216 VkSampleCountFlagBits color_sample_count;
2217 VkSampleCountFlagBits depth_sample_count;
2218 VkSampleCountFlagBits max_sample_count;
2219 };
2220
2221 uint32_t
2222 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer);
2223
2224 struct radv_render_pass_attachment {
2225 VkFormat format;
2226 uint32_t samples;
2227 VkAttachmentLoadOp load_op;
2228 VkAttachmentLoadOp stencil_load_op;
2229 VkImageLayout initial_layout;
2230 VkImageLayout final_layout;
2231 VkImageLayout stencil_initial_layout;
2232 VkImageLayout stencil_final_layout;
2233
2234 /* The subpass id in which the attachment will be used first/last. */
2235 uint32_t first_subpass_idx;
2236 uint32_t last_subpass_idx;
2237 };
2238
2239 struct radv_render_pass {
2240 struct vk_object_base base;
2241 uint32_t attachment_count;
2242 uint32_t subpass_count;
2243 struct radv_subpass_attachment * subpass_attachments;
2244 struct radv_render_pass_attachment * attachments;
2245 struct radv_subpass_barrier end_barrier;
2246 struct radv_subpass subpasses[0];
2247 };
2248
2249 VkResult radv_device_init_meta(struct radv_device *device);
2250 void radv_device_finish_meta(struct radv_device *device);
2251
2252 struct radv_query_pool {
2253 struct vk_object_base base;
2254 struct radeon_winsys_bo *bo;
2255 uint32_t stride;
2256 uint32_t availability_offset;
2257 uint64_t size;
2258 char *ptr;
2259 VkQueryType type;
2260 uint32_t pipeline_stats_mask;
2261 };
2262
2263 typedef enum {
2264 RADV_SEMAPHORE_NONE,
2265 RADV_SEMAPHORE_WINSYS,
2266 RADV_SEMAPHORE_SYNCOBJ,
2267 RADV_SEMAPHORE_TIMELINE,
2268 } radv_semaphore_kind;
2269
2270 struct radv_deferred_queue_submission;
2271
2272 struct radv_timeline_waiter {
2273 struct list_head list;
2274 struct radv_deferred_queue_submission *submission;
2275 uint64_t value;
2276 };
2277
2278 struct radv_timeline_point {
2279 struct list_head list;
2280
2281 uint64_t value;
2282 uint32_t syncobj;
2283
2284 /* Separate from the list to accomodate CPU wait being async, as well
2285 * as prevent point deletion during submission. */
2286 unsigned wait_count;
2287 };
2288
2289 struct radv_timeline {
2290 /* Using a pthread mutex to be compatible with condition variables. */
2291 pthread_mutex_t mutex;
2292
2293 uint64_t highest_signaled;
2294 uint64_t highest_submitted;
2295
2296 struct list_head points;
2297
2298 /* Keep free points on hand so we do not have to recreate syncobjs all
2299 * the time. */
2300 struct list_head free_points;
2301
2302 /* Submissions that are deferred waiting for a specific value to be
2303 * submitted. */
2304 struct list_head waiters;
2305 };
2306
2307 struct radv_semaphore_part {
2308 radv_semaphore_kind kind;
2309 union {
2310 uint32_t syncobj;
2311 struct radeon_winsys_sem *ws_sem;
2312 struct radv_timeline timeline;
2313 };
2314 };
2315
2316 struct radv_semaphore {
2317 struct vk_object_base base;
2318 struct radv_semaphore_part permanent;
2319 struct radv_semaphore_part temporary;
2320 };
2321
2322 bool radv_queue_internal_submit(struct radv_queue *queue,
2323 struct radeon_cmdbuf *cs);
2324
2325 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2326 VkPipelineBindPoint bind_point,
2327 struct radv_descriptor_set *set,
2328 unsigned idx);
2329
2330 void
2331 radv_update_descriptor_sets(struct radv_device *device,
2332 struct radv_cmd_buffer *cmd_buffer,
2333 VkDescriptorSet overrideSet,
2334 uint32_t descriptorWriteCount,
2335 const VkWriteDescriptorSet *pDescriptorWrites,
2336 uint32_t descriptorCopyCount,
2337 const VkCopyDescriptorSet *pDescriptorCopies);
2338
2339 void
2340 radv_update_descriptor_set_with_template(struct radv_device *device,
2341 struct radv_cmd_buffer *cmd_buffer,
2342 struct radv_descriptor_set *set,
2343 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
2344 const void *pData);
2345
2346 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2347 VkPipelineBindPoint pipelineBindPoint,
2348 VkPipelineLayout _layout,
2349 uint32_t set,
2350 uint32_t descriptorWriteCount,
2351 const VkWriteDescriptorSet *pDescriptorWrites);
2352
2353 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
2354 struct radv_image *image,
2355 const VkImageSubresourceRange *range, uint32_t value);
2356
2357 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
2358 struct radv_image *image,
2359 const VkImageSubresourceRange *range);
2360
2361 struct radv_fence {
2362 struct vk_object_base base;
2363 struct radeon_winsys_fence *fence;
2364 struct wsi_fence *fence_wsi;
2365
2366 uint32_t syncobj;
2367 uint32_t temp_syncobj;
2368 };
2369
2370 /* radv_nir_to_llvm.c */
2371 struct radv_shader_args;
2372
2373 void llvm_compile_shader(struct radv_device *device,
2374 unsigned shader_count,
2375 struct nir_shader *const *shaders,
2376 struct radv_shader_binary **binary,
2377 struct radv_shader_args *args);
2378
2379 unsigned radv_nir_get_max_workgroup_size(enum chip_class chip_class,
2380 gl_shader_stage stage,
2381 const struct nir_shader *nir);
2382
2383 /* radv_shader_info.h */
2384 struct radv_shader_info;
2385 struct radv_shader_variant_key;
2386
2387 void radv_nir_shader_info_pass(const struct nir_shader *nir,
2388 const struct radv_pipeline_layout *layout,
2389 const struct radv_shader_variant_key *key,
2390 struct radv_shader_info *info,
2391 bool use_llvm);
2392
2393 void radv_nir_shader_info_init(struct radv_shader_info *info);
2394
2395 /* radv_sqtt.c */
2396 struct radv_thread_trace_info {
2397 uint32_t cur_offset;
2398 uint32_t trace_status;
2399 union {
2400 uint32_t gfx9_write_counter;
2401 uint32_t gfx10_dropped_cntr;
2402 };
2403 };
2404
2405 struct radv_thread_trace_se {
2406 struct radv_thread_trace_info info;
2407 void *data_ptr;
2408 uint32_t shader_engine;
2409 uint32_t compute_unit;
2410 };
2411
2412 struct radv_thread_trace {
2413 uint32_t num_traces;
2414 struct radv_thread_trace_se traces[4];
2415 };
2416
2417 bool radv_thread_trace_init(struct radv_device *device);
2418 void radv_thread_trace_finish(struct radv_device *device);
2419 bool radv_begin_thread_trace(struct radv_queue *queue);
2420 bool radv_end_thread_trace(struct radv_queue *queue);
2421 bool radv_get_thread_trace(struct radv_queue *queue,
2422 struct radv_thread_trace *thread_trace);
2423 void radv_emit_thread_trace_userdata(struct radeon_cmdbuf *cs,
2424 const void *data, uint32_t num_dwords);
2425
2426 /* radv_rgp.c */
2427 int radv_dump_thread_trace(struct radv_device *device,
2428 const struct radv_thread_trace *trace);
2429
2430 /* radv_sqtt_layer_.c */
2431 struct radv_barrier_data {
2432 union {
2433 struct {
2434 uint16_t depth_stencil_expand : 1;
2435 uint16_t htile_hiz_range_expand : 1;
2436 uint16_t depth_stencil_resummarize : 1;
2437 uint16_t dcc_decompress : 1;
2438 uint16_t fmask_decompress : 1;
2439 uint16_t fast_clear_eliminate : 1;
2440 uint16_t fmask_color_expand : 1;
2441 uint16_t init_mask_ram : 1;
2442 uint16_t reserved : 8;
2443 };
2444 uint16_t all;
2445 } layout_transitions;
2446 };
2447
2448 /**
2449 * Value for the reason field of an RGP barrier start marker originating from
2450 * the Vulkan client (does not include PAL-defined values). (Table 15)
2451 */
2452 enum rgp_barrier_reason {
2453 RGP_BARRIER_UNKNOWN_REASON = 0xFFFFFFFF,
2454
2455 /* External app-generated barrier reasons, i.e. API synchronization
2456 * commands Range of valid values: [0x00000001 ... 0x7FFFFFFF].
2457 */
2458 RGP_BARRIER_EXTERNAL_CMD_PIPELINE_BARRIER = 0x00000001,
2459 RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC = 0x00000002,
2460 RGP_BARRIER_EXTERNAL_CMD_WAIT_EVENTS = 0x00000003,
2461
2462 /* Internal barrier reasons, i.e. implicit synchronization inserted by
2463 * the Vulkan driver Range of valid values: [0xC0000000 ... 0xFFFFFFFE].
2464 */
2465 RGP_BARRIER_INTERNAL_BASE = 0xC0000000,
2466 RGP_BARRIER_INTERNAL_PRE_RESET_QUERY_POOL_SYNC = RGP_BARRIER_INTERNAL_BASE + 0,
2467 RGP_BARRIER_INTERNAL_POST_RESET_QUERY_POOL_SYNC = RGP_BARRIER_INTERNAL_BASE + 1,
2468 RGP_BARRIER_INTERNAL_GPU_EVENT_RECYCLE_STALL = RGP_BARRIER_INTERNAL_BASE + 2,
2469 RGP_BARRIER_INTERNAL_PRE_COPY_QUERY_POOL_RESULTS_SYNC = RGP_BARRIER_INTERNAL_BASE + 3
2470 };
2471
2472 void radv_describe_begin_cmd_buffer(struct radv_cmd_buffer *cmd_buffer);
2473 void radv_describe_end_cmd_buffer(struct radv_cmd_buffer *cmd_buffer);
2474 void radv_describe_draw(struct radv_cmd_buffer *cmd_buffer);
2475 void radv_describe_dispatch(struct radv_cmd_buffer *cmd_buffer, int x, int y, int z);
2476 void radv_describe_begin_render_pass_clear(struct radv_cmd_buffer *cmd_buffer,
2477 VkImageAspectFlagBits aspects);
2478 void radv_describe_end_render_pass_clear(struct radv_cmd_buffer *cmd_buffer);
2479 void radv_describe_barrier_start(struct radv_cmd_buffer *cmd_buffer,
2480 enum rgp_barrier_reason reason);
2481 void radv_describe_barrier_end(struct radv_cmd_buffer *cmd_buffer);
2482 void radv_describe_layout_transition(struct radv_cmd_buffer *cmd_buffer,
2483 const struct radv_barrier_data *barrier);
2484
2485 struct radeon_winsys_sem;
2486
2487 uint64_t radv_get_current_time(void);
2488
2489 static inline uint32_t
2490 si_conv_gl_prim_to_vertices(unsigned gl_prim)
2491 {
2492 switch (gl_prim) {
2493 case 0: /* GL_POINTS */
2494 return 1;
2495 case 1: /* GL_LINES */
2496 case 3: /* GL_LINE_STRIP */
2497 return 2;
2498 case 4: /* GL_TRIANGLES */
2499 case 5: /* GL_TRIANGLE_STRIP */
2500 return 3;
2501 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
2502 return 4;
2503 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
2504 return 6;
2505 case 7: /* GL_QUADS */
2506 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
2507 default:
2508 assert(0);
2509 return 0;
2510 }
2511 }
2512
2513 void radv_cmd_buffer_begin_render_pass(struct radv_cmd_buffer *cmd_buffer,
2514 const VkRenderPassBeginInfo *pRenderPassBegin);
2515 void radv_cmd_buffer_end_render_pass(struct radv_cmd_buffer *cmd_buffer);
2516
2517 static inline uint32_t si_translate_prim(unsigned topology)
2518 {
2519 switch (topology) {
2520 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
2521 return V_008958_DI_PT_POINTLIST;
2522 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
2523 return V_008958_DI_PT_LINELIST;
2524 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
2525 return V_008958_DI_PT_LINESTRIP;
2526 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
2527 return V_008958_DI_PT_TRILIST;
2528 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
2529 return V_008958_DI_PT_TRISTRIP;
2530 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
2531 return V_008958_DI_PT_TRIFAN;
2532 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
2533 return V_008958_DI_PT_LINELIST_ADJ;
2534 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
2535 return V_008958_DI_PT_LINESTRIP_ADJ;
2536 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
2537 return V_008958_DI_PT_TRILIST_ADJ;
2538 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
2539 return V_008958_DI_PT_TRISTRIP_ADJ;
2540 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
2541 return V_008958_DI_PT_PATCH;
2542 default:
2543 assert(0);
2544 return 0;
2545 }
2546 }
2547
2548 static inline uint32_t si_translate_stencil_op(enum VkStencilOp op)
2549 {
2550 switch (op) {
2551 case VK_STENCIL_OP_KEEP:
2552 return V_02842C_STENCIL_KEEP;
2553 case VK_STENCIL_OP_ZERO:
2554 return V_02842C_STENCIL_ZERO;
2555 case VK_STENCIL_OP_REPLACE:
2556 return V_02842C_STENCIL_REPLACE_TEST;
2557 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
2558 return V_02842C_STENCIL_ADD_CLAMP;
2559 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
2560 return V_02842C_STENCIL_SUB_CLAMP;
2561 case VK_STENCIL_OP_INVERT:
2562 return V_02842C_STENCIL_INVERT;
2563 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
2564 return V_02842C_STENCIL_ADD_WRAP;
2565 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
2566 return V_02842C_STENCIL_SUB_WRAP;
2567 default:
2568 return 0;
2569 }
2570 }
2571
2572 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
2573 \
2574 static inline struct __radv_type * \
2575 __radv_type ## _from_handle(__VkType _handle) \
2576 { \
2577 return (struct __radv_type *) _handle; \
2578 } \
2579 \
2580 static inline __VkType \
2581 __radv_type ## _to_handle(struct __radv_type *_obj) \
2582 { \
2583 return (__VkType) _obj; \
2584 }
2585
2586 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
2587 \
2588 static inline struct __radv_type * \
2589 __radv_type ## _from_handle(__VkType _handle) \
2590 { \
2591 return (struct __radv_type *)(uintptr_t) _handle; \
2592 } \
2593 \
2594 static inline __VkType \
2595 __radv_type ## _to_handle(struct __radv_type *_obj) \
2596 { \
2597 return (__VkType)(uintptr_t) _obj; \
2598 }
2599
2600 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
2601 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
2602
2603 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
2604 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
2605 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
2606 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
2607 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
2608
2609 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
2610 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
2611 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
2612 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
2613 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
2614 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
2615 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplate)
2616 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
2617 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
2618 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
2619 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
2620 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
2621 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
2622 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
2623 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
2624 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
2625 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
2626 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
2627 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
2628 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler_ycbcr_conversion, VkSamplerYcbcrConversion)
2629 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
2630 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
2631
2632 #endif /* RADV_PRIVATE_H */