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radv: add support for dynamic vertex input binding stride
[mesa.git] / src / amd / vulkan / radv_private.h
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
30
31 #include <stdlib.h>
32 #include <stdio.h>
33 #include <stdbool.h>
34 #include <pthread.h>
35 #include <assert.h>
36 #include <stdint.h>
37 #include <string.h>
38 #ifdef HAVE_VALGRIND
39 #include <valgrind.h>
40 #include <memcheck.h>
41 #define VG(x) x
42 #else
43 #define VG(x) ((void)0)
44 #endif
45
46 #include "c11/threads.h"
47 #include <amdgpu.h>
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "util/xmlconfig.h"
52 #include "vk_alloc.h"
53 #include "vk_debug_report.h"
54 #include "vk_object.h"
55
56 #include "radv_radeon_winsys.h"
57 #include "ac_binary.h"
58 #include "ac_nir_to_llvm.h"
59 #include "ac_gpu_info.h"
60 #include "ac_surface.h"
61 #include "ac_llvm_build.h"
62 #include "ac_llvm_util.h"
63 #include "radv_constants.h"
64 #include "radv_descriptor_set.h"
65 #include "radv_extensions.h"
66 #include "sid.h"
67
68 /* Pre-declarations needed for WSI entrypoints */
69 struct wl_surface;
70 struct wl_display;
71 typedef struct xcb_connection_t xcb_connection_t;
72 typedef uint32_t xcb_visualid_t;
73 typedef uint32_t xcb_window_t;
74
75 #include <vulkan/vulkan.h>
76 #include <vulkan/vulkan_intel.h>
77 #include <vulkan/vulkan_android.h>
78 #include <vulkan/vk_icd.h>
79 #include <vulkan/vk_android_native_buffer.h>
80
81 #include "radv_entrypoints.h"
82
83 #include "wsi_common.h"
84 #include "wsi_common_display.h"
85
86 /* Helper to determine if we should compile
87 * any of the Android AHB support.
88 *
89 * To actually enable the ext we also need
90 * the necessary kernel support.
91 */
92 #if defined(ANDROID) && ANDROID_API_LEVEL >= 26
93 #define RADV_SUPPORT_ANDROID_HARDWARE_BUFFER 1
94 #else
95 #define RADV_SUPPORT_ANDROID_HARDWARE_BUFFER 0
96 #endif
97
98 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
99
100 static inline uint32_t
101 align_u32(uint32_t v, uint32_t a)
102 {
103 assert(a != 0 && a == (a & -a));
104 return (v + a - 1) & ~(a - 1);
105 }
106
107 static inline uint32_t
108 align_u32_npot(uint32_t v, uint32_t a)
109 {
110 return (v + a - 1) / a * a;
111 }
112
113 static inline uint64_t
114 align_u64(uint64_t v, uint64_t a)
115 {
116 assert(a != 0 && a == (a & -a));
117 return (v + a - 1) & ~(a - 1);
118 }
119
120 static inline int32_t
121 align_i32(int32_t v, int32_t a)
122 {
123 assert(a != 0 && a == (a & -a));
124 return (v + a - 1) & ~(a - 1);
125 }
126
127 /** Alignment must be a power of 2. */
128 static inline bool
129 radv_is_aligned(uintmax_t n, uintmax_t a)
130 {
131 assert(a == (a & -a));
132 return (n & (a - 1)) == 0;
133 }
134
135 static inline uint32_t
136 round_up_u32(uint32_t v, uint32_t a)
137 {
138 return (v + a - 1) / a;
139 }
140
141 static inline uint64_t
142 round_up_u64(uint64_t v, uint64_t a)
143 {
144 return (v + a - 1) / a;
145 }
146
147 static inline uint32_t
148 radv_minify(uint32_t n, uint32_t levels)
149 {
150 if (unlikely(n == 0))
151 return 0;
152 else
153 return MAX2(n >> levels, 1);
154 }
155 static inline float
156 radv_clamp_f(float f, float min, float max)
157 {
158 assert(min < max);
159
160 if (f > max)
161 return max;
162 else if (f < min)
163 return min;
164 else
165 return f;
166 }
167
168 static inline bool
169 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
170 {
171 if (*inout_mask & clear_mask) {
172 *inout_mask &= ~clear_mask;
173 return true;
174 } else {
175 return false;
176 }
177 }
178
179 #define for_each_bit(b, dword) \
180 for (uint32_t __dword = (dword); \
181 (b) = __builtin_ffs(__dword) - 1, __dword; \
182 __dword &= ~(1 << (b)))
183
184 #define typed_memcpy(dest, src, count) ({ \
185 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
186 memcpy((dest), (src), (count) * sizeof(*(src))); \
187 })
188
189 /* Whenever we generate an error, pass it through this function. Useful for
190 * debugging, where we can break on it. Only call at error site, not when
191 * propagating errors. Might be useful to plug in a stack trace here.
192 */
193
194 struct radv_image_view;
195 struct radv_instance;
196
197 VkResult __vk_errorf(struct radv_instance *instance, VkResult error, const char *file, int line, const char *format, ...);
198
199 #define vk_error(instance, error) __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
200 #define vk_errorf(instance, error, format, ...) __vk_errorf(instance, error, __FILE__, __LINE__, format, ## __VA_ARGS__);
201
202 void __radv_finishme(const char *file, int line, const char *format, ...)
203 radv_printflike(3, 4);
204 void radv_loge(const char *format, ...) radv_printflike(1, 2);
205 void radv_loge_v(const char *format, va_list va);
206 void radv_logi(const char *format, ...) radv_printflike(1, 2);
207 void radv_logi_v(const char *format, va_list va);
208
209 /**
210 * Print a FINISHME message, including its source location.
211 */
212 #define radv_finishme(format, ...) \
213 do { \
214 static bool reported = false; \
215 if (!reported) { \
216 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
217 reported = true; \
218 } \
219 } while (0)
220
221 /* A non-fatal assert. Useful for debugging. */
222 #ifdef DEBUG
223 #define radv_assert(x) ({ \
224 if (unlikely(!(x))) \
225 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
226 })
227 #else
228 #define radv_assert(x) do {} while(0)
229 #endif
230
231 #define stub_return(v) \
232 do { \
233 radv_finishme("stub %s", __func__); \
234 return (v); \
235 } while (0)
236
237 #define stub() \
238 do { \
239 radv_finishme("stub %s", __func__); \
240 return; \
241 } while (0)
242
243 int radv_get_instance_entrypoint_index(const char *name);
244 int radv_get_device_entrypoint_index(const char *name);
245 int radv_get_physical_device_entrypoint_index(const char *name);
246
247 const char *radv_get_instance_entry_name(int index);
248 const char *radv_get_physical_device_entry_name(int index);
249 const char *radv_get_device_entry_name(int index);
250
251 bool radv_instance_entrypoint_is_enabled(int index, uint32_t core_version,
252 const struct radv_instance_extension_table *instance);
253 bool radv_physical_device_entrypoint_is_enabled(int index, uint32_t core_version,
254 const struct radv_instance_extension_table *instance);
255 bool radv_device_entrypoint_is_enabled(int index, uint32_t core_version,
256 const struct radv_instance_extension_table *instance,
257 const struct radv_device_extension_table *device);
258
259 void *radv_lookup_entrypoint(const char *name);
260
261 struct radv_physical_device {
262 VK_LOADER_DATA _loader_data;
263
264 /* Link in radv_instance::physical_devices */
265 struct list_head link;
266
267 struct radv_instance * instance;
268
269 struct radeon_winsys *ws;
270 struct radeon_info rad_info;
271 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
272 uint8_t driver_uuid[VK_UUID_SIZE];
273 uint8_t device_uuid[VK_UUID_SIZE];
274 uint8_t cache_uuid[VK_UUID_SIZE];
275
276 int local_fd;
277 int master_fd;
278 struct wsi_device wsi_device;
279
280 bool out_of_order_rast_allowed;
281
282 /* Whether DCC should be enabled for MSAA textures. */
283 bool dcc_msaa_allowed;
284
285 /* Whether to enable NGG. */
286 bool use_ngg;
287
288 /* Whether to enable NGG GS. */
289 bool use_ngg_gs;
290
291 /* Whether to enable NGG streamout. */
292 bool use_ngg_streamout;
293
294 /* Number of threads per wave. */
295 uint8_t ps_wave_size;
296 uint8_t cs_wave_size;
297 uint8_t ge_wave_size;
298
299 /* Whether to use the LLVM compiler backend */
300 bool use_llvm;
301
302 /* This is the drivers on-disk cache used as a fallback as opposed to
303 * the pipeline cache defined by apps.
304 */
305 struct disk_cache * disk_cache;
306
307 VkPhysicalDeviceMemoryProperties memory_properties;
308 enum radeon_bo_domain memory_domains[VK_MAX_MEMORY_TYPES];
309 enum radeon_bo_flag memory_flags[VK_MAX_MEMORY_TYPES];
310
311 drmPciBusInfo bus_info;
312
313 struct radv_device_extension_table supported_extensions;
314 };
315
316 struct radv_instance {
317 struct vk_object_base base;
318
319 VkAllocationCallbacks alloc;
320
321 uint32_t apiVersion;
322
323 char * engineName;
324 uint32_t engineVersion;
325
326 uint64_t debug_flags;
327 uint64_t perftest_flags;
328
329 struct vk_debug_report_instance debug_report_callbacks;
330
331 struct radv_instance_extension_table enabled_extensions;
332 struct radv_instance_dispatch_table dispatch;
333 struct radv_physical_device_dispatch_table physical_device_dispatch;
334 struct radv_device_dispatch_table device_dispatch;
335
336 bool physical_devices_enumerated;
337 struct list_head physical_devices;
338
339 struct driOptionCache dri_options;
340 struct driOptionCache available_dri_options;
341
342 /**
343 * Workarounds for game bugs.
344 */
345 bool enable_mrt_output_nan_fixup;
346 };
347
348 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
349 void radv_finish_wsi(struct radv_physical_device *physical_device);
350
351 bool radv_instance_extension_supported(const char *name);
352 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
353 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
354 const char *name);
355
356 struct cache_entry;
357
358 struct radv_pipeline_cache {
359 struct vk_object_base base;
360 struct radv_device * device;
361 pthread_mutex_t mutex;
362 VkPipelineCacheCreateFlags flags;
363
364 uint32_t total_size;
365 uint32_t table_size;
366 uint32_t kernel_count;
367 struct cache_entry ** hash_table;
368 bool modified;
369
370 VkAllocationCallbacks alloc;
371 };
372
373 struct radv_pipeline_key {
374 uint32_t instance_rate_inputs;
375 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
376 uint8_t vertex_attribute_formats[MAX_VERTEX_ATTRIBS];
377 uint32_t vertex_attribute_bindings[MAX_VERTEX_ATTRIBS];
378 uint32_t vertex_attribute_offsets[MAX_VERTEX_ATTRIBS];
379 uint32_t vertex_attribute_strides[MAX_VERTEX_ATTRIBS];
380 uint64_t vertex_alpha_adjust;
381 uint32_t vertex_post_shuffle;
382 unsigned tess_input_vertices;
383 uint32_t col_format;
384 uint32_t is_int8;
385 uint32_t is_int10;
386 uint8_t log2_ps_iter_samples;
387 uint8_t num_samples;
388 bool is_dual_src;
389 uint32_t has_multiview_view_index : 1;
390 uint32_t optimisations_disabled : 1;
391 uint8_t topology;
392
393 /* Non-zero if a required subgroup size is specified via
394 * VK_EXT_subgroup_size_control.
395 */
396 uint8_t compute_subgroup_size;
397 };
398
399 struct radv_shader_binary;
400 struct radv_shader_variant;
401
402 void
403 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
404 struct radv_device *device);
405 void
406 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
407 bool
408 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
409 const void *data, size_t size);
410
411 bool
412 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
413 struct radv_pipeline_cache *cache,
414 const unsigned char *sha1,
415 struct radv_shader_variant **variants,
416 bool *found_in_application_cache);
417
418 void
419 radv_pipeline_cache_insert_shaders(struct radv_device *device,
420 struct radv_pipeline_cache *cache,
421 const unsigned char *sha1,
422 struct radv_shader_variant **variants,
423 struct radv_shader_binary *const *binaries);
424
425 enum radv_blit_ds_layout {
426 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
427 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
428 RADV_BLIT_DS_LAYOUT_COUNT,
429 };
430
431 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
432 {
433 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
434 }
435
436 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
437 {
438 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
439 }
440
441 enum radv_meta_dst_layout {
442 RADV_META_DST_LAYOUT_GENERAL,
443 RADV_META_DST_LAYOUT_OPTIMAL,
444 RADV_META_DST_LAYOUT_COUNT,
445 };
446
447 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
448 {
449 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
450 }
451
452 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
453 {
454 return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
455 }
456
457 struct radv_meta_state {
458 VkAllocationCallbacks alloc;
459
460 struct radv_pipeline_cache cache;
461
462 /*
463 * For on-demand pipeline creation, makes sure that
464 * only one thread tries to build a pipeline at the same time.
465 */
466 mtx_t mtx;
467
468 /**
469 * Use array element `i` for images with `2^i` samples.
470 */
471 struct {
472 VkRenderPass render_pass[NUM_META_FS_KEYS];
473 VkPipeline color_pipelines[NUM_META_FS_KEYS];
474
475 VkRenderPass depthstencil_rp;
476 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
477 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
478 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
479
480 VkPipeline depth_only_unrestricted_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
481 VkPipeline stencil_only_unrestricted_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
482 VkPipeline depthstencil_unrestricted_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
483 } clear[MAX_SAMPLES_LOG2];
484
485 VkPipelineLayout clear_color_p_layout;
486 VkPipelineLayout clear_depth_p_layout;
487 VkPipelineLayout clear_depth_unrestricted_p_layout;
488
489 /* Optimized compute fast HTILE clear for stencil or depth only. */
490 VkPipeline clear_htile_mask_pipeline;
491 VkPipelineLayout clear_htile_mask_p_layout;
492 VkDescriptorSetLayout clear_htile_mask_ds_layout;
493
494 struct {
495 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
496
497 /** Pipeline that blits from a 1D image. */
498 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
499
500 /** Pipeline that blits from a 2D image. */
501 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
502
503 /** Pipeline that blits from a 3D image. */
504 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
505
506 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
507 VkPipeline depth_only_1d_pipeline;
508 VkPipeline depth_only_2d_pipeline;
509 VkPipeline depth_only_3d_pipeline;
510
511 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
512 VkPipeline stencil_only_1d_pipeline;
513 VkPipeline stencil_only_2d_pipeline;
514 VkPipeline stencil_only_3d_pipeline;
515 VkPipelineLayout pipeline_layout;
516 VkDescriptorSetLayout ds_layout;
517 } blit;
518
519 struct {
520 VkPipelineLayout p_layouts[5];
521 VkDescriptorSetLayout ds_layouts[5];
522 VkPipeline pipelines[5][NUM_META_FS_KEYS];
523
524 VkPipeline depth_only_pipeline[5];
525
526 VkPipeline stencil_only_pipeline[5];
527 } blit2d[MAX_SAMPLES_LOG2];
528
529 VkRenderPass blit2d_render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
530 VkRenderPass blit2d_depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
531 VkRenderPass blit2d_stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
532
533 struct {
534 VkPipelineLayout img_p_layout;
535 VkDescriptorSetLayout img_ds_layout;
536 VkPipeline pipeline;
537 VkPipeline pipeline_3d;
538 } itob;
539 struct {
540 VkPipelineLayout img_p_layout;
541 VkDescriptorSetLayout img_ds_layout;
542 VkPipeline pipeline;
543 VkPipeline pipeline_3d;
544 } btoi;
545 struct {
546 VkPipelineLayout img_p_layout;
547 VkDescriptorSetLayout img_ds_layout;
548 VkPipeline pipeline;
549 } btoi_r32g32b32;
550 struct {
551 VkPipelineLayout img_p_layout;
552 VkDescriptorSetLayout img_ds_layout;
553 VkPipeline pipeline;
554 VkPipeline pipeline_3d;
555 } itoi;
556 struct {
557 VkPipelineLayout img_p_layout;
558 VkDescriptorSetLayout img_ds_layout;
559 VkPipeline pipeline;
560 } itoi_r32g32b32;
561 struct {
562 VkPipelineLayout img_p_layout;
563 VkDescriptorSetLayout img_ds_layout;
564 VkPipeline pipeline;
565 VkPipeline pipeline_3d;
566 } cleari;
567 struct {
568 VkPipelineLayout img_p_layout;
569 VkDescriptorSetLayout img_ds_layout;
570 VkPipeline pipeline;
571 } cleari_r32g32b32;
572
573 struct {
574 VkPipelineLayout p_layout;
575 VkPipeline pipeline[NUM_META_FS_KEYS];
576 VkRenderPass pass[NUM_META_FS_KEYS];
577 } resolve;
578
579 struct {
580 VkDescriptorSetLayout ds_layout;
581 VkPipelineLayout p_layout;
582 struct {
583 VkPipeline pipeline;
584 VkPipeline i_pipeline;
585 VkPipeline srgb_pipeline;
586 } rc[MAX_SAMPLES_LOG2];
587
588 VkPipeline depth_zero_pipeline;
589 struct {
590 VkPipeline average_pipeline;
591 VkPipeline max_pipeline;
592 VkPipeline min_pipeline;
593 } depth[MAX_SAMPLES_LOG2];
594
595 VkPipeline stencil_zero_pipeline;
596 struct {
597 VkPipeline max_pipeline;
598 VkPipeline min_pipeline;
599 } stencil[MAX_SAMPLES_LOG2];
600 } resolve_compute;
601
602 struct {
603 VkDescriptorSetLayout ds_layout;
604 VkPipelineLayout p_layout;
605
606 struct {
607 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
608 VkPipeline pipeline[NUM_META_FS_KEYS];
609 } rc[MAX_SAMPLES_LOG2];
610
611 VkRenderPass depth_render_pass;
612 VkPipeline depth_zero_pipeline;
613 struct {
614 VkPipeline average_pipeline;
615 VkPipeline max_pipeline;
616 VkPipeline min_pipeline;
617 } depth[MAX_SAMPLES_LOG2];
618
619 VkRenderPass stencil_render_pass;
620 VkPipeline stencil_zero_pipeline;
621 struct {
622 VkPipeline max_pipeline;
623 VkPipeline min_pipeline;
624 } stencil[MAX_SAMPLES_LOG2];
625 } resolve_fragment;
626
627 struct {
628 VkPipelineLayout p_layout;
629 VkPipeline decompress_pipeline[NUM_DEPTH_DECOMPRESS_PIPELINES];
630 VkPipeline resummarize_pipeline;
631 VkRenderPass pass;
632 } depth_decomp[MAX_SAMPLES_LOG2];
633
634 struct {
635 VkPipelineLayout p_layout;
636 VkPipeline cmask_eliminate_pipeline;
637 VkPipeline fmask_decompress_pipeline;
638 VkPipeline dcc_decompress_pipeline;
639 VkRenderPass pass;
640
641 VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
642 VkPipelineLayout dcc_decompress_compute_p_layout;
643 VkPipeline dcc_decompress_compute_pipeline;
644 } fast_clear_flush;
645
646 struct {
647 VkPipelineLayout fill_p_layout;
648 VkPipelineLayout copy_p_layout;
649 VkDescriptorSetLayout fill_ds_layout;
650 VkDescriptorSetLayout copy_ds_layout;
651 VkPipeline fill_pipeline;
652 VkPipeline copy_pipeline;
653 } buffer;
654
655 struct {
656 VkDescriptorSetLayout ds_layout;
657 VkPipelineLayout p_layout;
658 VkPipeline occlusion_query_pipeline;
659 VkPipeline pipeline_statistics_query_pipeline;
660 VkPipeline tfb_query_pipeline;
661 VkPipeline timestamp_query_pipeline;
662 } query;
663
664 struct {
665 VkDescriptorSetLayout ds_layout;
666 VkPipelineLayout p_layout;
667 VkPipeline pipeline[MAX_SAMPLES_LOG2];
668 } fmask_expand;
669 };
670
671 /* queue types */
672 #define RADV_QUEUE_GENERAL 0
673 #define RADV_QUEUE_COMPUTE 1
674 #define RADV_QUEUE_TRANSFER 2
675
676 #define RADV_MAX_QUEUE_FAMILIES 3
677
678 enum ring_type radv_queue_family_to_ring(int f);
679
680 struct radv_queue {
681 VK_LOADER_DATA _loader_data;
682 struct radv_device * device;
683 struct radeon_winsys_ctx *hw_ctx;
684 enum radeon_ctx_priority priority;
685 uint32_t queue_family_index;
686 int queue_idx;
687 VkDeviceQueueCreateFlags flags;
688
689 uint32_t scratch_size_per_wave;
690 uint32_t scratch_waves;
691 uint32_t compute_scratch_size_per_wave;
692 uint32_t compute_scratch_waves;
693 uint32_t esgs_ring_size;
694 uint32_t gsvs_ring_size;
695 bool has_tess_rings;
696 bool has_gds;
697 bool has_gds_oa;
698 bool has_sample_positions;
699
700 struct radeon_winsys_bo *scratch_bo;
701 struct radeon_winsys_bo *descriptor_bo;
702 struct radeon_winsys_bo *compute_scratch_bo;
703 struct radeon_winsys_bo *esgs_ring_bo;
704 struct radeon_winsys_bo *gsvs_ring_bo;
705 struct radeon_winsys_bo *tess_rings_bo;
706 struct radeon_winsys_bo *gds_bo;
707 struct radeon_winsys_bo *gds_oa_bo;
708 struct radeon_cmdbuf *initial_preamble_cs;
709 struct radeon_cmdbuf *initial_full_flush_preamble_cs;
710 struct radeon_cmdbuf *continue_preamble_cs;
711
712 struct list_head pending_submissions;
713 pthread_mutex_t pending_mutex;
714 };
715
716 struct radv_bo_list {
717 struct radv_winsys_bo_list list;
718 unsigned capacity;
719 pthread_mutex_t mutex;
720 };
721
722 VkResult radv_bo_list_add(struct radv_device *device,
723 struct radeon_winsys_bo *bo);
724 void radv_bo_list_remove(struct radv_device *device,
725 struct radeon_winsys_bo *bo);
726
727 #define RADV_BORDER_COLOR_COUNT 4096
728 #define RADV_BORDER_COLOR_BUFFER_SIZE (sizeof(VkClearColorValue) * RADV_BORDER_COLOR_COUNT)
729
730 struct radv_device_border_color_data {
731 bool used[RADV_BORDER_COLOR_COUNT];
732
733 struct radeon_winsys_bo *bo;
734 VkClearColorValue *colors_gpu_ptr;
735
736 /* Mutex is required to guarantee vkCreateSampler thread safety
737 * given that we are writing to a buffer and checking color occupation */
738 pthread_mutex_t mutex;
739 };
740
741 struct radv_device {
742 struct vk_device vk;
743
744 struct radv_instance * instance;
745 struct radeon_winsys *ws;
746
747 struct radv_meta_state meta_state;
748
749 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
750 int queue_count[RADV_MAX_QUEUE_FAMILIES];
751 struct radeon_cmdbuf *empty_cs[RADV_MAX_QUEUE_FAMILIES];
752
753 bool always_use_syncobj;
754 bool pbb_allowed;
755 bool dfsm_allowed;
756 uint32_t tess_offchip_block_dw_size;
757 uint32_t scratch_waves;
758 uint32_t dispatch_initiator;
759
760 uint32_t gs_table_depth;
761
762 /* MSAA sample locations.
763 * The first index is the sample index.
764 * The second index is the coordinate: X, Y. */
765 float sample_locations_1x[1][2];
766 float sample_locations_2x[2][2];
767 float sample_locations_4x[4][2];
768 float sample_locations_8x[8][2];
769
770 /* GFX7 and later */
771 uint32_t gfx_init_size_dw;
772 struct radeon_winsys_bo *gfx_init;
773
774 struct radeon_winsys_bo *trace_bo;
775 uint32_t *trace_id_ptr;
776
777 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
778 bool keep_shader_info;
779
780 struct radv_physical_device *physical_device;
781
782 /* Backup in-memory cache to be used if the app doesn't provide one */
783 struct radv_pipeline_cache * mem_cache;
784
785 /*
786 * use different counters so MSAA MRTs get consecutive surface indices,
787 * even if MASK is allocated in between.
788 */
789 uint32_t image_mrt_offset_counter;
790 uint32_t fmask_mrt_offset_counter;
791 struct list_head shader_slabs;
792 mtx_t shader_slab_mutex;
793
794 /* For detecting VM faults reported by dmesg. */
795 uint64_t dmesg_timestamp;
796
797 struct radv_device_extension_table enabled_extensions;
798 struct radv_device_dispatch_table dispatch;
799
800 /* Whether the app has enabled the robustBufferAccess feature. */
801 bool robust_buffer_access;
802
803 /* Whether the driver uses a global BO list. */
804 bool use_global_bo_list;
805
806 struct radv_bo_list bo_list;
807
808 /* Whether anisotropy is forced with RADV_TEX_ANISO (-1 is disabled). */
809 int force_aniso;
810
811 struct radv_device_border_color_data border_color_data;
812
813 /* Condition variable for legacy timelines, to notify waiters when a
814 * new point gets submitted. */
815 pthread_cond_t timeline_cond;
816
817 /* Thread trace. */
818 struct radeon_cmdbuf *thread_trace_start_cs[2];
819 struct radeon_cmdbuf *thread_trace_stop_cs[2];
820 struct radeon_winsys_bo *thread_trace_bo;
821 void *thread_trace_ptr;
822 uint32_t thread_trace_buffer_size;
823 int thread_trace_start_frame;
824
825 /* Overallocation. */
826 bool overallocation_disallowed;
827 uint64_t allocated_memory_size[VK_MAX_MEMORY_HEAPS];
828 mtx_t overallocation_mutex;
829 };
830
831 struct radv_device_memory {
832 struct vk_object_base base;
833 struct radeon_winsys_bo *bo;
834 /* for dedicated allocations */
835 struct radv_image *image;
836 struct radv_buffer *buffer;
837 uint32_t heap_index;
838 uint64_t alloc_size;
839 void * map;
840 void * user_ptr;
841
842 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
843 struct AHardwareBuffer * android_hardware_buffer;
844 #endif
845 };
846
847
848 struct radv_descriptor_range {
849 uint64_t va;
850 uint32_t size;
851 };
852
853 struct radv_descriptor_set {
854 struct vk_object_base base;
855 const struct radv_descriptor_set_layout *layout;
856 uint32_t size;
857 uint32_t buffer_count;
858
859 struct radeon_winsys_bo *bo;
860 uint64_t va;
861 uint32_t *mapped_ptr;
862 struct radv_descriptor_range *dynamic_descriptors;
863
864 struct radeon_winsys_bo *descriptors[0];
865 };
866
867 struct radv_push_descriptor_set
868 {
869 struct radv_descriptor_set set;
870 uint32_t capacity;
871 };
872
873 struct radv_descriptor_pool_entry {
874 uint32_t offset;
875 uint32_t size;
876 struct radv_descriptor_set *set;
877 };
878
879 struct radv_descriptor_pool {
880 struct vk_object_base base;
881 struct radeon_winsys_bo *bo;
882 uint8_t *mapped_ptr;
883 uint64_t current_offset;
884 uint64_t size;
885
886 uint8_t *host_memory_base;
887 uint8_t *host_memory_ptr;
888 uint8_t *host_memory_end;
889
890 uint32_t entry_count;
891 uint32_t max_entry_count;
892 struct radv_descriptor_pool_entry entries[0];
893 };
894
895 struct radv_descriptor_update_template_entry {
896 VkDescriptorType descriptor_type;
897
898 /* The number of descriptors to update */
899 uint32_t descriptor_count;
900
901 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
902 uint32_t dst_offset;
903
904 /* In dwords. Not valid/used for dynamic descriptors */
905 uint32_t dst_stride;
906
907 uint32_t buffer_offset;
908
909 /* Only valid for combined image samplers and samplers */
910 uint8_t has_sampler;
911 uint8_t sampler_offset;
912
913 /* In bytes */
914 size_t src_offset;
915 size_t src_stride;
916
917 /* For push descriptors */
918 const uint32_t *immutable_samplers;
919 };
920
921 struct radv_descriptor_update_template {
922 struct vk_object_base base;
923 uint32_t entry_count;
924 VkPipelineBindPoint bind_point;
925 struct radv_descriptor_update_template_entry entry[0];
926 };
927
928 struct radv_buffer {
929 struct vk_object_base base;
930 VkDeviceSize size;
931
932 VkBufferUsageFlags usage;
933 VkBufferCreateFlags flags;
934
935 /* Set when bound */
936 struct radeon_winsys_bo * bo;
937 VkDeviceSize offset;
938
939 bool shareable;
940 };
941
942 enum radv_dynamic_state_bits {
943 RADV_DYNAMIC_VIEWPORT = 1 << 0,
944 RADV_DYNAMIC_SCISSOR = 1 << 1,
945 RADV_DYNAMIC_LINE_WIDTH = 1 << 2,
946 RADV_DYNAMIC_DEPTH_BIAS = 1 << 3,
947 RADV_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
948 RADV_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
949 RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
950 RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
951 RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
952 RADV_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
953 RADV_DYNAMIC_SAMPLE_LOCATIONS = 1 << 10,
954 RADV_DYNAMIC_LINE_STIPPLE = 1 << 11,
955 RADV_DYNAMIC_CULL_MODE = 1 << 12,
956 RADV_DYNAMIC_FRONT_FACE = 1 << 13,
957 RADV_DYNAMIC_PRIMITIVE_TOPOLOGY = 1 << 14,
958 RADV_DYNAMIC_DEPTH_TEST_ENABLE = 1 << 15,
959 RADV_DYNAMIC_DEPTH_WRITE_ENABLE = 1 << 16,
960 RADV_DYNAMIC_DEPTH_COMPARE_OP = 1 << 17,
961 RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE = 1 << 18,
962 RADV_DYNAMIC_STENCIL_TEST_ENABLE = 1 << 19,
963 RADV_DYNAMIC_STENCIL_OP = 1 << 20,
964 RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE = 1 << 21,
965 RADV_DYNAMIC_ALL = (1 << 22) - 1,
966 };
967
968 enum radv_cmd_dirty_bits {
969 /* Keep the dynamic state dirty bits in sync with
970 * enum radv_dynamic_state_bits */
971 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0,
972 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1,
973 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2,
974 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3,
975 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
976 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
977 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
978 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
979 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
980 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
981 RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS = 1 << 10,
982 RADV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE = 1 << 11,
983 RADV_CMD_DIRTY_DYNAMIC_CULL_MODE = 1 << 12,
984 RADV_CMD_DIRTY_DYNAMIC_FRONT_FACE = 1 << 13,
985 RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY = 1 << 14,
986 RADV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE = 1 << 15,
987 RADV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE = 1 << 16,
988 RADV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP = 1 << 17,
989 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE = 1 << 18,
990 RADV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE = 1 << 19,
991 RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP = 1 << 20,
992 RADV_CMD_DIRTY_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE = 1 << 21,
993 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 22) - 1,
994 RADV_CMD_DIRTY_PIPELINE = 1 << 22,
995 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 23,
996 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 24,
997 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 25,
998 RADV_CMD_DIRTY_STREAMOUT_BUFFER = 1 << 26,
999 };
1000
1001 enum radv_cmd_flush_bits {
1002 /* Instruction cache. */
1003 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
1004 /* Scalar L1 cache. */
1005 RADV_CMD_FLAG_INV_SCACHE = 1 << 1,
1006 /* Vector L1 cache. */
1007 RADV_CMD_FLAG_INV_VCACHE = 1 << 2,
1008 /* L2 cache + L2 metadata cache writeback & invalidate.
1009 * GFX6-8: Used by shaders only. GFX9-10: Used by everything. */
1010 RADV_CMD_FLAG_INV_L2 = 1 << 3,
1011 /* L2 writeback (write dirty L2 lines to memory for non-L2 clients).
1012 * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8.
1013 * GFX6-7 will do complete invalidation, because the writeback is unsupported. */
1014 RADV_CMD_FLAG_WB_L2 = 1 << 4,
1015 /* Framebuffer caches */
1016 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
1017 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
1018 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
1019 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
1020 /* Engine synchronization. */
1021 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
1022 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
1023 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
1024 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
1025 /* Pipeline query controls. */
1026 RADV_CMD_FLAG_START_PIPELINE_STATS = 1 << 13,
1027 RADV_CMD_FLAG_STOP_PIPELINE_STATS = 1 << 14,
1028 RADV_CMD_FLAG_VGT_STREAMOUT_SYNC = 1 << 15,
1029
1030 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1031 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1032 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1033 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
1034 };
1035
1036 struct radv_vertex_binding {
1037 struct radv_buffer * buffer;
1038 VkDeviceSize offset;
1039 VkDeviceSize size;
1040 VkDeviceSize stride;
1041 };
1042
1043 struct radv_streamout_binding {
1044 struct radv_buffer *buffer;
1045 VkDeviceSize offset;
1046 VkDeviceSize size;
1047 };
1048
1049 struct radv_streamout_state {
1050 /* Mask of bound streamout buffers. */
1051 uint8_t enabled_mask;
1052
1053 /* External state that comes from the last vertex stage, it must be
1054 * set explicitely when binding a new graphics pipeline.
1055 */
1056 uint16_t stride_in_dw[MAX_SO_BUFFERS];
1057 uint32_t enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
1058
1059 /* State of VGT_STRMOUT_BUFFER_(CONFIG|END) */
1060 uint32_t hw_enabled_mask;
1061
1062 /* State of VGT_STRMOUT_(CONFIG|EN) */
1063 bool streamout_enabled;
1064 };
1065
1066 struct radv_viewport_state {
1067 uint32_t count;
1068 VkViewport viewports[MAX_VIEWPORTS];
1069 };
1070
1071 struct radv_scissor_state {
1072 uint32_t count;
1073 VkRect2D scissors[MAX_SCISSORS];
1074 };
1075
1076 struct radv_discard_rectangle_state {
1077 uint32_t count;
1078 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
1079 };
1080
1081 struct radv_sample_locations_state {
1082 VkSampleCountFlagBits per_pixel;
1083 VkExtent2D grid_size;
1084 uint32_t count;
1085 VkSampleLocationEXT locations[MAX_SAMPLE_LOCATIONS];
1086 };
1087
1088 struct radv_dynamic_state {
1089 /**
1090 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
1091 * Defines the set of saved dynamic state.
1092 */
1093 uint32_t mask;
1094
1095 struct radv_viewport_state viewport;
1096
1097 struct radv_scissor_state scissor;
1098
1099 float line_width;
1100
1101 struct {
1102 float bias;
1103 float clamp;
1104 float slope;
1105 } depth_bias;
1106
1107 float blend_constants[4];
1108
1109 struct {
1110 float min;
1111 float max;
1112 } depth_bounds;
1113
1114 struct {
1115 uint32_t front;
1116 uint32_t back;
1117 } stencil_compare_mask;
1118
1119 struct {
1120 uint32_t front;
1121 uint32_t back;
1122 } stencil_write_mask;
1123
1124 struct {
1125 struct {
1126 VkStencilOp fail_op;
1127 VkStencilOp pass_op;
1128 VkStencilOp depth_fail_op;
1129 VkCompareOp compare_op;
1130 } front;
1131
1132 struct {
1133 VkStencilOp fail_op;
1134 VkStencilOp pass_op;
1135 VkStencilOp depth_fail_op;
1136 VkCompareOp compare_op;
1137 } back;
1138 } stencil_op;
1139
1140 struct {
1141 uint32_t front;
1142 uint32_t back;
1143 } stencil_reference;
1144
1145 struct radv_discard_rectangle_state discard_rectangle;
1146
1147 struct radv_sample_locations_state sample_location;
1148
1149 struct {
1150 uint32_t factor;
1151 uint16_t pattern;
1152 } line_stipple;
1153
1154 VkCullModeFlags cull_mode;
1155 VkFrontFace front_face;
1156 unsigned primitive_topology;
1157
1158 bool depth_test_enable;
1159 bool depth_write_enable;
1160 VkCompareOp depth_compare_op;
1161 bool depth_bounds_test_enable;
1162 bool stencil_test_enable;
1163 };
1164
1165 extern const struct radv_dynamic_state default_dynamic_state;
1166
1167 const char *
1168 radv_get_debug_option_name(int id);
1169
1170 const char *
1171 radv_get_perftest_option_name(int id);
1172
1173 struct radv_color_buffer_info {
1174 uint64_t cb_color_base;
1175 uint64_t cb_color_cmask;
1176 uint64_t cb_color_fmask;
1177 uint64_t cb_dcc_base;
1178 uint32_t cb_color_slice;
1179 uint32_t cb_color_view;
1180 uint32_t cb_color_info;
1181 uint32_t cb_color_attrib;
1182 uint32_t cb_color_attrib2; /* GFX9 and later */
1183 uint32_t cb_color_attrib3; /* GFX10 and later */
1184 uint32_t cb_dcc_control;
1185 uint32_t cb_color_cmask_slice;
1186 uint32_t cb_color_fmask_slice;
1187 union {
1188 uint32_t cb_color_pitch; // GFX6-GFX8
1189 uint32_t cb_mrt_epitch; // GFX9+
1190 };
1191 };
1192
1193 struct radv_ds_buffer_info {
1194 uint64_t db_z_read_base;
1195 uint64_t db_stencil_read_base;
1196 uint64_t db_z_write_base;
1197 uint64_t db_stencil_write_base;
1198 uint64_t db_htile_data_base;
1199 uint32_t db_depth_info;
1200 uint32_t db_z_info;
1201 uint32_t db_stencil_info;
1202 uint32_t db_depth_view;
1203 uint32_t db_depth_size;
1204 uint32_t db_depth_slice;
1205 uint32_t db_htile_surface;
1206 uint32_t pa_su_poly_offset_db_fmt_cntl;
1207 uint32_t db_z_info2; /* GFX9 only */
1208 uint32_t db_stencil_info2; /* GFX9 only */
1209 float offset_scale;
1210 };
1211
1212 void
1213 radv_initialise_color_surface(struct radv_device *device,
1214 struct radv_color_buffer_info *cb,
1215 struct radv_image_view *iview);
1216 void
1217 radv_initialise_ds_surface(struct radv_device *device,
1218 struct radv_ds_buffer_info *ds,
1219 struct radv_image_view *iview);
1220
1221 /**
1222 * Attachment state when recording a renderpass instance.
1223 *
1224 * The clear value is valid only if there exists a pending clear.
1225 */
1226 struct radv_attachment_state {
1227 VkImageAspectFlags pending_clear_aspects;
1228 uint32_t cleared_views;
1229 VkClearValue clear_value;
1230 VkImageLayout current_layout;
1231 VkImageLayout current_stencil_layout;
1232 bool current_in_render_loop;
1233 struct radv_sample_locations_state sample_location;
1234
1235 union {
1236 struct radv_color_buffer_info cb;
1237 struct radv_ds_buffer_info ds;
1238 };
1239 struct radv_image_view *iview;
1240 };
1241
1242 struct radv_descriptor_state {
1243 struct radv_descriptor_set *sets[MAX_SETS];
1244 uint32_t dirty;
1245 uint32_t valid;
1246 struct radv_push_descriptor_set push_set;
1247 bool push_dirty;
1248 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
1249 };
1250
1251 struct radv_subpass_sample_locs_state {
1252 uint32_t subpass_idx;
1253 struct radv_sample_locations_state sample_location;
1254 };
1255
1256 struct radv_cmd_state {
1257 /* Vertex descriptors */
1258 uint64_t vb_va;
1259 unsigned vb_size;
1260
1261 bool predicating;
1262 uint32_t dirty;
1263
1264 uint32_t prefetch_L2_mask;
1265
1266 struct radv_pipeline * pipeline;
1267 struct radv_pipeline * emitted_pipeline;
1268 struct radv_pipeline * compute_pipeline;
1269 struct radv_pipeline * emitted_compute_pipeline;
1270 struct radv_framebuffer * framebuffer;
1271 struct radv_render_pass * pass;
1272 const struct radv_subpass * subpass;
1273 struct radv_dynamic_state dynamic;
1274 struct radv_attachment_state * attachments;
1275 struct radv_streamout_state streamout;
1276 VkRect2D render_area;
1277
1278 uint32_t num_subpass_sample_locs;
1279 struct radv_subpass_sample_locs_state * subpass_sample_locs;
1280
1281 /* Index buffer */
1282 struct radv_buffer *index_buffer;
1283 uint64_t index_offset;
1284 uint32_t index_type;
1285 uint32_t max_index_count;
1286 uint64_t index_va;
1287 int32_t last_index_type;
1288
1289 int32_t last_primitive_reset_en;
1290 uint32_t last_primitive_reset_index;
1291 enum radv_cmd_flush_bits flush_bits;
1292 unsigned active_occlusion_queries;
1293 bool perfect_occlusion_queries_enabled;
1294 unsigned active_pipeline_queries;
1295 unsigned active_pipeline_gds_queries;
1296 float offset_scale;
1297 uint32_t trace_id;
1298 uint32_t last_ia_multi_vgt_param;
1299
1300 uint32_t last_num_instances;
1301 uint32_t last_first_instance;
1302 uint32_t last_vertex_offset;
1303
1304 uint32_t last_sx_ps_downconvert;
1305 uint32_t last_sx_blend_opt_epsilon;
1306 uint32_t last_sx_blend_opt_control;
1307
1308 /* Whether CP DMA is busy/idle. */
1309 bool dma_is_busy;
1310
1311 /* Conditional rendering info. */
1312 int predication_type; /* -1: disabled, 0: normal, 1: inverted */
1313 uint64_t predication_va;
1314
1315 /* Inheritance info. */
1316 VkQueryPipelineStatisticFlags inherited_pipeline_statistics;
1317
1318 bool context_roll_without_scissor_emitted;
1319
1320 /* SQTT related state. */
1321 uint32_t current_event_type;
1322 uint32_t num_events;
1323 uint32_t num_layout_transitions;
1324 };
1325
1326 struct radv_cmd_pool {
1327 struct vk_object_base base;
1328 VkAllocationCallbacks alloc;
1329 struct list_head cmd_buffers;
1330 struct list_head free_cmd_buffers;
1331 uint32_t queue_family_index;
1332 };
1333
1334 struct radv_cmd_buffer_upload {
1335 uint8_t *map;
1336 unsigned offset;
1337 uint64_t size;
1338 struct radeon_winsys_bo *upload_bo;
1339 struct list_head list;
1340 };
1341
1342 enum radv_cmd_buffer_status {
1343 RADV_CMD_BUFFER_STATUS_INVALID,
1344 RADV_CMD_BUFFER_STATUS_INITIAL,
1345 RADV_CMD_BUFFER_STATUS_RECORDING,
1346 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
1347 RADV_CMD_BUFFER_STATUS_PENDING,
1348 };
1349
1350 struct radv_cmd_buffer {
1351 struct vk_object_base base;
1352
1353 struct radv_device * device;
1354
1355 struct radv_cmd_pool * pool;
1356 struct list_head pool_link;
1357
1358 VkCommandBufferUsageFlags usage_flags;
1359 VkCommandBufferLevel level;
1360 enum radv_cmd_buffer_status status;
1361 struct radeon_cmdbuf *cs;
1362 struct radv_cmd_state state;
1363 struct radv_vertex_binding vertex_bindings[MAX_VBS];
1364 struct radv_streamout_binding streamout_bindings[MAX_SO_BUFFERS];
1365 uint32_t queue_family_index;
1366
1367 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
1368 VkShaderStageFlags push_constant_stages;
1369 struct radv_descriptor_set meta_push_descriptors;
1370
1371 struct radv_descriptor_state descriptors[MAX_BIND_POINTS];
1372
1373 struct radv_cmd_buffer_upload upload;
1374
1375 uint32_t scratch_size_per_wave_needed;
1376 uint32_t scratch_waves_wanted;
1377 uint32_t compute_scratch_size_per_wave_needed;
1378 uint32_t compute_scratch_waves_wanted;
1379 uint32_t esgs_ring_size_needed;
1380 uint32_t gsvs_ring_size_needed;
1381 bool tess_rings_needed;
1382 bool gds_needed; /* for GFX10 streamout and NGG GS queries */
1383 bool gds_oa_needed; /* for GFX10 streamout */
1384 bool sample_positions_needed;
1385
1386 VkResult record_result;
1387
1388 uint64_t gfx9_fence_va;
1389 uint32_t gfx9_fence_idx;
1390 uint64_t gfx9_eop_bug_va;
1391
1392 /**
1393 * Whether a query pool has been resetted and we have to flush caches.
1394 */
1395 bool pending_reset_query;
1396
1397 /**
1398 * Bitmask of pending active query flushes.
1399 */
1400 enum radv_cmd_flush_bits active_query_flush_bits;
1401 };
1402
1403 struct radv_image;
1404 struct radv_image_view;
1405
1406 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
1407
1408 void si_emit_graphics(struct radv_device *device,
1409 struct radeon_cmdbuf *cs);
1410 void si_emit_compute(struct radv_physical_device *physical_device,
1411 struct radeon_cmdbuf *cs);
1412
1413 void cik_create_gfx_config(struct radv_device *device);
1414
1415 void si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
1416 int count, const VkViewport *viewports);
1417 void si_write_scissors(struct radeon_cmdbuf *cs, int first,
1418 int count, const VkRect2D *scissors,
1419 const VkViewport *viewports, bool can_use_guardband);
1420 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
1421 bool instanced_draw, bool indirect_draw,
1422 bool count_from_stream_output,
1423 uint32_t draw_vertex_count,
1424 unsigned topology);
1425 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
1426 enum chip_class chip_class,
1427 bool is_mec,
1428 unsigned event, unsigned event_flags,
1429 unsigned dst_sel, unsigned data_sel,
1430 uint64_t va,
1431 uint32_t new_fence,
1432 uint64_t gfx9_eop_bug_va);
1433
1434 void radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va,
1435 uint32_t ref, uint32_t mask);
1436 void si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
1437 enum chip_class chip_class,
1438 uint32_t *fence_ptr, uint64_t va,
1439 bool is_mec,
1440 enum radv_cmd_flush_bits flush_bits,
1441 uint64_t gfx9_eop_bug_va);
1442 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
1443 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
1444 bool inverted, uint64_t va);
1445 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1446 uint64_t src_va, uint64_t dest_va,
1447 uint64_t size);
1448 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1449 unsigned size);
1450 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1451 uint64_t size, unsigned value);
1452 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer);
1453
1454 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1455 bool
1456 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1457 unsigned size,
1458 unsigned alignment,
1459 unsigned *out_offset,
1460 void **ptr);
1461 void
1462 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1463 const struct radv_subpass *subpass);
1464 bool
1465 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1466 unsigned size, unsigned alignmnet,
1467 const void *data, unsigned *out_offset);
1468
1469 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1470 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1471 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1472 void radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer,
1473 VkImageAspectFlags aspects,
1474 VkResolveModeFlagBits resolve_mode);
1475 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1476 void radv_depth_stencil_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer,
1477 VkImageAspectFlags aspects,
1478 VkResolveModeFlagBits resolve_mode);
1479 void radv_emit_default_sample_locations(struct radeon_cmdbuf *cs, int nr_samples);
1480 unsigned radv_get_default_max_sample_dist(int log_samples);
1481 void radv_device_init_msaa(struct radv_device *device);
1482
1483 void radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1484 const struct radv_image_view *iview,
1485 VkClearDepthStencilValue ds_clear_value,
1486 VkImageAspectFlags aspects);
1487
1488 void radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1489 const struct radv_image_view *iview,
1490 int cb_idx,
1491 uint32_t color_values[2]);
1492
1493 void radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1494 struct radv_image *image,
1495 const VkImageSubresourceRange *range, bool value);
1496
1497 void radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1498 struct radv_image *image,
1499 const VkImageSubresourceRange *range, bool value);
1500
1501 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1502 struct radeon_winsys_bo *bo,
1503 uint64_t offset, uint64_t size, uint32_t value);
1504 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1505 bool radv_get_memory_fd(struct radv_device *device,
1506 struct radv_device_memory *memory,
1507 int *pFD);
1508
1509 static inline void
1510 radv_emit_shader_pointer_head(struct radeon_cmdbuf *cs,
1511 unsigned sh_offset, unsigned pointer_count,
1512 bool use_32bit_pointers)
1513 {
1514 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, pointer_count * (use_32bit_pointers ? 1 : 2), 0));
1515 radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2);
1516 }
1517
1518 static inline void
1519 radv_emit_shader_pointer_body(struct radv_device *device,
1520 struct radeon_cmdbuf *cs,
1521 uint64_t va, bool use_32bit_pointers)
1522 {
1523 radeon_emit(cs, va);
1524
1525 if (use_32bit_pointers) {
1526 assert(va == 0 ||
1527 (va >> 32) == device->physical_device->rad_info.address32_hi);
1528 } else {
1529 radeon_emit(cs, va >> 32);
1530 }
1531 }
1532
1533 static inline void
1534 radv_emit_shader_pointer(struct radv_device *device,
1535 struct radeon_cmdbuf *cs,
1536 uint32_t sh_offset, uint64_t va, bool global)
1537 {
1538 bool use_32bit_pointers = !global;
1539
1540 radv_emit_shader_pointer_head(cs, sh_offset, 1, use_32bit_pointers);
1541 radv_emit_shader_pointer_body(device, cs, va, use_32bit_pointers);
1542 }
1543
1544 static inline struct radv_descriptor_state *
1545 radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
1546 VkPipelineBindPoint bind_point)
1547 {
1548 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS ||
1549 bind_point == VK_PIPELINE_BIND_POINT_COMPUTE);
1550 return &cmd_buffer->descriptors[bind_point];
1551 }
1552
1553 /*
1554 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1555 *
1556 * Limitations: Can't call normal dispatch functions without binding or rebinding
1557 * the compute pipeline.
1558 */
1559 void radv_unaligned_dispatch(
1560 struct radv_cmd_buffer *cmd_buffer,
1561 uint32_t x,
1562 uint32_t y,
1563 uint32_t z);
1564
1565 struct radv_event {
1566 struct vk_object_base base;
1567 struct radeon_winsys_bo *bo;
1568 uint64_t *map;
1569 };
1570
1571 struct radv_shader_module;
1572
1573 #define RADV_HASH_SHADER_NO_NGG (1 << 0)
1574 #define RADV_HASH_SHADER_CS_WAVE32 (1 << 1)
1575 #define RADV_HASH_SHADER_PS_WAVE32 (1 << 2)
1576 #define RADV_HASH_SHADER_GE_WAVE32 (1 << 3)
1577 #define RADV_HASH_SHADER_LLVM (1 << 4)
1578
1579 void
1580 radv_hash_shaders(unsigned char *hash,
1581 const VkPipelineShaderStageCreateInfo **stages,
1582 const struct radv_pipeline_layout *layout,
1583 const struct radv_pipeline_key *key,
1584 uint32_t flags);
1585
1586 static inline gl_shader_stage
1587 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1588 {
1589 assert(__builtin_popcount(vk_stage) == 1);
1590 return ffs(vk_stage) - 1;
1591 }
1592
1593 static inline VkShaderStageFlagBits
1594 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1595 {
1596 return (1 << mesa_stage);
1597 }
1598
1599 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1600
1601 #define radv_foreach_stage(stage, stage_bits) \
1602 for (gl_shader_stage stage, \
1603 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1604 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1605 __tmp &= ~(1 << (stage)))
1606
1607 extern const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS];
1608 unsigned radv_format_meta_fs_key(VkFormat format);
1609
1610 struct radv_multisample_state {
1611 uint32_t db_eqaa;
1612 uint32_t pa_sc_line_cntl;
1613 uint32_t pa_sc_mode_cntl_0;
1614 uint32_t pa_sc_mode_cntl_1;
1615 uint32_t pa_sc_aa_config;
1616 uint32_t pa_sc_aa_mask[2];
1617 unsigned num_samples;
1618 };
1619
1620 struct radv_prim_vertex_count {
1621 uint8_t min;
1622 uint8_t incr;
1623 };
1624
1625 struct radv_vertex_elements_info {
1626 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1627 };
1628
1629 struct radv_ia_multi_vgt_param_helpers {
1630 uint32_t base;
1631 bool partial_es_wave;
1632 uint8_t primgroup_size;
1633 bool ia_switch_on_eoi;
1634 bool partial_vs_wave;
1635 };
1636
1637 struct radv_binning_state {
1638 uint32_t pa_sc_binner_cntl_0;
1639 uint32_t db_dfsm_control;
1640 };
1641
1642 #define SI_GS_PER_ES 128
1643
1644 struct radv_pipeline {
1645 struct vk_object_base base;
1646 struct radv_device * device;
1647 struct radv_dynamic_state dynamic_state;
1648
1649 struct radv_pipeline_layout * layout;
1650
1651 bool need_indirect_descriptor_sets;
1652 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1653 struct radv_shader_variant *gs_copy_shader;
1654 VkShaderStageFlags active_stages;
1655
1656 struct radeon_cmdbuf cs;
1657 uint32_t ctx_cs_hash;
1658 struct radeon_cmdbuf ctx_cs;
1659
1660 struct radv_vertex_elements_info vertex_elements;
1661
1662 uint32_t binding_stride[MAX_VBS];
1663 uint8_t num_vertex_bindings;
1664
1665 uint32_t user_data_0[MESA_SHADER_STAGES];
1666 union {
1667 struct {
1668 struct radv_multisample_state ms;
1669 struct radv_binning_state binning;
1670 uint32_t spi_baryc_cntl;
1671 bool prim_restart_enable;
1672 unsigned esgs_ring_size;
1673 unsigned gsvs_ring_size;
1674 uint32_t vtx_base_sgpr;
1675 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
1676 uint8_t vtx_emit_num;
1677 bool can_use_guardband;
1678 uint32_t needed_dynamic_state;
1679 bool disable_out_of_order_rast_for_occlusion;
1680 unsigned tess_patch_control_points;
1681 unsigned pa_su_sc_mode_cntl;
1682 unsigned db_depth_control;
1683 bool uses_dynamic_stride;
1684
1685 /* Used for rbplus */
1686 uint32_t col_format;
1687 uint32_t cb_target_mask;
1688 bool is_dual_src;
1689 } graphics;
1690 };
1691
1692 unsigned max_waves;
1693 unsigned scratch_bytes_per_wave;
1694
1695 /* Not NULL if graphics pipeline uses streamout. */
1696 struct radv_shader_variant *streamout_shader;
1697 };
1698
1699 static inline bool radv_pipeline_has_gs(const struct radv_pipeline *pipeline)
1700 {
1701 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1702 }
1703
1704 static inline bool radv_pipeline_has_tess(const struct radv_pipeline *pipeline)
1705 {
1706 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1707 }
1708
1709 bool radv_pipeline_has_ngg(const struct radv_pipeline *pipeline);
1710
1711 bool radv_pipeline_has_ngg_passthrough(const struct radv_pipeline *pipeline);
1712
1713 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline *pipeline);
1714
1715 struct radv_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1716 gl_shader_stage stage,
1717 int idx);
1718
1719 struct radv_shader_variant *radv_get_shader(struct radv_pipeline *pipeline,
1720 gl_shader_stage stage);
1721
1722 struct radv_graphics_pipeline_create_info {
1723 bool use_rectlist;
1724 bool db_depth_clear;
1725 bool db_stencil_clear;
1726 bool db_depth_disable_expclear;
1727 bool db_stencil_disable_expclear;
1728 bool depth_compress_disable;
1729 bool stencil_compress_disable;
1730 bool resummarize_enable;
1731 uint32_t custom_blend_mode;
1732 };
1733
1734 VkResult
1735 radv_graphics_pipeline_create(VkDevice device,
1736 VkPipelineCache cache,
1737 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1738 const struct radv_graphics_pipeline_create_info *extra,
1739 const VkAllocationCallbacks *alloc,
1740 VkPipeline *pPipeline);
1741
1742 struct radv_binning_settings {
1743 unsigned context_states_per_bin; /* allowed range: [1, 6] */
1744 unsigned persistent_states_per_bin; /* allowed range: [1, 32] */
1745 unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */
1746 };
1747
1748 struct radv_binning_settings
1749 radv_get_binning_settings(const struct radv_physical_device *pdev);
1750
1751 struct vk_format_description;
1752 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1753 int first_non_void);
1754 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1755 int first_non_void);
1756 bool radv_is_buffer_format_supported(VkFormat format, bool *scaled);
1757 uint32_t radv_translate_colorformat(VkFormat format);
1758 uint32_t radv_translate_color_numformat(VkFormat format,
1759 const struct vk_format_description *desc,
1760 int first_non_void);
1761 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1762 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1763 uint32_t radv_translate_dbformat(VkFormat format);
1764 uint32_t radv_translate_tex_dataformat(VkFormat format,
1765 const struct vk_format_description *desc,
1766 int first_non_void);
1767 uint32_t radv_translate_tex_numformat(VkFormat format,
1768 const struct vk_format_description *desc,
1769 int first_non_void);
1770 bool radv_format_pack_clear_color(VkFormat format,
1771 uint32_t clear_vals[2],
1772 VkClearColorValue *value);
1773 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1774 bool radv_dcc_formats_compatible(VkFormat format1,
1775 VkFormat format2);
1776 bool radv_device_supports_etc(struct radv_physical_device *physical_device);
1777
1778 struct radv_image_plane {
1779 VkFormat format;
1780 struct radeon_surf surface;
1781 uint64_t offset;
1782 };
1783
1784 struct radv_image {
1785 struct vk_object_base base;
1786 VkImageType type;
1787 /* The original VkFormat provided by the client. This may not match any
1788 * of the actual surface formats.
1789 */
1790 VkFormat vk_format;
1791 VkImageAspectFlags aspects;
1792 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1793 struct ac_surf_info info;
1794 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1795 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1796
1797 VkDeviceSize size;
1798 uint32_t alignment;
1799
1800 unsigned queue_family_mask;
1801 bool exclusive;
1802 bool shareable;
1803
1804 /* Set when bound */
1805 struct radeon_winsys_bo *bo;
1806 VkDeviceSize offset;
1807 bool tc_compatible_htile;
1808 bool tc_compatible_cmask;
1809
1810 uint64_t clear_value_offset;
1811 uint64_t fce_pred_offset;
1812 uint64_t dcc_pred_offset;
1813
1814 /*
1815 * Metadata for the TC-compat zrange workaround. If the 32-bit value
1816 * stored at this offset is UINT_MAX, the driver will emit
1817 * DB_Z_INFO.ZRANGE_PRECISION=0, otherwise it will skip the
1818 * SET_CONTEXT_REG packet.
1819 */
1820 uint64_t tc_compat_zrange_offset;
1821
1822 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1823 VkDeviceMemory owned_memory;
1824
1825 unsigned plane_count;
1826 struct radv_image_plane planes[0];
1827 };
1828
1829 /* Whether the image has a htile that is known consistent with the contents of
1830 * the image and is allowed to be in compressed form.
1831 *
1832 * If this is false reads that don't use the htile should be able to return
1833 * correct results.
1834 */
1835 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1836 VkImageLayout layout,
1837 bool in_render_loop,
1838 unsigned queue_mask);
1839
1840 bool radv_layout_can_fast_clear(const struct radv_image *image,
1841 VkImageLayout layout,
1842 bool in_render_loop,
1843 unsigned queue_mask);
1844
1845 bool radv_layout_dcc_compressed(const struct radv_device *device,
1846 const struct radv_image *image,
1847 VkImageLayout layout,
1848 bool in_render_loop,
1849 unsigned queue_mask);
1850
1851 /**
1852 * Return whether the image has CMASK metadata for color surfaces.
1853 */
1854 static inline bool
1855 radv_image_has_cmask(const struct radv_image *image)
1856 {
1857 return image->planes[0].surface.cmask_offset;
1858 }
1859
1860 /**
1861 * Return whether the image has FMASK metadata for color surfaces.
1862 */
1863 static inline bool
1864 radv_image_has_fmask(const struct radv_image *image)
1865 {
1866 return image->planes[0].surface.fmask_offset;
1867 }
1868
1869 /**
1870 * Return whether the image has DCC metadata for color surfaces.
1871 */
1872 static inline bool
1873 radv_image_has_dcc(const struct radv_image *image)
1874 {
1875 return image->planes[0].surface.dcc_size;
1876 }
1877
1878 /**
1879 * Return whether the image is TC-compatible CMASK.
1880 */
1881 static inline bool
1882 radv_image_is_tc_compat_cmask(const struct radv_image *image)
1883 {
1884 return radv_image_has_fmask(image) && image->tc_compatible_cmask;
1885 }
1886
1887 /**
1888 * Return whether DCC metadata is enabled for a level.
1889 */
1890 static inline bool
1891 radv_dcc_enabled(const struct radv_image *image, unsigned level)
1892 {
1893 return radv_image_has_dcc(image) &&
1894 level < image->planes[0].surface.num_dcc_levels;
1895 }
1896
1897 /**
1898 * Return whether the image has CB metadata.
1899 */
1900 static inline bool
1901 radv_image_has_CB_metadata(const struct radv_image *image)
1902 {
1903 return radv_image_has_cmask(image) ||
1904 radv_image_has_fmask(image) ||
1905 radv_image_has_dcc(image);
1906 }
1907
1908 /**
1909 * Return whether the image has HTILE metadata for depth surfaces.
1910 */
1911 static inline bool
1912 radv_image_has_htile(const struct radv_image *image)
1913 {
1914 return image->planes[0].surface.htile_size;
1915 }
1916
1917 /**
1918 * Return whether HTILE metadata is enabled for a level.
1919 */
1920 static inline bool
1921 radv_htile_enabled(const struct radv_image *image, unsigned level)
1922 {
1923 return radv_image_has_htile(image) && level == 0;
1924 }
1925
1926 /**
1927 * Return whether the image is TC-compatible HTILE.
1928 */
1929 static inline bool
1930 radv_image_is_tc_compat_htile(const struct radv_image *image)
1931 {
1932 return radv_image_has_htile(image) && image->tc_compatible_htile;
1933 }
1934
1935 static inline uint64_t
1936 radv_image_get_fast_clear_va(const struct radv_image *image,
1937 uint32_t base_level)
1938 {
1939 uint64_t va = radv_buffer_get_va(image->bo);
1940 va += image->offset + image->clear_value_offset + base_level * 8;
1941 return va;
1942 }
1943
1944 static inline uint64_t
1945 radv_image_get_fce_pred_va(const struct radv_image *image,
1946 uint32_t base_level)
1947 {
1948 uint64_t va = radv_buffer_get_va(image->bo);
1949 va += image->offset + image->fce_pred_offset + base_level * 8;
1950 return va;
1951 }
1952
1953 static inline uint64_t
1954 radv_image_get_dcc_pred_va(const struct radv_image *image,
1955 uint32_t base_level)
1956 {
1957 uint64_t va = radv_buffer_get_va(image->bo);
1958 va += image->offset + image->dcc_pred_offset + base_level * 8;
1959 return va;
1960 }
1961
1962 static inline uint64_t
1963 radv_get_tc_compat_zrange_va(const struct radv_image *image,
1964 uint32_t base_level)
1965 {
1966 uint64_t va = radv_buffer_get_va(image->bo);
1967 va += image->offset + image->tc_compat_zrange_offset + base_level * 4;
1968 return va;
1969 }
1970
1971 static inline uint64_t
1972 radv_get_ds_clear_value_va(const struct radv_image *image,
1973 uint32_t base_level)
1974 {
1975 uint64_t va = radv_buffer_get_va(image->bo);
1976 va += image->offset + image->clear_value_offset + base_level * 8;
1977 return va;
1978 }
1979
1980 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1981
1982 static inline uint32_t
1983 radv_get_layerCount(const struct radv_image *image,
1984 const VkImageSubresourceRange *range)
1985 {
1986 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1987 image->info.array_size - range->baseArrayLayer : range->layerCount;
1988 }
1989
1990 static inline uint32_t
1991 radv_get_levelCount(const struct radv_image *image,
1992 const VkImageSubresourceRange *range)
1993 {
1994 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1995 image->info.levels - range->baseMipLevel : range->levelCount;
1996 }
1997
1998 struct radeon_bo_metadata;
1999 void
2000 radv_init_metadata(struct radv_device *device,
2001 struct radv_image *image,
2002 struct radeon_bo_metadata *metadata);
2003
2004 void
2005 radv_image_override_offset_stride(struct radv_device *device,
2006 struct radv_image *image,
2007 uint64_t offset, uint32_t stride);
2008
2009 union radv_descriptor {
2010 struct {
2011 uint32_t plane0_descriptor[8];
2012 uint32_t fmask_descriptor[8];
2013 };
2014 struct {
2015 uint32_t plane_descriptors[3][8];
2016 };
2017 };
2018
2019 struct radv_image_view {
2020 struct vk_object_base base;
2021 struct radv_image *image; /**< VkImageViewCreateInfo::image */
2022 struct radeon_winsys_bo *bo;
2023
2024 VkImageViewType type;
2025 VkImageAspectFlags aspect_mask;
2026 VkFormat vk_format;
2027 unsigned plane_id;
2028 bool multiple_planes;
2029 uint32_t base_layer;
2030 uint32_t layer_count;
2031 uint32_t base_mip;
2032 uint32_t level_count;
2033 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
2034
2035 union radv_descriptor descriptor;
2036
2037 /* Descriptor for use as a storage image as opposed to a sampled image.
2038 * This has a few differences for cube maps (e.g. type).
2039 */
2040 union radv_descriptor storage_descriptor;
2041 };
2042
2043 struct radv_image_create_info {
2044 const VkImageCreateInfo *vk_info;
2045 bool scanout;
2046 bool no_metadata_planes;
2047 const struct radeon_bo_metadata *bo_metadata;
2048 };
2049
2050 VkResult
2051 radv_image_create_layout(struct radv_device *device,
2052 struct radv_image_create_info create_info,
2053 struct radv_image *image);
2054
2055 VkResult radv_image_create(VkDevice _device,
2056 const struct radv_image_create_info *info,
2057 const VkAllocationCallbacks* alloc,
2058 VkImage *pImage);
2059
2060 bool vi_alpha_is_on_msb(struct radv_device *device, VkFormat format);
2061
2062 VkResult
2063 radv_image_from_gralloc(VkDevice device_h,
2064 const VkImageCreateInfo *base_info,
2065 const VkNativeBufferANDROID *gralloc_info,
2066 const VkAllocationCallbacks *alloc,
2067 VkImage *out_image_h);
2068 uint64_t
2069 radv_ahb_usage_from_vk_usage(const VkImageCreateFlags vk_create,
2070 const VkImageUsageFlags vk_usage);
2071 VkResult
2072 radv_import_ahb_memory(struct radv_device *device,
2073 struct radv_device_memory *mem,
2074 unsigned priority,
2075 const VkImportAndroidHardwareBufferInfoANDROID *info);
2076 VkResult
2077 radv_create_ahb_memory(struct radv_device *device,
2078 struct radv_device_memory *mem,
2079 unsigned priority,
2080 const VkMemoryAllocateInfo *pAllocateInfo);
2081
2082 VkFormat
2083 radv_select_android_external_format(const void *next, VkFormat default_format);
2084
2085 bool radv_android_gralloc_supports_format(VkFormat format, VkImageUsageFlagBits usage);
2086
2087 struct radv_image_view_extra_create_info {
2088 bool disable_compression;
2089 };
2090
2091 void radv_image_view_init(struct radv_image_view *view,
2092 struct radv_device *device,
2093 const VkImageViewCreateInfo *pCreateInfo,
2094 const struct radv_image_view_extra_create_info* extra_create_info);
2095
2096 VkFormat radv_get_aspect_format(struct radv_image *image, VkImageAspectFlags mask);
2097
2098 struct radv_sampler_ycbcr_conversion {
2099 struct vk_object_base base;
2100 VkFormat format;
2101 VkSamplerYcbcrModelConversion ycbcr_model;
2102 VkSamplerYcbcrRange ycbcr_range;
2103 VkComponentMapping components;
2104 VkChromaLocation chroma_offsets[2];
2105 VkFilter chroma_filter;
2106 };
2107
2108 struct radv_buffer_view {
2109 struct vk_object_base base;
2110 struct radeon_winsys_bo *bo;
2111 VkFormat vk_format;
2112 uint64_t range; /**< VkBufferViewCreateInfo::range */
2113 uint32_t state[4];
2114 };
2115 void radv_buffer_view_init(struct radv_buffer_view *view,
2116 struct radv_device *device,
2117 const VkBufferViewCreateInfo* pCreateInfo);
2118
2119 static inline struct VkExtent3D
2120 radv_sanitize_image_extent(const VkImageType imageType,
2121 const struct VkExtent3D imageExtent)
2122 {
2123 switch (imageType) {
2124 case VK_IMAGE_TYPE_1D:
2125 return (VkExtent3D) { imageExtent.width, 1, 1 };
2126 case VK_IMAGE_TYPE_2D:
2127 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
2128 case VK_IMAGE_TYPE_3D:
2129 return imageExtent;
2130 default:
2131 unreachable("invalid image type");
2132 }
2133 }
2134
2135 static inline struct VkOffset3D
2136 radv_sanitize_image_offset(const VkImageType imageType,
2137 const struct VkOffset3D imageOffset)
2138 {
2139 switch (imageType) {
2140 case VK_IMAGE_TYPE_1D:
2141 return (VkOffset3D) { imageOffset.x, 0, 0 };
2142 case VK_IMAGE_TYPE_2D:
2143 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
2144 case VK_IMAGE_TYPE_3D:
2145 return imageOffset;
2146 default:
2147 unreachable("invalid image type");
2148 }
2149 }
2150
2151 static inline bool
2152 radv_image_extent_compare(const struct radv_image *image,
2153 const VkExtent3D *extent)
2154 {
2155 if (extent->width != image->info.width ||
2156 extent->height != image->info.height ||
2157 extent->depth != image->info.depth)
2158 return false;
2159 return true;
2160 }
2161
2162 struct radv_sampler {
2163 struct vk_object_base base;
2164 uint32_t state[4];
2165 struct radv_sampler_ycbcr_conversion *ycbcr_sampler;
2166 uint32_t border_color_slot;
2167 };
2168
2169 struct radv_framebuffer {
2170 struct vk_object_base base;
2171 uint32_t width;
2172 uint32_t height;
2173 uint32_t layers;
2174
2175 uint32_t attachment_count;
2176 struct radv_image_view *attachments[0];
2177 };
2178
2179 struct radv_subpass_barrier {
2180 VkPipelineStageFlags src_stage_mask;
2181 VkAccessFlags src_access_mask;
2182 VkAccessFlags dst_access_mask;
2183 };
2184
2185 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2186 const struct radv_subpass_barrier *barrier);
2187
2188 struct radv_subpass_attachment {
2189 uint32_t attachment;
2190 VkImageLayout layout;
2191 VkImageLayout stencil_layout;
2192 bool in_render_loop;
2193 };
2194
2195 struct radv_subpass {
2196 uint32_t attachment_count;
2197 struct radv_subpass_attachment * attachments;
2198
2199 uint32_t input_count;
2200 uint32_t color_count;
2201 struct radv_subpass_attachment * input_attachments;
2202 struct radv_subpass_attachment * color_attachments;
2203 struct radv_subpass_attachment * resolve_attachments;
2204 struct radv_subpass_attachment * depth_stencil_attachment;
2205 struct radv_subpass_attachment * ds_resolve_attachment;
2206 VkResolveModeFlagBits depth_resolve_mode;
2207 VkResolveModeFlagBits stencil_resolve_mode;
2208
2209 /** Subpass has at least one color resolve attachment */
2210 bool has_color_resolve;
2211
2212 /** Subpass has at least one color attachment */
2213 bool has_color_att;
2214
2215 struct radv_subpass_barrier start_barrier;
2216
2217 uint32_t view_mask;
2218
2219 VkSampleCountFlagBits color_sample_count;
2220 VkSampleCountFlagBits depth_sample_count;
2221 VkSampleCountFlagBits max_sample_count;
2222 };
2223
2224 uint32_t
2225 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer);
2226
2227 struct radv_render_pass_attachment {
2228 VkFormat format;
2229 uint32_t samples;
2230 VkAttachmentLoadOp load_op;
2231 VkAttachmentLoadOp stencil_load_op;
2232 VkImageLayout initial_layout;
2233 VkImageLayout final_layout;
2234 VkImageLayout stencil_initial_layout;
2235 VkImageLayout stencil_final_layout;
2236
2237 /* The subpass id in which the attachment will be used first/last. */
2238 uint32_t first_subpass_idx;
2239 uint32_t last_subpass_idx;
2240 };
2241
2242 struct radv_render_pass {
2243 struct vk_object_base base;
2244 uint32_t attachment_count;
2245 uint32_t subpass_count;
2246 struct radv_subpass_attachment * subpass_attachments;
2247 struct radv_render_pass_attachment * attachments;
2248 struct radv_subpass_barrier end_barrier;
2249 struct radv_subpass subpasses[0];
2250 };
2251
2252 VkResult radv_device_init_meta(struct radv_device *device);
2253 void radv_device_finish_meta(struct radv_device *device);
2254
2255 struct radv_query_pool {
2256 struct vk_object_base base;
2257 struct radeon_winsys_bo *bo;
2258 uint32_t stride;
2259 uint32_t availability_offset;
2260 uint64_t size;
2261 char *ptr;
2262 VkQueryType type;
2263 uint32_t pipeline_stats_mask;
2264 };
2265
2266 typedef enum {
2267 RADV_SEMAPHORE_NONE,
2268 RADV_SEMAPHORE_WINSYS,
2269 RADV_SEMAPHORE_SYNCOBJ,
2270 RADV_SEMAPHORE_TIMELINE,
2271 } radv_semaphore_kind;
2272
2273 struct radv_deferred_queue_submission;
2274
2275 struct radv_timeline_waiter {
2276 struct list_head list;
2277 struct radv_deferred_queue_submission *submission;
2278 uint64_t value;
2279 };
2280
2281 struct radv_timeline_point {
2282 struct list_head list;
2283
2284 uint64_t value;
2285 uint32_t syncobj;
2286
2287 /* Separate from the list to accomodate CPU wait being async, as well
2288 * as prevent point deletion during submission. */
2289 unsigned wait_count;
2290 };
2291
2292 struct radv_timeline {
2293 /* Using a pthread mutex to be compatible with condition variables. */
2294 pthread_mutex_t mutex;
2295
2296 uint64_t highest_signaled;
2297 uint64_t highest_submitted;
2298
2299 struct list_head points;
2300
2301 /* Keep free points on hand so we do not have to recreate syncobjs all
2302 * the time. */
2303 struct list_head free_points;
2304
2305 /* Submissions that are deferred waiting for a specific value to be
2306 * submitted. */
2307 struct list_head waiters;
2308 };
2309
2310 struct radv_semaphore_part {
2311 radv_semaphore_kind kind;
2312 union {
2313 uint32_t syncobj;
2314 struct radeon_winsys_sem *ws_sem;
2315 struct radv_timeline timeline;
2316 };
2317 };
2318
2319 struct radv_semaphore {
2320 struct vk_object_base base;
2321 struct radv_semaphore_part permanent;
2322 struct radv_semaphore_part temporary;
2323 };
2324
2325 bool radv_queue_internal_submit(struct radv_queue *queue,
2326 struct radeon_cmdbuf *cs);
2327
2328 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2329 VkPipelineBindPoint bind_point,
2330 struct radv_descriptor_set *set,
2331 unsigned idx);
2332
2333 void
2334 radv_update_descriptor_sets(struct radv_device *device,
2335 struct radv_cmd_buffer *cmd_buffer,
2336 VkDescriptorSet overrideSet,
2337 uint32_t descriptorWriteCount,
2338 const VkWriteDescriptorSet *pDescriptorWrites,
2339 uint32_t descriptorCopyCount,
2340 const VkCopyDescriptorSet *pDescriptorCopies);
2341
2342 void
2343 radv_update_descriptor_set_with_template(struct radv_device *device,
2344 struct radv_cmd_buffer *cmd_buffer,
2345 struct radv_descriptor_set *set,
2346 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
2347 const void *pData);
2348
2349 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2350 VkPipelineBindPoint pipelineBindPoint,
2351 VkPipelineLayout _layout,
2352 uint32_t set,
2353 uint32_t descriptorWriteCount,
2354 const VkWriteDescriptorSet *pDescriptorWrites);
2355
2356 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
2357 struct radv_image *image,
2358 const VkImageSubresourceRange *range, uint32_t value);
2359
2360 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
2361 struct radv_image *image,
2362 const VkImageSubresourceRange *range);
2363
2364 struct radv_fence {
2365 struct vk_object_base base;
2366 struct radeon_winsys_fence *fence;
2367 struct wsi_fence *fence_wsi;
2368
2369 uint32_t syncobj;
2370 uint32_t temp_syncobj;
2371 };
2372
2373 /* radv_nir_to_llvm.c */
2374 struct radv_shader_args;
2375
2376 void llvm_compile_shader(struct radv_device *device,
2377 unsigned shader_count,
2378 struct nir_shader *const *shaders,
2379 struct radv_shader_binary **binary,
2380 struct radv_shader_args *args);
2381
2382 unsigned radv_nir_get_max_workgroup_size(enum chip_class chip_class,
2383 gl_shader_stage stage,
2384 const struct nir_shader *nir);
2385
2386 /* radv_shader_info.h */
2387 struct radv_shader_info;
2388 struct radv_shader_variant_key;
2389
2390 void radv_nir_shader_info_pass(const struct nir_shader *nir,
2391 const struct radv_pipeline_layout *layout,
2392 const struct radv_shader_variant_key *key,
2393 struct radv_shader_info *info,
2394 bool use_llvm);
2395
2396 void radv_nir_shader_info_init(struct radv_shader_info *info);
2397
2398 /* radv_sqtt.c */
2399 struct radv_thread_trace_info {
2400 uint32_t cur_offset;
2401 uint32_t trace_status;
2402 union {
2403 uint32_t gfx9_write_counter;
2404 uint32_t gfx10_dropped_cntr;
2405 };
2406 };
2407
2408 struct radv_thread_trace_se {
2409 struct radv_thread_trace_info info;
2410 void *data_ptr;
2411 uint32_t shader_engine;
2412 uint32_t compute_unit;
2413 };
2414
2415 struct radv_thread_trace {
2416 uint32_t num_traces;
2417 struct radv_thread_trace_se traces[4];
2418 };
2419
2420 bool radv_thread_trace_init(struct radv_device *device);
2421 void radv_thread_trace_finish(struct radv_device *device);
2422 bool radv_begin_thread_trace(struct radv_queue *queue);
2423 bool radv_end_thread_trace(struct radv_queue *queue);
2424 bool radv_get_thread_trace(struct radv_queue *queue,
2425 struct radv_thread_trace *thread_trace);
2426 void radv_emit_thread_trace_userdata(struct radeon_cmdbuf *cs,
2427 const void *data, uint32_t num_dwords);
2428
2429 /* radv_rgp.c */
2430 int radv_dump_thread_trace(struct radv_device *device,
2431 const struct radv_thread_trace *trace);
2432
2433 /* radv_sqtt_layer_.c */
2434 struct radv_barrier_data {
2435 union {
2436 struct {
2437 uint16_t depth_stencil_expand : 1;
2438 uint16_t htile_hiz_range_expand : 1;
2439 uint16_t depth_stencil_resummarize : 1;
2440 uint16_t dcc_decompress : 1;
2441 uint16_t fmask_decompress : 1;
2442 uint16_t fast_clear_eliminate : 1;
2443 uint16_t fmask_color_expand : 1;
2444 uint16_t init_mask_ram : 1;
2445 uint16_t reserved : 8;
2446 };
2447 uint16_t all;
2448 } layout_transitions;
2449 };
2450
2451 /**
2452 * Value for the reason field of an RGP barrier start marker originating from
2453 * the Vulkan client (does not include PAL-defined values). (Table 15)
2454 */
2455 enum rgp_barrier_reason {
2456 RGP_BARRIER_UNKNOWN_REASON = 0xFFFFFFFF,
2457
2458 /* External app-generated barrier reasons, i.e. API synchronization
2459 * commands Range of valid values: [0x00000001 ... 0x7FFFFFFF].
2460 */
2461 RGP_BARRIER_EXTERNAL_CMD_PIPELINE_BARRIER = 0x00000001,
2462 RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC = 0x00000002,
2463 RGP_BARRIER_EXTERNAL_CMD_WAIT_EVENTS = 0x00000003,
2464
2465 /* Internal barrier reasons, i.e. implicit synchronization inserted by
2466 * the Vulkan driver Range of valid values: [0xC0000000 ... 0xFFFFFFFE].
2467 */
2468 RGP_BARRIER_INTERNAL_BASE = 0xC0000000,
2469 RGP_BARRIER_INTERNAL_PRE_RESET_QUERY_POOL_SYNC = RGP_BARRIER_INTERNAL_BASE + 0,
2470 RGP_BARRIER_INTERNAL_POST_RESET_QUERY_POOL_SYNC = RGP_BARRIER_INTERNAL_BASE + 1,
2471 RGP_BARRIER_INTERNAL_GPU_EVENT_RECYCLE_STALL = RGP_BARRIER_INTERNAL_BASE + 2,
2472 RGP_BARRIER_INTERNAL_PRE_COPY_QUERY_POOL_RESULTS_SYNC = RGP_BARRIER_INTERNAL_BASE + 3
2473 };
2474
2475 void radv_describe_begin_cmd_buffer(struct radv_cmd_buffer *cmd_buffer);
2476 void radv_describe_end_cmd_buffer(struct radv_cmd_buffer *cmd_buffer);
2477 void radv_describe_draw(struct radv_cmd_buffer *cmd_buffer);
2478 void radv_describe_dispatch(struct radv_cmd_buffer *cmd_buffer, int x, int y, int z);
2479 void radv_describe_begin_render_pass_clear(struct radv_cmd_buffer *cmd_buffer,
2480 VkImageAspectFlagBits aspects);
2481 void radv_describe_end_render_pass_clear(struct radv_cmd_buffer *cmd_buffer);
2482 void radv_describe_barrier_start(struct radv_cmd_buffer *cmd_buffer,
2483 enum rgp_barrier_reason reason);
2484 void radv_describe_barrier_end(struct radv_cmd_buffer *cmd_buffer);
2485 void radv_describe_layout_transition(struct radv_cmd_buffer *cmd_buffer,
2486 const struct radv_barrier_data *barrier);
2487
2488 struct radeon_winsys_sem;
2489
2490 uint64_t radv_get_current_time(void);
2491
2492 static inline uint32_t
2493 si_conv_gl_prim_to_vertices(unsigned gl_prim)
2494 {
2495 switch (gl_prim) {
2496 case 0: /* GL_POINTS */
2497 return 1;
2498 case 1: /* GL_LINES */
2499 case 3: /* GL_LINE_STRIP */
2500 return 2;
2501 case 4: /* GL_TRIANGLES */
2502 case 5: /* GL_TRIANGLE_STRIP */
2503 return 3;
2504 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
2505 return 4;
2506 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
2507 return 6;
2508 case 7: /* GL_QUADS */
2509 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
2510 default:
2511 assert(0);
2512 return 0;
2513 }
2514 }
2515
2516 void radv_cmd_buffer_begin_render_pass(struct radv_cmd_buffer *cmd_buffer,
2517 const VkRenderPassBeginInfo *pRenderPassBegin);
2518 void radv_cmd_buffer_end_render_pass(struct radv_cmd_buffer *cmd_buffer);
2519
2520 static inline uint32_t si_translate_prim(unsigned topology)
2521 {
2522 switch (topology) {
2523 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
2524 return V_008958_DI_PT_POINTLIST;
2525 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
2526 return V_008958_DI_PT_LINELIST;
2527 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
2528 return V_008958_DI_PT_LINESTRIP;
2529 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
2530 return V_008958_DI_PT_TRILIST;
2531 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
2532 return V_008958_DI_PT_TRISTRIP;
2533 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
2534 return V_008958_DI_PT_TRIFAN;
2535 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
2536 return V_008958_DI_PT_LINELIST_ADJ;
2537 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
2538 return V_008958_DI_PT_LINESTRIP_ADJ;
2539 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
2540 return V_008958_DI_PT_TRILIST_ADJ;
2541 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
2542 return V_008958_DI_PT_TRISTRIP_ADJ;
2543 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
2544 return V_008958_DI_PT_PATCH;
2545 default:
2546 assert(0);
2547 return 0;
2548 }
2549 }
2550
2551 static inline uint32_t si_translate_stencil_op(enum VkStencilOp op)
2552 {
2553 switch (op) {
2554 case VK_STENCIL_OP_KEEP:
2555 return V_02842C_STENCIL_KEEP;
2556 case VK_STENCIL_OP_ZERO:
2557 return V_02842C_STENCIL_ZERO;
2558 case VK_STENCIL_OP_REPLACE:
2559 return V_02842C_STENCIL_REPLACE_TEST;
2560 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
2561 return V_02842C_STENCIL_ADD_CLAMP;
2562 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
2563 return V_02842C_STENCIL_SUB_CLAMP;
2564 case VK_STENCIL_OP_INVERT:
2565 return V_02842C_STENCIL_INVERT;
2566 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
2567 return V_02842C_STENCIL_ADD_WRAP;
2568 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
2569 return V_02842C_STENCIL_SUB_WRAP;
2570 default:
2571 return 0;
2572 }
2573 }
2574
2575 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
2576 \
2577 static inline struct __radv_type * \
2578 __radv_type ## _from_handle(__VkType _handle) \
2579 { \
2580 return (struct __radv_type *) _handle; \
2581 } \
2582 \
2583 static inline __VkType \
2584 __radv_type ## _to_handle(struct __radv_type *_obj) \
2585 { \
2586 return (__VkType) _obj; \
2587 }
2588
2589 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
2590 \
2591 static inline struct __radv_type * \
2592 __radv_type ## _from_handle(__VkType _handle) \
2593 { \
2594 return (struct __radv_type *)(uintptr_t) _handle; \
2595 } \
2596 \
2597 static inline __VkType \
2598 __radv_type ## _to_handle(struct __radv_type *_obj) \
2599 { \
2600 return (__VkType)(uintptr_t) _obj; \
2601 }
2602
2603 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
2604 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
2605
2606 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
2607 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
2608 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
2609 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
2610 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
2611
2612 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
2613 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
2614 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
2615 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
2616 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
2617 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
2618 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplate)
2619 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
2620 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
2621 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
2622 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
2623 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
2624 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
2625 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
2626 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
2627 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
2628 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
2629 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
2630 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
2631 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler_ycbcr_conversion, VkSamplerYcbcrConversion)
2632 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
2633 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
2634
2635 #endif /* RADV_PRIVATE_H */