projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv: Return VK_NOT_READY if the query results are not available.
[mesa.git] / src / amd / vulkan / radv_query.c
1 /*
2 * Copyrigh 2016 Red Hat Inc.
3 * Based on anv:
4 * Copyright © 2015 Intel Corporation
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 */
25
26 #include <assert.h>
27 #include <stdbool.h>
28 #include <string.h>
29 #include <unistd.h>
30 #include <fcntl.h>
31
32 #include "nir/nir_builder.h"
33 #include "radv_meta.h"
34 #include "radv_private.h"
35 #include "radv_cs.h"
36 #include "sid.h"
37
38
39 static const int pipelinestat_block_size = 11 * 8;
40 static const unsigned pipeline_statistics_indices[] = {7, 6, 3, 4, 5, 2, 1, 0, 8, 9, 10};
41
42 static unsigned get_max_db(struct radv_device *device)
43 {
44 unsigned num_db = device->physical_device->rad_info.num_render_backends;
45 MAYBE_UNUSED unsigned rb_mask = device->physical_device->rad_info.enabled_rb_mask;
46
47 if (device->physical_device->rad_info.chip_class == SI)
48 num_db = 8;
49 else
50 num_db = MAX2(8, num_db);
51
52 /* Otherwise we need to change the query reset procedure */
53 assert(rb_mask == ((1ull << num_db) - 1));
54
55 return num_db;
56 }
57
58 static void radv_break_on_count(nir_builder *b, nir_variable *var, nir_ssa_def *count)
59 {
60 nir_ssa_def *counter = nir_load_var(b, var);
61
62 nir_if *if_stmt = nir_if_create(b->shader);
63 if_stmt->condition = nir_src_for_ssa(nir_uge(b, counter, count));
64 nir_cf_node_insert(b->cursor, &if_stmt->cf_node);
65
66 b->cursor = nir_after_cf_list(&if_stmt->then_list);
67
68 nir_jump_instr *instr = nir_jump_instr_create(b->shader, nir_jump_break);
69 nir_builder_instr_insert(b, &instr->instr);
70
71 b->cursor = nir_after_cf_node(&if_stmt->cf_node);
72 counter = nir_iadd(b, counter, nir_imm_int(b, 1));
73 nir_store_var(b, var, counter, 0x1);
74 }
75
76 static struct nir_ssa_def *
77 radv_load_push_int(nir_builder *b, unsigned offset, const char *name)
78 {
79 nir_intrinsic_instr *flags = nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_push_constant);
80 flags->src[0] = nir_src_for_ssa(nir_imm_int(b, offset));
81 flags->num_components = 1;
82 nir_ssa_dest_init(&flags->instr, &flags->dest, 1, 32, name);
83 nir_builder_instr_insert(b, &flags->instr);
84 return &flags->dest.ssa;
85 }
86
87 static nir_shader *
88 build_occlusion_query_shader(struct radv_device *device) {
89 /* the shader this builds is roughly
90 *
91 * push constants {
92 * uint32_t flags;
93 * uint32_t dst_stride;
94 * };
95 *
96 * uint32_t src_stride = 16 * db_count;
97 *
98 * location(binding = 0) buffer dst_buf;
99 * location(binding = 1) buffer src_buf;
100 *
101 * void main() {
102 * uint64_t result = 0;
103 * uint64_t src_offset = src_stride * global_id.x;
104 * uint64_t dst_offset = dst_stride * global_id.x;
105 * bool available = true;
106 * for (int i = 0; i < db_count; ++i) {
107 * uint64_t start = src_buf[src_offset + 16 * i];
108 * uint64_t end = src_buf[src_offset + 16 * i + 8];
109 * if ((start & (1ull << 63)) && (end & (1ull << 63)))
110 * result += end - start;
111 * else
112 * available = false;
113 * }
114 * uint32_t elem_size = flags & VK_QUERY_RESULT_64_BIT ? 8 : 4;
115 * if ((flags & VK_QUERY_RESULT_PARTIAL_BIT) || available) {
116 * if (flags & VK_QUERY_RESULT_64_BIT)
117 * dst_buf[dst_offset] = result;
118 * else
119 * dst_buf[dst_offset] = (uint32_t)result.
120 * }
121 * if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT) {
122 * dst_buf[dst_offset + elem_size] = available;
123 * }
124 * }
125 */
126 nir_builder b;
127 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_COMPUTE, NULL);
128 b.shader->info->name = ralloc_strdup(b.shader, "occlusion_query");
129 b.shader->info->cs.local_size[0] = 64;
130 b.shader->info->cs.local_size[1] = 1;
131 b.shader->info->cs.local_size[2] = 1;
132
133 nir_variable *result = nir_local_variable_create(b.impl, glsl_uint64_t_type(), "result");
134 nir_variable *outer_counter = nir_local_variable_create(b.impl, glsl_int_type(), "outer_counter");
135 nir_variable *start = nir_local_variable_create(b.impl, glsl_uint64_t_type(), "start");
136 nir_variable *end = nir_local_variable_create(b.impl, glsl_uint64_t_type(), "end");
137 nir_variable *available = nir_local_variable_create(b.impl, glsl_int_type(), "available");
138 unsigned db_count = get_max_db(device);
139
140 nir_ssa_def *flags = radv_load_push_int(&b, 0, "flags");
141
142 nir_intrinsic_instr *dst_buf = nir_intrinsic_instr_create(b.shader,
143 nir_intrinsic_vulkan_resource_index);
144 dst_buf->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
145 nir_intrinsic_set_desc_set(dst_buf, 0);
146 nir_intrinsic_set_binding(dst_buf, 0);
147 nir_ssa_dest_init(&dst_buf->instr, &dst_buf->dest, 1, 32, NULL);
148 nir_builder_instr_insert(&b, &dst_buf->instr);
149
150 nir_intrinsic_instr *src_buf = nir_intrinsic_instr_create(b.shader,
151 nir_intrinsic_vulkan_resource_index);
152 src_buf->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
153 nir_intrinsic_set_desc_set(src_buf, 0);
154 nir_intrinsic_set_binding(src_buf, 1);
155 nir_ssa_dest_init(&src_buf->instr, &src_buf->dest, 1, 32, NULL);
156 nir_builder_instr_insert(&b, &src_buf->instr);
157
158 nir_ssa_def *invoc_id = nir_load_system_value(&b, nir_intrinsic_load_local_invocation_id, 0);
159 nir_ssa_def *wg_id = nir_load_system_value(&b, nir_intrinsic_load_work_group_id, 0);
160 nir_ssa_def *block_size = nir_imm_ivec4(&b,
161 b.shader->info->cs.local_size[0],
162 b.shader->info->cs.local_size[1],
163 b.shader->info->cs.local_size[2], 0);
164 nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
165 global_id = nir_channel(&b, global_id, 0); // We only care about x here.
166
167 nir_ssa_def *input_stride = nir_imm_int(&b, db_count * 16);
168 nir_ssa_def *input_base = nir_imul(&b, input_stride, global_id);
169 nir_ssa_def *output_stride = radv_load_push_int(&b, 4, "output_stride");
170 nir_ssa_def *output_base = nir_imul(&b, output_stride, global_id);
171
172
173 nir_store_var(&b, result, nir_imm_int64(&b, 0), 0x1);
174 nir_store_var(&b, outer_counter, nir_imm_int(&b, 0), 0x1);
175 nir_store_var(&b, available, nir_imm_int(&b, 1), 0x1);
176
177 nir_loop *outer_loop = nir_loop_create(b.shader);
178 nir_builder_cf_insert(&b, &outer_loop->cf_node);
179 b.cursor = nir_after_cf_list(&outer_loop->body);
180
181 nir_ssa_def *current_outer_count = nir_load_var(&b, outer_counter);
182 radv_break_on_count(&b, outer_counter, nir_imm_int(&b, db_count));
183
184 nir_ssa_def *load_offset = nir_imul(&b, current_outer_count, nir_imm_int(&b, 16));
185 load_offset = nir_iadd(&b, input_base, load_offset);
186
187 nir_intrinsic_instr *load = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_ssbo);
188 load->src[0] = nir_src_for_ssa(&src_buf->dest.ssa);
189 load->src[1] = nir_src_for_ssa(load_offset);
190 nir_ssa_dest_init(&load->instr, &load->dest, 2, 64, NULL);
191 load->num_components = 2;
192 nir_builder_instr_insert(&b, &load->instr);
193
194 const unsigned swizzle0[] = {0,0,0,0};
195 const unsigned swizzle1[] = {1,1,1,1};
196 nir_store_var(&b, start, nir_swizzle(&b, &load->dest.ssa, swizzle0, 1, false), 0x1);
197 nir_store_var(&b, end, nir_swizzle(&b, &load->dest.ssa, swizzle1, 1, false), 0x1);
198
199 nir_ssa_def *start_done = nir_ilt(&b, nir_load_var(&b, start), nir_imm_int64(&b, 0));
200 nir_ssa_def *end_done = nir_ilt(&b, nir_load_var(&b, end), nir_imm_int64(&b, 0));
201
202 nir_if *update_if = nir_if_create(b.shader);
203 update_if->condition = nir_src_for_ssa(nir_iand(&b, start_done, end_done));
204 nir_cf_node_insert(b.cursor, &update_if->cf_node);
205
206 b.cursor = nir_after_cf_list(&update_if->then_list);
207
208 nir_store_var(&b, result,
209 nir_iadd(&b, nir_load_var(&b, result),
210 nir_isub(&b, nir_load_var(&b, end),
211 nir_load_var(&b, start))), 0x1);
212
213 b.cursor = nir_after_cf_list(&update_if->else_list);
214
215 nir_store_var(&b, available, nir_imm_int(&b, 0), 0x1);
216
217 b.cursor = nir_after_cf_node(&outer_loop->cf_node);
218
219 /* Store the result if complete or if partial results have been requested. */
220
221 nir_ssa_def *result_is_64bit = nir_iand(&b, flags,
222 nir_imm_int(&b, VK_QUERY_RESULT_64_BIT));
223 nir_ssa_def *result_size = nir_bcsel(&b, result_is_64bit, nir_imm_int(&b, 8), nir_imm_int(&b, 4));
224
225 nir_if *store_if = nir_if_create(b.shader);
226 store_if->condition = nir_src_for_ssa(nir_ior(&b, nir_iand(&b, flags, nir_imm_int(&b, VK_QUERY_RESULT_PARTIAL_BIT)), nir_load_var(&b, available)));
227 nir_cf_node_insert(b.cursor, &store_if->cf_node);
228
229 b.cursor = nir_after_cf_list(&store_if->then_list);
230
231 nir_if *store_64bit_if = nir_if_create(b.shader);
232 store_64bit_if->condition = nir_src_for_ssa(result_is_64bit);
233 nir_cf_node_insert(b.cursor, &store_64bit_if->cf_node);
234
235 b.cursor = nir_after_cf_list(&store_64bit_if->then_list);
236
237 nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
238 store->src[0] = nir_src_for_ssa(nir_load_var(&b, result));
239 store->src[1] = nir_src_for_ssa(&dst_buf->dest.ssa);
240 store->src[2] = nir_src_for_ssa(output_base);
241 nir_intrinsic_set_write_mask(store, 0x1);
242 store->num_components = 1;
243 nir_builder_instr_insert(&b, &store->instr);
244
245 b.cursor = nir_after_cf_list(&store_64bit_if->else_list);
246
247 store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
248 store->src[0] = nir_src_for_ssa(nir_u2u32(&b, nir_load_var(&b, result)));
249 store->src[1] = nir_src_for_ssa(&dst_buf->dest.ssa);
250 store->src[2] = nir_src_for_ssa(output_base);
251 nir_intrinsic_set_write_mask(store, 0x1);
252 store->num_components = 1;
253 nir_builder_instr_insert(&b, &store->instr);
254
255 b.cursor = nir_after_cf_node(&store_if->cf_node);
256
257 /* Store the availability bit if requested. */
258
259 nir_if *availability_if = nir_if_create(b.shader);
260 availability_if->condition = nir_src_for_ssa(nir_iand(&b, flags, nir_imm_int(&b, VK_QUERY_RESULT_WITH_AVAILABILITY_BIT)));
261 nir_cf_node_insert(b.cursor, &availability_if->cf_node);
262
263 b.cursor = nir_after_cf_list(&availability_if->then_list);
264
265 store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
266 store->src[0] = nir_src_for_ssa(nir_load_var(&b, available));
267 store->src[1] = nir_src_for_ssa(&dst_buf->dest.ssa);
268 store->src[2] = nir_src_for_ssa(nir_iadd(&b, result_size, output_base));
269 nir_intrinsic_set_write_mask(store, 0x1);
270 store->num_components = 1;
271 nir_builder_instr_insert(&b, &store->instr);
272
273 return b.shader;
274 }
275
276 static nir_shader *
277 build_pipeline_statistics_query_shader(struct radv_device *device) {
278 /* the shader this builds is roughly
279 *
280 * push constants {
281 * uint32_t flags;
282 * uint32_t dst_stride;
283 * uint32_t stats_mask;
284 * uint32_t avail_offset;
285 * };
286 *
287 * uint32_t src_stride = pipelinestat_block_size * 2;
288 *
289 * location(binding = 0) buffer dst_buf;
290 * location(binding = 1) buffer src_buf;
291 *
292 * void main() {
293 * uint64_t src_offset = src_stride * global_id.x;
294 * uint64_t dst_base = dst_stride * global_id.x;
295 * uint64_t dst_offset = dst_base;
296 * uint32_t elem_size = flags & VK_QUERY_RESULT_64_BIT ? 8 : 4;
297 * uint32_t elem_count = stats_mask >> 16;
298 * uint32_t available = src_buf[avail_offset + 4 * global_id.x];
299 * if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT) {
300 * dst_buf[dst_offset + elem_count * elem_size] = available;
301 * }
302 * if (available) {
303 * // repeat 11 times:
304 * if (stats_mask & (1 << 0)) {
305 * uint64_t start = src_buf[src_offset + 8 * indices[0]];
306 * uint64_t end = src_buf[src_offset + 8 * indices[0] + pipelinestat_block_size];
307 * uint64_t result = end - start;
308 * if (flags & VK_QUERY_RESULT_64_BIT)
309 * dst_buf[dst_offset] = result;
310 * else
311 * dst_buf[dst_offset] = (uint32_t)result.
312 * dst_offset += elem_size;
313 * }
314 * } else if (flags & VK_QUERY_RESULT_PARTIAL_BIT) {
315 * // Set everything to 0 as we don't know what is valid.
316 * for (int i = 0; i < elem_count; ++i)
317 * dst_buf[dst_base + elem_size * i] = 0;
318 * }
319 * }
320 */
321 nir_builder b;
322 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_COMPUTE, NULL);
323 b.shader->info->name = ralloc_strdup(b.shader, "pipeline_statistics_query");
324 b.shader->info->cs.local_size[0] = 64;
325 b.shader->info->cs.local_size[1] = 1;
326 b.shader->info->cs.local_size[2] = 1;
327
328 nir_variable *output_offset = nir_local_variable_create(b.impl, glsl_int_type(), "output_offset");
329
330 nir_ssa_def *flags = radv_load_push_int(&b, 0, "flags");
331 nir_ssa_def *stats_mask = radv_load_push_int(&b, 8, "stats_mask");
332 nir_ssa_def *avail_offset = radv_load_push_int(&b, 12, "avail_offset");
333
334 nir_intrinsic_instr *dst_buf = nir_intrinsic_instr_create(b.shader,
335 nir_intrinsic_vulkan_resource_index);
336 dst_buf->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
337 nir_intrinsic_set_desc_set(dst_buf, 0);
338 nir_intrinsic_set_binding(dst_buf, 0);
339 nir_ssa_dest_init(&dst_buf->instr, &dst_buf->dest, 1, 32, NULL);
340 nir_builder_instr_insert(&b, &dst_buf->instr);
341
342 nir_intrinsic_instr *src_buf = nir_intrinsic_instr_create(b.shader,
343 nir_intrinsic_vulkan_resource_index);
344 src_buf->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
345 nir_intrinsic_set_desc_set(src_buf, 0);
346 nir_intrinsic_set_binding(src_buf, 1);
347 nir_ssa_dest_init(&src_buf->instr, &src_buf->dest, 1, 32, NULL);
348 nir_builder_instr_insert(&b, &src_buf->instr);
349
350 nir_ssa_def *invoc_id = nir_load_system_value(&b, nir_intrinsic_load_local_invocation_id, 0);
351 nir_ssa_def *wg_id = nir_load_system_value(&b, nir_intrinsic_load_work_group_id, 0);
352 nir_ssa_def *block_size = nir_imm_ivec4(&b,
353 b.shader->info->cs.local_size[0],
354 b.shader->info->cs.local_size[1],
355 b.shader->info->cs.local_size[2], 0);
356 nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
357 global_id = nir_channel(&b, global_id, 0); // We only care about x here.
358
359 nir_ssa_def *input_stride = nir_imm_int(&b, pipelinestat_block_size * 2);
360 nir_ssa_def *input_base = nir_imul(&b, input_stride, global_id);
361 nir_ssa_def *output_stride = radv_load_push_int(&b, 4, "output_stride");
362 nir_ssa_def *output_base = nir_imul(&b, output_stride, global_id);
363
364
365 avail_offset = nir_iadd(&b, avail_offset,
366 nir_imul(&b, global_id, nir_imm_int(&b, 4)));
367
368 nir_intrinsic_instr *load = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_ssbo);
369 load->src[0] = nir_src_for_ssa(&src_buf->dest.ssa);
370 load->src[1] = nir_src_for_ssa(avail_offset);
371 nir_ssa_dest_init(&load->instr, &load->dest, 1, 32, NULL);
372 load->num_components = 1;
373 nir_builder_instr_insert(&b, &load->instr);
374 nir_ssa_def *available = &load->dest.ssa;
375
376 nir_ssa_def *result_is_64bit = nir_iand(&b, flags,
377 nir_imm_int(&b, VK_QUERY_RESULT_64_BIT));
378 nir_ssa_def *elem_size = nir_bcsel(&b, result_is_64bit, nir_imm_int(&b, 8), nir_imm_int(&b, 4));
379 nir_ssa_def *elem_count = nir_ushr(&b, stats_mask, nir_imm_int(&b, 16));
380
381 /* Store the availability bit if requested. */
382
383 nir_if *availability_if = nir_if_create(b.shader);
384 availability_if->condition = nir_src_for_ssa(nir_iand(&b, flags, nir_imm_int(&b, VK_QUERY_RESULT_WITH_AVAILABILITY_BIT)));
385 nir_cf_node_insert(b.cursor, &availability_if->cf_node);
386
387 b.cursor = nir_after_cf_list(&availability_if->then_list);
388
389 nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
390 store->src[0] = nir_src_for_ssa(available);
391 store->src[1] = nir_src_for_ssa(&dst_buf->dest.ssa);
392 store->src[2] = nir_src_for_ssa(nir_iadd(&b, output_base, nir_imul(&b, elem_count, elem_size)));
393 nir_intrinsic_set_write_mask(store, 0x1);
394 store->num_components = 1;
395 nir_builder_instr_insert(&b, &store->instr);
396
397 b.cursor = nir_after_cf_node(&availability_if->cf_node);
398
399 nir_if *available_if = nir_if_create(b.shader);
400 available_if->condition = nir_src_for_ssa(available);
401 nir_cf_node_insert(b.cursor, &available_if->cf_node);
402
403 b.cursor = nir_after_cf_list(&available_if->then_list);
404
405 nir_store_var(&b, output_offset, output_base, 0x1);
406 for (int i = 0; i < 11; ++i) {
407 nir_if *store_if = nir_if_create(b.shader);
408 store_if->condition = nir_src_for_ssa(nir_iand(&b, stats_mask, nir_imm_int(&b, 1u << i)));
409 nir_cf_node_insert(b.cursor, &store_if->cf_node);
410
411 b.cursor = nir_after_cf_list(&store_if->then_list);
412
413 load = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_ssbo);
414 load->src[0] = nir_src_for_ssa(&src_buf->dest.ssa);
415 load->src[1] = nir_src_for_ssa(nir_iadd(&b, input_base,
416 nir_imm_int(&b, pipeline_statistics_indices[i] * 8)));
417 nir_ssa_dest_init(&load->instr, &load->dest, 1, 64, NULL);
418 load->num_components = 1;
419 nir_builder_instr_insert(&b, &load->instr);
420 nir_ssa_def *start = &load->dest.ssa;
421
422 load = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_ssbo);
423 load->src[0] = nir_src_for_ssa(&src_buf->dest.ssa);
424 load->src[1] = nir_src_for_ssa(nir_iadd(&b, input_base,
425 nir_imm_int(&b, pipeline_statistics_indices[i] * 8 + pipelinestat_block_size)));
426 nir_ssa_dest_init(&load->instr, &load->dest, 1, 64, NULL);
427 load->num_components = 1;
428 nir_builder_instr_insert(&b, &load->instr);
429 nir_ssa_def *end = &load->dest.ssa;
430
431 nir_ssa_def *result = nir_isub(&b, end, start);
432
433 /* Store result */
434 nir_if *store_64bit_if = nir_if_create(b.shader);
435 store_64bit_if->condition = nir_src_for_ssa(result_is_64bit);
436 nir_cf_node_insert(b.cursor, &store_64bit_if->cf_node);
437
438 b.cursor = nir_after_cf_list(&store_64bit_if->then_list);
439
440 nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
441 store->src[0] = nir_src_for_ssa(result);
442 store->src[1] = nir_src_for_ssa(&dst_buf->dest.ssa);
443 store->src[2] = nir_src_for_ssa(nir_load_var(&b, output_offset));
444 nir_intrinsic_set_write_mask(store, 0x1);
445 store->num_components = 1;
446 nir_builder_instr_insert(&b, &store->instr);
447
448 b.cursor = nir_after_cf_list(&store_64bit_if->else_list);
449
450 store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
451 store->src[0] = nir_src_for_ssa(nir_u2u32(&b, result));
452 store->src[1] = nir_src_for_ssa(&dst_buf->dest.ssa);
453 store->src[2] = nir_src_for_ssa(nir_load_var(&b, output_offset));
454 nir_intrinsic_set_write_mask(store, 0x1);
455 store->num_components = 1;
456 nir_builder_instr_insert(&b, &store->instr);
457
458 b.cursor = nir_after_cf_node(&store_64bit_if->cf_node);
459
460 nir_store_var(&b, output_offset,
461 nir_iadd(&b, nir_load_var(&b, output_offset),
462 elem_size), 0x1);
463
464 b.cursor = nir_after_cf_node(&store_if->cf_node);
465 }
466
467 b.cursor = nir_after_cf_list(&available_if->else_list);
468
469 available_if = nir_if_create(b.shader);
470 available_if->condition = nir_src_for_ssa(nir_iand(&b, flags,
471 nir_imm_int(&b, VK_QUERY_RESULT_PARTIAL_BIT)));
472 nir_cf_node_insert(b.cursor, &available_if->cf_node);
473
474 b.cursor = nir_after_cf_list(&available_if->then_list);
475
476 /* Stores zeros in all outputs. */
477
478 nir_variable *counter = nir_local_variable_create(b.impl, glsl_int_type(), "counter");
479 nir_store_var(&b, counter, nir_imm_int(&b, 0), 0x1);
480
481 nir_loop *loop = nir_loop_create(b.shader);
482 nir_builder_cf_insert(&b, &loop->cf_node);
483 b.cursor = nir_after_cf_list(&loop->body);
484
485 nir_ssa_def *current_counter = nir_load_var(&b, counter);
486 radv_break_on_count(&b, counter, elem_count);
487
488 nir_ssa_def *output_elem = nir_iadd(&b, output_base,
489 nir_imul(&b, elem_size, current_counter));
490
491 nir_if *store_64bit_if = nir_if_create(b.shader);
492 store_64bit_if->condition = nir_src_for_ssa(result_is_64bit);
493 nir_cf_node_insert(b.cursor, &store_64bit_if->cf_node);
494
495 b.cursor = nir_after_cf_list(&store_64bit_if->then_list);
496
497 store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
498 store->src[0] = nir_src_for_ssa(nir_imm_int64(&b, 0));
499 store->src[1] = nir_src_for_ssa(&dst_buf->dest.ssa);
500 store->src[2] = nir_src_for_ssa(output_elem);
501 nir_intrinsic_set_write_mask(store, 0x1);
502 store->num_components = 1;
503 nir_builder_instr_insert(&b, &store->instr);
504
505 b.cursor = nir_after_cf_list(&store_64bit_if->else_list);
506
507 store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
508 store->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
509 store->src[1] = nir_src_for_ssa(&dst_buf->dest.ssa);
510 store->src[2] = nir_src_for_ssa(output_elem);
511 nir_intrinsic_set_write_mask(store, 0x1);
512 store->num_components = 1;
513 nir_builder_instr_insert(&b, &store->instr);
514
515 b.cursor = nir_after_cf_node(&loop->cf_node);
516 return b.shader;
517 }
518
519 VkResult radv_device_init_meta_query_state(struct radv_device *device)
520 {
521 VkResult result;
522 struct radv_shader_module occlusion_cs = { .nir = NULL };
523 struct radv_shader_module pipeline_statistics_cs = { .nir = NULL };
524
525 zero(device->meta_state.query);
526
527 occlusion_cs.nir = build_occlusion_query_shader(device);
528 pipeline_statistics_cs.nir = build_pipeline_statistics_query_shader(device);
529
530 VkDescriptorSetLayoutCreateInfo occlusion_ds_create_info = {
531 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
532 .bindingCount = 2,
533 .pBindings = (VkDescriptorSetLayoutBinding[]) {
534 {
535 .binding = 0,
536 .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
537 .descriptorCount = 1,
538 .stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
539 .pImmutableSamplers = NULL
540 },
541 {
542 .binding = 1,
543 .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
544 .descriptorCount = 1,
545 .stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
546 .pImmutableSamplers = NULL
547 },
548 }
549 };
550
551 result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
552 &occlusion_ds_create_info,
553 &device->meta_state.alloc,
554 &device->meta_state.query.ds_layout);
555 if (result != VK_SUCCESS)
556 goto fail;
557
558 VkPipelineLayoutCreateInfo occlusion_pl_create_info = {
559 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
560 .setLayoutCount = 1,
561 .pSetLayouts = &device->meta_state.query.ds_layout,
562 .pushConstantRangeCount = 1,
563 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_COMPUTE_BIT, 0, 16},
564 };
565
566 result = radv_CreatePipelineLayout(radv_device_to_handle(device),
567 &occlusion_pl_create_info,
568 &device->meta_state.alloc,
569 &device->meta_state.query.p_layout);
570 if (result != VK_SUCCESS)
571 goto fail;
572
573 VkPipelineShaderStageCreateInfo occlusion_pipeline_shader_stage = {
574 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
575 .stage = VK_SHADER_STAGE_COMPUTE_BIT,
576 .module = radv_shader_module_to_handle(&occlusion_cs),
577 .pName = "main",
578 .pSpecializationInfo = NULL,
579 };
580
581 VkComputePipelineCreateInfo occlusion_vk_pipeline_info = {
582 .sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
583 .stage = occlusion_pipeline_shader_stage,
584 .flags = 0,
585 .layout = device->meta_state.query.p_layout,
586 };
587
588 result = radv_CreateComputePipelines(radv_device_to_handle(device),
589 radv_pipeline_cache_to_handle(&device->meta_state.cache),
590 1, &occlusion_vk_pipeline_info, NULL,
591 &device->meta_state.query.occlusion_query_pipeline);
592 if (result != VK_SUCCESS)
593 goto fail;
594
595 VkPipelineShaderStageCreateInfo pipeline_statistics_pipeline_shader_stage = {
596 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
597 .stage = VK_SHADER_STAGE_COMPUTE_BIT,
598 .module = radv_shader_module_to_handle(&pipeline_statistics_cs),
599 .pName = "main",
600 .pSpecializationInfo = NULL,
601 };
602
603 VkComputePipelineCreateInfo pipeline_statistics_vk_pipeline_info = {
604 .sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
605 .stage = pipeline_statistics_pipeline_shader_stage,
606 .flags = 0,
607 .layout = device->meta_state.query.p_layout,
608 };
609
610 result = radv_CreateComputePipelines(radv_device_to_handle(device),
611 radv_pipeline_cache_to_handle(&device->meta_state.cache),
612 1, &pipeline_statistics_vk_pipeline_info, NULL,
613 &device->meta_state.query.pipeline_statistics_query_pipeline);
614 if (result != VK_SUCCESS)
615 goto fail;
616
617 return VK_SUCCESS;
618 fail:
619 radv_device_finish_meta_query_state(device);
620 ralloc_free(occlusion_cs.nir);
621 ralloc_free(pipeline_statistics_cs.nir);
622 return result;
623 }
624
625 void radv_device_finish_meta_query_state(struct radv_device *device)
626 {
627 if (device->meta_state.query.pipeline_statistics_query_pipeline)
628 radv_DestroyPipeline(radv_device_to_handle(device),
629 device->meta_state.query.pipeline_statistics_query_pipeline,
630 &device->meta_state.alloc);
631
632 if (device->meta_state.query.occlusion_query_pipeline)
633 radv_DestroyPipeline(radv_device_to_handle(device),
634 device->meta_state.query.occlusion_query_pipeline,
635 &device->meta_state.alloc);
636
637 if (device->meta_state.query.p_layout)
638 radv_DestroyPipelineLayout(radv_device_to_handle(device),
639 device->meta_state.query.p_layout,
640 &device->meta_state.alloc);
641
642 if (device->meta_state.query.ds_layout)
643 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
644 device->meta_state.query.ds_layout,
645 &device->meta_state.alloc);
646 }
647
648 static void radv_query_shader(struct radv_cmd_buffer *cmd_buffer,
649 VkPipeline pipeline,
650 struct radeon_winsys_bo *src_bo,
651 struct radeon_winsys_bo *dst_bo,
652 uint64_t src_offset, uint64_t dst_offset,
653 uint32_t src_stride, uint32_t dst_stride,
654 uint32_t count, uint32_t flags,
655 uint32_t pipeline_stats_mask, uint32_t avail_offset)
656 {
657 struct radv_device *device = cmd_buffer->device;
658 struct radv_meta_saved_compute_state saved_state;
659 VkDescriptorSet ds;
660
661 radv_meta_save_compute(&saved_state, cmd_buffer, 4);
662
663 radv_temp_descriptor_set_create(device, cmd_buffer,
664 device->meta_state.query.ds_layout,
665 &ds);
666
667 struct radv_buffer dst_buffer = {
668 .bo = dst_bo,
669 .offset = dst_offset,
670 .size = dst_stride * count
671 };
672
673 struct radv_buffer src_buffer = {
674 .bo = src_bo,
675 .offset = src_offset,
676 .size = MAX2(src_stride * count, avail_offset + 4 * count - src_offset)
677 };
678
679 radv_UpdateDescriptorSets(radv_device_to_handle(device),
680 2, /* writeCount */
681 (VkWriteDescriptorSet[]) {
682 {
683 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
684 .dstSet = ds,
685 .dstBinding = 0,
686 .dstArrayElement = 0,
687 .descriptorCount = 1,
688 .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
689 .pBufferInfo = &(VkDescriptorBufferInfo) {
690 .buffer = radv_buffer_to_handle(&dst_buffer),
691 .offset = 0,
692 .range = VK_WHOLE_SIZE
693 }
694 },
695 {
696 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
697 .dstSet = ds,
698 .dstBinding = 1,
699 .dstArrayElement = 0,
700 .descriptorCount = 1,
701 .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
702 .pBufferInfo = &(VkDescriptorBufferInfo) {
703 .buffer = radv_buffer_to_handle(&src_buffer),
704 .offset = 0,
705 .range = VK_WHOLE_SIZE
706 }
707 }
708 }, 0, NULL);
709
710 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
711 VK_PIPELINE_BIND_POINT_COMPUTE, pipeline);
712
713 radv_CmdBindDescriptorSets(radv_cmd_buffer_to_handle(cmd_buffer),
714 VK_PIPELINE_BIND_POINT_COMPUTE,
715 device->meta_state.query.p_layout, 0, 1,
716 &ds, 0, NULL);
717
718 /* Encode the number of elements for easy access by the shader. */
719 pipeline_stats_mask &= 0x7ff;
720 pipeline_stats_mask |= util_bitcount(pipeline_stats_mask) << 16;
721
722 avail_offset -= src_offset;
723
724 struct {
725 uint32_t flags;
726 uint32_t dst_stride;
727 uint32_t pipeline_stats_mask;
728 uint32_t avail_offset;
729 } push_constants = {
730 flags,
731 dst_stride,
732 pipeline_stats_mask,
733 avail_offset
734 };
735
736 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
737 device->meta_state.query.p_layout,
738 VK_SHADER_STAGE_COMPUTE_BIT, 0, sizeof(push_constants),
739 &push_constants);
740
741 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2 |
742 RADV_CMD_FLAG_INV_VMEM_L1;
743
744 if (flags & VK_QUERY_RESULT_WAIT_BIT)
745 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER;
746
747 radv_unaligned_dispatch(cmd_buffer, count, 1, 1);
748
749 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2 |
750 RADV_CMD_FLAG_INV_VMEM_L1 |
751 RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
752
753 radv_temp_descriptor_set_destroy(device, ds);
754
755 radv_meta_restore_compute(&saved_state, cmd_buffer, 4);
756 }
757
758 VkResult radv_CreateQueryPool(
759 VkDevice _device,
760 const VkQueryPoolCreateInfo* pCreateInfo,
761 const VkAllocationCallbacks* pAllocator,
762 VkQueryPool* pQueryPool)
763 {
764 RADV_FROM_HANDLE(radv_device, device, _device);
765 uint64_t size;
766 struct radv_query_pool *pool = vk_alloc2(&device->alloc, pAllocator,
767 sizeof(*pool), 8,
768 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
769
770 if (!pool)
771 return VK_ERROR_OUT_OF_HOST_MEMORY;
772
773
774 switch(pCreateInfo->queryType) {
775 case VK_QUERY_TYPE_OCCLUSION:
776 pool->stride = 16 * get_max_db(device);
777 break;
778 case VK_QUERY_TYPE_PIPELINE_STATISTICS:
779 pool->stride = pipelinestat_block_size * 2;
780 break;
781 case VK_QUERY_TYPE_TIMESTAMP:
782 pool->stride = 8;
783 break;
784 default:
785 unreachable("creating unhandled query type");
786 }
787
788 pool->type = pCreateInfo->queryType;
789 pool->pipeline_stats_mask = pCreateInfo->pipelineStatistics;
790 pool->availability_offset = pool->stride * pCreateInfo->queryCount;
791 size = pool->availability_offset;
792 if (pCreateInfo->queryType == VK_QUERY_TYPE_TIMESTAMP ||
793 pCreateInfo->queryType == VK_QUERY_TYPE_PIPELINE_STATISTICS)
794 size += 4 * pCreateInfo->queryCount;
795
796 pool->bo = device->ws->buffer_create(device->ws, size,
797 64, RADEON_DOMAIN_GTT, 0);
798
799 if (!pool->bo) {
800 vk_free2(&device->alloc, pAllocator, pool);
801 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
802 }
803
804 pool->ptr = device->ws->buffer_map(pool->bo);
805
806 if (!pool->ptr) {
807 device->ws->buffer_destroy(pool->bo);
808 vk_free2(&device->alloc, pAllocator, pool);
809 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
810 }
811 memset(pool->ptr, 0, size);
812
813 *pQueryPool = radv_query_pool_to_handle(pool);
814 return VK_SUCCESS;
815 }
816
817 void radv_DestroyQueryPool(
818 VkDevice _device,
819 VkQueryPool _pool,
820 const VkAllocationCallbacks* pAllocator)
821 {
822 RADV_FROM_HANDLE(radv_device, device, _device);
823 RADV_FROM_HANDLE(radv_query_pool, pool, _pool);
824
825 if (!pool)
826 return;
827
828 device->ws->buffer_destroy(pool->bo);
829 vk_free2(&device->alloc, pAllocator, pool);
830 }
831
832 VkResult radv_GetQueryPoolResults(
833 VkDevice _device,
834 VkQueryPool queryPool,
835 uint32_t firstQuery,
836 uint32_t queryCount,
837 size_t dataSize,
838 void* pData,
839 VkDeviceSize stride,
840 VkQueryResultFlags flags)
841 {
842 RADV_FROM_HANDLE(radv_device, device, _device);
843 RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);
844 char *data = pData;
845 VkResult result = VK_SUCCESS;
846
847 for(unsigned i = 0; i < queryCount; ++i, data += stride) {
848 char *dest = data;
849 unsigned query = firstQuery + i;
850 char *src = pool->ptr + query * pool->stride;
851 uint32_t available;
852
853 if (pool->type != VK_QUERY_TYPE_OCCLUSION) {
854 if (flags & VK_QUERY_RESULT_WAIT_BIT)
855 while(!*(volatile uint32_t*)(pool->ptr + pool->availability_offset + 4 * query))
856 ;
857 available = *(uint32_t*)(pool->ptr + pool->availability_offset + 4 * query);
858 }
859
860 switch (pool->type) {
861 case VK_QUERY_TYPE_TIMESTAMP: {
862 if (!available && !(flags & VK_QUERY_RESULT_PARTIAL_BIT)) {
863 result = VK_NOT_READY;
864 break;
865
866 }
867
868 if (flags & VK_QUERY_RESULT_64_BIT) {
869 *(uint64_t*)dest = *(uint64_t*)src;
870 dest += 8;
871 } else {
872 *(uint32_t*)dest = *(uint32_t*)src;
873 dest += 4;
874 }
875 break;
876 }
877 case VK_QUERY_TYPE_OCCLUSION: {
878 volatile uint64_t const *src64 = (volatile uint64_t const *)src;
879 uint64_t result = 0;
880 int db_count = get_max_db(device);
881 available = 1;
882
883 for (int i = 0; i < db_count; ++i) {
884 uint64_t start, end;
885 do {
886 start = src64[2 * i];
887 end = src64[2 * i + 1];
888 } while ((!(start & (1ull << 63)) || !(end & (1ull << 63))) && (flags & VK_QUERY_RESULT_WAIT_BIT));
889
890 if (!(start & (1ull << 63)) || !(end & (1ull << 63)))
891 available = 0;
892 else {
893 result += end - start;
894 }
895 }
896
897 if (!available && !(flags & VK_QUERY_RESULT_PARTIAL_BIT)) {
898 result = VK_NOT_READY;
899 break;
900
901 }
902
903 if (flags & VK_QUERY_RESULT_64_BIT) {
904 *(uint64_t*)dest = result;
905 dest += 8;
906 } else {
907 *(uint32_t*)dest = result;
908 dest += 4;
909 }
910 break;
911 }
912 case VK_QUERY_TYPE_PIPELINE_STATISTICS: {
913 if (!available && !(flags & VK_QUERY_RESULT_PARTIAL_BIT)) {
914 result = VK_NOT_READY;
915 break;
916
917 }
918
919 const uint64_t *start = (uint64_t*)src;
920 const uint64_t *stop = (uint64_t*)(src + pipelinestat_block_size);
921 if (flags & VK_QUERY_RESULT_64_BIT) {
922 uint64_t *dst = (uint64_t*)dest;
923 dest += util_bitcount(pool->pipeline_stats_mask) * 8;
924 for(int i = 0; i < 11; ++i)
925 if(pool->pipeline_stats_mask & (1u << i))
926 *dst++ = stop[pipeline_statistics_indices[i]] -
927 start[pipeline_statistics_indices[i]];
928
929 } else {
930 uint32_t *dst = (uint32_t*)dest;
931 dest += util_bitcount(pool->pipeline_stats_mask) * 4;
932 for(int i = 0; i < 11; ++i)
933 if(pool->pipeline_stats_mask & (1u << i))
934 *dst++ = stop[pipeline_statistics_indices[i]] -
935 start[pipeline_statistics_indices[i]];
936 }
937 break;
938 }
939 default:
940 unreachable("trying to get results of unhandled query type");
941 }
942
943 if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT) {
944 if (flags & VK_QUERY_RESULT_64_BIT) {
945 *(uint64_t*)dest = available;
946 } else {
947 *(uint32_t*)dest = available;
948 }
949 }
950 }
951
952 return result;
953 }
954
955 void radv_CmdCopyQueryPoolResults(
956 VkCommandBuffer commandBuffer,
957 VkQueryPool queryPool,
958 uint32_t firstQuery,
959 uint32_t queryCount,
960 VkBuffer dstBuffer,
961 VkDeviceSize dstOffset,
962 VkDeviceSize stride,
963 VkQueryResultFlags flags)
964 {
965 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
966 RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);
967 RADV_FROM_HANDLE(radv_buffer, dst_buffer, dstBuffer);
968 struct radeon_winsys_cs *cs = cmd_buffer->cs;
969 unsigned elem_size = (flags & VK_QUERY_RESULT_64_BIT) ? 8 : 4;
970 uint64_t va = cmd_buffer->device->ws->buffer_get_va(pool->bo);
971 uint64_t dest_va = cmd_buffer->device->ws->buffer_get_va(dst_buffer->bo);
972 dest_va += dst_buffer->offset + dstOffset;
973
974 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, pool->bo, 8);
975 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, dst_buffer->bo, 8);
976
977 switch (pool->type) {
978 case VK_QUERY_TYPE_OCCLUSION:
979 if (flags & VK_QUERY_RESULT_WAIT_BIT) {
980 for(unsigned i = 0; i < queryCount; ++i, dest_va += stride) {
981 unsigned query = firstQuery + i;
982 uint64_t src_va = va + query * pool->stride + pool->stride - 4;
983
984 /* Waits on the upper word of the last DB entry */
985 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
986 radeon_emit(cs, 5 | WAIT_REG_MEM_MEM_SPACE(1));
987 radeon_emit(cs, src_va);
988 radeon_emit(cs, src_va >> 32);
989 radeon_emit(cs, 0x80000000); /* reference value */
990 radeon_emit(cs, 0xffffffff); /* mask */
991 radeon_emit(cs, 4); /* poll interval */
992 }
993 }
994 radv_query_shader(cmd_buffer, cmd_buffer->device->meta_state.query.occlusion_query_pipeline,
995 pool->bo, dst_buffer->bo, firstQuery * pool->stride,
996 dst_buffer->offset + dstOffset,
997 get_max_db(cmd_buffer->device) * 16, stride,
998 queryCount, flags, 0, 0);
999 break;
1000 case VK_QUERY_TYPE_PIPELINE_STATISTICS:
1001 if (flags & VK_QUERY_RESULT_WAIT_BIT) {
1002 for(unsigned i = 0; i < queryCount; ++i, dest_va += stride) {
1003 unsigned query = firstQuery + i;
1004
1005 radeon_check_space(cmd_buffer->device->ws, cs, 7);
1006
1007 uint64_t avail_va = va + pool->availability_offset + 4 * query;
1008
1009 /* This waits on the ME. All copies below are done on the ME */
1010 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
1011 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
1012 radeon_emit(cs, avail_va);
1013 radeon_emit(cs, avail_va >> 32);
1014 radeon_emit(cs, 1); /* reference value */
1015 radeon_emit(cs, 0xffffffff); /* mask */
1016 radeon_emit(cs, 4); /* poll interval */
1017 }
1018 }
1019 radv_query_shader(cmd_buffer, cmd_buffer->device->meta_state.query.pipeline_statistics_query_pipeline,
1020 pool->bo, dst_buffer->bo, firstQuery * pool->stride,
1021 dst_buffer->offset + dstOffset,
1022 pipelinestat_block_size * 2, stride, queryCount, flags,
1023 pool->pipeline_stats_mask,
1024 pool->availability_offset + 4 * firstQuery);
1025 break;
1026 case VK_QUERY_TYPE_TIMESTAMP:
1027 for(unsigned i = 0; i < queryCount; ++i, dest_va += stride) {
1028 unsigned query = firstQuery + i;
1029 uint64_t local_src_va = va + query * pool->stride;
1030
1031 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 19);
1032
1033
1034 if (flags & VK_QUERY_RESULT_WAIT_BIT) {
1035 /* TODO, not sure if there is any case where we won't always be ready yet */
1036 uint64_t avail_va = va + pool->availability_offset + 4 * query;
1037
1038 /* This waits on the ME. All copies below are done on the ME */
1039 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
1040 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
1041 radeon_emit(cs, avail_va);
1042 radeon_emit(cs, avail_va >> 32);
1043 radeon_emit(cs, 1); /* reference value */
1044 radeon_emit(cs, 0xffffffff); /* mask */
1045 radeon_emit(cs, 4); /* poll interval */
1046 }
1047 if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT) {
1048 uint64_t avail_va = va + pool->availability_offset + 4 * query;
1049 uint64_t avail_dest_va = dest_va + elem_size;
1050
1051 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1052 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1053 COPY_DATA_DST_SEL(COPY_DATA_MEM));
1054 radeon_emit(cs, avail_va);
1055 radeon_emit(cs, avail_va >> 32);
1056 radeon_emit(cs, avail_dest_va);
1057 radeon_emit(cs, avail_dest_va >> 32);
1058 }
1059
1060 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1061 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1062 COPY_DATA_DST_SEL(COPY_DATA_MEM) |
1063 ((flags & VK_QUERY_RESULT_64_BIT) ? COPY_DATA_COUNT_SEL : 0));
1064 radeon_emit(cs, local_src_va);
1065 radeon_emit(cs, local_src_va >> 32);
1066 radeon_emit(cs, dest_va);
1067 radeon_emit(cs, dest_va >> 32);
1068
1069
1070 assert(cs->cdw <= cdw_max);
1071 }
1072 break;
1073 default:
1074 unreachable("trying to get results of unhandled query type");
1075 }
1076
1077 }
1078
1079 void radv_CmdResetQueryPool(
1080 VkCommandBuffer commandBuffer,
1081 VkQueryPool queryPool,
1082 uint32_t firstQuery,
1083 uint32_t queryCount)
1084 {
1085 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1086 RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);
1087 uint64_t va = cmd_buffer->device->ws->buffer_get_va(pool->bo);
1088
1089 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, pool->bo, 8);
1090
1091 si_cp_dma_clear_buffer(cmd_buffer, va + firstQuery * pool->stride,
1092 queryCount * pool->stride, 0);
1093 if (pool->type == VK_QUERY_TYPE_TIMESTAMP ||
1094 pool->type == VK_QUERY_TYPE_PIPELINE_STATISTICS)
1095 si_cp_dma_clear_buffer(cmd_buffer, va + pool->availability_offset + firstQuery * 4,
1096 queryCount * 4, 0);
1097 }
1098
1099 void radv_CmdBeginQuery(
1100 VkCommandBuffer commandBuffer,
1101 VkQueryPool queryPool,
1102 uint32_t query,
1103 VkQueryControlFlags flags)
1104 {
1105 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1106 RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);
1107 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1108 uint64_t va = cmd_buffer->device->ws->buffer_get_va(pool->bo);
1109 va += pool->stride * query;
1110
1111 cmd_buffer->device->ws->cs_add_buffer(cs, pool->bo, 8);
1112
1113 switch (pool->type) {
1114 case VK_QUERY_TYPE_OCCLUSION:
1115 radeon_check_space(cmd_buffer->device->ws, cs, 7);
1116
1117 ++cmd_buffer->state.active_occlusion_queries;
1118 if (cmd_buffer->state.active_occlusion_queries == 1)
1119 radv_set_db_count_control(cmd_buffer);
1120
1121 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
1122 radeon_emit(cs, EVENT_TYPE(V_028A90_ZPASS_DONE) | EVENT_INDEX(1));
1123 radeon_emit(cs, va);
1124 radeon_emit(cs, va >> 32);
1125 break;
1126 case VK_QUERY_TYPE_PIPELINE_STATISTICS:
1127 radeon_check_space(cmd_buffer->device->ws, cs, 4);
1128
1129 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
1130 radeon_emit(cs, EVENT_TYPE(V_028A90_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
1131 radeon_emit(cs, va);
1132 radeon_emit(cs, va >> 32);
1133 break;
1134 default:
1135 unreachable("beginning unhandled query type");
1136 }
1137 }
1138
1139
1140 void radv_CmdEndQuery(
1141 VkCommandBuffer commandBuffer,
1142 VkQueryPool queryPool,
1143 uint32_t query)
1144 {
1145 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1146 RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);
1147 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1148 uint64_t va = cmd_buffer->device->ws->buffer_get_va(pool->bo);
1149 uint64_t avail_va = va + pool->availability_offset + 4 * query;
1150 va += pool->stride * query;
1151
1152 cmd_buffer->device->ws->cs_add_buffer(cs, pool->bo, 8);
1153
1154 switch (pool->type) {
1155 case VK_QUERY_TYPE_OCCLUSION:
1156 radeon_check_space(cmd_buffer->device->ws, cs, 14);
1157
1158 cmd_buffer->state.active_occlusion_queries--;
1159 if (cmd_buffer->state.active_occlusion_queries == 0)
1160 radv_set_db_count_control(cmd_buffer);
1161
1162 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
1163 radeon_emit(cs, EVENT_TYPE(V_028A90_ZPASS_DONE) | EVENT_INDEX(1));
1164 radeon_emit(cs, va + 8);
1165 radeon_emit(cs, (va + 8) >> 32);
1166
1167 break;
1168 case VK_QUERY_TYPE_PIPELINE_STATISTICS:
1169 radeon_check_space(cmd_buffer->device->ws, cs, 10);
1170
1171 va += pipelinestat_block_size;
1172
1173 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
1174 radeon_emit(cs, EVENT_TYPE(V_028A90_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
1175 radeon_emit(cs, va);
1176 radeon_emit(cs, va >> 32);
1177
1178 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
1179 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
1180 EVENT_INDEX(5));
1181 radeon_emit(cs, avail_va);
1182 radeon_emit(cs, (avail_va >> 32) | EOP_DATA_SEL(1));
1183 radeon_emit(cs, 1);
1184 radeon_emit(cs, 0);
1185 break;
1186 default:
1187 unreachable("ending unhandled query type");
1188 }
1189 }
1190
1191 void radv_CmdWriteTimestamp(
1192 VkCommandBuffer commandBuffer,
1193 VkPipelineStageFlagBits pipelineStage,
1194 VkQueryPool queryPool,
1195 uint32_t query)
1196 {
1197 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1198 RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);
1199 bool mec = radv_cmd_buffer_uses_mec(cmd_buffer);
1200 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1201 uint64_t va = cmd_buffer->device->ws->buffer_get_va(pool->bo);
1202 uint64_t avail_va = va + pool->availability_offset + 4 * query;
1203 uint64_t query_va = va + pool->stride * query;
1204
1205 cmd_buffer->device->ws->cs_add_buffer(cs, pool->bo, 5);
1206
1207 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 12);
1208
1209 if (mec) {
1210 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, 5, 0));
1211 radeon_emit(cs, EVENT_TYPE(V_028A90_BOTTOM_OF_PIPE_TS) | EVENT_INDEX(5));
1212 radeon_emit(cs, 3 << 29);
1213 radeon_emit(cs, query_va);
1214 radeon_emit(cs, query_va >> 32);
1215 radeon_emit(cs, 0);
1216 radeon_emit(cs, 0);
1217 } else {
1218 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
1219 radeon_emit(cs, EVENT_TYPE(V_028A90_BOTTOM_OF_PIPE_TS) | EVENT_INDEX(5));
1220 radeon_emit(cs, query_va);
1221 radeon_emit(cs, (3 << 29) | ((query_va >> 32) & 0xFFFF));
1222 radeon_emit(cs, 0);
1223 radeon_emit(cs, 0);
1224 }
1225
1226 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
1227 radeon_emit(cs, S_370_DST_SEL(mec ? V_370_MEM_ASYNC : V_370_MEMORY_SYNC) |
1228 S_370_WR_CONFIRM(1) |
1229 S_370_ENGINE_SEL(V_370_ME));
1230 radeon_emit(cs, avail_va);
1231 radeon_emit(cs, avail_va >> 32);
1232 radeon_emit(cs, 1);
1233
1234 assert(cmd_buffer->cs->cdw <= cdw_max);
1235 }