src/amd/vulkan/radv_radeon_winsys.h

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * Based on radeon_winsys.h which is:
   6  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   7  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a
  10  * copy of this software and associated documentation files (the "Software"),
  11  * to deal in the Software without restriction, including without limitation
  12  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  13  * and/or sell copies of the Software, and to permit persons to whom the
  14  * Software is furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the next
  17  * paragraph) shall be included in all copies or substantial portions of the
  18  * Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  23  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  24  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  25  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  26  * IN THE SOFTWARE.
  27  */
  28
  29 #ifndef RADV_RADEON_WINSYS_H
  30 #define RADV_RADEON_WINSYS_H
  31
  32 #include <stdint.h>
  33 #include <stdbool.h>
  34 #include <stdlib.h>
  35 #include "main/macros.h"
  36 #include "amd_family.h"
  37
  38 struct radeon_info;
  39 struct ac_surf_info;
  40 struct radeon_surf;
  41
  42 #define FREE(x) free(x)
  43
  44 enum radeon_bo_domain { /* bitfield */
  45         RADEON_DOMAIN_GTT  = 2,
  46         RADEON_DOMAIN_VRAM = 4,
  47         RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
  48 };
  49
  50 enum radeon_bo_flag { /* bitfield */
  51         RADEON_FLAG_GTT_WC =        (1 << 0),
  52         RADEON_FLAG_CPU_ACCESS =    (1 << 1),
  53         RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
  54         RADEON_FLAG_VIRTUAL =       (1 << 3)
  55 };
  56
  57 enum radeon_bo_usage { /* bitfield */
  58         RADEON_USAGE_READ = 2,
  59         RADEON_USAGE_WRITE = 4,
  60         RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE
  61 };
  62
  63 enum ring_type {
  64         RING_GFX = 0,
  65         RING_COMPUTE,
  66         RING_DMA,
  67         RING_UVD,
  68         RING_VCE,
  69         RING_LAST,
  70 };
  71
  72 struct radeon_winsys_cs {
  73         unsigned cdw;  /* Number of used dwords. */
  74         unsigned max_dw; /* Maximum number of dwords. */
  75         uint32_t *buf; /* The base pointer of the chunk. */
  76 };
  77
  78 #define RADEON_SURF_TYPE_MASK                   0xFF
  79 #define RADEON_SURF_TYPE_SHIFT                  0
  80 #define     RADEON_SURF_TYPE_1D                     0
  81 #define     RADEON_SURF_TYPE_2D                     1
  82 #define     RADEON_SURF_TYPE_3D                     2
  83 #define     RADEON_SURF_TYPE_CUBEMAP                3
  84 #define     RADEON_SURF_TYPE_1D_ARRAY               4
  85 #define     RADEON_SURF_TYPE_2D_ARRAY               5
  86 #define RADEON_SURF_MODE_MASK                   0xFF
  87 #define RADEON_SURF_MODE_SHIFT                  8
  88
  89 #define RADEON_SURF_GET(v, field)   (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
  90 #define RADEON_SURF_SET(v, field)   (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
  91 #define RADEON_SURF_CLR(v, field)   ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
  92
  93 enum radeon_bo_layout {
  94         RADEON_LAYOUT_LINEAR = 0,
  95         RADEON_LAYOUT_TILED,
  96         RADEON_LAYOUT_SQUARETILED,
  97
  98         RADEON_LAYOUT_UNKNOWN
  99 };
 100
 101 /* Tiling info for display code, DRI sharing, and other data. */
 102 struct radeon_bo_metadata {
 103         /* Tiling flags describing the texture layout for display code
 104          * and DRI sharing.
 105          */
 106         union {
 107                 struct {
 108                         enum radeon_bo_layout   microtile;
 109                         enum radeon_bo_layout   macrotile;
 110                         unsigned                pipe_config;
 111                         unsigned                bankw;
 112                         unsigned                bankh;
 113                         unsigned                tile_split;
 114                         unsigned                mtilea;
 115                         unsigned                num_banks;
 116                         unsigned                stride;
 117                         bool                    scanout;
 118                 } legacy;
 119
 120                 struct {
 121                         /* surface flags */
 122                         unsigned swizzle_mode:5;
 123                 } gfx9;
 124         } u;
 125
 126         /* Additional metadata associated with the buffer, in bytes.
 127          * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
 128          * Supported by amdgpu only.
 129          */
 130         uint32_t                size_metadata;
 131         uint32_t                metadata[64];
 132 };
 133
 134 struct radeon_winsys_bo;
 135 struct radeon_winsys_fence;
 136 struct radeon_winsys_sem;
 137
 138 struct radeon_winsys {
 139         void (*destroy)(struct radeon_winsys *ws);
 140
 141         void (*query_info)(struct radeon_winsys *ws,
 142                            struct radeon_info *info);
 143
 144         struct radeon_winsys_bo *(*buffer_create)(struct radeon_winsys *ws,
 145                                                   uint64_t size,
 146                                                   unsigned alignment,
 147                                                   enum radeon_bo_domain domain,
 148                                                   enum radeon_bo_flag flags);
 149
 150         void (*buffer_destroy)(struct radeon_winsys_bo *bo);
 151         void *(*buffer_map)(struct radeon_winsys_bo *bo);
 152
 153         struct radeon_winsys_bo *(*buffer_from_fd)(struct radeon_winsys *ws,
 154                                                    int fd,
 155                                                    unsigned *stride, unsigned *offset);
 156
 157         bool (*buffer_get_fd)(struct radeon_winsys *ws,
 158                               struct radeon_winsys_bo *bo,
 159                               int *fd);
 160
 161         void (*buffer_unmap)(struct radeon_winsys_bo *bo);
 162
 163         uint64_t (*buffer_get_va)(struct radeon_winsys_bo *bo);
 164
 165         void (*buffer_set_metadata)(struct radeon_winsys_bo *bo,
 166                                     struct radeon_bo_metadata *md);
 167
 168         void (*buffer_virtual_bind)(struct radeon_winsys_bo *parent,
 169                                     uint64_t offset, uint64_t size,
 170                                     struct radeon_winsys_bo *bo, uint64_t bo_offset);
 171         struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws);
 172         void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
 173
 174         bool (*ctx_wait_idle)(struct radeon_winsys_ctx *ctx,
 175                               enum ring_type ring_type, int ring_index);
 176
 177         struct radeon_winsys_cs *(*cs_create)(struct radeon_winsys *ws,
 178                                               enum ring_type ring_type);
 179
 180         void (*cs_destroy)(struct radeon_winsys_cs *cs);
 181
 182         void (*cs_reset)(struct radeon_winsys_cs *cs);
 183
 184         bool (*cs_finalize)(struct radeon_winsys_cs *cs);
 185
 186         void (*cs_grow)(struct radeon_winsys_cs * cs, size_t min_size);
 187
 188         int (*cs_submit)(struct radeon_winsys_ctx *ctx,
 189                          int queue_index,
 190                          struct radeon_winsys_cs **cs_array,
 191                          unsigned cs_count,
 192                          struct radeon_winsys_cs *initial_preamble_cs,
 193                          struct radeon_winsys_cs *continue_preamble_cs,
 194                          struct radeon_winsys_sem **wait_sem,
 195                          unsigned wait_sem_count,
 196                          struct radeon_winsys_sem **signal_sem,
 197                          unsigned signal_sem_count,
 198                          bool can_patch,
 199                          struct radeon_winsys_fence *fence);
 200
 201         void (*cs_add_buffer)(struct radeon_winsys_cs *cs,
 202                               struct radeon_winsys_bo *bo,
 203                               uint8_t priority);
 204
 205         void (*cs_execute_secondary)(struct radeon_winsys_cs *parent,
 206                                     struct radeon_winsys_cs *child);
 207
 208         void (*cs_dump)(struct radeon_winsys_cs *cs, FILE* file, uint32_t trace_id);
 209
 210         int (*surface_init)(struct radeon_winsys *ws,
 211                             const struct ac_surf_info *surf_info,
 212                             struct radeon_surf *surf);
 213
 214         int (*surface_best)(struct radeon_winsys *ws,
 215                             struct radeon_surf *surf);
 216
 217         struct radeon_winsys_fence *(*create_fence)();
 218         void (*destroy_fence)(struct radeon_winsys_fence *fence);
 219         bool (*fence_wait)(struct radeon_winsys *ws,
 220                            struct radeon_winsys_fence *fence,
 221                            bool absolute,
 222                            uint64_t timeout);
 223
 224         /* old semaphores - non shareable */
 225         struct radeon_winsys_sem *(*create_sem)(struct radeon_winsys *ws);
 226         void (*destroy_sem)(struct radeon_winsys_sem *sem);
 227
 228         /* new shareable sync objects */
 229         int (*create_syncobj)(struct radeon_winsys *ws, uint32_t *handle);
 230         void (*destroy_syncobj)(struct radeon_winsys *ws, uint32_t handle);
 231
 232         int (*export_syncobj)(struct radeon_winsys *ws, uint32_t syncobj, int *fd);
 233         int (*import_syncobj)(struct radeon_winsys *ws, int fd, uint32_t *syncobj);
 234
 235 };
 236
 237 static inline void radeon_emit(struct radeon_winsys_cs *cs, uint32_t value)
 238 {
 239         cs->buf[cs->cdw++] = value;
 240 }
 241
 242 static inline void radeon_emit_array(struct radeon_winsys_cs *cs,
 243                                      const uint32_t *values, unsigned count)
 244 {
 245         memcpy(cs->buf + cs->cdw, values, count * 4);
 246         cs->cdw += count;
 247 }
 248
 249 #endif /* RADV_RADEON_WINSYS_H */