src/amd/vulkan/radv_radeon_winsys.h

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * Based on radeon_winsys.h which is:
   6  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   7  * Copyright 2010 Marek Olšák <maraeo@gmail.com>
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a
  10  * copy of this software and associated documentation files (the "Software"),
  11  * to deal in the Software without restriction, including without limitation
  12  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  13  * and/or sell copies of the Software, and to permit persons to whom the
  14  * Software is furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the next
  17  * paragraph) shall be included in all copies or substantial portions of the
  18  * Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  23  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  24  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  25  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  26  * IN THE SOFTWARE.
  27  */
  28
  29 #ifndef RADV_RADEON_WINSYS_H
  30 #define RADV_RADEON_WINSYS_H
  31
  32 #include <stdint.h>
  33 #include <stdbool.h>
  34 #include <stdlib.h>
  35 #include "main/macros.h"
  36 #include "amd_family.h"
  37
  38 struct radeon_info;
  39 struct ac_surf_info;
  40 struct radeon_surf;
  41
  42 #define FREE(x) free(x)
  43
  44 enum radeon_bo_domain { /* bitfield */
  45         RADEON_DOMAIN_GTT  = 2,
  46         RADEON_DOMAIN_VRAM = 4,
  47         RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT
  48 };
  49
  50 enum radeon_bo_flag { /* bitfield */
  51         RADEON_FLAG_GTT_WC =        (1 << 0),
  52         RADEON_FLAG_CPU_ACCESS =    (1 << 1),
  53         RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
  54         RADEON_FLAG_VIRTUAL =       (1 << 3),
  55         RADEON_FLAG_VA_UNCACHED =   (1 << 4),
  56 };
  57
  58 enum radeon_bo_usage { /* bitfield */
  59         RADEON_USAGE_READ = 2,
  60         RADEON_USAGE_WRITE = 4,
  61         RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE
  62 };
  63
  64 enum ring_type {
  65         RING_GFX = 0,
  66         RING_COMPUTE,
  67         RING_DMA,
  68         RING_UVD,
  69         RING_VCE,
  70         RING_LAST,
  71 };
  72
  73 enum radeon_ctx_priority {
  74         RADEON_CTX_PRIORITY_INVALID = -1,
  75         RADEON_CTX_PRIORITY_LOW = 0,
  76         RADEON_CTX_PRIORITY_MEDIUM,
  77         RADEON_CTX_PRIORITY_HIGH,
  78         RADEON_CTX_PRIORITY_REALTIME,
  79 };
  80
  81 struct radeon_winsys_cs {
  82         unsigned cdw;  /* Number of used dwords. */
  83         unsigned max_dw; /* Maximum number of dwords. */
  84         uint32_t *buf; /* The base pointer of the chunk. */
  85 };
  86
  87 #define RADEON_SURF_TYPE_MASK                   0xFF
  88 #define RADEON_SURF_TYPE_SHIFT                  0
  89 #define     RADEON_SURF_TYPE_1D                     0
  90 #define     RADEON_SURF_TYPE_2D                     1
  91 #define     RADEON_SURF_TYPE_3D                     2
  92 #define     RADEON_SURF_TYPE_CUBEMAP                3
  93 #define     RADEON_SURF_TYPE_1D_ARRAY               4
  94 #define     RADEON_SURF_TYPE_2D_ARRAY               5
  95 #define RADEON_SURF_MODE_MASK                   0xFF
  96 #define RADEON_SURF_MODE_SHIFT                  8
  97
  98 #define RADEON_SURF_GET(v, field)   (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
  99 #define RADEON_SURF_SET(v, field)   (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
 100 #define RADEON_SURF_CLR(v, field)   ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
 101
 102 enum radeon_bo_layout {
 103         RADEON_LAYOUT_LINEAR = 0,
 104         RADEON_LAYOUT_TILED,
 105         RADEON_LAYOUT_SQUARETILED,
 106
 107         RADEON_LAYOUT_UNKNOWN
 108 };
 109
 110 /* Tiling info for display code, DRI sharing, and other data. */
 111 struct radeon_bo_metadata {
 112         /* Tiling flags describing the texture layout for display code
 113          * and DRI sharing.
 114          */
 115         union {
 116                 struct {
 117                         enum radeon_bo_layout   microtile;
 118                         enum radeon_bo_layout   macrotile;
 119                         unsigned                pipe_config;
 120                         unsigned                bankw;
 121                         unsigned                bankh;
 122                         unsigned                tile_split;
 123                         unsigned                mtilea;
 124                         unsigned                num_banks;
 125                         unsigned                stride;
 126                         bool                    scanout;
 127                 } legacy;
 128
 129                 struct {
 130                         /* surface flags */
 131                         unsigned swizzle_mode:5;
 132                 } gfx9;
 133         } u;
 134
 135         /* Additional metadata associated with the buffer, in bytes.
 136          * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
 137          * Supported by amdgpu only.
 138          */
 139         uint32_t                size_metadata;
 140         uint32_t                metadata[64];
 141 };
 142
 143 uint32_t syncobj_handle;
 144 struct radeon_winsys_fence;
 145
 146 struct radeon_winsys_bo {
 147         uint64_t va;
 148 };
 149 struct radv_winsys_sem_counts {
 150         uint32_t syncobj_count;
 151         uint32_t sem_count;
 152         uint32_t *syncobj;
 153         struct radeon_winsys_sem **sem;
 154 };
 155
 156 struct radv_winsys_sem_info {
 157         bool cs_emit_signal;
 158         bool cs_emit_wait;
 159         struct radv_winsys_sem_counts wait;
 160         struct radv_winsys_sem_counts signal;
 161 };
 162
 163 struct radeon_winsys {
 164         void (*destroy)(struct radeon_winsys *ws);
 165
 166         void (*query_info)(struct radeon_winsys *ws,
 167                            struct radeon_info *info);
 168
 169         bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
 170                                unsigned num_registers, uint32_t *out);
 171
 172         const char *(*get_chip_name)(struct radeon_winsys *ws);
 173
 174         struct radeon_winsys_bo *(*buffer_create)(struct radeon_winsys *ws,
 175                                                   uint64_t size,
 176                                                   unsigned alignment,
 177                                                   enum radeon_bo_domain domain,
 178                                                   enum radeon_bo_flag flags);
 179
 180         void (*buffer_destroy)(struct radeon_winsys_bo *bo);
 181         void *(*buffer_map)(struct radeon_winsys_bo *bo);
 182
 183         struct radeon_winsys_bo *(*buffer_from_fd)(struct radeon_winsys *ws,
 184                                                    int fd,
 185                                                    unsigned *stride, unsigned *offset);
 186
 187         bool (*buffer_get_fd)(struct radeon_winsys *ws,
 188                               struct radeon_winsys_bo *bo,
 189                               int *fd);
 190
 191         void (*buffer_unmap)(struct radeon_winsys_bo *bo);
 192
 193         void (*buffer_set_metadata)(struct radeon_winsys_bo *bo,
 194                                     struct radeon_bo_metadata *md);
 195
 196         void (*buffer_virtual_bind)(struct radeon_winsys_bo *parent,
 197                                     uint64_t offset, uint64_t size,
 198                                     struct radeon_winsys_bo *bo, uint64_t bo_offset);
 199         struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws,
 200                                                 enum radeon_ctx_priority priority);
 201         void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
 202
 203         bool (*ctx_wait_idle)(struct radeon_winsys_ctx *ctx,
 204                               enum ring_type ring_type, int ring_index);
 205
 206         struct radeon_winsys_cs *(*cs_create)(struct radeon_winsys *ws,
 207                                               enum ring_type ring_type);
 208
 209         void (*cs_destroy)(struct radeon_winsys_cs *cs);
 210
 211         void (*cs_reset)(struct radeon_winsys_cs *cs);
 212
 213         bool (*cs_finalize)(struct radeon_winsys_cs *cs);
 214
 215         void (*cs_grow)(struct radeon_winsys_cs * cs, size_t min_size);
 216
 217         int (*cs_submit)(struct radeon_winsys_ctx *ctx,
 218                          int queue_index,
 219                          struct radeon_winsys_cs **cs_array,
 220                          unsigned cs_count,
 221                          struct radeon_winsys_cs *initial_preamble_cs,
 222                          struct radeon_winsys_cs *continue_preamble_cs,
 223                          struct radv_winsys_sem_info *sem_info,
 224                          bool can_patch,
 225                          struct radeon_winsys_fence *fence);
 226
 227         void (*cs_add_buffer)(struct radeon_winsys_cs *cs,
 228                               struct radeon_winsys_bo *bo,
 229                               uint8_t priority);
 230
 231         void (*cs_execute_secondary)(struct radeon_winsys_cs *parent,
 232                                     struct radeon_winsys_cs *child);
 233
 234         void (*cs_dump)(struct radeon_winsys_cs *cs, FILE* file, const int *trace_ids, int trace_id_count);
 235
 236         int (*surface_init)(struct radeon_winsys *ws,
 237                             const struct ac_surf_info *surf_info,
 238                             struct radeon_surf *surf);
 239
 240         int (*surface_best)(struct radeon_winsys *ws,
 241                             struct radeon_surf *surf);
 242
 243         struct radeon_winsys_fence *(*create_fence)();
 244         void (*destroy_fence)(struct radeon_winsys_fence *fence);
 245         bool (*fence_wait)(struct radeon_winsys *ws,
 246                            struct radeon_winsys_fence *fence,
 247                            bool absolute,
 248                            uint64_t timeout);
 249
 250         /* old semaphores - non shareable */
 251         struct radeon_winsys_sem *(*create_sem)(struct radeon_winsys *ws);
 252         void (*destroy_sem)(struct radeon_winsys_sem *sem);
 253
 254         /* new shareable sync objects */
 255         int (*create_syncobj)(struct radeon_winsys *ws, uint32_t *handle);
 256         void (*destroy_syncobj)(struct radeon_winsys *ws, uint32_t handle);
 257
 258         int (*export_syncobj)(struct radeon_winsys *ws, uint32_t syncobj, int *fd);
 259         int (*import_syncobj)(struct radeon_winsys *ws, int fd, uint32_t *syncobj);
 260
 261 };
 262
 263 static inline void radeon_emit(struct radeon_winsys_cs *cs, uint32_t value)
 264 {
 265         cs->buf[cs->cdw++] = value;
 266 }
 267
 268 static inline void radeon_emit_array(struct radeon_winsys_cs *cs,
 269                                      const uint32_t *values, unsigned count)
 270 {
 271         memcpy(cs->buf + cs->cdw, values, count * 4);
 272         cs->cdw += count;
 273 }
 274
 275 static inline uint64_t radv_buffer_get_va(struct radeon_winsys_bo *bo)
 276 {
 277         return bo->va;
 278 }
 279
 280 #endif /* RADV_RADEON_WINSYS_H */