src/amd/vulkan/radv_rgp.c

   1 /*
   2  * Copyright © 2020 Valve Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23 #include <stdbool.h>
  24 #include <string.h>
  25 #include <unistd.h>
  26 #include "radv_private.h"
  27
  28 #include "util/u_process.h"
  29
  30 #include <amdgpu_drm.h>
  31
  32 #define SQTT_FILE_MAGIC_NUMBER 0x50303042
  33 #define SQTT_FILE_VERSION_MAJOR 1
  34 #define SQTT_FILE_VERSION_MINOR 4
  35
  36 #define SQTT_GPU_NAME_MAX_SIZE 256
  37 #define SQTT_MAX_NUM_SE 32
  38 #define SQTT_SA_PER_SE 2
  39
  40 enum sqtt_version {
  41         SQTT_VERSION_NONE = 0x0,
  42         SQTT_VERSION_1_0  = 0x1,
  43         SQTT_VERSION_1_1  = 0x2,
  44         SQTT_VERSION_2_0  = 0x3, /* GFX6 */
  45         SQTT_VERSION_2_1  = 0x4, /* GFX7 */
  46         SQTT_VERSION_2_2  = 0x5, /* GFX8 */
  47         SQTT_VERSION_2_3  = 0x6, /* GFX9 */
  48         SQTT_VERSION_2_4  = 0x7  /* GFX10 */
  49 };
  50
  51 /**
  52  * SQTT chunks.
  53  */
  54 enum sqtt_file_chunk_type {
  55         SQTT_FILE_CHUNK_TYPE_ASIC_INFO,
  56         SQTT_FILE_CHUNK_TYPE_SQTT_DESC,
  57         SQTT_FILE_CHUNK_TYPE_SQTT_DATA,
  58         SQTT_FILE_CHUNK_TYPE_API_INFO,
  59         SQTT_FILE_CHUNK_TYPE_ISA_DATABASE,
  60         SQTT_FILE_CHUNK_TYPE_QUEUE_EVENT_TIMINGS,
  61         SQTT_FILE_CHUNK_TYPE_CLOCK_CALIBRATION,
  62         SQTT_FILE_CHUNK_TYPE_CPU_INFO,
  63         SQTT_FILE_CHUNK_TYPE_SPM_DB,
  64         SQTT_FILE_CHUNK_TYPE_CODE_OBJECT_DATABASE,
  65         SQTT_FILE_CHUNK_TYPE_CODE_OBJECT_LOADER_EVENTS,
  66         SQTT_FILE_CHUNK_TYPE_PSO_CORRELATION,
  67         SQTT_FILE_CHUNK_TYPE_INSTRUMENTATION_TABLE,
  68         SQTT_FILE_CHUNK_TYPE_COUNT
  69 };
  70
  71 struct sqtt_file_chunk_id {
  72         enum sqtt_file_chunk_type type : 8;
  73         int32_t index : 8;
  74         int32_t reserved : 16;
  75 };
  76
  77 struct sqtt_file_chunk_header {
  78         struct sqtt_file_chunk_id chunk_id;
  79         uint16_t minor_version;
  80         uint16_t major_version;
  81         int32_t size_in_bytes;
  82         int32_t padding;
  83 };
  84
  85 /**
  86  * SQTT file header.
  87  */
  88 struct sqtt_file_header_flags {
  89         union {
  90                 struct {
  91                         int32_t is_semaphore_queue_timing_etw : 1;
  92                         int32_t no_queue_semaphore_timestamps : 1;
  93                         int32_t reserved : 30;
  94                 };
  95
  96                 uint32_t value;
  97         };
  98 };
  99
 100 struct sqtt_file_header {
 101         uint32_t magic_number;
 102         uint32_t version_major;
 103         uint32_t version_minor;
 104         struct sqtt_file_header_flags flags;
 105         int32_t chunk_offset;
 106         int32_t second;
 107         int32_t minute;
 108         int32_t hour;
 109         int32_t day_in_month;
 110         int32_t month;
 111         int32_t year;
 112         int32_t day_in_week;
 113         int32_t day_in_year;
 114         int32_t is_daylight_savings;
 115 };
 116
 117 static_assert(sizeof(struct sqtt_file_header) == 56,
 118               "sqtt_file_header doesn't match RGP spec");
 119
 120 static void
 121 radv_sqtt_fill_header(struct sqtt_file_header *header)
 122 {
 123         struct tm *timep, result;
 124         time_t raw_time;
 125
 126         header->magic_number = SQTT_FILE_MAGIC_NUMBER;
 127         header->version_major = SQTT_FILE_VERSION_MAJOR;
 128         header->version_minor = SQTT_FILE_VERSION_MINOR;
 129         header->flags.value = 0;
 130         header->flags.is_semaphore_queue_timing_etw = 1;
 131         header->flags.no_queue_semaphore_timestamps = 0;
 132         header->chunk_offset = sizeof(*header);
 133
 134         time(&raw_time);
 135         timep = localtime_r(&raw_time, &result);
 136
 137         header->second = timep->tm_sec;
 138         header->minute = timep->tm_min;
 139         header->hour = timep->tm_hour;
 140         header->day_in_month = timep->tm_mday;
 141         header->month = timep->tm_mon;
 142         header->year = timep->tm_year;
 143         header->day_in_week = timep->tm_wday;
 144         header->day_in_year = timep->tm_yday;
 145         header->is_daylight_savings = timep->tm_isdst;
 146 }
 147
 148 /**
 149  * SQTT CPU info.
 150  */
 151 struct sqtt_file_chunk_cpu_info {
 152         struct sqtt_file_chunk_header header;
 153         uint32_t vendor_id[4];
 154         uint32_t processor_brand[12];
 155         uint32_t reserved[2];
 156         uint64_t cpu_timestamp_freq;
 157         uint32_t clock_speed;
 158         uint32_t num_logical_cores;
 159         uint32_t num_physical_cores;
 160         uint32_t system_ram_size;
 161 };
 162
 163 static_assert(sizeof(struct sqtt_file_chunk_cpu_info) == 112,
 164               "sqtt_file_chunk_cpu_info doesn't match RGP spec");
 165
 166 static void
 167 radv_sqtt_fill_cpu_info(struct sqtt_file_chunk_cpu_info *chunk)
 168 {
 169         chunk->header.chunk_id.type = SQTT_FILE_CHUNK_TYPE_CPU_INFO;
 170         chunk->header.chunk_id.index = 0;
 171         chunk->header.major_version = 0;
 172         chunk->header.minor_version = 0;
 173         chunk->header.size_in_bytes = sizeof(*chunk);
 174
 175         chunk->cpu_timestamp_freq = 1000000000; /* tick set to 1ns */
 176
 177         /* TODO: fill with real info. */
 178
 179         strncpy((char *)chunk->vendor_id, "Unknown", sizeof(chunk->vendor_id));
 180         strncpy((char *)chunk->processor_brand, "Unknown", sizeof(chunk->processor_brand));
 181         chunk->clock_speed = 0;
 182         chunk->num_logical_cores = 0;
 183         chunk->num_physical_cores = 0;
 184         chunk->system_ram_size = 0;
 185 }
 186
 187 /**
 188  * SQTT ASIC info.
 189  */
 190 enum sqtt_file_chunk_asic_info_flags
 191 {
 192         SQTT_FILE_CHUNK_ASIC_INFO_FLAG_SC_PACKER_NUMBERING      = (1 << 0),
 193         SQTT_FILE_CHUNK_ASIC_INFO_FLAG_PS1_EVENT_TOKENS_ENABLED = (1 << 1)
 194 };
 195
 196 enum sqtt_gpu_type {
 197         SQTT_GPU_TYPE_UNKNOWN    = 0x0,
 198         SQTT_GPU_TYPE_INTEGRATED = 0x1,
 199         SQTT_GPU_TYPE_DISCRETE   = 0x2,
 200         SQTT_GPU_TYPE_VIRTUAL    = 0x3
 201 };
 202
 203 enum sqtt_gfxip_level {
 204         SQTT_GFXIP_LEVEL_NONE       = 0x0,
 205         SQTT_GFXIP_LEVEL_GFXIP_6    = 0x1,
 206         SQTT_GFXIP_LEVEL_GFXIP_7    = 0x2,
 207         SQTT_GFXIP_LEVEL_GFXIP_8    = 0x3,
 208         SQTT_GFXIP_LEVEL_GFXIP_8_1  = 0x4,
 209         SQTT_GFXIP_LEVEL_GFXIP_9    = 0x5,
 210         SQTT_GFXIP_LEVEL_GFXIP_10_1 = 0x7,
 211 };
 212
 213 enum sqtt_memory_type {
 214         SQTT_MEMORY_TYPE_UNKNOWN = 0x0,
 215         SQTT_MEMORY_TYPE_DDR     = 0x1,
 216         SQTT_MEMORY_TYPE_DDR2    = 0x2,
 217         SQTT_MEMORY_TYPE_DDR3    = 0x3,
 218         SQTT_MEMORY_TYPE_DDR4    = 0x4,
 219         SQTT_MEMORY_TYPE_GDDR3   = 0x10,
 220         SQTT_MEMORY_TYPE_GDDR4   = 0x11,
 221         SQTT_MEMORY_TYPE_GDDR5   = 0x12,
 222         SQTT_MEMORY_TYPE_GDDR6   = 0x13,
 223         SQTT_MEMORY_TYPE_HBM     = 0x20,
 224         SQTT_MEMORY_TYPE_HBM2    = 0x21,
 225         SQTT_MEMORY_TYPE_HBM3    = 0x22,
 226 };
 227
 228 struct sqtt_file_chunk_asic_info {
 229         struct sqtt_file_chunk_header header;
 230         uint64_t flags;
 231         uint64_t trace_shader_core_clock;
 232         uint64_t trace_memory_clock;
 233         int32_t device_id;
 234         int32_t device_revision_id;
 235         int32_t vgprs_per_simd;
 236         int32_t sgprs_per_simd;
 237         int32_t shader_engines;
 238         int32_t compute_unit_per_shader_engine;
 239         int32_t simd_per_compute_unit;
 240         int32_t wavefronts_per_simd;
 241         int32_t minimum_vgpr_alloc;
 242         int32_t vgpr_alloc_granularity;
 243         int32_t minimum_sgpr_alloc;
 244         int32_t sgpr_alloc_granularity;
 245         int32_t hardware_contexts;
 246         enum sqtt_gpu_type gpu_type;
 247         enum sqtt_gfxip_level gfxip_level;
 248         int32_t gpu_index;
 249         int32_t gds_size;
 250         int32_t gds_per_shader_engine;
 251         int32_t ce_ram_size;
 252         int32_t ce_ram_size_graphics;
 253         int32_t ce_ram_size_compute;
 254         int32_t max_number_of_dedicated_cus;
 255         int64_t vram_size;
 256         int32_t vram_bus_width;
 257         int32_t l2_cache_size;
 258         int32_t l1_cache_size;
 259         int32_t lds_size;
 260         char gpu_name[SQTT_GPU_NAME_MAX_SIZE];
 261         float alu_per_clock;
 262         float texture_per_clock;
 263         float prims_per_clock;
 264         float pixels_per_clock;
 265         uint64_t gpu_timestamp_frequency;
 266         uint64_t max_shader_core_clock;
 267         uint64_t max_memory_clock;
 268         uint32_t memory_ops_per_clock;
 269         enum sqtt_memory_type memory_chip_type;
 270         uint32_t lds_granularity;
 271         uint16_t cu_mask[SQTT_MAX_NUM_SE][SQTT_SA_PER_SE];
 272         char reserved1[128];
 273         char padding[4];
 274 };
 275
 276 static_assert(sizeof(struct sqtt_file_chunk_asic_info) == 720,
 277               "sqtt_file_chunk_asic_info doesn't match RGP spec");
 278
 279 static enum sqtt_gfxip_level
 280 radv_chip_class_to_sqtt_gfxip_level(enum chip_class chip_class)
 281 {
 282         switch (chip_class) {
 283         case GFX6:
 284                 return SQTT_GFXIP_LEVEL_GFXIP_6;
 285         case GFX7:
 286                 return SQTT_GFXIP_LEVEL_GFXIP_7;
 287         case GFX8:
 288                 return SQTT_GFXIP_LEVEL_GFXIP_8;
 289         case GFX9:
 290                 return SQTT_GFXIP_LEVEL_GFXIP_9;
 291         case GFX10:
 292                 return SQTT_GFXIP_LEVEL_GFXIP_10_1;
 293         default:
 294                 unreachable("Invalid chip class");
 295         }
 296 }
 297
 298 static enum sqtt_memory_type
 299 radv_vram_type_to_sqtt_memory_type(uint32_t vram_type)
 300 {
 301         switch (vram_type) {
 302         case AMDGPU_VRAM_TYPE_UNKNOWN:
 303                 return SQTT_MEMORY_TYPE_UNKNOWN;
 304         case AMDGPU_VRAM_TYPE_DDR2:
 305                 return SQTT_MEMORY_TYPE_DDR2;
 306         case AMDGPU_VRAM_TYPE_DDR3:
 307                 return SQTT_MEMORY_TYPE_DDR3;
 308         case AMDGPU_VRAM_TYPE_DDR4:
 309                 return SQTT_MEMORY_TYPE_DDR4;
 310         case AMDGPU_VRAM_TYPE_GDDR5:
 311                 return SQTT_MEMORY_TYPE_GDDR5;
 312         case AMDGPU_VRAM_TYPE_HBM:
 313                 return SQTT_MEMORY_TYPE_HBM;
 314         case AMDGPU_VRAM_TYPE_GDDR6:
 315                 return SQTT_MEMORY_TYPE_GDDR6;
 316         case AMDGPU_VRAM_TYPE_GDDR1:
 317         case AMDGPU_VRAM_TYPE_GDDR3:
 318         case AMDGPU_VRAM_TYPE_GDDR4:
 319         default:
 320                 unreachable("Invalid vram type");
 321         }
 322 }
 323
 324 static void
 325 radv_fill_sqtt_asic_info(struct radv_device *device,
 326                          struct sqtt_file_chunk_asic_info *chunk)
 327 {
 328         struct radeon_info *rad_info = &device->physical_device->rad_info;
 329
 330         chunk->header.chunk_id.type = SQTT_FILE_CHUNK_TYPE_ASIC_INFO;
 331         chunk->header.chunk_id.index = 0;
 332         chunk->header.major_version = 0;
 333         chunk->header.minor_version = 4;
 334         chunk->header.size_in_bytes = sizeof(*chunk);
 335
 336         chunk->flags = 0;
 337
 338         /* All chips older than GFX9 are affected by the "SPI not
 339          * differentiating pkr_id for newwave commands" bug.
 340          */
 341         if (rad_info->chip_class < GFX9)
 342                 chunk->flags |= SQTT_FILE_CHUNK_ASIC_INFO_FLAG_SC_PACKER_NUMBERING;
 343
 344         /* Only FIJI and GFX9+ support PS1 events. */
 345         if (rad_info->family == CHIP_FIJI || rad_info->chip_class >= GFX9)
 346                 chunk->flags |= SQTT_FILE_CHUNK_ASIC_INFO_FLAG_PS1_EVENT_TOKENS_ENABLED;
 347
 348         chunk->trace_shader_core_clock = rad_info->max_shader_clock * 1000000;
 349         chunk->trace_memory_clock = rad_info->max_memory_clock * 1000000;
 350
 351         chunk->device_id = rad_info->pci_id;
 352         chunk->device_revision_id = rad_info->pci_rev_id;
 353         chunk->vgprs_per_simd = rad_info->num_physical_wave64_vgprs_per_simd;
 354         chunk->sgprs_per_simd = rad_info->num_physical_sgprs_per_simd;
 355         chunk->shader_engines = rad_info->max_se;
 356         chunk->compute_unit_per_shader_engine = rad_info->num_good_cu_per_sh;
 357         chunk->simd_per_compute_unit = rad_info->num_simd_per_compute_unit;
 358         chunk->wavefronts_per_simd = rad_info->max_wave64_per_simd;
 359
 360         chunk->minimum_vgpr_alloc = rad_info->min_vgpr_alloc;
 361         chunk->vgpr_alloc_granularity = rad_info->wave64_vgpr_alloc_granularity;
 362         chunk->minimum_sgpr_alloc = rad_info->min_sgpr_alloc;
 363         chunk->sgpr_alloc_granularity = rad_info->sgpr_alloc_granularity;
 364
 365         chunk->hardware_contexts = 8;
 366         chunk->gpu_type = rad_info->has_dedicated_vram ? SQTT_GPU_TYPE_DISCRETE : SQTT_GPU_TYPE_INTEGRATED;
 367         chunk->gfxip_level = radv_chip_class_to_sqtt_gfxip_level(rad_info->chip_class);
 368         chunk->gpu_index = 0;
 369
 370         chunk->max_number_of_dedicated_cus = 0;
 371         chunk->ce_ram_size = rad_info->ce_ram_size;
 372         chunk->ce_ram_size_graphics = 0;
 373         chunk->ce_ram_size_compute = 0;
 374
 375         chunk->vram_bus_width = rad_info->vram_bit_width;
 376         chunk->vram_size = rad_info->vram_size;
 377         chunk->l2_cache_size = rad_info->l2_cache_size;
 378         chunk->l1_cache_size = rad_info->l1_cache_size;
 379         chunk->lds_size = rad_info->lds_size_per_workgroup;
 380
 381         strncpy(chunk->gpu_name, device->physical_device->name, SQTT_GPU_NAME_MAX_SIZE);
 382
 383         chunk->alu_per_clock = 0.0;
 384         chunk->texture_per_clock = 0.0;
 385         chunk->prims_per_clock = 0.0;
 386         chunk->pixels_per_clock = 0.0;
 387
 388         chunk->gpu_timestamp_frequency = rad_info->clock_crystal_freq * 1000;
 389         chunk->max_shader_core_clock = rad_info->max_shader_clock * 1000000;
 390         chunk->max_memory_clock = rad_info->max_memory_clock * 1000000;
 391         chunk->memory_ops_per_clock = 0;
 392         chunk->memory_chip_type = radv_vram_type_to_sqtt_memory_type(rad_info->vram_type);
 393         chunk->lds_granularity = rad_info->lds_granularity;
 394
 395         for (unsigned se = 0; se < 32; se++) {
 396                 for (unsigned sa = 0; sa < 2; sa++) {
 397                         chunk->cu_mask[se][sa] = 0; /* TODO */
 398                 }
 399         }
 400 }
 401
 402 /**
 403  * SQTT API info.
 404  */
 405 enum sqtt_api_type {
 406         SQTT_API_TYPE_DIRECTX_12,
 407         SQTT_API_TYPE_VULKAN,
 408         SQTT_API_TYPE_GENERIC,
 409         SQTT_API_TYPE_OPENCL
 410 };
 411
 412 enum sqtt_instruction_trace_mode
 413 {
 414         SQTT_INSTRUCTION_TRACE_DISABLED   = 0x0,
 415         SQTT_INSTRUCTION_TRACE_FULL_FRAME = 0x1,
 416         SQTT_INSTRUCTION_TRACE_API_PSO    = 0x2,
 417 };
 418
 419 enum sqtt_profiling_mode {
 420         SQTT_PROFILING_MODE_PRESENT      = 0x0,
 421         SQTT_PROFILING_MODE_USER_MARKERS = 0x1,
 422         SQTT_PROFILING_MODE_INDEX        = 0x2,
 423         SQTT_PROFILING_MODE_TAG          = 0x3,
 424 };
 425
 426 union sqtt_profiling_mode_data {
 427         struct {
 428                 char start[256];
 429                 char end[256];
 430         } user_marker_profiling_data;
 431
 432         struct {
 433                 uint32_t start;
 434                 uint32_t end;
 435         } index_profiling_data;
 436
 437         struct {
 438                 uint32_t begin_hi;
 439                 uint32_t begin_lo;
 440                 uint32_t end_hi;
 441                 uint32_t end_lo;
 442         } tag_profiling_data;
 443 };
 444
 445 union sqtt_instruction_trace_data {
 446         struct {
 447                 uint64_t api_pso_filter;
 448         } api_pso_data;
 449
 450         struct {
 451                 char start[256];
 452                 char end[256];
 453         } user_marker_data;
 454 };
 455
 456 struct sqtt_file_chunk_api_info {
 457         struct sqtt_file_chunk_header header;
 458         enum sqtt_api_type api_type;
 459         uint16_t major_version;
 460         uint16_t minor_version;
 461         enum sqtt_profiling_mode profiling_mode;
 462         uint32_t reserved;
 463         union sqtt_profiling_mode_data profiling_mode_data;
 464         enum sqtt_instruction_trace_mode instruction_trace_mode;
 465         uint32_t reserved2;
 466         union sqtt_instruction_trace_data instruction_trace_data;
 467 };
 468
 469 static_assert(sizeof(struct sqtt_file_chunk_api_info) == 1064,
 470               "sqtt_file_chunk_api_info doesn't match RGP spec");
 471
 472 static void
 473 radv_sqtt_fill_api_info(struct sqtt_file_chunk_api_info *chunk)
 474 {
 475         chunk->header.chunk_id.type = SQTT_FILE_CHUNK_TYPE_API_INFO;
 476         chunk->header.chunk_id.index = 0;
 477         chunk->header.major_version = 0;
 478         chunk->header.minor_version = 1;
 479         chunk->header.size_in_bytes = sizeof(*chunk);
 480
 481         chunk->api_type = SQTT_API_TYPE_VULKAN;
 482         chunk->major_version = 0;
 483         chunk->minor_version = 0;
 484         chunk->profiling_mode = SQTT_PROFILING_MODE_PRESENT;
 485         chunk->instruction_trace_mode = SQTT_INSTRUCTION_TRACE_DISABLED;
 486 }
 487
 488 /**
 489  * SQTT desc info.
 490  */
 491 struct sqtt_file_chunk_sqtt_desc {
 492         struct sqtt_file_chunk_header header;
 493         int32_t shader_engine_index;
 494         enum sqtt_version sqtt_version;
 495         union {
 496                 struct {
 497                         int32_t instrumentation_version;
 498                 } v0;
 499                 struct {
 500                         int16_t instrumentation_spec_version;
 501                         int16_t instrumentation_api_version;
 502                         int32_t compute_unit_index;
 503                 } v1;
 504         };
 505 };
 506
 507 static_assert(sizeof(struct sqtt_file_chunk_sqtt_desc) == 32,
 508               "sqtt_file_chunk_sqtt_desc doesn't match RGP spec");
 509
 510 static enum sqtt_version
 511 radv_chip_class_to_sqtt_version(enum chip_class chip_class)
 512 {
 513         switch (chip_class) {
 514         case GFX6:
 515                 return SQTT_VERSION_2_0;
 516         case GFX7:
 517                 return SQTT_VERSION_2_1;
 518         case GFX8:
 519                 return SQTT_VERSION_2_2;
 520         case GFX9:
 521                 return SQTT_VERSION_2_3;
 522         case GFX10:
 523                 return SQTT_VERSION_2_4;
 524         default:
 525                 unreachable("Invalid chip class");
 526         }
 527 }
 528
 529 static void
 530 radv_sqtt_fill_sqtt_desc(struct radv_device *device,
 531                          struct sqtt_file_chunk_sqtt_desc *chunk,
 532                          int32_t chunk_index,
 533                          int32_t shader_engine_index,
 534                          int32_t compute_unit_index)
 535 {
 536         chunk->header.chunk_id.type = SQTT_FILE_CHUNK_TYPE_SQTT_DESC;
 537         chunk->header.chunk_id.index = chunk_index;
 538         chunk->header.major_version = 0;
 539         chunk->header.minor_version = 2;
 540         chunk->header.size_in_bytes = sizeof(*chunk);
 541
 542         chunk->sqtt_version = radv_chip_class_to_sqtt_version(device->physical_device->rad_info.chip_class);
 543         chunk->shader_engine_index = shader_engine_index;
 544         chunk->v1.instrumentation_spec_version = 0;
 545         chunk->v1.instrumentation_api_version = 0;
 546         chunk->v1.compute_unit_index = compute_unit_index;
 547 }
 548
 549 /**
 550  * SQTT data info.
 551  */
 552 struct sqtt_file_chunk_sqtt_data {
 553         struct sqtt_file_chunk_header header;
 554         int32_t offset; /* in bytes */
 555         int32_t size; /* in bytes */
 556 };
 557
 558 static_assert(sizeof(struct sqtt_file_chunk_sqtt_data) == 24,
 559               "sqtt_file_chunk_sqtt_data doesn't match RGP spec");
 560
 561 static void
 562 radv_sqtt_fill_sqtt_data(struct sqtt_file_chunk_sqtt_data *chunk,
 563                          int32_t chunk_index, int32_t offset, int32_t size)
 564 {
 565         chunk->header.chunk_id.type = SQTT_FILE_CHUNK_TYPE_SQTT_DATA;
 566         chunk->header.chunk_id.index = chunk_index;
 567         chunk->header.major_version = 0;
 568         chunk->header.minor_version = 0;
 569         chunk->header.size_in_bytes = sizeof(*chunk) + size;
 570
 571         chunk->offset = sizeof(*chunk) + offset;
 572         chunk->size = size;
 573 }
 574
 575 static void
 576 radv_sqtt_dump_data(struct radv_device *device,
 577                     const struct radv_thread_trace *thread_trace,
 578                     FILE *output)
 579 {
 580         struct sqtt_file_chunk_asic_info asic_info = {};
 581         struct sqtt_file_chunk_cpu_info cpu_info = {};
 582         struct sqtt_file_chunk_api_info api_info = {};
 583         struct sqtt_file_header header = {};
 584         size_t file_offset = 0;
 585
 586         /* SQTT header file. */
 587         radv_sqtt_fill_header(&header);
 588         file_offset += sizeof(header);
 589         fwrite(&header, sizeof(header), 1, output);
 590
 591         /* SQTT cpu chunk. */
 592         radv_sqtt_fill_cpu_info(&cpu_info);
 593         file_offset += sizeof(cpu_info);
 594         fwrite(&cpu_info, sizeof(cpu_info), 1, output);
 595
 596         /* SQTT asic chunk. */
 597         radv_fill_sqtt_asic_info(device, &asic_info);
 598         file_offset += sizeof(asic_info);
 599         fwrite(&asic_info, sizeof(asic_info), 1, output);
 600
 601         /* SQTT api chunk. */
 602         radv_sqtt_fill_api_info(&api_info);
 603         file_offset += sizeof(api_info);
 604         fwrite(&api_info, sizeof(api_info), 1, output);
 605
 606         if (thread_trace) {
 607                 for (unsigned i = 0; i < thread_trace->num_traces; i++) {
 608                         const struct radv_thread_trace_se *se = &thread_trace->traces[i];
 609                         const struct radv_thread_trace_info *info = &se->info;
 610                         struct sqtt_file_chunk_sqtt_desc desc = {};
 611                         struct sqtt_file_chunk_sqtt_data data = {};
 612                         uint64_t size = info->cur_offset * 32; /* unit of 32 bytes */
 613
 614                         /* SQTT desc chunk. */
 615                         radv_sqtt_fill_sqtt_desc(device, &desc, i,
 616                                                  se->shader_engine,
 617                                                  se->compute_unit);
 618                         file_offset += sizeof(desc);
 619                         fwrite(&desc, sizeof(desc), 1, output);
 620
 621                         /* SQTT data chunk. */
 622                         radv_sqtt_fill_sqtt_data(&data, i, file_offset, size);
 623                         file_offset += sizeof(data);
 624                         fwrite(&data, sizeof(data), 1, output);
 625
 626                         /* Copy thread trace data generated by the hardware. */
 627                         file_offset += size;
 628                         fwrite(se->data_ptr, size, 1, output);
 629                 }
 630         }
 631 }
 632
 633 int
 634 radv_dump_thread_trace(struct radv_device *device,
 635                        const struct radv_thread_trace *thread_trace)
 636 {
 637         char filename[2048];
 638         struct tm now;
 639         time_t t;
 640         FILE *f;
 641
 642         t = time(NULL);
 643         now = *localtime(&t);
 644
 645         snprintf(filename, sizeof(filename), "/tmp/%s_%04d.%02d.%02d_%02d.%02d.rgp",
 646                  util_get_process_name(), 1900 + now.tm_year, now.tm_mon + 1,
 647                  now.tm_mday, now.tm_hour, now.tm_min);
 648
 649         f = fopen(filename, "w+");
 650         if (!f)
 651                 return -1;
 652
 653         radv_sqtt_dump_data(device, thread_trace, f);
 654
 655         fprintf(stderr, "Thread trace capture saved to '%s'\n", filename);
 656
 657         fclose(f);
 658         return 0;
 659 }
 660