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[mesa.git] / src / amd / vulkan / radv_shader.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
33 #include "radv_shader_helper.h"
34 #include "radv_shader_args.h"
35 #include "nir/nir.h"
36 #include "nir/nir_builder.h"
37 #include "spirv/nir_spirv.h"
38
39 #include "sid.h"
40 #include "ac_binary.h"
41 #include "ac_llvm_util.h"
42 #include "ac_nir_to_llvm.h"
43 #include "ac_rtld.h"
44 #include "vk_format.h"
45 #include "util/debug.h"
46 #include "ac_exp_param.h"
47
48 #include "aco_interface.h"
49
50 #include "util/string_buffer.h"
51
52 static const struct nir_shader_compiler_options nir_options_llvm = {
53 .vertex_id_zero_based = true,
54 .lower_scmp = true,
55 .lower_flrp16 = true,
56 .lower_flrp32 = true,
57 .lower_flrp64 = true,
58 .lower_device_index_to_zero = true,
59 .lower_fsat = true,
60 .lower_fdiv = true,
61 .lower_fmod = true,
62 .lower_bitfield_insert_to_bitfield_select = true,
63 .lower_bitfield_extract = true,
64 .lower_sub = true,
65 .lower_pack_snorm_2x16 = true,
66 .lower_pack_snorm_4x8 = true,
67 .lower_pack_unorm_2x16 = true,
68 .lower_pack_unorm_4x8 = true,
69 .lower_unpack_snorm_2x16 = true,
70 .lower_unpack_snorm_4x8 = true,
71 .lower_unpack_unorm_2x16 = true,
72 .lower_unpack_unorm_4x8 = true,
73 .lower_extract_byte = true,
74 .lower_extract_word = true,
75 .lower_ffma = true,
76 .lower_fpow = true,
77 .lower_mul_2x32_64 = true,
78 .lower_rotate = true,
79 .max_unroll_iterations = 32,
80 .use_interpolated_input_intrinsics = true,
81 /* nir_lower_int64() isn't actually called for the LLVM backend, but
82 * this helps the loop unrolling heuristics. */
83 .lower_int64_options = nir_lower_imul64 |
84 nir_lower_imul_high64 |
85 nir_lower_imul_2x32_64 |
86 nir_lower_divmod64 |
87 nir_lower_minmax64 |
88 nir_lower_iabs64,
89 };
90
91 static const struct nir_shader_compiler_options nir_options_aco = {
92 .vertex_id_zero_based = true,
93 .lower_scmp = true,
94 .lower_flrp16 = true,
95 .lower_flrp32 = true,
96 .lower_flrp64 = true,
97 .lower_device_index_to_zero = true,
98 .lower_fdiv = true,
99 .lower_fmod = true,
100 .lower_bitfield_insert_to_bitfield_select = true,
101 .lower_bitfield_extract = true,
102 .lower_pack_snorm_2x16 = true,
103 .lower_pack_snorm_4x8 = true,
104 .lower_pack_unorm_2x16 = true,
105 .lower_pack_unorm_4x8 = true,
106 .lower_unpack_snorm_2x16 = true,
107 .lower_unpack_snorm_4x8 = true,
108 .lower_unpack_unorm_2x16 = true,
109 .lower_unpack_unorm_4x8 = true,
110 .lower_unpack_half_2x16 = true,
111 .lower_extract_byte = true,
112 .lower_extract_word = true,
113 .lower_ffma = true,
114 .lower_fpow = true,
115 .lower_mul_2x32_64 = true,
116 .lower_rotate = true,
117 .max_unroll_iterations = 32,
118 .use_interpolated_input_intrinsics = true,
119 .lower_int64_options = nir_lower_imul64 |
120 nir_lower_imul_high64 |
121 nir_lower_imul_2x32_64 |
122 nir_lower_divmod64 |
123 nir_lower_logic64 |
124 nir_lower_minmax64 |
125 nir_lower_iabs64,
126 };
127
128 bool
129 radv_can_dump_shader(struct radv_device *device,
130 struct radv_shader_module *module,
131 bool is_gs_copy_shader)
132 {
133 if (!(device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS))
134 return false;
135 if (module)
136 return !module->nir ||
137 (device->instance->debug_flags & RADV_DEBUG_DUMP_META_SHADERS);
138
139 return is_gs_copy_shader;
140 }
141
142 bool
143 radv_can_dump_shader_stats(struct radv_device *device,
144 struct radv_shader_module *module)
145 {
146 /* Only dump non-meta shader stats. */
147 return device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS &&
148 module && !module->nir;
149 }
150
151 VkResult radv_CreateShaderModule(
152 VkDevice _device,
153 const VkShaderModuleCreateInfo* pCreateInfo,
154 const VkAllocationCallbacks* pAllocator,
155 VkShaderModule* pShaderModule)
156 {
157 RADV_FROM_HANDLE(radv_device, device, _device);
158 struct radv_shader_module *module;
159
160 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
161 assert(pCreateInfo->flags == 0);
162
163 module = vk_alloc2(&device->vk.alloc, pAllocator,
164 sizeof(*module) + pCreateInfo->codeSize, 8,
165 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
166 if (module == NULL)
167 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
168
169 module->nir = NULL;
170 module->size = pCreateInfo->codeSize;
171 memcpy(module->data, pCreateInfo->pCode, module->size);
172
173 _mesa_sha1_compute(module->data, module->size, module->sha1);
174
175 *pShaderModule = radv_shader_module_to_handle(module);
176
177 return VK_SUCCESS;
178 }
179
180 void radv_DestroyShaderModule(
181 VkDevice _device,
182 VkShaderModule _module,
183 const VkAllocationCallbacks* pAllocator)
184 {
185 RADV_FROM_HANDLE(radv_device, device, _device);
186 RADV_FROM_HANDLE(radv_shader_module, module, _module);
187
188 if (!module)
189 return;
190
191 vk_free2(&device->vk.alloc, pAllocator, module);
192 }
193
194 void
195 radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
196 bool allow_copies)
197 {
198 bool progress;
199 unsigned lower_flrp =
200 (shader->options->lower_flrp16 ? 16 : 0) |
201 (shader->options->lower_flrp32 ? 32 : 0) |
202 (shader->options->lower_flrp64 ? 64 : 0);
203
204 do {
205 progress = false;
206
207 NIR_PASS(progress, shader, nir_split_array_vars, nir_var_function_temp);
208 NIR_PASS(progress, shader, nir_shrink_vec_array_vars, nir_var_function_temp);
209
210 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
211 NIR_PASS_V(shader, nir_lower_pack);
212
213 if (allow_copies) {
214 /* Only run this pass in the first call to
215 * radv_optimize_nir. Later calls assume that we've
216 * lowered away any copy_deref instructions and we
217 * don't want to introduce any more.
218 */
219 NIR_PASS(progress, shader, nir_opt_find_array_copies);
220 }
221
222 NIR_PASS(progress, shader, nir_opt_copy_prop_vars);
223 NIR_PASS(progress, shader, nir_opt_dead_write_vars);
224 NIR_PASS(progress, shader, nir_remove_dead_variables,
225 nir_var_function_temp | nir_var_shader_in | nir_var_shader_out);
226
227 NIR_PASS_V(shader, nir_lower_alu_to_scalar, NULL, NULL);
228 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
229
230 NIR_PASS(progress, shader, nir_copy_prop);
231 NIR_PASS(progress, shader, nir_opt_remove_phis);
232 NIR_PASS(progress, shader, nir_opt_dce);
233 if (nir_opt_trivial_continues(shader)) {
234 progress = true;
235 NIR_PASS(progress, shader, nir_copy_prop);
236 NIR_PASS(progress, shader, nir_opt_remove_phis);
237 NIR_PASS(progress, shader, nir_opt_dce);
238 }
239 NIR_PASS(progress, shader, nir_opt_if, true);
240 NIR_PASS(progress, shader, nir_opt_dead_cf);
241 NIR_PASS(progress, shader, nir_opt_cse);
242 NIR_PASS(progress, shader, nir_opt_peephole_select, 8, true, true);
243 NIR_PASS(progress, shader, nir_opt_constant_folding);
244 NIR_PASS(progress, shader, nir_opt_algebraic);
245
246 if (lower_flrp != 0) {
247 bool lower_flrp_progress = false;
248 NIR_PASS(lower_flrp_progress,
249 shader,
250 nir_lower_flrp,
251 lower_flrp,
252 false /* always_precise */,
253 shader->options->lower_ffma);
254 if (lower_flrp_progress) {
255 NIR_PASS(progress, shader,
256 nir_opt_constant_folding);
257 progress = true;
258 }
259
260 /* Nothing should rematerialize any flrps, so we only
261 * need to do this lowering once.
262 */
263 lower_flrp = 0;
264 }
265
266 NIR_PASS(progress, shader, nir_opt_undef);
267 if (shader->options->max_unroll_iterations) {
268 NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
269 }
270 } while (progress && !optimize_conservatively);
271
272 NIR_PASS(progress, shader, nir_opt_conditional_discard);
273 NIR_PASS(progress, shader, nir_opt_shrink_load);
274 NIR_PASS(progress, shader, nir_opt_move, nir_move_load_ubo);
275 }
276
277 static void
278 shared_var_info(const struct glsl_type *type, unsigned *size, unsigned *align)
279 {
280 assert(glsl_type_is_vector_or_scalar(type));
281
282 uint32_t comp_size = glsl_type_is_boolean(type) ? 4 : glsl_get_bit_size(type) / 8;
283 unsigned length = glsl_get_vector_elements(type);
284 *size = comp_size * length,
285 *align = comp_size;
286 }
287
288 nir_shader *
289 radv_shader_compile_to_nir(struct radv_device *device,
290 struct radv_shader_module *module,
291 const char *entrypoint_name,
292 gl_shader_stage stage,
293 const VkSpecializationInfo *spec_info,
294 const VkPipelineCreateFlags flags,
295 const struct radv_pipeline_layout *layout,
296 unsigned subgroup_size, unsigned ballot_bit_size)
297 {
298 nir_shader *nir;
299 const nir_shader_compiler_options *nir_options =
300 device->physical_device->use_aco ? &nir_options_aco :
301 &nir_options_llvm;
302
303 if (module->nir) {
304 /* Some things such as our meta clear/blit code will give us a NIR
305 * shader directly. In that case, we just ignore the SPIR-V entirely
306 * and just use the NIR shader */
307 nir = module->nir;
308 nir->options = nir_options;
309 nir_validate_shader(nir, "in internal shader");
310
311 assert(exec_list_length(&nir->functions) == 1);
312 } else {
313 uint32_t *spirv = (uint32_t *) module->data;
314 assert(module->size % 4 == 0);
315
316 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SPIRV)
317 radv_print_spirv(module->data, module->size, stderr);
318
319 uint32_t num_spec_entries = 0;
320 struct nir_spirv_specialization *spec_entries = NULL;
321 if (spec_info && spec_info->mapEntryCount > 0) {
322 num_spec_entries = spec_info->mapEntryCount;
323 spec_entries = calloc(num_spec_entries, sizeof(*spec_entries));
324 for (uint32_t i = 0; i < num_spec_entries; i++) {
325 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
326 const void *data = spec_info->pData + entry.offset;
327 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
328
329 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
330 switch (entry.size) {
331 case 8:
332 spec_entries[i].value.u64 = *(const uint64_t *)data;
333 break;
334 case 4:
335 spec_entries[i].value.u32 = *(const uint32_t *)data;
336 break;
337 case 2:
338 spec_entries[i].value.u16 = *(const uint16_t *)data;
339 break;
340 case 1:
341 spec_entries[i].value.u8 = *(const uint8_t *)data;
342 break;
343 default:
344 assert(!"Invalid spec constant size");
345 break;
346 }
347 }
348 }
349 bool int8_int16_enable = !device->physical_device->use_aco ||
350 device->physical_device->rad_info.chip_class >= GFX8;
351 const struct spirv_to_nir_options spirv_options = {
352 .lower_ubo_ssbo_access_to_offsets = true,
353 .caps = {
354 .amd_fragment_mask = true,
355 .amd_gcn_shader = true,
356 .amd_image_read_write_lod = true,
357 .amd_shader_ballot = device->physical_device->use_shader_ballot,
358 .amd_shader_explicit_vertex_parameter = true,
359 .amd_trinary_minmax = true,
360 .demote_to_helper_invocation = device->physical_device->use_aco,
361 .derivative_group = true,
362 .descriptor_array_dynamic_indexing = true,
363 .descriptor_array_non_uniform_indexing = true,
364 .descriptor_indexing = true,
365 .device_group = true,
366 .draw_parameters = true,
367 .float_controls = true,
368 .float16 = device->physical_device->rad_info.has_double_rate_fp16 && !device->physical_device->use_aco,
369 .float64 = true,
370 .geometry_streams = true,
371 .image_ms_array = true,
372 .image_read_without_format = true,
373 .image_write_without_format = true,
374 .int8 = int8_int16_enable,
375 .int16 = int8_int16_enable,
376 .int64 = true,
377 .int64_atomics = true,
378 .multiview = true,
379 .physical_storage_buffer_address = true,
380 .post_depth_coverage = true,
381 .runtime_descriptor_array = true,
382 .shader_clock = true,
383 .shader_viewport_index_layer = true,
384 .stencil_export = true,
385 .storage_8bit = int8_int16_enable,
386 .storage_16bit = int8_int16_enable,
387 .storage_image_ms = true,
388 .subgroup_arithmetic = true,
389 .subgroup_ballot = true,
390 .subgroup_basic = true,
391 .subgroup_quad = true,
392 .subgroup_shuffle = true,
393 .subgroup_vote = true,
394 .tessellation = true,
395 .transform_feedback = true,
396 .variable_pointers = true,
397 },
398 .ubo_addr_format = nir_address_format_32bit_index_offset,
399 .ssbo_addr_format = nir_address_format_32bit_index_offset,
400 .phys_ssbo_addr_format = nir_address_format_64bit_global,
401 .push_const_addr_format = nir_address_format_logical,
402 .shared_addr_format = nir_address_format_32bit_offset,
403 .frag_coord_is_sysval = true,
404 };
405 nir = spirv_to_nir(spirv, module->size / 4,
406 spec_entries, num_spec_entries,
407 stage, entrypoint_name,
408 &spirv_options, nir_options);
409 assert(nir->info.stage == stage);
410 nir_validate_shader(nir, "after spirv_to_nir");
411
412 free(spec_entries);
413
414 /* We have to lower away local constant initializers right before we
415 * inline functions. That way they get properly initialized at the top
416 * of the function and not at the top of its caller.
417 */
418 NIR_PASS_V(nir, nir_lower_variable_initializers, nir_var_function_temp);
419 NIR_PASS_V(nir, nir_lower_returns);
420 NIR_PASS_V(nir, nir_inline_functions);
421 NIR_PASS_V(nir, nir_opt_deref);
422
423 /* Pick off the single entrypoint that we want */
424 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
425 if (func->is_entrypoint)
426 func->name = ralloc_strdup(func, "main");
427 else
428 exec_node_remove(&func->node);
429 }
430 assert(exec_list_length(&nir->functions) == 1);
431
432 /* Make sure we lower constant initializers on output variables so that
433 * nir_remove_dead_variables below sees the corresponding stores
434 */
435 NIR_PASS_V(nir, nir_lower_variable_initializers, nir_var_shader_out);
436
437 /* Now that we've deleted all but the main function, we can go ahead and
438 * lower the rest of the constant initializers.
439 */
440 NIR_PASS_V(nir, nir_lower_variable_initializers, ~0);
441
442 /* Split member structs. We do this before lower_io_to_temporaries so that
443 * it doesn't lower system values to temporaries by accident.
444 */
445 NIR_PASS_V(nir, nir_split_var_copies);
446 NIR_PASS_V(nir, nir_split_per_member_structs);
447
448 if (nir->info.stage == MESA_SHADER_FRAGMENT &&
449 device->physical_device->use_aco)
450 NIR_PASS_V(nir, nir_lower_io_to_vector, nir_var_shader_out);
451 if (nir->info.stage == MESA_SHADER_FRAGMENT)
452 NIR_PASS_V(nir, nir_lower_input_attachments, true);
453
454 NIR_PASS_V(nir, nir_remove_dead_variables,
455 nir_var_shader_in | nir_var_shader_out | nir_var_system_value | nir_var_mem_shared);
456
457 NIR_PASS_V(nir, nir_propagate_invariant);
458
459 NIR_PASS_V(nir, nir_lower_system_values);
460 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
461 NIR_PASS_V(nir, radv_nir_lower_ycbcr_textures, layout);
462 if (device->instance->debug_flags & RADV_DEBUG_DISCARD_TO_DEMOTE)
463 NIR_PASS_V(nir, nir_lower_discard_to_demote);
464 }
465
466 /* Vulkan uses the separate-shader linking model */
467 nir->info.separate_shader = true;
468
469 nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
470
471 if (nir->info.stage == MESA_SHADER_GEOMETRY)
472 nir_lower_gs_intrinsics(nir, true);
473
474 static const nir_lower_tex_options tex_options = {
475 .lower_txp = ~0,
476 .lower_tg4_offsets = true,
477 };
478
479 nir_lower_tex(nir, &tex_options);
480
481 nir_lower_vars_to_ssa(nir);
482
483 if (nir->info.stage == MESA_SHADER_VERTEX ||
484 nir->info.stage == MESA_SHADER_GEOMETRY ||
485 nir->info.stage == MESA_SHADER_FRAGMENT) {
486 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
487 nir_shader_get_entrypoint(nir), true, true);
488 } else if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
489 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
490 nir_shader_get_entrypoint(nir), true, false);
491 }
492
493 nir_split_var_copies(nir);
494
495 nir_lower_global_vars_to_local(nir);
496 nir_remove_dead_variables(nir, nir_var_function_temp);
497 bool gfx7minus = device->physical_device->rad_info.chip_class <= GFX7;
498 nir_lower_subgroups(nir, &(struct nir_lower_subgroups_options) {
499 .subgroup_size = subgroup_size,
500 .ballot_bit_size = ballot_bit_size,
501 .lower_to_scalar = 1,
502 .lower_subgroup_masks = 1,
503 .lower_shuffle = 1,
504 .lower_shuffle_to_32bit = 1,
505 .lower_vote_eq_to_ballot = 1,
506 .lower_quad_broadcast_dynamic = 1,
507 .lower_quad_broadcast_dynamic_to_const = gfx7minus,
508 });
509
510 nir_lower_load_const_to_scalar(nir);
511
512 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
513 radv_optimize_nir(nir, false, true);
514
515 /* We call nir_lower_var_copies() after the first radv_optimize_nir()
516 * to remove any copies introduced by nir_opt_find_array_copies().
517 */
518 nir_lower_var_copies(nir);
519
520 /* Lower deref operations for compute shared memory. */
521 if (nir->info.stage == MESA_SHADER_COMPUTE) {
522 NIR_PASS_V(nir, nir_lower_vars_to_explicit_types,
523 nir_var_mem_shared, shared_var_info);
524 NIR_PASS_V(nir, nir_lower_explicit_io,
525 nir_var_mem_shared, nir_address_format_32bit_offset);
526 }
527
528 /* Lower large variables that are always constant with load_constant
529 * intrinsics, which get turned into PC-relative loads from a data
530 * section next to the shader.
531 */
532 NIR_PASS_V(nir, nir_opt_large_constants,
533 glsl_get_natural_size_align_bytes, 16);
534
535 /* Indirect lowering must be called after the radv_optimize_nir() loop
536 * has been called at least once. Otherwise indirect lowering can
537 * bloat the instruction count of the loop and cause it to be
538 * considered too large for unrolling.
539 */
540 ac_lower_indirect_derefs(nir, device->physical_device->rad_info.chip_class);
541 radv_optimize_nir(nir, flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT, false);
542
543 return nir;
544 }
545
546 static int
547 type_size_vec4(const struct glsl_type *type, bool bindless)
548 {
549 return glsl_count_attribute_slots(type, false);
550 }
551
552 static nir_variable *
553 find_layer_in_var(nir_shader *nir)
554 {
555 nir_foreach_variable(var, &nir->inputs) {
556 if (var->data.location == VARYING_SLOT_LAYER) {
557 return var;
558 }
559 }
560
561 nir_variable *var =
562 nir_variable_create(nir, nir_var_shader_in, glsl_int_type(), "layer id");
563 var->data.location = VARYING_SLOT_LAYER;
564 var->data.interpolation = INTERP_MODE_FLAT;
565 return var;
566 }
567
568 /* We use layered rendering to implement multiview, which means we need to map
569 * view_index to gl_Layer. The attachment lowering also uses needs to know the
570 * layer so that it can sample from the correct layer. The code generates a
571 * load from the layer_id sysval, but since we don't have a way to get at this
572 * information from the fragment shader, we also need to lower this to the
573 * gl_Layer varying. This pass lowers both to a varying load from the LAYER
574 * slot, before lowering io, so that nir_assign_var_locations() will give the
575 * LAYER varying the correct driver_location.
576 */
577
578 static bool
579 lower_view_index(nir_shader *nir)
580 {
581 bool progress = false;
582 nir_function_impl *entry = nir_shader_get_entrypoint(nir);
583 nir_builder b;
584 nir_builder_init(&b, entry);
585
586 nir_variable *layer = NULL;
587 nir_foreach_block(block, entry) {
588 nir_foreach_instr_safe(instr, block) {
589 if (instr->type != nir_instr_type_intrinsic)
590 continue;
591
592 nir_intrinsic_instr *load = nir_instr_as_intrinsic(instr);
593 if (load->intrinsic != nir_intrinsic_load_view_index &&
594 load->intrinsic != nir_intrinsic_load_layer_id)
595 continue;
596
597 if (!layer)
598 layer = find_layer_in_var(nir);
599
600 b.cursor = nir_before_instr(instr);
601 nir_ssa_def *def = nir_load_var(&b, layer);
602 nir_ssa_def_rewrite_uses(&load->dest.ssa,
603 nir_src_for_ssa(def));
604
605 nir_instr_remove(instr);
606 progress = true;
607 }
608 }
609
610 return progress;
611 }
612
613 void
614 radv_lower_fs_io(nir_shader *nir)
615 {
616 NIR_PASS_V(nir, lower_view_index);
617 nir_assign_io_var_locations(&nir->inputs, &nir->num_inputs,
618 MESA_SHADER_FRAGMENT);
619
620 NIR_PASS_V(nir, nir_lower_io, nir_var_shader_in, type_size_vec4, 0);
621
622 /* This pass needs actual constants */
623 nir_opt_constant_folding(nir);
624
625 NIR_PASS_V(nir, nir_io_add_const_offset_to_base, nir_var_shader_in);
626 }
627
628
629 void *
630 radv_alloc_shader_memory(struct radv_device *device,
631 struct radv_shader_variant *shader)
632 {
633 mtx_lock(&device->shader_slab_mutex);
634 list_for_each_entry(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
635 uint64_t offset = 0;
636 list_for_each_entry(struct radv_shader_variant, s, &slab->shaders, slab_list) {
637 if (s->bo_offset - offset >= shader->code_size) {
638 shader->bo = slab->bo;
639 shader->bo_offset = offset;
640 list_addtail(&shader->slab_list, &s->slab_list);
641 mtx_unlock(&device->shader_slab_mutex);
642 return slab->ptr + offset;
643 }
644 offset = align_u64(s->bo_offset + s->code_size, 256);
645 }
646 if (offset <= slab->size && slab->size - offset >= shader->code_size) {
647 shader->bo = slab->bo;
648 shader->bo_offset = offset;
649 list_addtail(&shader->slab_list, &slab->shaders);
650 mtx_unlock(&device->shader_slab_mutex);
651 return slab->ptr + offset;
652 }
653 }
654
655 mtx_unlock(&device->shader_slab_mutex);
656 struct radv_shader_slab *slab = calloc(1, sizeof(struct radv_shader_slab));
657
658 slab->size = MAX2(256 * 1024, shader->code_size);
659 slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
660 RADEON_DOMAIN_VRAM,
661 RADEON_FLAG_NO_INTERPROCESS_SHARING |
662 (device->physical_device->rad_info.cpdma_prefetch_writes_memory ?
663 0 : RADEON_FLAG_READ_ONLY),
664 RADV_BO_PRIORITY_SHADER);
665 slab->ptr = (char*)device->ws->buffer_map(slab->bo);
666 list_inithead(&slab->shaders);
667
668 mtx_lock(&device->shader_slab_mutex);
669 list_add(&slab->slabs, &device->shader_slabs);
670
671 shader->bo = slab->bo;
672 shader->bo_offset = 0;
673 list_add(&shader->slab_list, &slab->shaders);
674 mtx_unlock(&device->shader_slab_mutex);
675 return slab->ptr;
676 }
677
678 void
679 radv_destroy_shader_slabs(struct radv_device *device)
680 {
681 list_for_each_entry_safe(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
682 device->ws->buffer_destroy(slab->bo);
683 free(slab);
684 }
685 mtx_destroy(&device->shader_slab_mutex);
686 }
687
688 /* For the UMR disassembler. */
689 #define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */
690 #define DEBUGGER_NUM_MARKERS 5
691
692 static unsigned
693 radv_get_shader_binary_size(size_t code_size)
694 {
695 return code_size + DEBUGGER_NUM_MARKERS * 4;
696 }
697
698 static void radv_postprocess_config(const struct radv_physical_device *pdevice,
699 const struct ac_shader_config *config_in,
700 const struct radv_shader_info *info,
701 gl_shader_stage stage,
702 struct ac_shader_config *config_out)
703 {
704 bool scratch_enabled = config_in->scratch_bytes_per_wave > 0;
705 unsigned vgpr_comp_cnt = 0;
706 unsigned num_input_vgprs = info->num_input_vgprs;
707
708 if (stage == MESA_SHADER_FRAGMENT) {
709 num_input_vgprs = ac_get_fs_input_vgpr_cnt(config_in, NULL, NULL);
710 }
711
712 unsigned num_vgprs = MAX2(config_in->num_vgprs, num_input_vgprs);
713 /* +3 for scratch wave offset and VCC */
714 unsigned num_sgprs = MAX2(config_in->num_sgprs, info->num_input_sgprs + 3);
715 unsigned num_shared_vgprs = config_in->num_shared_vgprs;
716 /* shared VGPRs are introduced in Navi and are allocated in blocks of 8 (RDNA ref 3.6.5) */
717 assert((pdevice->rad_info.chip_class >= GFX10 && num_shared_vgprs % 8 == 0)
718 || (pdevice->rad_info.chip_class < GFX10 && num_shared_vgprs == 0));
719 unsigned num_shared_vgpr_blocks = num_shared_vgprs / 8;
720
721 *config_out = *config_in;
722 config_out->num_vgprs = num_vgprs;
723 config_out->num_sgprs = num_sgprs;
724 config_out->num_shared_vgprs = num_shared_vgprs;
725
726 config_out->rsrc2 = S_00B12C_USER_SGPR(info->num_user_sgprs) |
727 S_00B12C_SCRATCH_EN(scratch_enabled);
728
729 if (!pdevice->use_ngg_streamout) {
730 config_out->rsrc2 |= S_00B12C_SO_BASE0_EN(!!info->so.strides[0]) |
731 S_00B12C_SO_BASE1_EN(!!info->so.strides[1]) |
732 S_00B12C_SO_BASE2_EN(!!info->so.strides[2]) |
733 S_00B12C_SO_BASE3_EN(!!info->so.strides[3]) |
734 S_00B12C_SO_EN(!!info->so.num_outputs);
735 }
736
737 config_out->rsrc1 = S_00B848_VGPRS((num_vgprs - 1) /
738 (info->wave_size == 32 ? 8 : 4)) |
739 S_00B848_DX10_CLAMP(1) |
740 S_00B848_FLOAT_MODE(config_out->float_mode);
741
742 if (pdevice->rad_info.chip_class >= GFX10) {
743 config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(info->num_user_sgprs >> 5);
744 } else {
745 config_out->rsrc1 |= S_00B228_SGPRS((num_sgprs - 1) / 8);
746 config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(info->num_user_sgprs >> 5);
747 }
748
749 switch (stage) {
750 case MESA_SHADER_TESS_EVAL:
751 if (info->is_ngg) {
752 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
753 config_out->rsrc2 |= S_00B22C_OC_LDS_EN(1);
754 } else if (info->tes.as_es) {
755 assert(pdevice->rad_info.chip_class <= GFX8);
756 vgpr_comp_cnt = info->uses_prim_id ? 3 : 2;
757
758 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
759 } else {
760 bool enable_prim_id = info->tes.export_prim_id || info->uses_prim_id;
761 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
762
763 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
764 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
765 }
766 config_out->rsrc2 |= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
767 break;
768 case MESA_SHADER_TESS_CTRL:
769 if (pdevice->rad_info.chip_class >= GFX9) {
770 /* We need at least 2 components for LS.
771 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
772 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
773 */
774 if (pdevice->rad_info.chip_class >= GFX10) {
775 vgpr_comp_cnt = info->vs.needs_instance_id ? 3 : 1;
776 } else {
777 vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1;
778 }
779 } else {
780 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
781 }
782 config_out->rsrc1 |= S_00B428_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
783 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
784 config_out->rsrc2 |= S_00B42C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
785 break;
786 case MESA_SHADER_VERTEX:
787 if (info->is_ngg) {
788 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
789 } else if (info->vs.as_ls) {
790 assert(pdevice->rad_info.chip_class <= GFX8);
791 /* We need at least 2 components for LS.
792 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
793 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
794 */
795 vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1;
796 } else if (info->vs.as_es) {
797 assert(pdevice->rad_info.chip_class <= GFX8);
798 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
799 vgpr_comp_cnt = info->vs.needs_instance_id ? 1 : 0;
800 } else {
801 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
802 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
803 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
804 */
805 if (info->vs.needs_instance_id && pdevice->rad_info.chip_class >= GFX10) {
806 vgpr_comp_cnt = 3;
807 } else if (info->vs.export_prim_id) {
808 vgpr_comp_cnt = 2;
809 } else if (info->vs.needs_instance_id) {
810 vgpr_comp_cnt = 1;
811 } else {
812 vgpr_comp_cnt = 0;
813 }
814
815 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
816 }
817 config_out->rsrc2 |= S_00B12C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
818 break;
819 case MESA_SHADER_FRAGMENT:
820 config_out->rsrc1 |= S_00B028_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
821 config_out->rsrc2 |= S_00B02C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
822 break;
823 case MESA_SHADER_GEOMETRY:
824 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
825 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
826 config_out->rsrc2 |= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
827 break;
828 case MESA_SHADER_COMPUTE:
829 config_out->rsrc1 |= S_00B848_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
830 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
831 config_out->rsrc2 |=
832 S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) |
833 S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) |
834 S_00B84C_TGID_Z_EN(info->cs.uses_block_id[2]) |
835 S_00B84C_TIDIG_COMP_CNT(info->cs.uses_thread_id[2] ? 2 :
836 info->cs.uses_thread_id[1] ? 1 : 0) |
837 S_00B84C_TG_SIZE_EN(info->cs.uses_local_invocation_idx) |
838 S_00B84C_LDS_SIZE(config_in->lds_size);
839 config_out->rsrc3 |= S_00B8A0_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
840
841 break;
842 default:
843 unreachable("unsupported shader type");
844 break;
845 }
846
847 if (pdevice->rad_info.chip_class >= GFX10 && info->is_ngg &&
848 (stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_TESS_EVAL || stage == MESA_SHADER_GEOMETRY)) {
849 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
850 gl_shader_stage es_stage = stage;
851 if (stage == MESA_SHADER_GEOMETRY)
852 es_stage = info->gs.es_type;
853
854 /* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */
855 if (es_stage == MESA_SHADER_VERTEX) {
856 es_vgpr_comp_cnt = info->vs.needs_instance_id ? 3 : 0;
857 } else if (es_stage == MESA_SHADER_TESS_EVAL) {
858 bool enable_prim_id = info->tes.export_prim_id || info->uses_prim_id;
859 es_vgpr_comp_cnt = enable_prim_id ? 3 : 2;
860 } else
861 unreachable("Unexpected ES shader stage");
862
863 bool tes_triangles = stage == MESA_SHADER_TESS_EVAL &&
864 info->tes.primitive_mode >= 4; /* GL_TRIANGLES */
865 if (info->uses_invocation_id || stage == MESA_SHADER_VERTEX) {
866 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
867 } else if (info->uses_prim_id) {
868 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
869 } else if (info->gs.vertices_in >= 3 || tes_triangles) {
870 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
871 } else {
872 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
873 }
874
875 config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt) |
876 S_00B228_WGP_MODE(1);
877 config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
878 S_00B22C_LDS_SIZE(config_in->lds_size) |
879 S_00B22C_OC_LDS_EN(es_stage == MESA_SHADER_TESS_EVAL);
880 } else if (pdevice->rad_info.chip_class >= GFX9 &&
881 stage == MESA_SHADER_GEOMETRY) {
882 unsigned es_type = info->gs.es_type;
883 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
884
885 if (es_type == MESA_SHADER_VERTEX) {
886 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
887 if (info->vs.needs_instance_id) {
888 es_vgpr_comp_cnt = pdevice->rad_info.chip_class >= GFX10 ? 3 : 1;
889 } else {
890 es_vgpr_comp_cnt = 0;
891 }
892 } else if (es_type == MESA_SHADER_TESS_EVAL) {
893 es_vgpr_comp_cnt = info->uses_prim_id ? 3 : 2;
894 } else {
895 unreachable("invalid shader ES type");
896 }
897
898 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
899 * VGPR[0:4] are always loaded.
900 */
901 if (info->uses_invocation_id) {
902 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
903 } else if (info->uses_prim_id) {
904 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
905 } else if (info->gs.vertices_in >= 3) {
906 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
907 } else {
908 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
909 }
910
911 config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
912 config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
913 S_00B22C_OC_LDS_EN(es_type == MESA_SHADER_TESS_EVAL);
914 } else if (pdevice->rad_info.chip_class >= GFX9 &&
915 stage == MESA_SHADER_TESS_CTRL) {
916 config_out->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt);
917 } else {
918 config_out->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt);
919 }
920 }
921
922 struct radv_shader_variant *
923 radv_shader_variant_create(struct radv_device *device,
924 const struct radv_shader_binary *binary,
925 bool keep_shader_info)
926 {
927 struct ac_shader_config config = {0};
928 struct ac_rtld_binary rtld_binary = {0};
929 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
930 if (!variant)
931 return NULL;
932
933 variant->ref_count = 1;
934
935 if (binary->type == RADV_BINARY_TYPE_RTLD) {
936 struct ac_rtld_symbol lds_symbols[2];
937 unsigned num_lds_symbols = 0;
938 const char *elf_data = (const char *)((struct radv_shader_binary_rtld *)binary)->data;
939 size_t elf_size = ((struct radv_shader_binary_rtld *)binary)->elf_size;
940
941 if (device->physical_device->rad_info.chip_class >= GFX9 &&
942 (binary->stage == MESA_SHADER_GEOMETRY || binary->info.is_ngg) &&
943 !binary->is_gs_copy_shader) {
944 /* We add this symbol even on LLVM <= 8 to ensure that
945 * shader->config.lds_size is set correctly below.
946 */
947 struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
948 sym->name = "esgs_ring";
949 sym->size = binary->info.ngg_info.esgs_ring_size;
950 sym->align = 64 * 1024;
951 }
952
953 if (binary->info.is_ngg &&
954 binary->stage == MESA_SHADER_GEOMETRY) {
955 struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
956 sym->name = "ngg_emit";
957 sym->size = binary->info.ngg_info.ngg_emit_size * 4;
958 sym->align = 4;
959 }
960
961 struct ac_rtld_open_info open_info = {
962 .info = &device->physical_device->rad_info,
963 .shader_type = binary->stage,
964 .wave_size = binary->info.wave_size,
965 .num_parts = 1,
966 .elf_ptrs = &elf_data,
967 .elf_sizes = &elf_size,
968 .num_shared_lds_symbols = num_lds_symbols,
969 .shared_lds_symbols = lds_symbols,
970 };
971
972 if (!ac_rtld_open(&rtld_binary, open_info)) {
973 free(variant);
974 return NULL;
975 }
976
977 if (!ac_rtld_read_config(&rtld_binary, &config)) {
978 ac_rtld_close(&rtld_binary);
979 free(variant);
980 return NULL;
981 }
982
983 if (rtld_binary.lds_size > 0) {
984 unsigned alloc_granularity = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
985 config.lds_size = align(rtld_binary.lds_size, alloc_granularity) / alloc_granularity;
986 }
987
988 variant->code_size = rtld_binary.rx_size;
989 variant->exec_size = rtld_binary.exec_size;
990 } else {
991 assert(binary->type == RADV_BINARY_TYPE_LEGACY);
992 config = ((struct radv_shader_binary_legacy *)binary)->config;
993 variant->code_size = radv_get_shader_binary_size(((struct radv_shader_binary_legacy *)binary)->code_size);
994 variant->exec_size = ((struct radv_shader_binary_legacy *)binary)->exec_size;
995 }
996
997 variant->info = binary->info;
998 radv_postprocess_config(device->physical_device, &config, &binary->info,
999 binary->stage, &variant->config);
1000
1001 if (radv_device_use_secure_compile(device->instance)) {
1002 if (binary->type == RADV_BINARY_TYPE_RTLD)
1003 ac_rtld_close(&rtld_binary);
1004
1005 return variant;
1006 }
1007
1008 void *dest_ptr = radv_alloc_shader_memory(device, variant);
1009
1010 if (binary->type == RADV_BINARY_TYPE_RTLD) {
1011 struct radv_shader_binary_rtld* bin = (struct radv_shader_binary_rtld *)binary;
1012 struct ac_rtld_upload_info info = {
1013 .binary = &rtld_binary,
1014 .rx_va = radv_buffer_get_va(variant->bo) + variant->bo_offset,
1015 .rx_ptr = dest_ptr,
1016 };
1017
1018 if (!ac_rtld_upload(&info)) {
1019 radv_shader_variant_destroy(device, variant);
1020 ac_rtld_close(&rtld_binary);
1021 return NULL;
1022 }
1023
1024 if (keep_shader_info ||
1025 (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS)) {
1026 const char *disasm_data;
1027 size_t disasm_size;
1028 if (!ac_rtld_get_section_by_name(&rtld_binary, ".AMDGPU.disasm", &disasm_data, &disasm_size)) {
1029 radv_shader_variant_destroy(device, variant);
1030 ac_rtld_close(&rtld_binary);
1031 return NULL;
1032 }
1033
1034 variant->ir_string = bin->llvm_ir_size ? strdup((const char*)(bin->data + bin->elf_size)) : NULL;
1035 variant->disasm_string = malloc(disasm_size + 1);
1036 memcpy(variant->disasm_string, disasm_data, disasm_size);
1037 variant->disasm_string[disasm_size] = 0;
1038 }
1039
1040 ac_rtld_close(&rtld_binary);
1041 } else {
1042 struct radv_shader_binary_legacy* bin = (struct radv_shader_binary_legacy *)binary;
1043 memcpy(dest_ptr, bin->data + bin->stats_size, bin->code_size);
1044
1045 /* Add end-of-code markers for the UMR disassembler. */
1046 uint32_t *ptr32 = (uint32_t *)dest_ptr + bin->code_size / 4;
1047 for (unsigned i = 0; i < DEBUGGER_NUM_MARKERS; i++)
1048 ptr32[i] = DEBUGGER_END_OF_CODE_MARKER;
1049
1050 variant->ir_string = bin->ir_size ? strdup((const char*)(bin->data + bin->stats_size + bin->code_size)) : NULL;
1051 variant->disasm_string = bin->disasm_size ? strdup((const char*)(bin->data + bin->stats_size + bin->code_size + bin->ir_size)) : NULL;
1052
1053 if (bin->stats_size) {
1054 variant->statistics = calloc(bin->stats_size, 1);
1055 memcpy(variant->statistics, bin->data, bin->stats_size);
1056 }
1057 }
1058 return variant;
1059 }
1060
1061 static char *
1062 radv_dump_nir_shaders(struct nir_shader * const *shaders,
1063 int shader_count)
1064 {
1065 char *data = NULL;
1066 char *ret = NULL;
1067 size_t size = 0;
1068 FILE *f = open_memstream(&data, &size);
1069 if (f) {
1070 for (int i = 0; i < shader_count; ++i)
1071 nir_print_shader(shaders[i], f);
1072 fclose(f);
1073 }
1074
1075 ret = malloc(size + 1);
1076 if (ret) {
1077 memcpy(ret, data, size);
1078 ret[size] = 0;
1079 }
1080 free(data);
1081 return ret;
1082 }
1083
1084 static struct radv_shader_variant *
1085 shader_variant_compile(struct radv_device *device,
1086 struct radv_shader_module *module,
1087 struct nir_shader * const *shaders,
1088 int shader_count,
1089 gl_shader_stage stage,
1090 struct radv_shader_info *info,
1091 struct radv_nir_compiler_options *options,
1092 bool gs_copy_shader,
1093 bool keep_shader_info,
1094 bool keep_statistic_info,
1095 struct radv_shader_binary **binary_out)
1096 {
1097 enum radeon_family chip_family = device->physical_device->rad_info.family;
1098 struct radv_shader_binary *binary = NULL;
1099
1100 options->family = chip_family;
1101 options->chip_class = device->physical_device->rad_info.chip_class;
1102 options->dump_shader = radv_can_dump_shader(device, module, gs_copy_shader);
1103 options->dump_preoptir = options->dump_shader &&
1104 device->instance->debug_flags & RADV_DEBUG_PREOPTIR;
1105 options->record_ir = keep_shader_info;
1106 options->record_stats = keep_statistic_info;
1107 options->check_ir = device->instance->debug_flags & RADV_DEBUG_CHECKIR;
1108 options->tess_offchip_block_dw_size = device->tess_offchip_block_dw_size;
1109 options->address32_hi = device->physical_device->rad_info.address32_hi;
1110 options->has_ls_vgpr_init_bug = device->physical_device->rad_info.has_ls_vgpr_init_bug;
1111 options->use_ngg_streamout = device->physical_device->use_ngg_streamout;
1112
1113 struct radv_shader_args args = {};
1114 args.options = options;
1115 args.shader_info = info;
1116 args.is_gs_copy_shader = gs_copy_shader;
1117 radv_declare_shader_args(&args,
1118 gs_copy_shader ? MESA_SHADER_VERTEX
1119 : shaders[shader_count - 1]->info.stage,
1120 shader_count >= 2,
1121 shader_count >= 2 ? shaders[shader_count - 2]->info.stage
1122 : MESA_SHADER_VERTEX);
1123
1124 if (!device->physical_device->use_aco ||
1125 options->dump_shader || options->record_ir)
1126 ac_init_llvm_once();
1127
1128 if (device->physical_device->use_aco) {
1129 aco_compile_shader(shader_count, shaders, &binary, &args);
1130 } else {
1131 llvm_compile_shader(device, shader_count, shaders, &binary, &args);
1132 }
1133
1134 binary->info = *info;
1135
1136 struct radv_shader_variant *variant = radv_shader_variant_create(device, binary,
1137 keep_shader_info);
1138 if (!variant) {
1139 free(binary);
1140 return NULL;
1141 }
1142
1143 if (options->dump_shader) {
1144 fprintf(stderr, "%s", radv_get_shader_name(info, shaders[0]->info.stage));
1145 for (int i = 1; i < shader_count; ++i)
1146 fprintf(stderr, " + %s", radv_get_shader_name(info, shaders[i]->info.stage));
1147
1148 fprintf(stderr, "\ndisasm:\n%s\n", variant->disasm_string);
1149 }
1150
1151
1152 if (keep_shader_info) {
1153 variant->nir_string = radv_dump_nir_shaders(shaders, shader_count);
1154 if (!gs_copy_shader && !module->nir) {
1155 variant->spirv = malloc(module->size);
1156 if (!variant->spirv) {
1157 free(variant);
1158 free(binary);
1159 return NULL;
1160 }
1161
1162 memcpy(variant->spirv, module->data, module->size);
1163 variant->spirv_size = module->size;
1164 }
1165 }
1166
1167 if (binary_out)
1168 *binary_out = binary;
1169 else
1170 free(binary);
1171
1172 return variant;
1173 }
1174
1175 struct radv_shader_variant *
1176 radv_shader_variant_compile(struct radv_device *device,
1177 struct radv_shader_module *module,
1178 struct nir_shader *const *shaders,
1179 int shader_count,
1180 struct radv_pipeline_layout *layout,
1181 const struct radv_shader_variant_key *key,
1182 struct radv_shader_info *info,
1183 bool keep_shader_info, bool keep_statistic_info,
1184 struct radv_shader_binary **binary_out)
1185 {
1186 struct radv_nir_compiler_options options = {0};
1187
1188 options.layout = layout;
1189 if (key)
1190 options.key = *key;
1191
1192 options.explicit_scratch_args = device->physical_device->use_aco;
1193 options.robust_buffer_access = device->robust_buffer_access;
1194
1195 return shader_variant_compile(device, module, shaders, shader_count, shaders[shader_count - 1]->info.stage, info,
1196 &options, false, keep_shader_info, keep_statistic_info, binary_out);
1197 }
1198
1199 struct radv_shader_variant *
1200 radv_create_gs_copy_shader(struct radv_device *device,
1201 struct nir_shader *shader,
1202 struct radv_shader_info *info,
1203 struct radv_shader_binary **binary_out,
1204 bool keep_shader_info, bool keep_statistic_info,
1205 bool multiview)
1206 {
1207 struct radv_nir_compiler_options options = {0};
1208
1209 options.explicit_scratch_args = device->physical_device->use_aco;
1210 options.key.has_multiview_view_index = multiview;
1211
1212 return shader_variant_compile(device, NULL, &shader, 1, MESA_SHADER_VERTEX,
1213 info, &options, true, keep_shader_info, keep_statistic_info, binary_out);
1214 }
1215
1216 void
1217 radv_shader_variant_destroy(struct radv_device *device,
1218 struct radv_shader_variant *variant)
1219 {
1220 if (!p_atomic_dec_zero(&variant->ref_count))
1221 return;
1222
1223 mtx_lock(&device->shader_slab_mutex);
1224 list_del(&variant->slab_list);
1225 mtx_unlock(&device->shader_slab_mutex);
1226
1227 free(variant->spirv);
1228 free(variant->nir_string);
1229 free(variant->disasm_string);
1230 free(variant->ir_string);
1231 free(variant->statistics);
1232 free(variant);
1233 }
1234
1235 const char *
1236 radv_get_shader_name(struct radv_shader_info *info,
1237 gl_shader_stage stage)
1238 {
1239 switch (stage) {
1240 case MESA_SHADER_VERTEX:
1241 if (info->vs.as_ls)
1242 return "Vertex Shader as LS";
1243 else if (info->vs.as_es)
1244 return "Vertex Shader as ES";
1245 else if (info->is_ngg)
1246 return "Vertex Shader as ESGS";
1247 else
1248 return "Vertex Shader as VS";
1249 case MESA_SHADER_TESS_CTRL:
1250 return "Tessellation Control Shader";
1251 case MESA_SHADER_TESS_EVAL:
1252 if (info->tes.as_es)
1253 return "Tessellation Evaluation Shader as ES";
1254 else if (info->is_ngg)
1255 return "Tessellation Evaluation Shader as ESGS";
1256 else
1257 return "Tessellation Evaluation Shader as VS";
1258 case MESA_SHADER_GEOMETRY:
1259 return "Geometry Shader";
1260 case MESA_SHADER_FRAGMENT:
1261 return "Pixel Shader";
1262 case MESA_SHADER_COMPUTE:
1263 return "Compute Shader";
1264 default:
1265 return "Unknown shader";
1266 };
1267 }
1268
1269 unsigned
1270 radv_get_max_workgroup_size(enum chip_class chip_class,
1271 gl_shader_stage stage,
1272 const unsigned *sizes)
1273 {
1274 switch (stage) {
1275 case MESA_SHADER_TESS_CTRL:
1276 return chip_class >= GFX7 ? 128 : 64;
1277 case MESA_SHADER_GEOMETRY:
1278 return chip_class >= GFX9 ? 128 : 64;
1279 case MESA_SHADER_COMPUTE:
1280 break;
1281 default:
1282 return 0;
1283 }
1284
1285 unsigned max_workgroup_size = sizes[0] * sizes[1] * sizes[2];
1286 return max_workgroup_size;
1287 }
1288
1289 unsigned
1290 radv_get_max_waves(struct radv_device *device,
1291 struct radv_shader_variant *variant,
1292 gl_shader_stage stage)
1293 {
1294 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
1295 unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
1296 uint8_t wave_size = variant->info.wave_size;
1297 struct ac_shader_config *conf = &variant->config;
1298 unsigned max_simd_waves;
1299 unsigned lds_per_wave = 0;
1300
1301 max_simd_waves = device->physical_device->rad_info.max_wave64_per_simd;
1302
1303 if (stage == MESA_SHADER_FRAGMENT) {
1304 lds_per_wave = conf->lds_size * lds_increment +
1305 align(variant->info.ps.num_interp * 48,
1306 lds_increment);
1307 } else if (stage == MESA_SHADER_COMPUTE) {
1308 unsigned max_workgroup_size =
1309 radv_get_max_workgroup_size(chip_class, stage, variant->info.cs.block_size);
1310 lds_per_wave = (conf->lds_size * lds_increment) /
1311 DIV_ROUND_UP(max_workgroup_size, wave_size);
1312 }
1313
1314 if (conf->num_sgprs) {
1315 unsigned sgprs = align(conf->num_sgprs, chip_class >= GFX8 ? 16 : 8);
1316 max_simd_waves =
1317 MIN2(max_simd_waves,
1318 device->physical_device->rad_info.num_physical_sgprs_per_simd /
1319 sgprs);
1320 }
1321
1322 if (conf->num_vgprs) {
1323 unsigned vgprs = align(conf->num_vgprs, wave_size == 32 ? 8 : 4);
1324 max_simd_waves =
1325 MIN2(max_simd_waves,
1326 device->physical_device->rad_info.num_physical_wave64_vgprs_per_simd / vgprs);
1327 }
1328
1329 unsigned max_lds_per_simd = device->physical_device->rad_info.lds_size_per_workgroup / device->physical_device->rad_info.num_simd_per_compute_unit;
1330 if (lds_per_wave)
1331 max_simd_waves = MIN2(max_simd_waves, max_lds_per_simd / lds_per_wave);
1332
1333 return max_simd_waves;
1334 }
1335
1336 static void
1337 generate_shader_stats(struct radv_device *device,
1338 struct radv_shader_variant *variant,
1339 gl_shader_stage stage,
1340 struct _mesa_string_buffer *buf)
1341 {
1342 struct ac_shader_config *conf = &variant->config;
1343 unsigned max_simd_waves = radv_get_max_waves(device, variant, stage);
1344
1345 if (stage == MESA_SHADER_FRAGMENT) {
1346 _mesa_string_buffer_printf(buf, "*** SHADER CONFIG ***\n"
1347 "SPI_PS_INPUT_ADDR = 0x%04x\n"
1348 "SPI_PS_INPUT_ENA = 0x%04x\n",
1349 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
1350 }
1351
1352 _mesa_string_buffer_printf(buf, "*** SHADER STATS ***\n"
1353 "SGPRS: %d\n"
1354 "VGPRS: %d\n"
1355 "Spilled SGPRs: %d\n"
1356 "Spilled VGPRs: %d\n"
1357 "PrivMem VGPRS: %d\n"
1358 "Code Size: %d bytes\n"
1359 "LDS: %d blocks\n"
1360 "Scratch: %d bytes per wave\n"
1361 "Max Waves: %d\n",
1362 conf->num_sgprs, conf->num_vgprs,
1363 conf->spilled_sgprs, conf->spilled_vgprs,
1364 variant->info.private_mem_vgprs, variant->exec_size,
1365 conf->lds_size, conf->scratch_bytes_per_wave,
1366 max_simd_waves);
1367
1368 if (variant->statistics) {
1369 _mesa_string_buffer_printf(buf, "*** COMPILER STATS ***\n");
1370 for (unsigned i = 0; i < variant->statistics->count; i++) {
1371 struct radv_compiler_statistic_info *info = &variant->statistics->infos[i];
1372 uint32_t value = variant->statistics->values[i];
1373 _mesa_string_buffer_printf(buf, "%s: %lu\n", info->name, value);
1374 }
1375 }
1376
1377 _mesa_string_buffer_printf(buf, "********************\n\n\n");
1378 }
1379
1380 void
1381 radv_shader_dump_stats(struct radv_device *device,
1382 struct radv_shader_variant *variant,
1383 gl_shader_stage stage,
1384 FILE *file)
1385 {
1386 struct _mesa_string_buffer *buf = _mesa_string_buffer_create(NULL, 256);
1387
1388 generate_shader_stats(device, variant, stage, buf);
1389
1390 fprintf(file, "\n%s:\n", radv_get_shader_name(&variant->info, stage));
1391 fprintf(file, "%s", buf->buf);
1392
1393 _mesa_string_buffer_destroy(buf);
1394 }
1395
1396 VkResult
1397 radv_GetShaderInfoAMD(VkDevice _device,
1398 VkPipeline _pipeline,
1399 VkShaderStageFlagBits shaderStage,
1400 VkShaderInfoTypeAMD infoType,
1401 size_t* pInfoSize,
1402 void* pInfo)
1403 {
1404 RADV_FROM_HANDLE(radv_device, device, _device);
1405 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
1406 gl_shader_stage stage = vk_to_mesa_shader_stage(shaderStage);
1407 struct radv_shader_variant *variant = pipeline->shaders[stage];
1408 struct _mesa_string_buffer *buf;
1409 VkResult result = VK_SUCCESS;
1410
1411 /* Spec doesn't indicate what to do if the stage is invalid, so just
1412 * return no info for this. */
1413 if (!variant)
1414 return vk_error(device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1415
1416 switch (infoType) {
1417 case VK_SHADER_INFO_TYPE_STATISTICS_AMD:
1418 if (!pInfo) {
1419 *pInfoSize = sizeof(VkShaderStatisticsInfoAMD);
1420 } else {
1421 unsigned lds_multiplier = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
1422 struct ac_shader_config *conf = &variant->config;
1423
1424 VkShaderStatisticsInfoAMD statistics = {};
1425 statistics.shaderStageMask = shaderStage;
1426 statistics.numPhysicalVgprs = device->physical_device->rad_info.num_physical_wave64_vgprs_per_simd;
1427 statistics.numPhysicalSgprs = device->physical_device->rad_info.num_physical_sgprs_per_simd;
1428 statistics.numAvailableSgprs = statistics.numPhysicalSgprs;
1429
1430 if (stage == MESA_SHADER_COMPUTE) {
1431 unsigned *local_size = variant->info.cs.block_size;
1432 unsigned workgroup_size = local_size[0] * local_size[1] * local_size[2];
1433
1434 statistics.numAvailableVgprs = statistics.numPhysicalVgprs /
1435 ceil((double)workgroup_size / statistics.numPhysicalVgprs);
1436
1437 statistics.computeWorkGroupSize[0] = local_size[0];
1438 statistics.computeWorkGroupSize[1] = local_size[1];
1439 statistics.computeWorkGroupSize[2] = local_size[2];
1440 } else {
1441 statistics.numAvailableVgprs = statistics.numPhysicalVgprs;
1442 }
1443
1444 statistics.resourceUsage.numUsedVgprs = conf->num_vgprs;
1445 statistics.resourceUsage.numUsedSgprs = conf->num_sgprs;
1446 statistics.resourceUsage.ldsSizePerLocalWorkGroup = 32768;
1447 statistics.resourceUsage.ldsUsageSizeInBytes = conf->lds_size * lds_multiplier;
1448 statistics.resourceUsage.scratchMemUsageInBytes = conf->scratch_bytes_per_wave;
1449
1450 size_t size = *pInfoSize;
1451 *pInfoSize = sizeof(statistics);
1452
1453 memcpy(pInfo, &statistics, MIN2(size, *pInfoSize));
1454
1455 if (size < *pInfoSize)
1456 result = VK_INCOMPLETE;
1457 }
1458
1459 break;
1460 case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD:
1461 buf = _mesa_string_buffer_create(NULL, 1024);
1462
1463 _mesa_string_buffer_printf(buf, "%s:\n", radv_get_shader_name(&variant->info, stage));
1464 _mesa_string_buffer_printf(buf, "%s\n\n", variant->ir_string);
1465 _mesa_string_buffer_printf(buf, "%s\n\n", variant->disasm_string);
1466 generate_shader_stats(device, variant, stage, buf);
1467
1468 /* Need to include the null terminator. */
1469 size_t length = buf->length + 1;
1470
1471 if (!pInfo) {
1472 *pInfoSize = length;
1473 } else {
1474 size_t size = *pInfoSize;
1475 *pInfoSize = length;
1476
1477 memcpy(pInfo, buf->buf, MIN2(size, length));
1478
1479 if (size < length)
1480 result = VK_INCOMPLETE;
1481 }
1482
1483 _mesa_string_buffer_destroy(buf);
1484 break;
1485 default:
1486 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
1487 result = VK_ERROR_FEATURE_NOT_PRESENT;
1488 break;
1489 }
1490
1491 return result;
1492 }