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radv: advertise VK_AMD_shader_image_load_store_lod
[mesa.git] / src / amd / vulkan / radv_shader.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
33 #include "radv_shader_helper.h"
34 #include "radv_shader_args.h"
35 #include "nir/nir.h"
36 #include "nir/nir_builder.h"
37 #include "spirv/nir_spirv.h"
38
39 #include <llvm-c/Core.h>
40 #include <llvm-c/TargetMachine.h>
41 #include <llvm-c/Support.h>
42
43 #include "sid.h"
44 #include "ac_binary.h"
45 #include "ac_llvm_util.h"
46 #include "ac_nir_to_llvm.h"
47 #include "ac_rtld.h"
48 #include "vk_format.h"
49 #include "util/debug.h"
50 #include "ac_exp_param.h"
51
52 #include "aco_interface.h"
53
54 #include "util/string_buffer.h"
55
56 static const struct nir_shader_compiler_options nir_options_llvm = {
57 .vertex_id_zero_based = true,
58 .lower_scmp = true,
59 .lower_flrp16 = true,
60 .lower_flrp32 = true,
61 .lower_flrp64 = true,
62 .lower_device_index_to_zero = true,
63 .lower_fsat = true,
64 .lower_fdiv = true,
65 .lower_fmod = true,
66 .lower_bitfield_insert_to_bitfield_select = true,
67 .lower_bitfield_extract = true,
68 .lower_sub = true,
69 .lower_pack_snorm_2x16 = true,
70 .lower_pack_snorm_4x8 = true,
71 .lower_pack_unorm_2x16 = true,
72 .lower_pack_unorm_4x8 = true,
73 .lower_unpack_snorm_2x16 = true,
74 .lower_unpack_snorm_4x8 = true,
75 .lower_unpack_unorm_2x16 = true,
76 .lower_unpack_unorm_4x8 = true,
77 .lower_extract_byte = true,
78 .lower_extract_word = true,
79 .lower_ffma = true,
80 .lower_fpow = true,
81 .lower_mul_2x32_64 = true,
82 .lower_rotate = true,
83 .max_unroll_iterations = 32,
84 .use_interpolated_input_intrinsics = true,
85 /* nir_lower_int64() isn't actually called for the LLVM backend, but
86 * this helps the loop unrolling heuristics. */
87 .lower_int64_options = nir_lower_imul64 |
88 nir_lower_imul_high64 |
89 nir_lower_imul_2x32_64 |
90 nir_lower_divmod64 |
91 nir_lower_minmax64 |
92 nir_lower_iabs64,
93 };
94
95 static const struct nir_shader_compiler_options nir_options_aco = {
96 .vertex_id_zero_based = true,
97 .lower_scmp = true,
98 .lower_flrp16 = true,
99 .lower_flrp32 = true,
100 .lower_flrp64 = true,
101 .lower_device_index_to_zero = true,
102 .lower_fdiv = true,
103 .lower_fmod = true,
104 .lower_bitfield_insert_to_bitfield_select = true,
105 .lower_bitfield_extract = true,
106 .lower_pack_snorm_2x16 = true,
107 .lower_pack_snorm_4x8 = true,
108 .lower_pack_unorm_2x16 = true,
109 .lower_pack_unorm_4x8 = true,
110 .lower_unpack_snorm_2x16 = true,
111 .lower_unpack_snorm_4x8 = true,
112 .lower_unpack_unorm_2x16 = true,
113 .lower_unpack_unorm_4x8 = true,
114 .lower_unpack_half_2x16 = true,
115 .lower_extract_byte = true,
116 .lower_extract_word = true,
117 .lower_ffma = true,
118 .lower_fpow = true,
119 .lower_mul_2x32_64 = true,
120 .lower_rotate = true,
121 .max_unroll_iterations = 32,
122 .use_interpolated_input_intrinsics = true,
123 .lower_int64_options = nir_lower_imul64 |
124 nir_lower_imul_high64 |
125 nir_lower_imul_2x32_64 |
126 nir_lower_divmod64 |
127 nir_lower_logic64 |
128 nir_lower_minmax64 |
129 nir_lower_iabs64,
130 };
131
132 bool
133 radv_can_dump_shader(struct radv_device *device,
134 struct radv_shader_module *module,
135 bool is_gs_copy_shader)
136 {
137 if (!(device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS))
138 return false;
139 if (module)
140 return !module->nir ||
141 (device->instance->debug_flags & RADV_DEBUG_DUMP_META_SHADERS);
142
143 return is_gs_copy_shader;
144 }
145
146 bool
147 radv_can_dump_shader_stats(struct radv_device *device,
148 struct radv_shader_module *module)
149 {
150 /* Only dump non-meta shader stats. */
151 return device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS &&
152 module && !module->nir;
153 }
154
155 unsigned shader_io_get_unique_index(gl_varying_slot slot)
156 {
157 /* handle patch indices separate */
158 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
159 return 0;
160 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
161 return 1;
162 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
163 return 2 + (slot - VARYING_SLOT_PATCH0);
164 if (slot == VARYING_SLOT_POS)
165 return 0;
166 if (slot == VARYING_SLOT_PSIZ)
167 return 1;
168 if (slot == VARYING_SLOT_CLIP_DIST0)
169 return 2;
170 if (slot == VARYING_SLOT_CLIP_DIST1)
171 return 3;
172 /* 3 is reserved for clip dist as well */
173 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
174 return 4 + (slot - VARYING_SLOT_VAR0);
175 unreachable("illegal slot in get unique index\n");
176 }
177
178 VkResult radv_CreateShaderModule(
179 VkDevice _device,
180 const VkShaderModuleCreateInfo* pCreateInfo,
181 const VkAllocationCallbacks* pAllocator,
182 VkShaderModule* pShaderModule)
183 {
184 RADV_FROM_HANDLE(radv_device, device, _device);
185 struct radv_shader_module *module;
186
187 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
188 assert(pCreateInfo->flags == 0);
189
190 module = vk_alloc2(&device->alloc, pAllocator,
191 sizeof(*module) + pCreateInfo->codeSize, 8,
192 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
193 if (module == NULL)
194 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
195
196 module->nir = NULL;
197 module->size = pCreateInfo->codeSize;
198 memcpy(module->data, pCreateInfo->pCode, module->size);
199
200 _mesa_sha1_compute(module->data, module->size, module->sha1);
201
202 *pShaderModule = radv_shader_module_to_handle(module);
203
204 return VK_SUCCESS;
205 }
206
207 void radv_DestroyShaderModule(
208 VkDevice _device,
209 VkShaderModule _module,
210 const VkAllocationCallbacks* pAllocator)
211 {
212 RADV_FROM_HANDLE(radv_device, device, _device);
213 RADV_FROM_HANDLE(radv_shader_module, module, _module);
214
215 if (!module)
216 return;
217
218 vk_free2(&device->alloc, pAllocator, module);
219 }
220
221 void
222 radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
223 bool allow_copies)
224 {
225 bool progress;
226 unsigned lower_flrp =
227 (shader->options->lower_flrp16 ? 16 : 0) |
228 (shader->options->lower_flrp32 ? 32 : 0) |
229 (shader->options->lower_flrp64 ? 64 : 0);
230
231 do {
232 progress = false;
233
234 NIR_PASS(progress, shader, nir_split_array_vars, nir_var_function_temp);
235 NIR_PASS(progress, shader, nir_shrink_vec_array_vars, nir_var_function_temp);
236
237 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
238 NIR_PASS_V(shader, nir_lower_pack);
239
240 if (allow_copies) {
241 /* Only run this pass in the first call to
242 * radv_optimize_nir. Later calls assume that we've
243 * lowered away any copy_deref instructions and we
244 * don't want to introduce any more.
245 */
246 NIR_PASS(progress, shader, nir_opt_find_array_copies);
247 }
248
249 NIR_PASS(progress, shader, nir_opt_copy_prop_vars);
250 NIR_PASS(progress, shader, nir_opt_dead_write_vars);
251 NIR_PASS(progress, shader, nir_remove_dead_variables,
252 nir_var_function_temp | nir_var_shader_in | nir_var_shader_out);
253
254 NIR_PASS_V(shader, nir_lower_alu_to_scalar, NULL, NULL);
255 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
256
257 NIR_PASS(progress, shader, nir_copy_prop);
258 NIR_PASS(progress, shader, nir_opt_remove_phis);
259 NIR_PASS(progress, shader, nir_opt_dce);
260 if (nir_opt_trivial_continues(shader)) {
261 progress = true;
262 NIR_PASS(progress, shader, nir_copy_prop);
263 NIR_PASS(progress, shader, nir_opt_remove_phis);
264 NIR_PASS(progress, shader, nir_opt_dce);
265 }
266 NIR_PASS(progress, shader, nir_opt_if, true);
267 NIR_PASS(progress, shader, nir_opt_dead_cf);
268 NIR_PASS(progress, shader, nir_opt_cse);
269 NIR_PASS(progress, shader, nir_opt_peephole_select, 8, true, true);
270 NIR_PASS(progress, shader, nir_opt_constant_folding);
271 NIR_PASS(progress, shader, nir_opt_algebraic);
272
273 if (lower_flrp != 0) {
274 bool lower_flrp_progress = false;
275 NIR_PASS(lower_flrp_progress,
276 shader,
277 nir_lower_flrp,
278 lower_flrp,
279 false /* always_precise */,
280 shader->options->lower_ffma);
281 if (lower_flrp_progress) {
282 NIR_PASS(progress, shader,
283 nir_opt_constant_folding);
284 progress = true;
285 }
286
287 /* Nothing should rematerialize any flrps, so we only
288 * need to do this lowering once.
289 */
290 lower_flrp = 0;
291 }
292
293 NIR_PASS(progress, shader, nir_opt_undef);
294 if (shader->options->max_unroll_iterations) {
295 NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
296 }
297 } while (progress && !optimize_conservatively);
298
299 NIR_PASS(progress, shader, nir_opt_conditional_discard);
300 NIR_PASS(progress, shader, nir_opt_shrink_load);
301 NIR_PASS(progress, shader, nir_opt_move, nir_move_load_ubo);
302 }
303
304 static void
305 shared_var_info(const struct glsl_type *type, unsigned *size, unsigned *align)
306 {
307 assert(glsl_type_is_vector_or_scalar(type));
308
309 uint32_t comp_size = glsl_type_is_boolean(type) ? 4 : glsl_get_bit_size(type) / 8;
310 unsigned length = glsl_get_vector_elements(type);
311 *size = comp_size * length,
312 *align = comp_size;
313 }
314
315 nir_shader *
316 radv_shader_compile_to_nir(struct radv_device *device,
317 struct radv_shader_module *module,
318 const char *entrypoint_name,
319 gl_shader_stage stage,
320 const VkSpecializationInfo *spec_info,
321 const VkPipelineCreateFlags flags,
322 const struct radv_pipeline_layout *layout,
323 bool use_aco)
324 {
325 nir_shader *nir;
326 const nir_shader_compiler_options *nir_options = use_aco ? &nir_options_aco :
327 &nir_options_llvm;
328 if (module->nir) {
329 /* Some things such as our meta clear/blit code will give us a NIR
330 * shader directly. In that case, we just ignore the SPIR-V entirely
331 * and just use the NIR shader */
332 nir = module->nir;
333 nir->options = nir_options;
334 nir_validate_shader(nir, "in internal shader");
335
336 assert(exec_list_length(&nir->functions) == 1);
337 } else {
338 uint32_t *spirv = (uint32_t *) module->data;
339 assert(module->size % 4 == 0);
340
341 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SPIRV)
342 radv_print_spirv(module->data, module->size, stderr);
343
344 uint32_t num_spec_entries = 0;
345 struct nir_spirv_specialization *spec_entries = NULL;
346 if (spec_info && spec_info->mapEntryCount > 0) {
347 num_spec_entries = spec_info->mapEntryCount;
348 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
349 for (uint32_t i = 0; i < num_spec_entries; i++) {
350 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
351 const void *data = spec_info->pData + entry.offset;
352 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
353
354 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
355 if (spec_info->dataSize == 8)
356 spec_entries[i].data64 = *(const uint64_t *)data;
357 else
358 spec_entries[i].data32 = *(const uint32_t *)data;
359 }
360 }
361 const struct spirv_to_nir_options spirv_options = {
362 .lower_ubo_ssbo_access_to_offsets = true,
363 .caps = {
364 .amd_gcn_shader = true,
365 .amd_image_read_write_lod = true,
366 .amd_shader_ballot = device->physical_device->use_shader_ballot,
367 .amd_trinary_minmax = true,
368 .demote_to_helper_invocation = device->physical_device->use_aco,
369 .derivative_group = true,
370 .descriptor_array_dynamic_indexing = true,
371 .descriptor_array_non_uniform_indexing = true,
372 .descriptor_indexing = true,
373 .device_group = true,
374 .draw_parameters = true,
375 .float_controls = true,
376 .float16 = !device->physical_device->use_aco,
377 .float64 = true,
378 .geometry_streams = true,
379 .image_ms_array = true,
380 .image_read_without_format = true,
381 .image_write_without_format = true,
382 .int8 = !device->physical_device->use_aco,
383 .int16 = !device->physical_device->use_aco,
384 .int64 = true,
385 .int64_atomics = true,
386 .multiview = true,
387 .physical_storage_buffer_address = true,
388 .post_depth_coverage = true,
389 .runtime_descriptor_array = true,
390 .shader_clock = true,
391 .shader_viewport_index_layer = true,
392 .stencil_export = true,
393 .storage_8bit = !device->physical_device->use_aco,
394 .storage_16bit = !device->physical_device->use_aco,
395 .storage_image_ms = true,
396 .subgroup_arithmetic = true,
397 .subgroup_ballot = true,
398 .subgroup_basic = true,
399 .subgroup_quad = true,
400 .subgroup_shuffle = true,
401 .subgroup_vote = true,
402 .tessellation = true,
403 .transform_feedback = true,
404 .variable_pointers = true,
405 },
406 .ubo_addr_format = nir_address_format_32bit_index_offset,
407 .ssbo_addr_format = nir_address_format_32bit_index_offset,
408 .phys_ssbo_addr_format = nir_address_format_64bit_global,
409 .push_const_addr_format = nir_address_format_logical,
410 .shared_addr_format = nir_address_format_32bit_offset,
411 .frag_coord_is_sysval = true,
412 };
413 nir = spirv_to_nir(spirv, module->size / 4,
414 spec_entries, num_spec_entries,
415 stage, entrypoint_name,
416 &spirv_options, nir_options);
417 assert(nir->info.stage == stage);
418 nir_validate_shader(nir, "after spirv_to_nir");
419
420 free(spec_entries);
421
422 /* We have to lower away local constant initializers right before we
423 * inline functions. That way they get properly initialized at the top
424 * of the function and not at the top of its caller.
425 */
426 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_function_temp);
427 NIR_PASS_V(nir, nir_lower_returns);
428 NIR_PASS_V(nir, nir_inline_functions);
429 NIR_PASS_V(nir, nir_opt_deref);
430
431 /* Pick off the single entrypoint that we want */
432 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
433 if (func->is_entrypoint)
434 func->name = ralloc_strdup(func, "main");
435 else
436 exec_node_remove(&func->node);
437 }
438 assert(exec_list_length(&nir->functions) == 1);
439
440 /* Make sure we lower constant initializers on output variables so that
441 * nir_remove_dead_variables below sees the corresponding stores
442 */
443 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_shader_out);
444
445 /* Now that we've deleted all but the main function, we can go ahead and
446 * lower the rest of the constant initializers.
447 */
448 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
449
450 /* Split member structs. We do this before lower_io_to_temporaries so that
451 * it doesn't lower system values to temporaries by accident.
452 */
453 NIR_PASS_V(nir, nir_split_var_copies);
454 NIR_PASS_V(nir, nir_split_per_member_structs);
455
456 if (nir->info.stage == MESA_SHADER_FRAGMENT && use_aco)
457 NIR_PASS_V(nir, nir_lower_io_to_vector, nir_var_shader_out);
458 if (nir->info.stage == MESA_SHADER_FRAGMENT)
459 NIR_PASS_V(nir, nir_lower_input_attachments, true);
460
461 NIR_PASS_V(nir, nir_remove_dead_variables,
462 nir_var_shader_in | nir_var_shader_out | nir_var_system_value | nir_var_mem_shared);
463
464 NIR_PASS_V(nir, nir_propagate_invariant);
465
466 NIR_PASS_V(nir, nir_lower_system_values);
467 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
468 NIR_PASS_V(nir, radv_nir_lower_ycbcr_textures, layout);
469 }
470
471 /* Vulkan uses the separate-shader linking model */
472 nir->info.separate_shader = true;
473
474 nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
475
476 static const nir_lower_tex_options tex_options = {
477 .lower_txp = ~0,
478 .lower_tg4_offsets = true,
479 };
480
481 nir_lower_tex(nir, &tex_options);
482
483 nir_lower_vars_to_ssa(nir);
484
485 if (nir->info.stage == MESA_SHADER_VERTEX ||
486 nir->info.stage == MESA_SHADER_GEOMETRY ||
487 nir->info.stage == MESA_SHADER_FRAGMENT) {
488 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
489 nir_shader_get_entrypoint(nir), true, true);
490 } else if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
491 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
492 nir_shader_get_entrypoint(nir), true, false);
493 }
494
495 nir_split_var_copies(nir);
496
497 nir_lower_global_vars_to_local(nir);
498 nir_remove_dead_variables(nir, nir_var_function_temp);
499 nir_lower_subgroups(nir, &(struct nir_lower_subgroups_options) {
500 .subgroup_size = 64,
501 .ballot_bit_size = 64,
502 .lower_to_scalar = 1,
503 .lower_subgroup_masks = 1,
504 .lower_shuffle = 1,
505 .lower_shuffle_to_32bit = 1,
506 .lower_vote_eq_to_ballot = 1,
507 });
508
509 nir_lower_load_const_to_scalar(nir);
510
511 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
512 radv_optimize_nir(nir, false, true);
513
514 /* We call nir_lower_var_copies() after the first radv_optimize_nir()
515 * to remove any copies introduced by nir_opt_find_array_copies().
516 */
517 nir_lower_var_copies(nir);
518
519 /* Lower deref operations for compute shared memory. */
520 if (nir->info.stage == MESA_SHADER_COMPUTE) {
521 NIR_PASS_V(nir, nir_lower_vars_to_explicit_types,
522 nir_var_mem_shared, shared_var_info);
523 NIR_PASS_V(nir, nir_lower_explicit_io,
524 nir_var_mem_shared, nir_address_format_32bit_offset);
525 }
526
527 /* Lower large variables that are always constant with load_constant
528 * intrinsics, which get turned into PC-relative loads from a data
529 * section next to the shader.
530 */
531 NIR_PASS_V(nir, nir_opt_large_constants,
532 glsl_get_natural_size_align_bytes, 16);
533
534 /* Indirect lowering must be called after the radv_optimize_nir() loop
535 * has been called at least once. Otherwise indirect lowering can
536 * bloat the instruction count of the loop and cause it to be
537 * considered too large for unrolling.
538 */
539 ac_lower_indirect_derefs(nir, device->physical_device->rad_info.chip_class);
540 radv_optimize_nir(nir, flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT, false);
541
542 return nir;
543 }
544
545 static int
546 type_size_vec4(const struct glsl_type *type, bool bindless)
547 {
548 return glsl_count_attribute_slots(type, false);
549 }
550
551 static nir_variable *
552 find_layer_in_var(nir_shader *nir)
553 {
554 nir_foreach_variable(var, &nir->inputs) {
555 if (var->data.location == VARYING_SLOT_LAYER) {
556 return var;
557 }
558 }
559
560 nir_variable *var =
561 nir_variable_create(nir, nir_var_shader_in, glsl_int_type(), "layer id");
562 var->data.location = VARYING_SLOT_LAYER;
563 var->data.interpolation = INTERP_MODE_FLAT;
564 return var;
565 }
566
567 /* We use layered rendering to implement multiview, which means we need to map
568 * view_index to gl_Layer. The attachment lowering also uses needs to know the
569 * layer so that it can sample from the correct layer. The code generates a
570 * load from the layer_id sysval, but since we don't have a way to get at this
571 * information from the fragment shader, we also need to lower this to the
572 * gl_Layer varying. This pass lowers both to a varying load from the LAYER
573 * slot, before lowering io, so that nir_assign_var_locations() will give the
574 * LAYER varying the correct driver_location.
575 */
576
577 static bool
578 lower_view_index(nir_shader *nir)
579 {
580 bool progress = false;
581 nir_function_impl *entry = nir_shader_get_entrypoint(nir);
582 nir_builder b;
583 nir_builder_init(&b, entry);
584
585 nir_variable *layer = NULL;
586 nir_foreach_block(block, entry) {
587 nir_foreach_instr_safe(instr, block) {
588 if (instr->type != nir_instr_type_intrinsic)
589 continue;
590
591 nir_intrinsic_instr *load = nir_instr_as_intrinsic(instr);
592 if (load->intrinsic != nir_intrinsic_load_view_index &&
593 load->intrinsic != nir_intrinsic_load_layer_id)
594 continue;
595
596 if (!layer)
597 layer = find_layer_in_var(nir);
598
599 b.cursor = nir_before_instr(instr);
600 nir_ssa_def *def = nir_load_var(&b, layer);
601 nir_ssa_def_rewrite_uses(&load->dest.ssa,
602 nir_src_for_ssa(def));
603
604 nir_instr_remove(instr);
605 progress = true;
606 }
607 }
608
609 return progress;
610 }
611
612 void
613 radv_lower_fs_io(nir_shader *nir)
614 {
615 NIR_PASS_V(nir, lower_view_index);
616 nir_assign_io_var_locations(&nir->inputs, &nir->num_inputs,
617 MESA_SHADER_FRAGMENT);
618
619 NIR_PASS_V(nir, nir_lower_io, nir_var_shader_in, type_size_vec4, 0);
620
621 /* This pass needs actual constants */
622 nir_opt_constant_folding(nir);
623
624 NIR_PASS_V(nir, nir_io_add_const_offset_to_base, nir_var_shader_in);
625 }
626
627
628 void *
629 radv_alloc_shader_memory(struct radv_device *device,
630 struct radv_shader_variant *shader)
631 {
632 mtx_lock(&device->shader_slab_mutex);
633 list_for_each_entry(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
634 uint64_t offset = 0;
635 list_for_each_entry(struct radv_shader_variant, s, &slab->shaders, slab_list) {
636 if (s->bo_offset - offset >= shader->code_size) {
637 shader->bo = slab->bo;
638 shader->bo_offset = offset;
639 list_addtail(&shader->slab_list, &s->slab_list);
640 mtx_unlock(&device->shader_slab_mutex);
641 return slab->ptr + offset;
642 }
643 offset = align_u64(s->bo_offset + s->code_size, 256);
644 }
645 if (slab->size - offset >= shader->code_size) {
646 shader->bo = slab->bo;
647 shader->bo_offset = offset;
648 list_addtail(&shader->slab_list, &slab->shaders);
649 mtx_unlock(&device->shader_slab_mutex);
650 return slab->ptr + offset;
651 }
652 }
653
654 mtx_unlock(&device->shader_slab_mutex);
655 struct radv_shader_slab *slab = calloc(1, sizeof(struct radv_shader_slab));
656
657 slab->size = 256 * 1024;
658 slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
659 RADEON_DOMAIN_VRAM,
660 RADEON_FLAG_NO_INTERPROCESS_SHARING |
661 (device->physical_device->rad_info.cpdma_prefetch_writes_memory ?
662 0 : RADEON_FLAG_READ_ONLY),
663 RADV_BO_PRIORITY_SHADER);
664 slab->ptr = (char*)device->ws->buffer_map(slab->bo);
665 list_inithead(&slab->shaders);
666
667 mtx_lock(&device->shader_slab_mutex);
668 list_add(&slab->slabs, &device->shader_slabs);
669
670 shader->bo = slab->bo;
671 shader->bo_offset = 0;
672 list_add(&shader->slab_list, &slab->shaders);
673 mtx_unlock(&device->shader_slab_mutex);
674 return slab->ptr;
675 }
676
677 void
678 radv_destroy_shader_slabs(struct radv_device *device)
679 {
680 list_for_each_entry_safe(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
681 device->ws->buffer_destroy(slab->bo);
682 free(slab);
683 }
684 mtx_destroy(&device->shader_slab_mutex);
685 }
686
687 /* For the UMR disassembler. */
688 #define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */
689 #define DEBUGGER_NUM_MARKERS 5
690
691 static unsigned
692 radv_get_shader_binary_size(size_t code_size)
693 {
694 return code_size + DEBUGGER_NUM_MARKERS * 4;
695 }
696
697 static void radv_postprocess_config(const struct radv_physical_device *pdevice,
698 const struct ac_shader_config *config_in,
699 const struct radv_shader_info *info,
700 gl_shader_stage stage,
701 struct ac_shader_config *config_out)
702 {
703 bool scratch_enabled = config_in->scratch_bytes_per_wave > 0;
704 unsigned vgpr_comp_cnt = 0;
705 unsigned num_input_vgprs = info->num_input_vgprs;
706
707 if (stage == MESA_SHADER_FRAGMENT) {
708 num_input_vgprs = ac_get_fs_input_vgpr_cnt(config_in, NULL, NULL);
709 }
710
711 unsigned num_vgprs = MAX2(config_in->num_vgprs, num_input_vgprs);
712 /* +3 for scratch wave offset and VCC */
713 unsigned num_sgprs = MAX2(config_in->num_sgprs, info->num_input_sgprs + 3);
714 unsigned num_shared_vgprs = config_in->num_shared_vgprs;
715 /* shared VGPRs are introduced in Navi and are allocated in blocks of 8 (RDNA ref 3.6.5) */
716 assert((pdevice->rad_info.chip_class >= GFX10 && num_shared_vgprs % 8 == 0)
717 || (pdevice->rad_info.chip_class < GFX10 && num_shared_vgprs == 0));
718 unsigned num_shared_vgpr_blocks = num_shared_vgprs / 8;
719
720 *config_out = *config_in;
721 config_out->num_vgprs = num_vgprs;
722 config_out->num_sgprs = num_sgprs;
723 config_out->num_shared_vgprs = num_shared_vgprs;
724
725 config_out->rsrc2 = S_00B12C_USER_SGPR(info->num_user_sgprs) |
726 S_00B12C_SCRATCH_EN(scratch_enabled);
727
728 if (!pdevice->use_ngg_streamout) {
729 config_out->rsrc2 |= S_00B12C_SO_BASE0_EN(!!info->so.strides[0]) |
730 S_00B12C_SO_BASE1_EN(!!info->so.strides[1]) |
731 S_00B12C_SO_BASE2_EN(!!info->so.strides[2]) |
732 S_00B12C_SO_BASE3_EN(!!info->so.strides[3]) |
733 S_00B12C_SO_EN(!!info->so.num_outputs);
734 }
735
736 config_out->rsrc1 = S_00B848_VGPRS((num_vgprs - 1) /
737 (info->wave_size == 32 ? 8 : 4)) |
738 S_00B848_DX10_CLAMP(1) |
739 S_00B848_FLOAT_MODE(config_out->float_mode);
740
741 if (pdevice->rad_info.chip_class >= GFX10) {
742 config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(info->num_user_sgprs >> 5);
743 } else {
744 config_out->rsrc1 |= S_00B228_SGPRS((num_sgprs - 1) / 8);
745 config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(info->num_user_sgprs >> 5);
746 }
747
748 switch (stage) {
749 case MESA_SHADER_TESS_EVAL:
750 if (info->is_ngg) {
751 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
752 config_out->rsrc2 |= S_00B22C_OC_LDS_EN(1);
753 } else if (info->tes.as_es) {
754 assert(pdevice->rad_info.chip_class <= GFX8);
755 vgpr_comp_cnt = info->uses_prim_id ? 3 : 2;
756
757 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
758 } else {
759 bool enable_prim_id = info->tes.export_prim_id || info->uses_prim_id;
760 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
761
762 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
763 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
764 }
765 config_out->rsrc2 |= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
766 break;
767 case MESA_SHADER_TESS_CTRL:
768 if (pdevice->rad_info.chip_class >= GFX9) {
769 /* We need at least 2 components for LS.
770 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
771 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
772 */
773 if (pdevice->rad_info.chip_class >= GFX10) {
774 vgpr_comp_cnt = info->vs.needs_instance_id ? 3 : 1;
775 } else {
776 vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1;
777 }
778 } else {
779 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
780 }
781 config_out->rsrc1 |= S_00B428_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
782 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
783 config_out->rsrc2 |= S_00B42C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
784 break;
785 case MESA_SHADER_VERTEX:
786 if (info->is_ngg) {
787 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
788 } else if (info->vs.as_ls) {
789 assert(pdevice->rad_info.chip_class <= GFX8);
790 /* We need at least 2 components for LS.
791 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
792 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
793 */
794 vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1;
795 } else if (info->vs.as_es) {
796 assert(pdevice->rad_info.chip_class <= GFX8);
797 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
798 vgpr_comp_cnt = info->vs.needs_instance_id ? 1 : 0;
799 } else {
800 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
801 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
802 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
803 */
804 if (info->vs.needs_instance_id && pdevice->rad_info.chip_class >= GFX10) {
805 vgpr_comp_cnt = 3;
806 } else if (info->vs.export_prim_id) {
807 vgpr_comp_cnt = 2;
808 } else if (info->vs.needs_instance_id) {
809 vgpr_comp_cnt = 1;
810 } else {
811 vgpr_comp_cnt = 0;
812 }
813
814 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
815 config_out->rsrc2 |= S_00B12C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
816 }
817 break;
818 case MESA_SHADER_FRAGMENT:
819 config_out->rsrc1 |= S_00B028_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
820 config_out->rsrc2 |= S_00B02C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
821 break;
822 case MESA_SHADER_GEOMETRY:
823 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
824 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
825 config_out->rsrc2 |= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
826 break;
827 case MESA_SHADER_COMPUTE:
828 config_out->rsrc1 |= S_00B848_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
829 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
830 config_out->rsrc2 |=
831 S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) |
832 S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) |
833 S_00B84C_TGID_Z_EN(info->cs.uses_block_id[2]) |
834 S_00B84C_TIDIG_COMP_CNT(info->cs.uses_thread_id[2] ? 2 :
835 info->cs.uses_thread_id[1] ? 1 : 0) |
836 S_00B84C_TG_SIZE_EN(info->cs.uses_local_invocation_idx) |
837 S_00B84C_LDS_SIZE(config_in->lds_size);
838 config_out->rsrc3 |= S_00B8A0_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
839
840 break;
841 default:
842 unreachable("unsupported shader type");
843 break;
844 }
845
846 if (pdevice->rad_info.chip_class >= GFX10 && info->is_ngg &&
847 (stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_TESS_EVAL || stage == MESA_SHADER_GEOMETRY)) {
848 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
849 gl_shader_stage es_stage = stage;
850 if (stage == MESA_SHADER_GEOMETRY)
851 es_stage = info->gs.es_type;
852
853 /* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */
854 if (es_stage == MESA_SHADER_VERTEX) {
855 es_vgpr_comp_cnt = info->vs.needs_instance_id ? 3 : 0;
856 } else if (es_stage == MESA_SHADER_TESS_EVAL) {
857 bool enable_prim_id = info->tes.export_prim_id || info->uses_prim_id;
858 es_vgpr_comp_cnt = enable_prim_id ? 3 : 2;
859 } else
860 unreachable("Unexpected ES shader stage");
861
862 bool tes_triangles = stage == MESA_SHADER_TESS_EVAL &&
863 info->tes.primitive_mode >= 4; /* GL_TRIANGLES */
864 if (info->uses_invocation_id || stage == MESA_SHADER_VERTEX) {
865 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
866 } else if (info->uses_prim_id) {
867 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
868 } else if (info->gs.vertices_in >= 3 || tes_triangles) {
869 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
870 } else {
871 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
872 }
873
874 config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt) |
875 S_00B228_WGP_MODE(1);
876 config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
877 S_00B22C_LDS_SIZE(config_in->lds_size) |
878 S_00B22C_OC_LDS_EN(es_stage == MESA_SHADER_TESS_EVAL);
879 } else if (pdevice->rad_info.chip_class >= GFX9 &&
880 stage == MESA_SHADER_GEOMETRY) {
881 unsigned es_type = info->gs.es_type;
882 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
883
884 if (es_type == MESA_SHADER_VERTEX) {
885 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
886 if (info->vs.needs_instance_id) {
887 es_vgpr_comp_cnt = pdevice->rad_info.chip_class >= GFX10 ? 3 : 1;
888 } else {
889 es_vgpr_comp_cnt = 0;
890 }
891 } else if (es_type == MESA_SHADER_TESS_EVAL) {
892 es_vgpr_comp_cnt = info->uses_prim_id ? 3 : 2;
893 } else {
894 unreachable("invalid shader ES type");
895 }
896
897 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
898 * VGPR[0:4] are always loaded.
899 */
900 if (info->uses_invocation_id) {
901 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
902 } else if (info->uses_prim_id) {
903 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
904 } else if (info->gs.vertices_in >= 3) {
905 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
906 } else {
907 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
908 }
909
910 config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
911 config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
912 S_00B22C_OC_LDS_EN(es_type == MESA_SHADER_TESS_EVAL);
913 } else if (pdevice->rad_info.chip_class >= GFX9 &&
914 stage == MESA_SHADER_TESS_CTRL) {
915 config_out->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt);
916 } else {
917 config_out->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt);
918 }
919 }
920
921 struct radv_shader_variant *
922 radv_shader_variant_create(struct radv_device *device,
923 const struct radv_shader_binary *binary,
924 bool keep_shader_info)
925 {
926 struct ac_shader_config config = {0};
927 struct ac_rtld_binary rtld_binary = {0};
928 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
929 if (!variant)
930 return NULL;
931
932 variant->ref_count = 1;
933
934 if (binary->type == RADV_BINARY_TYPE_RTLD) {
935 struct ac_rtld_symbol lds_symbols[2];
936 unsigned num_lds_symbols = 0;
937 const char *elf_data = (const char *)((struct radv_shader_binary_rtld *)binary)->data;
938 size_t elf_size = ((struct radv_shader_binary_rtld *)binary)->elf_size;
939
940 if (device->physical_device->rad_info.chip_class >= GFX9 &&
941 (binary->stage == MESA_SHADER_GEOMETRY || binary->info.is_ngg) &&
942 !binary->is_gs_copy_shader) {
943 /* We add this symbol even on LLVM <= 8 to ensure that
944 * shader->config.lds_size is set correctly below.
945 */
946 struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
947 sym->name = "esgs_ring";
948 sym->size = binary->info.ngg_info.esgs_ring_size;
949 sym->align = 64 * 1024;
950 }
951
952 if (binary->info.is_ngg &&
953 binary->stage == MESA_SHADER_GEOMETRY) {
954 struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
955 sym->name = "ngg_emit";
956 sym->size = binary->info.ngg_info.ngg_emit_size * 4;
957 sym->align = 4;
958 }
959
960 struct ac_rtld_open_info open_info = {
961 .info = &device->physical_device->rad_info,
962 .shader_type = binary->stage,
963 .wave_size = binary->info.wave_size,
964 .num_parts = 1,
965 .elf_ptrs = &elf_data,
966 .elf_sizes = &elf_size,
967 .num_shared_lds_symbols = num_lds_symbols,
968 .shared_lds_symbols = lds_symbols,
969 };
970
971 if (!ac_rtld_open(&rtld_binary, open_info)) {
972 free(variant);
973 return NULL;
974 }
975
976 if (!ac_rtld_read_config(&rtld_binary, &config)) {
977 ac_rtld_close(&rtld_binary);
978 free(variant);
979 return NULL;
980 }
981
982 /* Enable 64-bit and 16-bit denormals, because there is no performance
983 * cost.
984 *
985 * If denormals are enabled, all floating-point output modifiers are
986 * ignored.
987 *
988 * Don't enable denormals for 32-bit floats, because:
989 * - Floating-point output modifiers would be ignored by the hw.
990 * - Some opcodes don't support denormals, such as v_mad_f32. We would
991 * have to stop using those.
992 * - GFX6 & GFX7 would be very slow.
993 */
994 config.float_mode |= V_00B028_FP_64_DENORMS;
995
996 if (rtld_binary.lds_size > 0) {
997 unsigned alloc_granularity = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
998 config.lds_size = align(rtld_binary.lds_size, alloc_granularity) / alloc_granularity;
999 }
1000
1001 variant->code_size = rtld_binary.rx_size;
1002 variant->exec_size = rtld_binary.exec_size;
1003 } else {
1004 assert(binary->type == RADV_BINARY_TYPE_LEGACY);
1005 config = ((struct radv_shader_binary_legacy *)binary)->config;
1006 variant->code_size = radv_get_shader_binary_size(((struct radv_shader_binary_legacy *)binary)->code_size);
1007 variant->exec_size = ((struct radv_shader_binary_legacy *)binary)->exec_size;
1008 }
1009
1010 variant->info = binary->info;
1011 radv_postprocess_config(device->physical_device, &config, &binary->info,
1012 binary->stage, &variant->config);
1013
1014 if (radv_device_use_secure_compile(device->instance)) {
1015 if (binary->type == RADV_BINARY_TYPE_RTLD)
1016 ac_rtld_close(&rtld_binary);
1017
1018 return variant;
1019 }
1020
1021 void *dest_ptr = radv_alloc_shader_memory(device, variant);
1022
1023 if (binary->type == RADV_BINARY_TYPE_RTLD) {
1024 struct radv_shader_binary_rtld* bin = (struct radv_shader_binary_rtld *)binary;
1025 struct ac_rtld_upload_info info = {
1026 .binary = &rtld_binary,
1027 .rx_va = radv_buffer_get_va(variant->bo) + variant->bo_offset,
1028 .rx_ptr = dest_ptr,
1029 };
1030
1031 if (!ac_rtld_upload(&info)) {
1032 radv_shader_variant_destroy(device, variant);
1033 ac_rtld_close(&rtld_binary);
1034 return NULL;
1035 }
1036
1037 if (keep_shader_info ||
1038 (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS)) {
1039 const char *disasm_data;
1040 size_t disasm_size;
1041 if (!ac_rtld_get_section_by_name(&rtld_binary, ".AMDGPU.disasm", &disasm_data, &disasm_size)) {
1042 radv_shader_variant_destroy(device, variant);
1043 ac_rtld_close(&rtld_binary);
1044 return NULL;
1045 }
1046
1047 variant->ir_string = bin->llvm_ir_size ? strdup((const char*)(bin->data + bin->elf_size)) : NULL;
1048 variant->disasm_string = malloc(disasm_size + 1);
1049 memcpy(variant->disasm_string, disasm_data, disasm_size);
1050 variant->disasm_string[disasm_size] = 0;
1051 }
1052
1053 ac_rtld_close(&rtld_binary);
1054 } else {
1055 struct radv_shader_binary_legacy* bin = (struct radv_shader_binary_legacy *)binary;
1056 memcpy(dest_ptr, bin->data, bin->code_size);
1057
1058 /* Add end-of-code markers for the UMR disassembler. */
1059 uint32_t *ptr32 = (uint32_t *)dest_ptr + bin->code_size / 4;
1060 for (unsigned i = 0; i < DEBUGGER_NUM_MARKERS; i++)
1061 ptr32[i] = DEBUGGER_END_OF_CODE_MARKER;
1062
1063 variant->ir_string = bin->ir_size ? strdup((const char*)(bin->data + bin->code_size)) : NULL;
1064 variant->disasm_string = bin->disasm_size ? strdup((const char*)(bin->data + bin->code_size + bin->ir_size)) : NULL;
1065 }
1066 return variant;
1067 }
1068
1069 static char *
1070 radv_dump_nir_shaders(struct nir_shader * const *shaders,
1071 int shader_count)
1072 {
1073 char *data = NULL;
1074 char *ret = NULL;
1075 size_t size = 0;
1076 FILE *f = open_memstream(&data, &size);
1077 if (f) {
1078 for (int i = 0; i < shader_count; ++i)
1079 nir_print_shader(shaders[i], f);
1080 fclose(f);
1081 }
1082
1083 ret = malloc(size + 1);
1084 if (ret) {
1085 memcpy(ret, data, size);
1086 ret[size] = 0;
1087 }
1088 free(data);
1089 return ret;
1090 }
1091
1092 static struct radv_shader_variant *
1093 shader_variant_compile(struct radv_device *device,
1094 struct radv_shader_module *module,
1095 struct nir_shader * const *shaders,
1096 int shader_count,
1097 gl_shader_stage stage,
1098 struct radv_shader_info *info,
1099 struct radv_nir_compiler_options *options,
1100 bool gs_copy_shader,
1101 bool keep_shader_info,
1102 bool use_aco,
1103 struct radv_shader_binary **binary_out)
1104 {
1105 enum radeon_family chip_family = device->physical_device->rad_info.family;
1106 struct radv_shader_binary *binary = NULL;
1107
1108 options->family = chip_family;
1109 options->chip_class = device->physical_device->rad_info.chip_class;
1110 options->dump_shader = radv_can_dump_shader(device, module, gs_copy_shader);
1111 options->dump_preoptir = options->dump_shader &&
1112 device->instance->debug_flags & RADV_DEBUG_PREOPTIR;
1113 options->record_ir = keep_shader_info;
1114 options->check_ir = device->instance->debug_flags & RADV_DEBUG_CHECKIR;
1115 options->tess_offchip_block_dw_size = device->tess_offchip_block_dw_size;
1116 options->address32_hi = device->physical_device->rad_info.address32_hi;
1117 options->has_ls_vgpr_init_bug = device->physical_device->rad_info.has_ls_vgpr_init_bug;
1118 options->use_ngg_streamout = device->physical_device->use_ngg_streamout;
1119
1120 struct radv_shader_args args = {};
1121 args.options = options;
1122 args.shader_info = info;
1123 args.is_gs_copy_shader = gs_copy_shader;
1124 radv_declare_shader_args(&args,
1125 gs_copy_shader ? MESA_SHADER_VERTEX
1126 : shaders[shader_count - 1]->info.stage,
1127 shader_count >= 2,
1128 shader_count >= 2 ? shaders[shader_count - 2]->info.stage
1129 : MESA_SHADER_VERTEX);
1130
1131 if (!use_aco || options->dump_shader || options->record_ir)
1132 ac_init_llvm_once();
1133
1134 if (use_aco) {
1135 aco_compile_shader(shader_count, shaders, &binary, &args);
1136 binary->info = *info;
1137 } else {
1138 enum ac_target_machine_options tm_options = 0;
1139 struct ac_llvm_compiler ac_llvm;
1140 bool thread_compiler;
1141
1142 tm_options |= AC_TM_SUPPORTS_SPILL;
1143 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
1144 tm_options |= AC_TM_SISCHED;
1145 if (options->check_ir)
1146 tm_options |= AC_TM_CHECK_IR;
1147 if (device->instance->debug_flags & RADV_DEBUG_NO_LOAD_STORE_OPT)
1148 tm_options |= AC_TM_NO_LOAD_STORE_OPT;
1149
1150 thread_compiler = !(device->instance->debug_flags & RADV_DEBUG_NOTHREADLLVM);
1151 radv_init_llvm_compiler(&ac_llvm,
1152 thread_compiler,
1153 chip_family, tm_options,
1154 info->wave_size);
1155
1156 if (gs_copy_shader) {
1157 assert(shader_count == 1);
1158 radv_compile_gs_copy_shader(&ac_llvm, *shaders, &binary,
1159 &args);
1160 } else {
1161 radv_compile_nir_shader(&ac_llvm, &binary, &args,
1162 shaders, shader_count);
1163 }
1164
1165 binary->info = *info;
1166 radv_destroy_llvm_compiler(&ac_llvm, thread_compiler);
1167 }
1168
1169 struct radv_shader_variant *variant = radv_shader_variant_create(device, binary,
1170 keep_shader_info);
1171 if (!variant) {
1172 free(binary);
1173 return NULL;
1174 }
1175 variant->aco_used = use_aco;
1176
1177 if (options->dump_shader) {
1178 fprintf(stderr, "disasm:\n%s\n", variant->disasm_string);
1179 }
1180
1181
1182 if (keep_shader_info) {
1183 variant->nir_string = radv_dump_nir_shaders(shaders, shader_count);
1184 if (!gs_copy_shader && !module->nir) {
1185 variant->spirv = malloc(module->size);
1186 if (!variant->spirv) {
1187 free(variant);
1188 free(binary);
1189 return NULL;
1190 }
1191
1192 memcpy(variant->spirv, module->data, module->size);
1193 variant->spirv_size = module->size;
1194 }
1195 }
1196
1197 if (binary_out)
1198 *binary_out = binary;
1199 else
1200 free(binary);
1201
1202 return variant;
1203 }
1204
1205 struct radv_shader_variant *
1206 radv_shader_variant_compile(struct radv_device *device,
1207 struct radv_shader_module *module,
1208 struct nir_shader *const *shaders,
1209 int shader_count,
1210 struct radv_pipeline_layout *layout,
1211 const struct radv_shader_variant_key *key,
1212 struct radv_shader_info *info,
1213 bool keep_shader_info,
1214 bool use_aco,
1215 struct radv_shader_binary **binary_out)
1216 {
1217 struct radv_nir_compiler_options options = {0};
1218
1219 options.layout = layout;
1220 if (key)
1221 options.key = *key;
1222
1223 options.explicit_scratch_args = use_aco;
1224 options.robust_buffer_access = device->robust_buffer_access;
1225
1226 return shader_variant_compile(device, module, shaders, shader_count, shaders[shader_count - 1]->info.stage, info,
1227 &options, false, keep_shader_info, use_aco, binary_out);
1228 }
1229
1230 struct radv_shader_variant *
1231 radv_create_gs_copy_shader(struct radv_device *device,
1232 struct nir_shader *shader,
1233 struct radv_shader_info *info,
1234 struct radv_shader_binary **binary_out,
1235 bool keep_shader_info,
1236 bool multiview)
1237 {
1238 struct radv_nir_compiler_options options = {0};
1239
1240 options.key.has_multiview_view_index = multiview;
1241
1242 return shader_variant_compile(device, NULL, &shader, 1, MESA_SHADER_VERTEX,
1243 info, &options, true, keep_shader_info, false, binary_out);
1244 }
1245
1246 void
1247 radv_shader_variant_destroy(struct radv_device *device,
1248 struct radv_shader_variant *variant)
1249 {
1250 if (!p_atomic_dec_zero(&variant->ref_count))
1251 return;
1252
1253 mtx_lock(&device->shader_slab_mutex);
1254 list_del(&variant->slab_list);
1255 mtx_unlock(&device->shader_slab_mutex);
1256
1257 free(variant->spirv);
1258 free(variant->nir_string);
1259 free(variant->disasm_string);
1260 free(variant->ir_string);
1261 free(variant);
1262 }
1263
1264 const char *
1265 radv_get_shader_name(struct radv_shader_info *info,
1266 gl_shader_stage stage)
1267 {
1268 switch (stage) {
1269 case MESA_SHADER_VERTEX:
1270 if (info->vs.as_ls)
1271 return "Vertex Shader as LS";
1272 else if (info->vs.as_es)
1273 return "Vertex Shader as ES";
1274 else if (info->is_ngg)
1275 return "Vertex Shader as ESGS";
1276 else
1277 return "Vertex Shader as VS";
1278 case MESA_SHADER_TESS_CTRL:
1279 return "Tessellation Control Shader";
1280 case MESA_SHADER_TESS_EVAL:
1281 if (info->tes.as_es)
1282 return "Tessellation Evaluation Shader as ES";
1283 else if (info->is_ngg)
1284 return "Tessellation Evaluation Shader as ESGS";
1285 else
1286 return "Tessellation Evaluation Shader as VS";
1287 case MESA_SHADER_GEOMETRY:
1288 return "Geometry Shader";
1289 case MESA_SHADER_FRAGMENT:
1290 return "Pixel Shader";
1291 case MESA_SHADER_COMPUTE:
1292 return "Compute Shader";
1293 default:
1294 return "Unknown shader";
1295 };
1296 }
1297
1298 unsigned
1299 radv_get_max_workgroup_size(enum chip_class chip_class,
1300 gl_shader_stage stage,
1301 const unsigned *sizes)
1302 {
1303 switch (stage) {
1304 case MESA_SHADER_TESS_CTRL:
1305 return chip_class >= GFX7 ? 128 : 64;
1306 case MESA_SHADER_GEOMETRY:
1307 return chip_class >= GFX9 ? 128 : 64;
1308 case MESA_SHADER_COMPUTE:
1309 break;
1310 default:
1311 return 0;
1312 }
1313
1314 unsigned max_workgroup_size = sizes[0] * sizes[1] * sizes[2];
1315 return max_workgroup_size;
1316 }
1317
1318 unsigned
1319 radv_get_max_waves(struct radv_device *device,
1320 struct radv_shader_variant *variant,
1321 gl_shader_stage stage)
1322 {
1323 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
1324 unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
1325 uint8_t wave_size = variant->info.wave_size;
1326 struct ac_shader_config *conf = &variant->config;
1327 unsigned max_simd_waves;
1328 unsigned lds_per_wave = 0;
1329
1330 max_simd_waves = device->physical_device->rad_info.max_wave64_per_simd;
1331
1332 if (stage == MESA_SHADER_FRAGMENT) {
1333 lds_per_wave = conf->lds_size * lds_increment +
1334 align(variant->info.ps.num_interp * 48,
1335 lds_increment);
1336 } else if (stage == MESA_SHADER_COMPUTE) {
1337 unsigned max_workgroup_size =
1338 radv_get_max_workgroup_size(chip_class, stage, variant->info.cs.block_size);
1339 lds_per_wave = (conf->lds_size * lds_increment) /
1340 DIV_ROUND_UP(max_workgroup_size, wave_size);
1341 }
1342
1343 if (conf->num_sgprs) {
1344 unsigned sgprs = align(conf->num_sgprs, chip_class >= GFX8 ? 16 : 8);
1345 max_simd_waves =
1346 MIN2(max_simd_waves,
1347 device->physical_device->rad_info.num_physical_sgprs_per_simd /
1348 sgprs);
1349 }
1350
1351 if (conf->num_vgprs) {
1352 unsigned vgprs = align(conf->num_vgprs, wave_size == 32 ? 8 : 4);
1353 max_simd_waves =
1354 MIN2(max_simd_waves,
1355 RADV_NUM_PHYSICAL_VGPRS / vgprs);
1356 }
1357
1358 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
1359 * that PS can use.
1360 */
1361 if (lds_per_wave)
1362 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
1363
1364 return max_simd_waves;
1365 }
1366
1367 static void
1368 generate_shader_stats(struct radv_device *device,
1369 struct radv_shader_variant *variant,
1370 gl_shader_stage stage,
1371 struct _mesa_string_buffer *buf)
1372 {
1373 struct ac_shader_config *conf = &variant->config;
1374 unsigned max_simd_waves = radv_get_max_waves(device, variant, stage);
1375
1376 if (stage == MESA_SHADER_FRAGMENT) {
1377 _mesa_string_buffer_printf(buf, "*** SHADER CONFIG ***\n"
1378 "SPI_PS_INPUT_ADDR = 0x%04x\n"
1379 "SPI_PS_INPUT_ENA = 0x%04x\n",
1380 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
1381 }
1382
1383 _mesa_string_buffer_printf(buf, "*** SHADER STATS ***\n"
1384 "SGPRS: %d\n"
1385 "VGPRS: %d\n"
1386 "Spilled SGPRs: %d\n"
1387 "Spilled VGPRs: %d\n"
1388 "PrivMem VGPRS: %d\n"
1389 "Code Size: %d bytes\n"
1390 "LDS: %d blocks\n"
1391 "Scratch: %d bytes per wave\n"
1392 "Max Waves: %d\n"
1393 "********************\n\n\n",
1394 conf->num_sgprs, conf->num_vgprs,
1395 conf->spilled_sgprs, conf->spilled_vgprs,
1396 variant->info.private_mem_vgprs, variant->exec_size,
1397 conf->lds_size, conf->scratch_bytes_per_wave,
1398 max_simd_waves);
1399 }
1400
1401 void
1402 radv_shader_dump_stats(struct radv_device *device,
1403 struct radv_shader_variant *variant,
1404 gl_shader_stage stage,
1405 FILE *file)
1406 {
1407 struct _mesa_string_buffer *buf = _mesa_string_buffer_create(NULL, 256);
1408
1409 generate_shader_stats(device, variant, stage, buf);
1410
1411 fprintf(file, "\n%s:\n", radv_get_shader_name(&variant->info, stage));
1412 fprintf(file, "%s", buf->buf);
1413
1414 _mesa_string_buffer_destroy(buf);
1415 }
1416
1417 VkResult
1418 radv_GetShaderInfoAMD(VkDevice _device,
1419 VkPipeline _pipeline,
1420 VkShaderStageFlagBits shaderStage,
1421 VkShaderInfoTypeAMD infoType,
1422 size_t* pInfoSize,
1423 void* pInfo)
1424 {
1425 RADV_FROM_HANDLE(radv_device, device, _device);
1426 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
1427 gl_shader_stage stage = vk_to_mesa_shader_stage(shaderStage);
1428 struct radv_shader_variant *variant = pipeline->shaders[stage];
1429 struct _mesa_string_buffer *buf;
1430 VkResult result = VK_SUCCESS;
1431
1432 /* Spec doesn't indicate what to do if the stage is invalid, so just
1433 * return no info for this. */
1434 if (!variant)
1435 return vk_error(device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1436
1437 switch (infoType) {
1438 case VK_SHADER_INFO_TYPE_STATISTICS_AMD:
1439 if (!pInfo) {
1440 *pInfoSize = sizeof(VkShaderStatisticsInfoAMD);
1441 } else {
1442 unsigned lds_multiplier = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
1443 struct ac_shader_config *conf = &variant->config;
1444
1445 VkShaderStatisticsInfoAMD statistics = {};
1446 statistics.shaderStageMask = shaderStage;
1447 statistics.numPhysicalVgprs = RADV_NUM_PHYSICAL_VGPRS;
1448 statistics.numPhysicalSgprs = device->physical_device->rad_info.num_physical_sgprs_per_simd;
1449 statistics.numAvailableSgprs = statistics.numPhysicalSgprs;
1450
1451 if (stage == MESA_SHADER_COMPUTE) {
1452 unsigned *local_size = variant->info.cs.block_size;
1453 unsigned workgroup_size = local_size[0] * local_size[1] * local_size[2];
1454
1455 statistics.numAvailableVgprs = statistics.numPhysicalVgprs /
1456 ceil((double)workgroup_size / statistics.numPhysicalVgprs);
1457
1458 statistics.computeWorkGroupSize[0] = local_size[0];
1459 statistics.computeWorkGroupSize[1] = local_size[1];
1460 statistics.computeWorkGroupSize[2] = local_size[2];
1461 } else {
1462 statistics.numAvailableVgprs = statistics.numPhysicalVgprs;
1463 }
1464
1465 statistics.resourceUsage.numUsedVgprs = conf->num_vgprs;
1466 statistics.resourceUsage.numUsedSgprs = conf->num_sgprs;
1467 statistics.resourceUsage.ldsSizePerLocalWorkGroup = 32768;
1468 statistics.resourceUsage.ldsUsageSizeInBytes = conf->lds_size * lds_multiplier;
1469 statistics.resourceUsage.scratchMemUsageInBytes = conf->scratch_bytes_per_wave;
1470
1471 size_t size = *pInfoSize;
1472 *pInfoSize = sizeof(statistics);
1473
1474 memcpy(pInfo, &statistics, MIN2(size, *pInfoSize));
1475
1476 if (size < *pInfoSize)
1477 result = VK_INCOMPLETE;
1478 }
1479
1480 break;
1481 case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD:
1482 buf = _mesa_string_buffer_create(NULL, 1024);
1483
1484 _mesa_string_buffer_printf(buf, "%s:\n", radv_get_shader_name(&variant->info, stage));
1485 _mesa_string_buffer_printf(buf, "%s\n\n", variant->ir_string);
1486 _mesa_string_buffer_printf(buf, "%s\n\n", variant->disasm_string);
1487 generate_shader_stats(device, variant, stage, buf);
1488
1489 /* Need to include the null terminator. */
1490 size_t length = buf->length + 1;
1491
1492 if (!pInfo) {
1493 *pInfoSize = length;
1494 } else {
1495 size_t size = *pInfoSize;
1496 *pInfoSize = length;
1497
1498 memcpy(pInfo, buf->buf, MIN2(size, length));
1499
1500 if (size < length)
1501 result = VK_INCOMPLETE;
1502 }
1503
1504 _mesa_string_buffer_destroy(buf);
1505 break;
1506 default:
1507 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
1508 result = VK_ERROR_FEATURE_NOT_PRESENT;
1509 break;
1510 }
1511
1512 return result;
1513 }