src/amd/vulkan/radv_shader.h

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #ifndef RADV_SHADER_H
  29 #define RADV_SHADER_H
  30
  31 #include "ac_binary.h"
  32 #include "amd_family.h"
  33 #include "radv_constants.h"
  34
  35 #include "nir/nir.h"
  36 #include "vulkan/vulkan.h"
  37
  38 struct radv_device;
  39
  40 struct radv_shader_module {
  41         struct nir_shader *nir;
  42         unsigned char sha1[20];
  43         uint32_t size;
  44         char data[0];
  45 };
  46
  47 enum {
  48         RADV_ALPHA_ADJUST_NONE = 0,
  49         RADV_ALPHA_ADJUST_SNORM = 1,
  50         RADV_ALPHA_ADJUST_SINT = 2,
  51         RADV_ALPHA_ADJUST_SSCALED = 3,
  52 };
  53
  54 struct radv_vs_out_key {
  55         uint32_t as_es:1;
  56         uint32_t as_ls:1;
  57         uint32_t as_ngg:1;
  58         uint32_t as_ngg_passthrough:1;
  59         uint32_t export_prim_id:1;
  60         uint32_t export_layer_id:1;
  61         uint32_t export_clip_dists:1;
  62 };
  63
  64 struct radv_vs_variant_key {
  65         struct radv_vs_out_key out;
  66
  67         uint32_t instance_rate_inputs;
  68         uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
  69         uint8_t vertex_attribute_formats[MAX_VERTEX_ATTRIBS];
  70         uint32_t vertex_attribute_bindings[MAX_VERTEX_ATTRIBS];
  71         uint32_t vertex_attribute_offsets[MAX_VERTEX_ATTRIBS];
  72         uint32_t vertex_attribute_strides[MAX_VERTEX_ATTRIBS];
  73
  74         /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
  75          * so we may need to fix it up. */
  76         uint64_t alpha_adjust;
  77
  78         /* For some formats the channels have to be shuffled. */
  79         uint32_t post_shuffle;
  80
  81         /* Output primitive type. */
  82         uint8_t outprim;
  83 };
  84
  85 struct radv_tes_variant_key {
  86         struct radv_vs_out_key out;
  87
  88         uint8_t num_patches;
  89         uint8_t tcs_num_outputs;
  90 };
  91
  92 struct radv_tcs_variant_key {
  93         struct radv_vs_variant_key vs_key;
  94         unsigned primitive_mode;
  95         unsigned input_vertices;
  96         unsigned num_inputs;
  97         uint32_t tes_reads_tess_factors:1;
  98 };
  99
 100 struct radv_fs_variant_key {
 101         uint32_t col_format;
 102         uint8_t log2_ps_iter_samples;
 103         uint8_t num_samples;
 104         uint32_t is_int8;
 105         uint32_t is_int10;
 106 };
 107
 108 struct radv_cs_variant_key {
 109         uint8_t subgroup_size;
 110 };
 111
 112 struct radv_shader_variant_key {
 113         union {
 114                 struct radv_vs_variant_key vs;
 115                 struct radv_fs_variant_key fs;
 116                 struct radv_tes_variant_key tes;
 117                 struct radv_tcs_variant_key tcs;
 118                 struct radv_cs_variant_key cs;
 119
 120                 /* A common prefix of the vs and tes keys. */
 121                 struct radv_vs_out_key vs_common_out;
 122         };
 123         bool has_multiview_view_index;
 124 };
 125
 126 struct radv_nir_compiler_options {
 127         struct radv_pipeline_layout *layout;
 128         struct radv_shader_variant_key key;
 129         bool explicit_scratch_args;
 130         bool clamp_shadow_reference;
 131         bool robust_buffer_access;
 132         bool dump_shader;
 133         bool dump_preoptir;
 134         bool record_ir;
 135         bool check_ir;
 136         bool has_ls_vgpr_init_bug;
 137         bool use_ngg_streamout;
 138         enum radeon_family family;
 139         enum chip_class chip_class;
 140         uint32_t tess_offchip_block_dw_size;
 141         uint32_t address32_hi;
 142 };
 143
 144 enum radv_ud_index {
 145         AC_UD_SCRATCH_RING_OFFSETS = 0,
 146         AC_UD_PUSH_CONSTANTS = 1,
 147         AC_UD_INLINE_PUSH_CONSTANTS = 2,
 148         AC_UD_INDIRECT_DESCRIPTOR_SETS = 3,
 149         AC_UD_VIEW_INDEX = 4,
 150         AC_UD_STREAMOUT_BUFFERS = 5,
 151         AC_UD_SHADER_START = 6,
 152         AC_UD_VS_VERTEX_BUFFERS = AC_UD_SHADER_START,
 153         AC_UD_VS_BASE_VERTEX_START_INSTANCE,
 154         AC_UD_VS_MAX_UD,
 155         AC_UD_PS_MAX_UD,
 156         AC_UD_CS_GRID_SIZE = AC_UD_SHADER_START,
 157         AC_UD_CS_MAX_UD,
 158         AC_UD_GS_MAX_UD,
 159         AC_UD_TCS_MAX_UD,
 160         AC_UD_TES_MAX_UD,
 161         AC_UD_MAX_UD = AC_UD_TCS_MAX_UD,
 162 };
 163
 164 struct radv_stream_output {
 165         uint8_t location;
 166         uint8_t buffer;
 167         uint16_t offset;
 168         uint8_t component_mask;
 169         uint8_t stream;
 170 };
 171
 172 struct radv_streamout_info {
 173         uint16_t num_outputs;
 174         struct radv_stream_output outputs[MAX_SO_OUTPUTS];
 175         uint16_t strides[MAX_SO_BUFFERS];
 176         uint32_t enabled_stream_buffers_mask;
 177 };
 178
 179 struct radv_userdata_info {
 180         int8_t sgpr_idx;
 181         uint8_t num_sgprs;
 182 };
 183
 184 struct radv_userdata_locations {
 185         struct radv_userdata_info descriptor_sets[MAX_SETS];
 186         struct radv_userdata_info shader_data[AC_UD_MAX_UD];
 187         uint32_t descriptor_sets_enabled;
 188 };
 189
 190 struct radv_vs_output_info {
 191         uint8_t vs_output_param_offset[VARYING_SLOT_MAX];
 192         uint8_t clip_dist_mask;
 193         uint8_t cull_dist_mask;
 194         uint8_t param_exports;
 195         bool writes_pointsize;
 196         bool writes_layer;
 197         bool writes_viewport_index;
 198         bool export_prim_id;
 199         unsigned pos_exports;
 200 };
 201
 202 struct radv_es_output_info {
 203        uint32_t esgs_itemsize;
 204 };
 205
 206 struct gfx9_gs_info {
 207         uint32_t vgt_gs_onchip_cntl;
 208         uint32_t vgt_gs_max_prims_per_subgroup;
 209         uint32_t vgt_esgs_ring_itemsize;
 210         uint32_t lds_size;
 211 };
 212
 213 struct gfx10_ngg_info {
 214         uint16_t ngg_emit_size; /* in dwords */
 215         uint32_t hw_max_esverts;
 216         uint32_t max_gsprims;
 217         uint32_t max_out_verts;
 218         uint32_t prim_amp_factor;
 219         uint32_t vgt_esgs_ring_itemsize;
 220         uint32_t esgs_ring_size;
 221         bool max_vert_out_per_gs_instance;
 222 };
 223
 224 struct radv_shader_info {
 225         bool loads_push_constants;
 226         bool loads_dynamic_offsets;
 227         uint8_t min_push_constant_used;
 228         uint8_t max_push_constant_used;
 229         bool has_only_32bit_push_constants;
 230         bool has_indirect_push_constants;
 231         uint8_t num_inline_push_consts;
 232         uint8_t base_inline_push_consts;
 233         uint32_t desc_set_used_mask;
 234         bool needs_multiview_view_index;
 235         bool uses_invocation_id;
 236         bool uses_prim_id;
 237         uint8_t wave_size;
 238         struct radv_userdata_locations user_sgprs_locs;
 239         unsigned num_user_sgprs;
 240         unsigned num_input_sgprs;
 241         unsigned num_input_vgprs;
 242         unsigned private_mem_vgprs;
 243         bool need_indirect_descriptor_sets;
 244         bool is_ngg;
 245         bool is_ngg_passthrough;
 246         struct {
 247                 uint64_t ls_outputs_written;
 248                 uint8_t input_usage_mask[VERT_ATTRIB_MAX];
 249                 uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
 250                 bool has_vertex_buffers; /* needs vertex buffers and base/start */
 251                 bool needs_draw_id;
 252                 bool needs_instance_id;
 253                 struct radv_vs_output_info outinfo;
 254                 struct radv_es_output_info es_info;
 255                 bool as_es;
 256                 bool as_ls;
 257                 bool export_prim_id;
 258         } vs;
 259         struct {
 260                 uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
 261                 uint8_t num_stream_output_components[4];
 262                 uint8_t output_streams[VARYING_SLOT_VAR31 + 1];
 263                 uint8_t max_stream;
 264                 bool writes_memory;
 265                 unsigned gsvs_vertex_size;
 266                 unsigned max_gsvs_emit_size;
 267                 unsigned vertices_in;
 268                 unsigned vertices_out;
 269                 unsigned output_prim;
 270                 unsigned invocations;
 271                 unsigned es_type; /* GFX9: VS or TES */
 272         } gs;
 273         struct {
 274                 uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
 275                 struct radv_vs_output_info outinfo;
 276                 struct radv_es_output_info es_info;
 277                 bool as_es;
 278                 unsigned primitive_mode;
 279                 enum gl_tess_spacing spacing;
 280                 bool ccw;
 281                 bool point_mode;
 282                 bool export_prim_id;
 283         } tes;
 284         struct {
 285                 bool force_persample;
 286                 bool needs_sample_positions;
 287                 bool writes_memory;
 288                 bool writes_z;
 289                 bool writes_stencil;
 290                 bool writes_sample_mask;
 291                 bool has_pcoord;
 292                 bool prim_id_input;
 293                 bool layer_input;
 294                 uint8_t num_input_clips_culls;
 295                 uint32_t input_mask;
 296                 uint32_t flat_shaded_mask;
 297                 uint32_t explicit_shaded_mask;
 298                 uint32_t float16_shaded_mask;
 299                 uint32_t num_interp;
 300                 bool can_discard;
 301                 bool early_fragment_test;
 302                 bool post_depth_coverage;
 303         } ps;
 304         struct {
 305                 bool uses_grid_size;
 306                 bool uses_block_id[3];
 307                 bool uses_thread_id[3];
 308                 bool uses_local_invocation_idx;
 309                 unsigned block_size[3];
 310         } cs;
 311         struct {
 312                 uint64_t outputs_written;
 313                 uint64_t patch_outputs_written;
 314                 unsigned tcs_vertices_out;
 315                 uint32_t num_patches;
 316                 uint32_t lds_size;
 317         } tcs;
 318
 319         struct radv_streamout_info so;
 320
 321         struct gfx9_gs_info gs_ring_info;
 322         struct gfx10_ngg_info ngg_info;
 323
 324         unsigned float_controls_mode;
 325 };
 326
 327 enum radv_shader_binary_type {
 328         RADV_BINARY_TYPE_LEGACY,
 329         RADV_BINARY_TYPE_RTLD
 330 };
 331
 332 struct radv_shader_binary {
 333         enum radv_shader_binary_type type;
 334         gl_shader_stage stage;
 335         bool is_gs_copy_shader;
 336
 337         struct radv_shader_info info;
 338
 339         /* Self-referential size so we avoid consistency issues. */
 340         uint32_t total_size;
 341 };
 342
 343 struct radv_shader_binary_legacy {
 344         struct radv_shader_binary base;
 345         struct ac_shader_config config;
 346         unsigned code_size;
 347         unsigned exec_size;
 348         unsigned ir_size;
 349         unsigned disasm_size;
 350
 351         /* data has size of code_size + ir_size + disasm_size + 2, where
 352          * the +2 is for 0 of the ir strings. */
 353         uint8_t data[0];
 354 };
 355
 356 struct radv_shader_binary_rtld {
 357         struct radv_shader_binary base;
 358         unsigned elf_size;
 359         unsigned llvm_ir_size;
 360         uint8_t data[0];
 361 };
 362
 363 struct radv_shader_variant {
 364         uint32_t ref_count;
 365
 366         struct radeon_winsys_bo *bo;
 367         uint64_t bo_offset;
 368         struct ac_shader_config config;
 369         uint32_t code_size;
 370         uint32_t exec_size;
 371         struct radv_shader_info info;
 372
 373         /* debug only */
 374         bool aco_used;
 375         char *spirv;
 376         uint32_t spirv_size;
 377         char *nir_string;
 378         char *disasm_string;
 379         char *ir_string;
 380
 381         struct list_head slab_list;
 382 };
 383
 384 struct radv_shader_slab {
 385         struct list_head slabs;
 386         struct list_head shaders;
 387         struct radeon_winsys_bo *bo;
 388         uint64_t size;
 389         char *ptr;
 390 };
 391
 392 void
 393 radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
 394                   bool allow_copies);
 395 bool
 396 radv_nir_lower_ycbcr_textures(nir_shader *shader,
 397                              const struct radv_pipeline_layout *layout);
 398
 399 nir_shader *
 400 radv_shader_compile_to_nir(struct radv_device *device,
 401                            struct radv_shader_module *module,
 402                            const char *entrypoint_name,
 403                            gl_shader_stage stage,
 404                            const VkSpecializationInfo *spec_info,
 405                            const VkPipelineCreateFlags flags,
 406                            const struct radv_pipeline_layout *layout,
 407                            bool use_aco);
 408
 409 void *
 410 radv_alloc_shader_memory(struct radv_device *device,
 411                           struct radv_shader_variant *shader);
 412
 413 void
 414 radv_destroy_shader_slabs(struct radv_device *device);
 415
 416 void
 417 radv_create_shaders(struct radv_pipeline *pipeline,
 418                     struct radv_device *device,
 419                     struct radv_pipeline_cache *cache,
 420                     const struct radv_pipeline_key *key,
 421                     const VkPipelineShaderStageCreateInfo **pStages,
 422                     const VkPipelineCreateFlags flags,
 423                     VkPipelineCreationFeedbackEXT *pipeline_feedback,
 424                     VkPipelineCreationFeedbackEXT **stage_feedbacks);
 425
 426 struct radv_shader_variant *
 427 radv_shader_variant_create(struct radv_device *device,
 428                            const struct radv_shader_binary *binary,
 429                            bool keep_shader_info);
 430 struct radv_shader_variant *
 431 radv_shader_variant_compile(struct radv_device *device,
 432                             struct radv_shader_module *module,
 433                             struct nir_shader *const *shaders,
 434                             int shader_count,
 435                             struct radv_pipeline_layout *layout,
 436                             const struct radv_shader_variant_key *key,
 437                             struct radv_shader_info *info,
 438                             bool keep_shader_info,
 439                             bool use_aco,
 440                             struct radv_shader_binary **binary_out);
 441
 442 struct radv_shader_variant *
 443 radv_create_gs_copy_shader(struct radv_device *device, struct nir_shader *nir,
 444                            struct radv_shader_info *info,
 445                            struct radv_shader_binary **binary_out,
 446                            bool multiview,  bool keep_shader_info,
 447                            bool use_aco);
 448
 449 void
 450 radv_shader_variant_destroy(struct radv_device *device,
 451                             struct radv_shader_variant *variant);
 452
 453
 454 unsigned
 455 radv_get_max_waves(struct radv_device *device,
 456                    struct radv_shader_variant *variant,
 457                    gl_shader_stage stage);
 458
 459 unsigned
 460 radv_get_max_workgroup_size(enum chip_class chip_class,
 461                             gl_shader_stage stage,
 462                             const unsigned *sizes);
 463
 464 const char *
 465 radv_get_shader_name(struct radv_shader_info *info,
 466                      gl_shader_stage stage);
 467
 468 void
 469 radv_shader_dump_stats(struct radv_device *device,
 470                        struct radv_shader_variant *variant,
 471                        gl_shader_stage stage,
 472                        FILE *file);
 473
 474 bool
 475 radv_can_dump_shader(struct radv_device *device,
 476                      struct radv_shader_module *module,
 477                      bool is_gs_copy_shader);
 478
 479 bool
 480 radv_can_dump_shader_stats(struct radv_device *device,
 481                            struct radv_shader_module *module);
 482
 483 static inline unsigned
 484 shader_io_get_unique_index(gl_varying_slot slot)
 485 {
 486         /* handle patch indices separate */
 487         if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
 488                 return 0;
 489         if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
 490                 return 1;
 491         if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
 492                 return 2 + (slot - VARYING_SLOT_PATCH0);
 493         if (slot == VARYING_SLOT_POS)
 494                 return 0;
 495         if (slot == VARYING_SLOT_PSIZ)
 496                 return 1;
 497         if (slot == VARYING_SLOT_CLIP_DIST0)
 498                 return 2;
 499         if (slot == VARYING_SLOT_CLIP_DIST1)
 500                 return 3;
 501         /* 3 is reserved for clip dist as well */
 502         if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
 503                 return 4 + (slot - VARYING_SLOT_VAR0);
 504         unreachable("illegal slot in get unique index\n");
 505 }
 506
 507 void
 508 radv_lower_fs_io(nir_shader *nir);
 509
 510 #endif