src/amd/vulkan/radv_shader.h

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #ifndef RADV_SHADER_H
  29 #define RADV_SHADER_H
  30
  31 #include "radv_debug.h"
  32 #include "radv_private.h"
  33
  34 #include "nir/nir.h"
  35
  36 /* descriptor index into scratch ring offsets */
  37 #define RING_SCRATCH 0
  38 #define RING_ESGS_VS 1
  39 #define RING_ESGS_GS 2
  40 #define RING_GSVS_VS 3
  41 #define RING_GSVS_GS 4
  42 #define RING_HS_TESS_FACTOR 5
  43 #define RING_HS_TESS_OFFCHIP 6
  44 #define RING_PS_SAMPLE_POSITIONS 7
  45
  46 // Match MAX_SETS from radv_descriptor_set.h
  47 #define RADV_UD_MAX_SETS MAX_SETS
  48
  49 #define RADV_NUM_PHYSICAL_VGPRS 256
  50
  51 struct radv_shader_module {
  52         struct nir_shader *nir;
  53         unsigned char sha1[20];
  54         uint32_t size;
  55         char data[0];
  56 };
  57
  58 enum {
  59         RADV_ALPHA_ADJUST_NONE = 0,
  60         RADV_ALPHA_ADJUST_SNORM = 1,
  61         RADV_ALPHA_ADJUST_SINT = 2,
  62         RADV_ALPHA_ADJUST_SSCALED = 3,
  63 };
  64
  65 struct radv_vs_variant_key {
  66         uint32_t instance_rate_inputs;
  67         uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
  68
  69         /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
  70          * so we may need to fix it up. */
  71         uint64_t alpha_adjust;
  72
  73         uint32_t as_es:1;
  74         uint32_t as_ls:1;
  75         uint32_t export_prim_id:1;
  76         uint32_t export_layer_id:1;
  77 };
  78
  79 struct radv_tes_variant_key {
  80         uint32_t as_es:1;
  81         uint32_t export_prim_id:1;
  82         uint32_t export_layer_id:1;
  83         uint8_t num_patches;
  84         uint8_t tcs_num_outputs;
  85 };
  86
  87 struct radv_tcs_variant_key {
  88         struct radv_vs_variant_key vs_key;
  89         unsigned primitive_mode;
  90         unsigned input_vertices;
  91         unsigned num_inputs;
  92         uint32_t tes_reads_tess_factors:1;
  93 };
  94
  95 struct radv_fs_variant_key {
  96         uint32_t col_format;
  97         uint8_t log2_ps_iter_samples;
  98         uint8_t num_samples;
  99         uint32_t is_int8;
 100         uint32_t is_int10;
 101 };
 102
 103 struct radv_shader_variant_key {
 104         union {
 105                 struct radv_vs_variant_key vs;
 106                 struct radv_fs_variant_key fs;
 107                 struct radv_tes_variant_key tes;
 108                 struct radv_tcs_variant_key tcs;
 109         };
 110         bool has_multiview_view_index;
 111 };
 112
 113 struct radv_nir_compiler_options {
 114         struct radv_pipeline_layout *layout;
 115         struct radv_shader_variant_key key;
 116         bool unsafe_math;
 117         bool supports_spill;
 118         bool clamp_shadow_reference;
 119         bool dump_shader;
 120         bool dump_preoptir;
 121         bool record_llvm_ir;
 122         bool check_ir;
 123         enum radeon_family family;
 124         enum chip_class chip_class;
 125         uint32_t tess_offchip_block_dw_size;
 126         uint32_t address32_hi;
 127 };
 128
 129 enum radv_ud_index {
 130         AC_UD_SCRATCH_RING_OFFSETS = 0,
 131         AC_UD_PUSH_CONSTANTS = 1,
 132         AC_UD_INDIRECT_DESCRIPTOR_SETS = 2,
 133         AC_UD_VIEW_INDEX = 3,
 134         AC_UD_SHADER_START = 4,
 135         AC_UD_VS_VERTEX_BUFFERS = AC_UD_SHADER_START,
 136         AC_UD_VS_BASE_VERTEX_START_INSTANCE,
 137         AC_UD_VS_MAX_UD,
 138         AC_UD_PS_MAX_UD,
 139         AC_UD_CS_GRID_SIZE = AC_UD_SHADER_START,
 140         AC_UD_CS_MAX_UD,
 141         AC_UD_GS_MAX_UD,
 142         AC_UD_TCS_MAX_UD,
 143         AC_UD_TES_MAX_UD,
 144         AC_UD_MAX_UD = AC_UD_TCS_MAX_UD,
 145 };
 146 struct radv_shader_info {
 147         bool loads_push_constants;
 148         uint32_t desc_set_used_mask;
 149         bool needs_multiview_view_index;
 150         bool uses_invocation_id;
 151         bool uses_prim_id;
 152         struct {
 153                 uint64_t ls_outputs_written;
 154                 uint8_t input_usage_mask[VERT_ATTRIB_MAX];
 155                 uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
 156                 bool has_vertex_buffers; /* needs vertex buffers and base/start */
 157                 bool needs_draw_id;
 158                 bool needs_instance_id;
 159         } vs;
 160         struct {
 161                 uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
 162                 uint8_t num_stream_output_components[4];
 163                 uint8_t output_streams[VARYING_SLOT_VAR31 + 1];
 164                 uint8_t max_stream;
 165         } gs;
 166         struct {
 167                 uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
 168         } tes;
 169         struct {
 170                 bool force_persample;
 171                 bool needs_sample_positions;
 172                 bool uses_input_attachments;
 173                 bool writes_memory;
 174                 bool writes_z;
 175                 bool writes_stencil;
 176                 bool writes_sample_mask;
 177                 bool has_pcoord;
 178                 bool prim_id_input;
 179                 bool layer_input;
 180                 uint8_t num_input_clips_culls;
 181         } ps;
 182         struct {
 183                 bool uses_grid_size;
 184                 bool uses_block_id[3];
 185                 bool uses_thread_id[3];
 186                 bool uses_local_invocation_idx;
 187         } cs;
 188         struct {
 189                 uint64_t outputs_written;
 190                 uint64_t patch_outputs_written;
 191         } tcs;
 192 };
 193
 194 struct radv_userdata_info {
 195         int8_t sgpr_idx;
 196         uint8_t num_sgprs;
 197         bool indirect;
 198 };
 199
 200 struct radv_userdata_locations {
 201         struct radv_userdata_info descriptor_sets[RADV_UD_MAX_SETS];
 202         struct radv_userdata_info shader_data[AC_UD_MAX_UD];
 203         uint32_t descriptor_sets_enabled;
 204 };
 205
 206 struct radv_vs_output_info {
 207         uint8_t vs_output_param_offset[VARYING_SLOT_MAX];
 208         uint8_t clip_dist_mask;
 209         uint8_t cull_dist_mask;
 210         uint8_t param_exports;
 211         bool writes_pointsize;
 212         bool writes_layer;
 213         bool writes_viewport_index;
 214         bool export_prim_id;
 215         unsigned pos_exports;
 216 };
 217
 218 struct radv_es_output_info {
 219         uint32_t esgs_itemsize;
 220 };
 221
 222 struct radv_shader_variant_info {
 223         struct radv_userdata_locations user_sgprs_locs;
 224         struct radv_shader_info info;
 225         unsigned num_user_sgprs;
 226         unsigned num_input_sgprs;
 227         unsigned num_input_vgprs;
 228         unsigned private_mem_vgprs;
 229         bool need_indirect_descriptor_sets;
 230         struct {
 231                 struct {
 232                         struct radv_vs_output_info outinfo;
 233                         struct radv_es_output_info es_info;
 234                         unsigned vgpr_comp_cnt;
 235                         bool as_es;
 236                         bool as_ls;
 237                 } vs;
 238                 struct {
 239                         unsigned num_interp;
 240                         uint32_t input_mask;
 241                         uint32_t flat_shaded_mask;
 242                         bool can_discard;
 243                         bool early_fragment_test;
 244                 } fs;
 245                 struct {
 246                         unsigned block_size[3];
 247                 } cs;
 248                 struct {
 249                         unsigned vertices_in;
 250                         unsigned vertices_out;
 251                         unsigned output_prim;
 252                         unsigned invocations;
 253                         unsigned gsvs_vertex_size;
 254                         unsigned max_gsvs_emit_size;
 255                         unsigned es_type; /* GFX9: VS or TES */
 256                 } gs;
 257                 struct {
 258                         unsigned tcs_vertices_out;
 259                         uint32_t num_patches;
 260                         uint32_t lds_size;
 261                 } tcs;
 262                 struct {
 263                         struct radv_vs_output_info outinfo;
 264                         struct radv_es_output_info es_info;
 265                         bool as_es;
 266                         unsigned primitive_mode;
 267                         enum gl_tess_spacing spacing;
 268                         bool ccw;
 269                         bool point_mode;
 270                 } tes;
 271         };
 272 };
 273
 274 struct radv_shader_variant {
 275         uint32_t ref_count;
 276
 277         struct radeon_winsys_bo *bo;
 278         uint64_t bo_offset;
 279         struct ac_shader_config config;
 280         uint32_t code_size;
 281         struct radv_shader_variant_info info;
 282         unsigned rsrc1;
 283         unsigned rsrc2;
 284
 285         /* debug only */
 286         uint32_t *spirv;
 287         uint32_t spirv_size;
 288         struct nir_shader *nir;
 289         char *disasm_string;
 290         char *llvm_ir_string;
 291
 292         struct list_head slab_list;
 293 };
 294
 295 struct radv_shader_slab {
 296         struct list_head slabs;
 297         struct list_head shaders;
 298         struct radeon_winsys_bo *bo;
 299         uint64_t size;
 300         char *ptr;
 301 };
 302
 303 void
 304 radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
 305                   bool allow_copies);
 306
 307 nir_shader *
 308 radv_shader_compile_to_nir(struct radv_device *device,
 309                            struct radv_shader_module *module,
 310                            const char *entrypoint_name,
 311                            gl_shader_stage stage,
 312                            const VkSpecializationInfo *spec_info,
 313                            const VkPipelineCreateFlags flags);
 314
 315 void *
 316 radv_alloc_shader_memory(struct radv_device *device,
 317                           struct radv_shader_variant *shader);
 318
 319 void
 320 radv_destroy_shader_slabs(struct radv_device *device);
 321
 322 struct radv_shader_variant *
 323 radv_shader_variant_create(struct radv_device *device,
 324                            struct radv_shader_module *module,
 325                            struct nir_shader *const *shaders,
 326                            int shader_count,
 327                            struct radv_pipeline_layout *layout,
 328                            const struct radv_shader_variant_key *key,
 329                            void **code_out,
 330                            unsigned *code_size_out);
 331
 332 struct radv_shader_variant *
 333 radv_create_gs_copy_shader(struct radv_device *device, struct nir_shader *nir,
 334                            void **code_out, unsigned *code_size_out,
 335                            bool multiview);
 336
 337 void
 338 radv_shader_variant_destroy(struct radv_device *device,
 339                             struct radv_shader_variant *variant);
 340
 341 const char *
 342 radv_get_shader_name(struct radv_shader_variant *var, gl_shader_stage stage);
 343
 344 void
 345 radv_shader_dump_stats(struct radv_device *device,
 346                        struct radv_shader_variant *variant,
 347                        gl_shader_stage stage,
 348                        FILE *file);
 349
 350 static inline bool
 351 radv_can_dump_shader(struct radv_device *device,
 352                      struct radv_shader_module *module,
 353                      bool is_gs_copy_shader)
 354 {
 355         if (!(device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS))
 356                 return false;
 357
 358         /* Only dump non-meta shaders, useful for debugging purposes. */
 359         return (module && !module->nir) || is_gs_copy_shader;
 360 }
 361
 362 static inline bool
 363 radv_can_dump_shader_stats(struct radv_device *device,
 364                            struct radv_shader_module *module)
 365 {
 366         /* Only dump non-meta shader stats. */
 367         return device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS &&
 368                module && !module->nir;
 369 }
 370
 371 static inline unsigned shader_io_get_unique_index(gl_varying_slot slot)
 372 {
 373         /* handle patch indices separate */
 374         if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
 375                 return 0;
 376         if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
 377                 return 1;
 378         if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
 379                 return 2 + (slot - VARYING_SLOT_PATCH0);
 380         if (slot == VARYING_SLOT_POS)
 381                 return 0;
 382         if (slot == VARYING_SLOT_PSIZ)
 383                 return 1;
 384         if (slot == VARYING_SLOT_CLIP_DIST0)
 385                 return 2;
 386         /* 3 is reserved for clip dist as well */
 387         if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
 388                 return 4 + (slot - VARYING_SLOT_VAR0);
 389         unreachable("illegal slot in get unique index\n");
 390 }
 391
 392 static inline uint32_t
 393 radv_get_num_physical_sgprs(struct radv_physical_device *physical_device)
 394 {
 395         return physical_device->rad_info.chip_class >= VI ? 800 : 512;
 396 }
 397
 398 #endif