src/amd/vulkan/radv_shader.h

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #ifndef RADV_SHADER_H
  29 #define RADV_SHADER_H
  30
  31 #include "ac_binary.h"
  32 #include "amd_family.h"
  33 #include "radv_constants.h"
  34
  35 #include "nir/nir.h"
  36 #include "vulkan/vulkan.h"
  37
  38 struct radv_device;
  39
  40 struct radv_shader_module {
  41         struct nir_shader *nir;
  42         unsigned char sha1[20];
  43         uint32_t size;
  44         char data[0];
  45 };
  46
  47 enum {
  48         RADV_ALPHA_ADJUST_NONE = 0,
  49         RADV_ALPHA_ADJUST_SNORM = 1,
  50         RADV_ALPHA_ADJUST_SINT = 2,
  51         RADV_ALPHA_ADJUST_SSCALED = 3,
  52 };
  53
  54 struct radv_vs_out_key {
  55         uint32_t as_es:1;
  56         uint32_t as_ls:1;
  57         uint32_t as_ngg:1;
  58         uint32_t export_prim_id:1;
  59         uint32_t export_layer_id:1;
  60         uint32_t export_clip_dists:1;
  61 };
  62
  63 struct radv_vs_variant_key {
  64         struct radv_vs_out_key out;
  65
  66         uint32_t instance_rate_inputs;
  67         uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
  68         uint8_t vertex_attribute_formats[MAX_VERTEX_ATTRIBS];
  69         uint32_t vertex_attribute_bindings[MAX_VERTEX_ATTRIBS];
  70         uint32_t vertex_attribute_offsets[MAX_VERTEX_ATTRIBS];
  71         uint32_t vertex_attribute_strides[MAX_VERTEX_ATTRIBS];
  72
  73         /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
  74          * so we may need to fix it up. */
  75         uint64_t alpha_adjust;
  76
  77         /* For some formats the channels have to be shuffled. */
  78         uint32_t post_shuffle;
  79
  80         /* Output primitive type. */
  81         uint8_t outprim;
  82 };
  83
  84 struct radv_tes_variant_key {
  85         struct radv_vs_out_key out;
  86
  87         uint8_t num_patches;
  88         uint8_t tcs_num_outputs;
  89 };
  90
  91 struct radv_tcs_variant_key {
  92         struct radv_vs_variant_key vs_key;
  93         unsigned primitive_mode;
  94         unsigned input_vertices;
  95         unsigned num_inputs;
  96         uint32_t tes_reads_tess_factors:1;
  97 };
  98
  99 struct radv_fs_variant_key {
 100         uint32_t col_format;
 101         uint8_t log2_ps_iter_samples;
 102         uint8_t num_samples;
 103         uint32_t is_int8;
 104         uint32_t is_int10;
 105 };
 106
 107 struct radv_shader_variant_key {
 108         union {
 109                 struct radv_vs_variant_key vs;
 110                 struct radv_fs_variant_key fs;
 111                 struct radv_tes_variant_key tes;
 112                 struct radv_tcs_variant_key tcs;
 113
 114                 /* A common prefix of the vs and tes keys. */
 115                 struct radv_vs_out_key vs_common_out;
 116         };
 117         bool has_multiview_view_index;
 118 };
 119
 120 struct radv_nir_compiler_options {
 121         struct radv_pipeline_layout *layout;
 122         struct radv_shader_variant_key key;
 123         bool unsafe_math;
 124         bool supports_spill;
 125         bool clamp_shadow_reference;
 126         bool robust_buffer_access;
 127         bool dump_shader;
 128         bool dump_preoptir;
 129         bool record_ir;
 130         bool check_ir;
 131         bool has_ls_vgpr_init_bug;
 132         bool use_ngg_streamout;
 133         enum radeon_family family;
 134         enum chip_class chip_class;
 135         uint32_t tess_offchip_block_dw_size;
 136         uint32_t address32_hi;
 137         uint8_t wave_size;
 138 };
 139
 140 enum radv_ud_index {
 141         AC_UD_SCRATCH_RING_OFFSETS = 0,
 142         AC_UD_PUSH_CONSTANTS = 1,
 143         AC_UD_INLINE_PUSH_CONSTANTS = 2,
 144         AC_UD_INDIRECT_DESCRIPTOR_SETS = 3,
 145         AC_UD_VIEW_INDEX = 4,
 146         AC_UD_STREAMOUT_BUFFERS = 5,
 147         AC_UD_SHADER_START = 6,
 148         AC_UD_VS_VERTEX_BUFFERS = AC_UD_SHADER_START,
 149         AC_UD_VS_BASE_VERTEX_START_INSTANCE,
 150         AC_UD_VS_MAX_UD,
 151         AC_UD_PS_MAX_UD,
 152         AC_UD_CS_GRID_SIZE = AC_UD_SHADER_START,
 153         AC_UD_CS_MAX_UD,
 154         AC_UD_GS_MAX_UD,
 155         AC_UD_TCS_MAX_UD,
 156         AC_UD_TES_MAX_UD,
 157         AC_UD_MAX_UD = AC_UD_TCS_MAX_UD,
 158 };
 159
 160 struct radv_stream_output {
 161         uint8_t location;
 162         uint8_t buffer;
 163         uint16_t offset;
 164         uint8_t component_mask;
 165         uint8_t stream;
 166 };
 167
 168 struct radv_streamout_info {
 169         uint16_t num_outputs;
 170         struct radv_stream_output outputs[MAX_SO_OUTPUTS];
 171         uint16_t strides[MAX_SO_BUFFERS];
 172         uint32_t enabled_stream_buffers_mask;
 173 };
 174
 175 struct radv_userdata_info {
 176         int8_t sgpr_idx;
 177         uint8_t num_sgprs;
 178 };
 179
 180 struct radv_userdata_locations {
 181         struct radv_userdata_info descriptor_sets[MAX_SETS];
 182         struct radv_userdata_info shader_data[AC_UD_MAX_UD];
 183         uint32_t descriptor_sets_enabled;
 184 };
 185
 186 struct radv_vs_output_info {
 187         uint8_t vs_output_param_offset[VARYING_SLOT_MAX];
 188         uint8_t clip_dist_mask;
 189         uint8_t cull_dist_mask;
 190         uint8_t param_exports;
 191         bool writes_pointsize;
 192         bool writes_layer;
 193         bool writes_viewport_index;
 194         bool export_prim_id;
 195         unsigned pos_exports;
 196 };
 197
 198 struct radv_es_output_info {
 199        uint32_t esgs_itemsize;
 200 };
 201
 202 struct gfx9_gs_info {
 203         uint32_t vgt_gs_onchip_cntl;
 204         uint32_t vgt_gs_max_prims_per_subgroup;
 205         uint32_t vgt_esgs_ring_itemsize;
 206         uint32_t lds_size;
 207 };
 208
 209 struct gfx10_ngg_info {
 210         uint16_t ngg_emit_size; /* in dwords */
 211         uint32_t hw_max_esverts;
 212         uint32_t max_gsprims;
 213         uint32_t max_out_verts;
 214         uint32_t prim_amp_factor;
 215         uint32_t vgt_esgs_ring_itemsize;
 216         uint32_t esgs_ring_size;
 217         bool max_vert_out_per_gs_instance;
 218 };
 219
 220 struct radv_shader_info {
 221         bool loads_push_constants;
 222         bool loads_dynamic_offsets;
 223         uint8_t min_push_constant_used;
 224         uint8_t max_push_constant_used;
 225         bool has_only_32bit_push_constants;
 226         bool has_indirect_push_constants;
 227         uint8_t num_inline_push_consts;
 228         uint8_t base_inline_push_consts;
 229         uint32_t desc_set_used_mask;
 230         bool needs_multiview_view_index;
 231         bool uses_invocation_id;
 232         bool uses_prim_id;
 233         uint8_t wave_size;
 234         struct radv_userdata_locations user_sgprs_locs;
 235         unsigned num_user_sgprs;
 236         unsigned num_input_sgprs;
 237         unsigned num_input_vgprs;
 238         unsigned private_mem_vgprs;
 239         bool need_indirect_descriptor_sets;
 240         bool is_ngg;
 241         struct {
 242                 uint64_t ls_outputs_written;
 243                 uint8_t input_usage_mask[VERT_ATTRIB_MAX];
 244                 uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
 245                 bool has_vertex_buffers; /* needs vertex buffers and base/start */
 246                 bool needs_draw_id;
 247                 bool needs_instance_id;
 248                 struct radv_vs_output_info outinfo;
 249                 struct radv_es_output_info es_info;
 250                 bool as_es;
 251                 bool as_ls;
 252                 bool export_prim_id;
 253         } vs;
 254         struct {
 255                 uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
 256                 uint8_t num_stream_output_components[4];
 257                 uint8_t output_streams[VARYING_SLOT_VAR31 + 1];
 258                 uint8_t max_stream;
 259                 bool writes_memory;
 260                 unsigned gsvs_vertex_size;
 261                 unsigned max_gsvs_emit_size;
 262                 unsigned vertices_in;
 263                 unsigned vertices_out;
 264                 unsigned output_prim;
 265                 unsigned invocations;
 266                 unsigned es_type; /* GFX9: VS or TES */
 267         } gs;
 268         struct {
 269                 uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
 270                 struct radv_vs_output_info outinfo;
 271                 struct radv_es_output_info es_info;
 272                 bool as_es;
 273                 unsigned primitive_mode;
 274                 enum gl_tess_spacing spacing;
 275                 bool ccw;
 276                 bool point_mode;
 277                 bool export_prim_id;
 278         } tes;
 279         struct {
 280                 bool force_persample;
 281                 bool needs_sample_positions;
 282                 bool writes_memory;
 283                 bool writes_z;
 284                 bool writes_stencil;
 285                 bool writes_sample_mask;
 286                 bool has_pcoord;
 287                 bool prim_id_input;
 288                 bool layer_input;
 289                 uint8_t num_input_clips_culls;
 290                 uint32_t input_mask;
 291                 uint32_t flat_shaded_mask;
 292                 uint32_t float16_shaded_mask;
 293                 uint32_t num_interp;
 294                 bool can_discard;
 295                 bool early_fragment_test;
 296                 bool post_depth_coverage;
 297         } ps;
 298         struct {
 299                 bool uses_grid_size;
 300                 bool uses_block_id[3];
 301                 bool uses_thread_id[3];
 302                 bool uses_local_invocation_idx;
 303                 unsigned block_size[3];
 304         } cs;
 305         struct {
 306                 uint64_t outputs_written;
 307                 uint64_t patch_outputs_written;
 308                 unsigned tcs_vertices_out;
 309                 uint32_t num_patches;
 310                 uint32_t lds_size;
 311         } tcs;
 312
 313         struct radv_streamout_info so;
 314
 315         struct gfx9_gs_info gs_ring_info;
 316         struct gfx10_ngg_info ngg_info;
 317
 318         unsigned float_controls_mode;
 319 };
 320
 321 enum radv_shader_binary_type {
 322         RADV_BINARY_TYPE_LEGACY,
 323         RADV_BINARY_TYPE_RTLD
 324 };
 325
 326 struct radv_shader_binary {
 327         enum radv_shader_binary_type type;
 328         gl_shader_stage stage;
 329         bool is_gs_copy_shader;
 330
 331         struct radv_shader_info info;
 332
 333         /* Self-referential size so we avoid consistency issues. */
 334         uint32_t total_size;
 335 };
 336
 337 struct radv_shader_binary_legacy {
 338         struct radv_shader_binary base;
 339         struct ac_shader_config config;
 340         unsigned code_size;
 341         unsigned exec_size;
 342         unsigned ir_size;
 343         unsigned disasm_size;
 344
 345         /* data has size of code_size + ir_size + disasm_size + 2, where
 346          * the +2 is for 0 of the ir strings. */
 347         uint8_t data[0];
 348 };
 349
 350 struct radv_shader_binary_rtld {
 351         struct radv_shader_binary base;
 352         unsigned elf_size;
 353         unsigned llvm_ir_size;
 354         uint8_t data[0];
 355 };
 356
 357 struct radv_shader_variant {
 358         uint32_t ref_count;
 359
 360         struct radeon_winsys_bo *bo;
 361         uint64_t bo_offset;
 362         struct ac_shader_config config;
 363         uint32_t code_size;
 364         uint32_t exec_size;
 365         struct radv_shader_info info;
 366
 367         /* debug only */
 368         bool aco_used;
 369         char *spirv;
 370         uint32_t spirv_size;
 371         char *nir_string;
 372         char *disasm_string;
 373         char *ir_string;
 374
 375         struct list_head slab_list;
 376 };
 377
 378 struct radv_shader_slab {
 379         struct list_head slabs;
 380         struct list_head shaders;
 381         struct radeon_winsys_bo *bo;
 382         uint64_t size;
 383         char *ptr;
 384 };
 385
 386 void
 387 radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
 388                   bool allow_copies);
 389 bool
 390 radv_nir_lower_ycbcr_textures(nir_shader *shader,
 391                              const struct radv_pipeline_layout *layout);
 392
 393 nir_shader *
 394 radv_shader_compile_to_nir(struct radv_device *device,
 395                            struct radv_shader_module *module,
 396                            const char *entrypoint_name,
 397                            gl_shader_stage stage,
 398                            const VkSpecializationInfo *spec_info,
 399                            const VkPipelineCreateFlags flags,
 400                            const struct radv_pipeline_layout *layout,
 401                            bool use_aco);
 402
 403 void *
 404 radv_alloc_shader_memory(struct radv_device *device,
 405                           struct radv_shader_variant *shader);
 406
 407 void
 408 radv_destroy_shader_slabs(struct radv_device *device);
 409
 410 void
 411 radv_create_shaders(struct radv_pipeline *pipeline,
 412                     struct radv_device *device,
 413                     struct radv_pipeline_cache *cache,
 414                     const struct radv_pipeline_key *key,
 415                     const VkPipelineShaderStageCreateInfo **pStages,
 416                     const VkPipelineCreateFlags flags,
 417                     VkPipelineCreationFeedbackEXT *pipeline_feedback,
 418                     VkPipelineCreationFeedbackEXT **stage_feedbacks);
 419
 420 struct radv_shader_variant *
 421 radv_shader_variant_create(struct radv_device *device,
 422                            const struct radv_shader_binary *binary,
 423                            bool keep_shader_info);
 424 struct radv_shader_variant *
 425 radv_shader_variant_compile(struct radv_device *device,
 426                             struct radv_shader_module *module,
 427                             struct nir_shader *const *shaders,
 428                             int shader_count,
 429                             struct radv_pipeline_layout *layout,
 430                             const struct radv_shader_variant_key *key,
 431                             struct radv_shader_info *info,
 432                             bool keep_shader_info,
 433                             bool use_aco,
 434                             struct radv_shader_binary **binary_out);
 435
 436 struct radv_shader_variant *
 437 radv_create_gs_copy_shader(struct radv_device *device, struct nir_shader *nir,
 438                            struct radv_shader_info *info,
 439                            struct radv_shader_binary **binary_out,
 440                            bool multiview,  bool keep_shader_info);
 441
 442 void
 443 radv_shader_variant_destroy(struct radv_device *device,
 444                             struct radv_shader_variant *variant);
 445
 446
 447 unsigned
 448 radv_get_max_waves(struct radv_device *device,
 449                    struct radv_shader_variant *variant,
 450                    gl_shader_stage stage);
 451
 452 unsigned
 453 radv_get_max_workgroup_size(enum chip_class chip_class,
 454                             gl_shader_stage stage,
 455                             const unsigned *sizes);
 456
 457 const char *
 458 radv_get_shader_name(struct radv_shader_info *info,
 459                      gl_shader_stage stage);
 460
 461 void
 462 radv_shader_dump_stats(struct radv_device *device,
 463                        struct radv_shader_variant *variant,
 464                        gl_shader_stage stage,
 465                        FILE *file);
 466
 467 bool
 468 radv_can_dump_shader(struct radv_device *device,
 469                      struct radv_shader_module *module,
 470                      bool is_gs_copy_shader);
 471
 472 bool
 473 radv_can_dump_shader_stats(struct radv_device *device,
 474                            struct radv_shader_module *module);
 475
 476 unsigned
 477 shader_io_get_unique_index(gl_varying_slot slot);
 478
 479 void
 480 radv_lower_fs_io(nir_shader *nir);
 481
 482 #endif