src/amd/vulkan/radv_shader.h

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #ifndef RADV_SHADER_H
  29 #define RADV_SHADER_H
  30
  31 #include "radv_debug.h"
  32 #include "radv_private.h"
  33
  34 #include "nir/nir.h"
  35
  36 /* descriptor index into scratch ring offsets */
  37 #define RING_SCRATCH 0
  38 #define RING_ESGS_VS 1
  39 #define RING_ESGS_GS 2
  40 #define RING_GSVS_VS 3
  41 #define RING_GSVS_GS 4
  42 #define RING_HS_TESS_FACTOR 5
  43 #define RING_HS_TESS_OFFCHIP 6
  44 #define RING_PS_SAMPLE_POSITIONS 7
  45
  46 // Match MAX_SETS from radv_descriptor_set.h
  47 #define RADV_UD_MAX_SETS MAX_SETS
  48
  49 #define RADV_NUM_PHYSICAL_VGPRS 256
  50
  51 struct radv_shader_module {
  52         struct nir_shader *nir;
  53         unsigned char sha1[20];
  54         uint32_t size;
  55         char data[0];
  56 };
  57
  58 enum {
  59         RADV_ALPHA_ADJUST_NONE = 0,
  60         RADV_ALPHA_ADJUST_SNORM = 1,
  61         RADV_ALPHA_ADJUST_SINT = 2,
  62         RADV_ALPHA_ADJUST_SSCALED = 3,
  63 };
  64
  65 struct radv_vs_out_key {
  66         uint32_t as_es:1;
  67         uint32_t as_ls:1;
  68         uint32_t as_ngg:1;
  69         uint32_t export_prim_id:1;
  70         uint32_t export_layer_id:1;
  71         uint32_t export_clip_dists:1;
  72 };
  73
  74 struct radv_vs_variant_key {
  75         struct radv_vs_out_key out;
  76
  77         uint32_t instance_rate_inputs;
  78         uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
  79         uint8_t vertex_attribute_formats[MAX_VERTEX_ATTRIBS];
  80         uint32_t vertex_attribute_bindings[MAX_VERTEX_ATTRIBS];
  81         uint32_t vertex_attribute_offsets[MAX_VERTEX_ATTRIBS];
  82         uint32_t vertex_attribute_strides[MAX_VERTEX_ATTRIBS];
  83
  84         /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
  85          * so we may need to fix it up. */
  86         uint64_t alpha_adjust;
  87
  88         /* For some formats the channels have to be shuffled. */
  89         uint32_t post_shuffle;
  90 };
  91
  92 struct radv_tes_variant_key {
  93         struct radv_vs_out_key out;
  94
  95         uint8_t num_patches;
  96         uint8_t tcs_num_outputs;
  97 };
  98
  99 struct radv_tcs_variant_key {
 100         struct radv_vs_variant_key vs_key;
 101         unsigned primitive_mode;
 102         unsigned input_vertices;
 103         unsigned num_inputs;
 104         uint32_t tes_reads_tess_factors:1;
 105 };
 106
 107 struct radv_fs_variant_key {
 108         uint32_t col_format;
 109         uint8_t log2_ps_iter_samples;
 110         uint8_t num_samples;
 111         uint32_t is_int8;
 112         uint32_t is_int10;
 113 };
 114
 115 struct radv_shader_variant_key {
 116         union {
 117                 struct radv_vs_variant_key vs;
 118                 struct radv_fs_variant_key fs;
 119                 struct radv_tes_variant_key tes;
 120                 struct radv_tcs_variant_key tcs;
 121         };
 122         bool has_multiview_view_index;
 123 };
 124
 125 struct radv_nir_compiler_options {
 126         struct radv_pipeline_layout *layout;
 127         struct radv_shader_variant_key key;
 128         bool unsafe_math;
 129         bool supports_spill;
 130         bool clamp_shadow_reference;
 131         bool dump_shader;
 132         bool dump_preoptir;
 133         bool record_llvm_ir;
 134         bool check_ir;
 135         enum radeon_family family;
 136         enum chip_class chip_class;
 137         uint32_t tess_offchip_block_dw_size;
 138         uint32_t address32_hi;
 139 };
 140
 141 enum radv_ud_index {
 142         AC_UD_SCRATCH_RING_OFFSETS = 0,
 143         AC_UD_PUSH_CONSTANTS = 1,
 144         AC_UD_INLINE_PUSH_CONSTANTS = 2,
 145         AC_UD_INDIRECT_DESCRIPTOR_SETS = 3,
 146         AC_UD_VIEW_INDEX = 4,
 147         AC_UD_STREAMOUT_BUFFERS = 5,
 148         AC_UD_SHADER_START = 6,
 149         AC_UD_VS_VERTEX_BUFFERS = AC_UD_SHADER_START,
 150         AC_UD_VS_BASE_VERTEX_START_INSTANCE,
 151         AC_UD_VS_MAX_UD,
 152         AC_UD_PS_MAX_UD,
 153         AC_UD_CS_GRID_SIZE = AC_UD_SHADER_START,
 154         AC_UD_CS_MAX_UD,
 155         AC_UD_GS_MAX_UD,
 156         AC_UD_TCS_MAX_UD,
 157         AC_UD_TES_MAX_UD,
 158         AC_UD_MAX_UD = AC_UD_TCS_MAX_UD,
 159 };
 160
 161 struct radv_stream_output {
 162         uint8_t location;
 163         uint8_t buffer;
 164         uint16_t offset;
 165         uint8_t component_mask;
 166         uint8_t stream;
 167 };
 168
 169 struct radv_streamout_info {
 170         uint16_t num_outputs;
 171         struct radv_stream_output outputs[MAX_SO_OUTPUTS];
 172         uint16_t strides[MAX_SO_BUFFERS];
 173         uint32_t enabled_stream_buffers_mask;
 174 };
 175
 176 struct radv_shader_info {
 177         bool loads_push_constants;
 178         bool loads_dynamic_offsets;
 179         uint8_t min_push_constant_used;
 180         uint8_t max_push_constant_used;
 181         bool has_only_32bit_push_constants;
 182         bool has_indirect_push_constants;
 183         uint8_t num_inline_push_consts;
 184         uint8_t base_inline_push_consts;
 185         uint32_t desc_set_used_mask;
 186         bool needs_multiview_view_index;
 187         bool uses_invocation_id;
 188         bool uses_prim_id;
 189         struct {
 190                 uint64_t ls_outputs_written;
 191                 uint8_t input_usage_mask[VERT_ATTRIB_MAX];
 192                 uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
 193                 bool has_vertex_buffers; /* needs vertex buffers and base/start */
 194                 bool needs_draw_id;
 195                 bool needs_instance_id;
 196         } vs;
 197         struct {
 198                 uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
 199                 uint8_t num_stream_output_components[4];
 200                 uint8_t output_streams[VARYING_SLOT_VAR31 + 1];
 201                 uint8_t max_stream;
 202         } gs;
 203         struct {
 204                 uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
 205         } tes;
 206         struct {
 207                 bool force_persample;
 208                 bool needs_sample_positions;
 209                 bool writes_memory;
 210                 bool writes_z;
 211                 bool writes_stencil;
 212                 bool writes_sample_mask;
 213                 bool has_pcoord;
 214                 bool prim_id_input;
 215                 bool layer_input;
 216                 uint8_t num_input_clips_culls;
 217         } ps;
 218         struct {
 219                 bool uses_grid_size;
 220                 bool uses_block_id[3];
 221                 bool uses_thread_id[3];
 222                 bool uses_local_invocation_idx;
 223         } cs;
 224         struct {
 225                 uint64_t outputs_written;
 226                 uint64_t patch_outputs_written;
 227         } tcs;
 228
 229         struct radv_streamout_info so;
 230 };
 231
 232 struct radv_userdata_info {
 233         int8_t sgpr_idx;
 234         uint8_t num_sgprs;
 235 };
 236
 237 struct radv_userdata_locations {
 238         struct radv_userdata_info descriptor_sets[RADV_UD_MAX_SETS];
 239         struct radv_userdata_info shader_data[AC_UD_MAX_UD];
 240         uint32_t descriptor_sets_enabled;
 241 };
 242
 243 struct radv_vs_output_info {
 244         uint8_t vs_output_param_offset[VARYING_SLOT_MAX];
 245         uint8_t clip_dist_mask;
 246         uint8_t cull_dist_mask;
 247         uint8_t param_exports;
 248         bool writes_pointsize;
 249         bool writes_layer;
 250         bool writes_viewport_index;
 251         bool export_prim_id;
 252         unsigned pos_exports;
 253 };
 254
 255 struct radv_es_output_info {
 256         uint32_t esgs_itemsize;
 257 };
 258
 259 struct radv_shader_variant_info {
 260         struct radv_userdata_locations user_sgprs_locs;
 261         struct radv_shader_info info;
 262         unsigned num_user_sgprs;
 263         unsigned num_input_sgprs;
 264         unsigned num_input_vgprs;
 265         unsigned private_mem_vgprs;
 266         bool need_indirect_descriptor_sets;
 267         bool is_ngg;
 268         struct {
 269                 struct {
 270                         struct radv_vs_output_info outinfo;
 271                         struct radv_es_output_info es_info;
 272                         bool as_es;
 273                         bool as_ls;
 274                         bool export_prim_id;
 275                 } vs;
 276                 struct {
 277                         unsigned num_interp;
 278                         uint32_t input_mask;
 279                         uint32_t flat_shaded_mask;
 280                         uint32_t float16_shaded_mask;
 281                         bool can_discard;
 282                         bool early_fragment_test;
 283                 } fs;
 284                 struct {
 285                         unsigned block_size[3];
 286                 } cs;
 287                 struct {
 288                         unsigned vertices_in;
 289                         unsigned vertices_out;
 290                         unsigned output_prim;
 291                         unsigned invocations;
 292                         unsigned gsvs_vertex_size;
 293                         unsigned max_gsvs_emit_size;
 294                         unsigned es_type; /* GFX9: VS or TES */
 295                 } gs;
 296                 struct {
 297                         unsigned tcs_vertices_out;
 298                         uint32_t num_patches;
 299                         uint32_t lds_size;
 300                 } tcs;
 301                 struct {
 302                         struct radv_vs_output_info outinfo;
 303                         struct radv_es_output_info es_info;
 304                         bool as_es;
 305                         unsigned primitive_mode;
 306                         enum gl_tess_spacing spacing;
 307                         bool ccw;
 308                         bool point_mode;
 309                         bool export_prim_id;
 310                 } tes;
 311         };
 312 };
 313
 314 enum radv_shader_binary_type {
 315         RADV_BINARY_TYPE_LEGACY,
 316         RADV_BINARY_TYPE_RTLD
 317 };
 318
 319 struct radv_shader_binary {
 320         enum radv_shader_binary_type type;
 321         gl_shader_stage stage;
 322         bool is_gs_copy_shader;
 323
 324         struct radv_shader_variant_info variant_info;
 325
 326         /* Self-referential size so we avoid consistency issues. */
 327         uint32_t total_size;
 328 };
 329
 330 struct radv_shader_binary_legacy {
 331         struct radv_shader_binary base;
 332         struct ac_shader_config config;
 333         unsigned code_size;
 334         unsigned llvm_ir_size;
 335         unsigned disasm_size;
 336
 337         /* data has size of code_size + llvm_ir_size + disasm_size + 2, where
 338          * the +2 is for 0 of the ir strings. */
 339         uint8_t data[0];
 340 };
 341
 342 struct radv_shader_binary_rtld {
 343         struct radv_shader_binary base;
 344         unsigned elf_size;
 345         unsigned llvm_ir_size;
 346         uint8_t data[0];
 347 };
 348
 349 struct radv_shader_variant {
 350         uint32_t ref_count;
 351
 352         struct radeon_winsys_bo *bo;
 353         uint64_t bo_offset;
 354         struct ac_shader_config config;
 355         uint32_t code_size;
 356         struct radv_shader_variant_info info;
 357
 358         /* debug only */
 359         uint32_t *spirv;
 360         uint32_t spirv_size;
 361         struct nir_shader *nir;
 362         char *disasm_string;
 363         char *llvm_ir_string;
 364
 365         struct list_head slab_list;
 366 };
 367
 368 struct radv_shader_slab {
 369         struct list_head slabs;
 370         struct list_head shaders;
 371         struct radeon_winsys_bo *bo;
 372         uint64_t size;
 373         char *ptr;
 374 };
 375
 376 void
 377 radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
 378                   bool allow_copies);
 379 bool
 380 radv_nir_lower_ycbcr_textures(nir_shader *shader,
 381                              const struct radv_pipeline_layout *layout);
 382
 383 nir_shader *
 384 radv_shader_compile_to_nir(struct radv_device *device,
 385                            struct radv_shader_module *module,
 386                            const char *entrypoint_name,
 387                            gl_shader_stage stage,
 388                            const VkSpecializationInfo *spec_info,
 389                            const VkPipelineCreateFlags flags,
 390                            const struct radv_pipeline_layout *layout);
 391
 392 void *
 393 radv_alloc_shader_memory(struct radv_device *device,
 394                           struct radv_shader_variant *shader);
 395
 396 void
 397 radv_destroy_shader_slabs(struct radv_device *device);
 398
 399 struct radv_shader_variant *
 400 radv_shader_variant_create(struct radv_device *device,
 401                            const struct radv_shader_binary *binary);
 402 struct radv_shader_variant *
 403 radv_shader_variant_compile(struct radv_device *device,
 404                             struct radv_shader_module *module,
 405                             struct nir_shader *const *shaders,
 406                             int shader_count,
 407                             struct radv_pipeline_layout *layout,
 408                             const struct radv_shader_variant_key *key,
 409                             struct radv_shader_binary **binary_out);
 410
 411 struct radv_shader_variant *
 412 radv_create_gs_copy_shader(struct radv_device *device, struct nir_shader *nir,
 413                            struct radv_shader_binary **binary_out,
 414                            bool multiview);
 415
 416 void
 417 radv_shader_variant_destroy(struct radv_device *device,
 418                             struct radv_shader_variant *variant);
 419
 420 const char *
 421 radv_get_shader_name(struct radv_shader_variant *var, gl_shader_stage stage);
 422
 423 void
 424 radv_shader_dump_stats(struct radv_device *device,
 425                        struct radv_shader_variant *variant,
 426                        gl_shader_stage stage,
 427                        FILE *file);
 428
 429 static inline bool
 430 radv_can_dump_shader(struct radv_device *device,
 431                      struct radv_shader_module *module,
 432                      bool is_gs_copy_shader)
 433 {
 434         if (!(device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS))
 435                 return false;
 436
 437         /* Only dump non-meta shaders, useful for debugging purposes. */
 438         return (module && !module->nir) || is_gs_copy_shader;
 439 }
 440
 441 static inline bool
 442 radv_can_dump_shader_stats(struct radv_device *device,
 443                            struct radv_shader_module *module)
 444 {
 445         /* Only dump non-meta shader stats. */
 446         return device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS &&
 447                module && !module->nir;
 448 }
 449
 450 static inline unsigned shader_io_get_unique_index(gl_varying_slot slot)
 451 {
 452         /* handle patch indices separate */
 453         if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
 454                 return 0;
 455         if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
 456                 return 1;
 457         if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
 458                 return 2 + (slot - VARYING_SLOT_PATCH0);
 459         if (slot == VARYING_SLOT_POS)
 460                 return 0;
 461         if (slot == VARYING_SLOT_PSIZ)
 462                 return 1;
 463         if (slot == VARYING_SLOT_CLIP_DIST0)
 464                 return 2;
 465         if (slot == VARYING_SLOT_CLIP_DIST1)
 466                 return 3;
 467         /* 3 is reserved for clip dist as well */
 468         if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
 469                 return 4 + (slot - VARYING_SLOT_VAR0);
 470         unreachable("illegal slot in get unique index\n");
 471 }
 472
 473 #endif