src/amd/vulkan/radv_shader_info.c

   1 /*
   2  * Copyright © 2017 Red Hat
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23 #include "radv_private.h"
  24 #include "radv_shader.h"
  25 #include "nir/nir.h"
  26
  27 static void mark_sampler_desc(const nir_variable *var,
  28                               struct radv_shader_info *info)
  29 {
  30         info->desc_set_used_mask |= (1 << var->data.descriptor_set);
  31 }
  32
  33 static void mark_ls_output(struct radv_shader_info *info,
  34                            uint32_t param, int num_slots)
  35 {
  36         uint64_t mask = (1ull << num_slots) - 1ull;
  37         info->vs.ls_outputs_written |= (mask << param);
  38 }
  39
  40 static void mark_tess_output(struct radv_shader_info *info,
  41                              bool is_patch, uint32_t param, int num_slots)
  42 {
  43         uint64_t mask = (1ull << num_slots) - 1ull;
  44         if (is_patch)
  45                 info->tcs.patch_outputs_written |= (mask << param);
  46         else
  47                 info->tcs.outputs_written |= (mask << param);
  48 }
  49
  50 static void get_deref_offset(nir_deref_var *deref, unsigned *const_out)
  51 {
  52         nir_deref *tail = &deref->deref;
  53         unsigned const_offset = 0;
  54
  55         if (deref->var->data.compact) {
  56                 assert(tail->child->deref_type == nir_deref_type_array);
  57                 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
  58
  59                 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
  60                 /* We always lower indirect dereferences for "compact" array vars. */
  61                 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
  62
  63                 *const_out = deref_array->base_offset;
  64                 return;
  65         }
  66
  67         while (tail->child != NULL) {
  68                 const struct glsl_type *parent_type = tail->type;
  69                 tail = tail->child;
  70
  71                 if (tail->deref_type == nir_deref_type_array) {
  72                         nir_deref_array *deref_array = nir_deref_as_array(tail);
  73                         unsigned size = glsl_count_attribute_slots(tail->type, false);
  74
  75                         const_offset += size * deref_array->base_offset;
  76                 } else if (tail->deref_type == nir_deref_type_struct) {
  77                         nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
  78
  79                         for (unsigned i = 0; i < deref_struct->index; i++) {
  80                                 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
  81                                 const_offset += glsl_count_attribute_slots(ft, false);
  82                         }
  83                 } else
  84                         unreachable("unsupported deref type");
  85         }
  86
  87         *const_out = const_offset;
  88 }
  89
  90 static void
  91 gather_intrinsic_info(const nir_shader *nir, const nir_intrinsic_instr *instr,
  92                       struct radv_shader_info *info)
  93 {
  94         switch (instr->intrinsic) {
  95         case nir_intrinsic_interp_var_at_sample:
  96                 info->ps.needs_sample_positions = true;
  97                 break;
  98         case nir_intrinsic_load_draw_id:
  99                 info->vs.needs_draw_id = true;
 100                 break;
 101         case nir_intrinsic_load_instance_id:
 102                 info->vs.needs_instance_id = true;
 103                 break;
 104         case nir_intrinsic_load_num_work_groups:
 105                 info->cs.uses_grid_size = true;
 106                 break;
 107         case nir_intrinsic_load_local_invocation_id:
 108         case nir_intrinsic_load_work_group_id: {
 109                 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
 110                 while (mask) {
 111                         unsigned i = u_bit_scan(&mask);
 112
 113                         if (instr->intrinsic == nir_intrinsic_load_work_group_id)
 114                                 info->cs.uses_block_id[i] = true;
 115                         else
 116                                 info->cs.uses_thread_id[i] = true;
 117                 }
 118                 break;
 119         }
 120         case nir_intrinsic_load_local_invocation_index:
 121         case nir_intrinsic_load_subgroup_id:
 122         case nir_intrinsic_load_num_subgroups:
 123                 info->cs.uses_local_invocation_idx = true;
 124                 break;
 125         case nir_intrinsic_load_sample_id:
 126                 info->ps.force_persample = true;
 127                 break;
 128         case nir_intrinsic_load_sample_pos:
 129                 info->ps.force_persample = true;
 130                 break;
 131         case nir_intrinsic_load_view_index:
 132                 info->needs_multiview_view_index = true;
 133                 if (nir->info.stage == MESA_SHADER_FRAGMENT)
 134                         info->ps.layer_input = true;
 135                 break;
 136         case nir_intrinsic_load_invocation_id:
 137                 info->uses_invocation_id = true;
 138                 break;
 139         case nir_intrinsic_load_primitive_id:
 140                 info->uses_prim_id = true;
 141                 break;
 142         case nir_intrinsic_load_push_constant:
 143                 info->loads_push_constants = true;
 144                 break;
 145         case nir_intrinsic_vulkan_resource_index:
 146                 info->desc_set_used_mask |= (1 << nir_intrinsic_desc_set(instr));
 147                 break;
 148         case nir_intrinsic_image_var_load:
 149         case nir_intrinsic_image_var_store:
 150         case nir_intrinsic_image_var_atomic_add:
 151         case nir_intrinsic_image_var_atomic_min:
 152         case nir_intrinsic_image_var_atomic_max:
 153         case nir_intrinsic_image_var_atomic_and:
 154         case nir_intrinsic_image_var_atomic_or:
 155         case nir_intrinsic_image_var_atomic_xor:
 156         case nir_intrinsic_image_var_atomic_exchange:
 157         case nir_intrinsic_image_var_atomic_comp_swap:
 158         case nir_intrinsic_image_var_size: {
 159                 const struct glsl_type *type = instr->variables[0]->var->type;
 160                 if(instr->variables[0]->deref.child)
 161                         type = instr->variables[0]->deref.child->type;
 162
 163                 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
 164                 if (dim == GLSL_SAMPLER_DIM_SUBPASS ||
 165                     dim == GLSL_SAMPLER_DIM_SUBPASS_MS) {
 166                         info->ps.layer_input = true;
 167                         info->ps.uses_input_attachments = true;
 168                 }
 169                 mark_sampler_desc(instr->variables[0]->var, info);
 170
 171                 if (nir_intrinsic_image_var_store ||
 172                     nir_intrinsic_image_var_atomic_add ||
 173                     nir_intrinsic_image_var_atomic_min ||
 174                     nir_intrinsic_image_var_atomic_max ||
 175                     nir_intrinsic_image_var_atomic_and ||
 176                     nir_intrinsic_image_var_atomic_or ||
 177                     nir_intrinsic_image_var_atomic_xor ||
 178                     nir_intrinsic_image_var_atomic_exchange ||
 179                     nir_intrinsic_image_var_atomic_comp_swap) {
 180                         if (nir->info.stage == MESA_SHADER_FRAGMENT)
 181                                 info->ps.writes_memory = true;
 182                 }
 183                 break;
 184         }
 185         case nir_intrinsic_store_ssbo:
 186         case nir_intrinsic_ssbo_atomic_add:
 187         case nir_intrinsic_ssbo_atomic_imin:
 188         case nir_intrinsic_ssbo_atomic_umin:
 189         case nir_intrinsic_ssbo_atomic_imax:
 190         case nir_intrinsic_ssbo_atomic_umax:
 191         case nir_intrinsic_ssbo_atomic_and:
 192         case nir_intrinsic_ssbo_atomic_or:
 193         case nir_intrinsic_ssbo_atomic_xor:
 194         case nir_intrinsic_ssbo_atomic_exchange:
 195         case nir_intrinsic_ssbo_atomic_comp_swap:
 196                 if (nir->info.stage == MESA_SHADER_FRAGMENT)
 197                         info->ps.writes_memory = true;
 198                 break;
 199         case nir_intrinsic_load_var:
 200                 if (nir->info.stage == MESA_SHADER_VERTEX) {
 201                         nir_deref_var *dvar = instr->variables[0];
 202                         nir_variable *var = dvar->var;
 203
 204                         if (var->data.mode == nir_var_shader_in) {
 205                                 unsigned idx = var->data.location;
 206                                 uint8_t mask =
 207                                         nir_ssa_def_components_read(&instr->dest.ssa) << var->data.location_frac;
 208                                 info->vs.input_usage_mask[idx] |= mask;
 209                         }
 210                 }
 211                 break;
 212         case nir_intrinsic_store_var: {
 213                 nir_deref_var *dvar = instr->variables[0];
 214                 nir_variable *var = dvar->var;
 215
 216                 if (var->data.mode == nir_var_shader_out) {
 217                         unsigned attrib_count = glsl_count_attribute_slots(var->type, false);
 218                         unsigned idx = var->data.location;
 219                         unsigned comp = var->data.location_frac;
 220                         unsigned const_offset = 0;
 221
 222                         get_deref_offset(dvar, &const_offset);
 223
 224                         if (nir->info.stage == MESA_SHADER_VERTEX) {
 225                                 for (unsigned i = 0; i < attrib_count; i++) {
 226                                         info->vs.output_usage_mask[idx + i + const_offset] |=
 227                                                 instr->const_index[0] << comp;
 228                                 }
 229                         } else if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
 230                                 for (unsigned i = 0; i < attrib_count; i++) {
 231                                         info->tes.output_usage_mask[idx + i + const_offset] |=
 232                                                 instr->const_index[0] << comp;
 233                                 }
 234                         } else if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
 235                                 unsigned param = shader_io_get_unique_index(idx);
 236                                 const struct glsl_type *type = var->type;
 237                                 if (!var->data.patch)
 238                                         type = glsl_get_array_element(var->type);
 239                                 unsigned slots =
 240                                         var->data.compact ? DIV_ROUND_UP(glsl_get_length(type), 4)
 241                                         : glsl_count_attribute_slots(type, false);
 242                                 if (idx == VARYING_SLOT_CLIP_DIST0)
 243                                         slots = (nir->info.clip_distance_array_size + nir->info.cull_distance_array_size > 4) ? 2 : 1;
 244                                 mark_tess_output(info, var->data.patch, param, slots);
 245                         }
 246                 }
 247                 break;
 248         }
 249         default:
 250                 break;
 251         }
 252 }
 253
 254 static void
 255 gather_tex_info(const nir_shader *nir, const nir_tex_instr *instr,
 256                 struct radv_shader_info *info)
 257 {
 258         if (instr->sampler)
 259                 mark_sampler_desc(instr->sampler->var, info);
 260         if (instr->texture)
 261                 mark_sampler_desc(instr->texture->var, info);
 262 }
 263
 264 static void
 265 gather_info_block(const nir_shader *nir, const nir_block *block,
 266                   struct radv_shader_info *info)
 267 {
 268         nir_foreach_instr(instr, block) {
 269                 switch (instr->type) {
 270                 case nir_instr_type_intrinsic:
 271                         gather_intrinsic_info(nir, nir_instr_as_intrinsic(instr), info);
 272                         break;
 273                 case nir_instr_type_tex:
 274                         gather_tex_info(nir, nir_instr_as_tex(instr), info);
 275                         break;
 276                 default:
 277                         break;
 278                 }
 279         }
 280 }
 281
 282 static void
 283 gather_info_input_decl_vs(const nir_shader *nir, const nir_variable *var,
 284                           struct radv_shader_info *info)
 285 {
 286         int idx = var->data.location;
 287
 288         if (idx >= VERT_ATTRIB_GENERIC0 && idx <= VERT_ATTRIB_GENERIC15)
 289                 info->vs.has_vertex_buffers = true;
 290 }
 291
 292 static void
 293 gather_info_input_decl_ps(const nir_shader *nir, const nir_variable *var,
 294                           struct radv_shader_info *info)
 295 {
 296         const struct glsl_type *type = glsl_without_array(var->type);
 297         int idx = var->data.location;
 298
 299         switch (idx) {
 300         case VARYING_SLOT_PNTC:
 301                 info->ps.has_pcoord = true;
 302                 break;
 303         case VARYING_SLOT_PRIMITIVE_ID:
 304                 info->ps.prim_id_input = true;
 305                 break;
 306         case VARYING_SLOT_LAYER:
 307                 info->ps.layer_input = true;
 308                 break;
 309         default:
 310                 break;
 311         }
 312
 313         if (glsl_get_base_type(type) == GLSL_TYPE_FLOAT) {
 314                 if (var->data.sample)
 315                         info->ps.force_persample = true;
 316         }
 317 }
 318
 319 static void
 320 gather_info_input_decl(const nir_shader *nir, const nir_variable *var,
 321                        struct radv_shader_info *info)
 322 {
 323         switch (nir->info.stage) {
 324         case MESA_SHADER_VERTEX:
 325                 gather_info_input_decl_vs(nir, var, info);
 326                 break;
 327         case MESA_SHADER_FRAGMENT:
 328                 gather_info_input_decl_ps(nir, var, info);
 329                 break;
 330         default:
 331                 break;
 332         }
 333 }
 334
 335 static void
 336 gather_info_output_decl_ls(const nir_shader *nir, const nir_variable *var,
 337                            struct radv_shader_info *info)
 338 {
 339         int idx = var->data.location;
 340         unsigned param = shader_io_get_unique_index(idx);
 341         int num_slots = glsl_count_attribute_slots(var->type, false);
 342         if (idx == VARYING_SLOT_CLIP_DIST0)
 343                 num_slots = (nir->info.clip_distance_array_size + nir->info.cull_distance_array_size > 4) ? 2 : 1;
 344         mark_ls_output(info, param, num_slots);
 345 }
 346
 347 static void
 348 gather_info_output_decl_ps(const nir_shader *nir, const nir_variable *var,
 349                            struct radv_shader_info *info)
 350 {
 351         int idx = var->data.location;
 352
 353         switch (idx) {
 354         case FRAG_RESULT_DEPTH:
 355                 info->ps.writes_z = true;
 356                 break;
 357         case FRAG_RESULT_STENCIL:
 358                 info->ps.writes_stencil = true;
 359                 break;
 360         case FRAG_RESULT_SAMPLE_MASK:
 361                 info->ps.writes_sample_mask = true;
 362                 break;
 363         default:
 364                 break;
 365         }
 366 }
 367
 368 static void
 369 gather_info_output_decl(const nir_shader *nir, const nir_variable *var,
 370                         struct radv_shader_info *info,
 371                         const struct radv_nir_compiler_options *options)
 372 {
 373         switch (nir->info.stage) {
 374         case MESA_SHADER_FRAGMENT:
 375                 gather_info_output_decl_ps(nir, var, info);
 376                 break;
 377         case MESA_SHADER_VERTEX:
 378                 if (options->key.vs.as_ls)
 379                         gather_info_output_decl_ls(nir, var, info);
 380                 break;
 381         default:
 382                 break;
 383         }
 384 }
 385
 386 void
 387 radv_nir_shader_info_pass(const struct nir_shader *nir,
 388                           const struct radv_nir_compiler_options *options,
 389                           struct radv_shader_info *info)
 390 {
 391         struct nir_function *func =
 392                 (struct nir_function *)exec_list_get_head_const(&nir->functions);
 393
 394         if (options->layout->dynamic_offset_count)
 395                 info->loads_push_constants = true;
 396
 397         nir_foreach_variable(variable, &nir->inputs)
 398                 gather_info_input_decl(nir, variable, info);
 399
 400         nir_foreach_block(block, func->impl) {
 401                 gather_info_block(nir, block, info);
 402         }
 403
 404         nir_foreach_variable(variable, &nir->outputs)
 405                 gather_info_output_decl(nir, variable, info, options);
 406 }