src/amd/vulkan/radv_shader_info.c

   1 /*
   2  * Copyright © 2017 Red Hat
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23 #include "radv_private.h"
  24 #include "radv_shader.h"
  25 #include "nir/nir.h"
  26 #include "nir/nir_deref.h"
  27 #include "nir/nir_xfb_info.h"
  28
  29 static void mark_sampler_desc(const nir_variable *var,
  30                               struct radv_shader_info *info)
  31 {
  32         info->desc_set_used_mask |= (1 << var->data.descriptor_set);
  33 }
  34
  35 static void mark_ls_output(struct radv_shader_info *info,
  36                            uint32_t param, int num_slots)
  37 {
  38         uint64_t mask = (1ull << num_slots) - 1ull;
  39         info->vs.ls_outputs_written |= (mask << param);
  40 }
  41
  42 static void mark_tess_output(struct radv_shader_info *info,
  43                              bool is_patch, uint32_t param, int num_slots)
  44 {
  45         uint64_t mask = (1ull << num_slots) - 1ull;
  46         if (is_patch)
  47                 info->tcs.patch_outputs_written |= (mask << param);
  48         else
  49                 info->tcs.outputs_written |= (mask << param);
  50 }
  51
  52 static void
  53 get_deref_offset(nir_deref_instr *instr,
  54                  unsigned *const_out)
  55 {
  56         nir_variable *var = nir_deref_instr_get_variable(instr);
  57         nir_deref_path path;
  58         unsigned idx_lvl = 1;
  59
  60         if (var->data.compact) {
  61                 assert(instr->deref_type == nir_deref_type_array);
  62                 nir_const_value *v = nir_src_as_const_value(instr->arr.index);
  63                 assert(v);
  64                 *const_out = v->u32[0];
  65                 return;
  66         }
  67
  68         nir_deref_path_init(&path, instr, NULL);
  69
  70         uint32_t const_offset = 0;
  71
  72         for (; path.path[idx_lvl]; ++idx_lvl) {
  73                 const struct glsl_type *parent_type = path.path[idx_lvl - 1]->type;
  74                 if (path.path[idx_lvl]->deref_type == nir_deref_type_struct) {
  75                         unsigned index = path.path[idx_lvl]->strct.index;
  76
  77                         for (unsigned i = 0; i < index; i++) {
  78                                 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
  79                                 const_offset += glsl_count_attribute_slots(ft, false);
  80                         }
  81                 } else if(path.path[idx_lvl]->deref_type == nir_deref_type_array) {
  82                         unsigned size = glsl_count_attribute_slots(path.path[idx_lvl]->type, false);
  83                         nir_const_value *v = nir_src_as_const_value(path.path[idx_lvl]->arr.index);
  84                         if (v)
  85                                 const_offset += v->u32[0] * size;
  86                 } else
  87                         unreachable("Uhandled deref type in get_deref_instr_offset");
  88         }
  89
  90         *const_out = const_offset;
  91
  92         nir_deref_path_finish(&path);
  93 }
  94
  95 static void
  96 gather_intrinsic_load_deref_info(const nir_shader *nir,
  97                                const nir_intrinsic_instr *instr,
  98                                struct radv_shader_info *info)
  99 {
 100         switch (nir->info.stage) {
 101         case MESA_SHADER_VERTEX: {
 102                 nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
 103
 104                 if (var->data.mode == nir_var_shader_in) {
 105                         unsigned idx = var->data.location;
 106                         uint8_t mask = nir_ssa_def_components_read(&instr->dest.ssa);
 107
 108                         info->vs.input_usage_mask[idx] |=
 109                                 mask << var->data.location_frac;
 110                 }
 111                 break;
 112         }
 113         default:
 114                 break;
 115         }
 116 }
 117
 118 static void
 119 set_output_usage_mask(const nir_shader *nir, const nir_intrinsic_instr *instr,
 120                       uint8_t *output_usage_mask)
 121 {
 122         nir_deref_instr *deref_instr =
 123                 nir_instr_as_deref(instr->src[0].ssa->parent_instr);
 124         nir_variable *var = nir_deref_instr_get_variable(deref_instr);
 125         unsigned attrib_count = glsl_count_attribute_slots(var->type, false);
 126         unsigned idx = var->data.location;
 127         unsigned comp = var->data.location_frac;
 128         unsigned const_offset = 0;
 129
 130         get_deref_offset(deref_instr, &const_offset);
 131
 132         if (idx == VARYING_SLOT_CLIP_DIST0) {
 133                 /* Special case for clip/cull distances because there are
 134                  * combined into a single array that contains both.
 135                  */
 136                 output_usage_mask[idx] |= 1 << const_offset;
 137                 return;
 138         }
 139
 140         for (unsigned i = 0; i < attrib_count; i++) {
 141                 output_usage_mask[idx + i + const_offset] |=
 142                         instr->const_index[0] << comp;
 143         }
 144 }
 145
 146 static void
 147 gather_intrinsic_store_deref_info(const nir_shader *nir,
 148                                 const nir_intrinsic_instr *instr,
 149                                 struct radv_shader_info *info)
 150 {
 151         nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
 152
 153         if (var->data.mode == nir_var_shader_out) {
 154                 unsigned idx = var->data.location;
 155
 156                 switch (nir->info.stage) {
 157                 case MESA_SHADER_VERTEX:
 158                         set_output_usage_mask(nir, instr,
 159                                               info->vs.output_usage_mask);
 160                         break;
 161                 case MESA_SHADER_GEOMETRY:
 162                         set_output_usage_mask(nir, instr,
 163                                               info->gs.output_usage_mask);
 164                         break;
 165                 case MESA_SHADER_TESS_EVAL:
 166                         set_output_usage_mask(nir, instr,
 167                                               info->tes.output_usage_mask);
 168                         break;
 169                 case MESA_SHADER_TESS_CTRL: {
 170                         unsigned param = shader_io_get_unique_index(idx);
 171                         const struct glsl_type *type = var->type;
 172
 173                         if (!var->data.patch)
 174                                 type = glsl_get_array_element(var->type);
 175
 176                         unsigned slots =
 177                                 var->data.compact ? DIV_ROUND_UP(glsl_get_length(type), 4)
 178                                                   : glsl_count_attribute_slots(type, false);
 179
 180                         if (idx == VARYING_SLOT_CLIP_DIST0)
 181                                 slots = (nir->info.clip_distance_array_size +
 182                                          nir->info.cull_distance_array_size > 4) ? 2 : 1;
 183
 184                         mark_tess_output(info, var->data.patch, param, slots);
 185                         break;
 186                 }
 187                 default:
 188                         break;
 189                 }
 190         }
 191 }
 192
 193 static void
 194 gather_intrinsic_info(const nir_shader *nir, const nir_intrinsic_instr *instr,
 195                       struct radv_shader_info *info)
 196 {
 197         switch (instr->intrinsic) {
 198         case nir_intrinsic_interp_deref_at_sample:
 199                 info->ps.needs_sample_positions = true;
 200                 break;
 201         case nir_intrinsic_load_draw_id:
 202                 info->vs.needs_draw_id = true;
 203                 break;
 204         case nir_intrinsic_load_instance_id:
 205                 info->vs.needs_instance_id = true;
 206                 break;
 207         case nir_intrinsic_load_num_work_groups:
 208                 info->cs.uses_grid_size = true;
 209                 break;
 210         case nir_intrinsic_load_local_invocation_id:
 211         case nir_intrinsic_load_work_group_id: {
 212                 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
 213                 while (mask) {
 214                         unsigned i = u_bit_scan(&mask);
 215
 216                         if (instr->intrinsic == nir_intrinsic_load_work_group_id)
 217                                 info->cs.uses_block_id[i] = true;
 218                         else
 219                                 info->cs.uses_thread_id[i] = true;
 220                 }
 221                 break;
 222         }
 223         case nir_intrinsic_load_local_invocation_index:
 224         case nir_intrinsic_load_subgroup_id:
 225         case nir_intrinsic_load_num_subgroups:
 226                 info->cs.uses_local_invocation_idx = true;
 227                 break;
 228         case nir_intrinsic_load_sample_id:
 229                 info->ps.force_persample = true;
 230                 break;
 231         case nir_intrinsic_load_sample_pos:
 232                 info->ps.force_persample = true;
 233                 break;
 234         case nir_intrinsic_load_view_index:
 235                 info->needs_multiview_view_index = true;
 236                 if (nir->info.stage == MESA_SHADER_FRAGMENT)
 237                         info->ps.layer_input = true;
 238                 break;
 239         case nir_intrinsic_load_invocation_id:
 240                 info->uses_invocation_id = true;
 241                 break;
 242         case nir_intrinsic_load_primitive_id:
 243                 info->uses_prim_id = true;
 244                 break;
 245         case nir_intrinsic_load_push_constant:
 246                 info->loads_push_constants = true;
 247                 break;
 248         case nir_intrinsic_vulkan_resource_index:
 249                 info->desc_set_used_mask |= (1 << nir_intrinsic_desc_set(instr));
 250                 break;
 251         case nir_intrinsic_image_deref_load:
 252         case nir_intrinsic_image_deref_store:
 253         case nir_intrinsic_image_deref_atomic_add:
 254         case nir_intrinsic_image_deref_atomic_min:
 255         case nir_intrinsic_image_deref_atomic_max:
 256         case nir_intrinsic_image_deref_atomic_and:
 257         case nir_intrinsic_image_deref_atomic_or:
 258         case nir_intrinsic_image_deref_atomic_xor:
 259         case nir_intrinsic_image_deref_atomic_exchange:
 260         case nir_intrinsic_image_deref_atomic_comp_swap:
 261         case nir_intrinsic_image_deref_size: {
 262                 nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
 263                 const struct glsl_type *type = glsl_without_array(var->type);
 264
 265                 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
 266                 if (dim == GLSL_SAMPLER_DIM_SUBPASS ||
 267                     dim == GLSL_SAMPLER_DIM_SUBPASS_MS) {
 268                         info->ps.layer_input = true;
 269                         info->ps.uses_input_attachments = true;
 270                 }
 271                 mark_sampler_desc(var, info);
 272
 273                 if (instr->intrinsic == nir_intrinsic_image_deref_store ||
 274                     instr->intrinsic == nir_intrinsic_image_deref_atomic_add ||
 275                     instr->intrinsic == nir_intrinsic_image_deref_atomic_min ||
 276                     instr->intrinsic == nir_intrinsic_image_deref_atomic_max ||
 277                     instr->intrinsic == nir_intrinsic_image_deref_atomic_and ||
 278                     instr->intrinsic == nir_intrinsic_image_deref_atomic_or ||
 279                     instr->intrinsic == nir_intrinsic_image_deref_atomic_xor ||
 280                     instr->intrinsic == nir_intrinsic_image_deref_atomic_exchange ||
 281                     instr->intrinsic == nir_intrinsic_image_deref_atomic_comp_swap) {
 282                         if (nir->info.stage == MESA_SHADER_FRAGMENT)
 283                                 info->ps.writes_memory = true;
 284                 }
 285                 break;
 286         }
 287         case nir_intrinsic_store_ssbo:
 288         case nir_intrinsic_ssbo_atomic_add:
 289         case nir_intrinsic_ssbo_atomic_imin:
 290         case nir_intrinsic_ssbo_atomic_umin:
 291         case nir_intrinsic_ssbo_atomic_imax:
 292         case nir_intrinsic_ssbo_atomic_umax:
 293         case nir_intrinsic_ssbo_atomic_and:
 294         case nir_intrinsic_ssbo_atomic_or:
 295         case nir_intrinsic_ssbo_atomic_xor:
 296         case nir_intrinsic_ssbo_atomic_exchange:
 297         case nir_intrinsic_ssbo_atomic_comp_swap:
 298                 if (nir->info.stage == MESA_SHADER_FRAGMENT)
 299                         info->ps.writes_memory = true;
 300                 break;
 301         case nir_intrinsic_load_deref:
 302                 gather_intrinsic_load_deref_info(nir, instr, info);
 303                 break;
 304         case nir_intrinsic_store_deref:
 305                 gather_intrinsic_store_deref_info(nir, instr, info);
 306                 break;
 307         default:
 308                 break;
 309         }
 310 }
 311
 312 static void
 313 gather_tex_info(const nir_shader *nir, const nir_tex_instr *instr,
 314                 struct radv_shader_info *info)
 315 {
 316         for (unsigned i = 0; i < instr->num_srcs; i++) {
 317                 switch (instr->src[i].src_type) {
 318                 case nir_tex_src_texture_deref:
 319                         mark_sampler_desc(nir_deref_instr_get_variable(nir_src_as_deref(instr->src[i].src)), info);
 320                         break;
 321                 case nir_tex_src_sampler_deref:
 322                         mark_sampler_desc(nir_deref_instr_get_variable(nir_src_as_deref(instr->src[i].src)), info);
 323                         break;
 324                 default:
 325                         break;
 326                 }
 327         }
 328 }
 329
 330 static void
 331 gather_info_block(const nir_shader *nir, const nir_block *block,
 332                   struct radv_shader_info *info)
 333 {
 334         nir_foreach_instr(instr, block) {
 335                 switch (instr->type) {
 336                 case nir_instr_type_intrinsic:
 337                         gather_intrinsic_info(nir, nir_instr_as_intrinsic(instr), info);
 338                         break;
 339                 case nir_instr_type_tex:
 340                         gather_tex_info(nir, nir_instr_as_tex(instr), info);
 341                         break;
 342                 default:
 343                         break;
 344                 }
 345         }
 346 }
 347
 348 static void
 349 gather_info_input_decl_vs(const nir_shader *nir, const nir_variable *var,
 350                           struct radv_shader_info *info)
 351 {
 352         int idx = var->data.location;
 353
 354         if (idx >= VERT_ATTRIB_GENERIC0 && idx <= VERT_ATTRIB_GENERIC15)
 355                 info->vs.has_vertex_buffers = true;
 356 }
 357
 358 static void
 359 gather_info_input_decl_ps(const nir_shader *nir, const nir_variable *var,
 360                           struct radv_shader_info *info)
 361 {
 362         unsigned attrib_count = glsl_count_attribute_slots(var->type, false);
 363         const struct glsl_type *type = glsl_without_array(var->type);
 364         int idx = var->data.location;
 365
 366         switch (idx) {
 367         case VARYING_SLOT_PNTC:
 368                 info->ps.has_pcoord = true;
 369                 break;
 370         case VARYING_SLOT_PRIMITIVE_ID:
 371                 info->ps.prim_id_input = true;
 372                 break;
 373         case VARYING_SLOT_LAYER:
 374                 info->ps.layer_input = true;
 375                 break;
 376         case VARYING_SLOT_CLIP_DIST0:
 377                 info->ps.num_input_clips_culls = attrib_count;
 378                 break;
 379         default:
 380                 break;
 381         }
 382
 383         if (glsl_get_base_type(type) == GLSL_TYPE_FLOAT) {
 384                 if (var->data.sample)
 385                         info->ps.force_persample = true;
 386         }
 387 }
 388
 389 static void
 390 gather_info_input_decl(const nir_shader *nir, const nir_variable *var,
 391                        struct radv_shader_info *info)
 392 {
 393         switch (nir->info.stage) {
 394         case MESA_SHADER_VERTEX:
 395                 gather_info_input_decl_vs(nir, var, info);
 396                 break;
 397         case MESA_SHADER_FRAGMENT:
 398                 gather_info_input_decl_ps(nir, var, info);
 399                 break;
 400         default:
 401                 break;
 402         }
 403 }
 404
 405 static void
 406 gather_info_output_decl_ls(const nir_shader *nir, const nir_variable *var,
 407                            struct radv_shader_info *info)
 408 {
 409         int idx = var->data.location;
 410         unsigned param = shader_io_get_unique_index(idx);
 411         int num_slots = glsl_count_attribute_slots(var->type, false);
 412         if (idx == VARYING_SLOT_CLIP_DIST0)
 413                 num_slots = (nir->info.clip_distance_array_size + nir->info.cull_distance_array_size > 4) ? 2 : 1;
 414         mark_ls_output(info, param, num_slots);
 415 }
 416
 417 static void
 418 gather_info_output_decl_ps(const nir_shader *nir, const nir_variable *var,
 419                            struct radv_shader_info *info)
 420 {
 421         int idx = var->data.location;
 422
 423         switch (idx) {
 424         case FRAG_RESULT_DEPTH:
 425                 info->ps.writes_z = true;
 426                 break;
 427         case FRAG_RESULT_STENCIL:
 428                 info->ps.writes_stencil = true;
 429                 break;
 430         case FRAG_RESULT_SAMPLE_MASK:
 431                 info->ps.writes_sample_mask = true;
 432                 break;
 433         default:
 434                 break;
 435         }
 436 }
 437
 438 static void
 439 gather_info_output_decl_gs(const nir_shader *nir, const nir_variable *var,
 440                            struct radv_shader_info *info)
 441 {
 442         unsigned num_components = glsl_get_component_slots(var->type);
 443         unsigned stream = var->data.stream;
 444         unsigned idx = var->data.location;
 445
 446         assert(stream < 4);
 447
 448         info->gs.max_stream = MAX2(info->gs.max_stream, stream);
 449         info->gs.num_stream_output_components[stream] += num_components;
 450         info->gs.output_streams[idx] = stream;
 451 }
 452
 453 static void
 454 gather_info_output_decl(const nir_shader *nir, const nir_variable *var,
 455                         struct radv_shader_info *info,
 456                         const struct radv_nir_compiler_options *options)
 457 {
 458         switch (nir->info.stage) {
 459         case MESA_SHADER_FRAGMENT:
 460                 gather_info_output_decl_ps(nir, var, info);
 461                 break;
 462         case MESA_SHADER_VERTEX:
 463                 if (options->key.vs.as_ls)
 464                         gather_info_output_decl_ls(nir, var, info);
 465                 break;
 466         case MESA_SHADER_GEOMETRY:
 467                 gather_info_output_decl_gs(nir, var, info);
 468                 break;
 469         default:
 470                 break;
 471         }
 472 }
 473
 474 static void
 475 gather_xfb_info(const nir_shader *nir, struct radv_shader_info *info)
 476 {
 477         nir_xfb_info *xfb = nir_gather_xfb_info(nir, NULL);
 478         struct radv_streamout_info *so = &info->so;
 479
 480         if (!xfb)
 481                 return;
 482
 483         assert(xfb->output_count < MAX_SO_OUTPUTS);
 484         so->num_outputs = xfb->output_count;
 485
 486         for (unsigned i = 0; i < xfb->output_count; i++) {
 487                 struct radv_stream_output *output = &so->outputs[i];
 488
 489                 output->buffer = xfb->outputs[i].buffer;
 490                 output->stream = xfb->buffer_to_stream[xfb->outputs[i].buffer];
 491                 output->offset = xfb->outputs[i].offset;
 492                 output->location = xfb->outputs[i].location;
 493                 output->component_mask = xfb->outputs[i].component_mask;
 494
 495                 so->enabled_stream_buffers_mask |=
 496                         (1 << output->buffer) << (output->stream * 4);
 497
 498         }
 499
 500         for (unsigned i = 0; i < NIR_MAX_XFB_BUFFERS; i++) {
 501                 so->strides[i] = xfb->strides[i] / 4;
 502         }
 503
 504         ralloc_free(xfb);
 505 }
 506
 507 void
 508 radv_nir_shader_info_pass(const struct nir_shader *nir,
 509                           const struct radv_nir_compiler_options *options,
 510                           struct radv_shader_info *info)
 511 {
 512         struct nir_function *func =
 513                 (struct nir_function *)exec_list_get_head_const(&nir->functions);
 514
 515         if (options->layout && options->layout->dynamic_offset_count)
 516                 info->loads_push_constants = true;
 517
 518         nir_foreach_variable(variable, &nir->inputs)
 519                 gather_info_input_decl(nir, variable, info);
 520
 521         nir_foreach_block(block, func->impl) {
 522                 gather_info_block(nir, block, info);
 523         }
 524
 525         nir_foreach_variable(variable, &nir->outputs)
 526                 gather_info_output_decl(nir, variable, info, options);
 527
 528         if (nir->info.stage == MESA_SHADER_VERTEX ||
 529             nir->info.stage == MESA_SHADER_TESS_EVAL ||
 530             nir->info.stage == MESA_SHADER_GEOMETRY)
 531                 gather_xfb_info(nir, info);
 532 }