src/amd/vulkan/radv_shader_info.c

   1 /*
   2  * Copyright © 2017 Red Hat
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23 #include "radv_private.h"
  24 #include "radv_shader.h"
  25 #include "nir/nir.h"
  26 #include "nir/nir_deref.h"
  27 #include "nir/nir_xfb_info.h"
  28
  29 static void mark_sampler_desc(const nir_variable *var,
  30                               struct radv_shader_info *info)
  31 {
  32         info->desc_set_used_mask |= (1 << var->data.descriptor_set);
  33 }
  34
  35 static void mark_ls_output(struct radv_shader_info *info,
  36                            uint32_t param, int num_slots)
  37 {
  38         uint64_t mask = (1ull << num_slots) - 1ull;
  39         info->vs.ls_outputs_written |= (mask << param);
  40 }
  41
  42 static void mark_tess_output(struct radv_shader_info *info,
  43                              bool is_patch, uint32_t param, int num_slots)
  44 {
  45         uint64_t mask = (1ull << num_slots) - 1ull;
  46         if (is_patch)
  47                 info->tcs.patch_outputs_written |= (mask << param);
  48         else
  49                 info->tcs.outputs_written |= (mask << param);
  50 }
  51
  52 static void
  53 get_deref_offset(nir_deref_instr *instr,
  54                  unsigned *const_out)
  55 {
  56         nir_variable *var = nir_deref_instr_get_variable(instr);
  57         nir_deref_path path;
  58         unsigned idx_lvl = 1;
  59
  60         if (var->data.compact) {
  61                 assert(instr->deref_type == nir_deref_type_array);
  62                 *const_out = nir_src_as_uint(instr->arr.index);
  63                 return;
  64         }
  65
  66         nir_deref_path_init(&path, instr, NULL);
  67
  68         uint32_t const_offset = 0;
  69
  70         for (; path.path[idx_lvl]; ++idx_lvl) {
  71                 const struct glsl_type *parent_type = path.path[idx_lvl - 1]->type;
  72                 if (path.path[idx_lvl]->deref_type == nir_deref_type_struct) {
  73                         unsigned index = path.path[idx_lvl]->strct.index;
  74
  75                         for (unsigned i = 0; i < index; i++) {
  76                                 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
  77                                 const_offset += glsl_count_attribute_slots(ft, false);
  78                         }
  79                 } else if(path.path[idx_lvl]->deref_type == nir_deref_type_array) {
  80                         unsigned size = glsl_count_attribute_slots(path.path[idx_lvl]->type, false);
  81                         if (nir_src_is_const(path.path[idx_lvl]->arr.index))
  82                                 const_offset += nir_src_as_uint(path.path[idx_lvl]->arr.index) * size;
  83                 } else
  84                         unreachable("Uhandled deref type in get_deref_instr_offset");
  85         }
  86
  87         *const_out = const_offset;
  88
  89         nir_deref_path_finish(&path);
  90 }
  91
  92 static void
  93 gather_intrinsic_load_deref_info(const nir_shader *nir,
  94                                const nir_intrinsic_instr *instr,
  95                                struct radv_shader_info *info)
  96 {
  97         switch (nir->info.stage) {
  98         case MESA_SHADER_VERTEX: {
  99                 nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
 100
 101                 if (var && var->data.mode == nir_var_shader_in) {
 102                         unsigned idx = var->data.location;
 103                         uint8_t mask = nir_ssa_def_components_read(&instr->dest.ssa);
 104
 105                         info->vs.input_usage_mask[idx] |=
 106                                 mask << var->data.location_frac;
 107                 }
 108                 break;
 109         }
 110         default:
 111                 break;
 112         }
 113 }
 114
 115 static uint32_t
 116 widen_writemask(uint32_t wrmask)
 117 {
 118         uint32_t new_wrmask = 0;
 119         for(unsigned i = 0; i < 4; i++)
 120                 new_wrmask |= (wrmask & (1 << i) ? 0x3 : 0x0) << (i * 2);
 121         return new_wrmask;
 122 }
 123
 124 static void
 125 set_output_usage_mask(const nir_shader *nir, const nir_intrinsic_instr *instr,
 126                       uint8_t *output_usage_mask)
 127 {
 128         nir_deref_instr *deref_instr =
 129                 nir_instr_as_deref(instr->src[0].ssa->parent_instr);
 130         nir_variable *var = nir_deref_instr_get_variable(deref_instr);
 131         unsigned attrib_count = glsl_count_attribute_slots(deref_instr->type, false);
 132         unsigned idx = var->data.location;
 133         unsigned comp = var->data.location_frac;
 134         unsigned const_offset = 0;
 135
 136         get_deref_offset(deref_instr, &const_offset);
 137
 138         if (var->data.compact) {
 139                 assert(!glsl_type_is_64bit(deref_instr->type));
 140                 const_offset += comp;
 141                 output_usage_mask[idx + const_offset / 4] |= 1 << (const_offset % 4);
 142                 return;
 143         }
 144
 145         uint32_t wrmask = nir_intrinsic_write_mask(instr);
 146         if (glsl_type_is_64bit(deref_instr->type))
 147                 wrmask = widen_writemask(wrmask);
 148
 149         for (unsigned i = 0; i < attrib_count; i++)
 150                 output_usage_mask[idx + i + const_offset] |=
 151                         ((wrmask >> (i * 4)) & 0xf) << comp;
 152 }
 153
 154 static void
 155 gather_intrinsic_store_deref_info(const nir_shader *nir,
 156                                 const nir_intrinsic_instr *instr,
 157                                 struct radv_shader_info *info)
 158 {
 159         nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
 160
 161         if (var && var->data.mode == nir_var_shader_out) {
 162                 unsigned idx = var->data.location;
 163
 164                 switch (nir->info.stage) {
 165                 case MESA_SHADER_VERTEX:
 166                         set_output_usage_mask(nir, instr,
 167                                               info->vs.output_usage_mask);
 168                         break;
 169                 case MESA_SHADER_GEOMETRY:
 170                         set_output_usage_mask(nir, instr,
 171                                               info->gs.output_usage_mask);
 172                         break;
 173                 case MESA_SHADER_TESS_EVAL:
 174                         set_output_usage_mask(nir, instr,
 175                                               info->tes.output_usage_mask);
 176                         break;
 177                 case MESA_SHADER_TESS_CTRL: {
 178                         unsigned param = shader_io_get_unique_index(idx);
 179                         const struct glsl_type *type = var->type;
 180
 181                         if (!var->data.patch)
 182                                 type = glsl_get_array_element(var->type);
 183
 184                         unsigned slots =
 185                                 var->data.compact ? DIV_ROUND_UP(var->data.location_frac + glsl_get_length(type), 4)
 186                                                   : glsl_count_attribute_slots(type, false);
 187
 188                         mark_tess_output(info, var->data.patch, param, slots);
 189                         break;
 190                 }
 191                 default:
 192                         break;
 193                 }
 194         }
 195 }
 196
 197 static void
 198 gather_push_constant_info(const nir_shader *nir,
 199                           const nir_intrinsic_instr *instr,
 200                           struct radv_shader_info *info)
 201 {
 202         int base = nir_intrinsic_base(instr);
 203
 204         if (!nir_src_is_const(instr->src[0])) {
 205                 info->has_indirect_push_constants = true;
 206         } else {
 207                 uint32_t min = base + nir_src_as_uint(instr->src[0]);
 208                 uint32_t max = min + instr->num_components * 4;
 209
 210                 info->max_push_constant_used =
 211                         MAX2(max, info->max_push_constant_used);
 212                 info->min_push_constant_used =
 213                         MIN2(min, info->min_push_constant_used);
 214         }
 215
 216         if (instr->dest.ssa.bit_size != 32)
 217                 info->has_only_32bit_push_constants = false;
 218
 219         info->loads_push_constants = true;
 220 }
 221
 222 static void
 223 gather_intrinsic_info(const nir_shader *nir, const nir_intrinsic_instr *instr,
 224                       struct radv_shader_info *info)
 225 {
 226         switch (instr->intrinsic) {
 227         case nir_intrinsic_load_barycentric_at_sample:
 228                 info->ps.needs_sample_positions = true;
 229                 break;
 230         case nir_intrinsic_load_draw_id:
 231                 info->vs.needs_draw_id = true;
 232                 break;
 233         case nir_intrinsic_load_instance_id:
 234                 info->vs.needs_instance_id = true;
 235                 break;
 236         case nir_intrinsic_load_num_work_groups:
 237                 info->cs.uses_grid_size = true;
 238                 break;
 239         case nir_intrinsic_load_local_invocation_id:
 240         case nir_intrinsic_load_work_group_id: {
 241                 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
 242                 while (mask) {
 243                         unsigned i = u_bit_scan(&mask);
 244
 245                         if (instr->intrinsic == nir_intrinsic_load_work_group_id)
 246                                 info->cs.uses_block_id[i] = true;
 247                         else
 248                                 info->cs.uses_thread_id[i] = true;
 249                 }
 250                 break;
 251         }
 252         case nir_intrinsic_load_local_invocation_index:
 253         case nir_intrinsic_load_subgroup_id:
 254         case nir_intrinsic_load_num_subgroups:
 255                 info->cs.uses_local_invocation_idx = true;
 256                 break;
 257         case nir_intrinsic_load_sample_id:
 258                 info->ps.force_persample = true;
 259                 break;
 260         case nir_intrinsic_load_sample_pos:
 261                 info->ps.force_persample = true;
 262                 break;
 263         case nir_intrinsic_load_view_index:
 264                 info->needs_multiview_view_index = true;
 265                 if (nir->info.stage == MESA_SHADER_FRAGMENT)
 266                         info->ps.layer_input = true;
 267                 break;
 268         case nir_intrinsic_load_layer_id:
 269                 if (nir->info.stage == MESA_SHADER_FRAGMENT)
 270                         info->ps.layer_input = true;
 271                 break;
 272         case nir_intrinsic_load_invocation_id:
 273                 info->uses_invocation_id = true;
 274                 break;
 275         case nir_intrinsic_load_primitive_id:
 276                 info->uses_prim_id = true;
 277                 break;
 278         case nir_intrinsic_load_push_constant:
 279                 gather_push_constant_info(nir, instr, info);
 280                 break;
 281         case nir_intrinsic_vulkan_resource_index:
 282                 info->desc_set_used_mask |= (1 << nir_intrinsic_desc_set(instr));
 283                 break;
 284         case nir_intrinsic_image_deref_load:
 285         case nir_intrinsic_image_deref_store:
 286         case nir_intrinsic_image_deref_atomic_add:
 287         case nir_intrinsic_image_deref_atomic_imin:
 288         case nir_intrinsic_image_deref_atomic_umin:
 289         case nir_intrinsic_image_deref_atomic_imax:
 290         case nir_intrinsic_image_deref_atomic_umax:
 291         case nir_intrinsic_image_deref_atomic_and:
 292         case nir_intrinsic_image_deref_atomic_or:
 293         case nir_intrinsic_image_deref_atomic_xor:
 294         case nir_intrinsic_image_deref_atomic_exchange:
 295         case nir_intrinsic_image_deref_atomic_comp_swap:
 296         case nir_intrinsic_image_deref_size: {
 297                 nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
 298                 mark_sampler_desc(var, info);
 299
 300                 if (instr->intrinsic == nir_intrinsic_image_deref_store ||
 301                     instr->intrinsic == nir_intrinsic_image_deref_atomic_add ||
 302                     instr->intrinsic == nir_intrinsic_image_deref_atomic_imin ||
 303                     instr->intrinsic == nir_intrinsic_image_deref_atomic_umin ||
 304                     instr->intrinsic == nir_intrinsic_image_deref_atomic_imax ||
 305                     instr->intrinsic == nir_intrinsic_image_deref_atomic_umax ||
 306                     instr->intrinsic == nir_intrinsic_image_deref_atomic_and ||
 307                     instr->intrinsic == nir_intrinsic_image_deref_atomic_or ||
 308                     instr->intrinsic == nir_intrinsic_image_deref_atomic_xor ||
 309                     instr->intrinsic == nir_intrinsic_image_deref_atomic_exchange ||
 310                     instr->intrinsic == nir_intrinsic_image_deref_atomic_comp_swap) {
 311                         if (nir->info.stage == MESA_SHADER_FRAGMENT)
 312                                 info->ps.writes_memory = true;
 313                         else if (nir->info.stage == MESA_SHADER_GEOMETRY)
 314                                 info->gs.writes_memory = true;
 315                 }
 316                 break;
 317         }
 318         case nir_intrinsic_store_ssbo:
 319         case nir_intrinsic_ssbo_atomic_add:
 320         case nir_intrinsic_ssbo_atomic_imin:
 321         case nir_intrinsic_ssbo_atomic_umin:
 322         case nir_intrinsic_ssbo_atomic_imax:
 323         case nir_intrinsic_ssbo_atomic_umax:
 324         case nir_intrinsic_ssbo_atomic_and:
 325         case nir_intrinsic_ssbo_atomic_or:
 326         case nir_intrinsic_ssbo_atomic_xor:
 327         case nir_intrinsic_ssbo_atomic_exchange:
 328         case nir_intrinsic_ssbo_atomic_comp_swap:
 329                 if (nir->info.stage == MESA_SHADER_FRAGMENT)
 330                         info->ps.writes_memory = true;
 331                 else if (nir->info.stage == MESA_SHADER_GEOMETRY)
 332                         info->gs.writes_memory = true;
 333                 break;
 334         case nir_intrinsic_load_deref:
 335                 gather_intrinsic_load_deref_info(nir, instr, info);
 336                 break;
 337         case nir_intrinsic_store_deref:
 338                 gather_intrinsic_store_deref_info(nir, instr, info);
 339                 break;
 340         default:
 341                 break;
 342         }
 343 }
 344
 345 static void
 346 gather_tex_info(const nir_shader *nir, const nir_tex_instr *instr,
 347                 struct radv_shader_info *info)
 348 {
 349         for (unsigned i = 0; i < instr->num_srcs; i++) {
 350                 switch (instr->src[i].src_type) {
 351                 case nir_tex_src_texture_deref:
 352                         mark_sampler_desc(nir_deref_instr_get_variable(nir_src_as_deref(instr->src[i].src)), info);
 353                         break;
 354                 case nir_tex_src_sampler_deref:
 355                         mark_sampler_desc(nir_deref_instr_get_variable(nir_src_as_deref(instr->src[i].src)), info);
 356                         break;
 357                 default:
 358                         break;
 359                 }
 360         }
 361 }
 362
 363 static void
 364 gather_info_block(const nir_shader *nir, const nir_block *block,
 365                   struct radv_shader_info *info)
 366 {
 367         nir_foreach_instr(instr, block) {
 368                 switch (instr->type) {
 369                 case nir_instr_type_intrinsic:
 370                         gather_intrinsic_info(nir, nir_instr_as_intrinsic(instr), info);
 371                         break;
 372                 case nir_instr_type_tex:
 373                         gather_tex_info(nir, nir_instr_as_tex(instr), info);
 374                         break;
 375                 default:
 376                         break;
 377                 }
 378         }
 379 }
 380
 381 static void
 382 gather_info_input_decl_vs(const nir_shader *nir, const nir_variable *var,
 383                           struct radv_shader_info *info,
 384                           const struct radv_shader_variant_key *key)
 385 {
 386         unsigned attrib_count = glsl_count_attribute_slots(var->type, true);
 387         int idx = var->data.location;
 388
 389         if (idx >= VERT_ATTRIB_GENERIC0 && idx <= VERT_ATTRIB_GENERIC15)
 390                 info->vs.has_vertex_buffers = true;
 391
 392         for (unsigned i = 0; i < attrib_count; ++i) {
 393                 unsigned attrib_index = var->data.location + i - VERT_ATTRIB_GENERIC0;
 394
 395                 if (key->vs.instance_rate_inputs & (1u << attrib_index))
 396                         info->vs.needs_instance_id = true;
 397         }
 398 }
 399
 400 static void
 401 mark_16bit_ps_input(struct radv_shader_info *info, const struct glsl_type *type,
 402                     int location)
 403 {
 404         if (glsl_type_is_scalar(type) || glsl_type_is_vector(type) || glsl_type_is_matrix(type)) {
 405                 unsigned attrib_count = glsl_count_attribute_slots(type, false);
 406                 if (glsl_type_is_16bit(type)) {
 407                         info->ps.float16_shaded_mask |= ((1ull << attrib_count) - 1) << location;
 408                 }
 409         } else if (glsl_type_is_array(type)) {
 410                 unsigned stride = glsl_count_attribute_slots(glsl_get_array_element(type), false);
 411                 for (unsigned i = 0; i < glsl_get_length(type); ++i) {
 412                         mark_16bit_ps_input(info, glsl_get_array_element(type), location + i * stride);
 413                 }
 414         } else {
 415                 assert(glsl_type_is_struct_or_ifc(type));
 416                 for (unsigned i = 0; i < glsl_get_length(type); i++) {
 417                         mark_16bit_ps_input(info, glsl_get_struct_field(type, i), location);
 418                         location += glsl_count_attribute_slots(glsl_get_struct_field(type, i), false);
 419                 }
 420         }
 421 }
 422 static void
 423 gather_info_input_decl_ps(const nir_shader *nir, const nir_variable *var,
 424                           struct radv_shader_info *info)
 425 {
 426         unsigned attrib_count = glsl_count_attribute_slots(var->type, false);
 427         const struct glsl_type *type = glsl_without_array(var->type);
 428         int idx = var->data.location;
 429
 430         switch (idx) {
 431         case VARYING_SLOT_PNTC:
 432                 info->ps.has_pcoord = true;
 433                 break;
 434         case VARYING_SLOT_PRIMITIVE_ID:
 435                 info->ps.prim_id_input = true;
 436                 break;
 437         case VARYING_SLOT_LAYER:
 438                 info->ps.layer_input = true;
 439                 break;
 440         case VARYING_SLOT_CLIP_DIST0:
 441         case VARYING_SLOT_CLIP_DIST1:
 442                 info->ps.num_input_clips_culls += attrib_count;
 443                 break;
 444         default:
 445                 break;
 446         }
 447
 448         if (glsl_get_base_type(type) == GLSL_TYPE_FLOAT) {
 449                 if (var->data.sample)
 450                         info->ps.force_persample = true;
 451         }
 452
 453         if (var->data.compact) {
 454                 unsigned component_count = var->data.location_frac +
 455                                            glsl_get_length(var->type);
 456                 attrib_count = (component_count + 3) / 4;
 457         } else {
 458                 mark_16bit_ps_input(info, var->type, var->data.driver_location);
 459         }
 460
 461         uint64_t mask = ((1ull << attrib_count) - 1);
 462
 463         if (var->data.interpolation == INTERP_MODE_FLAT)
 464                 info->ps.flat_shaded_mask |= mask << var->data.driver_location;
 465
 466         if (var->data.location >= VARYING_SLOT_VAR0)
 467                 info->ps.input_mask |= mask << (var->data.location - VARYING_SLOT_VAR0);
 468 }
 469
 470 static void
 471 gather_info_input_decl(const nir_shader *nir, const nir_variable *var,
 472                        struct radv_shader_info *info,
 473                        const struct radv_shader_variant_key *key)
 474 {
 475         switch (nir->info.stage) {
 476         case MESA_SHADER_VERTEX:
 477                 gather_info_input_decl_vs(nir, var, info, key);
 478                 break;
 479         case MESA_SHADER_FRAGMENT:
 480                 gather_info_input_decl_ps(nir, var, info);
 481                 break;
 482         default:
 483                 break;
 484         }
 485 }
 486
 487 static void
 488 gather_info_output_decl_ls(const nir_shader *nir, const nir_variable *var,
 489                            struct radv_shader_info *info)
 490 {
 491         int idx = var->data.location;
 492         unsigned param = shader_io_get_unique_index(idx);
 493         int num_slots = glsl_count_attribute_slots(var->type, false);
 494         if (var->data.compact)
 495                 num_slots = DIV_ROUND_UP(var->data.location_frac + glsl_get_length(var->type), 4);
 496         mark_ls_output(info, param, num_slots);
 497 }
 498
 499 static void
 500 gather_info_output_decl_ps(const nir_shader *nir, const nir_variable *var,
 501                            struct radv_shader_info *info)
 502 {
 503         int idx = var->data.location;
 504
 505         switch (idx) {
 506         case FRAG_RESULT_DEPTH:
 507                 info->ps.writes_z = true;
 508                 break;
 509         case FRAG_RESULT_STENCIL:
 510                 info->ps.writes_stencil = true;
 511                 break;
 512         case FRAG_RESULT_SAMPLE_MASK:
 513                 info->ps.writes_sample_mask = true;
 514                 break;
 515         default:
 516                 break;
 517         }
 518 }
 519
 520 static void
 521 gather_info_output_decl_gs(const nir_shader *nir, const nir_variable *var,
 522                            struct radv_shader_info *info)
 523 {
 524         unsigned num_components = glsl_get_component_slots(var->type);
 525         unsigned stream = var->data.stream;
 526         unsigned idx = var->data.location;
 527
 528         assert(stream < 4);
 529
 530         info->gs.max_stream = MAX2(info->gs.max_stream, stream);
 531         info->gs.num_stream_output_components[stream] += num_components;
 532         info->gs.output_streams[idx] = stream;
 533 }
 534
 535 static void
 536 gather_info_output_decl(const nir_shader *nir, const nir_variable *var,
 537                         struct radv_shader_info *info,
 538                         const struct radv_shader_variant_key *key)
 539 {
 540         struct radv_vs_output_info *vs_info = NULL;
 541
 542         switch (nir->info.stage) {
 543         case MESA_SHADER_FRAGMENT:
 544                 gather_info_output_decl_ps(nir, var, info);
 545                 break;
 546         case MESA_SHADER_VERTEX:
 547                 if (!key->vs_common_out.as_ls &&
 548                     !key->vs_common_out.as_es)
 549                         vs_info = &info->vs.outinfo;
 550
 551                 if (key->vs_common_out.as_ls)
 552                         gather_info_output_decl_ls(nir, var, info);
 553                 else if (key->vs_common_out.as_ngg)
 554                         gather_info_output_decl_gs(nir, var, info);
 555                 break;
 556         case MESA_SHADER_GEOMETRY:
 557                 vs_info = &info->vs.outinfo;
 558                 gather_info_output_decl_gs(nir, var, info);
 559                 break;
 560         case MESA_SHADER_TESS_EVAL:
 561                 if (!key->vs_common_out.as_es)
 562                         vs_info = &info->tes.outinfo;
 563                 break;
 564         default:
 565                 break;
 566         }
 567
 568         if (vs_info) {
 569                 switch (var->data.location) {
 570                 case VARYING_SLOT_CLIP_DIST0:
 571                         vs_info->clip_dist_mask =
 572                                 (1 << nir->info.clip_distance_array_size) - 1;
 573                         vs_info->cull_dist_mask =
 574                                 (1 << nir->info.cull_distance_array_size) - 1;
 575                         vs_info->cull_dist_mask <<= nir->info.clip_distance_array_size;
 576                         break;
 577                 case VARYING_SLOT_PSIZ:
 578                         vs_info->writes_pointsize = true;
 579                         break;
 580                 case VARYING_SLOT_VIEWPORT:
 581                         vs_info->writes_viewport_index = true;
 582                         break;
 583                 case VARYING_SLOT_LAYER:
 584                         vs_info->writes_layer = true;
 585                         break;
 586                 default:
 587                         break;
 588                 }
 589         }
 590 }
 591
 592 static void
 593 gather_xfb_info(const nir_shader *nir, struct radv_shader_info *info)
 594 {
 595         nir_xfb_info *xfb = nir_gather_xfb_info(nir, NULL);
 596         struct radv_streamout_info *so = &info->so;
 597
 598         if (!xfb)
 599                 return;
 600
 601         assert(xfb->output_count < MAX_SO_OUTPUTS);
 602         so->num_outputs = xfb->output_count;
 603
 604         for (unsigned i = 0; i < xfb->output_count; i++) {
 605                 struct radv_stream_output *output = &so->outputs[i];
 606
 607                 output->buffer = xfb->outputs[i].buffer;
 608                 output->stream = xfb->buffer_to_stream[xfb->outputs[i].buffer];
 609                 output->offset = xfb->outputs[i].offset;
 610                 output->location = xfb->outputs[i].location;
 611                 output->component_mask = xfb->outputs[i].component_mask;
 612
 613                 so->enabled_stream_buffers_mask |=
 614                         (1 << output->buffer) << (output->stream * 4);
 615
 616         }
 617
 618         for (unsigned i = 0; i < NIR_MAX_XFB_BUFFERS; i++) {
 619                 so->strides[i] = xfb->buffers[i].stride / 4;
 620         }
 621
 622         ralloc_free(xfb);
 623 }
 624
 625 void
 626 radv_nir_shader_info_init(struct radv_shader_info *info)
 627 {
 628         /* Assume that shaders only have 32-bit push constants by default. */
 629         info->min_push_constant_used = UINT8_MAX;
 630         info->has_only_32bit_push_constants = true;
 631 }
 632
 633 void
 634 radv_nir_shader_info_pass(const struct nir_shader *nir,
 635                           const struct radv_pipeline_layout *layout,
 636                           const struct radv_shader_variant_key *key,
 637                           struct radv_shader_info *info)
 638 {
 639         struct nir_function *func =
 640                 (struct nir_function *)exec_list_get_head_const(&nir->functions);
 641
 642         if (layout && layout->dynamic_offset_count &&
 643             (layout->dynamic_shader_stages & mesa_to_vk_shader_stage(nir->info.stage))) {
 644                 info->loads_push_constants = true;
 645                 info->loads_dynamic_offsets = true;
 646         }
 647
 648         nir_foreach_variable(variable, &nir->inputs)
 649                 gather_info_input_decl(nir, variable, info, key);
 650
 651         nir_foreach_block(block, func->impl) {
 652                 gather_info_block(nir, block, info);
 653         }
 654
 655         nir_foreach_variable(variable, &nir->outputs)
 656                 gather_info_output_decl(nir, variable, info, key);
 657
 658         if (nir->info.stage == MESA_SHADER_VERTEX ||
 659             nir->info.stage == MESA_SHADER_TESS_EVAL ||
 660             nir->info.stage == MESA_SHADER_GEOMETRY)
 661                 gather_xfb_info(nir, info);
 662
 663         /* Make sure to export the LayerID if the fragment shader needs it. */
 664         if (key->vs_common_out.export_layer_id) {
 665                 switch (nir->info.stage) {
 666                 case MESA_SHADER_VERTEX:
 667                         info->vs.output_usage_mask[VARYING_SLOT_LAYER] |= 0x1;
 668                         break;
 669                 case MESA_SHADER_TESS_EVAL:
 670                         info->tes.output_usage_mask[VARYING_SLOT_LAYER] |= 0x1;
 671                         break;
 672                 case MESA_SHADER_GEOMETRY:
 673                         info->gs.output_usage_mask[VARYING_SLOT_LAYER] |= 0x1;
 674                         break;
 675                 default:
 676                         break;
 677                 }
 678         }
 679
 680         /* Make sure to export the LayerID if the subpass has multiviews. */
 681         if (key->has_multiview_view_index) {
 682                 switch (nir->info.stage) {
 683                 case MESA_SHADER_VERTEX:
 684                         info->vs.outinfo.writes_layer = true;
 685                         break;
 686                 case MESA_SHADER_TESS_EVAL:
 687                         info->tes.outinfo.writes_layer = true;
 688                         break;
 689                 case MESA_SHADER_GEOMETRY:
 690                         info->vs.outinfo.writes_layer = true;
 691                         break;
 692                 default:
 693                         break;
 694                 }
 695         }
 696
 697         /* Make sure to export the PrimitiveID if the fragment shader needs it. */
 698         if (key->vs_common_out.export_prim_id) {
 699                 switch (nir->info.stage) {
 700                 case MESA_SHADER_VERTEX:
 701                         info->vs.outinfo.export_prim_id = true;
 702                         break;
 703                 case MESA_SHADER_TESS_EVAL:
 704                         info->tes.outinfo.export_prim_id = true;
 705                         break;
 706                 case MESA_SHADER_GEOMETRY:
 707                         info->vs.outinfo.export_prim_id = true;
 708                         break;
 709                 default:
 710                         break;
 711                 }
 712         }
 713
 714         if (nir->info.stage == MESA_SHADER_FRAGMENT)
 715                 info->ps.num_interp = nir->num_inputs;
 716
 717         switch (nir->info.stage) {
 718         case MESA_SHADER_COMPUTE:
 719                 for (int i = 0; i < 3; ++i)
 720                         info->cs.block_size[i] = nir->info.cs.local_size[i];
 721                 break;
 722         case MESA_SHADER_FRAGMENT:
 723                 info->ps.can_discard = nir->info.fs.uses_discard;
 724                 info->ps.early_fragment_test = nir->info.fs.early_fragment_tests;
 725                 info->ps.post_depth_coverage = nir->info.fs.post_depth_coverage;
 726                 break;
 727         case MESA_SHADER_GEOMETRY:
 728                 info->gs.vertices_in = nir->info.gs.vertices_in;
 729                 info->gs.vertices_out = nir->info.gs.vertices_out;
 730                 info->gs.output_prim = nir->info.gs.output_primitive;
 731                 info->gs.invocations = nir->info.gs.invocations;
 732                 break;
 733         case MESA_SHADER_TESS_EVAL:
 734                 info->tes.primitive_mode = nir->info.tess.primitive_mode;
 735                 info->tes.spacing = nir->info.tess.spacing;
 736                 info->tes.ccw = nir->info.tess.ccw;
 737                 info->tes.point_mode = nir->info.tess.point_mode;
 738                 info->tes.as_es = key->vs_common_out.as_es;
 739                 info->tes.export_prim_id = key->vs_common_out.export_prim_id;
 740                 info->is_ngg = key->vs_common_out.as_ngg;
 741                 break;
 742         case MESA_SHADER_TESS_CTRL:
 743                 info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
 744                 break;
 745         case MESA_SHADER_VERTEX:
 746                 info->vs.as_es = key->vs_common_out.as_es;
 747                 info->vs.as_ls = key->vs_common_out.as_ls;
 748                 info->vs.export_prim_id = key->vs_common_out.export_prim_id;
 749                 info->is_ngg = key->vs_common_out.as_ngg;
 750                 break;
 751         default:
 752                 break;
 753         }
 754
 755         if (nir->info.stage == MESA_SHADER_GEOMETRY) {
 756                 unsigned add_clip = nir->info.clip_distance_array_size +
 757                                     nir->info.cull_distance_array_size > 4;
 758                 info->gs.gsvs_vertex_size =
 759                         (util_bitcount64(nir->info.outputs_written) + add_clip) * 16;
 760                 info->gs.max_gsvs_emit_size =
 761                         info->gs.gsvs_vertex_size * nir->info.gs.vertices_out;
 762         }
 763
 764         /* Compute the ESGS item size for VS or TES as ES. */
 765         if ((nir->info.stage == MESA_SHADER_VERTEX ||
 766              nir->info.stage == MESA_SHADER_TESS_EVAL) &&
 767             key->vs_common_out.as_es) {
 768                 struct radv_es_output_info *es_info =
 769                         nir->info.stage == MESA_SHADER_VERTEX ? &info->vs.es_info : &info->tes.es_info;
 770                 uint32_t max_output_written = 0;
 771
 772                 uint64_t output_mask = nir->info.outputs_written;
 773                 while (output_mask) {
 774                         const int i = u_bit_scan64(&output_mask);
 775                         unsigned param_index = shader_io_get_unique_index(i);
 776
 777                         max_output_written = MAX2(param_index, max_output_written);
 778                 }
 779
 780                 es_info->esgs_itemsize = (max_output_written + 1) * 16;
 781         }
 782
 783         info->float_controls_mode = nir->info.float_controls_execution_mode;
 784 }