projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv: drop wrong initialization of COMPUTE_RESOURCE_LIMITS
[mesa.git] / src / amd / vulkan / si_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based on si_state.c
6 * Copyright © 2015 Advanced Micro Devices, Inc.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 /* command buffer handling for SI */
29
30 #include "radv_private.h"
31 #include "radv_shader.h"
32 #include "radv_cs.h"
33 #include "sid.h"
34 #include "gfx9d.h"
35 #include "radv_util.h"
36 #include "main/macros.h"
37
38 static void
39 si_write_harvested_raster_configs(struct radv_physical_device *physical_device,
40 struct radeon_cmdbuf *cs,
41 unsigned raster_config,
42 unsigned raster_config_1)
43 {
44 unsigned num_se = MAX2(physical_device->rad_info.max_se, 1);
45 unsigned raster_config_se[4];
46 unsigned se;
47
48 ac_get_harvested_configs(&physical_device->rad_info,
49 raster_config,
50 &raster_config_1,
51 raster_config_se);
52
53 for (se = 0; se < num_se; se++) {
54 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
55 if (physical_device->rad_info.chip_class < CIK)
56 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
57 S_00802C_SE_INDEX(se) |
58 S_00802C_SH_BROADCAST_WRITES(1) |
59 S_00802C_INSTANCE_BROADCAST_WRITES(1));
60 else
61 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
62 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
63 S_030800_INSTANCE_BROADCAST_WRITES(1));
64 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
65 }
66
67 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
68 if (physical_device->rad_info.chip_class < CIK)
69 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
70 S_00802C_SE_BROADCAST_WRITES(1) |
71 S_00802C_SH_BROADCAST_WRITES(1) |
72 S_00802C_INSTANCE_BROADCAST_WRITES(1));
73 else
74 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
75 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
76 S_030800_INSTANCE_BROADCAST_WRITES(1));
77
78 if (physical_device->rad_info.chip_class >= CIK)
79 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
80 }
81
82 static void
83 si_emit_compute(struct radv_physical_device *physical_device,
84 struct radeon_cmdbuf *cs)
85 {
86 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
87 radeon_emit(cs, 0);
88 radeon_emit(cs, 0);
89 radeon_emit(cs, 0);
90
91 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
92 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
93 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
94 radeon_emit(cs, S_00B85C_SH0_CU_EN(0xffff) | S_00B85C_SH1_CU_EN(0xffff));
95
96 if (physical_device->rad_info.chip_class >= CIK) {
97 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
98 radeon_set_sh_reg_seq(cs,
99 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
100 radeon_emit(cs, S_00B864_SH0_CU_EN(0xffff) |
101 S_00B864_SH1_CU_EN(0xffff));
102 radeon_emit(cs, S_00B868_SH0_CU_EN(0xffff) |
103 S_00B868_SH1_CU_EN(0xffff));
104 }
105
106 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
107 * and is now per pipe, so it should be handled in the
108 * kernel if we want to use something other than the default value,
109 * which is now 0x22f.
110 */
111 if (physical_device->rad_info.chip_class <= SI) {
112 /* XXX: This should be:
113 * (number of compute units) * 4 * (waves per simd) - 1 */
114
115 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
116 0x190 /* Default value */);
117 }
118 }
119
120 void
121 si_init_compute(struct radv_cmd_buffer *cmd_buffer)
122 {
123 struct radv_physical_device *physical_device = cmd_buffer->device->physical_device;
124 si_emit_compute(physical_device, cmd_buffer->cs);
125 }
126
127 /* 12.4 fixed-point */
128 static unsigned radv_pack_float_12p4(float x)
129 {
130 return x <= 0 ? 0 :
131 x >= 4096 ? 0xffff : x * 16;
132 }
133
134 static void
135 si_set_raster_config(struct radv_physical_device *physical_device,
136 struct radeon_cmdbuf *cs)
137 {
138 unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
139 unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
140 unsigned raster_config, raster_config_1;
141
142 ac_get_raster_config(&physical_device->rad_info,
143 &raster_config,
144 &raster_config_1);
145
146 /* Always use the default config when all backends are enabled
147 * (or when we failed to determine the enabled backends).
148 */
149 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
150 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG,
151 raster_config);
152 if (physical_device->rad_info.chip_class >= CIK)
153 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1,
154 raster_config_1);
155 } else {
156 si_write_harvested_raster_configs(physical_device, cs,
157 raster_config,
158 raster_config_1);
159 }
160 }
161
162 static void
163 si_emit_config(struct radv_physical_device *physical_device,
164 struct radeon_cmdbuf *cs)
165 {
166 int i;
167
168 /* Only SI can disable CLEAR_STATE for now. */
169 assert(physical_device->has_clear_state ||
170 physical_device->rad_info.chip_class == SI);
171
172 radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
173 radeon_emit(cs, CONTEXT_CONTROL_LOAD_ENABLE(1));
174 radeon_emit(cs, CONTEXT_CONTROL_SHADOW_ENABLE(1));
175
176 if (physical_device->has_clear_state) {
177 radeon_emit(cs, PKT3(PKT3_CLEAR_STATE, 0, 0));
178 radeon_emit(cs, 0);
179 }
180
181 if (physical_device->rad_info.chip_class <= VI)
182 si_set_raster_config(physical_device, cs);
183
184 radeon_set_context_reg(cs, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
185 if (!physical_device->has_clear_state)
186 radeon_set_context_reg(cs, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
187
188 /* FIXME calculate these values somehow ??? */
189 if (physical_device->rad_info.chip_class <= VI) {
190 radeon_set_context_reg(cs, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
191 radeon_set_context_reg(cs, R_028A58_VGT_ES_PER_GS, 0x40);
192 }
193
194 if (!physical_device->has_clear_state) {
195 radeon_set_context_reg(cs, R_028A5C_VGT_GS_PER_VS, 0x2);
196 radeon_set_context_reg(cs, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
197 radeon_set_context_reg(cs, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
198 }
199
200 radeon_set_context_reg(cs, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
201 if (!physical_device->has_clear_state)
202 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, 0x0);
203 if (physical_device->rad_info.chip_class < CIK)
204 radeon_set_config_reg(cs, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
205 S_008A14_CLIP_VTX_REORDER_ENA(1));
206
207 radeon_set_context_reg(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
208 radeon_set_context_reg(cs, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
209
210 if (!physical_device->has_clear_state)
211 radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
212
213 /* CLEAR_STATE doesn't clear these correctly on certain generations.
214 * I don't know why. Deduced by trial and error.
215 */
216 if (physical_device->rad_info.chip_class <= CIK) {
217 radeon_set_context_reg(cs, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
218 radeon_set_context_reg(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL,
219 S_028204_WINDOW_OFFSET_DISABLE(1));
220 radeon_set_context_reg(cs, R_028240_PA_SC_GENERIC_SCISSOR_TL,
221 S_028240_WINDOW_OFFSET_DISABLE(1));
222 radeon_set_context_reg(cs, R_028244_PA_SC_GENERIC_SCISSOR_BR,
223 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
224 radeon_set_context_reg(cs, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
225 radeon_set_context_reg(cs, R_028034_PA_SC_SCREEN_SCISSOR_BR,
226 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
227 }
228
229 if (!physical_device->has_clear_state) {
230 for (i = 0; i < 16; i++) {
231 radeon_set_context_reg(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
232 radeon_set_context_reg(cs, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
233 }
234 }
235
236 if (!physical_device->has_clear_state) {
237 radeon_set_context_reg(cs, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
238 radeon_set_context_reg(cs, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
239 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
240 radeon_set_context_reg(cs, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
241 radeon_set_context_reg(cs, R_028820_PA_CL_NANINF_CNTL, 0);
242 radeon_set_context_reg(cs, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
243 radeon_set_context_reg(cs, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
244 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
245 }
246
247 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE,
248 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
249 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
250
251 if (physical_device->rad_info.chip_class >= GFX9) {
252 radeon_set_uconfig_reg(cs, R_030920_VGT_MAX_VTX_INDX, ~0);
253 radeon_set_uconfig_reg(cs, R_030924_VGT_MIN_VTX_INDX, 0);
254 radeon_set_uconfig_reg(cs, R_030928_VGT_INDX_OFFSET, 0);
255 } else {
256 /* These registers, when written, also overwrite the
257 * CLEAR_STATE context, so we can't rely on CLEAR_STATE setting
258 * them. It would be an issue if there was another UMD
259 * changing them.
260 */
261 radeon_set_context_reg(cs, R_028400_VGT_MAX_VTX_INDX, ~0);
262 radeon_set_context_reg(cs, R_028404_VGT_MIN_VTX_INDX, 0);
263 radeon_set_context_reg(cs, R_028408_VGT_INDX_OFFSET, 0);
264 }
265
266 if (physical_device->rad_info.chip_class >= CIK) {
267 if (physical_device->rad_info.chip_class >= GFX9) {
268 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
269 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
270 } else {
271 radeon_set_sh_reg(cs, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
272 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
273 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
274 S_00B41C_WAVE_LIMIT(0x3F));
275 radeon_set_sh_reg(cs, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
276 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
277 /* If this is 0, Bonaire can hang even if GS isn't being used.
278 * Other chips are unaffected. These are suboptimal values,
279 * but we don't use on-chip GS.
280 */
281 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL,
282 S_028A44_ES_VERTS_PER_SUBGRP(64) |
283 S_028A44_GS_PRIMS_PER_SUBGRP(4));
284 }
285 radeon_set_sh_reg(cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
286 S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
287
288 if (physical_device->rad_info.num_good_compute_units /
289 (physical_device->rad_info.max_se * physical_device->rad_info.max_sh_per_se) <= 4) {
290 /* Too few available compute units per SH. Disallowing
291 * VS to run on CU0 could hurt us more than late VS
292 * allocation would help.
293 *
294 * LATE_ALLOC_VS = 2 is the highest safe number.
295 */
296 radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
297 S_00B118_CU_EN(0xffff) | S_00B118_WAVE_LIMIT(0x3F) );
298 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
299 } else {
300 /* Set LATE_ALLOC_VS == 31. It should be less than
301 * the number of scratch waves. Limitations:
302 * - VS can't execute on CU0.
303 * - If HS writes outputs to LDS, LS can't execute on CU0.
304 */
305 radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
306 S_00B118_CU_EN(0xfffe) | S_00B118_WAVE_LIMIT(0x3F));
307 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
308 }
309
310 radeon_set_sh_reg(cs, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
311 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
312 }
313
314 if (physical_device->rad_info.chip_class >= VI) {
315 uint32_t vgt_tess_distribution;
316 radeon_set_context_reg(cs, R_028424_CB_DCC_CONTROL,
317 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
318 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
319
320 vgt_tess_distribution = S_028B50_ACCUM_ISOLINE(32) |
321 S_028B50_ACCUM_TRI(11) |
322 S_028B50_ACCUM_QUAD(11) |
323 S_028B50_DONUT_SPLIT(16);
324
325 if (physical_device->rad_info.family == CHIP_FIJI ||
326 physical_device->rad_info.family >= CHIP_POLARIS10)
327 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
328
329 radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION,
330 vgt_tess_distribution);
331 } else if (!physical_device->has_clear_state) {
332 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
333 radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
334 }
335
336 if (physical_device->rad_info.chip_class >= GFX9) {
337 unsigned num_se = physical_device->rad_info.max_se;
338 unsigned pc_lines = 0;
339
340 switch (physical_device->rad_info.family) {
341 case CHIP_VEGA10:
342 case CHIP_VEGA12:
343 pc_lines = 4096;
344 break;
345 case CHIP_RAVEN:
346 pc_lines = 1024;
347 break;
348 default:
349 assert(0);
350 }
351
352 radeon_set_context_reg(cs, R_028C48_PA_SC_BINNER_CNTL_1,
353 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines / (4 * num_se))) |
354 S_028C48_MAX_PRIM_PER_BATCH(1023));
355 radeon_set_context_reg(cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
356 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
357 radeon_set_uconfig_reg(cs, R_030968_VGT_INSTANCE_BASE_ID, 0);
358 }
359
360 unsigned tmp = (unsigned)(1.0 * 8.0);
361 radeon_set_context_reg_seq(cs, R_028A00_PA_SU_POINT_SIZE, 1);
362 radeon_emit(cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
363 radeon_set_context_reg_seq(cs, R_028A04_PA_SU_POINT_MINMAX, 1);
364 radeon_emit(cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
365 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2)));
366
367 if (!physical_device->has_clear_state) {
368 radeon_set_context_reg(cs, R_028004_DB_COUNT_CONTROL,
369 S_028004_ZPASS_INCREMENT_DISABLE(1));
370 }
371
372 /* Enable the Polaris small primitive filter control.
373 * XXX: There is possibly an issue when MSAA is off (see RadeonSI
374 * has_msaa_sample_loc_bug). But this doesn't seem to regress anything,
375 * and AMDVLK doesn't have a workaround as well.
376 */
377 if (physical_device->rad_info.family >= CHIP_POLARIS10) {
378 unsigned small_prim_filter_cntl =
379 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
380 /* Workaround for a hw line bug. */
381 S_028830_LINE_FILTER_DISABLE(physical_device->rad_info.family <= CHIP_POLARIS12);
382
383 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
384 small_prim_filter_cntl);
385 }
386
387 si_emit_compute(physical_device, cs);
388 }
389
390 void si_init_config(struct radv_cmd_buffer *cmd_buffer)
391 {
392 struct radv_physical_device *physical_device = cmd_buffer->device->physical_device;
393
394 si_emit_config(physical_device, cmd_buffer->cs);
395 }
396
397 void
398 cik_create_gfx_config(struct radv_device *device)
399 {
400 struct radeon_cmdbuf *cs = device->ws->cs_create(device->ws, RING_GFX);
401 if (!cs)
402 return;
403
404 si_emit_config(device->physical_device, cs);
405
406 while (cs->cdw & 7) {
407 if (device->physical_device->rad_info.gfx_ib_pad_with_type2)
408 radeon_emit(cs, 0x80000000);
409 else
410 radeon_emit(cs, 0xffff1000);
411 }
412
413 device->gfx_init = device->ws->buffer_create(device->ws,
414 cs->cdw * 4, 4096,
415 RADEON_DOMAIN_GTT,
416 RADEON_FLAG_CPU_ACCESS|
417 RADEON_FLAG_NO_INTERPROCESS_SHARING |
418 RADEON_FLAG_READ_ONLY);
419 if (!device->gfx_init)
420 goto fail;
421
422 void *map = device->ws->buffer_map(device->gfx_init);
423 if (!map) {
424 device->ws->buffer_destroy(device->gfx_init);
425 device->gfx_init = NULL;
426 goto fail;
427 }
428 memcpy(map, cs->buf, cs->cdw * 4);
429
430 device->ws->buffer_unmap(device->gfx_init);
431 device->gfx_init_size_dw = cs->cdw;
432 fail:
433 device->ws->cs_destroy(cs);
434 }
435
436 static void
437 get_viewport_xform(const VkViewport *viewport,
438 float scale[3], float translate[3])
439 {
440 float x = viewport->x;
441 float y = viewport->y;
442 float half_width = 0.5f * viewport->width;
443 float half_height = 0.5f * viewport->height;
444 double n = viewport->minDepth;
445 double f = viewport->maxDepth;
446
447 scale[0] = half_width;
448 translate[0] = half_width + x;
449 scale[1] = half_height;
450 translate[1] = half_height + y;
451
452 scale[2] = (f - n);
453 translate[2] = n;
454 }
455
456 void
457 si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
458 int count, const VkViewport *viewports)
459 {
460 int i;
461
462 assert(count);
463 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
464 first_vp * 4 * 6, count * 6);
465
466 for (i = 0; i < count; i++) {
467 float scale[3], translate[3];
468
469
470 get_viewport_xform(&viewports[i], scale, translate);
471 radeon_emit(cs, fui(scale[0]));
472 radeon_emit(cs, fui(translate[0]));
473 radeon_emit(cs, fui(scale[1]));
474 radeon_emit(cs, fui(translate[1]));
475 radeon_emit(cs, fui(scale[2]));
476 radeon_emit(cs, fui(translate[2]));
477 }
478
479 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 +
480 first_vp * 4 * 2, count * 2);
481 for (i = 0; i < count; i++) {
482 float zmin = MIN2(viewports[i].minDepth, viewports[i].maxDepth);
483 float zmax = MAX2(viewports[i].minDepth, viewports[i].maxDepth);
484 radeon_emit(cs, fui(zmin));
485 radeon_emit(cs, fui(zmax));
486 }
487 }
488
489 static VkRect2D si_scissor_from_viewport(const VkViewport *viewport)
490 {
491 float scale[3], translate[3];
492 VkRect2D rect;
493
494 get_viewport_xform(viewport, scale, translate);
495
496 rect.offset.x = translate[0] - fabs(scale[0]);
497 rect.offset.y = translate[1] - fabs(scale[1]);
498 rect.extent.width = ceilf(translate[0] + fabs(scale[0])) - rect.offset.x;
499 rect.extent.height = ceilf(translate[1] + fabs(scale[1])) - rect.offset.y;
500
501 return rect;
502 }
503
504 static VkRect2D si_intersect_scissor(const VkRect2D *a, const VkRect2D *b) {
505 VkRect2D ret;
506 ret.offset.x = MAX2(a->offset.x, b->offset.x);
507 ret.offset.y = MAX2(a->offset.y, b->offset.y);
508 ret.extent.width = MIN2(a->offset.x + a->extent.width,
509 b->offset.x + b->extent.width) - ret.offset.x;
510 ret.extent.height = MIN2(a->offset.y + a->extent.height,
511 b->offset.y + b->extent.height) - ret.offset.y;
512 return ret;
513 }
514
515 void
516 si_write_scissors(struct radeon_cmdbuf *cs, int first,
517 int count, const VkRect2D *scissors,
518 const VkViewport *viewports, bool can_use_guardband)
519 {
520 int i;
521 float scale[3], translate[3], guardband_x = INFINITY, guardband_y = INFINITY;
522 const float max_range = 32767.0f;
523 if (!count)
524 return;
525
526 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + first * 4 * 2, count * 2);
527 for (i = 0; i < count; i++) {
528 VkRect2D viewport_scissor = si_scissor_from_viewport(viewports + i);
529 VkRect2D scissor = si_intersect_scissor(&scissors[i], &viewport_scissor);
530
531 get_viewport_xform(viewports + i, scale, translate);
532 scale[0] = abs(scale[0]);
533 scale[1] = abs(scale[1]);
534
535 if (scale[0] < 0.5)
536 scale[0] = 0.5;
537 if (scale[1] < 0.5)
538 scale[1] = 0.5;
539
540 guardband_x = MIN2(guardband_x, (max_range - abs(translate[0])) / scale[0]);
541 guardband_y = MIN2(guardband_y, (max_range - abs(translate[1])) / scale[1]);
542
543 radeon_emit(cs, S_028250_TL_X(scissor.offset.x) |
544 S_028250_TL_Y(scissor.offset.y) |
545 S_028250_WINDOW_OFFSET_DISABLE(1));
546 radeon_emit(cs, S_028254_BR_X(scissor.offset.x + scissor.extent.width) |
547 S_028254_BR_Y(scissor.offset.y + scissor.extent.height));
548 }
549 if (!can_use_guardband) {
550 guardband_x = 1.0;
551 guardband_y = 1.0;
552 }
553
554 radeon_set_context_reg_seq(cs, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
555 radeon_emit(cs, fui(guardband_y));
556 radeon_emit(cs, fui(1.0));
557 radeon_emit(cs, fui(guardband_x));
558 radeon_emit(cs, fui(1.0));
559 }
560
561 static inline unsigned
562 radv_prims_for_vertices(struct radv_prim_vertex_count *info, unsigned num)
563 {
564 if (num == 0)
565 return 0;
566
567 if (info->incr == 0)
568 return 0;
569
570 if (num < info->min)
571 return 0;
572
573 return 1 + ((num - info->min) / info->incr);
574 }
575
576 uint32_t
577 si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
578 bool instanced_draw, bool indirect_draw,
579 uint32_t draw_vertex_count)
580 {
581 enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
582 enum radeon_family family = cmd_buffer->device->physical_device->rad_info.family;
583 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
584 const unsigned max_primgroup_in_wave = 2;
585 /* SWITCH_ON_EOP(0) is always preferable. */
586 bool wd_switch_on_eop = false;
587 bool ia_switch_on_eop = false;
588 bool ia_switch_on_eoi = false;
589 bool partial_vs_wave = false;
590 bool partial_es_wave = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.partial_es_wave;
591 bool multi_instances_smaller_than_primgroup;
592
593 multi_instances_smaller_than_primgroup = indirect_draw;
594 if (!multi_instances_smaller_than_primgroup && instanced_draw) {
595 uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
596 if (num_prims < cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.primgroup_size)
597 multi_instances_smaller_than_primgroup = true;
598 }
599
600 ia_switch_on_eoi = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.ia_switch_on_eoi;
601 partial_vs_wave = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.partial_vs_wave;
602
603 if (chip_class >= CIK) {
604 wd_switch_on_eop = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.wd_switch_on_eop;
605
606 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
607 * We don't know that for indirect drawing, so treat it as
608 * always problematic. */
609 if (family == CHIP_HAWAII &&
610 (instanced_draw || indirect_draw))
611 wd_switch_on_eop = true;
612
613 /* Performance recommendation for 4 SE Gfx7-8 parts if
614 * instances are smaller than a primgroup.
615 * Assume indirect draws always use small instances.
616 * This is needed for good VS wave utilization.
617 */
618 if (chip_class <= VI &&
619 info->max_se == 4 &&
620 multi_instances_smaller_than_primgroup)
621 wd_switch_on_eop = true;
622
623 /* Required on CIK and later. */
624 if (info->max_se > 2 && !wd_switch_on_eop)
625 ia_switch_on_eoi = true;
626
627 /* Required by Hawaii and, for some special cases, by VI. */
628 if (ia_switch_on_eoi &&
629 (family == CHIP_HAWAII ||
630 (chip_class == VI &&
631 /* max primgroup in wave is always 2 - leave this for documentation */
632 (radv_pipeline_has_gs(cmd_buffer->state.pipeline) || max_primgroup_in_wave != 2))))
633 partial_vs_wave = true;
634
635 /* Instancing bug on Bonaire. */
636 if (family == CHIP_BONAIRE && ia_switch_on_eoi &&
637 (instanced_draw || indirect_draw))
638 partial_vs_wave = true;
639
640 /* If the WD switch is false, the IA switch must be false too. */
641 assert(wd_switch_on_eop || !ia_switch_on_eop);
642 }
643 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
644 if (chip_class <= VI && ia_switch_on_eoi)
645 partial_es_wave = true;
646
647 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline)) {
648 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
649 * The hw doc says all multi-SE chips are affected, but amdgpu-pro Vulkan
650 * only applies it to Hawaii. Do what amdgpu-pro Vulkan does.
651 */
652 if (family == CHIP_HAWAII && ia_switch_on_eoi) {
653 bool set_vgt_flush = indirect_draw;
654 if (!set_vgt_flush && instanced_draw) {
655 uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
656 if (num_prims <= 1)
657 set_vgt_flush = true;
658 }
659 if (set_vgt_flush)
660 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
661 }
662 }
663
664 return cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.base |
665 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
666 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
667 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
668 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
669 S_028AA8_WD_SWITCH_ON_EOP(chip_class >= CIK ? wd_switch_on_eop : 0);
670
671 }
672
673 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
674 enum chip_class chip_class,
675 bool is_mec,
676 unsigned event, unsigned event_flags,
677 unsigned data_sel,
678 uint64_t va,
679 uint32_t old_fence,
680 uint32_t new_fence,
681 uint64_t gfx9_eop_bug_va)
682 {
683 unsigned op = EVENT_TYPE(event) |
684 EVENT_INDEX(5) |
685 event_flags;
686 unsigned is_gfx8_mec = is_mec && chip_class < GFX9;
687 unsigned sel = EOP_DATA_SEL(data_sel);
688
689 /* Wait for write confirmation before writing data, but don't send
690 * an interrupt. */
691 if (data_sel != EOP_DATA_SEL_DISCARD)
692 sel |= EOP_INT_SEL(EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM);
693
694 if (chip_class >= GFX9 || is_gfx8_mec) {
695 /* A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion
696 * counters) must immediately precede every timestamp event to
697 * prevent a GPU hang on GFX9.
698 */
699 if (chip_class == GFX9) {
700 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
701 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
702 radeon_emit(cs, gfx9_eop_bug_va);
703 radeon_emit(cs, gfx9_eop_bug_va >> 32);
704 }
705
706 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, is_gfx8_mec ? 5 : 6, false));
707 radeon_emit(cs, op);
708 radeon_emit(cs, sel);
709 radeon_emit(cs, va); /* address lo */
710 radeon_emit(cs, va >> 32); /* address hi */
711 radeon_emit(cs, new_fence); /* immediate data lo */
712 radeon_emit(cs, 0); /* immediate data hi */
713 if (!is_gfx8_mec)
714 radeon_emit(cs, 0); /* unused */
715 } else {
716 if (chip_class == CIK ||
717 chip_class == VI) {
718 /* Two EOP events are required to make all engines go idle
719 * (and optional cache flushes executed) before the timestamp
720 * is written.
721 */
722 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false));
723 radeon_emit(cs, op);
724 radeon_emit(cs, va);
725 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
726 radeon_emit(cs, old_fence); /* immediate data */
727 radeon_emit(cs, 0); /* unused */
728 }
729
730 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false));
731 radeon_emit(cs, op);
732 radeon_emit(cs, va);
733 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
734 radeon_emit(cs, new_fence); /* immediate data */
735 radeon_emit(cs, 0); /* unused */
736 }
737 }
738
739 void
740 si_emit_wait_fence(struct radeon_cmdbuf *cs,
741 uint64_t va, uint32_t ref,
742 uint32_t mask)
743 {
744 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, false));
745 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
746 radeon_emit(cs, va);
747 radeon_emit(cs, va >> 32);
748 radeon_emit(cs, ref); /* reference value */
749 radeon_emit(cs, mask); /* mask */
750 radeon_emit(cs, 4); /* poll interval */
751 }
752
753 static void
754 si_emit_acquire_mem(struct radeon_cmdbuf *cs,
755 bool is_mec,
756 bool is_gfx9,
757 unsigned cp_coher_cntl)
758 {
759 if (is_mec || is_gfx9) {
760 uint32_t hi_val = is_gfx9 ? 0xffffff : 0xff;
761 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, false) |
762 PKT3_SHADER_TYPE_S(is_mec));
763 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
764 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
765 radeon_emit(cs, hi_val); /* CP_COHER_SIZE_HI */
766 radeon_emit(cs, 0); /* CP_COHER_BASE */
767 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
768 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
769 } else {
770 /* ACQUIRE_MEM is only required on a compute ring. */
771 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, false));
772 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
773 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
774 radeon_emit(cs, 0); /* CP_COHER_BASE */
775 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
776 }
777 }
778
779 void
780 si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
781 enum chip_class chip_class,
782 uint32_t *flush_cnt,
783 uint64_t flush_va,
784 bool is_mec,
785 enum radv_cmd_flush_bits flush_bits,
786 uint64_t gfx9_eop_bug_va)
787 {
788 unsigned cp_coher_cntl = 0;
789 uint32_t flush_cb_db = flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
790 RADV_CMD_FLAG_FLUSH_AND_INV_DB);
791
792 if (flush_bits & RADV_CMD_FLAG_INV_ICACHE)
793 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
794 if (flush_bits & RADV_CMD_FLAG_INV_SMEM_L1)
795 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
796
797 if (chip_class <= VI) {
798 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
799 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
800 S_0085F0_CB0_DEST_BASE_ENA(1) |
801 S_0085F0_CB1_DEST_BASE_ENA(1) |
802 S_0085F0_CB2_DEST_BASE_ENA(1) |
803 S_0085F0_CB3_DEST_BASE_ENA(1) |
804 S_0085F0_CB4_DEST_BASE_ENA(1) |
805 S_0085F0_CB5_DEST_BASE_ENA(1) |
806 S_0085F0_CB6_DEST_BASE_ENA(1) |
807 S_0085F0_CB7_DEST_BASE_ENA(1);
808
809 /* Necessary for DCC */
810 if (chip_class >= VI) {
811 si_cs_emit_write_event_eop(cs,
812 chip_class,
813 is_mec,
814 V_028A90_FLUSH_AND_INV_CB_DATA_TS,
815 0,
816 EOP_DATA_SEL_DISCARD,
817 0, 0, 0,
818 gfx9_eop_bug_va);
819 }
820 }
821 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
822 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
823 S_0085F0_DB_DEST_BASE_ENA(1);
824 }
825 }
826
827 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) {
828 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
829 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
830 }
831
832 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) {
833 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
834 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
835 }
836
837 if (flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) {
838 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
839 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
840 } else if (flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) {
841 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
842 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
843 }
844
845 if (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) {
846 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
847 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
848 }
849
850 if (chip_class >= GFX9 && flush_cb_db) {
851 unsigned cb_db_event, tc_flags;
852
853 /* Set the CB/DB flush event. */
854 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
855
856 /* These are the only allowed combinations. If you need to
857 * do multiple operations at once, do them separately.
858 * All operations that invalidate L2 also seem to invalidate
859 * metadata. Volatile (VOL) and WC flushes are not listed here.
860 *
861 * TC | TC_WB = writeback & invalidate L2 & L1
862 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
863 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
864 * TC | TC_NC = invalidate L2 for MTYPE == NC
865 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
866 * TCL1 = invalidate L1
867 */
868 tc_flags = EVENT_TC_ACTION_ENA |
869 EVENT_TC_MD_ACTION_ENA;
870
871 /* Ideally flush TC together with CB/DB. */
872 if (flush_bits & RADV_CMD_FLAG_INV_GLOBAL_L2) {
873 /* Writeback and invalidate everything in L2 & L1. */
874 tc_flags = EVENT_TC_ACTION_ENA |
875 EVENT_TC_WB_ACTION_ENA;
876
877
878 /* Clear the flags. */
879 flush_bits &= ~(RADV_CMD_FLAG_INV_GLOBAL_L2 |
880 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 |
881 RADV_CMD_FLAG_INV_VMEM_L1);
882 }
883 assert(flush_cnt);
884 uint32_t old_fence = (*flush_cnt)++;
885
886 si_cs_emit_write_event_eop(cs, chip_class, false, cb_db_event, tc_flags,
887 EOP_DATA_SEL_VALUE_32BIT,
888 flush_va, old_fence, *flush_cnt,
889 gfx9_eop_bug_va);
890 si_emit_wait_fence(cs, flush_va, *flush_cnt, 0xffffffff);
891 }
892
893 /* VGT state sync */
894 if (flush_bits & RADV_CMD_FLAG_VGT_FLUSH) {
895 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
896 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
897 }
898
899 /* Make sure ME is idle (it executes most packets) before continuing.
900 * This prevents read-after-write hazards between PFP and ME.
901 */
902 if ((cp_coher_cntl ||
903 (flush_bits & (RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
904 RADV_CMD_FLAG_INV_VMEM_L1 |
905 RADV_CMD_FLAG_INV_GLOBAL_L2 |
906 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2))) &&
907 !is_mec) {
908 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
909 radeon_emit(cs, 0);
910 }
911
912 if ((flush_bits & RADV_CMD_FLAG_INV_GLOBAL_L2) ||
913 (chip_class <= CIK && (flush_bits & RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2))) {
914 si_emit_acquire_mem(cs, is_mec, chip_class >= GFX9,
915 cp_coher_cntl |
916 S_0085F0_TC_ACTION_ENA(1) |
917 S_0085F0_TCL1_ACTION_ENA(1) |
918 S_0301F0_TC_WB_ACTION_ENA(chip_class >= VI));
919 cp_coher_cntl = 0;
920 } else {
921 if(flush_bits & RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2) {
922 /* WB = write-back
923 * NC = apply to non-coherent MTYPEs
924 * (i.e. MTYPE <= 1, which is what we use everywhere)
925 *
926 * WB doesn't work without NC.
927 */
928 si_emit_acquire_mem(cs, is_mec,
929 chip_class >= GFX9,
930 cp_coher_cntl |
931 S_0301F0_TC_WB_ACTION_ENA(1) |
932 S_0301F0_TC_NC_ACTION_ENA(1));
933 cp_coher_cntl = 0;
934 }
935 if (flush_bits & RADV_CMD_FLAG_INV_VMEM_L1) {
936 si_emit_acquire_mem(cs, is_mec,
937 chip_class >= GFX9,
938 cp_coher_cntl |
939 S_0085F0_TCL1_ACTION_ENA(1));
940 cp_coher_cntl = 0;
941 }
942 }
943
944 /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
945 * Therefore, it should be last. Done in PFP.
946 */
947 if (cp_coher_cntl)
948 si_emit_acquire_mem(cs, is_mec, chip_class >= GFX9, cp_coher_cntl);
949
950 if (flush_bits & RADV_CMD_FLAG_START_PIPELINE_STATS) {
951 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
952 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
953 EVENT_INDEX(0));
954 } else if (flush_bits & RADV_CMD_FLAG_STOP_PIPELINE_STATS) {
955 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
956 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
957 EVENT_INDEX(0));
958 }
959 }
960
961 void
962 si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer)
963 {
964 bool is_compute = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
965
966 if (is_compute)
967 cmd_buffer->state.flush_bits &= ~(RADV_CMD_FLAG_FLUSH_AND_INV_CB |
968 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
969 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
970 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
971 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
972 RADV_CMD_FLAG_VS_PARTIAL_FLUSH |
973 RADV_CMD_FLAG_VGT_FLUSH |
974 RADV_CMD_FLAG_START_PIPELINE_STATS |
975 RADV_CMD_FLAG_STOP_PIPELINE_STATS);
976
977 if (!cmd_buffer->state.flush_bits)
978 return;
979
980 enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
981 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 128);
982
983 uint32_t *ptr = NULL;
984 uint64_t va = 0;
985 if (chip_class == GFX9) {
986 va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) + cmd_buffer->gfx9_fence_offset;
987 ptr = &cmd_buffer->gfx9_fence_idx;
988 }
989 si_cs_emit_cache_flush(cmd_buffer->cs,
990 cmd_buffer->device->physical_device->rad_info.chip_class,
991 ptr, va,
992 radv_cmd_buffer_uses_mec(cmd_buffer),
993 cmd_buffer->state.flush_bits,
994 cmd_buffer->gfx9_eop_bug_va);
995
996
997 if (unlikely(cmd_buffer->device->trace_bo))
998 radv_cmd_buffer_trace_emit(cmd_buffer);
999
1000 cmd_buffer->state.flush_bits = 0;
1001 }
1002
1003 /* sets the CP predication state using a boolean stored at va */
1004 void
1005 si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
1006 bool inverted, uint64_t va)
1007 {
1008 uint32_t op = 0;
1009
1010 if (va) {
1011 op = PRED_OP(PREDICATION_OP_BOOL64);
1012
1013 /* By default, our internal rendering commands are discarded
1014 * only if the predicate is non-zero (ie. DRAW_VISIBLE). But
1015 * VK_EXT_conditional_rendering also allows to discard commands
1016 * when the predicate is zero, which means we have to use a
1017 * different flag.
1018 */
1019 op |= inverted ? PREDICATION_DRAW_VISIBLE :
1020 PREDICATION_DRAW_NOT_VISIBLE;
1021 }
1022 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1023 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 2, 0));
1024 radeon_emit(cmd_buffer->cs, op);
1025 radeon_emit(cmd_buffer->cs, va);
1026 radeon_emit(cmd_buffer->cs, va >> 32);
1027 } else {
1028 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
1029 radeon_emit(cmd_buffer->cs, va);
1030 radeon_emit(cmd_buffer->cs, op | ((va >> 32) & 0xFF));
1031 }
1032 }
1033
1034 /* Set this if you want the 3D engine to wait until CP DMA is done.
1035 * It should be set on the last CP DMA packet. */
1036 #define CP_DMA_SYNC (1 << 0)
1037
1038 /* Set this if the source data was used as a destination in a previous CP DMA
1039 * packet. It's for preventing a read-after-write (RAW) hazard between two
1040 * CP DMA packets. */
1041 #define CP_DMA_RAW_WAIT (1 << 1)
1042 #define CP_DMA_USE_L2 (1 << 2)
1043 #define CP_DMA_CLEAR (1 << 3)
1044
1045 /* Alignment for optimal performance. */
1046 #define SI_CPDMA_ALIGNMENT 32
1047
1048 /* The max number of bytes that can be copied per packet. */
1049 static inline unsigned cp_dma_max_byte_count(struct radv_cmd_buffer *cmd_buffer)
1050 {
1051 unsigned max = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 ?
1052 S_414_BYTE_COUNT_GFX9(~0u) :
1053 S_414_BYTE_COUNT_GFX6(~0u);
1054
1055 /* make it aligned for optimal performance */
1056 return max & ~(SI_CPDMA_ALIGNMENT - 1);
1057 }
1058
1059 /* Emit a CP DMA packet to do a copy from one buffer to another, or to clear
1060 * a buffer. The size must fit in bits [20:0]. If CP_DMA_CLEAR is set, src_va is a 32-bit
1061 * clear value.
1062 */
1063 static void si_emit_cp_dma(struct radv_cmd_buffer *cmd_buffer,
1064 uint64_t dst_va, uint64_t src_va,
1065 unsigned size, unsigned flags)
1066 {
1067 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1068 uint32_t header = 0, command = 0;
1069
1070 assert(size <= cp_dma_max_byte_count(cmd_buffer));
1071
1072 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9);
1073 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1074 command |= S_414_BYTE_COUNT_GFX9(size);
1075 else
1076 command |= S_414_BYTE_COUNT_GFX6(size);
1077
1078 /* Sync flags. */
1079 if (flags & CP_DMA_SYNC)
1080 header |= S_411_CP_SYNC(1);
1081 else {
1082 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1083 command |= S_414_DISABLE_WR_CONFIRM_GFX9(1);
1084 else
1085 command |= S_414_DISABLE_WR_CONFIRM_GFX6(1);
1086 }
1087
1088 if (flags & CP_DMA_RAW_WAIT)
1089 command |= S_414_RAW_WAIT(1);
1090
1091 /* Src and dst flags. */
1092 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
1093 !(flags & CP_DMA_CLEAR) &&
1094 src_va == dst_va)
1095 header |= S_411_DST_SEL(V_411_NOWHERE); /* prefetch only */
1096 else if (flags & CP_DMA_USE_L2)
1097 header |= S_411_DST_SEL(V_411_DST_ADDR_TC_L2);
1098
1099 if (flags & CP_DMA_CLEAR)
1100 header |= S_411_SRC_SEL(V_411_DATA);
1101 else if (flags & CP_DMA_USE_L2)
1102 header |= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2);
1103
1104 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1105 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, cmd_buffer->state.predicating));
1106 radeon_emit(cs, header);
1107 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1108 radeon_emit(cs, src_va >> 32); /* SRC_ADDR_HI [31:0] */
1109 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1110 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [31:0] */
1111 radeon_emit(cs, command);
1112 } else {
1113 assert(!(flags & CP_DMA_USE_L2));
1114 header |= S_411_SRC_ADDR_HI(src_va >> 32);
1115 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, cmd_buffer->state.predicating));
1116 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1117 radeon_emit(cs, header); /* SRC_ADDR_HI [15:0] + flags. */
1118 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1119 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
1120 radeon_emit(cs, command);
1121 }
1122
1123 /* CP DMA is executed in ME, but index buffers are read by PFP.
1124 * This ensures that ME (CP DMA) is idle before PFP starts fetching
1125 * indices. If we wanted to execute CP DMA in PFP, this packet
1126 * should precede it.
1127 */
1128 if (flags & CP_DMA_SYNC) {
1129 if (cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
1130 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1131 radeon_emit(cs, 0);
1132 }
1133
1134 /* CP will see the sync flag and wait for all DMAs to complete. */
1135 cmd_buffer->state.dma_is_busy = false;
1136 }
1137
1138 if (unlikely(cmd_buffer->device->trace_bo))
1139 radv_cmd_buffer_trace_emit(cmd_buffer);
1140 }
1141
1142 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1143 unsigned size)
1144 {
1145 uint64_t aligned_va = va & ~(SI_CPDMA_ALIGNMENT - 1);
1146 uint64_t aligned_size = ((va + size + SI_CPDMA_ALIGNMENT -1) & ~(SI_CPDMA_ALIGNMENT - 1)) - aligned_va;
1147
1148 si_emit_cp_dma(cmd_buffer, aligned_va, aligned_va,
1149 aligned_size, CP_DMA_USE_L2);
1150 }
1151
1152 static void si_cp_dma_prepare(struct radv_cmd_buffer *cmd_buffer, uint64_t byte_count,
1153 uint64_t remaining_size, unsigned *flags)
1154 {
1155
1156 /* Flush the caches for the first copy only.
1157 * Also wait for the previous CP DMA operations.
1158 */
1159 if (cmd_buffer->state.flush_bits) {
1160 si_emit_cache_flush(cmd_buffer);
1161 *flags |= CP_DMA_RAW_WAIT;
1162 }
1163
1164 /* Do the synchronization after the last dma, so that all data
1165 * is written to memory.
1166 */
1167 if (byte_count == remaining_size)
1168 *flags |= CP_DMA_SYNC;
1169 }
1170
1171 static void si_cp_dma_realign_engine(struct radv_cmd_buffer *cmd_buffer, unsigned size)
1172 {
1173 uint64_t va;
1174 uint32_t offset;
1175 unsigned dma_flags = 0;
1176 unsigned buf_size = SI_CPDMA_ALIGNMENT * 2;
1177 void *ptr;
1178
1179 assert(size < SI_CPDMA_ALIGNMENT);
1180
1181 radv_cmd_buffer_upload_alloc(cmd_buffer, buf_size, SI_CPDMA_ALIGNMENT, &offset, &ptr);
1182
1183 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1184 va += offset;
1185
1186 si_cp_dma_prepare(cmd_buffer, size, size, &dma_flags);
1187
1188 si_emit_cp_dma(cmd_buffer, va, va + SI_CPDMA_ALIGNMENT, size,
1189 dma_flags);
1190 }
1191
1192 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1193 uint64_t src_va, uint64_t dest_va,
1194 uint64_t size)
1195 {
1196 uint64_t main_src_va, main_dest_va;
1197 uint64_t skipped_size = 0, realign_size = 0;
1198
1199 /* Assume that we are not going to sync after the last DMA operation. */
1200 cmd_buffer->state.dma_is_busy = true;
1201
1202 if (cmd_buffer->device->physical_device->rad_info.family <= CHIP_CARRIZO ||
1203 cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY) {
1204 /* If the size is not aligned, we must add a dummy copy at the end
1205 * just to align the internal counter. Otherwise, the DMA engine
1206 * would slow down by an order of magnitude for following copies.
1207 */
1208 if (size % SI_CPDMA_ALIGNMENT)
1209 realign_size = SI_CPDMA_ALIGNMENT - (size % SI_CPDMA_ALIGNMENT);
1210
1211 /* If the copy begins unaligned, we must start copying from the next
1212 * aligned block and the skipped part should be copied after everything
1213 * else has been copied. Only the src alignment matters, not dst.
1214 */
1215 if (src_va % SI_CPDMA_ALIGNMENT) {
1216 skipped_size = SI_CPDMA_ALIGNMENT - (src_va % SI_CPDMA_ALIGNMENT);
1217 /* The main part will be skipped if the size is too small. */
1218 skipped_size = MIN2(skipped_size, size);
1219 size -= skipped_size;
1220 }
1221 }
1222 main_src_va = src_va + skipped_size;
1223 main_dest_va = dest_va + skipped_size;
1224
1225 while (size) {
1226 unsigned dma_flags = 0;
1227 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1228
1229 si_cp_dma_prepare(cmd_buffer, byte_count,
1230 size + skipped_size + realign_size,
1231 &dma_flags);
1232
1233 si_emit_cp_dma(cmd_buffer, main_dest_va, main_src_va,
1234 byte_count, dma_flags);
1235
1236 size -= byte_count;
1237 main_src_va += byte_count;
1238 main_dest_va += byte_count;
1239 }
1240
1241 if (skipped_size) {
1242 unsigned dma_flags = 0;
1243
1244 si_cp_dma_prepare(cmd_buffer, skipped_size,
1245 size + skipped_size + realign_size,
1246 &dma_flags);
1247
1248 si_emit_cp_dma(cmd_buffer, dest_va, src_va,
1249 skipped_size, dma_flags);
1250 }
1251 if (realign_size)
1252 si_cp_dma_realign_engine(cmd_buffer, realign_size);
1253 }
1254
1255 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1256 uint64_t size, unsigned value)
1257 {
1258
1259 if (!size)
1260 return;
1261
1262 assert(va % 4 == 0 && size % 4 == 0);
1263
1264 /* Assume that we are not going to sync after the last DMA operation. */
1265 cmd_buffer->state.dma_is_busy = true;
1266
1267 while (size) {
1268 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1269 unsigned dma_flags = CP_DMA_CLEAR;
1270
1271 si_cp_dma_prepare(cmd_buffer, byte_count, size, &dma_flags);
1272
1273 /* Emit the clear packet. */
1274 si_emit_cp_dma(cmd_buffer, va, value, byte_count,
1275 dma_flags);
1276
1277 size -= byte_count;
1278 va += byte_count;
1279 }
1280 }
1281
1282 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer)
1283 {
1284 if (cmd_buffer->device->physical_device->rad_info.chip_class < CIK)
1285 return;
1286
1287 if (!cmd_buffer->state.dma_is_busy)
1288 return;
1289
1290 /* Issue a dummy DMA that copies zero bytes.
1291 *
1292 * The DMA engine will see that there's no work to do and skip this
1293 * DMA request, however, the CP will see the sync flag and still wait
1294 * for all DMAs to complete.
1295 */
1296 si_emit_cp_dma(cmd_buffer, 0, 0, 0, CP_DMA_SYNC);
1297
1298 cmd_buffer->state.dma_is_busy = false;
1299 }
1300
1301 /* For MSAA sample positions. */
1302 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1303 (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) | \
1304 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
1305 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
1306 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
1307
1308
1309 /* 2xMSAA
1310 * There are two locations (4, 4), (-4, -4). */
1311 const uint32_t eg_sample_locs_2x[4] = {
1312 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1313 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1314 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1315 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1316 };
1317 const unsigned eg_max_dist_2x = 4;
1318 /* 4xMSAA
1319 * There are 4 locations: (-2, 6), (6, -2), (-6, 2), (2, 6). */
1320 const uint32_t eg_sample_locs_4x[4] = {
1321 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1322 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1323 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1324 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1325 };
1326 const unsigned eg_max_dist_4x = 6;
1327
1328 /* Cayman 8xMSAA */
1329 static const uint32_t cm_sample_locs_8x[] = {
1330 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1331 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1332 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1333 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1334 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1335 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1336 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1337 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1338 };
1339 static const unsigned cm_max_dist_8x = 8;
1340 /* Cayman 16xMSAA */
1341 static const uint32_t cm_sample_locs_16x[] = {
1342 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1343 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1344 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1345 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1346 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1347 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1348 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1349 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1350 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1351 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1352 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1353 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1354 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1355 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1356 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1357 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1358 };
1359 static const unsigned cm_max_dist_16x = 8;
1360
1361 unsigned radv_cayman_get_maxdist(int log_samples)
1362 {
1363 unsigned max_dist[] = {
1364 0,
1365 eg_max_dist_2x,
1366 eg_max_dist_4x,
1367 cm_max_dist_8x,
1368 cm_max_dist_16x
1369 };
1370 return max_dist[log_samples];
1371 }
1372
1373 void radv_cayman_emit_msaa_sample_locs(struct radeon_cmdbuf *cs, int nr_samples)
1374 {
1375 switch (nr_samples) {
1376 default:
1377 case 1:
1378 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0);
1379 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0);
1380 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0);
1381 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0);
1382 break;
1383 case 2:
1384 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_2x[0]);
1385 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_2x[1]);
1386 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_2x[2]);
1387 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_2x[3]);
1388 break;
1389 case 4:
1390 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_4x[0]);
1391 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_4x[1]);
1392 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_4x[2]);
1393 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_4x[3]);
1394 break;
1395 case 8:
1396 radeon_set_context_reg_seq(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
1397 radeon_emit(cs, cm_sample_locs_8x[0]);
1398 radeon_emit(cs, cm_sample_locs_8x[4]);
1399 radeon_emit(cs, 0);
1400 radeon_emit(cs, 0);
1401 radeon_emit(cs, cm_sample_locs_8x[1]);
1402 radeon_emit(cs, cm_sample_locs_8x[5]);
1403 radeon_emit(cs, 0);
1404 radeon_emit(cs, 0);
1405 radeon_emit(cs, cm_sample_locs_8x[2]);
1406 radeon_emit(cs, cm_sample_locs_8x[6]);
1407 radeon_emit(cs, 0);
1408 radeon_emit(cs, 0);
1409 radeon_emit(cs, cm_sample_locs_8x[3]);
1410 radeon_emit(cs, cm_sample_locs_8x[7]);
1411 break;
1412 case 16:
1413 radeon_set_context_reg_seq(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 16);
1414 radeon_emit(cs, cm_sample_locs_16x[0]);
1415 radeon_emit(cs, cm_sample_locs_16x[4]);
1416 radeon_emit(cs, cm_sample_locs_16x[8]);
1417 radeon_emit(cs, cm_sample_locs_16x[12]);
1418 radeon_emit(cs, cm_sample_locs_16x[1]);
1419 radeon_emit(cs, cm_sample_locs_16x[5]);
1420 radeon_emit(cs, cm_sample_locs_16x[9]);
1421 radeon_emit(cs, cm_sample_locs_16x[13]);
1422 radeon_emit(cs, cm_sample_locs_16x[2]);
1423 radeon_emit(cs, cm_sample_locs_16x[6]);
1424 radeon_emit(cs, cm_sample_locs_16x[10]);
1425 radeon_emit(cs, cm_sample_locs_16x[14]);
1426 radeon_emit(cs, cm_sample_locs_16x[3]);
1427 radeon_emit(cs, cm_sample_locs_16x[7]);
1428 radeon_emit(cs, cm_sample_locs_16x[11]);
1429 radeon_emit(cs, cm_sample_locs_16x[15]);
1430 break;
1431 }
1432 }
1433
1434 static void radv_cayman_get_sample_position(struct radv_device *device,
1435 unsigned sample_count,
1436 unsigned sample_index, float *out_value)
1437 {
1438 int offset, index;
1439 struct {
1440 int idx:4;
1441 } val;
1442 switch (sample_count) {
1443 case 1:
1444 default:
1445 out_value[0] = out_value[1] = 0.5;
1446 break;
1447 case 2:
1448 offset = 4 * (sample_index * 2);
1449 val.idx = (eg_sample_locs_2x[0] >> offset) & 0xf;
1450 out_value[0] = (float)(val.idx + 8) / 16.0f;
1451 val.idx = (eg_sample_locs_2x[0] >> (offset + 4)) & 0xf;
1452 out_value[1] = (float)(val.idx + 8) / 16.0f;
1453 break;
1454 case 4:
1455 offset = 4 * (sample_index * 2);
1456 val.idx = (eg_sample_locs_4x[0] >> offset) & 0xf;
1457 out_value[0] = (float)(val.idx + 8) / 16.0f;
1458 val.idx = (eg_sample_locs_4x[0] >> (offset + 4)) & 0xf;
1459 out_value[1] = (float)(val.idx + 8) / 16.0f;
1460 break;
1461 case 8:
1462 offset = 4 * (sample_index % 4 * 2);
1463 index = (sample_index / 4) * 4;
1464 val.idx = (cm_sample_locs_8x[index] >> offset) & 0xf;
1465 out_value[0] = (float)(val.idx + 8) / 16.0f;
1466 val.idx = (cm_sample_locs_8x[index] >> (offset + 4)) & 0xf;
1467 out_value[1] = (float)(val.idx + 8) / 16.0f;
1468 break;
1469 case 16:
1470 offset = 4 * (sample_index % 4 * 2);
1471 index = (sample_index / 4) * 4;
1472 val.idx = (cm_sample_locs_16x[index] >> offset) & 0xf;
1473 out_value[0] = (float)(val.idx + 8) / 16.0f;
1474 val.idx = (cm_sample_locs_16x[index] >> (offset + 4)) & 0xf;
1475 out_value[1] = (float)(val.idx + 8) / 16.0f;
1476 break;
1477 }
1478 }
1479
1480 void radv_device_init_msaa(struct radv_device *device)
1481 {
1482 int i;
1483 radv_cayman_get_sample_position(device, 1, 0, device->sample_locations_1x[0]);
1484
1485 for (i = 0; i < 2; i++)
1486 radv_cayman_get_sample_position(device, 2, i, device->sample_locations_2x[i]);
1487 for (i = 0; i < 4; i++)
1488 radv_cayman_get_sample_position(device, 4, i, device->sample_locations_4x[i]);
1489 for (i = 0; i < 8; i++)
1490 radv_cayman_get_sample_position(device, 8, i, device->sample_locations_8x[i]);
1491 for (i = 0; i < 16; i++)
1492 radv_cayman_get_sample_position(device, 16, i, device->sample_locations_16x[i]);
1493 }