projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv: compute prim_vertex_count at draw time
[mesa.git] / src / amd / vulkan / si_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based on si_state.c
6 * Copyright © 2015 Advanced Micro Devices, Inc.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 /* command buffer handling for AMD GCN */
29
30 #include "radv_private.h"
31 #include "radv_shader.h"
32 #include "radv_cs.h"
33 #include "sid.h"
34 #include "radv_util.h"
35
36 static void
37 si_write_harvested_raster_configs(struct radv_physical_device *physical_device,
38 struct radeon_cmdbuf *cs,
39 unsigned raster_config,
40 unsigned raster_config_1)
41 {
42 unsigned num_se = MAX2(physical_device->rad_info.max_se, 1);
43 unsigned raster_config_se[4];
44 unsigned se;
45
46 ac_get_harvested_configs(&physical_device->rad_info,
47 raster_config,
48 &raster_config_1,
49 raster_config_se);
50
51 for (se = 0; se < num_se; se++) {
52 /* GRBM_GFX_INDEX has a different offset on GFX6 and GFX7+ */
53 if (physical_device->rad_info.chip_class < GFX7)
54 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
55 S_00802C_SE_INDEX(se) |
56 S_00802C_SH_BROADCAST_WRITES(1) |
57 S_00802C_INSTANCE_BROADCAST_WRITES(1));
58 else
59 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
60 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
61 S_030800_INSTANCE_BROADCAST_WRITES(1));
62 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
63 }
64
65 /* GRBM_GFX_INDEX has a different offset on GFX6 and GFX7+ */
66 if (physical_device->rad_info.chip_class < GFX7)
67 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
68 S_00802C_SE_BROADCAST_WRITES(1) |
69 S_00802C_SH_BROADCAST_WRITES(1) |
70 S_00802C_INSTANCE_BROADCAST_WRITES(1));
71 else
72 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
73 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
74 S_030800_INSTANCE_BROADCAST_WRITES(1));
75
76 if (physical_device->rad_info.chip_class >= GFX7)
77 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
78 }
79
80 void
81 si_emit_compute(struct radv_physical_device *physical_device,
82 struct radeon_cmdbuf *cs)
83 {
84 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
85 radeon_emit(cs, 0);
86 radeon_emit(cs, 0);
87 radeon_emit(cs, 0);
88
89 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
90 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1,
91 * renamed COMPUTE_DESTINATION_EN_SEn on gfx10. */
92 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
93 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
94
95 if (physical_device->rad_info.chip_class >= GFX7) {
96 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
97 radeon_set_sh_reg_seq(cs,
98 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
99 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
100 S_00B858_SH1_CU_EN(0xffff));
101 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
102 S_00B858_SH1_CU_EN(0xffff));
103 }
104
105 if (physical_device->rad_info.chip_class >= GFX10)
106 radeon_set_sh_reg(cs, R_00B8A0_COMPUTE_PGM_RSRC3, 0);
107
108 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
109 * and is now per pipe, so it should be handled in the
110 * kernel if we want to use something other than the default value,
111 * which is now 0x22f.
112 */
113 if (physical_device->rad_info.chip_class <= GFX6) {
114 /* XXX: This should be:
115 * (number of compute units) * 4 * (waves per simd) - 1 */
116
117 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
118 0x190 /* Default value */);
119 }
120 }
121
122 /* 12.4 fixed-point */
123 static unsigned radv_pack_float_12p4(float x)
124 {
125 return x <= 0 ? 0 :
126 x >= 4096 ? 0xffff : x * 16;
127 }
128
129 static void
130 si_set_raster_config(struct radv_physical_device *physical_device,
131 struct radeon_cmdbuf *cs)
132 {
133 unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
134 unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
135 unsigned raster_config, raster_config_1;
136
137 ac_get_raster_config(&physical_device->rad_info,
138 &raster_config,
139 &raster_config_1, NULL);
140
141 /* Always use the default config when all backends are enabled
142 * (or when we failed to determine the enabled backends).
143 */
144 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
145 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG,
146 raster_config);
147 if (physical_device->rad_info.chip_class >= GFX7)
148 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1,
149 raster_config_1);
150 } else {
151 si_write_harvested_raster_configs(physical_device, cs,
152 raster_config,
153 raster_config_1);
154 }
155 }
156
157 void
158 si_emit_graphics(struct radv_device *device,
159 struct radeon_cmdbuf *cs)
160 {
161 struct radv_physical_device *physical_device = device->physical_device;
162
163 bool has_clear_state = physical_device->rad_info.has_clear_state;
164 int i;
165
166 radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
167 radeon_emit(cs, CC0_UPDATE_LOAD_ENABLES(1));
168 radeon_emit(cs, CC1_UPDATE_SHADOW_ENABLES(1));
169
170 if (has_clear_state) {
171 radeon_emit(cs, PKT3(PKT3_CLEAR_STATE, 0, 0));
172 radeon_emit(cs, 0);
173 }
174
175 if (physical_device->rad_info.chip_class <= GFX8)
176 si_set_raster_config(physical_device, cs);
177
178 radeon_set_context_reg(cs, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
179 if (!has_clear_state)
180 radeon_set_context_reg(cs, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
181
182 /* FIXME calculate these values somehow ??? */
183 if (physical_device->rad_info.chip_class <= GFX8) {
184 radeon_set_context_reg(cs, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
185 radeon_set_context_reg(cs, R_028A58_VGT_ES_PER_GS, 0x40);
186 }
187
188 if (!has_clear_state) {
189 radeon_set_context_reg(cs, R_028A5C_VGT_GS_PER_VS, 0x2);
190 radeon_set_context_reg(cs, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
191 radeon_set_context_reg(cs, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
192 }
193
194 if (physical_device->rad_info.chip_class <= GFX9)
195 radeon_set_context_reg(cs, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
196 if (!has_clear_state)
197 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, 0x0);
198 if (physical_device->rad_info.chip_class < GFX7)
199 radeon_set_config_reg(cs, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
200 S_008A14_CLIP_VTX_REORDER_ENA(1));
201
202 if (!has_clear_state)
203 radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
204
205 /* CLEAR_STATE doesn't clear these correctly on certain generations.
206 * I don't know why. Deduced by trial and error.
207 */
208 if (physical_device->rad_info.chip_class <= GFX7 || !has_clear_state) {
209 radeon_set_context_reg(cs, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
210 radeon_set_context_reg(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL,
211 S_028204_WINDOW_OFFSET_DISABLE(1));
212 radeon_set_context_reg(cs, R_028240_PA_SC_GENERIC_SCISSOR_TL,
213 S_028240_WINDOW_OFFSET_DISABLE(1));
214 radeon_set_context_reg(cs, R_028244_PA_SC_GENERIC_SCISSOR_BR,
215 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
216 radeon_set_context_reg(cs, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
217 radeon_set_context_reg(cs, R_028034_PA_SC_SCREEN_SCISSOR_BR,
218 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
219 }
220
221 if (!has_clear_state) {
222 for (i = 0; i < 16; i++) {
223 radeon_set_context_reg(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
224 radeon_set_context_reg(cs, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
225 }
226 }
227
228 if (!has_clear_state) {
229 radeon_set_context_reg(cs, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
230 radeon_set_context_reg(cs, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
231 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on GFX6 */
232 radeon_set_context_reg(cs, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
233 radeon_set_context_reg(cs, R_028820_PA_CL_NANINF_CNTL, 0);
234 radeon_set_context_reg(cs, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
235 radeon_set_context_reg(cs, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
236 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
237 }
238
239 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE,
240 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
241 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
242
243 if (physical_device->rad_info.chip_class >= GFX10) {
244 radeon_set_context_reg(cs, R_028A98_VGT_DRAW_PAYLOAD_CNTL, 0);
245 radeon_set_uconfig_reg(cs, R_030964_GE_MAX_VTX_INDX, ~0);
246 radeon_set_uconfig_reg(cs, R_030924_GE_MIN_VTX_INDX, 0);
247 radeon_set_uconfig_reg(cs, R_030928_GE_INDX_OFFSET, 0);
248 radeon_set_uconfig_reg(cs, R_03097C_GE_STEREO_CNTL, 0);
249 radeon_set_uconfig_reg(cs, R_030988_GE_USER_VGPR_EN, 0);
250 } else if (physical_device->rad_info.chip_class == GFX9) {
251 radeon_set_uconfig_reg(cs, R_030920_VGT_MAX_VTX_INDX, ~0);
252 radeon_set_uconfig_reg(cs, R_030924_VGT_MIN_VTX_INDX, 0);
253 radeon_set_uconfig_reg(cs, R_030928_VGT_INDX_OFFSET, 0);
254 } else {
255 /* These registers, when written, also overwrite the
256 * CLEAR_STATE context, so we can't rely on CLEAR_STATE setting
257 * them. It would be an issue if there was another UMD
258 * changing them.
259 */
260 radeon_set_context_reg(cs, R_028400_VGT_MAX_VTX_INDX, ~0);
261 radeon_set_context_reg(cs, R_028404_VGT_MIN_VTX_INDX, 0);
262 radeon_set_context_reg(cs, R_028408_VGT_INDX_OFFSET, 0);
263 }
264
265 if (physical_device->rad_info.chip_class >= GFX7) {
266 if (physical_device->rad_info.chip_class >= GFX10) {
267 /* Logical CUs 16 - 31 */
268 radeon_set_sh_reg_idx(physical_device, cs, R_00B404_SPI_SHADER_PGM_RSRC4_HS,
269 3, S_00B404_CU_EN(0xffff));
270 radeon_set_sh_reg_idx(physical_device, cs, R_00B104_SPI_SHADER_PGM_RSRC4_VS,
271 3, S_00B104_CU_EN(0xffff));
272 radeon_set_sh_reg_idx(physical_device, cs, R_00B004_SPI_SHADER_PGM_RSRC4_PS,
273 3, S_00B004_CU_EN(0xffff));
274 }
275
276 if (physical_device->rad_info.chip_class >= GFX9) {
277 radeon_set_sh_reg_idx(physical_device, cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
278 3, S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
279 } else {
280 radeon_set_sh_reg(cs, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
281 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
282 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
283 S_00B41C_WAVE_LIMIT(0x3F));
284 radeon_set_sh_reg(cs, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
285 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
286 /* If this is 0, Bonaire can hang even if GS isn't being used.
287 * Other chips are unaffected. These are suboptimal values,
288 * but we don't use on-chip GS.
289 */
290 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL,
291 S_028A44_ES_VERTS_PER_SUBGRP(64) |
292 S_028A44_GS_PRIMS_PER_SUBGRP(4));
293 }
294
295 /* Compute LATE_ALLOC_VS.LIMIT. */
296 unsigned num_cu_per_sh = physical_device->rad_info.min_good_cu_per_sa;
297 unsigned late_alloc_wave64 = 0; /* The limit is per SA. */
298 unsigned late_alloc_wave64_gs = 0;
299 unsigned cu_mask_vs = 0xffff;
300 unsigned cu_mask_gs = 0xffff;
301
302 if (physical_device->rad_info.chip_class >= GFX10) {
303 /* For Wave32, the hw will launch twice the number of late
304 * alloc waves, so 1 == 2x wave32.
305 */
306 if (!physical_device->rad_info.use_late_alloc) {
307 late_alloc_wave64 = 0;
308 } else if (num_cu_per_sh <= 6) {
309 late_alloc_wave64 = num_cu_per_sh - 2;
310 } else {
311 late_alloc_wave64 = (num_cu_per_sh - 2) * 4;
312
313 /* CU2 & CU3 disabled because of the dual CU design */
314 cu_mask_vs = 0xfff3;
315 cu_mask_gs = 0xfff3; /* NGG only */
316 }
317
318 late_alloc_wave64_gs = late_alloc_wave64;
319
320 /* Don't use late alloc for NGG on Navi14 due to a hw
321 * bug. If NGG is never used, enable all CUs.
322 */
323 if (!physical_device->use_ngg ||
324 physical_device->rad_info.family == CHIP_NAVI14) {
325 late_alloc_wave64_gs = 0;
326 cu_mask_gs = 0xffff;
327 }
328 } else {
329 if (!physical_device->rad_info.use_late_alloc) {
330 late_alloc_wave64 = 0;
331 } else if (num_cu_per_sh <= 4) {
332 /* Too few available compute units per SA.
333 * Disallowing VS to run on one CU could hurt
334 * us more than late VS allocation would help.
335 *
336 * 2 is the highest safe number that allows us
337 * to keep all CUs enabled.
338 */
339 late_alloc_wave64 = 2;
340 } else {
341 /* This is a good initial value, allowing 1
342 * late_alloc wave per SIMD on num_cu - 2.
343 */
344 late_alloc_wave64 = (num_cu_per_sh - 2) * 4;
345 }
346
347 if (late_alloc_wave64 > 2)
348 cu_mask_vs = 0xfffe; /* 1 CU disabled */
349 }
350
351 radeon_set_sh_reg_idx(physical_device, cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
352 3, S_00B118_CU_EN(cu_mask_vs) |
353 S_00B118_WAVE_LIMIT(0x3F));
354 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
355 S_00B11C_LIMIT(late_alloc_wave64));
356
357 radeon_set_sh_reg_idx(physical_device, cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
358 3, S_00B21C_CU_EN(cu_mask_gs) | S_00B21C_WAVE_LIMIT(0x3F));
359
360 if (physical_device->rad_info.chip_class >= GFX10) {
361 radeon_set_sh_reg_idx(physical_device, cs, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
362 3, S_00B204_CU_EN(0xffff) |
363 S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(late_alloc_wave64_gs));
364 }
365
366 radeon_set_sh_reg_idx(physical_device, cs, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
367 3, S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
368 }
369
370 if (physical_device->rad_info.chip_class >= GFX10) {
371 /* Break up a pixel wave if it contains deallocs for more than
372 * half the parameter cache.
373 *
374 * To avoid a deadlock where pixel waves aren't launched
375 * because they're waiting for more pixels while the frontend
376 * is stuck waiting for PC space, the maximum allowed value is
377 * the size of the PC minus the largest possible allocation for
378 * a single primitive shader subgroup.
379 */
380 radeon_set_context_reg(cs, R_028C50_PA_SC_NGG_MODE_CNTL,
381 S_028C50_MAX_DEALLOCS_IN_WAVE(512));
382 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
383
384 /* Enable CMASK/FMASK/HTILE/DCC caching in L2 for small chips. */
385 unsigned meta_write_policy, meta_read_policy;
386
387 /* TODO: investigate whether LRU improves performance on other chips too */
388 if (physical_device->rad_info.num_render_backends <= 4) {
389 meta_write_policy = V_02807C_CACHE_LRU_WR; /* cache writes */
390 meta_read_policy = V_02807C_CACHE_LRU_RD; /* cache reads */
391 } else {
392 meta_write_policy = V_02807C_CACHE_STREAM_WR; /* write combine */
393 meta_read_policy = V_02807C_CACHE_NOA_RD; /* don't cache reads */
394 }
395
396 radeon_set_context_reg(cs, R_02807C_DB_RMI_L2_CACHE_CONTROL,
397 S_02807C_Z_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
398 S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
399 S_02807C_HTILE_WR_POLICY(meta_write_policy) |
400 S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
401 S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA_RD) |
402 S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA_RD) |
403 S_02807C_HTILE_RD_POLICY(meta_read_policy));
404
405 radeon_set_context_reg(cs, R_028410_CB_RMI_GL2_CACHE_CONTROL,
406 S_028410_CMASK_WR_POLICY(meta_write_policy) |
407 S_028410_FMASK_WR_POLICY(meta_write_policy) |
408 S_028410_DCC_WR_POLICY(meta_write_policy) |
409 S_028410_COLOR_WR_POLICY(V_028410_CACHE_STREAM_WR) |
410 S_028410_CMASK_RD_POLICY(meta_read_policy) |
411 S_028410_FMASK_RD_POLICY(meta_read_policy) |
412 S_028410_DCC_RD_POLICY(meta_read_policy) |
413 S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_RD));
414 radeon_set_context_reg(cs, R_028428_CB_COVERAGE_OUT_CONTROL, 0);
415
416 radeon_set_sh_reg(cs, R_00B0C0_SPI_SHADER_REQ_CTRL_PS,
417 S_00B0C0_SOFT_GROUPING_EN(1) |
418 S_00B0C0_NUMBER_OF_REQUESTS_PER_CU(4 - 1));
419 radeon_set_sh_reg(cs, R_00B1C0_SPI_SHADER_REQ_CTRL_VS, 0);
420
421 if (physical_device->rad_info.chip_class >= GFX10_3) {
422 radeon_set_context_reg(cs, R_028750_SX_PS_DOWNCONVERT_CONTROL_GFX103, 0xff);
423 }
424
425 if (physical_device->rad_info.chip_class == GFX10) {
426 /* SQ_NON_EVENT must be emitted before GE_PC_ALLOC is written. */
427 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
428 radeon_emit(cs, EVENT_TYPE(V_028A90_SQ_NON_EVENT) | EVENT_INDEX(0));
429 }
430
431 /* TODO: For culling, replace 128 with 256. */
432 radeon_set_uconfig_reg(cs, R_030980_GE_PC_ALLOC,
433 S_030980_OVERSUB_EN(physical_device->rad_info.use_late_alloc) |
434 S_030980_NUM_PC_LINES(128 * physical_device->rad_info.max_se - 1));
435 }
436
437 if (physical_device->rad_info.chip_class >= GFX9) {
438 radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION,
439 S_028B50_ACCUM_ISOLINE(40) |
440 S_028B50_ACCUM_TRI(30) |
441 S_028B50_ACCUM_QUAD(24) |
442 S_028B50_DONUT_SPLIT(24) |
443 S_028B50_TRAP_SPLIT(6));
444 } else if (physical_device->rad_info.chip_class >= GFX8) {
445 uint32_t vgt_tess_distribution;
446
447 vgt_tess_distribution = S_028B50_ACCUM_ISOLINE(32) |
448 S_028B50_ACCUM_TRI(11) |
449 S_028B50_ACCUM_QUAD(11) |
450 S_028B50_DONUT_SPLIT(16);
451
452 if (physical_device->rad_info.family == CHIP_FIJI ||
453 physical_device->rad_info.family >= CHIP_POLARIS10)
454 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
455
456 radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION,
457 vgt_tess_distribution);
458 } else if (!has_clear_state) {
459 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
460 radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
461 }
462
463 if (device->border_color_data.bo) {
464 uint64_t border_color_va = radv_buffer_get_va(device->border_color_data.bo);
465
466 radeon_set_context_reg(cs, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
467 if (physical_device->rad_info.chip_class >= GFX7) {
468 radeon_set_context_reg(cs, R_028084_TA_BC_BASE_ADDR_HI,
469 S_028084_ADDRESS(border_color_va >> 40));
470 }
471 }
472
473 if (physical_device->rad_info.chip_class >= GFX9) {
474 radeon_set_context_reg(cs, R_028C48_PA_SC_BINNER_CNTL_1,
475 S_028C48_MAX_ALLOC_COUNT(physical_device->rad_info.pbb_max_alloc_count - 1) |
476 S_028C48_MAX_PRIM_PER_BATCH(1023));
477 radeon_set_context_reg(cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
478 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
479 radeon_set_uconfig_reg(cs, R_030968_VGT_INSTANCE_BASE_ID, 0);
480 }
481
482 unsigned tmp = (unsigned)(1.0 * 8.0);
483 radeon_set_context_reg_seq(cs, R_028A00_PA_SU_POINT_SIZE, 1);
484 radeon_emit(cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
485 radeon_set_context_reg_seq(cs, R_028A04_PA_SU_POINT_MINMAX, 1);
486 radeon_emit(cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
487 S_028A04_MAX_SIZE(radv_pack_float_12p4(8191.875/2)));
488
489 if (!has_clear_state) {
490 radeon_set_context_reg(cs, R_028004_DB_COUNT_CONTROL,
491 S_028004_ZPASS_INCREMENT_DISABLE(1));
492 }
493
494 /* Enable the Polaris small primitive filter control.
495 * XXX: There is possibly an issue when MSAA is off (see RadeonSI
496 * has_msaa_sample_loc_bug). But this doesn't seem to regress anything,
497 * and AMDVLK doesn't have a workaround as well.
498 */
499 if (physical_device->rad_info.family >= CHIP_POLARIS10) {
500 unsigned small_prim_filter_cntl =
501 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
502 /* Workaround for a hw line bug. */
503 S_028830_LINE_FILTER_DISABLE(physical_device->rad_info.family <= CHIP_POLARIS12);
504
505 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
506 small_prim_filter_cntl);
507 }
508
509 si_emit_compute(physical_device, cs);
510 }
511
512 void
513 cik_create_gfx_config(struct radv_device *device)
514 {
515 struct radeon_cmdbuf *cs = device->ws->cs_create(device->ws, RING_GFX);
516 if (!cs)
517 return;
518
519 si_emit_graphics(device, cs);
520
521 while (cs->cdw & 7) {
522 if (device->physical_device->rad_info.gfx_ib_pad_with_type2)
523 radeon_emit(cs, PKT2_NOP_PAD);
524 else
525 radeon_emit(cs, PKT3_NOP_PAD);
526 }
527
528 device->gfx_init = device->ws->buffer_create(device->ws,
529 cs->cdw * 4, 4096,
530 RADEON_DOMAIN_GTT,
531 RADEON_FLAG_CPU_ACCESS|
532 RADEON_FLAG_NO_INTERPROCESS_SHARING |
533 RADEON_FLAG_READ_ONLY,
534 RADV_BO_PRIORITY_CS);
535 if (!device->gfx_init)
536 goto fail;
537
538 void *map = device->ws->buffer_map(device->gfx_init);
539 if (!map) {
540 device->ws->buffer_destroy(device->gfx_init);
541 device->gfx_init = NULL;
542 goto fail;
543 }
544 memcpy(map, cs->buf, cs->cdw * 4);
545
546 device->ws->buffer_unmap(device->gfx_init);
547 device->gfx_init_size_dw = cs->cdw;
548 fail:
549 device->ws->cs_destroy(cs);
550 }
551
552 static void
553 get_viewport_xform(const VkViewport *viewport,
554 float scale[3], float translate[3])
555 {
556 float x = viewport->x;
557 float y = viewport->y;
558 float half_width = 0.5f * viewport->width;
559 float half_height = 0.5f * viewport->height;
560 double n = viewport->minDepth;
561 double f = viewport->maxDepth;
562
563 scale[0] = half_width;
564 translate[0] = half_width + x;
565 scale[1] = half_height;
566 translate[1] = half_height + y;
567
568 scale[2] = (f - n);
569 translate[2] = n;
570 }
571
572 void
573 si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
574 int count, const VkViewport *viewports)
575 {
576 int i;
577
578 assert(count);
579 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
580 first_vp * 4 * 6, count * 6);
581
582 for (i = 0; i < count; i++) {
583 float scale[3], translate[3];
584
585
586 get_viewport_xform(&viewports[i], scale, translate);
587 radeon_emit(cs, fui(scale[0]));
588 radeon_emit(cs, fui(translate[0]));
589 radeon_emit(cs, fui(scale[1]));
590 radeon_emit(cs, fui(translate[1]));
591 radeon_emit(cs, fui(scale[2]));
592 radeon_emit(cs, fui(translate[2]));
593 }
594
595 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 +
596 first_vp * 4 * 2, count * 2);
597 for (i = 0; i < count; i++) {
598 float zmin = MIN2(viewports[i].minDepth, viewports[i].maxDepth);
599 float zmax = MAX2(viewports[i].minDepth, viewports[i].maxDepth);
600 radeon_emit(cs, fui(zmin));
601 radeon_emit(cs, fui(zmax));
602 }
603 }
604
605 static VkRect2D si_scissor_from_viewport(const VkViewport *viewport)
606 {
607 float scale[3], translate[3];
608 VkRect2D rect;
609
610 get_viewport_xform(viewport, scale, translate);
611
612 rect.offset.x = translate[0] - fabsf(scale[0]);
613 rect.offset.y = translate[1] - fabsf(scale[1]);
614 rect.extent.width = ceilf(translate[0] + fabsf(scale[0])) - rect.offset.x;
615 rect.extent.height = ceilf(translate[1] + fabsf(scale[1])) - rect.offset.y;
616
617 return rect;
618 }
619
620 static VkRect2D si_intersect_scissor(const VkRect2D *a, const VkRect2D *b) {
621 VkRect2D ret;
622 ret.offset.x = MAX2(a->offset.x, b->offset.x);
623 ret.offset.y = MAX2(a->offset.y, b->offset.y);
624 ret.extent.width = MIN2(a->offset.x + a->extent.width,
625 b->offset.x + b->extent.width) - ret.offset.x;
626 ret.extent.height = MIN2(a->offset.y + a->extent.height,
627 b->offset.y + b->extent.height) - ret.offset.y;
628 return ret;
629 }
630
631 void
632 si_write_scissors(struct radeon_cmdbuf *cs, int first,
633 int count, const VkRect2D *scissors,
634 const VkViewport *viewports, bool can_use_guardband)
635 {
636 int i;
637 float scale[3], translate[3], guardband_x = INFINITY, guardband_y = INFINITY;
638 const float max_range = 32767.0f;
639 if (!count)
640 return;
641
642 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + first * 4 * 2, count * 2);
643 for (i = 0; i < count; i++) {
644 VkRect2D viewport_scissor = si_scissor_from_viewport(viewports + i);
645 VkRect2D scissor = si_intersect_scissor(&scissors[i], &viewport_scissor);
646
647 get_viewport_xform(viewports + i, scale, translate);
648 scale[0] = fabsf(scale[0]);
649 scale[1] = fabsf(scale[1]);
650
651 if (scale[0] < 0.5)
652 scale[0] = 0.5;
653 if (scale[1] < 0.5)
654 scale[1] = 0.5;
655
656 guardband_x = MIN2(guardband_x, (max_range - fabsf(translate[0])) / scale[0]);
657 guardband_y = MIN2(guardband_y, (max_range - fabsf(translate[1])) / scale[1]);
658
659 radeon_emit(cs, S_028250_TL_X(scissor.offset.x) |
660 S_028250_TL_Y(scissor.offset.y) |
661 S_028250_WINDOW_OFFSET_DISABLE(1));
662 radeon_emit(cs, S_028254_BR_X(scissor.offset.x + scissor.extent.width) |
663 S_028254_BR_Y(scissor.offset.y + scissor.extent.height));
664 }
665 if (!can_use_guardband) {
666 guardband_x = 1.0;
667 guardband_y = 1.0;
668 }
669
670 radeon_set_context_reg_seq(cs, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
671 radeon_emit(cs, fui(guardband_y));
672 radeon_emit(cs, fui(1.0));
673 radeon_emit(cs, fui(guardband_x));
674 radeon_emit(cs, fui(1.0));
675 }
676
677 static inline unsigned
678 radv_prims_for_vertices(struct radv_prim_vertex_count *info, unsigned num)
679 {
680 if (num == 0)
681 return 0;
682
683 if (info->incr == 0)
684 return 0;
685
686 if (num < info->min)
687 return 0;
688
689 return 1 + ((num - info->min) / info->incr);
690 }
691
692 static const struct radv_prim_vertex_count prim_size_table[] = {
693 [V_008958_DI_PT_NONE] = {0, 0},
694 [V_008958_DI_PT_POINTLIST] = {1, 1},
695 [V_008958_DI_PT_LINELIST] = {2, 2},
696 [V_008958_DI_PT_LINESTRIP] = {2, 1},
697 [V_008958_DI_PT_TRILIST] = {3, 3},
698 [V_008958_DI_PT_TRIFAN] = {3, 1},
699 [V_008958_DI_PT_TRISTRIP] = {3, 1},
700 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
701 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
702 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
703 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
704 [V_008958_DI_PT_RECTLIST] = {3, 3},
705 [V_008958_DI_PT_LINELOOP] = {2, 1},
706 [V_008958_DI_PT_POLYGON] = {3, 1},
707 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
708 };
709
710 uint32_t
711 si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
712 bool instanced_draw, bool indirect_draw,
713 bool count_from_stream_output,
714 uint32_t draw_vertex_count)
715 {
716 enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
717 enum radeon_family family = cmd_buffer->device->physical_device->rad_info.family;
718 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
719 const unsigned max_primgroup_in_wave = 2;
720 /* SWITCH_ON_EOP(0) is always preferable. */
721 bool wd_switch_on_eop = false;
722 bool ia_switch_on_eop = false;
723 bool ia_switch_on_eoi = false;
724 bool partial_vs_wave = false;
725 bool partial_es_wave = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.partial_es_wave;
726 unsigned topology = cmd_buffer->state.pipeline->graphics.topology;
727 bool multi_instances_smaller_than_primgroup;
728 struct radv_prim_vertex_count prim_vertex_count = prim_size_table[topology];
729
730 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline)) {
731 if (topology == V_008958_DI_PT_PATCH) {
732 prim_vertex_count.min = cmd_buffer->state.pipeline->graphics.tess_patch_control_points;
733 prim_vertex_count.incr = 1;
734 }
735 }
736
737 multi_instances_smaller_than_primgroup = indirect_draw;
738 if (!multi_instances_smaller_than_primgroup && instanced_draw) {
739 uint32_t num_prims = radv_prims_for_vertices(&prim_vertex_count, draw_vertex_count);
740 if (num_prims < cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.primgroup_size)
741 multi_instances_smaller_than_primgroup = true;
742 }
743
744 ia_switch_on_eoi = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.ia_switch_on_eoi;
745 partial_vs_wave = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.partial_vs_wave;
746
747 if (chip_class >= GFX7) {
748 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
749 * 4 shader engines. Set 1 to pass the assertion below.
750 * The other cases are hardware requirements. */
751 if (cmd_buffer->device->physical_device->rad_info.max_se < 4 ||
752 topology == V_008958_DI_PT_POLYGON ||
753 topology == V_008958_DI_PT_LINELOOP ||
754 topology == V_008958_DI_PT_TRIFAN ||
755 topology == V_008958_DI_PT_TRISTRIP_ADJ ||
756 (cmd_buffer->state.pipeline->graphics.prim_restart_enable &&
757 (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10 ||
758 (topology != V_008958_DI_PT_POINTLIST &&
759 topology != V_008958_DI_PT_LINESTRIP))))
760 wd_switch_on_eop = true;
761
762 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
763 * We don't know that for indirect drawing, so treat it as
764 * always problematic. */
765 if (family == CHIP_HAWAII &&
766 (instanced_draw || indirect_draw))
767 wd_switch_on_eop = true;
768
769 /* Performance recommendation for 4 SE Gfx7-8 parts if
770 * instances are smaller than a primgroup.
771 * Assume indirect draws always use small instances.
772 * This is needed for good VS wave utilization.
773 */
774 if (chip_class <= GFX8 &&
775 info->max_se == 4 &&
776 multi_instances_smaller_than_primgroup)
777 wd_switch_on_eop = true;
778
779 /* Required on GFX7 and later. */
780 if (info->max_se > 2 && !wd_switch_on_eop)
781 ia_switch_on_eoi = true;
782
783 /* Required by Hawaii and, for some special cases, by GFX8. */
784 if (ia_switch_on_eoi &&
785 (family == CHIP_HAWAII ||
786 (chip_class == GFX8 &&
787 /* max primgroup in wave is always 2 - leave this for documentation */
788 (radv_pipeline_has_gs(cmd_buffer->state.pipeline) || max_primgroup_in_wave != 2))))
789 partial_vs_wave = true;
790
791 /* Instancing bug on Bonaire. */
792 if (family == CHIP_BONAIRE && ia_switch_on_eoi &&
793 (instanced_draw || indirect_draw))
794 partial_vs_wave = true;
795
796 /* Hardware requirement when drawing primitives from a stream
797 * output buffer.
798 */
799 if (count_from_stream_output)
800 wd_switch_on_eop = true;
801
802 /* If the WD switch is false, the IA switch must be false too. */
803 assert(wd_switch_on_eop || !ia_switch_on_eop);
804 }
805 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
806 if (chip_class <= GFX8 && ia_switch_on_eoi)
807 partial_es_wave = true;
808
809 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline)) {
810 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
811 * The hw doc says all multi-SE chips are affected, but amdgpu-pro Vulkan
812 * only applies it to Hawaii. Do what amdgpu-pro Vulkan does.
813 */
814 if (family == CHIP_HAWAII && ia_switch_on_eoi) {
815 bool set_vgt_flush = indirect_draw;
816 if (!set_vgt_flush && instanced_draw) {
817 uint32_t num_prims = radv_prims_for_vertices(&prim_vertex_count, draw_vertex_count);
818 if (num_prims <= 1)
819 set_vgt_flush = true;
820 }
821 if (set_vgt_flush)
822 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
823 }
824 }
825
826 /* Workaround for a VGT hang when strip primitive types are used with
827 * primitive restart.
828 */
829 if (cmd_buffer->state.pipeline->graphics.prim_restart_enable &&
830 (topology == V_008958_DI_PT_LINESTRIP ||
831 topology == V_008958_DI_PT_TRISTRIP ||
832 topology == V_008958_DI_PT_LINESTRIP_ADJ ||
833 topology == V_008958_DI_PT_TRISTRIP_ADJ)) {
834 partial_vs_wave = true;
835 }
836
837 return cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.base |
838 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
839 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
840 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
841 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
842 S_028AA8_WD_SWITCH_ON_EOP(chip_class >= GFX7 ? wd_switch_on_eop : 0);
843
844 }
845
846 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
847 enum chip_class chip_class,
848 bool is_mec,
849 unsigned event, unsigned event_flags,
850 unsigned dst_sel, unsigned data_sel,
851 uint64_t va,
852 uint32_t new_fence,
853 uint64_t gfx9_eop_bug_va)
854 {
855 unsigned op = EVENT_TYPE(event) |
856 EVENT_INDEX(event == V_028A90_CS_DONE ||
857 event == V_028A90_PS_DONE ? 6 : 5) |
858 event_flags;
859 unsigned is_gfx8_mec = is_mec && chip_class < GFX9;
860 unsigned sel = EOP_DST_SEL(dst_sel) |
861 EOP_DATA_SEL(data_sel);
862
863 /* Wait for write confirmation before writing data, but don't send
864 * an interrupt. */
865 if (data_sel != EOP_DATA_SEL_DISCARD)
866 sel |= EOP_INT_SEL(EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM);
867
868 if (chip_class >= GFX9 || is_gfx8_mec) {
869 /* A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion
870 * counters) must immediately precede every timestamp event to
871 * prevent a GPU hang on GFX9.
872 */
873 if (chip_class == GFX9 && !is_mec) {
874 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
875 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
876 radeon_emit(cs, gfx9_eop_bug_va);
877 radeon_emit(cs, gfx9_eop_bug_va >> 32);
878 }
879
880 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, is_gfx8_mec ? 5 : 6, false));
881 radeon_emit(cs, op);
882 radeon_emit(cs, sel);
883 radeon_emit(cs, va); /* address lo */
884 radeon_emit(cs, va >> 32); /* address hi */
885 radeon_emit(cs, new_fence); /* immediate data lo */
886 radeon_emit(cs, 0); /* immediate data hi */
887 if (!is_gfx8_mec)
888 radeon_emit(cs, 0); /* unused */
889 } else {
890 if (chip_class == GFX7 ||
891 chip_class == GFX8) {
892 /* Two EOP events are required to make all engines go idle
893 * (and optional cache flushes executed) before the timestamp
894 * is written.
895 */
896 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false));
897 radeon_emit(cs, op);
898 radeon_emit(cs, va);
899 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
900 radeon_emit(cs, 0); /* immediate data */
901 radeon_emit(cs, 0); /* unused */
902 }
903
904 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false));
905 radeon_emit(cs, op);
906 radeon_emit(cs, va);
907 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
908 radeon_emit(cs, new_fence); /* immediate data */
909 radeon_emit(cs, 0); /* unused */
910 }
911 }
912
913 void
914 radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va,
915 uint32_t ref, uint32_t mask)
916 {
917 assert(op == WAIT_REG_MEM_EQUAL ||
918 op == WAIT_REG_MEM_NOT_EQUAL ||
919 op == WAIT_REG_MEM_GREATER_OR_EQUAL);
920
921 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, false));
922 radeon_emit(cs, op | WAIT_REG_MEM_MEM_SPACE(1));
923 radeon_emit(cs, va);
924 radeon_emit(cs, va >> 32);
925 radeon_emit(cs, ref); /* reference value */
926 radeon_emit(cs, mask); /* mask */
927 radeon_emit(cs, 4); /* poll interval */
928 }
929
930 static void
931 si_emit_acquire_mem(struct radeon_cmdbuf *cs,
932 bool is_mec,
933 bool is_gfx9,
934 unsigned cp_coher_cntl)
935 {
936 if (is_mec || is_gfx9) {
937 uint32_t hi_val = is_gfx9 ? 0xffffff : 0xff;
938 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, false) |
939 PKT3_SHADER_TYPE_S(is_mec));
940 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
941 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
942 radeon_emit(cs, hi_val); /* CP_COHER_SIZE_HI */
943 radeon_emit(cs, 0); /* CP_COHER_BASE */
944 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
945 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
946 } else {
947 /* ACQUIRE_MEM is only required on a compute ring. */
948 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, false));
949 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
950 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
951 radeon_emit(cs, 0); /* CP_COHER_BASE */
952 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
953 }
954 }
955
956 static void
957 gfx10_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
958 enum chip_class chip_class,
959 uint32_t *flush_cnt,
960 uint64_t flush_va,
961 bool is_mec,
962 enum radv_cmd_flush_bits flush_bits,
963 uint64_t gfx9_eop_bug_va)
964 {
965 uint32_t gcr_cntl = 0;
966 unsigned cb_db_event = 0;
967
968 /* We don't need these. */
969 assert(!(flush_bits & (RADV_CMD_FLAG_VGT_STREAMOUT_SYNC)));
970
971 if (flush_bits & RADV_CMD_FLAG_INV_ICACHE)
972 gcr_cntl |= S_586_GLI_INV(V_586_GLI_ALL);
973 if (flush_bits & RADV_CMD_FLAG_INV_SCACHE) {
974 /* TODO: When writing to the SMEM L1 cache, we need to set SEQ
975 * to FORWARD when both L1 and L2 are written out (WB or INV).
976 */
977 gcr_cntl |= S_586_GL1_INV(1) | S_586_GLK_INV(1);
978 }
979 if (flush_bits & RADV_CMD_FLAG_INV_VCACHE)
980 gcr_cntl |= S_586_GL1_INV(1) | S_586_GLV_INV(1);
981 if (flush_bits & RADV_CMD_FLAG_INV_L2) {
982 /* Writeback and invalidate everything in L2. */
983 gcr_cntl |= S_586_GL2_INV(1) | S_586_GL2_WB(1) |
984 S_586_GLM_INV(1) | S_586_GLM_WB(1);
985 } else if (flush_bits & RADV_CMD_FLAG_WB_L2) {
986 /* Writeback but do not invalidate.
987 * GLM doesn't support WB alone. If WB is set, INV must be set too.
988 */
989 gcr_cntl |= S_586_GL2_WB(1) |
990 S_586_GLM_WB(1) | S_586_GLM_INV(1);
991 }
992
993 /* TODO: Implement this new flag for GFX9+.
994 else if (flush_bits & RADV_CMD_FLAG_INV_L2_METADATA)
995 gcr_cntl |= S_586_GLM_INV(1) | S_586_GLM_WB(1);
996 */
997
998 if (flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB)) {
999 /* TODO: trigger on RADV_CMD_FLAG_FLUSH_AND_INV_CB_META */
1000 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
1001 /* Flush CMASK/FMASK/DCC. Will wait for idle later. */
1002 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1003 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) |
1004 EVENT_INDEX(0));
1005 }
1006
1007 /* TODO: trigger on RADV_CMD_FLAG_FLUSH_AND_INV_DB_META ? */
1008 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
1009 /* Flush HTILE. Will wait for idle later. */
1010 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1011 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) |
1012 EVENT_INDEX(0));
1013 }
1014
1015 /* First flush CB/DB, then L1/L2. */
1016 gcr_cntl |= S_586_SEQ(V_586_SEQ_FORWARD);
1017
1018 if ((flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB)) ==
1019 (RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB)) {
1020 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1021 } else if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
1022 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
1023 } else if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
1024 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
1025 } else {
1026 assert(0);
1027 }
1028 } else {
1029 /* Wait for graphics shaders to go idle if requested. */
1030 if (flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) {
1031 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1032 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1033 } else if (flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) {
1034 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1035 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1036 }
1037 }
1038
1039 if (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) {
1040 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1041 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
1042 }
1043
1044 if (cb_db_event) {
1045 /* CB/DB flush and invalidate (or possibly just a wait for a
1046 * meta flush) via RELEASE_MEM.
1047 *
1048 * Combine this with other cache flushes when possible; this
1049 * requires affected shaders to be idle, so do it after the
1050 * CS_PARTIAL_FLUSH before (VS/PS partial flushes are always
1051 * implied).
1052 */
1053 /* Get GCR_CNTL fields, because the encoding is different in RELEASE_MEM. */
1054 unsigned glm_wb = G_586_GLM_WB(gcr_cntl);
1055 unsigned glm_inv = G_586_GLM_INV(gcr_cntl);
1056 unsigned glv_inv = G_586_GLV_INV(gcr_cntl);
1057 unsigned gl1_inv = G_586_GL1_INV(gcr_cntl);
1058 assert(G_586_GL2_US(gcr_cntl) == 0);
1059 assert(G_586_GL2_RANGE(gcr_cntl) == 0);
1060 assert(G_586_GL2_DISCARD(gcr_cntl) == 0);
1061 unsigned gl2_inv = G_586_GL2_INV(gcr_cntl);
1062 unsigned gl2_wb = G_586_GL2_WB(gcr_cntl);
1063 unsigned gcr_seq = G_586_SEQ(gcr_cntl);
1064
1065 gcr_cntl &= C_586_GLM_WB &
1066 C_586_GLM_INV &
1067 C_586_GLV_INV &
1068 C_586_GL1_INV &
1069 C_586_GL2_INV &
1070 C_586_GL2_WB; /* keep SEQ */
1071
1072 assert(flush_cnt);
1073 (*flush_cnt)++;
1074
1075 si_cs_emit_write_event_eop(cs, chip_class, false, cb_db_event,
1076 S_490_GLM_WB(glm_wb) |
1077 S_490_GLM_INV(glm_inv) |
1078 S_490_GLV_INV(glv_inv) |
1079 S_490_GL1_INV(gl1_inv) |
1080 S_490_GL2_INV(gl2_inv) |
1081 S_490_GL2_WB(gl2_wb) |
1082 S_490_SEQ(gcr_seq),
1083 EOP_DST_SEL_MEM,
1084 EOP_DATA_SEL_VALUE_32BIT,
1085 flush_va, *flush_cnt,
1086 gfx9_eop_bug_va);
1087
1088 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, flush_va,
1089 *flush_cnt, 0xffffffff);
1090 }
1091
1092 /* VGT state sync */
1093 if (flush_bits & RADV_CMD_FLAG_VGT_FLUSH) {
1094 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1095 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1096 }
1097
1098 /* Ignore fields that only modify the behavior of other fields. */
1099 if (gcr_cntl & C_586_GL1_RANGE & C_586_GL2_RANGE & C_586_SEQ) {
1100 /* Flush caches and wait for the caches to assert idle.
1101 * The cache flush is executed in the ME, but the PFP waits
1102 * for completion.
1103 */
1104 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 6, 0));
1105 radeon_emit(cs, 0); /* CP_COHER_CNTL */
1106 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
1107 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
1108 radeon_emit(cs, 0); /* CP_COHER_BASE */
1109 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
1110 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
1111 radeon_emit(cs, gcr_cntl); /* GCR_CNTL */
1112 } else if ((cb_db_event ||
1113 (flush_bits & (RADV_CMD_FLAG_VS_PARTIAL_FLUSH |
1114 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
1115 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)))
1116 && !is_mec) {
1117 /* We need to ensure that PFP waits as well. */
1118 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1119 radeon_emit(cs, 0);
1120 }
1121
1122 if (flush_bits & RADV_CMD_FLAG_START_PIPELINE_STATS) {
1123 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1124 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1125 EVENT_INDEX(0));
1126 } else if (flush_bits & RADV_CMD_FLAG_STOP_PIPELINE_STATS) {
1127 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1128 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1129 EVENT_INDEX(0));
1130 }
1131 }
1132
1133 void
1134 si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
1135 enum chip_class chip_class,
1136 uint32_t *flush_cnt,
1137 uint64_t flush_va,
1138 bool is_mec,
1139 enum radv_cmd_flush_bits flush_bits,
1140 uint64_t gfx9_eop_bug_va)
1141 {
1142 unsigned cp_coher_cntl = 0;
1143 uint32_t flush_cb_db = flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1144 RADV_CMD_FLAG_FLUSH_AND_INV_DB);
1145
1146 if (chip_class >= GFX10) {
1147 /* GFX10 cache flush handling is quite different. */
1148 gfx10_cs_emit_cache_flush(cs, chip_class, flush_cnt, flush_va,
1149 is_mec, flush_bits, gfx9_eop_bug_va);
1150 return;
1151 }
1152
1153 if (flush_bits & RADV_CMD_FLAG_INV_ICACHE)
1154 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
1155 if (flush_bits & RADV_CMD_FLAG_INV_SCACHE)
1156 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
1157
1158 if (chip_class <= GFX8) {
1159 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
1160 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
1161 S_0085F0_CB0_DEST_BASE_ENA(1) |
1162 S_0085F0_CB1_DEST_BASE_ENA(1) |
1163 S_0085F0_CB2_DEST_BASE_ENA(1) |
1164 S_0085F0_CB3_DEST_BASE_ENA(1) |
1165 S_0085F0_CB4_DEST_BASE_ENA(1) |
1166 S_0085F0_CB5_DEST_BASE_ENA(1) |
1167 S_0085F0_CB6_DEST_BASE_ENA(1) |
1168 S_0085F0_CB7_DEST_BASE_ENA(1);
1169
1170 /* Necessary for DCC */
1171 if (chip_class >= GFX8) {
1172 si_cs_emit_write_event_eop(cs,
1173 chip_class,
1174 is_mec,
1175 V_028A90_FLUSH_AND_INV_CB_DATA_TS,
1176 0,
1177 EOP_DST_SEL_MEM,
1178 EOP_DATA_SEL_DISCARD,
1179 0, 0,
1180 gfx9_eop_bug_va);
1181 }
1182 }
1183 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
1184 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
1185 S_0085F0_DB_DEST_BASE_ENA(1);
1186 }
1187 }
1188
1189 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) {
1190 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1191 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
1192 }
1193
1194 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) {
1195 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1196 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
1197 }
1198
1199 if (flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) {
1200 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1201 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1202 } else if (flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) {
1203 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1204 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1205 }
1206
1207 if (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) {
1208 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1209 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1210 }
1211
1212 if (chip_class == GFX9 && flush_cb_db) {
1213 unsigned cb_db_event, tc_flags;
1214
1215 /* Set the CB/DB flush event. */
1216 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1217
1218 /* These are the only allowed combinations. If you need to
1219 * do multiple operations at once, do them separately.
1220 * All operations that invalidate L2 also seem to invalidate
1221 * metadata. Volatile (VOL) and WC flushes are not listed here.
1222 *
1223 * TC | TC_WB = writeback & invalidate L2 & L1
1224 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
1225 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
1226 * TC | TC_NC = invalidate L2 for MTYPE == NC
1227 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
1228 * TCL1 = invalidate L1
1229 */
1230 tc_flags = EVENT_TC_ACTION_ENA |
1231 EVENT_TC_MD_ACTION_ENA;
1232
1233 /* Ideally flush TC together with CB/DB. */
1234 if (flush_bits & RADV_CMD_FLAG_INV_L2) {
1235 /* Writeback and invalidate everything in L2 & L1. */
1236 tc_flags = EVENT_TC_ACTION_ENA |
1237 EVENT_TC_WB_ACTION_ENA;
1238
1239
1240 /* Clear the flags. */
1241 flush_bits &= ~(RADV_CMD_FLAG_INV_L2 |
1242 RADV_CMD_FLAG_WB_L2 |
1243 RADV_CMD_FLAG_INV_VCACHE);
1244 }
1245 assert(flush_cnt);
1246 (*flush_cnt)++;
1247
1248 si_cs_emit_write_event_eop(cs, chip_class, false, cb_db_event, tc_flags,
1249 EOP_DST_SEL_MEM,
1250 EOP_DATA_SEL_VALUE_32BIT,
1251 flush_va, *flush_cnt,
1252 gfx9_eop_bug_va);
1253 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, flush_va,
1254 *flush_cnt, 0xffffffff);
1255 }
1256
1257 /* VGT state sync */
1258 if (flush_bits & RADV_CMD_FLAG_VGT_FLUSH) {
1259 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1260 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1261 }
1262
1263 /* VGT streamout state sync */
1264 if (flush_bits & RADV_CMD_FLAG_VGT_STREAMOUT_SYNC) {
1265 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1266 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
1267 }
1268
1269 /* Make sure ME is idle (it executes most packets) before continuing.
1270 * This prevents read-after-write hazards between PFP and ME.
1271 */
1272 if ((cp_coher_cntl ||
1273 (flush_bits & (RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
1274 RADV_CMD_FLAG_INV_VCACHE |
1275 RADV_CMD_FLAG_INV_L2 |
1276 RADV_CMD_FLAG_WB_L2))) &&
1277 !is_mec) {
1278 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1279 radeon_emit(cs, 0);
1280 }
1281
1282 if ((flush_bits & RADV_CMD_FLAG_INV_L2) ||
1283 (chip_class <= GFX7 && (flush_bits & RADV_CMD_FLAG_WB_L2))) {
1284 si_emit_acquire_mem(cs, is_mec, chip_class == GFX9,
1285 cp_coher_cntl |
1286 S_0085F0_TC_ACTION_ENA(1) |
1287 S_0085F0_TCL1_ACTION_ENA(1) |
1288 S_0301F0_TC_WB_ACTION_ENA(chip_class >= GFX8));
1289 cp_coher_cntl = 0;
1290 } else {
1291 if(flush_bits & RADV_CMD_FLAG_WB_L2) {
1292 /* WB = write-back
1293 * NC = apply to non-coherent MTYPEs
1294 * (i.e. MTYPE <= 1, which is what we use everywhere)
1295 *
1296 * WB doesn't work without NC.
1297 */
1298 si_emit_acquire_mem(cs, is_mec,
1299 chip_class == GFX9,
1300 cp_coher_cntl |
1301 S_0301F0_TC_WB_ACTION_ENA(1) |
1302 S_0301F0_TC_NC_ACTION_ENA(1));
1303 cp_coher_cntl = 0;
1304 }
1305 if (flush_bits & RADV_CMD_FLAG_INV_VCACHE) {
1306 si_emit_acquire_mem(cs, is_mec,
1307 chip_class == GFX9,
1308 cp_coher_cntl |
1309 S_0085F0_TCL1_ACTION_ENA(1));
1310 cp_coher_cntl = 0;
1311 }
1312 }
1313
1314 /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
1315 * Therefore, it should be last. Done in PFP.
1316 */
1317 if (cp_coher_cntl)
1318 si_emit_acquire_mem(cs, is_mec, chip_class == GFX9, cp_coher_cntl);
1319
1320 if (flush_bits & RADV_CMD_FLAG_START_PIPELINE_STATS) {
1321 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1322 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1323 EVENT_INDEX(0));
1324 } else if (flush_bits & RADV_CMD_FLAG_STOP_PIPELINE_STATS) {
1325 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1326 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1327 EVENT_INDEX(0));
1328 }
1329 }
1330
1331 void
1332 si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer)
1333 {
1334 bool is_compute = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
1335
1336 if (is_compute)
1337 cmd_buffer->state.flush_bits &= ~(RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1338 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1339 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1340 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1341 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
1342 RADV_CMD_FLAG_VS_PARTIAL_FLUSH |
1343 RADV_CMD_FLAG_VGT_FLUSH |
1344 RADV_CMD_FLAG_START_PIPELINE_STATS |
1345 RADV_CMD_FLAG_STOP_PIPELINE_STATS);
1346
1347 if (!cmd_buffer->state.flush_bits)
1348 return;
1349
1350 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 128);
1351
1352 si_cs_emit_cache_flush(cmd_buffer->cs,
1353 cmd_buffer->device->physical_device->rad_info.chip_class,
1354 &cmd_buffer->gfx9_fence_idx,
1355 cmd_buffer->gfx9_fence_va,
1356 radv_cmd_buffer_uses_mec(cmd_buffer),
1357 cmd_buffer->state.flush_bits,
1358 cmd_buffer->gfx9_eop_bug_va);
1359
1360
1361 if (unlikely(cmd_buffer->device->trace_bo))
1362 radv_cmd_buffer_trace_emit(cmd_buffer);
1363
1364 /* Clear the caches that have been flushed to avoid syncing too much
1365 * when there is some pending active queries.
1366 */
1367 cmd_buffer->active_query_flush_bits &= ~cmd_buffer->state.flush_bits;
1368
1369 cmd_buffer->state.flush_bits = 0;
1370
1371 /* If the driver used a compute shader for resetting a query pool, it
1372 * should be finished at this point.
1373 */
1374 cmd_buffer->pending_reset_query = false;
1375 }
1376
1377 /* sets the CP predication state using a boolean stored at va */
1378 void
1379 si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
1380 bool draw_visible, uint64_t va)
1381 {
1382 uint32_t op = 0;
1383
1384 if (va) {
1385 op = PRED_OP(PREDICATION_OP_BOOL64);
1386
1387 /* PREDICATION_DRAW_VISIBLE means that if the 32-bit value is
1388 * zero, all rendering commands are discarded. Otherwise, they
1389 * are discarded if the value is non zero.
1390 */
1391 op |= draw_visible ? PREDICATION_DRAW_VISIBLE :
1392 PREDICATION_DRAW_NOT_VISIBLE;
1393 }
1394 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1395 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 2, 0));
1396 radeon_emit(cmd_buffer->cs, op);
1397 radeon_emit(cmd_buffer->cs, va);
1398 radeon_emit(cmd_buffer->cs, va >> 32);
1399 } else {
1400 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
1401 radeon_emit(cmd_buffer->cs, va);
1402 radeon_emit(cmd_buffer->cs, op | ((va >> 32) & 0xFF));
1403 }
1404 }
1405
1406 /* Set this if you want the 3D engine to wait until CP DMA is done.
1407 * It should be set on the last CP DMA packet. */
1408 #define CP_DMA_SYNC (1 << 0)
1409
1410 /* Set this if the source data was used as a destination in a previous CP DMA
1411 * packet. It's for preventing a read-after-write (RAW) hazard between two
1412 * CP DMA packets. */
1413 #define CP_DMA_RAW_WAIT (1 << 1)
1414 #define CP_DMA_USE_L2 (1 << 2)
1415 #define CP_DMA_CLEAR (1 << 3)
1416
1417 /* Alignment for optimal performance. */
1418 #define SI_CPDMA_ALIGNMENT 32
1419
1420 /* The max number of bytes that can be copied per packet. */
1421 static inline unsigned cp_dma_max_byte_count(struct radv_cmd_buffer *cmd_buffer)
1422 {
1423 unsigned max = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 ?
1424 S_414_BYTE_COUNT_GFX9(~0u) :
1425 S_414_BYTE_COUNT_GFX6(~0u);
1426
1427 /* make it aligned for optimal performance */
1428 return max & ~(SI_CPDMA_ALIGNMENT - 1);
1429 }
1430
1431 /* Emit a CP DMA packet to do a copy from one buffer to another, or to clear
1432 * a buffer. The size must fit in bits [20:0]. If CP_DMA_CLEAR is set, src_va is a 32-bit
1433 * clear value.
1434 */
1435 static void si_emit_cp_dma(struct radv_cmd_buffer *cmd_buffer,
1436 uint64_t dst_va, uint64_t src_va,
1437 unsigned size, unsigned flags)
1438 {
1439 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1440 uint32_t header = 0, command = 0;
1441
1442 assert(size <= cp_dma_max_byte_count(cmd_buffer));
1443
1444 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9);
1445 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1446 command |= S_414_BYTE_COUNT_GFX9(size);
1447 else
1448 command |= S_414_BYTE_COUNT_GFX6(size);
1449
1450 /* Sync flags. */
1451 if (flags & CP_DMA_SYNC)
1452 header |= S_411_CP_SYNC(1);
1453 else {
1454 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1455 command |= S_414_DISABLE_WR_CONFIRM_GFX9(1);
1456 else
1457 command |= S_414_DISABLE_WR_CONFIRM_GFX6(1);
1458 }
1459
1460 if (flags & CP_DMA_RAW_WAIT)
1461 command |= S_414_RAW_WAIT(1);
1462
1463 /* Src and dst flags. */
1464 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
1465 !(flags & CP_DMA_CLEAR) &&
1466 src_va == dst_va)
1467 header |= S_411_DST_SEL(V_411_NOWHERE); /* prefetch only */
1468 else if (flags & CP_DMA_USE_L2)
1469 header |= S_411_DST_SEL(V_411_DST_ADDR_TC_L2);
1470
1471 if (flags & CP_DMA_CLEAR)
1472 header |= S_411_SRC_SEL(V_411_DATA);
1473 else if (flags & CP_DMA_USE_L2)
1474 header |= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2);
1475
1476 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
1477 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, cmd_buffer->state.predicating));
1478 radeon_emit(cs, header);
1479 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1480 radeon_emit(cs, src_va >> 32); /* SRC_ADDR_HI [31:0] */
1481 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1482 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [31:0] */
1483 radeon_emit(cs, command);
1484 } else {
1485 assert(!(flags & CP_DMA_USE_L2));
1486 header |= S_411_SRC_ADDR_HI(src_va >> 32);
1487 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, cmd_buffer->state.predicating));
1488 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1489 radeon_emit(cs, header); /* SRC_ADDR_HI [15:0] + flags. */
1490 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1491 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
1492 radeon_emit(cs, command);
1493 }
1494
1495 /* CP DMA is executed in ME, but index buffers are read by PFP.
1496 * This ensures that ME (CP DMA) is idle before PFP starts fetching
1497 * indices. If we wanted to execute CP DMA in PFP, this packet
1498 * should precede it.
1499 */
1500 if (flags & CP_DMA_SYNC) {
1501 if (cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
1502 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1503 radeon_emit(cs, 0);
1504 }
1505
1506 /* CP will see the sync flag and wait for all DMAs to complete. */
1507 cmd_buffer->state.dma_is_busy = false;
1508 }
1509
1510 if (unlikely(cmd_buffer->device->trace_bo))
1511 radv_cmd_buffer_trace_emit(cmd_buffer);
1512 }
1513
1514 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1515 unsigned size)
1516 {
1517 uint64_t aligned_va = va & ~(SI_CPDMA_ALIGNMENT - 1);
1518 uint64_t aligned_size = ((va + size + SI_CPDMA_ALIGNMENT -1) & ~(SI_CPDMA_ALIGNMENT - 1)) - aligned_va;
1519
1520 si_emit_cp_dma(cmd_buffer, aligned_va, aligned_va,
1521 aligned_size, CP_DMA_USE_L2);
1522 }
1523
1524 static void si_cp_dma_prepare(struct radv_cmd_buffer *cmd_buffer, uint64_t byte_count,
1525 uint64_t remaining_size, unsigned *flags)
1526 {
1527
1528 /* Flush the caches for the first copy only.
1529 * Also wait for the previous CP DMA operations.
1530 */
1531 if (cmd_buffer->state.flush_bits) {
1532 si_emit_cache_flush(cmd_buffer);
1533 *flags |= CP_DMA_RAW_WAIT;
1534 }
1535
1536 /* Do the synchronization after the last dma, so that all data
1537 * is written to memory.
1538 */
1539 if (byte_count == remaining_size)
1540 *flags |= CP_DMA_SYNC;
1541 }
1542
1543 static void si_cp_dma_realign_engine(struct radv_cmd_buffer *cmd_buffer, unsigned size)
1544 {
1545 uint64_t va;
1546 uint32_t offset;
1547 unsigned dma_flags = 0;
1548 unsigned buf_size = SI_CPDMA_ALIGNMENT * 2;
1549 void *ptr;
1550
1551 assert(size < SI_CPDMA_ALIGNMENT);
1552
1553 radv_cmd_buffer_upload_alloc(cmd_buffer, buf_size, SI_CPDMA_ALIGNMENT, &offset, &ptr);
1554
1555 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1556 va += offset;
1557
1558 si_cp_dma_prepare(cmd_buffer, size, size, &dma_flags);
1559
1560 si_emit_cp_dma(cmd_buffer, va, va + SI_CPDMA_ALIGNMENT, size,
1561 dma_flags);
1562 }
1563
1564 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1565 uint64_t src_va, uint64_t dest_va,
1566 uint64_t size)
1567 {
1568 uint64_t main_src_va, main_dest_va;
1569 uint64_t skipped_size = 0, realign_size = 0;
1570
1571 /* Assume that we are not going to sync after the last DMA operation. */
1572 cmd_buffer->state.dma_is_busy = true;
1573
1574 if (cmd_buffer->device->physical_device->rad_info.family <= CHIP_CARRIZO ||
1575 cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY) {
1576 /* If the size is not aligned, we must add a dummy copy at the end
1577 * just to align the internal counter. Otherwise, the DMA engine
1578 * would slow down by an order of magnitude for following copies.
1579 */
1580 if (size % SI_CPDMA_ALIGNMENT)
1581 realign_size = SI_CPDMA_ALIGNMENT - (size % SI_CPDMA_ALIGNMENT);
1582
1583 /* If the copy begins unaligned, we must start copying from the next
1584 * aligned block and the skipped part should be copied after everything
1585 * else has been copied. Only the src alignment matters, not dst.
1586 */
1587 if (src_va % SI_CPDMA_ALIGNMENT) {
1588 skipped_size = SI_CPDMA_ALIGNMENT - (src_va % SI_CPDMA_ALIGNMENT);
1589 /* The main part will be skipped if the size is too small. */
1590 skipped_size = MIN2(skipped_size, size);
1591 size -= skipped_size;
1592 }
1593 }
1594 main_src_va = src_va + skipped_size;
1595 main_dest_va = dest_va + skipped_size;
1596
1597 while (size) {
1598 unsigned dma_flags = 0;
1599 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1600
1601 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1602 /* DMA operations via L2 are coherent and faster.
1603 * TODO: GFX7-GFX9 should also support this but it
1604 * requires tests/benchmarks.
1605 */
1606 dma_flags |= CP_DMA_USE_L2;
1607 }
1608
1609 si_cp_dma_prepare(cmd_buffer, byte_count,
1610 size + skipped_size + realign_size,
1611 &dma_flags);
1612
1613 dma_flags &= ~CP_DMA_SYNC;
1614
1615 si_emit_cp_dma(cmd_buffer, main_dest_va, main_src_va,
1616 byte_count, dma_flags);
1617
1618 size -= byte_count;
1619 main_src_va += byte_count;
1620 main_dest_va += byte_count;
1621 }
1622
1623 if (skipped_size) {
1624 unsigned dma_flags = 0;
1625
1626 si_cp_dma_prepare(cmd_buffer, skipped_size,
1627 size + skipped_size + realign_size,
1628 &dma_flags);
1629
1630 si_emit_cp_dma(cmd_buffer, dest_va, src_va,
1631 skipped_size, dma_flags);
1632 }
1633 if (realign_size)
1634 si_cp_dma_realign_engine(cmd_buffer, realign_size);
1635 }
1636
1637 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1638 uint64_t size, unsigned value)
1639 {
1640
1641 if (!size)
1642 return;
1643
1644 assert(va % 4 == 0 && size % 4 == 0);
1645
1646 /* Assume that we are not going to sync after the last DMA operation. */
1647 cmd_buffer->state.dma_is_busy = true;
1648
1649 while (size) {
1650 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1651 unsigned dma_flags = CP_DMA_CLEAR;
1652
1653 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
1654 /* DMA operations via L2 are coherent and faster.
1655 * TODO: GFX7-GFX9 should also support this but it
1656 * requires tests/benchmarks.
1657 */
1658 dma_flags |= CP_DMA_USE_L2;
1659 }
1660
1661 si_cp_dma_prepare(cmd_buffer, byte_count, size, &dma_flags);
1662
1663 /* Emit the clear packet. */
1664 si_emit_cp_dma(cmd_buffer, va, value, byte_count,
1665 dma_flags);
1666
1667 size -= byte_count;
1668 va += byte_count;
1669 }
1670 }
1671
1672 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer)
1673 {
1674 if (cmd_buffer->device->physical_device->rad_info.chip_class < GFX7)
1675 return;
1676
1677 if (!cmd_buffer->state.dma_is_busy)
1678 return;
1679
1680 /* Issue a dummy DMA that copies zero bytes.
1681 *
1682 * The DMA engine will see that there's no work to do and skip this
1683 * DMA request, however, the CP will see the sync flag and still wait
1684 * for all DMAs to complete.
1685 */
1686 si_emit_cp_dma(cmd_buffer, 0, 0, 0, CP_DMA_SYNC);
1687
1688 cmd_buffer->state.dma_is_busy = false;
1689 }
1690
1691 /* For MSAA sample positions. */
1692 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1693 ((((unsigned)(s0x) & 0xf) << 0) | (((unsigned)(s0y) & 0xf) << 4) | \
1694 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
1695 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
1696 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
1697
1698 /* For obtaining location coordinates from registers */
1699 #define SEXT4(x) ((int)((x) | ((x) & 0x8 ? 0xfffffff0 : 0)))
1700 #define GET_SFIELD(reg, index) SEXT4(((reg) >> ((index) * 4)) & 0xf)
1701 #define GET_SX(reg, index) GET_SFIELD((reg)[(index) / 4], ((index) % 4) * 2)
1702 #define GET_SY(reg, index) GET_SFIELD((reg)[(index) / 4], ((index) % 4) * 2 + 1)
1703
1704 /* 1x MSAA */
1705 static const uint32_t sample_locs_1x =
1706 FILL_SREG(0, 0, 0, 0, 0, 0, 0, 0);
1707 static const unsigned max_dist_1x = 0;
1708 static const uint64_t centroid_priority_1x = 0x0000000000000000ull;
1709
1710 /* 2xMSAA */
1711 static const uint32_t sample_locs_2x =
1712 FILL_SREG(4,4, -4, -4, 0, 0, 0, 0);
1713 static const unsigned max_dist_2x = 4;
1714 static const uint64_t centroid_priority_2x = 0x1010101010101010ull;
1715
1716 /* 4xMSAA */
1717 static const uint32_t sample_locs_4x =
1718 FILL_SREG(-2,-6, 6, -2, -6, 2, 2, 6);
1719 static const unsigned max_dist_4x = 6;
1720 static const uint64_t centroid_priority_4x = 0x3210321032103210ull;
1721
1722 /* 8xMSAA */
1723 static const uint32_t sample_locs_8x[] = {
1724 FILL_SREG( 1,-3, -1, 3, 5, 1, -3,-5),
1725 FILL_SREG(-5, 5, -7,-1, 3, 7, 7,-7),
1726 /* The following are unused by hardware, but we emit them to IBs
1727 * instead of multiple SET_CONTEXT_REG packets. */
1728 0,
1729 0,
1730 };
1731 static const unsigned max_dist_8x = 7;
1732 static const uint64_t centroid_priority_8x = 0x7654321076543210ull;
1733
1734 unsigned radv_get_default_max_sample_dist(int log_samples)
1735 {
1736 unsigned max_dist[] = {
1737 max_dist_1x,
1738 max_dist_2x,
1739 max_dist_4x,
1740 max_dist_8x,
1741 };
1742 return max_dist[log_samples];
1743 }
1744
1745 void radv_emit_default_sample_locations(struct radeon_cmdbuf *cs, int nr_samples)
1746 {
1747 switch (nr_samples) {
1748 default:
1749 case 1:
1750 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1751 radeon_emit(cs, (uint32_t)centroid_priority_1x);
1752 radeon_emit(cs, centroid_priority_1x >> 32);
1753 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_1x);
1754 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_1x);
1755 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_1x);
1756 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_1x);
1757 break;
1758 case 2:
1759 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1760 radeon_emit(cs, (uint32_t)centroid_priority_2x);
1761 radeon_emit(cs, centroid_priority_2x >> 32);
1762 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x);
1763 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x);
1764 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x);
1765 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x);
1766 break;
1767 case 4:
1768 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1769 radeon_emit(cs, (uint32_t)centroid_priority_4x);
1770 radeon_emit(cs, centroid_priority_4x >> 32);
1771 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x);
1772 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x);
1773 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x);
1774 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x);
1775 break;
1776 case 8:
1777 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1778 radeon_emit(cs, (uint32_t)centroid_priority_8x);
1779 radeon_emit(cs, centroid_priority_8x >> 32);
1780 radeon_set_context_reg_seq(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
1781 radeon_emit_array(cs, sample_locs_8x, 4);
1782 radeon_emit_array(cs, sample_locs_8x, 4);
1783 radeon_emit_array(cs, sample_locs_8x, 4);
1784 radeon_emit_array(cs, sample_locs_8x, 2);
1785 break;
1786 }
1787 }
1788
1789 static void radv_get_sample_position(struct radv_device *device,
1790 unsigned sample_count,
1791 unsigned sample_index, float *out_value)
1792 {
1793 const uint32_t *sample_locs;
1794
1795 switch (sample_count) {
1796 case 1:
1797 default:
1798 sample_locs = &sample_locs_1x;
1799 break;
1800 case 2:
1801 sample_locs = &sample_locs_2x;
1802 break;
1803 case 4:
1804 sample_locs = &sample_locs_4x;
1805 break;
1806 case 8:
1807 sample_locs = sample_locs_8x;
1808 break;
1809 }
1810
1811 out_value[0] = (GET_SX(sample_locs, sample_index) + 8) / 16.0f;
1812 out_value[1] = (GET_SY(sample_locs, sample_index) + 8) / 16.0f;
1813 }
1814
1815 void radv_device_init_msaa(struct radv_device *device)
1816 {
1817 int i;
1818
1819 radv_get_sample_position(device, 1, 0, device->sample_locations_1x[0]);
1820
1821 for (i = 0; i < 2; i++)
1822 radv_get_sample_position(device, 2, i, device->sample_locations_2x[i]);
1823 for (i = 0; i < 4; i++)
1824 radv_get_sample_position(device, 4, i, device->sample_locations_4x[i]);
1825 for (i = 0; i < 8; i++)
1826 radv_get_sample_position(device, 8, i, device->sample_locations_8x[i]);
1827 }