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radv/gfx10: set cache control registers
[mesa.git] / src / amd / vulkan / si_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based on si_state.c
6 * Copyright © 2015 Advanced Micro Devices, Inc.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 /* command buffer handling for AMD GCN */
29
30 #include "radv_private.h"
31 #include "radv_shader.h"
32 #include "radv_cs.h"
33 #include "sid.h"
34 #include "radv_util.h"
35 #include "main/macros.h"
36
37 static void
38 si_write_harvested_raster_configs(struct radv_physical_device *physical_device,
39 struct radeon_cmdbuf *cs,
40 unsigned raster_config,
41 unsigned raster_config_1)
42 {
43 unsigned num_se = MAX2(physical_device->rad_info.max_se, 1);
44 unsigned raster_config_se[4];
45 unsigned se;
46
47 ac_get_harvested_configs(&physical_device->rad_info,
48 raster_config,
49 &raster_config_1,
50 raster_config_se);
51
52 for (se = 0; se < num_se; se++) {
53 /* GRBM_GFX_INDEX has a different offset on GFX6 and GFX7+ */
54 if (physical_device->rad_info.chip_class < GFX7)
55 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
56 S_00802C_SE_INDEX(se) |
57 S_00802C_SH_BROADCAST_WRITES(1) |
58 S_00802C_INSTANCE_BROADCAST_WRITES(1));
59 else
60 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
61 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
62 S_030800_INSTANCE_BROADCAST_WRITES(1));
63 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
64 }
65
66 /* GRBM_GFX_INDEX has a different offset on GFX6 and GFX7+ */
67 if (physical_device->rad_info.chip_class < GFX7)
68 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
69 S_00802C_SE_BROADCAST_WRITES(1) |
70 S_00802C_SH_BROADCAST_WRITES(1) |
71 S_00802C_INSTANCE_BROADCAST_WRITES(1));
72 else
73 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
74 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
75 S_030800_INSTANCE_BROADCAST_WRITES(1));
76
77 if (physical_device->rad_info.chip_class >= GFX7)
78 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
79 }
80
81 void
82 si_emit_compute(struct radv_physical_device *physical_device,
83 struct radeon_cmdbuf *cs)
84 {
85 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
86 radeon_emit(cs, 0);
87 radeon_emit(cs, 0);
88 radeon_emit(cs, 0);
89
90 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
91 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
92 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
93 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
94
95 if (physical_device->rad_info.chip_class >= GFX7) {
96 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
97 radeon_set_sh_reg_seq(cs,
98 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
99 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
100 S_00B858_SH1_CU_EN(0xffff));
101 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
102 S_00B858_SH1_CU_EN(0xffff));
103 }
104
105 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
106 * and is now per pipe, so it should be handled in the
107 * kernel if we want to use something other than the default value,
108 * which is now 0x22f.
109 */
110 if (physical_device->rad_info.chip_class <= GFX6) {
111 /* XXX: This should be:
112 * (number of compute units) * 4 * (waves per simd) - 1 */
113
114 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
115 0x190 /* Default value */);
116 }
117 }
118
119 /* 12.4 fixed-point */
120 static unsigned radv_pack_float_12p4(float x)
121 {
122 return x <= 0 ? 0 :
123 x >= 4096 ? 0xffff : x * 16;
124 }
125
126 static void
127 si_set_raster_config(struct radv_physical_device *physical_device,
128 struct radeon_cmdbuf *cs)
129 {
130 unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
131 unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
132 unsigned raster_config, raster_config_1;
133
134 ac_get_raster_config(&physical_device->rad_info,
135 &raster_config,
136 &raster_config_1, NULL);
137
138 /* Always use the default config when all backends are enabled
139 * (or when we failed to determine the enabled backends).
140 */
141 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
142 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG,
143 raster_config);
144 if (physical_device->rad_info.chip_class >= GFX7)
145 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1,
146 raster_config_1);
147 } else {
148 si_write_harvested_raster_configs(physical_device, cs,
149 raster_config,
150 raster_config_1);
151 }
152 }
153
154 void
155 si_emit_graphics(struct radv_physical_device *physical_device,
156 struct radeon_cmdbuf *cs)
157 {
158 int i;
159
160 /* Only GFX6 can disable CLEAR_STATE for now. */
161 assert(physical_device->has_clear_state ||
162 physical_device->rad_info.chip_class == GFX6);
163
164 radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
165 radeon_emit(cs, CONTEXT_CONTROL_LOAD_ENABLE(1));
166 radeon_emit(cs, CONTEXT_CONTROL_SHADOW_ENABLE(1));
167
168 if (physical_device->has_clear_state) {
169 radeon_emit(cs, PKT3(PKT3_CLEAR_STATE, 0, 0));
170 radeon_emit(cs, 0);
171 }
172
173 if (physical_device->rad_info.chip_class <= GFX8)
174 si_set_raster_config(physical_device, cs);
175
176 radeon_set_context_reg(cs, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
177 if (!physical_device->has_clear_state)
178 radeon_set_context_reg(cs, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
179
180 /* FIXME calculate these values somehow ??? */
181 if (physical_device->rad_info.chip_class <= GFX8) {
182 radeon_set_context_reg(cs, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
183 radeon_set_context_reg(cs, R_028A58_VGT_ES_PER_GS, 0x40);
184 }
185
186 if (!physical_device->has_clear_state) {
187 radeon_set_context_reg(cs, R_028A5C_VGT_GS_PER_VS, 0x2);
188 radeon_set_context_reg(cs, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
189 radeon_set_context_reg(cs, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
190 }
191
192 radeon_set_context_reg(cs, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
193 if (!physical_device->has_clear_state)
194 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, 0x0);
195 if (physical_device->rad_info.chip_class < GFX7)
196 radeon_set_config_reg(cs, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
197 S_008A14_CLIP_VTX_REORDER_ENA(1));
198
199 if (!physical_device->has_clear_state)
200 radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
201
202 /* CLEAR_STATE doesn't clear these correctly on certain generations.
203 * I don't know why. Deduced by trial and error.
204 */
205 if (physical_device->rad_info.chip_class <= GFX7) {
206 radeon_set_context_reg(cs, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
207 radeon_set_context_reg(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL,
208 S_028204_WINDOW_OFFSET_DISABLE(1));
209 radeon_set_context_reg(cs, R_028240_PA_SC_GENERIC_SCISSOR_TL,
210 S_028240_WINDOW_OFFSET_DISABLE(1));
211 radeon_set_context_reg(cs, R_028244_PA_SC_GENERIC_SCISSOR_BR,
212 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
213 radeon_set_context_reg(cs, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
214 radeon_set_context_reg(cs, R_028034_PA_SC_SCREEN_SCISSOR_BR,
215 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
216 }
217
218 if (!physical_device->has_clear_state) {
219 for (i = 0; i < 16; i++) {
220 radeon_set_context_reg(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
221 radeon_set_context_reg(cs, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
222 }
223 }
224
225 if (!physical_device->has_clear_state) {
226 radeon_set_context_reg(cs, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
227 radeon_set_context_reg(cs, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
228 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on GFX6 */
229 radeon_set_context_reg(cs, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
230 radeon_set_context_reg(cs, R_028820_PA_CL_NANINF_CNTL, 0);
231 radeon_set_context_reg(cs, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
232 radeon_set_context_reg(cs, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
233 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
234 }
235
236 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE,
237 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
238 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
239
240 if (physical_device->rad_info.chip_class >= GFX9) {
241 radeon_set_uconfig_reg(cs, R_030920_VGT_MAX_VTX_INDX, ~0);
242 radeon_set_uconfig_reg(cs, R_030924_VGT_MIN_VTX_INDX, 0);
243 radeon_set_uconfig_reg(cs, R_030928_VGT_INDX_OFFSET, 0);
244 } else {
245 /* These registers, when written, also overwrite the
246 * CLEAR_STATE context, so we can't rely on CLEAR_STATE setting
247 * them. It would be an issue if there was another UMD
248 * changing them.
249 */
250 radeon_set_context_reg(cs, R_028400_VGT_MAX_VTX_INDX, ~0);
251 radeon_set_context_reg(cs, R_028404_VGT_MIN_VTX_INDX, 0);
252 radeon_set_context_reg(cs, R_028408_VGT_INDX_OFFSET, 0);
253 }
254
255 if (physical_device->rad_info.chip_class >= GFX7) {
256 if (physical_device->rad_info.chip_class >= GFX9) {
257 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
258 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
259 } else {
260 radeon_set_sh_reg(cs, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
261 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
262 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
263 S_00B41C_WAVE_LIMIT(0x3F));
264 radeon_set_sh_reg(cs, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
265 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
266 /* If this is 0, Bonaire can hang even if GS isn't being used.
267 * Other chips are unaffected. These are suboptimal values,
268 * but we don't use on-chip GS.
269 */
270 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL,
271 S_028A44_ES_VERTS_PER_SUBGRP(64) |
272 S_028A44_GS_PRIMS_PER_SUBGRP(4));
273 }
274 radeon_set_sh_reg(cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
275 S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
276
277 if (physical_device->rad_info.num_good_cu_per_sh <= 4) {
278 /* Too few available compute units per SH. Disallowing
279 * VS to run on CU0 could hurt us more than late VS
280 * allocation would help.
281 *
282 * LATE_ALLOC_VS = 2 is the highest safe number.
283 */
284 radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
285 S_00B118_CU_EN(0xffff) | S_00B118_WAVE_LIMIT(0x3F) );
286 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
287 } else {
288 /* Set LATE_ALLOC_VS == 31. It should be less than
289 * the number of scratch waves. Limitations:
290 * - VS can't execute on CU0.
291 * - If HS writes outputs to LDS, LS can't execute on CU0.
292 */
293 radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
294 S_00B118_CU_EN(0xfffe) | S_00B118_WAVE_LIMIT(0x3F));
295 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
296 }
297
298 radeon_set_sh_reg(cs, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
299 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
300 }
301
302 if (physical_device->rad_info.chip_class >= GFX10) {
303 radeon_set_context_reg(cs, R_02807C_DB_RMI_L2_CACHE_CONTROL,
304 S_02807C_Z_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
305 S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
306 S_02807C_HTILE_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
307 S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
308 S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA_RD) |
309 S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA_RD) |
310 S_02807C_HTILE_RD_POLICY(V_02807C_CACHE_NOA_RD));
311
312 radeon_set_context_reg(cs, R_028410_CB_RMI_GL2_CACHE_CONTROL,
313 S_028410_CMASK_WR_POLICY(V_028410_CACHE_STREAM_WR) |
314 S_028410_FMASK_WR_POLICY(V_028410_CACHE_STREAM_WR) |
315 S_028410_DCC_WR_POLICY(V_028410_CACHE_STREAM_WR) |
316 S_028410_COLOR_WR_POLICY(V_028410_CACHE_STREAM_WR) |
317 S_028410_CMASK_RD_POLICY(V_028410_CACHE_NOA_RD) |
318 S_028410_FMASK_RD_POLICY(V_028410_CACHE_NOA_RD) |
319 S_028410_DCC_RD_POLICY(V_028410_CACHE_NOA_RD) |
320 S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_RD));
321 }
322
323 if (physical_device->rad_info.chip_class >= GFX8) {
324 uint32_t vgt_tess_distribution;
325
326 vgt_tess_distribution = S_028B50_ACCUM_ISOLINE(32) |
327 S_028B50_ACCUM_TRI(11) |
328 S_028B50_ACCUM_QUAD(11) |
329 S_028B50_DONUT_SPLIT(16);
330
331 if (physical_device->rad_info.family == CHIP_FIJI ||
332 physical_device->rad_info.family >= CHIP_POLARIS10)
333 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
334
335 radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION,
336 vgt_tess_distribution);
337 } else if (!physical_device->has_clear_state) {
338 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
339 radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
340 }
341
342 if (physical_device->rad_info.chip_class >= GFX9) {
343 unsigned num_se = physical_device->rad_info.max_se;
344 unsigned pc_lines = 0;
345 unsigned max_alloc_count = 0;
346
347 switch (physical_device->rad_info.family) {
348 case CHIP_VEGA10:
349 case CHIP_VEGA12:
350 case CHIP_VEGA20:
351 pc_lines = 4096;
352 break;
353 case CHIP_RAVEN:
354 case CHIP_RAVEN2:
355 case CHIP_NAVI10:
356 case CHIP_NAVI12:
357 pc_lines = 1024;
358 break;
359 case CHIP_NAVI14:
360 pc_lines = 512;
361 break;
362 default:
363 assert(0);
364 }
365
366 if (physical_device->rad_info.chip_class >= GFX10) {
367 max_alloc_count = pc_lines / 3;
368 } else {
369 max_alloc_count = MIN2(128, pc_lines / (4 * num_se));
370 }
371
372 radeon_set_context_reg(cs, R_028C48_PA_SC_BINNER_CNTL_1,
373 S_028C48_MAX_ALLOC_COUNT(max_alloc_count) |
374 S_028C48_MAX_PRIM_PER_BATCH(1023));
375 radeon_set_context_reg(cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
376 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
377 radeon_set_uconfig_reg(cs, R_030968_VGT_INSTANCE_BASE_ID, 0);
378 }
379
380 unsigned tmp = (unsigned)(1.0 * 8.0);
381 radeon_set_context_reg_seq(cs, R_028A00_PA_SU_POINT_SIZE, 1);
382 radeon_emit(cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
383 radeon_set_context_reg_seq(cs, R_028A04_PA_SU_POINT_MINMAX, 1);
384 radeon_emit(cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
385 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2)));
386
387 if (!physical_device->has_clear_state) {
388 radeon_set_context_reg(cs, R_028004_DB_COUNT_CONTROL,
389 S_028004_ZPASS_INCREMENT_DISABLE(1));
390 }
391
392 /* Enable the Polaris small primitive filter control.
393 * XXX: There is possibly an issue when MSAA is off (see RadeonSI
394 * has_msaa_sample_loc_bug). But this doesn't seem to regress anything,
395 * and AMDVLK doesn't have a workaround as well.
396 */
397 if (physical_device->rad_info.family >= CHIP_POLARIS10) {
398 unsigned small_prim_filter_cntl =
399 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
400 /* Workaround for a hw line bug. */
401 S_028830_LINE_FILTER_DISABLE(physical_device->rad_info.family <= CHIP_POLARIS12);
402
403 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
404 small_prim_filter_cntl);
405 }
406
407 si_emit_compute(physical_device, cs);
408 }
409
410 void
411 cik_create_gfx_config(struct radv_device *device)
412 {
413 struct radeon_cmdbuf *cs = device->ws->cs_create(device->ws, RING_GFX);
414 if (!cs)
415 return;
416
417 si_emit_graphics(device->physical_device, cs);
418
419 while (cs->cdw & 7) {
420 if (device->physical_device->rad_info.gfx_ib_pad_with_type2)
421 radeon_emit(cs, 0x80000000);
422 else
423 radeon_emit(cs, 0xffff1000);
424 }
425
426 device->gfx_init = device->ws->buffer_create(device->ws,
427 cs->cdw * 4, 4096,
428 RADEON_DOMAIN_GTT,
429 RADEON_FLAG_CPU_ACCESS|
430 RADEON_FLAG_NO_INTERPROCESS_SHARING |
431 RADEON_FLAG_READ_ONLY,
432 RADV_BO_PRIORITY_CS);
433 if (!device->gfx_init)
434 goto fail;
435
436 void *map = device->ws->buffer_map(device->gfx_init);
437 if (!map) {
438 device->ws->buffer_destroy(device->gfx_init);
439 device->gfx_init = NULL;
440 goto fail;
441 }
442 memcpy(map, cs->buf, cs->cdw * 4);
443
444 device->ws->buffer_unmap(device->gfx_init);
445 device->gfx_init_size_dw = cs->cdw;
446 fail:
447 device->ws->cs_destroy(cs);
448 }
449
450 static void
451 get_viewport_xform(const VkViewport *viewport,
452 float scale[3], float translate[3])
453 {
454 float x = viewport->x;
455 float y = viewport->y;
456 float half_width = 0.5f * viewport->width;
457 float half_height = 0.5f * viewport->height;
458 double n = viewport->minDepth;
459 double f = viewport->maxDepth;
460
461 scale[0] = half_width;
462 translate[0] = half_width + x;
463 scale[1] = half_height;
464 translate[1] = half_height + y;
465
466 scale[2] = (f - n);
467 translate[2] = n;
468 }
469
470 void
471 si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
472 int count, const VkViewport *viewports)
473 {
474 int i;
475
476 assert(count);
477 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
478 first_vp * 4 * 6, count * 6);
479
480 for (i = 0; i < count; i++) {
481 float scale[3], translate[3];
482
483
484 get_viewport_xform(&viewports[i], scale, translate);
485 radeon_emit(cs, fui(scale[0]));
486 radeon_emit(cs, fui(translate[0]));
487 radeon_emit(cs, fui(scale[1]));
488 radeon_emit(cs, fui(translate[1]));
489 radeon_emit(cs, fui(scale[2]));
490 radeon_emit(cs, fui(translate[2]));
491 }
492
493 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 +
494 first_vp * 4 * 2, count * 2);
495 for (i = 0; i < count; i++) {
496 float zmin = MIN2(viewports[i].minDepth, viewports[i].maxDepth);
497 float zmax = MAX2(viewports[i].minDepth, viewports[i].maxDepth);
498 radeon_emit(cs, fui(zmin));
499 radeon_emit(cs, fui(zmax));
500 }
501 }
502
503 static VkRect2D si_scissor_from_viewport(const VkViewport *viewport)
504 {
505 float scale[3], translate[3];
506 VkRect2D rect;
507
508 get_viewport_xform(viewport, scale, translate);
509
510 rect.offset.x = translate[0] - fabs(scale[0]);
511 rect.offset.y = translate[1] - fabs(scale[1]);
512 rect.extent.width = ceilf(translate[0] + fabs(scale[0])) - rect.offset.x;
513 rect.extent.height = ceilf(translate[1] + fabs(scale[1])) - rect.offset.y;
514
515 return rect;
516 }
517
518 static VkRect2D si_intersect_scissor(const VkRect2D *a, const VkRect2D *b) {
519 VkRect2D ret;
520 ret.offset.x = MAX2(a->offset.x, b->offset.x);
521 ret.offset.y = MAX2(a->offset.y, b->offset.y);
522 ret.extent.width = MIN2(a->offset.x + a->extent.width,
523 b->offset.x + b->extent.width) - ret.offset.x;
524 ret.extent.height = MIN2(a->offset.y + a->extent.height,
525 b->offset.y + b->extent.height) - ret.offset.y;
526 return ret;
527 }
528
529 void
530 si_write_scissors(struct radeon_cmdbuf *cs, int first,
531 int count, const VkRect2D *scissors,
532 const VkViewport *viewports, bool can_use_guardband)
533 {
534 int i;
535 float scale[3], translate[3], guardband_x = INFINITY, guardband_y = INFINITY;
536 const float max_range = 32767.0f;
537 if (!count)
538 return;
539
540 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + first * 4 * 2, count * 2);
541 for (i = 0; i < count; i++) {
542 VkRect2D viewport_scissor = si_scissor_from_viewport(viewports + i);
543 VkRect2D scissor = si_intersect_scissor(&scissors[i], &viewport_scissor);
544
545 get_viewport_xform(viewports + i, scale, translate);
546 scale[0] = fabsf(scale[0]);
547 scale[1] = fabsf(scale[1]);
548
549 if (scale[0] < 0.5)
550 scale[0] = 0.5;
551 if (scale[1] < 0.5)
552 scale[1] = 0.5;
553
554 guardband_x = MIN2(guardband_x, (max_range - fabsf(translate[0])) / scale[0]);
555 guardband_y = MIN2(guardband_y, (max_range - fabsf(translate[1])) / scale[1]);
556
557 radeon_emit(cs, S_028250_TL_X(scissor.offset.x) |
558 S_028250_TL_Y(scissor.offset.y) |
559 S_028250_WINDOW_OFFSET_DISABLE(1));
560 radeon_emit(cs, S_028254_BR_X(scissor.offset.x + scissor.extent.width) |
561 S_028254_BR_Y(scissor.offset.y + scissor.extent.height));
562 }
563 if (!can_use_guardband) {
564 guardband_x = 1.0;
565 guardband_y = 1.0;
566 }
567
568 radeon_set_context_reg_seq(cs, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
569 radeon_emit(cs, fui(guardband_y));
570 radeon_emit(cs, fui(1.0));
571 radeon_emit(cs, fui(guardband_x));
572 radeon_emit(cs, fui(1.0));
573 }
574
575 static inline unsigned
576 radv_prims_for_vertices(struct radv_prim_vertex_count *info, unsigned num)
577 {
578 if (num == 0)
579 return 0;
580
581 if (info->incr == 0)
582 return 0;
583
584 if (num < info->min)
585 return 0;
586
587 return 1 + ((num - info->min) / info->incr);
588 }
589
590 uint32_t
591 si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
592 bool instanced_draw, bool indirect_draw,
593 bool count_from_stream_output,
594 uint32_t draw_vertex_count)
595 {
596 enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
597 enum radeon_family family = cmd_buffer->device->physical_device->rad_info.family;
598 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
599 const unsigned max_primgroup_in_wave = 2;
600 /* SWITCH_ON_EOP(0) is always preferable. */
601 bool wd_switch_on_eop = false;
602 bool ia_switch_on_eop = false;
603 bool ia_switch_on_eoi = false;
604 bool partial_vs_wave = false;
605 bool partial_es_wave = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.partial_es_wave;
606 bool multi_instances_smaller_than_primgroup;
607
608 multi_instances_smaller_than_primgroup = indirect_draw;
609 if (!multi_instances_smaller_than_primgroup && instanced_draw) {
610 uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
611 if (num_prims < cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.primgroup_size)
612 multi_instances_smaller_than_primgroup = true;
613 }
614
615 ia_switch_on_eoi = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.ia_switch_on_eoi;
616 partial_vs_wave = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.partial_vs_wave;
617
618 if (chip_class >= GFX7) {
619 wd_switch_on_eop = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.wd_switch_on_eop;
620
621 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
622 * We don't know that for indirect drawing, so treat it as
623 * always problematic. */
624 if (family == CHIP_HAWAII &&
625 (instanced_draw || indirect_draw))
626 wd_switch_on_eop = true;
627
628 /* Performance recommendation for 4 SE Gfx7-8 parts if
629 * instances are smaller than a primgroup.
630 * Assume indirect draws always use small instances.
631 * This is needed for good VS wave utilization.
632 */
633 if (chip_class <= GFX8 &&
634 info->max_se == 4 &&
635 multi_instances_smaller_than_primgroup)
636 wd_switch_on_eop = true;
637
638 /* Required on GFX7 and later. */
639 if (info->max_se > 2 && !wd_switch_on_eop)
640 ia_switch_on_eoi = true;
641
642 /* Required by Hawaii and, for some special cases, by GFX8. */
643 if (ia_switch_on_eoi &&
644 (family == CHIP_HAWAII ||
645 (chip_class == GFX8 &&
646 /* max primgroup in wave is always 2 - leave this for documentation */
647 (radv_pipeline_has_gs(cmd_buffer->state.pipeline) || max_primgroup_in_wave != 2))))
648 partial_vs_wave = true;
649
650 /* Instancing bug on Bonaire. */
651 if (family == CHIP_BONAIRE && ia_switch_on_eoi &&
652 (instanced_draw || indirect_draw))
653 partial_vs_wave = true;
654
655 /* Hardware requirement when drawing primitives from a stream
656 * output buffer.
657 */
658 if (count_from_stream_output)
659 wd_switch_on_eop = true;
660
661 /* If the WD switch is false, the IA switch must be false too. */
662 assert(wd_switch_on_eop || !ia_switch_on_eop);
663 }
664 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
665 if (chip_class <= GFX8 && ia_switch_on_eoi)
666 partial_es_wave = true;
667
668 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline)) {
669 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
670 * The hw doc says all multi-SE chips are affected, but amdgpu-pro Vulkan
671 * only applies it to Hawaii. Do what amdgpu-pro Vulkan does.
672 */
673 if (family == CHIP_HAWAII && ia_switch_on_eoi) {
674 bool set_vgt_flush = indirect_draw;
675 if (!set_vgt_flush && instanced_draw) {
676 uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
677 if (num_prims <= 1)
678 set_vgt_flush = true;
679 }
680 if (set_vgt_flush)
681 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
682 }
683 }
684
685 return cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.base |
686 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
687 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
688 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
689 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
690 S_028AA8_WD_SWITCH_ON_EOP(chip_class >= GFX7 ? wd_switch_on_eop : 0);
691
692 }
693
694 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
695 enum chip_class chip_class,
696 bool is_mec,
697 unsigned event, unsigned event_flags,
698 unsigned data_sel,
699 uint64_t va,
700 uint32_t new_fence,
701 uint64_t gfx9_eop_bug_va)
702 {
703 unsigned op = EVENT_TYPE(event) |
704 EVENT_INDEX(5) |
705 event_flags;
706 unsigned is_gfx8_mec = is_mec && chip_class < GFX9;
707 unsigned sel = EOP_DATA_SEL(data_sel);
708
709 /* Wait for write confirmation before writing data, but don't send
710 * an interrupt. */
711 if (data_sel != EOP_DATA_SEL_DISCARD)
712 sel |= EOP_INT_SEL(EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM);
713
714 if (chip_class >= GFX9 || is_gfx8_mec) {
715 /* A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion
716 * counters) must immediately precede every timestamp event to
717 * prevent a GPU hang on GFX9.
718 */
719 if (chip_class == GFX9 && !is_mec) {
720 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
721 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
722 radeon_emit(cs, gfx9_eop_bug_va);
723 radeon_emit(cs, gfx9_eop_bug_va >> 32);
724 }
725
726 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, is_gfx8_mec ? 5 : 6, false));
727 radeon_emit(cs, op);
728 radeon_emit(cs, sel);
729 radeon_emit(cs, va); /* address lo */
730 radeon_emit(cs, va >> 32); /* address hi */
731 radeon_emit(cs, new_fence); /* immediate data lo */
732 radeon_emit(cs, 0); /* immediate data hi */
733 if (!is_gfx8_mec)
734 radeon_emit(cs, 0); /* unused */
735 } else {
736 if (chip_class == GFX7 ||
737 chip_class == GFX8) {
738 /* Two EOP events are required to make all engines go idle
739 * (and optional cache flushes executed) before the timestamp
740 * is written.
741 */
742 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false));
743 radeon_emit(cs, op);
744 radeon_emit(cs, va);
745 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
746 radeon_emit(cs, 0); /* immediate data */
747 radeon_emit(cs, 0); /* unused */
748 }
749
750 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false));
751 radeon_emit(cs, op);
752 radeon_emit(cs, va);
753 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
754 radeon_emit(cs, new_fence); /* immediate data */
755 radeon_emit(cs, 0); /* unused */
756 }
757 }
758
759 void
760 radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va,
761 uint32_t ref, uint32_t mask)
762 {
763 assert(op == WAIT_REG_MEM_EQUAL ||
764 op == WAIT_REG_MEM_NOT_EQUAL ||
765 op == WAIT_REG_MEM_GREATER_OR_EQUAL);
766
767 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, false));
768 radeon_emit(cs, op | WAIT_REG_MEM_MEM_SPACE(1));
769 radeon_emit(cs, va);
770 radeon_emit(cs, va >> 32);
771 radeon_emit(cs, ref); /* reference value */
772 radeon_emit(cs, mask); /* mask */
773 radeon_emit(cs, 4); /* poll interval */
774 }
775
776 static void
777 si_emit_acquire_mem(struct radeon_cmdbuf *cs,
778 bool is_mec,
779 bool is_gfx9,
780 unsigned cp_coher_cntl)
781 {
782 if (is_mec || is_gfx9) {
783 uint32_t hi_val = is_gfx9 ? 0xffffff : 0xff;
784 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, false) |
785 PKT3_SHADER_TYPE_S(is_mec));
786 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
787 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
788 radeon_emit(cs, hi_val); /* CP_COHER_SIZE_HI */
789 radeon_emit(cs, 0); /* CP_COHER_BASE */
790 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
791 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
792 } else {
793 /* ACQUIRE_MEM is only required on a compute ring. */
794 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, false));
795 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
796 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
797 radeon_emit(cs, 0); /* CP_COHER_BASE */
798 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
799 }
800 }
801
802 void
803 si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
804 enum chip_class chip_class,
805 uint32_t *flush_cnt,
806 uint64_t flush_va,
807 bool is_mec,
808 enum radv_cmd_flush_bits flush_bits,
809 uint64_t gfx9_eop_bug_va)
810 {
811 unsigned cp_coher_cntl = 0;
812 uint32_t flush_cb_db = flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
813 RADV_CMD_FLAG_FLUSH_AND_INV_DB);
814
815 if (flush_bits & RADV_CMD_FLAG_INV_ICACHE)
816 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
817 if (flush_bits & RADV_CMD_FLAG_INV_SCACHE)
818 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
819
820 if (chip_class <= GFX8) {
821 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
822 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
823 S_0085F0_CB0_DEST_BASE_ENA(1) |
824 S_0085F0_CB1_DEST_BASE_ENA(1) |
825 S_0085F0_CB2_DEST_BASE_ENA(1) |
826 S_0085F0_CB3_DEST_BASE_ENA(1) |
827 S_0085F0_CB4_DEST_BASE_ENA(1) |
828 S_0085F0_CB5_DEST_BASE_ENA(1) |
829 S_0085F0_CB6_DEST_BASE_ENA(1) |
830 S_0085F0_CB7_DEST_BASE_ENA(1);
831
832 /* Necessary for DCC */
833 if (chip_class >= GFX8) {
834 si_cs_emit_write_event_eop(cs,
835 chip_class,
836 is_mec,
837 V_028A90_FLUSH_AND_INV_CB_DATA_TS,
838 0,
839 EOP_DATA_SEL_DISCARD,
840 0, 0,
841 gfx9_eop_bug_va);
842 }
843 }
844 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
845 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
846 S_0085F0_DB_DEST_BASE_ENA(1);
847 }
848 }
849
850 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) {
851 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
852 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
853 }
854
855 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) {
856 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
857 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
858 }
859
860 if (flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) {
861 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
862 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
863 } else if (flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) {
864 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
865 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
866 }
867
868 if (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) {
869 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
870 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
871 }
872
873 if (chip_class >= GFX9 && flush_cb_db) {
874 unsigned cb_db_event, tc_flags;
875
876 /* Set the CB/DB flush event. */
877 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
878
879 /* These are the only allowed combinations. If you need to
880 * do multiple operations at once, do them separately.
881 * All operations that invalidate L2 also seem to invalidate
882 * metadata. Volatile (VOL) and WC flushes are not listed here.
883 *
884 * TC | TC_WB = writeback & invalidate L2 & L1
885 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
886 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
887 * TC | TC_NC = invalidate L2 for MTYPE == NC
888 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
889 * TCL1 = invalidate L1
890 */
891 tc_flags = EVENT_TC_ACTION_ENA |
892 EVENT_TC_MD_ACTION_ENA;
893
894 /* Ideally flush TC together with CB/DB. */
895 if (flush_bits & RADV_CMD_FLAG_INV_L2) {
896 /* Writeback and invalidate everything in L2 & L1. */
897 tc_flags = EVENT_TC_ACTION_ENA |
898 EVENT_TC_WB_ACTION_ENA;
899
900
901 /* Clear the flags. */
902 flush_bits &= ~(RADV_CMD_FLAG_INV_L2 |
903 RADV_CMD_FLAG_WB_L2 |
904 RADV_CMD_FLAG_INV_VCACHE);
905 }
906 assert(flush_cnt);
907 (*flush_cnt)++;
908
909 si_cs_emit_write_event_eop(cs, chip_class, false, cb_db_event, tc_flags,
910 EOP_DATA_SEL_VALUE_32BIT,
911 flush_va, *flush_cnt,
912 gfx9_eop_bug_va);
913 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, flush_va,
914 *flush_cnt, 0xffffffff);
915 }
916
917 /* VGT state sync */
918 if (flush_bits & RADV_CMD_FLAG_VGT_FLUSH) {
919 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
920 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
921 }
922
923 /* VGT streamout state sync */
924 if (flush_bits & RADV_CMD_FLAG_VGT_STREAMOUT_SYNC) {
925 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
926 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
927 }
928
929 /* Make sure ME is idle (it executes most packets) before continuing.
930 * This prevents read-after-write hazards between PFP and ME.
931 */
932 if ((cp_coher_cntl ||
933 (flush_bits & (RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
934 RADV_CMD_FLAG_INV_VCACHE |
935 RADV_CMD_FLAG_INV_L2 |
936 RADV_CMD_FLAG_WB_L2))) &&
937 !is_mec) {
938 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
939 radeon_emit(cs, 0);
940 }
941
942 if ((flush_bits & RADV_CMD_FLAG_INV_L2) ||
943 (chip_class <= GFX7 && (flush_bits & RADV_CMD_FLAG_WB_L2))) {
944 si_emit_acquire_mem(cs, is_mec, chip_class >= GFX9,
945 cp_coher_cntl |
946 S_0085F0_TC_ACTION_ENA(1) |
947 S_0085F0_TCL1_ACTION_ENA(1) |
948 S_0301F0_TC_WB_ACTION_ENA(chip_class >= GFX8));
949 cp_coher_cntl = 0;
950 } else {
951 if(flush_bits & RADV_CMD_FLAG_WB_L2) {
952 /* WB = write-back
953 * NC = apply to non-coherent MTYPEs
954 * (i.e. MTYPE <= 1, which is what we use everywhere)
955 *
956 * WB doesn't work without NC.
957 */
958 si_emit_acquire_mem(cs, is_mec,
959 chip_class >= GFX9,
960 cp_coher_cntl |
961 S_0301F0_TC_WB_ACTION_ENA(1) |
962 S_0301F0_TC_NC_ACTION_ENA(1));
963 cp_coher_cntl = 0;
964 }
965 if (flush_bits & RADV_CMD_FLAG_INV_VCACHE) {
966 si_emit_acquire_mem(cs, is_mec,
967 chip_class >= GFX9,
968 cp_coher_cntl |
969 S_0085F0_TCL1_ACTION_ENA(1));
970 cp_coher_cntl = 0;
971 }
972 }
973
974 /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
975 * Therefore, it should be last. Done in PFP.
976 */
977 if (cp_coher_cntl)
978 si_emit_acquire_mem(cs, is_mec, chip_class >= GFX9, cp_coher_cntl);
979
980 if (flush_bits & RADV_CMD_FLAG_START_PIPELINE_STATS) {
981 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
982 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
983 EVENT_INDEX(0));
984 } else if (flush_bits & RADV_CMD_FLAG_STOP_PIPELINE_STATS) {
985 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
986 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
987 EVENT_INDEX(0));
988 }
989 }
990
991 void
992 si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer)
993 {
994 bool is_compute = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
995
996 if (is_compute)
997 cmd_buffer->state.flush_bits &= ~(RADV_CMD_FLAG_FLUSH_AND_INV_CB |
998 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
999 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1000 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1001 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
1002 RADV_CMD_FLAG_VS_PARTIAL_FLUSH |
1003 RADV_CMD_FLAG_VGT_FLUSH |
1004 RADV_CMD_FLAG_START_PIPELINE_STATS |
1005 RADV_CMD_FLAG_STOP_PIPELINE_STATS);
1006
1007 if (!cmd_buffer->state.flush_bits)
1008 return;
1009
1010 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 128);
1011
1012 si_cs_emit_cache_flush(cmd_buffer->cs,
1013 cmd_buffer->device->physical_device->rad_info.chip_class,
1014 &cmd_buffer->gfx9_fence_idx,
1015 cmd_buffer->gfx9_fence_va,
1016 radv_cmd_buffer_uses_mec(cmd_buffer),
1017 cmd_buffer->state.flush_bits,
1018 cmd_buffer->gfx9_eop_bug_va);
1019
1020
1021 if (unlikely(cmd_buffer->device->trace_bo))
1022 radv_cmd_buffer_trace_emit(cmd_buffer);
1023
1024 /* Clear the caches that have been flushed to avoid syncing too much
1025 * when there is some pending active queries.
1026 */
1027 cmd_buffer->active_query_flush_bits &= ~cmd_buffer->state.flush_bits;
1028
1029 cmd_buffer->state.flush_bits = 0;
1030
1031 /* If the driver used a compute shader for resetting a query pool, it
1032 * should be finished at this point.
1033 */
1034 cmd_buffer->pending_reset_query = false;
1035 }
1036
1037 /* sets the CP predication state using a boolean stored at va */
1038 void
1039 si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
1040 bool draw_visible, uint64_t va)
1041 {
1042 uint32_t op = 0;
1043
1044 if (va) {
1045 op = PRED_OP(PREDICATION_OP_BOOL64);
1046
1047 /* PREDICATION_DRAW_VISIBLE means that if the 32-bit value is
1048 * zero, all rendering commands are discarded. Otherwise, they
1049 * are discarded if the value is non zero.
1050 */
1051 op |= draw_visible ? PREDICATION_DRAW_VISIBLE :
1052 PREDICATION_DRAW_NOT_VISIBLE;
1053 }
1054 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1055 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 2, 0));
1056 radeon_emit(cmd_buffer->cs, op);
1057 radeon_emit(cmd_buffer->cs, va);
1058 radeon_emit(cmd_buffer->cs, va >> 32);
1059 } else {
1060 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
1061 radeon_emit(cmd_buffer->cs, va);
1062 radeon_emit(cmd_buffer->cs, op | ((va >> 32) & 0xFF));
1063 }
1064 }
1065
1066 /* Set this if you want the 3D engine to wait until CP DMA is done.
1067 * It should be set on the last CP DMA packet. */
1068 #define CP_DMA_SYNC (1 << 0)
1069
1070 /* Set this if the source data was used as a destination in a previous CP DMA
1071 * packet. It's for preventing a read-after-write (RAW) hazard between two
1072 * CP DMA packets. */
1073 #define CP_DMA_RAW_WAIT (1 << 1)
1074 #define CP_DMA_USE_L2 (1 << 2)
1075 #define CP_DMA_CLEAR (1 << 3)
1076
1077 /* Alignment for optimal performance. */
1078 #define SI_CPDMA_ALIGNMENT 32
1079
1080 /* The max number of bytes that can be copied per packet. */
1081 static inline unsigned cp_dma_max_byte_count(struct radv_cmd_buffer *cmd_buffer)
1082 {
1083 unsigned max = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 ?
1084 S_414_BYTE_COUNT_GFX9(~0u) :
1085 S_414_BYTE_COUNT_GFX6(~0u);
1086
1087 /* make it aligned for optimal performance */
1088 return max & ~(SI_CPDMA_ALIGNMENT - 1);
1089 }
1090
1091 /* Emit a CP DMA packet to do a copy from one buffer to another, or to clear
1092 * a buffer. The size must fit in bits [20:0]. If CP_DMA_CLEAR is set, src_va is a 32-bit
1093 * clear value.
1094 */
1095 static void si_emit_cp_dma(struct radv_cmd_buffer *cmd_buffer,
1096 uint64_t dst_va, uint64_t src_va,
1097 unsigned size, unsigned flags)
1098 {
1099 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1100 uint32_t header = 0, command = 0;
1101
1102 assert(size <= cp_dma_max_byte_count(cmd_buffer));
1103
1104 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9);
1105 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1106 command |= S_414_BYTE_COUNT_GFX9(size);
1107 else
1108 command |= S_414_BYTE_COUNT_GFX6(size);
1109
1110 /* Sync flags. */
1111 if (flags & CP_DMA_SYNC)
1112 header |= S_411_CP_SYNC(1);
1113 else {
1114 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1115 command |= S_414_DISABLE_WR_CONFIRM_GFX9(1);
1116 else
1117 command |= S_414_DISABLE_WR_CONFIRM_GFX6(1);
1118 }
1119
1120 if (flags & CP_DMA_RAW_WAIT)
1121 command |= S_414_RAW_WAIT(1);
1122
1123 /* Src and dst flags. */
1124 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
1125 !(flags & CP_DMA_CLEAR) &&
1126 src_va == dst_va)
1127 header |= S_411_DST_SEL(V_411_NOWHERE); /* prefetch only */
1128 else if (flags & CP_DMA_USE_L2)
1129 header |= S_411_DST_SEL(V_411_DST_ADDR_TC_L2);
1130
1131 if (flags & CP_DMA_CLEAR)
1132 header |= S_411_SRC_SEL(V_411_DATA);
1133 else if (flags & CP_DMA_USE_L2)
1134 header |= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2);
1135
1136 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
1137 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, cmd_buffer->state.predicating));
1138 radeon_emit(cs, header);
1139 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1140 radeon_emit(cs, src_va >> 32); /* SRC_ADDR_HI [31:0] */
1141 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1142 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [31:0] */
1143 radeon_emit(cs, command);
1144 } else {
1145 assert(!(flags & CP_DMA_USE_L2));
1146 header |= S_411_SRC_ADDR_HI(src_va >> 32);
1147 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, cmd_buffer->state.predicating));
1148 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1149 radeon_emit(cs, header); /* SRC_ADDR_HI [15:0] + flags. */
1150 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1151 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
1152 radeon_emit(cs, command);
1153 }
1154
1155 /* CP DMA is executed in ME, but index buffers are read by PFP.
1156 * This ensures that ME (CP DMA) is idle before PFP starts fetching
1157 * indices. If we wanted to execute CP DMA in PFP, this packet
1158 * should precede it.
1159 */
1160 if (flags & CP_DMA_SYNC) {
1161 if (cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
1162 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1163 radeon_emit(cs, 0);
1164 }
1165
1166 /* CP will see the sync flag and wait for all DMAs to complete. */
1167 cmd_buffer->state.dma_is_busy = false;
1168 }
1169
1170 if (unlikely(cmd_buffer->device->trace_bo))
1171 radv_cmd_buffer_trace_emit(cmd_buffer);
1172 }
1173
1174 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1175 unsigned size)
1176 {
1177 uint64_t aligned_va = va & ~(SI_CPDMA_ALIGNMENT - 1);
1178 uint64_t aligned_size = ((va + size + SI_CPDMA_ALIGNMENT -1) & ~(SI_CPDMA_ALIGNMENT - 1)) - aligned_va;
1179
1180 si_emit_cp_dma(cmd_buffer, aligned_va, aligned_va,
1181 aligned_size, CP_DMA_USE_L2);
1182 }
1183
1184 static void si_cp_dma_prepare(struct radv_cmd_buffer *cmd_buffer, uint64_t byte_count,
1185 uint64_t remaining_size, unsigned *flags)
1186 {
1187
1188 /* Flush the caches for the first copy only.
1189 * Also wait for the previous CP DMA operations.
1190 */
1191 if (cmd_buffer->state.flush_bits) {
1192 si_emit_cache_flush(cmd_buffer);
1193 *flags |= CP_DMA_RAW_WAIT;
1194 }
1195
1196 /* Do the synchronization after the last dma, so that all data
1197 * is written to memory.
1198 */
1199 if (byte_count == remaining_size)
1200 *flags |= CP_DMA_SYNC;
1201 }
1202
1203 static void si_cp_dma_realign_engine(struct radv_cmd_buffer *cmd_buffer, unsigned size)
1204 {
1205 uint64_t va;
1206 uint32_t offset;
1207 unsigned dma_flags = 0;
1208 unsigned buf_size = SI_CPDMA_ALIGNMENT * 2;
1209 void *ptr;
1210
1211 assert(size < SI_CPDMA_ALIGNMENT);
1212
1213 radv_cmd_buffer_upload_alloc(cmd_buffer, buf_size, SI_CPDMA_ALIGNMENT, &offset, &ptr);
1214
1215 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1216 va += offset;
1217
1218 si_cp_dma_prepare(cmd_buffer, size, size, &dma_flags);
1219
1220 si_emit_cp_dma(cmd_buffer, va, va + SI_CPDMA_ALIGNMENT, size,
1221 dma_flags);
1222 }
1223
1224 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1225 uint64_t src_va, uint64_t dest_va,
1226 uint64_t size)
1227 {
1228 uint64_t main_src_va, main_dest_va;
1229 uint64_t skipped_size = 0, realign_size = 0;
1230
1231 /* Assume that we are not going to sync after the last DMA operation. */
1232 cmd_buffer->state.dma_is_busy = true;
1233
1234 if (cmd_buffer->device->physical_device->rad_info.family <= CHIP_CARRIZO ||
1235 cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY) {
1236 /* If the size is not aligned, we must add a dummy copy at the end
1237 * just to align the internal counter. Otherwise, the DMA engine
1238 * would slow down by an order of magnitude for following copies.
1239 */
1240 if (size % SI_CPDMA_ALIGNMENT)
1241 realign_size = SI_CPDMA_ALIGNMENT - (size % SI_CPDMA_ALIGNMENT);
1242
1243 /* If the copy begins unaligned, we must start copying from the next
1244 * aligned block and the skipped part should be copied after everything
1245 * else has been copied. Only the src alignment matters, not dst.
1246 */
1247 if (src_va % SI_CPDMA_ALIGNMENT) {
1248 skipped_size = SI_CPDMA_ALIGNMENT - (src_va % SI_CPDMA_ALIGNMENT);
1249 /* The main part will be skipped if the size is too small. */
1250 skipped_size = MIN2(skipped_size, size);
1251 size -= skipped_size;
1252 }
1253 }
1254 main_src_va = src_va + skipped_size;
1255 main_dest_va = dest_va + skipped_size;
1256
1257 while (size) {
1258 unsigned dma_flags = 0;
1259 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1260
1261 si_cp_dma_prepare(cmd_buffer, byte_count,
1262 size + skipped_size + realign_size,
1263 &dma_flags);
1264
1265 dma_flags &= ~CP_DMA_SYNC;
1266
1267 si_emit_cp_dma(cmd_buffer, main_dest_va, main_src_va,
1268 byte_count, dma_flags);
1269
1270 size -= byte_count;
1271 main_src_va += byte_count;
1272 main_dest_va += byte_count;
1273 }
1274
1275 if (skipped_size) {
1276 unsigned dma_flags = 0;
1277
1278 si_cp_dma_prepare(cmd_buffer, skipped_size,
1279 size + skipped_size + realign_size,
1280 &dma_flags);
1281
1282 si_emit_cp_dma(cmd_buffer, dest_va, src_va,
1283 skipped_size, dma_flags);
1284 }
1285 if (realign_size)
1286 si_cp_dma_realign_engine(cmd_buffer, realign_size);
1287 }
1288
1289 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1290 uint64_t size, unsigned value)
1291 {
1292
1293 if (!size)
1294 return;
1295
1296 assert(va % 4 == 0 && size % 4 == 0);
1297
1298 /* Assume that we are not going to sync after the last DMA operation. */
1299 cmd_buffer->state.dma_is_busy = true;
1300
1301 while (size) {
1302 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1303 unsigned dma_flags = CP_DMA_CLEAR;
1304
1305 si_cp_dma_prepare(cmd_buffer, byte_count, size, &dma_flags);
1306
1307 /* Emit the clear packet. */
1308 si_emit_cp_dma(cmd_buffer, va, value, byte_count,
1309 dma_flags);
1310
1311 size -= byte_count;
1312 va += byte_count;
1313 }
1314 }
1315
1316 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer)
1317 {
1318 if (cmd_buffer->device->physical_device->rad_info.chip_class < GFX7)
1319 return;
1320
1321 if (!cmd_buffer->state.dma_is_busy)
1322 return;
1323
1324 /* Issue a dummy DMA that copies zero bytes.
1325 *
1326 * The DMA engine will see that there's no work to do and skip this
1327 * DMA request, however, the CP will see the sync flag and still wait
1328 * for all DMAs to complete.
1329 */
1330 si_emit_cp_dma(cmd_buffer, 0, 0, 0, CP_DMA_SYNC);
1331
1332 cmd_buffer->state.dma_is_busy = false;
1333 }
1334
1335 /* For MSAA sample positions. */
1336 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1337 ((((unsigned)(s0x) & 0xf) << 0) | (((unsigned)(s0y) & 0xf) << 4) | \
1338 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
1339 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
1340 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
1341
1342 /* For obtaining location coordinates from registers */
1343 #define SEXT4(x) ((int)((x) | ((x) & 0x8 ? 0xfffffff0 : 0)))
1344 #define GET_SFIELD(reg, index) SEXT4(((reg) >> ((index) * 4)) & 0xf)
1345 #define GET_SX(reg, index) GET_SFIELD((reg)[(index) / 4], ((index) % 4) * 2)
1346 #define GET_SY(reg, index) GET_SFIELD((reg)[(index) / 4], ((index) % 4) * 2 + 1)
1347
1348 /* 1x MSAA */
1349 static const uint32_t sample_locs_1x =
1350 FILL_SREG(0, 0, 0, 0, 0, 0, 0, 0);
1351 static const unsigned max_dist_1x = 0;
1352 static const uint64_t centroid_priority_1x = 0x0000000000000000ull;
1353
1354 /* 2xMSAA */
1355 static const uint32_t sample_locs_2x =
1356 FILL_SREG(4,4, -4, -4, 0, 0, 0, 0);
1357 static const unsigned max_dist_2x = 4;
1358 static const uint64_t centroid_priority_2x = 0x1010101010101010ull;
1359
1360 /* 4xMSAA */
1361 static const uint32_t sample_locs_4x =
1362 FILL_SREG(-2,-6, 6, -2, -6, 2, 2, 6);
1363 static const unsigned max_dist_4x = 6;
1364 static const uint64_t centroid_priority_4x = 0x3210321032103210ull;
1365
1366 /* 8xMSAA */
1367 static const uint32_t sample_locs_8x[] = {
1368 FILL_SREG( 1,-3, -1, 3, 5, 1, -3,-5),
1369 FILL_SREG(-5, 5, -7,-1, 3, 7, 7,-7),
1370 /* The following are unused by hardware, but we emit them to IBs
1371 * instead of multiple SET_CONTEXT_REG packets. */
1372 0,
1373 0,
1374 };
1375 static const unsigned max_dist_8x = 7;
1376 static const uint64_t centroid_priority_8x = 0x7654321076543210ull;
1377
1378 unsigned radv_get_default_max_sample_dist(int log_samples)
1379 {
1380 unsigned max_dist[] = {
1381 max_dist_1x,
1382 max_dist_2x,
1383 max_dist_4x,
1384 max_dist_8x,
1385 };
1386 return max_dist[log_samples];
1387 }
1388
1389 void radv_emit_default_sample_locations(struct radeon_cmdbuf *cs, int nr_samples)
1390 {
1391 switch (nr_samples) {
1392 default:
1393 case 1:
1394 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1395 radeon_emit(cs, (uint32_t)centroid_priority_1x);
1396 radeon_emit(cs, centroid_priority_1x >> 32);
1397 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_1x);
1398 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_1x);
1399 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_1x);
1400 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_1x);
1401 break;
1402 case 2:
1403 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1404 radeon_emit(cs, (uint32_t)centroid_priority_2x);
1405 radeon_emit(cs, centroid_priority_2x >> 32);
1406 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x);
1407 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x);
1408 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x);
1409 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x);
1410 break;
1411 case 4:
1412 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1413 radeon_emit(cs, (uint32_t)centroid_priority_4x);
1414 radeon_emit(cs, centroid_priority_4x >> 32);
1415 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x);
1416 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x);
1417 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x);
1418 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x);
1419 break;
1420 case 8:
1421 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1422 radeon_emit(cs, (uint32_t)centroid_priority_8x);
1423 radeon_emit(cs, centroid_priority_8x >> 32);
1424 radeon_set_context_reg_seq(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
1425 radeon_emit_array(cs, sample_locs_8x, 4);
1426 radeon_emit_array(cs, sample_locs_8x, 4);
1427 radeon_emit_array(cs, sample_locs_8x, 4);
1428 radeon_emit_array(cs, sample_locs_8x, 2);
1429 break;
1430 }
1431 }
1432
1433 static void radv_get_sample_position(struct radv_device *device,
1434 unsigned sample_count,
1435 unsigned sample_index, float *out_value)
1436 {
1437 const uint32_t *sample_locs;
1438
1439 switch (sample_count) {
1440 case 1:
1441 default:
1442 sample_locs = &sample_locs_1x;
1443 break;
1444 case 2:
1445 sample_locs = &sample_locs_2x;
1446 break;
1447 case 4:
1448 sample_locs = &sample_locs_4x;
1449 break;
1450 case 8:
1451 sample_locs = sample_locs_8x;
1452 break;
1453 }
1454
1455 out_value[0] = (GET_SX(sample_locs, sample_index) + 8) / 16.0f;
1456 out_value[1] = (GET_SY(sample_locs, sample_index) + 8) / 16.0f;
1457 }
1458
1459 void radv_device_init_msaa(struct radv_device *device)
1460 {
1461 int i;
1462
1463 radv_get_sample_position(device, 1, 0, device->sample_locations_1x[0]);
1464
1465 for (i = 0; i < 2; i++)
1466 radv_get_sample_position(device, 2, i, device->sample_locations_2x[i]);
1467 for (i = 0; i < 4; i++)
1468 radv_get_sample_position(device, 4, i, device->sample_locations_4x[i]);
1469 for (i = 0; i < 8; i++)
1470 radv_get_sample_position(device, 8, i, device->sample_locations_8x[i]);
1471 }