projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv: add support for local bos. (v3)
[mesa.git] / src / amd / vulkan / si_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based on si_state.c
6 * Copyright © 2015 Advanced Micro Devices, Inc.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 /* command buffer handling for SI */
29
30 #include "radv_private.h"
31 #include "radv_shader.h"
32 #include "radv_cs.h"
33 #include "sid.h"
34 #include "gfx9d.h"
35 #include "radv_util.h"
36 #include "main/macros.h"
37
38 static void
39 si_write_harvested_raster_configs(struct radv_physical_device *physical_device,
40 struct radeon_winsys_cs *cs,
41 unsigned raster_config,
42 unsigned raster_config_1)
43 {
44 unsigned sh_per_se = MAX2(physical_device->rad_info.max_sh_per_se, 1);
45 unsigned num_se = MAX2(physical_device->rad_info.max_se, 1);
46 unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
47 unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
48 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
49 unsigned rb_per_se = num_rb / num_se;
50 unsigned se_mask[4];
51 unsigned se;
52
53 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
54 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
55 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
56 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
57
58 assert(num_se == 1 || num_se == 2 || num_se == 4);
59 assert(sh_per_se == 1 || sh_per_se == 2);
60 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
61
62 /* XXX: I can't figure out what the *_XSEL and *_YSEL
63 * fields are for, so I'm leaving them as their default
64 * values. */
65
66 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
67 (!se_mask[2] && !se_mask[3]))) {
68 raster_config_1 &= C_028354_SE_PAIR_MAP;
69
70 if (!se_mask[0] && !se_mask[1]) {
71 raster_config_1 |=
72 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
73 } else {
74 raster_config_1 |=
75 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
76 }
77 }
78
79 for (se = 0; se < num_se; se++) {
80 unsigned raster_config_se = raster_config;
81 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
82 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
83 int idx = (se / 2) * 2;
84
85 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
86 raster_config_se &= C_028350_SE_MAP;
87
88 if (!se_mask[idx]) {
89 raster_config_se |=
90 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
91 } else {
92 raster_config_se |=
93 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
94 }
95 }
96
97 pkr0_mask &= rb_mask;
98 pkr1_mask &= rb_mask;
99 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
100 raster_config_se &= C_028350_PKR_MAP;
101
102 if (!pkr0_mask) {
103 raster_config_se |=
104 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
105 } else {
106 raster_config_se |=
107 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
108 }
109 }
110
111 if (rb_per_se >= 2) {
112 unsigned rb0_mask = 1 << (se * rb_per_se);
113 unsigned rb1_mask = rb0_mask << 1;
114
115 rb0_mask &= rb_mask;
116 rb1_mask &= rb_mask;
117 if (!rb0_mask || !rb1_mask) {
118 raster_config_se &= C_028350_RB_MAP_PKR0;
119
120 if (!rb0_mask) {
121 raster_config_se |=
122 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
123 } else {
124 raster_config_se |=
125 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
126 }
127 }
128
129 if (rb_per_se > 2) {
130 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
131 rb1_mask = rb0_mask << 1;
132 rb0_mask &= rb_mask;
133 rb1_mask &= rb_mask;
134 if (!rb0_mask || !rb1_mask) {
135 raster_config_se &= C_028350_RB_MAP_PKR1;
136
137 if (!rb0_mask) {
138 raster_config_se |=
139 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
140 } else {
141 raster_config_se |=
142 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
143 }
144 }
145 }
146 }
147
148 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
149 if (physical_device->rad_info.chip_class < CIK)
150 radeon_set_config_reg(cs, GRBM_GFX_INDEX,
151 SE_INDEX(se) | SH_BROADCAST_WRITES |
152 INSTANCE_BROADCAST_WRITES);
153 else
154 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
155 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
156 S_030800_INSTANCE_BROADCAST_WRITES(1));
157 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
158 if (physical_device->rad_info.chip_class >= CIK)
159 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
160 }
161
162 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
163 if (physical_device->rad_info.chip_class < CIK)
164 radeon_set_config_reg(cs, GRBM_GFX_INDEX,
165 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
166 INSTANCE_BROADCAST_WRITES);
167 else
168 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
169 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
170 S_030800_INSTANCE_BROADCAST_WRITES(1));
171 }
172
173 static void
174 si_emit_compute(struct radv_physical_device *physical_device,
175 struct radeon_winsys_cs *cs)
176 {
177 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
178 radeon_emit(cs, 0);
179 radeon_emit(cs, 0);
180 radeon_emit(cs, 0);
181
182 radeon_set_sh_reg_seq(cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
183 S_00B854_WAVES_PER_SH(0x3));
184 radeon_emit(cs, 0);
185 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
186 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
187 radeon_emit(cs, S_00B85C_SH0_CU_EN(0xffff) | S_00B85C_SH1_CU_EN(0xffff));
188
189 if (physical_device->rad_info.chip_class >= CIK) {
190 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
191 radeon_set_sh_reg_seq(cs,
192 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
193 radeon_emit(cs, S_00B864_SH0_CU_EN(0xffff) |
194 S_00B864_SH1_CU_EN(0xffff));
195 radeon_emit(cs, S_00B868_SH0_CU_EN(0xffff) |
196 S_00B868_SH1_CU_EN(0xffff));
197 }
198
199 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
200 * and is now per pipe, so it should be handled in the
201 * kernel if we want to use something other than the default value,
202 * which is now 0x22f.
203 */
204 if (physical_device->rad_info.chip_class <= SI) {
205 /* XXX: This should be:
206 * (number of compute units) * 4 * (waves per simd) - 1 */
207
208 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
209 0x190 /* Default value */);
210 }
211 }
212
213 void
214 si_init_compute(struct radv_cmd_buffer *cmd_buffer)
215 {
216 struct radv_physical_device *physical_device = cmd_buffer->device->physical_device;
217 si_emit_compute(physical_device, cmd_buffer->cs);
218 }
219
220 /* 12.4 fixed-point */
221 static unsigned radv_pack_float_12p4(float x)
222 {
223 return x <= 0 ? 0 :
224 x >= 4096 ? 0xffff : x * 16;
225 }
226
227 static void
228 si_set_raster_config(struct radv_physical_device *physical_device,
229 struct radeon_winsys_cs *cs)
230 {
231 unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
232 unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
233 unsigned raster_config, raster_config_1;
234
235 switch (physical_device->rad_info.family) {
236 case CHIP_TAHITI:
237 case CHIP_PITCAIRN:
238 raster_config = 0x2a00126a;
239 raster_config_1 = 0x00000000;
240 break;
241 case CHIP_VERDE:
242 raster_config = 0x0000124a;
243 raster_config_1 = 0x00000000;
244 break;
245 case CHIP_OLAND:
246 raster_config = 0x00000082;
247 raster_config_1 = 0x00000000;
248 break;
249 case CHIP_HAINAN:
250 raster_config = 0x00000000;
251 raster_config_1 = 0x00000000;
252 break;
253 case CHIP_BONAIRE:
254 raster_config = 0x16000012;
255 raster_config_1 = 0x00000000;
256 break;
257 case CHIP_HAWAII:
258 raster_config = 0x3a00161a;
259 raster_config_1 = 0x0000002e;
260 break;
261 case CHIP_FIJI:
262 if (physical_device->rad_info.cik_macrotile_mode_array[0] == 0x000000e8) {
263 /* old kernels with old tiling config */
264 raster_config = 0x16000012;
265 raster_config_1 = 0x0000002a;
266 } else {
267 raster_config = 0x3a00161a;
268 raster_config_1 = 0x0000002e;
269 }
270 break;
271 case CHIP_POLARIS10:
272 raster_config = 0x16000012;
273 raster_config_1 = 0x0000002a;
274 break;
275 case CHIP_POLARIS11:
276 case CHIP_POLARIS12:
277 raster_config = 0x16000012;
278 raster_config_1 = 0x00000000;
279 break;
280 case CHIP_TONGA:
281 raster_config = 0x16000012;
282 raster_config_1 = 0x0000002a;
283 break;
284 case CHIP_ICELAND:
285 if (num_rb == 1)
286 raster_config = 0x00000000;
287 else
288 raster_config = 0x00000002;
289 raster_config_1 = 0x00000000;
290 break;
291 case CHIP_CARRIZO:
292 raster_config = 0x00000002;
293 raster_config_1 = 0x00000000;
294 break;
295 case CHIP_KAVERI:
296 /* KV should be 0x00000002, but that causes problems with radeon */
297 raster_config = 0x00000000; /* 0x00000002 */
298 raster_config_1 = 0x00000000;
299 break;
300 case CHIP_KABINI:
301 case CHIP_MULLINS:
302 case CHIP_STONEY:
303 raster_config = 0x00000000;
304 raster_config_1 = 0x00000000;
305 break;
306 default:
307 fprintf(stderr,
308 "radv: Unknown GPU, using 0 for raster_config\n");
309 raster_config = 0x00000000;
310 raster_config_1 = 0x00000000;
311 break;
312 }
313
314 /* Always use the default config when all backends are enabled
315 * (or when we failed to determine the enabled backends).
316 */
317 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
318 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG,
319 raster_config);
320 if (physical_device->rad_info.chip_class >= CIK)
321 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1,
322 raster_config_1);
323 } else {
324 si_write_harvested_raster_configs(physical_device, cs,
325 raster_config,
326 raster_config_1);
327 }
328 }
329
330 static void
331 si_emit_config(struct radv_physical_device *physical_device,
332 struct radeon_winsys_cs *cs)
333 {
334 int i;
335
336 /* Only SI can disable CLEAR_STATE for now. */
337 assert(physical_device->has_clear_state ||
338 physical_device->rad_info.chip_class == SI);
339
340 radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
341 radeon_emit(cs, CONTEXT_CONTROL_LOAD_ENABLE(1));
342 radeon_emit(cs, CONTEXT_CONTROL_SHADOW_ENABLE(1));
343
344 if (physical_device->has_clear_state) {
345 radeon_emit(cs, PKT3(PKT3_CLEAR_STATE, 0, 0));
346 radeon_emit(cs, 0);
347 }
348
349 if (physical_device->rad_info.chip_class <= VI)
350 si_set_raster_config(physical_device, cs);
351
352 radeon_set_context_reg(cs, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
353 if (!physical_device->has_clear_state)
354 radeon_set_context_reg(cs, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
355
356 /* FIXME calculate these values somehow ??? */
357 if (physical_device->rad_info.chip_class <= VI) {
358 radeon_set_context_reg(cs, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
359 radeon_set_context_reg(cs, R_028A58_VGT_ES_PER_GS, 0x40);
360 }
361
362 if (!physical_device->has_clear_state) {
363 radeon_set_context_reg(cs, R_028A5C_VGT_GS_PER_VS, 0x2);
364 radeon_set_context_reg(cs, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
365 radeon_set_context_reg(cs, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
366 }
367
368 radeon_set_context_reg(cs, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
369 if (!physical_device->has_clear_state)
370 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, 0x0);
371 if (physical_device->rad_info.chip_class < CIK)
372 radeon_set_config_reg(cs, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
373 S_008A14_CLIP_VTX_REORDER_ENA(1));
374
375 radeon_set_context_reg(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
376 radeon_set_context_reg(cs, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
377
378 if (!physical_device->has_clear_state)
379 radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
380
381 /* CLEAR_STATE doesn't clear these correctly on certain generations.
382 * I don't know why. Deduced by trial and error.
383 */
384 if (physical_device->rad_info.chip_class <= CIK) {
385 radeon_set_context_reg(cs, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
386 radeon_set_context_reg(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL,
387 S_028204_WINDOW_OFFSET_DISABLE(1));
388 radeon_set_context_reg(cs, R_028240_PA_SC_GENERIC_SCISSOR_TL,
389 S_028240_WINDOW_OFFSET_DISABLE(1));
390 radeon_set_context_reg(cs, R_028244_PA_SC_GENERIC_SCISSOR_BR,
391 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
392 radeon_set_context_reg(cs, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
393 radeon_set_context_reg(cs, R_028034_PA_SC_SCREEN_SCISSOR_BR,
394 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
395 }
396
397 if (!physical_device->has_clear_state) {
398 for (i = 0; i < 16; i++) {
399 radeon_set_context_reg(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
400 radeon_set_context_reg(cs, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
401 }
402 }
403
404 if (!physical_device->has_clear_state) {
405 radeon_set_context_reg(cs, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
406 radeon_set_context_reg(cs, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
407 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
408 radeon_set_context_reg(cs, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
409 radeon_set_context_reg(cs, R_028820_PA_CL_NANINF_CNTL, 0);
410 radeon_set_context_reg(cs, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
411 radeon_set_context_reg(cs, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
412 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
413 }
414
415 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE,
416 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
417 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
418
419 if (physical_device->rad_info.chip_class >= GFX9) {
420 radeon_set_uconfig_reg(cs, R_030920_VGT_MAX_VTX_INDX, ~0);
421 radeon_set_uconfig_reg(cs, R_030924_VGT_MIN_VTX_INDX, 0);
422 radeon_set_uconfig_reg(cs, R_030928_VGT_INDX_OFFSET, 0);
423 } else {
424 /* These registers, when written, also overwrite the
425 * CLEAR_STATE context, so we can't rely on CLEAR_STATE setting
426 * them. It would be an issue if there was another UMD
427 * changing them.
428 */
429 radeon_set_context_reg(cs, R_028400_VGT_MAX_VTX_INDX, ~0);
430 radeon_set_context_reg(cs, R_028404_VGT_MIN_VTX_INDX, 0);
431 radeon_set_context_reg(cs, R_028408_VGT_INDX_OFFSET, 0);
432 }
433
434 if (physical_device->rad_info.chip_class >= CIK) {
435 if (physical_device->rad_info.chip_class >= GFX9) {
436 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
437 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
438 } else {
439 radeon_set_sh_reg(cs, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
440 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
441 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
442 S_00B41C_WAVE_LIMIT(0x3F));
443 radeon_set_sh_reg(cs, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
444 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
445 /* If this is 0, Bonaire can hang even if GS isn't being used.
446 * Other chips are unaffected. These are suboptimal values,
447 * but we don't use on-chip GS.
448 */
449 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL,
450 S_028A44_ES_VERTS_PER_SUBGRP(64) |
451 S_028A44_GS_PRIMS_PER_SUBGRP(4));
452 }
453 radeon_set_sh_reg(cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
454 S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
455
456 if (physical_device->rad_info.num_good_compute_units /
457 (physical_device->rad_info.max_se * physical_device->rad_info.max_sh_per_se) <= 4) {
458 /* Too few available compute units per SH. Disallowing
459 * VS to run on CU0 could hurt us more than late VS
460 * allocation would help.
461 *
462 * LATE_ALLOC_VS = 2 is the highest safe number.
463 */
464 radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
465 S_00B118_CU_EN(0xffff) | S_00B118_WAVE_LIMIT(0x3F) );
466 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
467 } else {
468 /* Set LATE_ALLOC_VS == 31. It should be less than
469 * the number of scratch waves. Limitations:
470 * - VS can't execute on CU0.
471 * - If HS writes outputs to LDS, LS can't execute on CU0.
472 */
473 radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
474 S_00B118_CU_EN(0xfffe) | S_00B118_WAVE_LIMIT(0x3F));
475 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
476 }
477
478 radeon_set_sh_reg(cs, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
479 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
480 }
481
482 if (physical_device->rad_info.chip_class >= VI) {
483 uint32_t vgt_tess_distribution;
484 radeon_set_context_reg(cs, R_028424_CB_DCC_CONTROL,
485 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
486 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
487
488 vgt_tess_distribution = S_028B50_ACCUM_ISOLINE(32) |
489 S_028B50_ACCUM_TRI(11) |
490 S_028B50_ACCUM_QUAD(11) |
491 S_028B50_DONUT_SPLIT(16);
492
493 if (physical_device->rad_info.family == CHIP_FIJI ||
494 physical_device->rad_info.family >= CHIP_POLARIS10)
495 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
496
497 radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION,
498 vgt_tess_distribution);
499 } else if (!physical_device->has_clear_state) {
500 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
501 radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
502 }
503
504 if (physical_device->rad_info.chip_class >= GFX9) {
505 unsigned num_se = physical_device->rad_info.max_se;
506 unsigned pc_lines = 0;
507
508 switch (physical_device->rad_info.family) {
509 case CHIP_VEGA10:
510 pc_lines = 4096;
511 break;
512 case CHIP_RAVEN:
513 pc_lines = 1024;
514 break;
515 default:
516 assert(0);
517 }
518
519 radeon_set_context_reg(cs, R_028060_DB_DFSM_CONTROL,
520 S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF));
521 /* TODO: Enable the binner: */
522 radeon_set_context_reg(cs, R_028C44_PA_SC_BINNER_CNTL_0,
523 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
524 S_028C44_DISABLE_START_OF_PRIM(1));
525 radeon_set_context_reg(cs, R_028C48_PA_SC_BINNER_CNTL_1,
526 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines / (4 * num_se))) |
527 S_028C48_MAX_PRIM_PER_BATCH(1023));
528 radeon_set_context_reg(cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
529 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
530 radeon_set_uconfig_reg(cs, R_030968_VGT_INSTANCE_BASE_ID, 0);
531 }
532
533 unsigned tmp = (unsigned)(1.0 * 8.0);
534 radeon_set_context_reg_seq(cs, R_028A00_PA_SU_POINT_SIZE, 1);
535 radeon_emit(cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
536 radeon_set_context_reg_seq(cs, R_028A04_PA_SU_POINT_MINMAX, 1);
537 radeon_emit(cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
538 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2)));
539
540 if (!physical_device->has_clear_state) {
541 radeon_set_context_reg(cs, R_028004_DB_COUNT_CONTROL,
542 S_028004_ZPASS_INCREMENT_DISABLE(1));
543 }
544
545 si_emit_compute(physical_device, cs);
546 }
547
548 void si_init_config(struct radv_cmd_buffer *cmd_buffer)
549 {
550 struct radv_physical_device *physical_device = cmd_buffer->device->physical_device;
551
552 si_emit_config(physical_device, cmd_buffer->cs);
553 }
554
555 void
556 cik_create_gfx_config(struct radv_device *device)
557 {
558 struct radeon_winsys_cs *cs = device->ws->cs_create(device->ws, RING_GFX);
559 if (!cs)
560 return;
561
562 si_emit_config(device->physical_device, cs);
563
564 while (cs->cdw & 7) {
565 if (device->physical_device->rad_info.gfx_ib_pad_with_type2)
566 radeon_emit(cs, 0x80000000);
567 else
568 radeon_emit(cs, 0xffff1000);
569 }
570
571 device->gfx_init = device->ws->buffer_create(device->ws,
572 cs->cdw * 4, 4096,
573 RADEON_DOMAIN_GTT,
574 RADEON_FLAG_CPU_ACCESS|
575 RADEON_FLAG_NO_INTERPROCESS_SHARING);
576 if (!device->gfx_init)
577 goto fail;
578
579 void *map = device->ws->buffer_map(device->gfx_init);
580 if (!map) {
581 device->ws->buffer_destroy(device->gfx_init);
582 device->gfx_init = NULL;
583 goto fail;
584 }
585 memcpy(map, cs->buf, cs->cdw * 4);
586
587 device->ws->buffer_unmap(device->gfx_init);
588 device->gfx_init_size_dw = cs->cdw;
589 fail:
590 device->ws->cs_destroy(cs);
591 }
592
593 static void
594 get_viewport_xform(const VkViewport *viewport,
595 float scale[3], float translate[3])
596 {
597 float x = viewport->x;
598 float y = viewport->y;
599 float half_width = 0.5f * viewport->width;
600 float half_height = 0.5f * viewport->height;
601 double n = viewport->minDepth;
602 double f = viewport->maxDepth;
603
604 scale[0] = half_width;
605 translate[0] = half_width + x;
606 scale[1] = half_height;
607 translate[1] = half_height + y;
608
609 scale[2] = (f - n);
610 translate[2] = n;
611 }
612
613 void
614 si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
615 int count, const VkViewport *viewports)
616 {
617 int i;
618
619 assert(count);
620 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
621 first_vp * 4 * 6, count * 6);
622
623 for (i = 0; i < count; i++) {
624 float scale[3], translate[3];
625
626
627 get_viewport_xform(&viewports[i], scale, translate);
628 radeon_emit(cs, fui(scale[0]));
629 radeon_emit(cs, fui(translate[0]));
630 radeon_emit(cs, fui(scale[1]));
631 radeon_emit(cs, fui(translate[1]));
632 radeon_emit(cs, fui(scale[2]));
633 radeon_emit(cs, fui(translate[2]));
634 }
635
636 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 +
637 first_vp * 4 * 2, count * 2);
638 for (i = 0; i < count; i++) {
639 float zmin = MIN2(viewports[i].minDepth, viewports[i].maxDepth);
640 float zmax = MAX2(viewports[i].minDepth, viewports[i].maxDepth);
641 radeon_emit(cs, fui(zmin));
642 radeon_emit(cs, fui(zmax));
643 }
644 }
645
646 static VkRect2D si_scissor_from_viewport(const VkViewport *viewport)
647 {
648 float scale[3], translate[3];
649 VkRect2D rect;
650
651 get_viewport_xform(viewport, scale, translate);
652
653 rect.offset.x = translate[0] - abs(scale[0]);
654 rect.offset.y = translate[1] - abs(scale[1]);
655 rect.extent.width = ceilf(translate[0] + abs(scale[0])) - rect.offset.x;
656 rect.extent.height = ceilf(translate[1] + abs(scale[1])) - rect.offset.y;
657
658 return rect;
659 }
660
661 static VkRect2D si_intersect_scissor(const VkRect2D *a, const VkRect2D *b) {
662 VkRect2D ret;
663 ret.offset.x = MAX2(a->offset.x, b->offset.x);
664 ret.offset.y = MAX2(a->offset.y, b->offset.y);
665 ret.extent.width = MIN2(a->offset.x + a->extent.width,
666 b->offset.x + b->extent.width) - ret.offset.x;
667 ret.extent.height = MIN2(a->offset.y + a->extent.height,
668 b->offset.y + b->extent.height) - ret.offset.y;
669 return ret;
670 }
671
672 void
673 si_write_scissors(struct radeon_winsys_cs *cs, int first,
674 int count, const VkRect2D *scissors,
675 const VkViewport *viewports, bool can_use_guardband)
676 {
677 int i;
678 float scale[3], translate[3], guardband_x = INFINITY, guardband_y = INFINITY;
679 const float max_range = 32767.0f;
680 assert(count);
681
682 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + first * 4 * 2, count * 2);
683 for (i = 0; i < count; i++) {
684 VkRect2D viewport_scissor = si_scissor_from_viewport(viewports + i);
685 VkRect2D scissor = si_intersect_scissor(&scissors[i], &viewport_scissor);
686
687 get_viewport_xform(viewports + i, scale, translate);
688 scale[0] = abs(scale[0]);
689 scale[1] = abs(scale[1]);
690
691 if (scale[0] < 0.5)
692 scale[0] = 0.5;
693 if (scale[1] < 0.5)
694 scale[1] = 0.5;
695
696 guardband_x = MIN2(guardband_x, (max_range - abs(translate[0])) / scale[0]);
697 guardband_y = MIN2(guardband_y, (max_range - abs(translate[1])) / scale[1]);
698
699 radeon_emit(cs, S_028250_TL_X(scissor.offset.x) |
700 S_028250_TL_Y(scissor.offset.y) |
701 S_028250_WINDOW_OFFSET_DISABLE(1));
702 radeon_emit(cs, S_028254_BR_X(scissor.offset.x + scissor.extent.width) |
703 S_028254_BR_Y(scissor.offset.y + scissor.extent.height));
704 }
705 if (!can_use_guardband) {
706 guardband_x = 1.0;
707 guardband_y = 1.0;
708 }
709
710 radeon_set_context_reg_seq(cs, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
711 radeon_emit(cs, fui(guardband_y));
712 radeon_emit(cs, fui(1.0));
713 radeon_emit(cs, fui(guardband_x));
714 radeon_emit(cs, fui(1.0));
715 }
716
717 static inline unsigned
718 radv_prims_for_vertices(struct radv_prim_vertex_count *info, unsigned num)
719 {
720 if (num == 0)
721 return 0;
722
723 if (info->incr == 0)
724 return 0;
725
726 if (num < info->min)
727 return 0;
728
729 return 1 + ((num - info->min) / info->incr);
730 }
731
732 uint32_t
733 si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
734 bool instanced_draw, bool indirect_draw,
735 uint32_t draw_vertex_count)
736 {
737 enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
738 enum radeon_family family = cmd_buffer->device->physical_device->rad_info.family;
739 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
740 const unsigned max_primgroup_in_wave = 2;
741 /* SWITCH_ON_EOP(0) is always preferable. */
742 bool wd_switch_on_eop = false;
743 bool ia_switch_on_eop = false;
744 bool ia_switch_on_eoi = false;
745 bool partial_vs_wave = false;
746 bool partial_es_wave = cmd_buffer->state.pipeline->graphics.partial_es_wave;
747 bool multi_instances_smaller_than_primgroup;
748
749 multi_instances_smaller_than_primgroup = indirect_draw;
750 if (!multi_instances_smaller_than_primgroup && instanced_draw) {
751 uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
752 if (num_prims < cmd_buffer->state.pipeline->graphics.primgroup_size)
753 multi_instances_smaller_than_primgroup = true;
754 }
755
756 ia_switch_on_eoi = cmd_buffer->state.pipeline->graphics.ia_switch_on_eoi;
757 partial_vs_wave = cmd_buffer->state.pipeline->graphics.partial_vs_wave;
758
759 if (chip_class >= CIK) {
760 wd_switch_on_eop = cmd_buffer->state.pipeline->graphics.wd_switch_on_eop;
761
762 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
763 * We don't know that for indirect drawing, so treat it as
764 * always problematic. */
765 if (family == CHIP_HAWAII &&
766 (instanced_draw || indirect_draw))
767 wd_switch_on_eop = true;
768
769 /* Performance recommendation for 4 SE Gfx7-8 parts if
770 * instances are smaller than a primgroup.
771 * Assume indirect draws always use small instances.
772 * This is needed for good VS wave utilization.
773 */
774 if (chip_class <= VI &&
775 info->max_se == 4 &&
776 multi_instances_smaller_than_primgroup)
777 wd_switch_on_eop = true;
778
779 /* Required on CIK and later. */
780 if (info->max_se > 2 && !wd_switch_on_eop)
781 ia_switch_on_eoi = true;
782
783 /* Required by Hawaii and, for some special cases, by VI. */
784 if (ia_switch_on_eoi &&
785 (family == CHIP_HAWAII ||
786 (chip_class == VI &&
787 /* max primgroup in wave is always 2 - leave this for documentation */
788 (radv_pipeline_has_gs(cmd_buffer->state.pipeline) || max_primgroup_in_wave != 2))))
789 partial_vs_wave = true;
790
791 /* Instancing bug on Bonaire. */
792 if (family == CHIP_BONAIRE && ia_switch_on_eoi &&
793 (instanced_draw || indirect_draw))
794 partial_vs_wave = true;
795
796 /* If the WD switch is false, the IA switch must be false too. */
797 assert(wd_switch_on_eop || !ia_switch_on_eop);
798 }
799 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
800 if (chip_class <= VI && ia_switch_on_eoi)
801 partial_es_wave = true;
802
803 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline)) {
804 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
805 * The hw doc says all multi-SE chips are affected, but amdgpu-pro Vulkan
806 * only applies it to Hawaii. Do what amdgpu-pro Vulkan does.
807 */
808 if (family == CHIP_HAWAII && ia_switch_on_eoi) {
809 bool set_vgt_flush = indirect_draw;
810 if (!set_vgt_flush && instanced_draw) {
811 uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
812 if (num_prims <= 1)
813 set_vgt_flush = true;
814 }
815 if (set_vgt_flush)
816 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
817 }
818 }
819
820 return cmd_buffer->state.pipeline->graphics.base_ia_multi_vgt_param |
821 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
822 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
823 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
824 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
825 S_028AA8_WD_SWITCH_ON_EOP(chip_class >= CIK ? wd_switch_on_eop : 0);
826
827 }
828
829 void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
830 bool predicated,
831 enum chip_class chip_class,
832 bool is_mec,
833 unsigned event, unsigned event_flags,
834 unsigned data_sel,
835 uint64_t va,
836 uint32_t old_fence,
837 uint32_t new_fence)
838 {
839 unsigned op = EVENT_TYPE(event) |
840 EVENT_INDEX(5) |
841 event_flags;
842 unsigned is_gfx8_mec = is_mec && chip_class < GFX9;
843
844 if (chip_class >= GFX9 || is_gfx8_mec) {
845 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, is_gfx8_mec ? 5 : 6, predicated));
846 radeon_emit(cs, op);
847 radeon_emit(cs, EOP_DATA_SEL(data_sel));
848 radeon_emit(cs, va); /* address lo */
849 radeon_emit(cs, va >> 32); /* address hi */
850 radeon_emit(cs, new_fence); /* immediate data lo */
851 radeon_emit(cs, 0); /* immediate data hi */
852 if (!is_gfx8_mec)
853 radeon_emit(cs, 0); /* unused */
854 } else {
855 if (chip_class == CIK ||
856 chip_class == VI) {
857 /* Two EOP events are required to make all engines go idle
858 * (and optional cache flushes executed) before the timestamp
859 * is written.
860 */
861 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, predicated));
862 radeon_emit(cs, op);
863 radeon_emit(cs, va);
864 radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel));
865 radeon_emit(cs, old_fence); /* immediate data */
866 radeon_emit(cs, 0); /* unused */
867 }
868
869 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, predicated));
870 radeon_emit(cs, op);
871 radeon_emit(cs, va);
872 radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel));
873 radeon_emit(cs, new_fence); /* immediate data */
874 radeon_emit(cs, 0); /* unused */
875 }
876 }
877
878 void
879 si_emit_wait_fence(struct radeon_winsys_cs *cs,
880 bool predicated,
881 uint64_t va, uint32_t ref,
882 uint32_t mask)
883 {
884 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, predicated));
885 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
886 radeon_emit(cs, va);
887 radeon_emit(cs, va >> 32);
888 radeon_emit(cs, ref); /* reference value */
889 radeon_emit(cs, mask); /* mask */
890 radeon_emit(cs, 4); /* poll interval */
891 }
892
893 static void
894 si_emit_acquire_mem(struct radeon_winsys_cs *cs,
895 bool is_mec,
896 bool predicated,
897 bool is_gfx9,
898 unsigned cp_coher_cntl)
899 {
900 if (is_mec || is_gfx9) {
901 uint32_t hi_val = is_gfx9 ? 0xffffff : 0xff;
902 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, predicated) |
903 PKT3_SHADER_TYPE_S(is_mec));
904 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
905 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
906 radeon_emit(cs, hi_val); /* CP_COHER_SIZE_HI */
907 radeon_emit(cs, 0); /* CP_COHER_BASE */
908 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
909 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
910 } else {
911 /* ACQUIRE_MEM is only required on a compute ring. */
912 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, predicated));
913 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
914 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
915 radeon_emit(cs, 0); /* CP_COHER_BASE */
916 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
917 }
918 }
919
920 void
921 si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
922 bool predicated,
923 enum chip_class chip_class,
924 uint32_t *flush_cnt,
925 uint64_t flush_va,
926 bool is_mec,
927 enum radv_cmd_flush_bits flush_bits)
928 {
929 unsigned cp_coher_cntl = 0;
930 uint32_t flush_cb_db = flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
931 RADV_CMD_FLAG_FLUSH_AND_INV_DB);
932
933 if (flush_bits & RADV_CMD_FLAG_INV_ICACHE)
934 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
935 if (flush_bits & RADV_CMD_FLAG_INV_SMEM_L1)
936 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
937
938 if (chip_class <= VI) {
939 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
940 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
941 S_0085F0_CB0_DEST_BASE_ENA(1) |
942 S_0085F0_CB1_DEST_BASE_ENA(1) |
943 S_0085F0_CB2_DEST_BASE_ENA(1) |
944 S_0085F0_CB3_DEST_BASE_ENA(1) |
945 S_0085F0_CB4_DEST_BASE_ENA(1) |
946 S_0085F0_CB5_DEST_BASE_ENA(1) |
947 S_0085F0_CB6_DEST_BASE_ENA(1) |
948 S_0085F0_CB7_DEST_BASE_ENA(1);
949
950 /* Necessary for DCC */
951 if (chip_class >= VI) {
952 si_cs_emit_write_event_eop(cs,
953 predicated,
954 chip_class,
955 is_mec,
956 V_028A90_FLUSH_AND_INV_CB_DATA_TS,
957 0, 0, 0, 0, 0);
958 }
959 }
960 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
961 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
962 S_0085F0_DB_DEST_BASE_ENA(1);
963 }
964 }
965
966 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) {
967 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, predicated));
968 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
969 }
970
971 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) {
972 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, predicated));
973 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
974 }
975
976 if (flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) {
977 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
978 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
979 } else if (flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) {
980 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
981 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
982 }
983
984 if (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) {
985 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, predicated));
986 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
987 }
988
989 if (chip_class >= GFX9 && flush_cb_db) {
990 unsigned cb_db_event, tc_flags;
991
992 /* Set the CB/DB flush event. */
993 switch (flush_cb_db) {
994 case RADV_CMD_FLAG_FLUSH_AND_INV_CB:
995 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
996 break;
997 case RADV_CMD_FLAG_FLUSH_AND_INV_DB:
998 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
999 break;
1000 default:
1001 /* both CB & DB */
1002 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1003 }
1004
1005 /* TC | TC_WB = invalidate L2 data
1006 * TC_MD | TC_WB = invalidate L2 metadata
1007 * TC | TC_WB | TC_MD = invalidate L2 data & metadata
1008 *
1009 * The metadata cache must always be invalidated for coherency
1010 * between CB/DB and shaders. (metadata = HTILE, CMASK, DCC)
1011 *
1012 * TC must be invalidated on GFX9 only if the CB/DB surface is
1013 * not pipe-aligned. If the surface is RB-aligned, it might not
1014 * strictly be pipe-aligned since RB alignment takes precendence.
1015 */
1016 tc_flags = EVENT_TC_WB_ACTION_ENA |
1017 EVENT_TC_MD_ACTION_ENA;
1018
1019 /* Ideally flush TC together with CB/DB. */
1020 if (flush_bits & RADV_CMD_FLAG_INV_GLOBAL_L2) {
1021 tc_flags |= EVENT_TC_ACTION_ENA |
1022 EVENT_TCL1_ACTION_ENA;
1023
1024 /* Clear the flags. */
1025 flush_bits &= ~(RADV_CMD_FLAG_INV_GLOBAL_L2 |
1026 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 |
1027 RADV_CMD_FLAG_INV_VMEM_L1);
1028 }
1029 assert(flush_cnt);
1030 uint32_t old_fence = (*flush_cnt)++;
1031
1032 si_cs_emit_write_event_eop(cs, predicated, chip_class, false, cb_db_event, tc_flags, 1,
1033 flush_va, old_fence, *flush_cnt);
1034 si_emit_wait_fence(cs, predicated, flush_va, *flush_cnt, 0xffffffff);
1035 }
1036
1037 /* VGT state sync */
1038 if (flush_bits & RADV_CMD_FLAG_VGT_FLUSH) {
1039 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, predicated));
1040 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1041 }
1042
1043 /* Make sure ME is idle (it executes most packets) before continuing.
1044 * This prevents read-after-write hazards between PFP and ME.
1045 */
1046 if ((cp_coher_cntl ||
1047 (flush_bits & (RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
1048 RADV_CMD_FLAG_INV_VMEM_L1 |
1049 RADV_CMD_FLAG_INV_GLOBAL_L2 |
1050 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2))) &&
1051 !is_mec) {
1052 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, predicated));
1053 radeon_emit(cs, 0);
1054 }
1055
1056 if ((flush_bits & RADV_CMD_FLAG_INV_GLOBAL_L2) ||
1057 (chip_class <= CIK && (flush_bits & RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2))) {
1058 si_emit_acquire_mem(cs, is_mec, predicated, chip_class >= GFX9,
1059 cp_coher_cntl |
1060 S_0085F0_TC_ACTION_ENA(1) |
1061 S_0085F0_TCL1_ACTION_ENA(1) |
1062 S_0301F0_TC_WB_ACTION_ENA(chip_class >= VI));
1063 cp_coher_cntl = 0;
1064 } else {
1065 if(flush_bits & RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2) {
1066 /* WB = write-back
1067 * NC = apply to non-coherent MTYPEs
1068 * (i.e. MTYPE <= 1, which is what we use everywhere)
1069 *
1070 * WB doesn't work without NC.
1071 */
1072 si_emit_acquire_mem(cs, is_mec, predicated,
1073 chip_class >= GFX9,
1074 cp_coher_cntl |
1075 S_0301F0_TC_WB_ACTION_ENA(1) |
1076 S_0301F0_TC_NC_ACTION_ENA(1));
1077 cp_coher_cntl = 0;
1078 }
1079 if (flush_bits & RADV_CMD_FLAG_INV_VMEM_L1) {
1080 si_emit_acquire_mem(cs, is_mec,
1081 predicated, chip_class >= GFX9,
1082 cp_coher_cntl |
1083 S_0085F0_TCL1_ACTION_ENA(1));
1084 cp_coher_cntl = 0;
1085 }
1086 }
1087
1088 /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
1089 * Therefore, it should be last. Done in PFP.
1090 */
1091 if (cp_coher_cntl)
1092 si_emit_acquire_mem(cs, is_mec, predicated, chip_class >= GFX9, cp_coher_cntl);
1093 }
1094
1095 void
1096 si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer)
1097 {
1098 bool is_compute = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
1099
1100 if (is_compute)
1101 cmd_buffer->state.flush_bits &= ~(RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1102 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1103 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1104 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1105 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
1106 RADV_CMD_FLAG_VS_PARTIAL_FLUSH |
1107 RADV_CMD_FLAG_VGT_FLUSH);
1108
1109 if (!cmd_buffer->state.flush_bits)
1110 return;
1111
1112 enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
1113 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 128);
1114
1115 uint32_t *ptr = NULL;
1116 uint64_t va = 0;
1117 if (chip_class == GFX9) {
1118 va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) + cmd_buffer->gfx9_fence_offset;
1119 ptr = &cmd_buffer->gfx9_fence_idx;
1120 }
1121 si_cs_emit_cache_flush(cmd_buffer->cs,
1122 cmd_buffer->state.predicating,
1123 cmd_buffer->device->physical_device->rad_info.chip_class,
1124 ptr, va,
1125 radv_cmd_buffer_uses_mec(cmd_buffer),
1126 cmd_buffer->state.flush_bits);
1127
1128
1129 radv_cmd_buffer_trace_emit(cmd_buffer);
1130 cmd_buffer->state.flush_bits = 0;
1131 }
1132
1133 /* sets the CP predication state using a boolean stored at va */
1134 void
1135 si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
1136 {
1137 uint32_t op = 0;
1138
1139 if (va)
1140 op = PRED_OP(PREDICATION_OP_BOOL64) | PREDICATION_DRAW_VISIBLE;
1141 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1142 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 2, 0));
1143 radeon_emit(cmd_buffer->cs, op);
1144 radeon_emit(cmd_buffer->cs, va);
1145 radeon_emit(cmd_buffer->cs, va >> 32);
1146 } else {
1147 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
1148 radeon_emit(cmd_buffer->cs, va);
1149 radeon_emit(cmd_buffer->cs, op | ((va >> 32) & 0xFF));
1150 }
1151 }
1152
1153 /* Set this if you want the 3D engine to wait until CP DMA is done.
1154 * It should be set on the last CP DMA packet. */
1155 #define CP_DMA_SYNC (1 << 0)
1156
1157 /* Set this if the source data was used as a destination in a previous CP DMA
1158 * packet. It's for preventing a read-after-write (RAW) hazard between two
1159 * CP DMA packets. */
1160 #define CP_DMA_RAW_WAIT (1 << 1)
1161 #define CP_DMA_USE_L2 (1 << 2)
1162 #define CP_DMA_CLEAR (1 << 3)
1163
1164 /* Alignment for optimal performance. */
1165 #define SI_CPDMA_ALIGNMENT 32
1166
1167 /* The max number of bytes that can be copied per packet. */
1168 static inline unsigned cp_dma_max_byte_count(struct radv_cmd_buffer *cmd_buffer)
1169 {
1170 unsigned max = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 ?
1171 S_414_BYTE_COUNT_GFX9(~0u) :
1172 S_414_BYTE_COUNT_GFX6(~0u);
1173
1174 /* make it aligned for optimal performance */
1175 return max & ~(SI_CPDMA_ALIGNMENT - 1);
1176 }
1177
1178 /* Emit a CP DMA packet to do a copy from one buffer to another, or to clear
1179 * a buffer. The size must fit in bits [20:0]. If CP_DMA_CLEAR is set, src_va is a 32-bit
1180 * clear value.
1181 */
1182 static void si_emit_cp_dma(struct radv_cmd_buffer *cmd_buffer,
1183 uint64_t dst_va, uint64_t src_va,
1184 unsigned size, unsigned flags)
1185 {
1186 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1187 uint32_t header = 0, command = 0;
1188
1189 assert(size);
1190 assert(size <= cp_dma_max_byte_count(cmd_buffer));
1191
1192 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9);
1193 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1194 command |= S_414_BYTE_COUNT_GFX9(size);
1195 else
1196 command |= S_414_BYTE_COUNT_GFX6(size);
1197
1198 /* Sync flags. */
1199 if (flags & CP_DMA_SYNC)
1200 header |= S_411_CP_SYNC(1);
1201 else {
1202 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1203 command |= S_414_DISABLE_WR_CONFIRM_GFX9(1);
1204 else
1205 command |= S_414_DISABLE_WR_CONFIRM_GFX6(1);
1206 }
1207
1208 if (flags & CP_DMA_RAW_WAIT)
1209 command |= S_414_RAW_WAIT(1);
1210
1211 /* Src and dst flags. */
1212 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
1213 !(flags & CP_DMA_CLEAR) &&
1214 src_va == dst_va)
1215 header |= S_411_DSL_SEL(V_411_NOWHERE); /* prefetch only */
1216 else if (flags & CP_DMA_USE_L2)
1217 header |= S_411_DSL_SEL(V_411_DST_ADDR_TC_L2);
1218
1219 if (flags & CP_DMA_CLEAR)
1220 header |= S_411_SRC_SEL(V_411_DATA);
1221 else if (flags & CP_DMA_USE_L2)
1222 header |= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2);
1223
1224 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1225 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, cmd_buffer->state.predicating));
1226 radeon_emit(cs, header);
1227 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1228 radeon_emit(cs, src_va >> 32); /* SRC_ADDR_HI [31:0] */
1229 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1230 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [31:0] */
1231 radeon_emit(cs, command);
1232 } else {
1233 assert(!(flags & CP_DMA_USE_L2));
1234 header |= S_411_SRC_ADDR_HI(src_va >> 32);
1235 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, cmd_buffer->state.predicating));
1236 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1237 radeon_emit(cs, header); /* SRC_ADDR_HI [15:0] + flags. */
1238 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1239 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
1240 radeon_emit(cs, command);
1241 }
1242
1243 /* CP DMA is executed in ME, but index buffers are read by PFP.
1244 * This ensures that ME (CP DMA) is idle before PFP starts fetching
1245 * indices. If we wanted to execute CP DMA in PFP, this packet
1246 * should precede it.
1247 */
1248 if ((flags & CP_DMA_SYNC) && cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
1249 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1250 radeon_emit(cs, 0);
1251 }
1252
1253 radv_cmd_buffer_trace_emit(cmd_buffer);
1254 }
1255
1256 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1257 unsigned size)
1258 {
1259 uint64_t aligned_va = va & ~(SI_CPDMA_ALIGNMENT - 1);
1260 uint64_t aligned_size = ((va + size + SI_CPDMA_ALIGNMENT -1) & ~(SI_CPDMA_ALIGNMENT - 1)) - aligned_va;
1261
1262 si_emit_cp_dma(cmd_buffer, aligned_va, aligned_va,
1263 aligned_size, CP_DMA_USE_L2);
1264 }
1265
1266 static void si_cp_dma_prepare(struct radv_cmd_buffer *cmd_buffer, uint64_t byte_count,
1267 uint64_t remaining_size, unsigned *flags)
1268 {
1269
1270 /* Flush the caches for the first copy only.
1271 * Also wait for the previous CP DMA operations.
1272 */
1273 if (cmd_buffer->state.flush_bits) {
1274 si_emit_cache_flush(cmd_buffer);
1275 *flags |= CP_DMA_RAW_WAIT;
1276 }
1277
1278 /* Do the synchronization after the last dma, so that all data
1279 * is written to memory.
1280 */
1281 if (byte_count == remaining_size)
1282 *flags |= CP_DMA_SYNC;
1283 }
1284
1285 static void si_cp_dma_realign_engine(struct radv_cmd_buffer *cmd_buffer, unsigned size)
1286 {
1287 uint64_t va;
1288 uint32_t offset;
1289 unsigned dma_flags = 0;
1290 unsigned buf_size = SI_CPDMA_ALIGNMENT * 2;
1291 void *ptr;
1292
1293 assert(size < SI_CPDMA_ALIGNMENT);
1294
1295 radv_cmd_buffer_upload_alloc(cmd_buffer, buf_size, SI_CPDMA_ALIGNMENT, &offset, &ptr);
1296
1297 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1298 va += offset;
1299
1300 si_cp_dma_prepare(cmd_buffer, size, size, &dma_flags);
1301
1302 si_emit_cp_dma(cmd_buffer, va, va + SI_CPDMA_ALIGNMENT, size,
1303 dma_flags);
1304 }
1305
1306 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1307 uint64_t src_va, uint64_t dest_va,
1308 uint64_t size)
1309 {
1310 uint64_t main_src_va, main_dest_va;
1311 uint64_t skipped_size = 0, realign_size = 0;
1312
1313
1314 if (cmd_buffer->device->physical_device->rad_info.family <= CHIP_CARRIZO ||
1315 cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY) {
1316 /* If the size is not aligned, we must add a dummy copy at the end
1317 * just to align the internal counter. Otherwise, the DMA engine
1318 * would slow down by an order of magnitude for following copies.
1319 */
1320 if (size % SI_CPDMA_ALIGNMENT)
1321 realign_size = SI_CPDMA_ALIGNMENT - (size % SI_CPDMA_ALIGNMENT);
1322
1323 /* If the copy begins unaligned, we must start copying from the next
1324 * aligned block and the skipped part should be copied after everything
1325 * else has been copied. Only the src alignment matters, not dst.
1326 */
1327 if (src_va % SI_CPDMA_ALIGNMENT) {
1328 skipped_size = SI_CPDMA_ALIGNMENT - (src_va % SI_CPDMA_ALIGNMENT);
1329 /* The main part will be skipped if the size is too small. */
1330 skipped_size = MIN2(skipped_size, size);
1331 size -= skipped_size;
1332 }
1333 }
1334 main_src_va = src_va + skipped_size;
1335 main_dest_va = dest_va + skipped_size;
1336
1337 while (size) {
1338 unsigned dma_flags = 0;
1339 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1340
1341 si_cp_dma_prepare(cmd_buffer, byte_count,
1342 size + skipped_size + realign_size,
1343 &dma_flags);
1344
1345 si_emit_cp_dma(cmd_buffer, main_dest_va, main_src_va,
1346 byte_count, dma_flags);
1347
1348 size -= byte_count;
1349 main_src_va += byte_count;
1350 main_dest_va += byte_count;
1351 }
1352
1353 if (skipped_size) {
1354 unsigned dma_flags = 0;
1355
1356 si_cp_dma_prepare(cmd_buffer, skipped_size,
1357 size + skipped_size + realign_size,
1358 &dma_flags);
1359
1360 si_emit_cp_dma(cmd_buffer, dest_va, src_va,
1361 skipped_size, dma_flags);
1362 }
1363 if (realign_size)
1364 si_cp_dma_realign_engine(cmd_buffer, realign_size);
1365 }
1366
1367 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1368 uint64_t size, unsigned value)
1369 {
1370
1371 if (!size)
1372 return;
1373
1374 assert(va % 4 == 0 && size % 4 == 0);
1375
1376 while (size) {
1377 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1378 unsigned dma_flags = CP_DMA_CLEAR;
1379
1380 si_cp_dma_prepare(cmd_buffer, byte_count, size, &dma_flags);
1381
1382 /* Emit the clear packet. */
1383 si_emit_cp_dma(cmd_buffer, va, value, byte_count,
1384 dma_flags);
1385
1386 size -= byte_count;
1387 va += byte_count;
1388 }
1389 }
1390
1391 /* For MSAA sample positions. */
1392 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1393 (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) | \
1394 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
1395 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
1396 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
1397
1398
1399 /* 2xMSAA
1400 * There are two locations (4, 4), (-4, -4). */
1401 const uint32_t eg_sample_locs_2x[4] = {
1402 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1403 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1404 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1405 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
1406 };
1407 const unsigned eg_max_dist_2x = 4;
1408 /* 4xMSAA
1409 * There are 4 locations: (-2, 6), (6, -2), (-6, 2), (2, 6). */
1410 const uint32_t eg_sample_locs_4x[4] = {
1411 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1412 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1413 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1414 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
1415 };
1416 const unsigned eg_max_dist_4x = 6;
1417
1418 /* Cayman 8xMSAA */
1419 static const uint32_t cm_sample_locs_8x[] = {
1420 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1421 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1422 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1423 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
1424 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1425 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1426 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1427 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1428 };
1429 static const unsigned cm_max_dist_8x = 8;
1430 /* Cayman 16xMSAA */
1431 static const uint32_t cm_sample_locs_16x[] = {
1432 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1433 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1434 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1435 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
1436 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1437 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1438 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1439 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
1440 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1441 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1442 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1443 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
1444 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1445 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1446 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1447 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
1448 };
1449 static const unsigned cm_max_dist_16x = 8;
1450
1451 unsigned radv_cayman_get_maxdist(int log_samples)
1452 {
1453 unsigned max_dist[] = {
1454 0,
1455 eg_max_dist_2x,
1456 eg_max_dist_4x,
1457 cm_max_dist_8x,
1458 cm_max_dist_16x
1459 };
1460 return max_dist[log_samples];
1461 }
1462
1463 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples)
1464 {
1465 switch (nr_samples) {
1466 default:
1467 case 1:
1468 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0);
1469 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0);
1470 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0);
1471 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0);
1472 break;
1473 case 2:
1474 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_2x[0]);
1475 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_2x[1]);
1476 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_2x[2]);
1477 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_2x[3]);
1478 break;
1479 case 4:
1480 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_4x[0]);
1481 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_4x[1]);
1482 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_4x[2]);
1483 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_4x[3]);
1484 break;
1485 case 8:
1486 radeon_set_context_reg_seq(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
1487 radeon_emit(cs, cm_sample_locs_8x[0]);
1488 radeon_emit(cs, cm_sample_locs_8x[4]);
1489 radeon_emit(cs, 0);
1490 radeon_emit(cs, 0);
1491 radeon_emit(cs, cm_sample_locs_8x[1]);
1492 radeon_emit(cs, cm_sample_locs_8x[5]);
1493 radeon_emit(cs, 0);
1494 radeon_emit(cs, 0);
1495 radeon_emit(cs, cm_sample_locs_8x[2]);
1496 radeon_emit(cs, cm_sample_locs_8x[6]);
1497 radeon_emit(cs, 0);
1498 radeon_emit(cs, 0);
1499 radeon_emit(cs, cm_sample_locs_8x[3]);
1500 radeon_emit(cs, cm_sample_locs_8x[7]);
1501 break;
1502 case 16:
1503 radeon_set_context_reg_seq(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 16);
1504 radeon_emit(cs, cm_sample_locs_16x[0]);
1505 radeon_emit(cs, cm_sample_locs_16x[4]);
1506 radeon_emit(cs, cm_sample_locs_16x[8]);
1507 radeon_emit(cs, cm_sample_locs_16x[12]);
1508 radeon_emit(cs, cm_sample_locs_16x[1]);
1509 radeon_emit(cs, cm_sample_locs_16x[5]);
1510 radeon_emit(cs, cm_sample_locs_16x[9]);
1511 radeon_emit(cs, cm_sample_locs_16x[13]);
1512 radeon_emit(cs, cm_sample_locs_16x[2]);
1513 radeon_emit(cs, cm_sample_locs_16x[6]);
1514 radeon_emit(cs, cm_sample_locs_16x[10]);
1515 radeon_emit(cs, cm_sample_locs_16x[14]);
1516 radeon_emit(cs, cm_sample_locs_16x[3]);
1517 radeon_emit(cs, cm_sample_locs_16x[7]);
1518 radeon_emit(cs, cm_sample_locs_16x[11]);
1519 radeon_emit(cs, cm_sample_locs_16x[15]);
1520 break;
1521 }
1522 }
1523
1524 static void radv_cayman_get_sample_position(struct radv_device *device,
1525 unsigned sample_count,
1526 unsigned sample_index, float *out_value)
1527 {
1528 int offset, index;
1529 struct {
1530 int idx:4;
1531 } val;
1532 switch (sample_count) {
1533 case 1:
1534 default:
1535 out_value[0] = out_value[1] = 0.5;
1536 break;
1537 case 2:
1538 offset = 4 * (sample_index * 2);
1539 val.idx = (eg_sample_locs_2x[0] >> offset) & 0xf;
1540 out_value[0] = (float)(val.idx + 8) / 16.0f;
1541 val.idx = (eg_sample_locs_2x[0] >> (offset + 4)) & 0xf;
1542 out_value[1] = (float)(val.idx + 8) / 16.0f;
1543 break;
1544 case 4:
1545 offset = 4 * (sample_index * 2);
1546 val.idx = (eg_sample_locs_4x[0] >> offset) & 0xf;
1547 out_value[0] = (float)(val.idx + 8) / 16.0f;
1548 val.idx = (eg_sample_locs_4x[0] >> (offset + 4)) & 0xf;
1549 out_value[1] = (float)(val.idx + 8) / 16.0f;
1550 break;
1551 case 8:
1552 offset = 4 * (sample_index % 4 * 2);
1553 index = (sample_index / 4) * 4;
1554 val.idx = (cm_sample_locs_8x[index] >> offset) & 0xf;
1555 out_value[0] = (float)(val.idx + 8) / 16.0f;
1556 val.idx = (cm_sample_locs_8x[index] >> (offset + 4)) & 0xf;
1557 out_value[1] = (float)(val.idx + 8) / 16.0f;
1558 break;
1559 case 16:
1560 offset = 4 * (sample_index % 4 * 2);
1561 index = (sample_index / 4) * 4;
1562 val.idx = (cm_sample_locs_16x[index] >> offset) & 0xf;
1563 out_value[0] = (float)(val.idx + 8) / 16.0f;
1564 val.idx = (cm_sample_locs_16x[index] >> (offset + 4)) & 0xf;
1565 out_value[1] = (float)(val.idx + 8) / 16.0f;
1566 break;
1567 }
1568 }
1569
1570 void radv_device_init_msaa(struct radv_device *device)
1571 {
1572 int i;
1573 radv_cayman_get_sample_position(device, 1, 0, device->sample_locations_1x[0]);
1574
1575 for (i = 0; i < 2; i++)
1576 radv_cayman_get_sample_position(device, 2, i, device->sample_locations_2x[i]);
1577 for (i = 0; i < 4; i++)
1578 radv_cayman_get_sample_position(device, 4, i, device->sample_locations_4x[i]);
1579 for (i = 0; i < 8; i++)
1580 radv_cayman_get_sample_position(device, 8, i, device->sample_locations_8x[i]);
1581 for (i = 0; i < 16; i++)
1582 radv_cayman_get_sample_position(device, 16, i, device->sample_locations_16x[i]);
1583 }