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radv: fix some compiler warnings
[mesa.git] / src / amd / vulkan / si_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based on si_state.c
6 * Copyright © 2015 Advanced Micro Devices, Inc.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 /* command buffer handling for AMD GCN */
29
30 #include "radv_private.h"
31 #include "radv_shader.h"
32 #include "radv_cs.h"
33 #include "sid.h"
34 #include "radv_util.h"
35 #include "main/macros.h"
36
37 static void
38 si_write_harvested_raster_configs(struct radv_physical_device *physical_device,
39 struct radeon_cmdbuf *cs,
40 unsigned raster_config,
41 unsigned raster_config_1)
42 {
43 unsigned num_se = MAX2(physical_device->rad_info.max_se, 1);
44 unsigned raster_config_se[4];
45 unsigned se;
46
47 ac_get_harvested_configs(&physical_device->rad_info,
48 raster_config,
49 &raster_config_1,
50 raster_config_se);
51
52 for (se = 0; se < num_se; se++) {
53 /* GRBM_GFX_INDEX has a different offset on GFX6 and GFX7+ */
54 if (physical_device->rad_info.chip_class < GFX7)
55 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
56 S_00802C_SE_INDEX(se) |
57 S_00802C_SH_BROADCAST_WRITES(1) |
58 S_00802C_INSTANCE_BROADCAST_WRITES(1));
59 else
60 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
61 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
62 S_030800_INSTANCE_BROADCAST_WRITES(1));
63 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
64 }
65
66 /* GRBM_GFX_INDEX has a different offset on GFX6 and GFX7+ */
67 if (physical_device->rad_info.chip_class < GFX7)
68 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
69 S_00802C_SE_BROADCAST_WRITES(1) |
70 S_00802C_SH_BROADCAST_WRITES(1) |
71 S_00802C_INSTANCE_BROADCAST_WRITES(1));
72 else
73 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
74 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
75 S_030800_INSTANCE_BROADCAST_WRITES(1));
76
77 if (physical_device->rad_info.chip_class >= GFX7)
78 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
79 }
80
81 void
82 si_emit_compute(struct radv_physical_device *physical_device,
83 struct radeon_cmdbuf *cs)
84 {
85 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
86 radeon_emit(cs, 0);
87 radeon_emit(cs, 0);
88 radeon_emit(cs, 0);
89
90 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
91 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
92 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
93 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
94
95 if (physical_device->rad_info.chip_class >= GFX7) {
96 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
97 radeon_set_sh_reg_seq(cs,
98 R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
99 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
100 S_00B858_SH1_CU_EN(0xffff));
101 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
102 S_00B858_SH1_CU_EN(0xffff));
103 }
104
105 /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
106 * and is now per pipe, so it should be handled in the
107 * kernel if we want to use something other than the default value,
108 * which is now 0x22f.
109 */
110 if (physical_device->rad_info.chip_class <= GFX6) {
111 /* XXX: This should be:
112 * (number of compute units) * 4 * (waves per simd) - 1 */
113
114 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
115 0x190 /* Default value */);
116 }
117 }
118
119 /* 12.4 fixed-point */
120 static unsigned radv_pack_float_12p4(float x)
121 {
122 return x <= 0 ? 0 :
123 x >= 4096 ? 0xffff : x * 16;
124 }
125
126 static void
127 si_set_raster_config(struct radv_physical_device *physical_device,
128 struct radeon_cmdbuf *cs)
129 {
130 unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16);
131 unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
132 unsigned raster_config, raster_config_1;
133
134 ac_get_raster_config(&physical_device->rad_info,
135 &raster_config,
136 &raster_config_1, NULL);
137
138 /* Always use the default config when all backends are enabled
139 * (or when we failed to determine the enabled backends).
140 */
141 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
142 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG,
143 raster_config);
144 if (physical_device->rad_info.chip_class >= GFX7)
145 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1,
146 raster_config_1);
147 } else {
148 si_write_harvested_raster_configs(physical_device, cs,
149 raster_config,
150 raster_config_1);
151 }
152 }
153
154 void
155 si_emit_graphics(struct radv_physical_device *physical_device,
156 struct radeon_cmdbuf *cs)
157 {
158 int i;
159
160 /* Only GFX6 can disable CLEAR_STATE for now. */
161 assert(physical_device->has_clear_state ||
162 physical_device->rad_info.chip_class == GFX6);
163
164 radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
165 radeon_emit(cs, CONTEXT_CONTROL_LOAD_ENABLE(1));
166 radeon_emit(cs, CONTEXT_CONTROL_SHADOW_ENABLE(1));
167
168 if (physical_device->has_clear_state) {
169 radeon_emit(cs, PKT3(PKT3_CLEAR_STATE, 0, 0));
170 radeon_emit(cs, 0);
171 }
172
173 if (physical_device->rad_info.chip_class <= GFX8)
174 si_set_raster_config(physical_device, cs);
175
176 radeon_set_context_reg(cs, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
177 if (!physical_device->has_clear_state)
178 radeon_set_context_reg(cs, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
179
180 /* FIXME calculate these values somehow ??? */
181 if (physical_device->rad_info.chip_class <= GFX8) {
182 radeon_set_context_reg(cs, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
183 radeon_set_context_reg(cs, R_028A58_VGT_ES_PER_GS, 0x40);
184 }
185
186 if (!physical_device->has_clear_state) {
187 radeon_set_context_reg(cs, R_028A5C_VGT_GS_PER_VS, 0x2);
188 radeon_set_context_reg(cs, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
189 radeon_set_context_reg(cs, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
190 }
191
192 radeon_set_context_reg(cs, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
193 if (!physical_device->has_clear_state)
194 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, 0x0);
195 if (physical_device->rad_info.chip_class < GFX7)
196 radeon_set_config_reg(cs, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
197 S_008A14_CLIP_VTX_REORDER_ENA(1));
198
199 if (!physical_device->has_clear_state)
200 radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
201
202 /* CLEAR_STATE doesn't clear these correctly on certain generations.
203 * I don't know why. Deduced by trial and error.
204 */
205 if (physical_device->rad_info.chip_class <= GFX7) {
206 radeon_set_context_reg(cs, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
207 radeon_set_context_reg(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL,
208 S_028204_WINDOW_OFFSET_DISABLE(1));
209 radeon_set_context_reg(cs, R_028240_PA_SC_GENERIC_SCISSOR_TL,
210 S_028240_WINDOW_OFFSET_DISABLE(1));
211 radeon_set_context_reg(cs, R_028244_PA_SC_GENERIC_SCISSOR_BR,
212 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
213 radeon_set_context_reg(cs, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
214 radeon_set_context_reg(cs, R_028034_PA_SC_SCREEN_SCISSOR_BR,
215 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
216 }
217
218 if (!physical_device->has_clear_state) {
219 for (i = 0; i < 16; i++) {
220 radeon_set_context_reg(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
221 radeon_set_context_reg(cs, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
222 }
223 }
224
225 if (!physical_device->has_clear_state) {
226 radeon_set_context_reg(cs, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
227 radeon_set_context_reg(cs, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
228 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on GFX6 */
229 radeon_set_context_reg(cs, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
230 radeon_set_context_reg(cs, R_028820_PA_CL_NANINF_CNTL, 0);
231 radeon_set_context_reg(cs, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
232 radeon_set_context_reg(cs, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
233 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
234 }
235
236 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE,
237 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
238 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
239
240 if (physical_device->rad_info.chip_class >= GFX9) {
241 radeon_set_uconfig_reg(cs, R_030920_VGT_MAX_VTX_INDX, ~0);
242 radeon_set_uconfig_reg(cs, R_030924_VGT_MIN_VTX_INDX, 0);
243 radeon_set_uconfig_reg(cs, R_030928_VGT_INDX_OFFSET, 0);
244 } else {
245 /* These registers, when written, also overwrite the
246 * CLEAR_STATE context, so we can't rely on CLEAR_STATE setting
247 * them. It would be an issue if there was another UMD
248 * changing them.
249 */
250 radeon_set_context_reg(cs, R_028400_VGT_MAX_VTX_INDX, ~0);
251 radeon_set_context_reg(cs, R_028404_VGT_MIN_VTX_INDX, 0);
252 radeon_set_context_reg(cs, R_028408_VGT_INDX_OFFSET, 0);
253 }
254
255 if (physical_device->rad_info.chip_class >= GFX7) {
256 if (physical_device->rad_info.chip_class >= GFX9) {
257 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
258 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
259 } else {
260 radeon_set_sh_reg(cs, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
261 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
262 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
263 S_00B41C_WAVE_LIMIT(0x3F));
264 radeon_set_sh_reg(cs, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
265 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
266 /* If this is 0, Bonaire can hang even if GS isn't being used.
267 * Other chips are unaffected. These are suboptimal values,
268 * but we don't use on-chip GS.
269 */
270 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL,
271 S_028A44_ES_VERTS_PER_SUBGRP(64) |
272 S_028A44_GS_PRIMS_PER_SUBGRP(4));
273 }
274 radeon_set_sh_reg(cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
275 S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
276
277 if (physical_device->rad_info.num_good_cu_per_sh <= 4) {
278 /* Too few available compute units per SH. Disallowing
279 * VS to run on CU0 could hurt us more than late VS
280 * allocation would help.
281 *
282 * LATE_ALLOC_VS = 2 is the highest safe number.
283 */
284 radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
285 S_00B118_CU_EN(0xffff) | S_00B118_WAVE_LIMIT(0x3F) );
286 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
287 } else {
288 /* Set LATE_ALLOC_VS == 31. It should be less than
289 * the number of scratch waves. Limitations:
290 * - VS can't execute on CU0.
291 * - If HS writes outputs to LDS, LS can't execute on CU0.
292 */
293 radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
294 S_00B118_CU_EN(0xfffe) | S_00B118_WAVE_LIMIT(0x3F));
295 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
296 }
297
298 radeon_set_sh_reg(cs, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
299 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
300 }
301
302 if (physical_device->rad_info.chip_class >= GFX8) {
303 uint32_t vgt_tess_distribution;
304
305 vgt_tess_distribution = S_028B50_ACCUM_ISOLINE(32) |
306 S_028B50_ACCUM_TRI(11) |
307 S_028B50_ACCUM_QUAD(11) |
308 S_028B50_DONUT_SPLIT(16);
309
310 if (physical_device->rad_info.family == CHIP_FIJI ||
311 physical_device->rad_info.family >= CHIP_POLARIS10)
312 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
313
314 radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION,
315 vgt_tess_distribution);
316 } else if (!physical_device->has_clear_state) {
317 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
318 radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
319 }
320
321 if (physical_device->rad_info.chip_class >= GFX9) {
322 unsigned num_se = physical_device->rad_info.max_se;
323 unsigned pc_lines = 0;
324
325 switch (physical_device->rad_info.family) {
326 case CHIP_VEGA10:
327 case CHIP_VEGA12:
328 case CHIP_VEGA20:
329 pc_lines = 4096;
330 break;
331 case CHIP_RAVEN:
332 case CHIP_RAVEN2:
333 pc_lines = 1024;
334 break;
335 default:
336 assert(0);
337 }
338
339 radeon_set_context_reg(cs, R_028C48_PA_SC_BINNER_CNTL_1,
340 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines / (4 * num_se))) |
341 S_028C48_MAX_PRIM_PER_BATCH(1023));
342 radeon_set_context_reg(cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
343 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
344 radeon_set_uconfig_reg(cs, R_030968_VGT_INSTANCE_BASE_ID, 0);
345 }
346
347 unsigned tmp = (unsigned)(1.0 * 8.0);
348 radeon_set_context_reg_seq(cs, R_028A00_PA_SU_POINT_SIZE, 1);
349 radeon_emit(cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
350 radeon_set_context_reg_seq(cs, R_028A04_PA_SU_POINT_MINMAX, 1);
351 radeon_emit(cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
352 S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2)));
353
354 if (!physical_device->has_clear_state) {
355 radeon_set_context_reg(cs, R_028004_DB_COUNT_CONTROL,
356 S_028004_ZPASS_INCREMENT_DISABLE(1));
357 }
358
359 /* Enable the Polaris small primitive filter control.
360 * XXX: There is possibly an issue when MSAA is off (see RadeonSI
361 * has_msaa_sample_loc_bug). But this doesn't seem to regress anything,
362 * and AMDVLK doesn't have a workaround as well.
363 */
364 if (physical_device->rad_info.family >= CHIP_POLARIS10) {
365 unsigned small_prim_filter_cntl =
366 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
367 /* Workaround for a hw line bug. */
368 S_028830_LINE_FILTER_DISABLE(physical_device->rad_info.family <= CHIP_POLARIS12);
369
370 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
371 small_prim_filter_cntl);
372 }
373
374 si_emit_compute(physical_device, cs);
375 }
376
377 void
378 cik_create_gfx_config(struct radv_device *device)
379 {
380 struct radeon_cmdbuf *cs = device->ws->cs_create(device->ws, RING_GFX);
381 if (!cs)
382 return;
383
384 si_emit_graphics(device->physical_device, cs);
385
386 while (cs->cdw & 7) {
387 if (device->physical_device->rad_info.gfx_ib_pad_with_type2)
388 radeon_emit(cs, 0x80000000);
389 else
390 radeon_emit(cs, 0xffff1000);
391 }
392
393 device->gfx_init = device->ws->buffer_create(device->ws,
394 cs->cdw * 4, 4096,
395 RADEON_DOMAIN_GTT,
396 RADEON_FLAG_CPU_ACCESS|
397 RADEON_FLAG_NO_INTERPROCESS_SHARING |
398 RADEON_FLAG_READ_ONLY,
399 RADV_BO_PRIORITY_CS);
400 if (!device->gfx_init)
401 goto fail;
402
403 void *map = device->ws->buffer_map(device->gfx_init);
404 if (!map) {
405 device->ws->buffer_destroy(device->gfx_init);
406 device->gfx_init = NULL;
407 goto fail;
408 }
409 memcpy(map, cs->buf, cs->cdw * 4);
410
411 device->ws->buffer_unmap(device->gfx_init);
412 device->gfx_init_size_dw = cs->cdw;
413 fail:
414 device->ws->cs_destroy(cs);
415 }
416
417 static void
418 get_viewport_xform(const VkViewport *viewport,
419 float scale[3], float translate[3])
420 {
421 float x = viewport->x;
422 float y = viewport->y;
423 float half_width = 0.5f * viewport->width;
424 float half_height = 0.5f * viewport->height;
425 double n = viewport->minDepth;
426 double f = viewport->maxDepth;
427
428 scale[0] = half_width;
429 translate[0] = half_width + x;
430 scale[1] = half_height;
431 translate[1] = half_height + y;
432
433 scale[2] = (f - n);
434 translate[2] = n;
435 }
436
437 void
438 si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
439 int count, const VkViewport *viewports)
440 {
441 int i;
442
443 assert(count);
444 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
445 first_vp * 4 * 6, count * 6);
446
447 for (i = 0; i < count; i++) {
448 float scale[3], translate[3];
449
450
451 get_viewport_xform(&viewports[i], scale, translate);
452 radeon_emit(cs, fui(scale[0]));
453 radeon_emit(cs, fui(translate[0]));
454 radeon_emit(cs, fui(scale[1]));
455 radeon_emit(cs, fui(translate[1]));
456 radeon_emit(cs, fui(scale[2]));
457 radeon_emit(cs, fui(translate[2]));
458 }
459
460 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 +
461 first_vp * 4 * 2, count * 2);
462 for (i = 0; i < count; i++) {
463 float zmin = MIN2(viewports[i].minDepth, viewports[i].maxDepth);
464 float zmax = MAX2(viewports[i].minDepth, viewports[i].maxDepth);
465 radeon_emit(cs, fui(zmin));
466 radeon_emit(cs, fui(zmax));
467 }
468 }
469
470 static VkRect2D si_scissor_from_viewport(const VkViewport *viewport)
471 {
472 float scale[3], translate[3];
473 VkRect2D rect;
474
475 get_viewport_xform(viewport, scale, translate);
476
477 rect.offset.x = translate[0] - fabs(scale[0]);
478 rect.offset.y = translate[1] - fabs(scale[1]);
479 rect.extent.width = ceilf(translate[0] + fabs(scale[0])) - rect.offset.x;
480 rect.extent.height = ceilf(translate[1] + fabs(scale[1])) - rect.offset.y;
481
482 return rect;
483 }
484
485 static VkRect2D si_intersect_scissor(const VkRect2D *a, const VkRect2D *b) {
486 VkRect2D ret;
487 ret.offset.x = MAX2(a->offset.x, b->offset.x);
488 ret.offset.y = MAX2(a->offset.y, b->offset.y);
489 ret.extent.width = MIN2(a->offset.x + a->extent.width,
490 b->offset.x + b->extent.width) - ret.offset.x;
491 ret.extent.height = MIN2(a->offset.y + a->extent.height,
492 b->offset.y + b->extent.height) - ret.offset.y;
493 return ret;
494 }
495
496 void
497 si_write_scissors(struct radeon_cmdbuf *cs, int first,
498 int count, const VkRect2D *scissors,
499 const VkViewport *viewports, bool can_use_guardband)
500 {
501 int i;
502 float scale[3], translate[3], guardband_x = INFINITY, guardband_y = INFINITY;
503 const float max_range = 32767.0f;
504 if (!count)
505 return;
506
507 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + first * 4 * 2, count * 2);
508 for (i = 0; i < count; i++) {
509 VkRect2D viewport_scissor = si_scissor_from_viewport(viewports + i);
510 VkRect2D scissor = si_intersect_scissor(&scissors[i], &viewport_scissor);
511
512 get_viewport_xform(viewports + i, scale, translate);
513 scale[0] = fabsf(scale[0]);
514 scale[1] = fabsf(scale[1]);
515
516 if (scale[0] < 0.5)
517 scale[0] = 0.5;
518 if (scale[1] < 0.5)
519 scale[1] = 0.5;
520
521 guardband_x = MIN2(guardband_x, (max_range - fabsf(translate[0])) / scale[0]);
522 guardband_y = MIN2(guardband_y, (max_range - fabsf(translate[1])) / scale[1]);
523
524 radeon_emit(cs, S_028250_TL_X(scissor.offset.x) |
525 S_028250_TL_Y(scissor.offset.y) |
526 S_028250_WINDOW_OFFSET_DISABLE(1));
527 radeon_emit(cs, S_028254_BR_X(scissor.offset.x + scissor.extent.width) |
528 S_028254_BR_Y(scissor.offset.y + scissor.extent.height));
529 }
530 if (!can_use_guardband) {
531 guardband_x = 1.0;
532 guardband_y = 1.0;
533 }
534
535 radeon_set_context_reg_seq(cs, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
536 radeon_emit(cs, fui(guardband_y));
537 radeon_emit(cs, fui(1.0));
538 radeon_emit(cs, fui(guardband_x));
539 radeon_emit(cs, fui(1.0));
540 }
541
542 static inline unsigned
543 radv_prims_for_vertices(struct radv_prim_vertex_count *info, unsigned num)
544 {
545 if (num == 0)
546 return 0;
547
548 if (info->incr == 0)
549 return 0;
550
551 if (num < info->min)
552 return 0;
553
554 return 1 + ((num - info->min) / info->incr);
555 }
556
557 uint32_t
558 si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
559 bool instanced_draw, bool indirect_draw,
560 bool count_from_stream_output,
561 uint32_t draw_vertex_count)
562 {
563 enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
564 enum radeon_family family = cmd_buffer->device->physical_device->rad_info.family;
565 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
566 const unsigned max_primgroup_in_wave = 2;
567 /* SWITCH_ON_EOP(0) is always preferable. */
568 bool wd_switch_on_eop = false;
569 bool ia_switch_on_eop = false;
570 bool ia_switch_on_eoi = false;
571 bool partial_vs_wave = false;
572 bool partial_es_wave = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.partial_es_wave;
573 bool multi_instances_smaller_than_primgroup;
574
575 multi_instances_smaller_than_primgroup = indirect_draw;
576 if (!multi_instances_smaller_than_primgroup && instanced_draw) {
577 uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
578 if (num_prims < cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.primgroup_size)
579 multi_instances_smaller_than_primgroup = true;
580 }
581
582 ia_switch_on_eoi = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.ia_switch_on_eoi;
583 partial_vs_wave = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.partial_vs_wave;
584
585 if (chip_class >= GFX7) {
586 wd_switch_on_eop = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.wd_switch_on_eop;
587
588 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
589 * We don't know that for indirect drawing, so treat it as
590 * always problematic. */
591 if (family == CHIP_HAWAII &&
592 (instanced_draw || indirect_draw))
593 wd_switch_on_eop = true;
594
595 /* Performance recommendation for 4 SE Gfx7-8 parts if
596 * instances are smaller than a primgroup.
597 * Assume indirect draws always use small instances.
598 * This is needed for good VS wave utilization.
599 */
600 if (chip_class <= GFX8 &&
601 info->max_se == 4 &&
602 multi_instances_smaller_than_primgroup)
603 wd_switch_on_eop = true;
604
605 /* Required on GFX7 and later. */
606 if (info->max_se > 2 && !wd_switch_on_eop)
607 ia_switch_on_eoi = true;
608
609 /* Required by Hawaii and, for some special cases, by GFX8. */
610 if (ia_switch_on_eoi &&
611 (family == CHIP_HAWAII ||
612 (chip_class == GFX8 &&
613 /* max primgroup in wave is always 2 - leave this for documentation */
614 (radv_pipeline_has_gs(cmd_buffer->state.pipeline) || max_primgroup_in_wave != 2))))
615 partial_vs_wave = true;
616
617 /* Instancing bug on Bonaire. */
618 if (family == CHIP_BONAIRE && ia_switch_on_eoi &&
619 (instanced_draw || indirect_draw))
620 partial_vs_wave = true;
621
622 /* Hardware requirement when drawing primitives from a stream
623 * output buffer.
624 */
625 if (count_from_stream_output)
626 wd_switch_on_eop = true;
627
628 /* If the WD switch is false, the IA switch must be false too. */
629 assert(wd_switch_on_eop || !ia_switch_on_eop);
630 }
631 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
632 if (chip_class <= GFX8 && ia_switch_on_eoi)
633 partial_es_wave = true;
634
635 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline)) {
636 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
637 * The hw doc says all multi-SE chips are affected, but amdgpu-pro Vulkan
638 * only applies it to Hawaii. Do what amdgpu-pro Vulkan does.
639 */
640 if (family == CHIP_HAWAII && ia_switch_on_eoi) {
641 bool set_vgt_flush = indirect_draw;
642 if (!set_vgt_flush && instanced_draw) {
643 uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count);
644 if (num_prims <= 1)
645 set_vgt_flush = true;
646 }
647 if (set_vgt_flush)
648 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
649 }
650 }
651
652 return cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.base |
653 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
654 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
655 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
656 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
657 S_028AA8_WD_SWITCH_ON_EOP(chip_class >= GFX7 ? wd_switch_on_eop : 0);
658
659 }
660
661 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
662 enum chip_class chip_class,
663 bool is_mec,
664 unsigned event, unsigned event_flags,
665 unsigned data_sel,
666 uint64_t va,
667 uint32_t new_fence,
668 uint64_t gfx9_eop_bug_va)
669 {
670 unsigned op = EVENT_TYPE(event) |
671 EVENT_INDEX(5) |
672 event_flags;
673 unsigned is_gfx8_mec = is_mec && chip_class < GFX9;
674 unsigned sel = EOP_DATA_SEL(data_sel);
675
676 /* Wait for write confirmation before writing data, but don't send
677 * an interrupt. */
678 if (data_sel != EOP_DATA_SEL_DISCARD)
679 sel |= EOP_INT_SEL(EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM);
680
681 if (chip_class >= GFX9 || is_gfx8_mec) {
682 /* A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion
683 * counters) must immediately precede every timestamp event to
684 * prevent a GPU hang on GFX9.
685 */
686 if (chip_class == GFX9 && !is_mec) {
687 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
688 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
689 radeon_emit(cs, gfx9_eop_bug_va);
690 radeon_emit(cs, gfx9_eop_bug_va >> 32);
691 }
692
693 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, is_gfx8_mec ? 5 : 6, false));
694 radeon_emit(cs, op);
695 radeon_emit(cs, sel);
696 radeon_emit(cs, va); /* address lo */
697 radeon_emit(cs, va >> 32); /* address hi */
698 radeon_emit(cs, new_fence); /* immediate data lo */
699 radeon_emit(cs, 0); /* immediate data hi */
700 if (!is_gfx8_mec)
701 radeon_emit(cs, 0); /* unused */
702 } else {
703 if (chip_class == GFX7 ||
704 chip_class == GFX8) {
705 /* Two EOP events are required to make all engines go idle
706 * (and optional cache flushes executed) before the timestamp
707 * is written.
708 */
709 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false));
710 radeon_emit(cs, op);
711 radeon_emit(cs, va);
712 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
713 radeon_emit(cs, 0); /* immediate data */
714 radeon_emit(cs, 0); /* unused */
715 }
716
717 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false));
718 radeon_emit(cs, op);
719 radeon_emit(cs, va);
720 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
721 radeon_emit(cs, new_fence); /* immediate data */
722 radeon_emit(cs, 0); /* unused */
723 }
724 }
725
726 void
727 radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va,
728 uint32_t ref, uint32_t mask)
729 {
730 assert(op == WAIT_REG_MEM_EQUAL ||
731 op == WAIT_REG_MEM_NOT_EQUAL ||
732 op == WAIT_REG_MEM_GREATER_OR_EQUAL);
733
734 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, false));
735 radeon_emit(cs, op | WAIT_REG_MEM_MEM_SPACE(1));
736 radeon_emit(cs, va);
737 radeon_emit(cs, va >> 32);
738 radeon_emit(cs, ref); /* reference value */
739 radeon_emit(cs, mask); /* mask */
740 radeon_emit(cs, 4); /* poll interval */
741 }
742
743 static void
744 si_emit_acquire_mem(struct radeon_cmdbuf *cs,
745 bool is_mec,
746 bool is_gfx9,
747 unsigned cp_coher_cntl)
748 {
749 if (is_mec || is_gfx9) {
750 uint32_t hi_val = is_gfx9 ? 0xffffff : 0xff;
751 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, false) |
752 PKT3_SHADER_TYPE_S(is_mec));
753 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
754 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
755 radeon_emit(cs, hi_val); /* CP_COHER_SIZE_HI */
756 radeon_emit(cs, 0); /* CP_COHER_BASE */
757 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
758 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
759 } else {
760 /* ACQUIRE_MEM is only required on a compute ring. */
761 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, false));
762 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
763 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
764 radeon_emit(cs, 0); /* CP_COHER_BASE */
765 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
766 }
767 }
768
769 void
770 si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
771 enum chip_class chip_class,
772 uint32_t *flush_cnt,
773 uint64_t flush_va,
774 bool is_mec,
775 enum radv_cmd_flush_bits flush_bits,
776 uint64_t gfx9_eop_bug_va)
777 {
778 unsigned cp_coher_cntl = 0;
779 uint32_t flush_cb_db = flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
780 RADV_CMD_FLAG_FLUSH_AND_INV_DB);
781
782 if (flush_bits & RADV_CMD_FLAG_INV_ICACHE)
783 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
784 if (flush_bits & RADV_CMD_FLAG_INV_SMEM_L1)
785 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
786
787 if (chip_class <= GFX8) {
788 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
789 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
790 S_0085F0_CB0_DEST_BASE_ENA(1) |
791 S_0085F0_CB1_DEST_BASE_ENA(1) |
792 S_0085F0_CB2_DEST_BASE_ENA(1) |
793 S_0085F0_CB3_DEST_BASE_ENA(1) |
794 S_0085F0_CB4_DEST_BASE_ENA(1) |
795 S_0085F0_CB5_DEST_BASE_ENA(1) |
796 S_0085F0_CB6_DEST_BASE_ENA(1) |
797 S_0085F0_CB7_DEST_BASE_ENA(1);
798
799 /* Necessary for DCC */
800 if (chip_class >= GFX8) {
801 si_cs_emit_write_event_eop(cs,
802 chip_class,
803 is_mec,
804 V_028A90_FLUSH_AND_INV_CB_DATA_TS,
805 0,
806 EOP_DATA_SEL_DISCARD,
807 0, 0,
808 gfx9_eop_bug_va);
809 }
810 }
811 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
812 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
813 S_0085F0_DB_DEST_BASE_ENA(1);
814 }
815 }
816
817 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) {
818 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
819 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
820 }
821
822 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) {
823 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
824 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
825 }
826
827 if (flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) {
828 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
829 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
830 } else if (flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) {
831 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
832 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
833 }
834
835 if (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) {
836 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
837 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
838 }
839
840 if (chip_class >= GFX9 && flush_cb_db) {
841 unsigned cb_db_event, tc_flags;
842
843 /* Set the CB/DB flush event. */
844 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
845
846 /* These are the only allowed combinations. If you need to
847 * do multiple operations at once, do them separately.
848 * All operations that invalidate L2 also seem to invalidate
849 * metadata. Volatile (VOL) and WC flushes are not listed here.
850 *
851 * TC | TC_WB = writeback & invalidate L2 & L1
852 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
853 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
854 * TC | TC_NC = invalidate L2 for MTYPE == NC
855 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
856 * TCL1 = invalidate L1
857 */
858 tc_flags = EVENT_TC_ACTION_ENA |
859 EVENT_TC_MD_ACTION_ENA;
860
861 /* Ideally flush TC together with CB/DB. */
862 if (flush_bits & RADV_CMD_FLAG_INV_GLOBAL_L2) {
863 /* Writeback and invalidate everything in L2 & L1. */
864 tc_flags = EVENT_TC_ACTION_ENA |
865 EVENT_TC_WB_ACTION_ENA;
866
867
868 /* Clear the flags. */
869 flush_bits &= ~(RADV_CMD_FLAG_INV_GLOBAL_L2 |
870 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 |
871 RADV_CMD_FLAG_INV_VMEM_L1);
872 }
873 assert(flush_cnt);
874 (*flush_cnt)++;
875
876 si_cs_emit_write_event_eop(cs, chip_class, false, cb_db_event, tc_flags,
877 EOP_DATA_SEL_VALUE_32BIT,
878 flush_va, *flush_cnt,
879 gfx9_eop_bug_va);
880 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, flush_va,
881 *flush_cnt, 0xffffffff);
882 }
883
884 /* VGT state sync */
885 if (flush_bits & RADV_CMD_FLAG_VGT_FLUSH) {
886 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
887 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
888 }
889
890 /* VGT streamout state sync */
891 if (flush_bits & RADV_CMD_FLAG_VGT_STREAMOUT_SYNC) {
892 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
893 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
894 }
895
896 /* Make sure ME is idle (it executes most packets) before continuing.
897 * This prevents read-after-write hazards between PFP and ME.
898 */
899 if ((cp_coher_cntl ||
900 (flush_bits & (RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
901 RADV_CMD_FLAG_INV_VMEM_L1 |
902 RADV_CMD_FLAG_INV_GLOBAL_L2 |
903 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2))) &&
904 !is_mec) {
905 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
906 radeon_emit(cs, 0);
907 }
908
909 if ((flush_bits & RADV_CMD_FLAG_INV_GLOBAL_L2) ||
910 (chip_class <= GFX7 && (flush_bits & RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2))) {
911 si_emit_acquire_mem(cs, is_mec, chip_class >= GFX9,
912 cp_coher_cntl |
913 S_0085F0_TC_ACTION_ENA(1) |
914 S_0085F0_TCL1_ACTION_ENA(1) |
915 S_0301F0_TC_WB_ACTION_ENA(chip_class >= GFX8));
916 cp_coher_cntl = 0;
917 } else {
918 if(flush_bits & RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2) {
919 /* WB = write-back
920 * NC = apply to non-coherent MTYPEs
921 * (i.e. MTYPE <= 1, which is what we use everywhere)
922 *
923 * WB doesn't work without NC.
924 */
925 si_emit_acquire_mem(cs, is_mec,
926 chip_class >= GFX9,
927 cp_coher_cntl |
928 S_0301F0_TC_WB_ACTION_ENA(1) |
929 S_0301F0_TC_NC_ACTION_ENA(1));
930 cp_coher_cntl = 0;
931 }
932 if (flush_bits & RADV_CMD_FLAG_INV_VMEM_L1) {
933 si_emit_acquire_mem(cs, is_mec,
934 chip_class >= GFX9,
935 cp_coher_cntl |
936 S_0085F0_TCL1_ACTION_ENA(1));
937 cp_coher_cntl = 0;
938 }
939 }
940
941 /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
942 * Therefore, it should be last. Done in PFP.
943 */
944 if (cp_coher_cntl)
945 si_emit_acquire_mem(cs, is_mec, chip_class >= GFX9, cp_coher_cntl);
946
947 if (flush_bits & RADV_CMD_FLAG_START_PIPELINE_STATS) {
948 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
949 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
950 EVENT_INDEX(0));
951 } else if (flush_bits & RADV_CMD_FLAG_STOP_PIPELINE_STATS) {
952 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
953 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
954 EVENT_INDEX(0));
955 }
956 }
957
958 void
959 si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer)
960 {
961 bool is_compute = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
962
963 if (is_compute)
964 cmd_buffer->state.flush_bits &= ~(RADV_CMD_FLAG_FLUSH_AND_INV_CB |
965 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
966 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
967 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
968 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
969 RADV_CMD_FLAG_VS_PARTIAL_FLUSH |
970 RADV_CMD_FLAG_VGT_FLUSH |
971 RADV_CMD_FLAG_START_PIPELINE_STATS |
972 RADV_CMD_FLAG_STOP_PIPELINE_STATS);
973
974 if (!cmd_buffer->state.flush_bits)
975 return;
976
977 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 128);
978
979 si_cs_emit_cache_flush(cmd_buffer->cs,
980 cmd_buffer->device->physical_device->rad_info.chip_class,
981 &cmd_buffer->gfx9_fence_idx,
982 cmd_buffer->gfx9_fence_va,
983 radv_cmd_buffer_uses_mec(cmd_buffer),
984 cmd_buffer->state.flush_bits,
985 cmd_buffer->gfx9_eop_bug_va);
986
987
988 if (unlikely(cmd_buffer->device->trace_bo))
989 radv_cmd_buffer_trace_emit(cmd_buffer);
990
991 /* Clear the caches that have been flushed to avoid syncing too much
992 * when there is some pending active queries.
993 */
994 cmd_buffer->active_query_flush_bits &= ~cmd_buffer->state.flush_bits;
995
996 cmd_buffer->state.flush_bits = 0;
997
998 /* If the driver used a compute shader for resetting a query pool, it
999 * should be finished at this point.
1000 */
1001 cmd_buffer->pending_reset_query = false;
1002 }
1003
1004 /* sets the CP predication state using a boolean stored at va */
1005 void
1006 si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
1007 bool draw_visible, uint64_t va)
1008 {
1009 uint32_t op = 0;
1010
1011 if (va) {
1012 op = PRED_OP(PREDICATION_OP_BOOL64);
1013
1014 /* PREDICATION_DRAW_VISIBLE means that if the 32-bit value is
1015 * zero, all rendering commands are discarded. Otherwise, they
1016 * are discarded if the value is non zero.
1017 */
1018 op |= draw_visible ? PREDICATION_DRAW_VISIBLE :
1019 PREDICATION_DRAW_NOT_VISIBLE;
1020 }
1021 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1022 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 2, 0));
1023 radeon_emit(cmd_buffer->cs, op);
1024 radeon_emit(cmd_buffer->cs, va);
1025 radeon_emit(cmd_buffer->cs, va >> 32);
1026 } else {
1027 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
1028 radeon_emit(cmd_buffer->cs, va);
1029 radeon_emit(cmd_buffer->cs, op | ((va >> 32) & 0xFF));
1030 }
1031 }
1032
1033 /* Set this if you want the 3D engine to wait until CP DMA is done.
1034 * It should be set on the last CP DMA packet. */
1035 #define CP_DMA_SYNC (1 << 0)
1036
1037 /* Set this if the source data was used as a destination in a previous CP DMA
1038 * packet. It's for preventing a read-after-write (RAW) hazard between two
1039 * CP DMA packets. */
1040 #define CP_DMA_RAW_WAIT (1 << 1)
1041 #define CP_DMA_USE_L2 (1 << 2)
1042 #define CP_DMA_CLEAR (1 << 3)
1043
1044 /* Alignment for optimal performance. */
1045 #define SI_CPDMA_ALIGNMENT 32
1046
1047 /* The max number of bytes that can be copied per packet. */
1048 static inline unsigned cp_dma_max_byte_count(struct radv_cmd_buffer *cmd_buffer)
1049 {
1050 unsigned max = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 ?
1051 S_414_BYTE_COUNT_GFX9(~0u) :
1052 S_414_BYTE_COUNT_GFX6(~0u);
1053
1054 /* make it aligned for optimal performance */
1055 return max & ~(SI_CPDMA_ALIGNMENT - 1);
1056 }
1057
1058 /* Emit a CP DMA packet to do a copy from one buffer to another, or to clear
1059 * a buffer. The size must fit in bits [20:0]. If CP_DMA_CLEAR is set, src_va is a 32-bit
1060 * clear value.
1061 */
1062 static void si_emit_cp_dma(struct radv_cmd_buffer *cmd_buffer,
1063 uint64_t dst_va, uint64_t src_va,
1064 unsigned size, unsigned flags)
1065 {
1066 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1067 uint32_t header = 0, command = 0;
1068
1069 assert(size <= cp_dma_max_byte_count(cmd_buffer));
1070
1071 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9);
1072 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1073 command |= S_414_BYTE_COUNT_GFX9(size);
1074 else
1075 command |= S_414_BYTE_COUNT_GFX6(size);
1076
1077 /* Sync flags. */
1078 if (flags & CP_DMA_SYNC)
1079 header |= S_411_CP_SYNC(1);
1080 else {
1081 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1082 command |= S_414_DISABLE_WR_CONFIRM_GFX9(1);
1083 else
1084 command |= S_414_DISABLE_WR_CONFIRM_GFX6(1);
1085 }
1086
1087 if (flags & CP_DMA_RAW_WAIT)
1088 command |= S_414_RAW_WAIT(1);
1089
1090 /* Src and dst flags. */
1091 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
1092 !(flags & CP_DMA_CLEAR) &&
1093 src_va == dst_va)
1094 header |= S_411_DST_SEL(V_411_NOWHERE); /* prefetch only */
1095 else if (flags & CP_DMA_USE_L2)
1096 header |= S_411_DST_SEL(V_411_DST_ADDR_TC_L2);
1097
1098 if (flags & CP_DMA_CLEAR)
1099 header |= S_411_SRC_SEL(V_411_DATA);
1100 else if (flags & CP_DMA_USE_L2)
1101 header |= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2);
1102
1103 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
1104 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, cmd_buffer->state.predicating));
1105 radeon_emit(cs, header);
1106 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1107 radeon_emit(cs, src_va >> 32); /* SRC_ADDR_HI [31:0] */
1108 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1109 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [31:0] */
1110 radeon_emit(cs, command);
1111 } else {
1112 assert(!(flags & CP_DMA_USE_L2));
1113 header |= S_411_SRC_ADDR_HI(src_va >> 32);
1114 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, cmd_buffer->state.predicating));
1115 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1116 radeon_emit(cs, header); /* SRC_ADDR_HI [15:0] + flags. */
1117 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1118 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
1119 radeon_emit(cs, command);
1120 }
1121
1122 /* CP DMA is executed in ME, but index buffers are read by PFP.
1123 * This ensures that ME (CP DMA) is idle before PFP starts fetching
1124 * indices. If we wanted to execute CP DMA in PFP, this packet
1125 * should precede it.
1126 */
1127 if (flags & CP_DMA_SYNC) {
1128 if (cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
1129 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1130 radeon_emit(cs, 0);
1131 }
1132
1133 /* CP will see the sync flag and wait for all DMAs to complete. */
1134 cmd_buffer->state.dma_is_busy = false;
1135 }
1136
1137 if (unlikely(cmd_buffer->device->trace_bo))
1138 radv_cmd_buffer_trace_emit(cmd_buffer);
1139 }
1140
1141 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1142 unsigned size)
1143 {
1144 uint64_t aligned_va = va & ~(SI_CPDMA_ALIGNMENT - 1);
1145 uint64_t aligned_size = ((va + size + SI_CPDMA_ALIGNMENT -1) & ~(SI_CPDMA_ALIGNMENT - 1)) - aligned_va;
1146
1147 si_emit_cp_dma(cmd_buffer, aligned_va, aligned_va,
1148 aligned_size, CP_DMA_USE_L2);
1149 }
1150
1151 static void si_cp_dma_prepare(struct radv_cmd_buffer *cmd_buffer, uint64_t byte_count,
1152 uint64_t remaining_size, unsigned *flags)
1153 {
1154
1155 /* Flush the caches for the first copy only.
1156 * Also wait for the previous CP DMA operations.
1157 */
1158 if (cmd_buffer->state.flush_bits) {
1159 si_emit_cache_flush(cmd_buffer);
1160 *flags |= CP_DMA_RAW_WAIT;
1161 }
1162
1163 /* Do the synchronization after the last dma, so that all data
1164 * is written to memory.
1165 */
1166 if (byte_count == remaining_size)
1167 *flags |= CP_DMA_SYNC;
1168 }
1169
1170 static void si_cp_dma_realign_engine(struct radv_cmd_buffer *cmd_buffer, unsigned size)
1171 {
1172 uint64_t va;
1173 uint32_t offset;
1174 unsigned dma_flags = 0;
1175 unsigned buf_size = SI_CPDMA_ALIGNMENT * 2;
1176 void *ptr;
1177
1178 assert(size < SI_CPDMA_ALIGNMENT);
1179
1180 radv_cmd_buffer_upload_alloc(cmd_buffer, buf_size, SI_CPDMA_ALIGNMENT, &offset, &ptr);
1181
1182 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1183 va += offset;
1184
1185 si_cp_dma_prepare(cmd_buffer, size, size, &dma_flags);
1186
1187 si_emit_cp_dma(cmd_buffer, va, va + SI_CPDMA_ALIGNMENT, size,
1188 dma_flags);
1189 }
1190
1191 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1192 uint64_t src_va, uint64_t dest_va,
1193 uint64_t size)
1194 {
1195 uint64_t main_src_va, main_dest_va;
1196 uint64_t skipped_size = 0, realign_size = 0;
1197
1198 /* Assume that we are not going to sync after the last DMA operation. */
1199 cmd_buffer->state.dma_is_busy = true;
1200
1201 if (cmd_buffer->device->physical_device->rad_info.family <= CHIP_CARRIZO ||
1202 cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY) {
1203 /* If the size is not aligned, we must add a dummy copy at the end
1204 * just to align the internal counter. Otherwise, the DMA engine
1205 * would slow down by an order of magnitude for following copies.
1206 */
1207 if (size % SI_CPDMA_ALIGNMENT)
1208 realign_size = SI_CPDMA_ALIGNMENT - (size % SI_CPDMA_ALIGNMENT);
1209
1210 /* If the copy begins unaligned, we must start copying from the next
1211 * aligned block and the skipped part should be copied after everything
1212 * else has been copied. Only the src alignment matters, not dst.
1213 */
1214 if (src_va % SI_CPDMA_ALIGNMENT) {
1215 skipped_size = SI_CPDMA_ALIGNMENT - (src_va % SI_CPDMA_ALIGNMENT);
1216 /* The main part will be skipped if the size is too small. */
1217 skipped_size = MIN2(skipped_size, size);
1218 size -= skipped_size;
1219 }
1220 }
1221 main_src_va = src_va + skipped_size;
1222 main_dest_va = dest_va + skipped_size;
1223
1224 while (size) {
1225 unsigned dma_flags = 0;
1226 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1227
1228 si_cp_dma_prepare(cmd_buffer, byte_count,
1229 size + skipped_size + realign_size,
1230 &dma_flags);
1231
1232 dma_flags &= ~CP_DMA_SYNC;
1233
1234 si_emit_cp_dma(cmd_buffer, main_dest_va, main_src_va,
1235 byte_count, dma_flags);
1236
1237 size -= byte_count;
1238 main_src_va += byte_count;
1239 main_dest_va += byte_count;
1240 }
1241
1242 if (skipped_size) {
1243 unsigned dma_flags = 0;
1244
1245 si_cp_dma_prepare(cmd_buffer, skipped_size,
1246 size + skipped_size + realign_size,
1247 &dma_flags);
1248
1249 si_emit_cp_dma(cmd_buffer, dest_va, src_va,
1250 skipped_size, dma_flags);
1251 }
1252 if (realign_size)
1253 si_cp_dma_realign_engine(cmd_buffer, realign_size);
1254 }
1255
1256 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1257 uint64_t size, unsigned value)
1258 {
1259
1260 if (!size)
1261 return;
1262
1263 assert(va % 4 == 0 && size % 4 == 0);
1264
1265 /* Assume that we are not going to sync after the last DMA operation. */
1266 cmd_buffer->state.dma_is_busy = true;
1267
1268 while (size) {
1269 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(cmd_buffer));
1270 unsigned dma_flags = CP_DMA_CLEAR;
1271
1272 si_cp_dma_prepare(cmd_buffer, byte_count, size, &dma_flags);
1273
1274 /* Emit the clear packet. */
1275 si_emit_cp_dma(cmd_buffer, va, value, byte_count,
1276 dma_flags);
1277
1278 size -= byte_count;
1279 va += byte_count;
1280 }
1281 }
1282
1283 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer)
1284 {
1285 if (cmd_buffer->device->physical_device->rad_info.chip_class < GFX7)
1286 return;
1287
1288 if (!cmd_buffer->state.dma_is_busy)
1289 return;
1290
1291 /* Issue a dummy DMA that copies zero bytes.
1292 *
1293 * The DMA engine will see that there's no work to do and skip this
1294 * DMA request, however, the CP will see the sync flag and still wait
1295 * for all DMAs to complete.
1296 */
1297 si_emit_cp_dma(cmd_buffer, 0, 0, 0, CP_DMA_SYNC);
1298
1299 cmd_buffer->state.dma_is_busy = false;
1300 }
1301
1302 /* For MSAA sample positions. */
1303 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1304 ((((unsigned)(s0x) & 0xf) << 0) | (((unsigned)(s0y) & 0xf) << 4) | \
1305 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
1306 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
1307 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
1308
1309 /* For obtaining location coordinates from registers */
1310 #define SEXT4(x) ((int)((x) | ((x) & 0x8 ? 0xfffffff0 : 0)))
1311 #define GET_SFIELD(reg, index) SEXT4(((reg) >> ((index) * 4)) & 0xf)
1312 #define GET_SX(reg, index) GET_SFIELD((reg)[(index) / 4], ((index) % 4) * 2)
1313 #define GET_SY(reg, index) GET_SFIELD((reg)[(index) / 4], ((index) % 4) * 2 + 1)
1314
1315 /* 1x MSAA */
1316 static const uint32_t sample_locs_1x =
1317 FILL_SREG(0, 0, 0, 0, 0, 0, 0, 0);
1318 static const unsigned max_dist_1x = 0;
1319 static const uint64_t centroid_priority_1x = 0x0000000000000000ull;
1320
1321 /* 2xMSAA */
1322 static const uint32_t sample_locs_2x =
1323 FILL_SREG(4,4, -4, -4, 0, 0, 0, 0);
1324 static const unsigned max_dist_2x = 4;
1325 static const uint64_t centroid_priority_2x = 0x1010101010101010ull;
1326
1327 /* 4xMSAA */
1328 static const uint32_t sample_locs_4x =
1329 FILL_SREG(-2,-6, 6, -2, -6, 2, 2, 6);
1330 static const unsigned max_dist_4x = 6;
1331 static const uint64_t centroid_priority_4x = 0x3210321032103210ull;
1332
1333 /* 8xMSAA */
1334 static const uint32_t sample_locs_8x[] = {
1335 FILL_SREG( 1,-3, -1, 3, 5, 1, -3,-5),
1336 FILL_SREG(-5, 5, -7,-1, 3, 7, 7,-7),
1337 /* The following are unused by hardware, but we emit them to IBs
1338 * instead of multiple SET_CONTEXT_REG packets. */
1339 0,
1340 0,
1341 };
1342 static const unsigned max_dist_8x = 7;
1343 static const uint64_t centroid_priority_8x = 0x7654321076543210ull;
1344
1345 unsigned radv_get_default_max_sample_dist(int log_samples)
1346 {
1347 unsigned max_dist[] = {
1348 max_dist_1x,
1349 max_dist_2x,
1350 max_dist_4x,
1351 max_dist_8x,
1352 };
1353 return max_dist[log_samples];
1354 }
1355
1356 void radv_emit_default_sample_locations(struct radeon_cmdbuf *cs, int nr_samples)
1357 {
1358 switch (nr_samples) {
1359 default:
1360 case 1:
1361 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1362 radeon_emit(cs, (uint32_t)centroid_priority_1x);
1363 radeon_emit(cs, centroid_priority_1x >> 32);
1364 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_1x);
1365 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_1x);
1366 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_1x);
1367 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_1x);
1368 break;
1369 case 2:
1370 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1371 radeon_emit(cs, (uint32_t)centroid_priority_2x);
1372 radeon_emit(cs, centroid_priority_2x >> 32);
1373 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x);
1374 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x);
1375 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x);
1376 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x);
1377 break;
1378 case 4:
1379 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1380 radeon_emit(cs, (uint32_t)centroid_priority_4x);
1381 radeon_emit(cs, centroid_priority_4x >> 32);
1382 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x);
1383 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x);
1384 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x);
1385 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x);
1386 break;
1387 case 8:
1388 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1389 radeon_emit(cs, (uint32_t)centroid_priority_8x);
1390 radeon_emit(cs, centroid_priority_8x >> 32);
1391 radeon_set_context_reg_seq(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
1392 radeon_emit_array(cs, sample_locs_8x, 4);
1393 radeon_emit_array(cs, sample_locs_8x, 4);
1394 radeon_emit_array(cs, sample_locs_8x, 4);
1395 radeon_emit_array(cs, sample_locs_8x, 2);
1396 break;
1397 }
1398 }
1399
1400 static void radv_get_sample_position(struct radv_device *device,
1401 unsigned sample_count,
1402 unsigned sample_index, float *out_value)
1403 {
1404 const uint32_t *sample_locs;
1405
1406 switch (sample_count) {
1407 case 1:
1408 default:
1409 sample_locs = &sample_locs_1x;
1410 break;
1411 case 2:
1412 sample_locs = &sample_locs_2x;
1413 break;
1414 case 4:
1415 sample_locs = &sample_locs_4x;
1416 break;
1417 case 8:
1418 sample_locs = sample_locs_8x;
1419 break;
1420 }
1421
1422 out_value[0] = (GET_SX(sample_locs, sample_index) + 8) / 16.0f;
1423 out_value[1] = (GET_SY(sample_locs, sample_index) + 8) / 16.0f;
1424 }
1425
1426 void radv_device_init_msaa(struct radv_device *device)
1427 {
1428 int i;
1429
1430 radv_get_sample_position(device, 1, 0, device->sample_locations_1x[0]);
1431
1432 for (i = 0; i < 2; i++)
1433 radv_get_sample_position(device, 2, i, device->sample_locations_2x[i]);
1434 for (i = 0; i < 4; i++)
1435 radv_get_sample_position(device, 4, i, device->sample_locations_4x[i]);
1436 for (i = 0; i < 8; i++)
1437 radv_get_sample_position(device, 8, i, device->sample_locations_8x[i]);
1438 }