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[mesa.git] / src / amd / vulkan / winsys / amdgpu / radv_amdgpu_cs.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <stdlib.h>
26 #include <amdgpu.h>
27 #include "drm-uapi/amdgpu_drm.h"
28 #include <assert.h>
29 #include <pthread.h>
30 #include <errno.h>
31
32 #include "util/u_memory.h"
33 #include "ac_debug.h"
34 #include "radv_radeon_winsys.h"
35 #include "radv_amdgpu_cs.h"
36 #include "radv_amdgpu_bo.h"
37 #include "sid.h"
38
39
40 enum {
41 VIRTUAL_BUFFER_HASH_TABLE_SIZE = 1024
42 };
43
44 struct radv_amdgpu_cs {
45 struct radeon_cmdbuf base;
46 struct radv_amdgpu_winsys *ws;
47
48 struct amdgpu_cs_ib_info ib;
49
50 struct radeon_winsys_bo *ib_buffer;
51 uint8_t *ib_mapped;
52 unsigned max_num_buffers;
53 unsigned num_buffers;
54 struct drm_amdgpu_bo_list_entry *handles;
55
56 struct radeon_winsys_bo **old_ib_buffers;
57 unsigned num_old_ib_buffers;
58 unsigned max_num_old_ib_buffers;
59 unsigned *ib_size_ptr;
60 VkResult status;
61 bool is_chained;
62
63 int buffer_hash_table[1024];
64 unsigned hw_ip;
65
66 unsigned num_virtual_buffers;
67 unsigned max_num_virtual_buffers;
68 struct radeon_winsys_bo **virtual_buffers;
69 int *virtual_buffer_hash_table;
70
71 /* For chips that don't support chaining. */
72 struct radeon_cmdbuf *old_cs_buffers;
73 unsigned num_old_cs_buffers;
74 };
75
76 static inline struct radv_amdgpu_cs *
77 radv_amdgpu_cs(struct radeon_cmdbuf *base)
78 {
79 return (struct radv_amdgpu_cs*)base;
80 }
81
82 static int ring_to_hw_ip(enum ring_type ring)
83 {
84 switch (ring) {
85 case RING_GFX:
86 return AMDGPU_HW_IP_GFX;
87 case RING_DMA:
88 return AMDGPU_HW_IP_DMA;
89 case RING_COMPUTE:
90 return AMDGPU_HW_IP_COMPUTE;
91 default:
92 unreachable("unsupported ring");
93 }
94 }
95
96 struct radv_amdgpu_cs_request {
97 /** Specify flags with additional information */
98 uint64_t flags;
99
100 /** Specify HW IP block type to which to send the IB. */
101 unsigned ip_type;
102
103 /** IP instance index if there are several IPs of the same type. */
104 unsigned ip_instance;
105
106 /**
107 * Specify ring index of the IP. We could have several rings
108 * in the same IP. E.g. 0 for SDMA0 and 1 for SDMA1.
109 */
110 uint32_t ring;
111
112 /**
113 * BO list handles used by this request.
114 */
115 struct drm_amdgpu_bo_list_entry *handles;
116 uint32_t num_handles;
117
118 /**
119 * Number of dependencies this Command submission needs to
120 * wait for before starting execution.
121 */
122 uint32_t number_of_dependencies;
123
124 /**
125 * Array of dependencies which need to be met before
126 * execution can start.
127 */
128 struct amdgpu_cs_fence *dependencies;
129
130 /** Number of IBs to submit in the field ibs. */
131 uint32_t number_of_ibs;
132
133 /**
134 * IBs to submit. Those IBs will be submit together as single entity
135 */
136 struct amdgpu_cs_ib_info *ibs;
137
138 /**
139 * The returned sequence number for the command submission
140 */
141 uint64_t seq_no;
142
143 /**
144 * The fence information
145 */
146 struct amdgpu_cs_fence_info fence_info;
147 };
148
149
150 static int radv_amdgpu_signal_sems(struct radv_amdgpu_ctx *ctx,
151 uint32_t ip_type,
152 uint32_t ring,
153 struct radv_winsys_sem_info *sem_info);
154 static int radv_amdgpu_cs_submit(struct radv_amdgpu_ctx *ctx,
155 struct radv_amdgpu_cs_request *request,
156 struct radv_winsys_sem_info *sem_info);
157
158 static void radv_amdgpu_request_to_fence(struct radv_amdgpu_ctx *ctx,
159 struct radv_amdgpu_fence *fence,
160 struct radv_amdgpu_cs_request *req)
161 {
162 fence->fence.context = ctx->ctx;
163 fence->fence.ip_type = req->ip_type;
164 fence->fence.ip_instance = req->ip_instance;
165 fence->fence.ring = req->ring;
166 fence->fence.fence = req->seq_no;
167 fence->user_ptr = (volatile uint64_t*)(ctx->fence_map + req->ip_type * MAX_RINGS_PER_TYPE + req->ring);
168 }
169
170 static struct radeon_winsys_fence *radv_amdgpu_create_fence()
171 {
172 struct radv_amdgpu_fence *fence = calloc(1, sizeof(struct radv_amdgpu_fence));
173 if (!fence)
174 return NULL;
175
176 fence->fence.fence = UINT64_MAX;
177 return (struct radeon_winsys_fence*)fence;
178 }
179
180 static void radv_amdgpu_destroy_fence(struct radeon_winsys_fence *_fence)
181 {
182 struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
183 free(fence);
184 }
185
186 static void radv_amdgpu_reset_fence(struct radeon_winsys_fence *_fence)
187 {
188 struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
189 fence->fence.fence = UINT64_MAX;
190 }
191
192 static void radv_amdgpu_signal_fence(struct radeon_winsys_fence *_fence)
193 {
194 struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
195 fence->fence.fence = 0;
196 }
197
198 static bool radv_amdgpu_is_fence_waitable(struct radeon_winsys_fence *_fence)
199 {
200 struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
201 return fence->fence.fence < UINT64_MAX;
202 }
203
204 static bool radv_amdgpu_fence_wait(struct radeon_winsys *_ws,
205 struct radeon_winsys_fence *_fence,
206 bool absolute,
207 uint64_t timeout)
208 {
209 struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
210 unsigned flags = absolute ? AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE : 0;
211 int r;
212 uint32_t expired = 0;
213
214 /* Special casing 0 and UINT64_MAX so that they work without user_ptr/fence.ctx */
215 if (fence->fence.fence == UINT64_MAX)
216 return false;
217
218 if (fence->fence.fence == 0)
219 return true;
220
221 if (fence->user_ptr) {
222 if (*fence->user_ptr >= fence->fence.fence)
223 return true;
224 if (!absolute && !timeout)
225 return false;
226 }
227
228 /* Now use the libdrm query. */
229 r = amdgpu_cs_query_fence_status(&fence->fence,
230 timeout,
231 flags,
232 &expired);
233
234 if (r) {
235 fprintf(stderr, "amdgpu: radv_amdgpu_cs_query_fence_status failed.\n");
236 return false;
237 }
238
239 if (expired)
240 return true;
241
242 return false;
243 }
244
245
246 static bool radv_amdgpu_fences_wait(struct radeon_winsys *_ws,
247 struct radeon_winsys_fence *const *_fences,
248 uint32_t fence_count,
249 bool wait_all,
250 uint64_t timeout)
251 {
252 struct amdgpu_cs_fence *fences = malloc(sizeof(struct amdgpu_cs_fence) * fence_count);
253 int r;
254 uint32_t expired = 0, first = 0;
255
256 if (!fences)
257 return false;
258
259 for (uint32_t i = 0; i < fence_count; ++i)
260 fences[i] = ((struct radv_amdgpu_fence *)_fences[i])->fence;
261
262 /* Now use the libdrm query. */
263 r = amdgpu_cs_wait_fences(fences, fence_count, wait_all,
264 timeout, &expired, &first);
265
266 free(fences);
267 if (r) {
268 fprintf(stderr, "amdgpu: amdgpu_cs_wait_fences failed.\n");
269 return false;
270 }
271
272 if (expired)
273 return true;
274
275 return false;
276 }
277
278 static void radv_amdgpu_cs_destroy(struct radeon_cmdbuf *rcs)
279 {
280 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(rcs);
281
282 if (cs->ib_buffer)
283 cs->ws->base.buffer_destroy(cs->ib_buffer);
284 else
285 free(cs->base.buf);
286
287 for (unsigned i = 0; i < cs->num_old_ib_buffers; ++i)
288 cs->ws->base.buffer_destroy(cs->old_ib_buffers[i]);
289
290 for (unsigned i = 0; i < cs->num_old_cs_buffers; ++i) {
291 struct radeon_cmdbuf *rcs = &cs->old_cs_buffers[i];
292 free(rcs->buf);
293 }
294
295 free(cs->old_cs_buffers);
296 free(cs->old_ib_buffers);
297 free(cs->virtual_buffers);
298 free(cs->virtual_buffer_hash_table);
299 free(cs->handles);
300 free(cs);
301 }
302
303 static void radv_amdgpu_init_cs(struct radv_amdgpu_cs *cs,
304 enum ring_type ring_type)
305 {
306 for (int i = 0; i < ARRAY_SIZE(cs->buffer_hash_table); ++i)
307 cs->buffer_hash_table[i] = -1;
308
309 cs->hw_ip = ring_to_hw_ip(ring_type);
310 }
311
312 static struct radeon_cmdbuf *
313 radv_amdgpu_cs_create(struct radeon_winsys *ws,
314 enum ring_type ring_type)
315 {
316 struct radv_amdgpu_cs *cs;
317 uint32_t ib_size = 20 * 1024 * 4;
318 cs = calloc(1, sizeof(struct radv_amdgpu_cs));
319 if (!cs)
320 return NULL;
321
322 cs->ws = radv_amdgpu_winsys(ws);
323 radv_amdgpu_init_cs(cs, ring_type);
324
325 if (cs->ws->use_ib_bos) {
326 cs->ib_buffer = ws->buffer_create(ws, ib_size, 0,
327 RADEON_DOMAIN_GTT,
328 RADEON_FLAG_CPU_ACCESS |
329 RADEON_FLAG_NO_INTERPROCESS_SHARING |
330 RADEON_FLAG_READ_ONLY |
331 RADEON_FLAG_GTT_WC,
332 RADV_BO_PRIORITY_CS);
333 if (!cs->ib_buffer) {
334 free(cs);
335 return NULL;
336 }
337
338 cs->ib_mapped = ws->buffer_map(cs->ib_buffer);
339 if (!cs->ib_mapped) {
340 ws->buffer_destroy(cs->ib_buffer);
341 free(cs);
342 return NULL;
343 }
344
345 cs->ib.ib_mc_address = radv_amdgpu_winsys_bo(cs->ib_buffer)->base.va;
346 cs->base.buf = (uint32_t *)cs->ib_mapped;
347 cs->base.max_dw = ib_size / 4 - 4;
348 cs->ib_size_ptr = &cs->ib.size;
349 cs->ib.size = 0;
350
351 ws->cs_add_buffer(&cs->base, cs->ib_buffer);
352 } else {
353 uint32_t *buf = malloc(16384);
354 if (!buf) {
355 free(cs);
356 return NULL;
357 }
358 cs->base.buf = buf;
359 cs->base.max_dw = 4096;
360 }
361
362 return &cs->base;
363 }
364
365 static void radv_amdgpu_cs_grow(struct radeon_cmdbuf *_cs, size_t min_size)
366 {
367 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
368
369 if (cs->status != VK_SUCCESS) {
370 cs->base.cdw = 0;
371 return;
372 }
373
374 if (!cs->ws->use_ib_bos) {
375 const uint64_t limit_dws = 0xffff8;
376 uint64_t ib_dws = MAX2(cs->base.cdw + min_size,
377 MIN2(cs->base.max_dw * 2, limit_dws));
378
379 /* The total ib size cannot exceed limit_dws dwords. */
380 if (ib_dws > limit_dws)
381 {
382 /* The maximum size in dwords has been reached,
383 * try to allocate a new one.
384 */
385 struct radeon_cmdbuf *old_cs_buffers =
386 realloc(cs->old_cs_buffers,
387 (cs->num_old_cs_buffers + 1) * sizeof(*cs->old_cs_buffers));
388 if (!old_cs_buffers) {
389 cs->status = VK_ERROR_OUT_OF_HOST_MEMORY;
390 cs->base.cdw = 0;
391 return;
392 }
393 cs->old_cs_buffers = old_cs_buffers;
394
395 /* Store the current one for submitting it later. */
396 cs->old_cs_buffers[cs->num_old_cs_buffers].cdw = cs->base.cdw;
397 cs->old_cs_buffers[cs->num_old_cs_buffers].max_dw = cs->base.max_dw;
398 cs->old_cs_buffers[cs->num_old_cs_buffers].buf = cs->base.buf;
399 cs->num_old_cs_buffers++;
400
401 /* Reset the cs, it will be re-allocated below. */
402 cs->base.cdw = 0;
403 cs->base.buf = NULL;
404
405 /* Re-compute the number of dwords to allocate. */
406 ib_dws = MAX2(cs->base.cdw + min_size,
407 MIN2(cs->base.max_dw * 2, limit_dws));
408 if (ib_dws > limit_dws) {
409 fprintf(stderr, "amdgpu: Too high number of "
410 "dwords to allocate\n");
411 cs->status = VK_ERROR_OUT_OF_HOST_MEMORY;
412 return;
413 }
414 }
415
416 uint32_t *new_buf = realloc(cs->base.buf, ib_dws * 4);
417 if (new_buf) {
418 cs->base.buf = new_buf;
419 cs->base.max_dw = ib_dws;
420 } else {
421 cs->status = VK_ERROR_OUT_OF_HOST_MEMORY;
422 cs->base.cdw = 0;
423 }
424 return;
425 }
426
427 uint64_t ib_size = MAX2(min_size * 4 + 16, cs->base.max_dw * 4 * 2);
428
429 /* max that fits in the chain size field. */
430 ib_size = MIN2(ib_size, 0xfffff);
431
432 while (!cs->base.cdw || (cs->base.cdw & 7) != 4)
433 radeon_emit(&cs->base, PKT3_NOP_PAD);
434
435 *cs->ib_size_ptr |= cs->base.cdw + 4;
436
437 if (cs->num_old_ib_buffers == cs->max_num_old_ib_buffers) {
438 unsigned max_num_old_ib_buffers =
439 MAX2(1, cs->max_num_old_ib_buffers * 2);
440 struct radeon_winsys_bo **old_ib_buffers =
441 realloc(cs->old_ib_buffers,
442 max_num_old_ib_buffers * sizeof(void*));
443 if (!old_ib_buffers) {
444 cs->status = VK_ERROR_OUT_OF_HOST_MEMORY;
445 return;
446 }
447 cs->max_num_old_ib_buffers = max_num_old_ib_buffers;
448 cs->old_ib_buffers = old_ib_buffers;
449 }
450
451 cs->old_ib_buffers[cs->num_old_ib_buffers++] = cs->ib_buffer;
452
453 cs->ib_buffer = cs->ws->base.buffer_create(&cs->ws->base, ib_size, 0,
454 RADEON_DOMAIN_GTT,
455 RADEON_FLAG_CPU_ACCESS |
456 RADEON_FLAG_NO_INTERPROCESS_SHARING |
457 RADEON_FLAG_READ_ONLY |
458 RADEON_FLAG_GTT_WC,
459 RADV_BO_PRIORITY_CS);
460
461 if (!cs->ib_buffer) {
462 cs->base.cdw = 0;
463 cs->status = VK_ERROR_OUT_OF_DEVICE_MEMORY;
464 cs->ib_buffer = cs->old_ib_buffers[--cs->num_old_ib_buffers];
465 }
466
467 cs->ib_mapped = cs->ws->base.buffer_map(cs->ib_buffer);
468 if (!cs->ib_mapped) {
469 cs->ws->base.buffer_destroy(cs->ib_buffer);
470 cs->base.cdw = 0;
471
472 /* VK_ERROR_MEMORY_MAP_FAILED is not valid for vkEndCommandBuffer. */
473 cs->status = VK_ERROR_OUT_OF_DEVICE_MEMORY;
474 cs->ib_buffer = cs->old_ib_buffers[--cs->num_old_ib_buffers];
475 }
476
477 cs->ws->base.cs_add_buffer(&cs->base, cs->ib_buffer);
478
479 radeon_emit(&cs->base, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
480 radeon_emit(&cs->base, radv_amdgpu_winsys_bo(cs->ib_buffer)->base.va);
481 radeon_emit(&cs->base, radv_amdgpu_winsys_bo(cs->ib_buffer)->base.va >> 32);
482 radeon_emit(&cs->base, S_3F2_CHAIN(1) | S_3F2_VALID(1));
483
484 cs->ib_size_ptr = cs->base.buf + cs->base.cdw - 1;
485
486 cs->base.buf = (uint32_t *)cs->ib_mapped;
487 cs->base.cdw = 0;
488 cs->base.max_dw = ib_size / 4 - 4;
489
490 }
491
492 static VkResult radv_amdgpu_cs_finalize(struct radeon_cmdbuf *_cs)
493 {
494 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
495
496 if (cs->ws->use_ib_bos) {
497 while (!cs->base.cdw || (cs->base.cdw & 7) != 0)
498 radeon_emit(&cs->base, PKT3_NOP_PAD);
499
500 *cs->ib_size_ptr |= cs->base.cdw;
501
502 cs->is_chained = false;
503 }
504
505 return cs->status;
506 }
507
508 static void radv_amdgpu_cs_reset(struct radeon_cmdbuf *_cs)
509 {
510 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
511 cs->base.cdw = 0;
512 cs->status = VK_SUCCESS;
513
514 for (unsigned i = 0; i < cs->num_buffers; ++i) {
515 unsigned hash = cs->handles[i].bo_handle &
516 (ARRAY_SIZE(cs->buffer_hash_table) - 1);
517 cs->buffer_hash_table[hash] = -1;
518 }
519
520 for (unsigned i = 0; i < cs->num_virtual_buffers; ++i) {
521 unsigned hash = ((uintptr_t)cs->virtual_buffers[i] >> 6) & (VIRTUAL_BUFFER_HASH_TABLE_SIZE - 1);
522 cs->virtual_buffer_hash_table[hash] = -1;
523 }
524
525 cs->num_buffers = 0;
526 cs->num_virtual_buffers = 0;
527
528 if (cs->ws->use_ib_bos) {
529 cs->ws->base.cs_add_buffer(&cs->base, cs->ib_buffer);
530
531 for (unsigned i = 0; i < cs->num_old_ib_buffers; ++i)
532 cs->ws->base.buffer_destroy(cs->old_ib_buffers[i]);
533
534 cs->num_old_ib_buffers = 0;
535 cs->ib.ib_mc_address = radv_amdgpu_winsys_bo(cs->ib_buffer)->base.va;
536 cs->ib_size_ptr = &cs->ib.size;
537 cs->ib.size = 0;
538 } else {
539 for (unsigned i = 0; i < cs->num_old_cs_buffers; ++i) {
540 struct radeon_cmdbuf *rcs = &cs->old_cs_buffers[i];
541 free(rcs->buf);
542 }
543
544 free(cs->old_cs_buffers);
545 cs->old_cs_buffers = NULL;
546 cs->num_old_cs_buffers = 0;
547 }
548 }
549
550 static int radv_amdgpu_cs_find_buffer(struct radv_amdgpu_cs *cs,
551 uint32_t bo)
552 {
553 unsigned hash = bo & (ARRAY_SIZE(cs->buffer_hash_table) - 1);
554 int index = cs->buffer_hash_table[hash];
555
556 if (index == -1)
557 return -1;
558
559 if (cs->handles[index].bo_handle == bo)
560 return index;
561
562 for (unsigned i = 0; i < cs->num_buffers; ++i) {
563 if (cs->handles[i].bo_handle == bo) {
564 cs->buffer_hash_table[hash] = i;
565 return i;
566 }
567 }
568
569 return -1;
570 }
571
572 static void radv_amdgpu_cs_add_buffer_internal(struct radv_amdgpu_cs *cs,
573 uint32_t bo, uint8_t priority)
574 {
575 unsigned hash;
576 int index = radv_amdgpu_cs_find_buffer(cs, bo);
577
578 if (index != -1 || cs->status != VK_SUCCESS)
579 return;
580
581 if (cs->num_buffers == cs->max_num_buffers) {
582 unsigned new_count = MAX2(1, cs->max_num_buffers * 2);
583 struct drm_amdgpu_bo_list_entry *new_entries =
584 realloc(cs->handles, new_count * sizeof(struct drm_amdgpu_bo_list_entry));
585 if (new_entries) {
586 cs->max_num_buffers = new_count;
587 cs->handles = new_entries;
588 } else {
589 cs->status = VK_ERROR_OUT_OF_HOST_MEMORY;
590 return;
591 }
592 }
593
594 cs->handles[cs->num_buffers].bo_handle = bo;
595 cs->handles[cs->num_buffers].bo_priority = priority;
596
597 hash = bo & (ARRAY_SIZE(cs->buffer_hash_table) - 1);
598 cs->buffer_hash_table[hash] = cs->num_buffers;
599
600 ++cs->num_buffers;
601 }
602
603 static void radv_amdgpu_cs_add_virtual_buffer(struct radeon_cmdbuf *_cs,
604 struct radeon_winsys_bo *bo)
605 {
606 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
607 unsigned hash = ((uintptr_t)bo >> 6) & (VIRTUAL_BUFFER_HASH_TABLE_SIZE - 1);
608
609
610 if (!cs->virtual_buffer_hash_table) {
611 int *virtual_buffer_hash_table =
612 malloc(VIRTUAL_BUFFER_HASH_TABLE_SIZE * sizeof(int));
613 if (!virtual_buffer_hash_table) {
614 cs->status = VK_ERROR_OUT_OF_HOST_MEMORY;
615 return;
616 }
617 cs->virtual_buffer_hash_table = virtual_buffer_hash_table;
618
619 for (int i = 0; i < VIRTUAL_BUFFER_HASH_TABLE_SIZE; ++i)
620 cs->virtual_buffer_hash_table[i] = -1;
621 }
622
623 if (cs->virtual_buffer_hash_table[hash] >= 0) {
624 int idx = cs->virtual_buffer_hash_table[hash];
625 if (cs->virtual_buffers[idx] == bo) {
626 return;
627 }
628 for (unsigned i = 0; i < cs->num_virtual_buffers; ++i) {
629 if (cs->virtual_buffers[i] == bo) {
630 cs->virtual_buffer_hash_table[hash] = i;
631 return;
632 }
633 }
634 }
635
636 if(cs->max_num_virtual_buffers <= cs->num_virtual_buffers) {
637 unsigned max_num_virtual_buffers =
638 MAX2(2, cs->max_num_virtual_buffers * 2);
639 struct radeon_winsys_bo **virtual_buffers =
640 realloc(cs->virtual_buffers,
641 sizeof(struct radv_amdgpu_virtual_virtual_buffer*) * max_num_virtual_buffers);
642 if (!virtual_buffers) {
643 cs->status = VK_ERROR_OUT_OF_HOST_MEMORY;
644 return;
645 }
646 cs->max_num_virtual_buffers = max_num_virtual_buffers;
647 cs->virtual_buffers = virtual_buffers;
648 }
649
650 cs->virtual_buffers[cs->num_virtual_buffers] = bo;
651
652 cs->virtual_buffer_hash_table[hash] = cs->num_virtual_buffers;
653 ++cs->num_virtual_buffers;
654
655 }
656
657 static void radv_amdgpu_cs_add_buffer(struct radeon_cmdbuf *_cs,
658 struct radeon_winsys_bo *_bo)
659 {
660 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
661 struct radv_amdgpu_winsys_bo *bo = radv_amdgpu_winsys_bo(_bo);
662
663 if (bo->is_virtual) {
664 radv_amdgpu_cs_add_virtual_buffer(_cs, _bo);
665 return;
666 }
667
668 if (bo->base.is_local)
669 return;
670
671 radv_amdgpu_cs_add_buffer_internal(cs, bo->bo_handle, bo->priority);
672 }
673
674 static void radv_amdgpu_cs_execute_secondary(struct radeon_cmdbuf *_parent,
675 struct radeon_cmdbuf *_child)
676 {
677 struct radv_amdgpu_cs *parent = radv_amdgpu_cs(_parent);
678 struct radv_amdgpu_cs *child = radv_amdgpu_cs(_child);
679
680 for (unsigned i = 0; i < child->num_buffers; ++i) {
681 radv_amdgpu_cs_add_buffer_internal(parent,
682 child->handles[i].bo_handle,
683 child->handles[i].bo_priority);
684 }
685
686 for (unsigned i = 0; i < child->num_virtual_buffers; ++i) {
687 radv_amdgpu_cs_add_buffer(&parent->base, child->virtual_buffers[i]);
688 }
689
690 if (parent->ws->use_ib_bos) {
691 if (parent->base.cdw + 4 > parent->base.max_dw)
692 radv_amdgpu_cs_grow(&parent->base, 4);
693
694 radeon_emit(&parent->base, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
695 radeon_emit(&parent->base, child->ib.ib_mc_address);
696 radeon_emit(&parent->base, child->ib.ib_mc_address >> 32);
697 radeon_emit(&parent->base, child->ib.size);
698 } else {
699 if (parent->base.cdw + child->base.cdw > parent->base.max_dw)
700 radv_amdgpu_cs_grow(&parent->base, child->base.cdw);
701
702 memcpy(parent->base.buf + parent->base.cdw, child->base.buf, 4 * child->base.cdw);
703 parent->base.cdw += child->base.cdw;
704 }
705 }
706
707 static VkResult
708 radv_amdgpu_get_bo_list(struct radv_amdgpu_winsys *ws,
709 struct radeon_cmdbuf **cs_array,
710 unsigned count,
711 struct radv_amdgpu_winsys_bo **extra_bo_array,
712 unsigned num_extra_bo,
713 struct radeon_cmdbuf *extra_cs,
714 const struct radv_winsys_bo_list *radv_bo_list,
715 unsigned *rnum_handles,
716 struct drm_amdgpu_bo_list_entry **rhandles)
717 {
718 struct drm_amdgpu_bo_list_entry *handles = NULL;
719 unsigned num_handles = 0;
720
721 if (ws->debug_all_bos) {
722 struct radv_amdgpu_winsys_bo *bo;
723
724 pthread_mutex_lock(&ws->global_bo_list_lock);
725
726 handles = malloc(sizeof(handles[0]) * ws->num_buffers);
727 if (!handles) {
728 pthread_mutex_unlock(&ws->global_bo_list_lock);
729 return VK_ERROR_OUT_OF_HOST_MEMORY;
730 }
731
732 LIST_FOR_EACH_ENTRY(bo, &ws->global_bo_list, global_list_item) {
733 assert(num_handles < ws->num_buffers);
734 handles[num_handles].bo_handle = bo->bo_handle;
735 handles[num_handles].bo_priority = bo->priority;
736 num_handles++;
737 }
738
739 pthread_mutex_unlock(&ws->global_bo_list_lock);
740 } else if (count == 1 && !num_extra_bo && !extra_cs && !radv_bo_list &&
741 !radv_amdgpu_cs(cs_array[0])->num_virtual_buffers) {
742 struct radv_amdgpu_cs *cs = (struct radv_amdgpu_cs*)cs_array[0];
743 if (cs->num_buffers == 0)
744 return VK_SUCCESS;
745
746 handles = malloc(sizeof(handles[0]) * cs->num_buffers);
747 if (!handles)
748 return VK_ERROR_OUT_OF_HOST_MEMORY;
749
750 memcpy(handles, cs->handles,
751 sizeof(handles[0]) * cs->num_buffers);
752 num_handles = cs->num_buffers;
753 } else {
754 unsigned total_buffer_count = num_extra_bo;
755 num_handles = num_extra_bo;
756 for (unsigned i = 0; i < count; ++i) {
757 struct radv_amdgpu_cs *cs = (struct radv_amdgpu_cs*)cs_array[i];
758 total_buffer_count += cs->num_buffers;
759 for (unsigned j = 0; j < cs->num_virtual_buffers; ++j)
760 total_buffer_count += radv_amdgpu_winsys_bo(cs->virtual_buffers[j])->bo_count;
761 }
762
763 if (extra_cs) {
764 total_buffer_count += ((struct radv_amdgpu_cs*)extra_cs)->num_buffers;
765 }
766
767 if (radv_bo_list) {
768 total_buffer_count += radv_bo_list->count;
769 }
770
771 if (total_buffer_count == 0)
772 return VK_SUCCESS;
773
774 handles = malloc(sizeof(handles[0]) * total_buffer_count);
775 if (!handles)
776 return VK_ERROR_OUT_OF_HOST_MEMORY;
777
778 for (unsigned i = 0; i < num_extra_bo; i++) {
779 handles[i].bo_handle = extra_bo_array[i]->bo_handle;
780 handles[i].bo_priority = extra_bo_array[i]->priority;
781 }
782
783 for (unsigned i = 0; i < count + !!extra_cs; ++i) {
784 struct radv_amdgpu_cs *cs;
785
786 if (i == count)
787 cs = (struct radv_amdgpu_cs*)extra_cs;
788 else
789 cs = (struct radv_amdgpu_cs*)cs_array[i];
790
791 if (!cs->num_buffers)
792 continue;
793
794 if (num_handles == 0 && !cs->num_virtual_buffers) {
795 memcpy(handles, cs->handles, cs->num_buffers * sizeof(struct drm_amdgpu_bo_list_entry));
796 num_handles = cs->num_buffers;
797 continue;
798 }
799 int unique_bo_so_far = num_handles;
800 for (unsigned j = 0; j < cs->num_buffers; ++j) {
801 bool found = false;
802 for (unsigned k = 0; k < unique_bo_so_far; ++k) {
803 if (handles[k].bo_handle == cs->handles[j].bo_handle) {
804 found = true;
805 break;
806 }
807 }
808 if (!found) {
809 handles[num_handles] = cs->handles[j];
810 ++num_handles;
811 }
812 }
813 for (unsigned j = 0; j < cs->num_virtual_buffers; ++j) {
814 struct radv_amdgpu_winsys_bo *virtual_bo = radv_amdgpu_winsys_bo(cs->virtual_buffers[j]);
815 for(unsigned k = 0; k < virtual_bo->bo_count; ++k) {
816 struct radv_amdgpu_winsys_bo *bo = virtual_bo->bos[k];
817 bool found = false;
818 for (unsigned m = 0; m < num_handles; ++m) {
819 if (handles[m].bo_handle == bo->bo_handle) {
820 found = true;
821 break;
822 }
823 }
824 if (!found) {
825 handles[num_handles].bo_handle = bo->bo_handle;
826 handles[num_handles].bo_priority = bo->priority;
827 ++num_handles;
828 }
829 }
830 }
831 }
832
833 if (radv_bo_list) {
834 unsigned unique_bo_so_far = num_handles;
835 for (unsigned i = 0; i < radv_bo_list->count; ++i) {
836 struct radv_amdgpu_winsys_bo *bo = radv_amdgpu_winsys_bo(radv_bo_list->bos[i]);
837 bool found = false;
838 for (unsigned j = 0; j < unique_bo_so_far; ++j) {
839 if (bo->bo_handle == handles[j].bo_handle) {
840 found = true;
841 break;
842 }
843 }
844 if (!found) {
845 handles[num_handles].bo_handle = bo->bo_handle;
846 handles[num_handles].bo_priority = bo->priority;
847 ++num_handles;
848 }
849 }
850 }
851 }
852
853 *rhandles = handles;
854 *rnum_handles = num_handles;
855
856 return VK_SUCCESS;
857 }
858
859 static struct amdgpu_cs_fence_info radv_set_cs_fence(struct radv_amdgpu_ctx *ctx, int ip_type, int ring)
860 {
861 struct amdgpu_cs_fence_info ret = {0};
862 if (ctx->fence_map) {
863 ret.handle = radv_amdgpu_winsys_bo(ctx->fence_bo)->bo;
864 ret.offset = (ip_type * MAX_RINGS_PER_TYPE + ring) * sizeof(uint64_t);
865 }
866 return ret;
867 }
868
869 static void radv_assign_last_submit(struct radv_amdgpu_ctx *ctx,
870 struct radv_amdgpu_cs_request *request)
871 {
872 radv_amdgpu_request_to_fence(ctx,
873 &ctx->last_submission[request->ip_type][request->ring],
874 request);
875 }
876
877 static VkResult
878 radv_amdgpu_winsys_cs_submit_chained(struct radeon_winsys_ctx *_ctx,
879 int queue_idx,
880 struct radv_winsys_sem_info *sem_info,
881 const struct radv_winsys_bo_list *radv_bo_list,
882 struct radeon_cmdbuf **cs_array,
883 unsigned cs_count,
884 struct radeon_cmdbuf *initial_preamble_cs,
885 struct radeon_cmdbuf *continue_preamble_cs,
886 struct radeon_winsys_fence *_fence)
887 {
888 struct radv_amdgpu_ctx *ctx = radv_amdgpu_ctx(_ctx);
889 struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
890 struct radv_amdgpu_cs *cs0 = radv_amdgpu_cs(cs_array[0]);
891 struct drm_amdgpu_bo_list_entry *handles = NULL;
892 struct radv_amdgpu_cs_request request = {0};
893 struct amdgpu_cs_ib_info ibs[2];
894 unsigned number_of_ibs = 1;
895 unsigned num_handles = 0;
896 VkResult result;
897
898 for (unsigned i = cs_count; i--;) {
899 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[i]);
900
901 if (cs->is_chained) {
902 *cs->ib_size_ptr -= 4;
903 cs->is_chained = false;
904 }
905
906 if (i + 1 < cs_count) {
907 struct radv_amdgpu_cs *next = radv_amdgpu_cs(cs_array[i + 1]);
908 assert(cs->base.cdw + 4 <= cs->base.max_dw);
909
910 cs->is_chained = true;
911 *cs->ib_size_ptr += 4;
912
913 cs->base.buf[cs->base.cdw + 0] = PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0);
914 cs->base.buf[cs->base.cdw + 1] = next->ib.ib_mc_address;
915 cs->base.buf[cs->base.cdw + 2] = next->ib.ib_mc_address >> 32;
916 cs->base.buf[cs->base.cdw + 3] = S_3F2_CHAIN(1) | S_3F2_VALID(1) | next->ib.size;
917 }
918 }
919
920 /* Get the BO list. */
921 result = radv_amdgpu_get_bo_list(cs0->ws, cs_array, cs_count, NULL, 0,
922 initial_preamble_cs, radv_bo_list,
923 &num_handles, &handles);
924 if (result != VK_SUCCESS)
925 return result;
926
927 /* Configure the CS request. */
928 if (initial_preamble_cs) {
929 ibs[0] = radv_amdgpu_cs(initial_preamble_cs)->ib;
930 ibs[1] = cs0->ib;
931 number_of_ibs++;
932 } else {
933 ibs[0] = cs0->ib;
934 }
935
936 request.ip_type = cs0->hw_ip;
937 request.ring = queue_idx;
938 request.number_of_ibs = number_of_ibs;
939 request.ibs = ibs;
940 request.handles = handles;
941 request.num_handles = num_handles;
942 request.fence_info = radv_set_cs_fence(ctx, cs0->hw_ip, queue_idx);
943
944 /* Submit the CS. */
945 result = radv_amdgpu_cs_submit(ctx, &request, sem_info);
946
947 free(request.handles);
948
949 if (result != VK_SUCCESS)
950 return result;
951
952 if (fence)
953 radv_amdgpu_request_to_fence(ctx, fence, &request);
954
955 radv_assign_last_submit(ctx, &request);
956
957 return VK_SUCCESS;
958 }
959
960 static VkResult
961 radv_amdgpu_winsys_cs_submit_fallback(struct radeon_winsys_ctx *_ctx,
962 int queue_idx,
963 struct radv_winsys_sem_info *sem_info,
964 const struct radv_winsys_bo_list *radv_bo_list,
965 struct radeon_cmdbuf **cs_array,
966 unsigned cs_count,
967 struct radeon_cmdbuf *initial_preamble_cs,
968 struct radeon_cmdbuf *continue_preamble_cs,
969 struct radeon_winsys_fence *_fence)
970 {
971 struct radv_amdgpu_ctx *ctx = radv_amdgpu_ctx(_ctx);
972 struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
973 struct drm_amdgpu_bo_list_entry *handles = NULL;
974 struct radv_amdgpu_cs_request request = {};
975 struct amdgpu_cs_ib_info *ibs;
976 struct radv_amdgpu_cs *cs0;
977 unsigned num_handles = 0;
978 unsigned number_of_ibs;
979 VkResult result;
980
981 assert(cs_count);
982 cs0 = radv_amdgpu_cs(cs_array[0]);
983
984 /* Compute the number of IBs for this submit. */
985 number_of_ibs = cs_count + !!initial_preamble_cs;
986
987 /* Get the BO list. */
988 result = radv_amdgpu_get_bo_list(cs0->ws, &cs_array[0], cs_count, NULL, 0,
989 initial_preamble_cs, radv_bo_list,
990 &num_handles, &handles);
991 if (result != VK_SUCCESS)
992 return result;
993
994 ibs = malloc(number_of_ibs * sizeof(*ibs));
995 if (!ibs) {
996 free(request.handles);
997 return VK_ERROR_OUT_OF_HOST_MEMORY;
998 }
999
1000 /* Configure the CS request. */
1001 if (initial_preamble_cs)
1002 ibs[0] = radv_amdgpu_cs(initial_preamble_cs)->ib;
1003
1004 for (unsigned i = 0; i < cs_count; i++) {
1005 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[i]);
1006
1007 ibs[i + !!initial_preamble_cs] = cs->ib;
1008
1009 if (cs->is_chained) {
1010 *cs->ib_size_ptr -= 4;
1011 cs->is_chained = false;
1012 }
1013 }
1014
1015 request.ip_type = cs0->hw_ip;
1016 request.ring = queue_idx;
1017 request.handles = handles;
1018 request.num_handles = num_handles;
1019 request.number_of_ibs = number_of_ibs;
1020 request.ibs = ibs;
1021 request.fence_info = radv_set_cs_fence(ctx, cs0->hw_ip, queue_idx);
1022
1023 /* Submit the CS. */
1024 result = radv_amdgpu_cs_submit(ctx, &request, sem_info);
1025
1026 free(request.handles);
1027 free(ibs);
1028
1029 if (result != VK_SUCCESS)
1030 return result;
1031
1032 if (fence)
1033 radv_amdgpu_request_to_fence(ctx, fence, &request);
1034
1035 radv_assign_last_submit(ctx, &request);
1036
1037 return VK_SUCCESS;
1038 }
1039
1040 static VkResult
1041 radv_amdgpu_winsys_cs_submit_sysmem(struct radeon_winsys_ctx *_ctx,
1042 int queue_idx,
1043 struct radv_winsys_sem_info *sem_info,
1044 const struct radv_winsys_bo_list *radv_bo_list,
1045 struct radeon_cmdbuf **cs_array,
1046 unsigned cs_count,
1047 struct radeon_cmdbuf *initial_preamble_cs,
1048 struct radeon_cmdbuf *continue_preamble_cs,
1049 struct radeon_winsys_fence *_fence)
1050 {
1051 struct radv_amdgpu_ctx *ctx = radv_amdgpu_ctx(_ctx);
1052 struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
1053 struct radv_amdgpu_cs *cs0 = radv_amdgpu_cs(cs_array[0]);
1054 struct radeon_winsys *ws = (struct radeon_winsys*)cs0->ws;
1055 struct radv_amdgpu_cs_request request;
1056 uint32_t pad_word = PKT3_NOP_PAD;
1057 bool emit_signal_sem = sem_info->cs_emit_signal;
1058 VkResult result;
1059
1060 if (radv_amdgpu_winsys(ws)->info.chip_class == GFX6)
1061 pad_word = 0x80000000;
1062
1063 assert(cs_count);
1064
1065 for (unsigned i = 0; i < cs_count;) {
1066 struct amdgpu_cs_ib_info *ibs;
1067 struct radeon_winsys_bo **bos;
1068 struct radeon_cmdbuf *preamble_cs = i ? continue_preamble_cs : initial_preamble_cs;
1069 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[i]);
1070 struct drm_amdgpu_bo_list_entry *handles = NULL;
1071 unsigned num_handles = 0;
1072 unsigned number_of_ibs;
1073 uint32_t *ptr;
1074 unsigned cnt = 0;
1075 unsigned size = 0;
1076 unsigned pad_words = 0;
1077
1078 /* Compute the number of IBs for this submit. */
1079 number_of_ibs = cs->num_old_cs_buffers + 1;
1080
1081 ibs = malloc(number_of_ibs * sizeof(*ibs));
1082 if (!ibs)
1083 return VK_ERROR_OUT_OF_HOST_MEMORY;
1084
1085 bos = malloc(number_of_ibs * sizeof(*bos));
1086 if (!bos) {
1087 free(ibs);
1088 return VK_ERROR_OUT_OF_HOST_MEMORY;
1089 }
1090
1091 if (number_of_ibs > 1) {
1092 /* Special path when the maximum size in dwords has
1093 * been reached because we need to handle more than one
1094 * IB per submit.
1095 */
1096 struct radeon_cmdbuf **new_cs_array;
1097 unsigned idx = 0;
1098
1099 new_cs_array = malloc(cs->num_old_cs_buffers *
1100 sizeof(*new_cs_array));
1101 assert(new_cs_array);
1102
1103 for (unsigned j = 0; j < cs->num_old_cs_buffers; j++)
1104 new_cs_array[idx++] = &cs->old_cs_buffers[j];
1105 new_cs_array[idx++] = cs_array[i];
1106
1107 for (unsigned j = 0; j < number_of_ibs; j++) {
1108 struct radeon_cmdbuf *rcs = new_cs_array[j];
1109 bool needs_preamble = preamble_cs && j == 0;
1110 unsigned size = 0;
1111
1112 if (needs_preamble)
1113 size += preamble_cs->cdw;
1114 size += rcs->cdw;
1115
1116 assert(size < 0xffff8);
1117
1118 while (!size || (size & 7)) {
1119 size++;
1120 pad_words++;
1121 }
1122
1123 bos[j] = ws->buffer_create(ws, 4 * size, 4096,
1124 RADEON_DOMAIN_GTT,
1125 RADEON_FLAG_CPU_ACCESS |
1126 RADEON_FLAG_NO_INTERPROCESS_SHARING |
1127 RADEON_FLAG_READ_ONLY,
1128 RADV_BO_PRIORITY_CS);
1129 ptr = ws->buffer_map(bos[j]);
1130
1131 if (needs_preamble) {
1132 memcpy(ptr, preamble_cs->buf, preamble_cs->cdw * 4);
1133 ptr += preamble_cs->cdw;
1134 }
1135
1136 memcpy(ptr, rcs->buf, 4 * rcs->cdw);
1137 ptr += rcs->cdw;
1138
1139 for (unsigned k = 0; k < pad_words; ++k)
1140 *ptr++ = pad_word;
1141
1142 ibs[j].size = size;
1143 ibs[j].ib_mc_address = radv_buffer_get_va(bos[j]);
1144 ibs[j].flags = 0;
1145 }
1146
1147 cnt++;
1148 free(new_cs_array);
1149 } else {
1150 if (preamble_cs)
1151 size += preamble_cs->cdw;
1152
1153 while (i + cnt < cs_count && 0xffff8 - size >= radv_amdgpu_cs(cs_array[i + cnt])->base.cdw) {
1154 size += radv_amdgpu_cs(cs_array[i + cnt])->base.cdw;
1155 ++cnt;
1156 }
1157
1158 while (!size || (size & 7)) {
1159 size++;
1160 pad_words++;
1161 }
1162 assert(cnt);
1163
1164 bos[0] = ws->buffer_create(ws, 4 * size, 4096,
1165 RADEON_DOMAIN_GTT,
1166 RADEON_FLAG_CPU_ACCESS |
1167 RADEON_FLAG_NO_INTERPROCESS_SHARING |
1168 RADEON_FLAG_READ_ONLY,
1169 RADV_BO_PRIORITY_CS);
1170 ptr = ws->buffer_map(bos[0]);
1171
1172 if (preamble_cs) {
1173 memcpy(ptr, preamble_cs->buf, preamble_cs->cdw * 4);
1174 ptr += preamble_cs->cdw;
1175 }
1176
1177 for (unsigned j = 0; j < cnt; ++j) {
1178 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[i + j]);
1179 memcpy(ptr, cs->base.buf, 4 * cs->base.cdw);
1180 ptr += cs->base.cdw;
1181
1182 }
1183
1184 for (unsigned j = 0; j < pad_words; ++j)
1185 *ptr++ = pad_word;
1186
1187 ibs[0].size = size;
1188 ibs[0].ib_mc_address = radv_buffer_get_va(bos[0]);
1189 ibs[0].flags = 0;
1190 }
1191
1192 result = radv_amdgpu_get_bo_list(cs0->ws, &cs_array[i], cnt,
1193 (struct radv_amdgpu_winsys_bo **)bos,
1194 number_of_ibs, preamble_cs,
1195 radv_bo_list,
1196 &num_handles, &handles);
1197 if (result != VK_SUCCESS) {
1198 free(ibs);
1199 free(bos);
1200 return result;
1201 }
1202
1203 memset(&request, 0, sizeof(request));
1204
1205 request.ip_type = cs0->hw_ip;
1206 request.ring = queue_idx;
1207 request.handles = handles;
1208 request.num_handles = num_handles;
1209 request.number_of_ibs = number_of_ibs;
1210 request.ibs = ibs;
1211 request.fence_info = radv_set_cs_fence(ctx, cs0->hw_ip, queue_idx);
1212
1213 sem_info->cs_emit_signal = (i == cs_count - cnt) ? emit_signal_sem : false;
1214 result = radv_amdgpu_cs_submit(ctx, &request, sem_info);
1215
1216 free(request.handles);
1217
1218 for (unsigned j = 0; j < number_of_ibs; j++) {
1219 ws->buffer_destroy(bos[j]);
1220 }
1221
1222 free(ibs);
1223 free(bos);
1224
1225 if (result != VK_SUCCESS)
1226 return result;
1227
1228 i += cnt;
1229 }
1230 if (fence)
1231 radv_amdgpu_request_to_fence(ctx, fence, &request);
1232
1233 radv_assign_last_submit(ctx, &request);
1234
1235 return VK_SUCCESS;
1236 }
1237
1238 static VkResult radv_amdgpu_winsys_cs_submit(struct radeon_winsys_ctx *_ctx,
1239 int queue_idx,
1240 struct radeon_cmdbuf **cs_array,
1241 unsigned cs_count,
1242 struct radeon_cmdbuf *initial_preamble_cs,
1243 struct radeon_cmdbuf *continue_preamble_cs,
1244 struct radv_winsys_sem_info *sem_info,
1245 const struct radv_winsys_bo_list *bo_list,
1246 bool can_patch,
1247 struct radeon_winsys_fence *_fence)
1248 {
1249 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[0]);
1250 struct radv_amdgpu_ctx *ctx = radv_amdgpu_ctx(_ctx);
1251 VkResult result;
1252
1253 assert(sem_info);
1254 if (!cs->ws->use_ib_bos) {
1255 result = radv_amdgpu_winsys_cs_submit_sysmem(_ctx, queue_idx, sem_info, bo_list, cs_array,
1256 cs_count, initial_preamble_cs, continue_preamble_cs, _fence);
1257 } else if (can_patch) {
1258 result = radv_amdgpu_winsys_cs_submit_chained(_ctx, queue_idx, sem_info, bo_list, cs_array,
1259 cs_count, initial_preamble_cs, continue_preamble_cs, _fence);
1260 } else {
1261 result = radv_amdgpu_winsys_cs_submit_fallback(_ctx, queue_idx, sem_info, bo_list, cs_array,
1262 cs_count, initial_preamble_cs, continue_preamble_cs, _fence);
1263 }
1264
1265 radv_amdgpu_signal_sems(ctx, cs->hw_ip, queue_idx, sem_info);
1266 return result;
1267 }
1268
1269 static void *radv_amdgpu_winsys_get_cpu_addr(void *_cs, uint64_t addr)
1270 {
1271 struct radv_amdgpu_cs *cs = (struct radv_amdgpu_cs *)_cs;
1272 void *ret = NULL;
1273
1274 if (!cs->ib_buffer)
1275 return NULL;
1276 for (unsigned i = 0; i <= cs->num_old_ib_buffers; ++i) {
1277 struct radv_amdgpu_winsys_bo *bo;
1278
1279 bo = (struct radv_amdgpu_winsys_bo*)
1280 (i == cs->num_old_ib_buffers ? cs->ib_buffer : cs->old_ib_buffers[i]);
1281 if (addr >= bo->base.va && addr - bo->base.va < bo->size) {
1282 if (amdgpu_bo_cpu_map(bo->bo, &ret) == 0)
1283 return (char *)ret + (addr - bo->base.va);
1284 }
1285 }
1286 if(cs->ws->debug_all_bos) {
1287 pthread_mutex_lock(&cs->ws->global_bo_list_lock);
1288 list_for_each_entry(struct radv_amdgpu_winsys_bo, bo,
1289 &cs->ws->global_bo_list, global_list_item) {
1290 if (addr >= bo->base.va && addr - bo->base.va < bo->size) {
1291 if (amdgpu_bo_cpu_map(bo->bo, &ret) == 0) {
1292 pthread_mutex_unlock(&cs->ws->global_bo_list_lock);
1293 return (char *)ret + (addr - bo->base.va);
1294 }
1295 }
1296 }
1297 pthread_mutex_unlock(&cs->ws->global_bo_list_lock);
1298 }
1299 return ret;
1300 }
1301
1302 static void radv_amdgpu_winsys_cs_dump(struct radeon_cmdbuf *_cs,
1303 FILE* file,
1304 const int *trace_ids, int trace_id_count)
1305 {
1306 struct radv_amdgpu_cs *cs = (struct radv_amdgpu_cs *)_cs;
1307 void *ib = cs->base.buf;
1308 int num_dw = cs->base.cdw;
1309
1310 if (cs->ws->use_ib_bos) {
1311 ib = radv_amdgpu_winsys_get_cpu_addr(cs, cs->ib.ib_mc_address);
1312 num_dw = cs->ib.size;
1313 }
1314 assert(ib);
1315 ac_parse_ib(file, ib, num_dw, trace_ids, trace_id_count, "main IB",
1316 cs->ws->info.chip_class, radv_amdgpu_winsys_get_cpu_addr, cs);
1317 }
1318
1319 static uint32_t radv_to_amdgpu_priority(enum radeon_ctx_priority radv_priority)
1320 {
1321 switch (radv_priority) {
1322 case RADEON_CTX_PRIORITY_REALTIME:
1323 return AMDGPU_CTX_PRIORITY_VERY_HIGH;
1324 case RADEON_CTX_PRIORITY_HIGH:
1325 return AMDGPU_CTX_PRIORITY_HIGH;
1326 case RADEON_CTX_PRIORITY_MEDIUM:
1327 return AMDGPU_CTX_PRIORITY_NORMAL;
1328 case RADEON_CTX_PRIORITY_LOW:
1329 return AMDGPU_CTX_PRIORITY_LOW;
1330 default:
1331 unreachable("Invalid context priority");
1332 }
1333 }
1334
1335 static VkResult radv_amdgpu_ctx_create(struct radeon_winsys *_ws,
1336 enum radeon_ctx_priority priority,
1337 struct radeon_winsys_ctx **rctx)
1338 {
1339 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1340 struct radv_amdgpu_ctx *ctx = CALLOC_STRUCT(radv_amdgpu_ctx);
1341 uint32_t amdgpu_priority = radv_to_amdgpu_priority(priority);
1342 VkResult result;
1343 int r;
1344
1345 if (!ctx)
1346 return VK_ERROR_OUT_OF_HOST_MEMORY;
1347
1348 r = amdgpu_cs_ctx_create2(ws->dev, amdgpu_priority, &ctx->ctx);
1349 if (r && r == -EACCES) {
1350 result = VK_ERROR_NOT_PERMITTED_EXT;
1351 goto fail_create;
1352 } else if (r) {
1353 fprintf(stderr, "amdgpu: radv_amdgpu_cs_ctx_create2 failed. (%i)\n", r);
1354 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1355 goto fail_create;
1356 }
1357 ctx->ws = ws;
1358
1359 assert(AMDGPU_HW_IP_NUM * MAX_RINGS_PER_TYPE * sizeof(uint64_t) <= 4096);
1360 ctx->fence_bo = ws->base.buffer_create(&ws->base, 4096, 8,
1361 RADEON_DOMAIN_GTT,
1362 RADEON_FLAG_CPU_ACCESS |
1363 RADEON_FLAG_NO_INTERPROCESS_SHARING,
1364 RADV_BO_PRIORITY_CS);
1365 if (!ctx->fence_bo) {
1366 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
1367 goto fail_alloc;
1368 }
1369
1370 ctx->fence_map = (uint64_t *)ws->base.buffer_map(ctx->fence_bo);
1371 if (!ctx->fence_map) {
1372 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
1373 goto fail_map;
1374 }
1375
1376 memset(ctx->fence_map, 0, 4096);
1377
1378 *rctx = (struct radeon_winsys_ctx *)ctx;
1379 return VK_SUCCESS;
1380
1381 fail_map:
1382 ws->base.buffer_destroy(ctx->fence_bo);
1383 fail_alloc:
1384 amdgpu_cs_ctx_free(ctx->ctx);
1385 fail_create:
1386 FREE(ctx);
1387 return result;
1388 }
1389
1390 static void radv_amdgpu_ctx_destroy(struct radeon_winsys_ctx *rwctx)
1391 {
1392 struct radv_amdgpu_ctx *ctx = (struct radv_amdgpu_ctx *)rwctx;
1393 ctx->ws->base.buffer_destroy(ctx->fence_bo);
1394 amdgpu_cs_ctx_free(ctx->ctx);
1395 FREE(ctx);
1396 }
1397
1398 static bool radv_amdgpu_ctx_wait_idle(struct radeon_winsys_ctx *rwctx,
1399 enum ring_type ring_type, int ring_index)
1400 {
1401 struct radv_amdgpu_ctx *ctx = (struct radv_amdgpu_ctx *)rwctx;
1402 int ip_type = ring_to_hw_ip(ring_type);
1403
1404 if (ctx->last_submission[ip_type][ring_index].fence.fence) {
1405 uint32_t expired;
1406 int ret = amdgpu_cs_query_fence_status(&ctx->last_submission[ip_type][ring_index].fence,
1407 1000000000ull, 0, &expired);
1408
1409 if (ret || !expired)
1410 return false;
1411 }
1412
1413 return true;
1414 }
1415
1416 static struct radeon_winsys_sem *radv_amdgpu_create_sem(struct radeon_winsys *_ws)
1417 {
1418 struct amdgpu_cs_fence *sem = CALLOC_STRUCT(amdgpu_cs_fence);
1419 if (!sem)
1420 return NULL;
1421
1422 return (struct radeon_winsys_sem *)sem;
1423 }
1424
1425 static void radv_amdgpu_destroy_sem(struct radeon_winsys_sem *_sem)
1426 {
1427 struct amdgpu_cs_fence *sem = (struct amdgpu_cs_fence *)_sem;
1428 FREE(sem);
1429 }
1430
1431 static int radv_amdgpu_signal_sems(struct radv_amdgpu_ctx *ctx,
1432 uint32_t ip_type,
1433 uint32_t ring,
1434 struct radv_winsys_sem_info *sem_info)
1435 {
1436 for (unsigned i = 0; i < sem_info->signal.sem_count; i++) {
1437 struct amdgpu_cs_fence *sem = (struct amdgpu_cs_fence *)(sem_info->signal.sem)[i];
1438
1439 if (sem->context)
1440 return -EINVAL;
1441
1442 *sem = ctx->last_submission[ip_type][ring].fence;
1443 }
1444 return 0;
1445 }
1446
1447 static struct drm_amdgpu_cs_chunk_sem *radv_amdgpu_cs_alloc_syncobj_chunk(struct radv_winsys_sem_counts *counts,
1448 struct drm_amdgpu_cs_chunk *chunk, int chunk_id)
1449 {
1450 struct drm_amdgpu_cs_chunk_sem *syncobj = malloc(sizeof(struct drm_amdgpu_cs_chunk_sem) * counts->syncobj_count);
1451 if (!syncobj)
1452 return NULL;
1453
1454 for (unsigned i = 0; i < counts->syncobj_count; i++) {
1455 struct drm_amdgpu_cs_chunk_sem *sem = &syncobj[i];
1456 sem->handle = counts->syncobj[i];
1457 }
1458
1459 chunk->chunk_id = chunk_id;
1460 chunk->length_dw = sizeof(struct drm_amdgpu_cs_chunk_sem) / 4 * counts->syncobj_count;
1461 chunk->chunk_data = (uint64_t)(uintptr_t)syncobj;
1462 return syncobj;
1463 }
1464
1465 static VkResult
1466 radv_amdgpu_cs_submit(struct radv_amdgpu_ctx *ctx,
1467 struct radv_amdgpu_cs_request *request,
1468 struct radv_winsys_sem_info *sem_info)
1469 {
1470 int r;
1471 int num_chunks;
1472 int size;
1473 bool user_fence;
1474 struct drm_amdgpu_cs_chunk *chunks;
1475 struct drm_amdgpu_cs_chunk_data *chunk_data;
1476 struct drm_amdgpu_cs_chunk_dep *sem_dependencies = NULL;
1477 struct drm_amdgpu_cs_chunk_sem *wait_syncobj = NULL, *signal_syncobj = NULL;
1478 bool use_bo_list_create = ctx->ws->info.drm_minor < 27;
1479 struct drm_amdgpu_bo_list_in bo_list_in;
1480 int i;
1481 struct amdgpu_cs_fence *sem;
1482 uint32_t bo_list = 0;
1483 VkResult result = VK_SUCCESS;
1484
1485 user_fence = (request->fence_info.handle != NULL);
1486 size = request->number_of_ibs + (user_fence ? 2 : 1) + (!use_bo_list_create ? 1 : 0) + 3;
1487
1488 chunks = malloc(sizeof(chunks[0]) * size);
1489 if (!chunks)
1490 return VK_ERROR_OUT_OF_HOST_MEMORY;
1491
1492 size = request->number_of_ibs + (user_fence ? 1 : 0);
1493
1494 chunk_data = malloc(sizeof(chunk_data[0]) * size);
1495 if (!chunk_data) {
1496 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1497 goto error_out;
1498 }
1499
1500 num_chunks = request->number_of_ibs;
1501 for (i = 0; i < request->number_of_ibs; i++) {
1502 struct amdgpu_cs_ib_info *ib;
1503 chunks[i].chunk_id = AMDGPU_CHUNK_ID_IB;
1504 chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
1505 chunks[i].chunk_data = (uint64_t)(uintptr_t)&chunk_data[i];
1506
1507 ib = &request->ibs[i];
1508
1509 chunk_data[i].ib_data._pad = 0;
1510 chunk_data[i].ib_data.va_start = ib->ib_mc_address;
1511 chunk_data[i].ib_data.ib_bytes = ib->size * 4;
1512 chunk_data[i].ib_data.ip_type = request->ip_type;
1513 chunk_data[i].ib_data.ip_instance = request->ip_instance;
1514 chunk_data[i].ib_data.ring = request->ring;
1515 chunk_data[i].ib_data.flags = ib->flags;
1516 }
1517
1518 if (user_fence) {
1519 i = num_chunks++;
1520
1521 chunks[i].chunk_id = AMDGPU_CHUNK_ID_FENCE;
1522 chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_fence) / 4;
1523 chunks[i].chunk_data = (uint64_t)(uintptr_t)&chunk_data[i];
1524
1525 amdgpu_cs_chunk_fence_info_to_data(&request->fence_info,
1526 &chunk_data[i]);
1527 }
1528
1529 if (sem_info->wait.syncobj_count && sem_info->cs_emit_wait) {
1530 wait_syncobj = radv_amdgpu_cs_alloc_syncobj_chunk(&sem_info->wait,
1531 &chunks[num_chunks],
1532 AMDGPU_CHUNK_ID_SYNCOBJ_IN);
1533 if (!wait_syncobj) {
1534 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1535 goto error_out;
1536 }
1537 num_chunks++;
1538
1539 if (sem_info->wait.sem_count == 0)
1540 sem_info->cs_emit_wait = false;
1541
1542 }
1543
1544 if (sem_info->wait.sem_count && sem_info->cs_emit_wait) {
1545 sem_dependencies = malloc(sizeof(sem_dependencies[0]) * sem_info->wait.sem_count);
1546 if (!sem_dependencies) {
1547 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1548 goto error_out;
1549 }
1550
1551 int sem_count = 0;
1552
1553 for (unsigned j = 0; j < sem_info->wait.sem_count; j++) {
1554 sem = (struct amdgpu_cs_fence *)sem_info->wait.sem[j];
1555 if (!sem->context)
1556 continue;
1557 struct drm_amdgpu_cs_chunk_dep *dep = &sem_dependencies[sem_count++];
1558
1559 amdgpu_cs_chunk_fence_to_dep(sem, dep);
1560
1561 sem->context = NULL;
1562 }
1563 i = num_chunks++;
1564
1565 /* dependencies chunk */
1566 chunks[i].chunk_id = AMDGPU_CHUNK_ID_DEPENDENCIES;
1567 chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_dep) / 4 * sem_count;
1568 chunks[i].chunk_data = (uint64_t)(uintptr_t)sem_dependencies;
1569
1570 sem_info->cs_emit_wait = false;
1571 }
1572
1573 if (sem_info->signal.syncobj_count && sem_info->cs_emit_signal) {
1574 signal_syncobj = radv_amdgpu_cs_alloc_syncobj_chunk(&sem_info->signal,
1575 &chunks[num_chunks],
1576 AMDGPU_CHUNK_ID_SYNCOBJ_OUT);
1577 if (!signal_syncobj) {
1578 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1579 goto error_out;
1580 }
1581 num_chunks++;
1582 }
1583
1584 if (use_bo_list_create) {
1585 /* Legacy path creating the buffer list handle and passing it
1586 * to the CS ioctl.
1587 */
1588 r = amdgpu_bo_list_create_raw(ctx->ws->dev, request->num_handles,
1589 request->handles, &bo_list);
1590 if (r) {
1591 if (r == -ENOMEM) {
1592 fprintf(stderr, "amdgpu: Not enough memory for buffer list creation.\n");
1593 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1594 } else {
1595 fprintf(stderr, "amdgpu: buffer list creation failed (%d).\n", r);
1596 result = VK_ERROR_UNKNOWN;
1597 }
1598 goto error_out;
1599 }
1600 } else {
1601 /* Standard path passing the buffer list via the CS ioctl. */
1602 bo_list_in.operation = ~0;
1603 bo_list_in.list_handle = ~0;
1604 bo_list_in.bo_number = request->num_handles;
1605 bo_list_in.bo_info_size = sizeof(struct drm_amdgpu_bo_list_entry);
1606 bo_list_in.bo_info_ptr = (uint64_t)(uintptr_t)request->handles;
1607
1608 chunks[num_chunks].chunk_id = AMDGPU_CHUNK_ID_BO_HANDLES;
1609 chunks[num_chunks].length_dw = sizeof(struct drm_amdgpu_bo_list_in) / 4;
1610 chunks[num_chunks].chunk_data = (uintptr_t)&bo_list_in;
1611 num_chunks++;
1612 }
1613
1614 r = amdgpu_cs_submit_raw2(ctx->ws->dev,
1615 ctx->ctx,
1616 bo_list,
1617 num_chunks,
1618 chunks,
1619 &request->seq_no);
1620
1621 if (bo_list)
1622 amdgpu_bo_list_destroy_raw(ctx->ws->dev, bo_list);
1623
1624 if (r) {
1625 if (r == -ENOMEM) {
1626 fprintf(stderr, "amdgpu: Not enough memory for command submission.\n");
1627 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1628 } else if (r == -ECANCELED) {
1629 fprintf(stderr, "amdgpu: The CS has been cancelled because the context is lost.\n");
1630 result = VK_ERROR_DEVICE_LOST;
1631 } else {
1632 fprintf(stderr, "amdgpu: The CS has been rejected, "
1633 "see dmesg for more information (%i).\n", r);
1634 result = VK_ERROR_UNKNOWN;
1635 }
1636 }
1637
1638 error_out:
1639 free(chunks);
1640 free(chunk_data);
1641 free(sem_dependencies);
1642 free(wait_syncobj);
1643 free(signal_syncobj);
1644 return result;
1645 }
1646
1647 static int radv_amdgpu_create_syncobj(struct radeon_winsys *_ws,
1648 bool create_signaled,
1649 uint32_t *handle)
1650 {
1651 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1652 uint32_t flags = 0;
1653
1654 if (create_signaled)
1655 flags |= DRM_SYNCOBJ_CREATE_SIGNALED;
1656
1657 return amdgpu_cs_create_syncobj2(ws->dev, flags, handle);
1658 }
1659
1660 static void radv_amdgpu_destroy_syncobj(struct radeon_winsys *_ws,
1661 uint32_t handle)
1662 {
1663 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1664 amdgpu_cs_destroy_syncobj(ws->dev, handle);
1665 }
1666
1667 static void radv_amdgpu_reset_syncobj(struct radeon_winsys *_ws,
1668 uint32_t handle)
1669 {
1670 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1671 amdgpu_cs_syncobj_reset(ws->dev, &handle, 1);
1672 }
1673
1674 static void radv_amdgpu_signal_syncobj(struct radeon_winsys *_ws,
1675 uint32_t handle)
1676 {
1677 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1678 amdgpu_cs_syncobj_signal(ws->dev, &handle, 1);
1679 }
1680
1681 static bool radv_amdgpu_wait_syncobj(struct radeon_winsys *_ws, const uint32_t *handles,
1682 uint32_t handle_count, bool wait_all, uint64_t timeout)
1683 {
1684 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1685 uint32_t tmp;
1686
1687 /* The timeouts are signed, while vulkan timeouts are unsigned. */
1688 timeout = MIN2(timeout, INT64_MAX);
1689
1690 int ret = amdgpu_cs_syncobj_wait(ws->dev, (uint32_t*)handles, handle_count, timeout,
1691 DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT |
1692 (wait_all ? DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL : 0),
1693 &tmp);
1694 if (ret == 0) {
1695 return true;
1696 } else if (ret == -ETIME) {
1697 return false;
1698 } else {
1699 fprintf(stderr, "amdgpu: radv_amdgpu_wait_syncobj failed!\nerrno: %d\n", errno);
1700 return false;
1701 }
1702 }
1703
1704 static int radv_amdgpu_export_syncobj(struct radeon_winsys *_ws,
1705 uint32_t syncobj,
1706 int *fd)
1707 {
1708 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1709
1710 return amdgpu_cs_export_syncobj(ws->dev, syncobj, fd);
1711 }
1712
1713 static int radv_amdgpu_import_syncobj(struct radeon_winsys *_ws,
1714 int fd,
1715 uint32_t *syncobj)
1716 {
1717 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1718
1719 return amdgpu_cs_import_syncobj(ws->dev, fd, syncobj);
1720 }
1721
1722
1723 static int radv_amdgpu_export_syncobj_to_sync_file(struct radeon_winsys *_ws,
1724 uint32_t syncobj,
1725 int *fd)
1726 {
1727 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1728
1729 return amdgpu_cs_syncobj_export_sync_file(ws->dev, syncobj, fd);
1730 }
1731
1732 static int radv_amdgpu_import_syncobj_from_sync_file(struct radeon_winsys *_ws,
1733 uint32_t syncobj,
1734 int fd)
1735 {
1736 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1737
1738 return amdgpu_cs_syncobj_import_sync_file(ws->dev, syncobj, fd);
1739 }
1740
1741 void radv_amdgpu_cs_init_functions(struct radv_amdgpu_winsys *ws)
1742 {
1743 ws->base.ctx_create = radv_amdgpu_ctx_create;
1744 ws->base.ctx_destroy = radv_amdgpu_ctx_destroy;
1745 ws->base.ctx_wait_idle = radv_amdgpu_ctx_wait_idle;
1746 ws->base.cs_create = radv_amdgpu_cs_create;
1747 ws->base.cs_destroy = radv_amdgpu_cs_destroy;
1748 ws->base.cs_grow = radv_amdgpu_cs_grow;
1749 ws->base.cs_finalize = radv_amdgpu_cs_finalize;
1750 ws->base.cs_reset = radv_amdgpu_cs_reset;
1751 ws->base.cs_add_buffer = radv_amdgpu_cs_add_buffer;
1752 ws->base.cs_execute_secondary = radv_amdgpu_cs_execute_secondary;
1753 ws->base.cs_submit = radv_amdgpu_winsys_cs_submit;
1754 ws->base.cs_dump = radv_amdgpu_winsys_cs_dump;
1755 ws->base.create_fence = radv_amdgpu_create_fence;
1756 ws->base.destroy_fence = radv_amdgpu_destroy_fence;
1757 ws->base.reset_fence = radv_amdgpu_reset_fence;
1758 ws->base.signal_fence = radv_amdgpu_signal_fence;
1759 ws->base.is_fence_waitable = radv_amdgpu_is_fence_waitable;
1760 ws->base.create_sem = radv_amdgpu_create_sem;
1761 ws->base.destroy_sem = radv_amdgpu_destroy_sem;
1762 ws->base.create_syncobj = radv_amdgpu_create_syncobj;
1763 ws->base.destroy_syncobj = radv_amdgpu_destroy_syncobj;
1764 ws->base.reset_syncobj = radv_amdgpu_reset_syncobj;
1765 ws->base.signal_syncobj = radv_amdgpu_signal_syncobj;
1766 ws->base.wait_syncobj = radv_amdgpu_wait_syncobj;
1767 ws->base.export_syncobj = radv_amdgpu_export_syncobj;
1768 ws->base.import_syncobj = radv_amdgpu_import_syncobj;
1769 ws->base.export_syncobj_to_sync_file = radv_amdgpu_export_syncobj_to_sync_file;
1770 ws->base.import_syncobj_from_sync_file = radv_amdgpu_import_syncobj_from_sync_file;
1771 ws->base.fence_wait = radv_amdgpu_fence_wait;
1772 ws->base.fences_wait = radv_amdgpu_fences_wait;
1773 }