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[mesa.git] / src / amd / vulkan / winsys / amdgpu / radv_amdgpu_cs.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <stdlib.h>
26 #include <amdgpu.h>
27 #include <amdgpu_drm.h>
28 #include <assert.h>
29 #include <pthread.h>
30 #include <errno.h>
31
32 #include "ac_debug.h"
33 #include "radv_radeon_winsys.h"
34 #include "radv_amdgpu_cs.h"
35 #include "radv_amdgpu_bo.h"
36 #include "sid.h"
37
38
39 enum {
40 VIRTUAL_BUFFER_HASH_TABLE_SIZE = 1024
41 };
42
43 struct radv_amdgpu_cs {
44 struct radeon_cmdbuf base;
45 struct radv_amdgpu_winsys *ws;
46
47 struct amdgpu_cs_ib_info ib;
48
49 struct radeon_winsys_bo *ib_buffer;
50 uint8_t *ib_mapped;
51 unsigned max_num_buffers;
52 unsigned num_buffers;
53 amdgpu_bo_handle *handles;
54
55 struct radeon_winsys_bo **old_ib_buffers;
56 unsigned num_old_ib_buffers;
57 unsigned max_num_old_ib_buffers;
58 unsigned *ib_size_ptr;
59 bool failed;
60 bool is_chained;
61
62 int buffer_hash_table[1024];
63 unsigned hw_ip;
64
65 unsigned num_virtual_buffers;
66 unsigned max_num_virtual_buffers;
67 struct radeon_winsys_bo **virtual_buffers;
68 int *virtual_buffer_hash_table;
69
70 /* For chips that don't support chaining. */
71 struct radeon_cmdbuf *old_cs_buffers;
72 unsigned num_old_cs_buffers;
73 };
74
75 static inline struct radv_amdgpu_cs *
76 radv_amdgpu_cs(struct radeon_cmdbuf *base)
77 {
78 return (struct radv_amdgpu_cs*)base;
79 }
80
81 static int ring_to_hw_ip(enum ring_type ring)
82 {
83 switch (ring) {
84 case RING_GFX:
85 return AMDGPU_HW_IP_GFX;
86 case RING_DMA:
87 return AMDGPU_HW_IP_DMA;
88 case RING_COMPUTE:
89 return AMDGPU_HW_IP_COMPUTE;
90 default:
91 unreachable("unsupported ring");
92 }
93 }
94
95 static int radv_amdgpu_signal_sems(struct radv_amdgpu_ctx *ctx,
96 uint32_t ip_type,
97 uint32_t ring,
98 struct radv_winsys_sem_info *sem_info);
99 static int radv_amdgpu_cs_submit(struct radv_amdgpu_ctx *ctx,
100 struct amdgpu_cs_request *request,
101 struct radv_winsys_sem_info *sem_info);
102
103 static void radv_amdgpu_request_to_fence(struct radv_amdgpu_ctx *ctx,
104 struct radv_amdgpu_fence *fence,
105 struct amdgpu_cs_request *req)
106 {
107 fence->fence.context = ctx->ctx;
108 fence->fence.ip_type = req->ip_type;
109 fence->fence.ip_instance = req->ip_instance;
110 fence->fence.ring = req->ring;
111 fence->fence.fence = req->seq_no;
112 fence->user_ptr = (volatile uint64_t*)(ctx->fence_map + (req->ip_type * MAX_RINGS_PER_TYPE + req->ring) * sizeof(uint64_t));
113 }
114
115 static struct radeon_winsys_fence *radv_amdgpu_create_fence()
116 {
117 struct radv_amdgpu_fence *fence = calloc(1, sizeof(struct radv_amdgpu_fence));
118 return (struct radeon_winsys_fence*)fence;
119 }
120
121 static void radv_amdgpu_destroy_fence(struct radeon_winsys_fence *_fence)
122 {
123 struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
124 free(fence);
125 }
126
127 static bool radv_amdgpu_fence_wait(struct radeon_winsys *_ws,
128 struct radeon_winsys_fence *_fence,
129 bool absolute,
130 uint64_t timeout)
131 {
132 struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
133 unsigned flags = absolute ? AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE : 0;
134 int r;
135 uint32_t expired = 0;
136
137 if (fence->user_ptr) {
138 if (*fence->user_ptr >= fence->fence.fence)
139 return true;
140 if (!absolute && !timeout)
141 return false;
142 }
143
144 /* Now use the libdrm query. */
145 r = amdgpu_cs_query_fence_status(&fence->fence,
146 timeout,
147 flags,
148 &expired);
149
150 if (r) {
151 fprintf(stderr, "amdgpu: radv_amdgpu_cs_query_fence_status failed.\n");
152 return false;
153 }
154
155 if (expired)
156 return true;
157
158 return false;
159 }
160
161
162 static bool radv_amdgpu_fences_wait(struct radeon_winsys *_ws,
163 struct radeon_winsys_fence *const *_fences,
164 uint32_t fence_count,
165 bool wait_all,
166 uint64_t timeout)
167 {
168 struct amdgpu_cs_fence *fences = malloc(sizeof(struct amdgpu_cs_fence) * fence_count);
169 int r;
170 uint32_t expired = 0, first = 0;
171
172 if (!fences)
173 return false;
174
175 for (uint32_t i = 0; i < fence_count; ++i)
176 fences[i] = ((struct radv_amdgpu_fence *)_fences[i])->fence;
177
178 /* Now use the libdrm query. */
179 r = amdgpu_cs_wait_fences(fences, fence_count, wait_all,
180 timeout, &expired, &first);
181
182 free(fences);
183 if (r) {
184 fprintf(stderr, "amdgpu: amdgpu_cs_wait_fences failed.\n");
185 return false;
186 }
187
188 if (expired)
189 return true;
190
191 return false;
192 }
193
194 static void radv_amdgpu_cs_destroy(struct radeon_cmdbuf *rcs)
195 {
196 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(rcs);
197
198 if (cs->ib_buffer)
199 cs->ws->base.buffer_destroy(cs->ib_buffer);
200 else
201 free(cs->base.buf);
202
203 for (unsigned i = 0; i < cs->num_old_ib_buffers; ++i)
204 cs->ws->base.buffer_destroy(cs->old_ib_buffers[i]);
205
206 for (unsigned i = 0; i < cs->num_old_cs_buffers; ++i) {
207 struct radeon_cmdbuf *rcs = &cs->old_cs_buffers[i];
208 free(rcs->buf);
209 }
210
211 free(cs->old_cs_buffers);
212 free(cs->old_ib_buffers);
213 free(cs->virtual_buffers);
214 free(cs->virtual_buffer_hash_table);
215 free(cs->handles);
216 free(cs);
217 }
218
219 static void radv_amdgpu_init_cs(struct radv_amdgpu_cs *cs,
220 enum ring_type ring_type)
221 {
222 for (int i = 0; i < ARRAY_SIZE(cs->buffer_hash_table); ++i)
223 cs->buffer_hash_table[i] = -1;
224
225 cs->hw_ip = ring_to_hw_ip(ring_type);
226 }
227
228 static struct radeon_cmdbuf *
229 radv_amdgpu_cs_create(struct radeon_winsys *ws,
230 enum ring_type ring_type)
231 {
232 struct radv_amdgpu_cs *cs;
233 uint32_t ib_size = 20 * 1024 * 4;
234 cs = calloc(1, sizeof(struct radv_amdgpu_cs));
235 if (!cs)
236 return NULL;
237
238 cs->ws = radv_amdgpu_winsys(ws);
239 radv_amdgpu_init_cs(cs, ring_type);
240
241 if (cs->ws->use_ib_bos) {
242 cs->ib_buffer = ws->buffer_create(ws, ib_size, 0,
243 RADEON_DOMAIN_GTT,
244 RADEON_FLAG_CPU_ACCESS |
245 RADEON_FLAG_NO_INTERPROCESS_SHARING |
246 RADEON_FLAG_READ_ONLY);
247 if (!cs->ib_buffer) {
248 free(cs);
249 return NULL;
250 }
251
252 cs->ib_mapped = ws->buffer_map(cs->ib_buffer);
253 if (!cs->ib_mapped) {
254 ws->buffer_destroy(cs->ib_buffer);
255 free(cs);
256 return NULL;
257 }
258
259 cs->ib.ib_mc_address = radv_amdgpu_winsys_bo(cs->ib_buffer)->base.va;
260 cs->base.buf = (uint32_t *)cs->ib_mapped;
261 cs->base.max_dw = ib_size / 4 - 4;
262 cs->ib_size_ptr = &cs->ib.size;
263 cs->ib.size = 0;
264
265 ws->cs_add_buffer(&cs->base, cs->ib_buffer);
266 } else {
267 cs->base.buf = malloc(16384);
268 cs->base.max_dw = 4096;
269 if (!cs->base.buf) {
270 free(cs);
271 return NULL;
272 }
273 }
274
275 return &cs->base;
276 }
277
278 static void radv_amdgpu_cs_grow(struct radeon_cmdbuf *_cs, size_t min_size)
279 {
280 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
281
282 if (cs->failed) {
283 cs->base.cdw = 0;
284 return;
285 }
286
287 if (!cs->ws->use_ib_bos) {
288 const uint64_t limit_dws = 0xffff8;
289 uint64_t ib_dws = MAX2(cs->base.cdw + min_size,
290 MIN2(cs->base.max_dw * 2, limit_dws));
291
292 /* The total ib size cannot exceed limit_dws dwords. */
293 if (ib_dws > limit_dws)
294 {
295 /* The maximum size in dwords has been reached,
296 * try to allocate a new one.
297 */
298 if (cs->num_old_cs_buffers + 1 >= AMDGPU_CS_MAX_IBS_PER_SUBMIT) {
299 /* TODO: Allow to submit more than 4 IBs. */
300 fprintf(stderr, "amdgpu: Maximum number of IBs "
301 "per submit reached.\n");
302 cs->failed = true;
303 cs->base.cdw = 0;
304 return;
305 }
306
307 cs->old_cs_buffers =
308 realloc(cs->old_cs_buffers,
309 (cs->num_old_cs_buffers + 1) * sizeof(*cs->old_cs_buffers));
310 if (!cs->old_cs_buffers) {
311 cs->failed = true;
312 cs->base.cdw = 0;
313 return;
314 }
315
316 /* Store the current one for submitting it later. */
317 cs->old_cs_buffers[cs->num_old_cs_buffers].cdw = cs->base.cdw;
318 cs->old_cs_buffers[cs->num_old_cs_buffers].max_dw = cs->base.max_dw;
319 cs->old_cs_buffers[cs->num_old_cs_buffers].buf = cs->base.buf;
320 cs->num_old_cs_buffers++;
321
322 /* Reset the cs, it will be re-allocated below. */
323 cs->base.cdw = 0;
324 cs->base.buf = NULL;
325
326 /* Re-compute the number of dwords to allocate. */
327 ib_dws = MAX2(cs->base.cdw + min_size,
328 MIN2(cs->base.max_dw * 2, limit_dws));
329 if (ib_dws > limit_dws) {
330 fprintf(stderr, "amdgpu: Too high number of "
331 "dwords to allocate\n");
332 cs->failed = true;
333 return;
334 }
335 }
336
337 uint32_t *new_buf = realloc(cs->base.buf, ib_dws * 4);
338 if (new_buf) {
339 cs->base.buf = new_buf;
340 cs->base.max_dw = ib_dws;
341 } else {
342 cs->failed = true;
343 cs->base.cdw = 0;
344 }
345 return;
346 }
347
348 uint64_t ib_size = MAX2(min_size * 4 + 16, cs->base.max_dw * 4 * 2);
349
350 /* max that fits in the chain size field. */
351 ib_size = MIN2(ib_size, 0xfffff);
352
353 while (!cs->base.cdw || (cs->base.cdw & 7) != 4)
354 radeon_emit(&cs->base, 0xffff1000);
355
356 *cs->ib_size_ptr |= cs->base.cdw + 4;
357
358 if (cs->num_old_ib_buffers == cs->max_num_old_ib_buffers) {
359 cs->max_num_old_ib_buffers = MAX2(1, cs->max_num_old_ib_buffers * 2);
360 cs->old_ib_buffers = realloc(cs->old_ib_buffers,
361 cs->max_num_old_ib_buffers * sizeof(void*));
362 }
363
364 cs->old_ib_buffers[cs->num_old_ib_buffers++] = cs->ib_buffer;
365
366 cs->ib_buffer = cs->ws->base.buffer_create(&cs->ws->base, ib_size, 0,
367 RADEON_DOMAIN_GTT,
368 RADEON_FLAG_CPU_ACCESS |
369 RADEON_FLAG_NO_INTERPROCESS_SHARING |
370 RADEON_FLAG_READ_ONLY);
371
372 if (!cs->ib_buffer) {
373 cs->base.cdw = 0;
374 cs->failed = true;
375 cs->ib_buffer = cs->old_ib_buffers[--cs->num_old_ib_buffers];
376 }
377
378 cs->ib_mapped = cs->ws->base.buffer_map(cs->ib_buffer);
379 if (!cs->ib_mapped) {
380 cs->ws->base.buffer_destroy(cs->ib_buffer);
381 cs->base.cdw = 0;
382 cs->failed = true;
383 cs->ib_buffer = cs->old_ib_buffers[--cs->num_old_ib_buffers];
384 }
385
386 cs->ws->base.cs_add_buffer(&cs->base, cs->ib_buffer);
387
388 radeon_emit(&cs->base, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
389 radeon_emit(&cs->base, radv_amdgpu_winsys_bo(cs->ib_buffer)->base.va);
390 radeon_emit(&cs->base, radv_amdgpu_winsys_bo(cs->ib_buffer)->base.va >> 32);
391 radeon_emit(&cs->base, S_3F2_CHAIN(1) | S_3F2_VALID(1));
392
393 cs->ib_size_ptr = cs->base.buf + cs->base.cdw - 1;
394
395 cs->base.buf = (uint32_t *)cs->ib_mapped;
396 cs->base.cdw = 0;
397 cs->base.max_dw = ib_size / 4 - 4;
398
399 }
400
401 static bool radv_amdgpu_cs_finalize(struct radeon_cmdbuf *_cs)
402 {
403 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
404
405 if (cs->ws->use_ib_bos) {
406 while (!cs->base.cdw || (cs->base.cdw & 7) != 0)
407 radeon_emit(&cs->base, 0xffff1000);
408
409 *cs->ib_size_ptr |= cs->base.cdw;
410
411 cs->is_chained = false;
412 }
413
414 return !cs->failed;
415 }
416
417 static void radv_amdgpu_cs_reset(struct radeon_cmdbuf *_cs)
418 {
419 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
420 cs->base.cdw = 0;
421 cs->failed = false;
422
423 for (unsigned i = 0; i < cs->num_buffers; ++i) {
424 unsigned hash = ((uintptr_t)cs->handles[i] >> 6) &
425 (ARRAY_SIZE(cs->buffer_hash_table) - 1);
426 cs->buffer_hash_table[hash] = -1;
427 }
428
429 for (unsigned i = 0; i < cs->num_virtual_buffers; ++i) {
430 unsigned hash = ((uintptr_t)cs->virtual_buffers[i] >> 6) & (VIRTUAL_BUFFER_HASH_TABLE_SIZE - 1);
431 cs->virtual_buffer_hash_table[hash] = -1;
432 }
433
434 cs->num_buffers = 0;
435 cs->num_virtual_buffers = 0;
436
437 if (cs->ws->use_ib_bos) {
438 cs->ws->base.cs_add_buffer(&cs->base, cs->ib_buffer);
439
440 for (unsigned i = 0; i < cs->num_old_ib_buffers; ++i)
441 cs->ws->base.buffer_destroy(cs->old_ib_buffers[i]);
442
443 cs->num_old_ib_buffers = 0;
444 cs->ib.ib_mc_address = radv_amdgpu_winsys_bo(cs->ib_buffer)->base.va;
445 cs->ib_size_ptr = &cs->ib.size;
446 cs->ib.size = 0;
447 } else {
448 for (unsigned i = 0; i < cs->num_old_cs_buffers; ++i) {
449 struct radeon_cmdbuf *rcs = &cs->old_cs_buffers[i];
450 free(rcs->buf);
451 }
452
453 free(cs->old_cs_buffers);
454 cs->old_cs_buffers = NULL;
455 cs->num_old_cs_buffers = 0;
456 }
457 }
458
459 static int radv_amdgpu_cs_find_buffer(struct radv_amdgpu_cs *cs,
460 amdgpu_bo_handle bo)
461 {
462 unsigned hash = ((uintptr_t)bo >> 6) & (ARRAY_SIZE(cs->buffer_hash_table) - 1);
463 int index = cs->buffer_hash_table[hash];
464
465 if (index == -1)
466 return -1;
467
468 if (cs->handles[index] == bo)
469 return index;
470
471 for (unsigned i = 0; i < cs->num_buffers; ++i) {
472 if (cs->handles[i] == bo) {
473 cs->buffer_hash_table[hash] = i;
474 return i;
475 }
476 }
477
478 return -1;
479 }
480
481 static void radv_amdgpu_cs_add_buffer_internal(struct radv_amdgpu_cs *cs,
482 amdgpu_bo_handle bo)
483 {
484 unsigned hash;
485 int index = radv_amdgpu_cs_find_buffer(cs, bo);
486
487 if (index != -1)
488 return;
489
490 if (cs->num_buffers == cs->max_num_buffers) {
491 unsigned new_count = MAX2(1, cs->max_num_buffers * 2);
492 cs->handles = realloc(cs->handles, new_count * sizeof(amdgpu_bo_handle));
493 cs->max_num_buffers = new_count;
494 }
495
496 cs->handles[cs->num_buffers] = bo;
497
498 hash = ((uintptr_t)bo >> 6) & (ARRAY_SIZE(cs->buffer_hash_table) - 1);
499 cs->buffer_hash_table[hash] = cs->num_buffers;
500
501 ++cs->num_buffers;
502 }
503
504 static void radv_amdgpu_cs_add_virtual_buffer(struct radeon_cmdbuf *_cs,
505 struct radeon_winsys_bo *bo)
506 {
507 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
508 unsigned hash = ((uintptr_t)bo >> 6) & (VIRTUAL_BUFFER_HASH_TABLE_SIZE - 1);
509
510
511 if (!cs->virtual_buffer_hash_table) {
512 cs->virtual_buffer_hash_table = malloc(VIRTUAL_BUFFER_HASH_TABLE_SIZE * sizeof(int));
513 for (int i = 0; i < VIRTUAL_BUFFER_HASH_TABLE_SIZE; ++i)
514 cs->virtual_buffer_hash_table[i] = -1;
515 }
516
517 if (cs->virtual_buffer_hash_table[hash] >= 0) {
518 int idx = cs->virtual_buffer_hash_table[hash];
519 if (cs->virtual_buffers[idx] == bo) {
520 return;
521 }
522 for (unsigned i = 0; i < cs->num_virtual_buffers; ++i) {
523 if (cs->virtual_buffers[i] == bo) {
524 cs->virtual_buffer_hash_table[hash] = i;
525 return;
526 }
527 }
528 }
529
530 if(cs->max_num_virtual_buffers <= cs->num_virtual_buffers) {
531 cs->max_num_virtual_buffers = MAX2(2, cs->max_num_virtual_buffers * 2);
532 cs->virtual_buffers = realloc(cs->virtual_buffers, sizeof(struct radv_amdgpu_virtual_virtual_buffer*) * cs->max_num_virtual_buffers);
533 }
534
535 cs->virtual_buffers[cs->num_virtual_buffers] = bo;
536
537 cs->virtual_buffer_hash_table[hash] = cs->num_virtual_buffers;
538 ++cs->num_virtual_buffers;
539
540 }
541
542 static void radv_amdgpu_cs_add_buffer(struct radeon_cmdbuf *_cs,
543 struct radeon_winsys_bo *_bo)
544 {
545 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
546 struct radv_amdgpu_winsys_bo *bo = radv_amdgpu_winsys_bo(_bo);
547
548 if (bo->is_virtual) {
549 radv_amdgpu_cs_add_virtual_buffer(_cs, _bo);
550 return;
551 }
552
553 if (bo->base.is_local)
554 return;
555
556 radv_amdgpu_cs_add_buffer_internal(cs, bo->bo);
557 }
558
559 static void radv_amdgpu_cs_execute_secondary(struct radeon_cmdbuf *_parent,
560 struct radeon_cmdbuf *_child)
561 {
562 struct radv_amdgpu_cs *parent = radv_amdgpu_cs(_parent);
563 struct radv_amdgpu_cs *child = radv_amdgpu_cs(_child);
564
565 for (unsigned i = 0; i < child->num_buffers; ++i) {
566 radv_amdgpu_cs_add_buffer_internal(parent, child->handles[i]);
567 }
568
569 for (unsigned i = 0; i < child->num_virtual_buffers; ++i) {
570 radv_amdgpu_cs_add_buffer(&parent->base, child->virtual_buffers[i]);
571 }
572
573 if (parent->ws->use_ib_bos) {
574 if (parent->base.cdw + 4 > parent->base.max_dw)
575 radv_amdgpu_cs_grow(&parent->base, 4);
576
577 radeon_emit(&parent->base, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
578 radeon_emit(&parent->base, child->ib.ib_mc_address);
579 radeon_emit(&parent->base, child->ib.ib_mc_address >> 32);
580 radeon_emit(&parent->base, child->ib.size);
581 } else {
582 if (parent->base.cdw + child->base.cdw > parent->base.max_dw)
583 radv_amdgpu_cs_grow(&parent->base, child->base.cdw);
584
585 memcpy(parent->base.buf + parent->base.cdw, child->base.buf, 4 * child->base.cdw);
586 parent->base.cdw += child->base.cdw;
587 }
588 }
589
590 static int radv_amdgpu_create_bo_list(struct radv_amdgpu_winsys *ws,
591 struct radeon_cmdbuf **cs_array,
592 unsigned count,
593 struct radv_amdgpu_winsys_bo **extra_bo_array,
594 unsigned num_extra_bo,
595 struct radeon_cmdbuf *extra_cs,
596 const struct radv_winsys_bo_list *radv_bo_list,
597 amdgpu_bo_list_handle *bo_list)
598 {
599 int r = 0;
600
601 if (ws->debug_all_bos) {
602 struct radv_amdgpu_winsys_bo *bo;
603 amdgpu_bo_handle *handles;
604 unsigned num = 0;
605
606 pthread_mutex_lock(&ws->global_bo_list_lock);
607
608 handles = malloc(sizeof(handles[0]) * ws->num_buffers);
609 if (!handles) {
610 pthread_mutex_unlock(&ws->global_bo_list_lock);
611 return -ENOMEM;
612 }
613
614 LIST_FOR_EACH_ENTRY(bo, &ws->global_bo_list, global_list_item) {
615 assert(num < ws->num_buffers);
616 handles[num++] = bo->bo;
617 }
618
619 r = amdgpu_bo_list_create(ws->dev, ws->num_buffers,
620 handles, NULL,
621 bo_list);
622 free(handles);
623 pthread_mutex_unlock(&ws->global_bo_list_lock);
624 } else if (count == 1 && !num_extra_bo && !extra_cs && !radv_bo_list &&
625 !radv_amdgpu_cs(cs_array[0])->num_virtual_buffers) {
626 struct radv_amdgpu_cs *cs = (struct radv_amdgpu_cs*)cs_array[0];
627 if (cs->num_buffers == 0) {
628 *bo_list = 0;
629 return 0;
630 }
631 r = amdgpu_bo_list_create(ws->dev, cs->num_buffers, cs->handles,
632 NULL, bo_list);
633 } else {
634 unsigned total_buffer_count = num_extra_bo;
635 unsigned unique_bo_count = num_extra_bo;
636 for (unsigned i = 0; i < count; ++i) {
637 struct radv_amdgpu_cs *cs = (struct radv_amdgpu_cs*)cs_array[i];
638 total_buffer_count += cs->num_buffers;
639 for (unsigned j = 0; j < cs->num_virtual_buffers; ++j)
640 total_buffer_count += radv_amdgpu_winsys_bo(cs->virtual_buffers[j])->bo_count;
641 }
642
643 if (extra_cs) {
644 total_buffer_count += ((struct radv_amdgpu_cs*)extra_cs)->num_buffers;
645 }
646
647 if (radv_bo_list) {
648 total_buffer_count += radv_bo_list->count;
649 }
650
651 if (total_buffer_count == 0) {
652 *bo_list = 0;
653 return 0;
654 }
655 amdgpu_bo_handle *handles = malloc(sizeof(amdgpu_bo_handle) * total_buffer_count);
656 if (!handles) {
657 free(handles);
658 return -ENOMEM;
659 }
660
661 for (unsigned i = 0; i < num_extra_bo; i++) {
662 handles[i] = extra_bo_array[i]->bo;
663 }
664
665 for (unsigned i = 0; i < count + !!extra_cs; ++i) {
666 struct radv_amdgpu_cs *cs;
667
668 if (i == count)
669 cs = (struct radv_amdgpu_cs*)extra_cs;
670 else
671 cs = (struct radv_amdgpu_cs*)cs_array[i];
672
673 if (!cs->num_buffers)
674 continue;
675
676 if (unique_bo_count == 0 && !cs->num_virtual_buffers) {
677 memcpy(handles, cs->handles, cs->num_buffers * sizeof(amdgpu_bo_handle));
678 unique_bo_count = cs->num_buffers;
679 continue;
680 }
681 int unique_bo_so_far = unique_bo_count;
682 for (unsigned j = 0; j < cs->num_buffers; ++j) {
683 bool found = false;
684 for (unsigned k = 0; k < unique_bo_so_far; ++k) {
685 if (handles[k] == cs->handles[j]) {
686 found = true;
687 break;
688 }
689 }
690 if (!found) {
691 handles[unique_bo_count] = cs->handles[j];
692 ++unique_bo_count;
693 }
694 }
695 for (unsigned j = 0; j < cs->num_virtual_buffers; ++j) {
696 struct radv_amdgpu_winsys_bo *virtual_bo = radv_amdgpu_winsys_bo(cs->virtual_buffers[j]);
697 for(unsigned k = 0; k < virtual_bo->bo_count; ++k) {
698 struct radv_amdgpu_winsys_bo *bo = virtual_bo->bos[k];
699 bool found = false;
700 for (unsigned m = 0; m < unique_bo_count; ++m) {
701 if (handles[m] == bo->bo) {
702 found = true;
703 break;
704 }
705 }
706 if (!found) {
707 handles[unique_bo_count] = bo->bo;
708 ++unique_bo_count;
709 }
710 }
711 }
712 }
713
714 if (radv_bo_list) {
715 unsigned unique_bo_so_far = unique_bo_count;
716 for (unsigned i = 0; i < radv_bo_list->count; ++i) {
717 struct radv_amdgpu_winsys_bo *bo = radv_amdgpu_winsys_bo(radv_bo_list->bos[i]);
718 bool found = false;
719 for (unsigned j = 0; j < unique_bo_so_far; ++j) {
720 if (bo->bo == handles[j]) {
721 found = true;
722 break;
723 }
724 }
725 if (!found) {
726 handles[unique_bo_count] = bo->bo;
727 ++unique_bo_count;
728 }
729 }
730 }
731
732 if (unique_bo_count > 0) {
733 r = amdgpu_bo_list_create(ws->dev, unique_bo_count, handles,
734 NULL, bo_list);
735 } else {
736 *bo_list = 0;
737 }
738
739 free(handles);
740 }
741
742 return r;
743 }
744
745 static struct amdgpu_cs_fence_info radv_set_cs_fence(struct radv_amdgpu_ctx *ctx, int ip_type, int ring)
746 {
747 struct amdgpu_cs_fence_info ret = {0};
748 if (ctx->fence_map) {
749 ret.handle = radv_amdgpu_winsys_bo(ctx->fence_bo)->bo;
750 ret.offset = (ip_type * MAX_RINGS_PER_TYPE + ring) * sizeof(uint64_t);
751 }
752 return ret;
753 }
754
755 static void radv_assign_last_submit(struct radv_amdgpu_ctx *ctx,
756 struct amdgpu_cs_request *request)
757 {
758 radv_amdgpu_request_to_fence(ctx,
759 &ctx->last_submission[request->ip_type][request->ring],
760 request);
761 }
762
763 static int radv_amdgpu_winsys_cs_submit_chained(struct radeon_winsys_ctx *_ctx,
764 int queue_idx,
765 struct radv_winsys_sem_info *sem_info,
766 const struct radv_winsys_bo_list *radv_bo_list,
767 struct radeon_cmdbuf **cs_array,
768 unsigned cs_count,
769 struct radeon_cmdbuf *initial_preamble_cs,
770 struct radeon_cmdbuf *continue_preamble_cs,
771 struct radeon_winsys_fence *_fence)
772 {
773 int r;
774 struct radv_amdgpu_ctx *ctx = radv_amdgpu_ctx(_ctx);
775 struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
776 struct radv_amdgpu_cs *cs0 = radv_amdgpu_cs(cs_array[0]);
777 amdgpu_bo_list_handle bo_list;
778 struct amdgpu_cs_request request = {0};
779 struct amdgpu_cs_ib_info ibs[2];
780 unsigned number_of_ibs = 1;
781
782 for (unsigned i = cs_count; i--;) {
783 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[i]);
784
785 if (cs->is_chained) {
786 *cs->ib_size_ptr -= 4;
787 cs->is_chained = false;
788 }
789
790 if (i + 1 < cs_count) {
791 struct radv_amdgpu_cs *next = radv_amdgpu_cs(cs_array[i + 1]);
792 assert(cs->base.cdw + 4 <= cs->base.max_dw);
793
794 cs->is_chained = true;
795 *cs->ib_size_ptr += 4;
796
797 cs->base.buf[cs->base.cdw + 0] = PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0);
798 cs->base.buf[cs->base.cdw + 1] = next->ib.ib_mc_address;
799 cs->base.buf[cs->base.cdw + 2] = next->ib.ib_mc_address >> 32;
800 cs->base.buf[cs->base.cdw + 3] = S_3F2_CHAIN(1) | S_3F2_VALID(1) | next->ib.size;
801 }
802 }
803
804 /* Create a buffer object list. */
805 r = radv_amdgpu_create_bo_list(cs0->ws, cs_array, cs_count, NULL, 0,
806 initial_preamble_cs, radv_bo_list,
807 &bo_list);
808 if (r) {
809 fprintf(stderr, "amdgpu: buffer list creation failed for the "
810 "chained submission(%d)\n", r);
811 return r;
812 }
813
814 /* Configure the CS request. */
815 if (initial_preamble_cs) {
816 ibs[0] = radv_amdgpu_cs(initial_preamble_cs)->ib;
817 ibs[1] = cs0->ib;
818 number_of_ibs++;
819 } else {
820 ibs[0] = cs0->ib;
821 }
822
823 request.ip_type = cs0->hw_ip;
824 request.ring = queue_idx;
825 request.number_of_ibs = number_of_ibs;
826 request.ibs = ibs;
827 request.resources = bo_list;
828 request.fence_info = radv_set_cs_fence(ctx, cs0->hw_ip, queue_idx);
829
830 /* Submit the CS. */
831 r = radv_amdgpu_cs_submit(ctx, &request, sem_info);
832 if (r) {
833 if (r == -ENOMEM)
834 fprintf(stderr, "amdgpu: Not enough memory for command submission.\n");
835 else
836 fprintf(stderr, "amdgpu: The CS has been rejected, "
837 "see dmesg for more information.\n");
838 }
839
840 if (bo_list)
841 amdgpu_bo_list_destroy(bo_list);
842
843 if (r)
844 return r;
845
846 if (fence)
847 radv_amdgpu_request_to_fence(ctx, fence, &request);
848
849 radv_assign_last_submit(ctx, &request);
850
851 return 0;
852 }
853
854 static int radv_amdgpu_winsys_cs_submit_fallback(struct radeon_winsys_ctx *_ctx,
855 int queue_idx,
856 struct radv_winsys_sem_info *sem_info,
857 const struct radv_winsys_bo_list *radv_bo_list,
858 struct radeon_cmdbuf **cs_array,
859 unsigned cs_count,
860 struct radeon_cmdbuf *initial_preamble_cs,
861 struct radeon_cmdbuf *continue_preamble_cs,
862 struct radeon_winsys_fence *_fence)
863 {
864 int r;
865 struct radv_amdgpu_ctx *ctx = radv_amdgpu_ctx(_ctx);
866 struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
867 amdgpu_bo_list_handle bo_list;
868 struct amdgpu_cs_request request = {};
869 struct amdgpu_cs_ib_info *ibs;
870 struct radv_amdgpu_cs *cs0;
871 unsigned number_of_ibs;
872
873 assert(cs_count);
874 cs0 = radv_amdgpu_cs(cs_array[0]);
875
876 /* Compute the number of IBs for this submit. */
877 number_of_ibs = cs_count + !!initial_preamble_cs;
878
879 /* Create a buffer object list. */
880 r = radv_amdgpu_create_bo_list(cs0->ws, &cs_array[0], cs_count, NULL, 0,
881 initial_preamble_cs, radv_bo_list,
882 &bo_list);
883 if (r) {
884 fprintf(stderr, "amdgpu: buffer list creation failed "
885 "for the fallback submission (%d)\n", r);
886 return r;
887 }
888
889 ibs = malloc(number_of_ibs * sizeof(*ibs));
890 if (!ibs) {
891 if (bo_list)
892 amdgpu_bo_list_destroy(bo_list);
893 return -ENOMEM;
894 }
895
896 /* Configure the CS request. */
897 if (initial_preamble_cs)
898 ibs[0] = radv_amdgpu_cs(initial_preamble_cs)->ib;
899
900 for (unsigned i = 0; i < cs_count; i++) {
901 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[i]);
902
903 ibs[i + !!initial_preamble_cs] = cs->ib;
904
905 if (cs->is_chained) {
906 *cs->ib_size_ptr -= 4;
907 cs->is_chained = false;
908 }
909 }
910
911 request.ip_type = cs0->hw_ip;
912 request.ring = queue_idx;
913 request.resources = bo_list;
914 request.number_of_ibs = number_of_ibs;
915 request.ibs = ibs;
916 request.fence_info = radv_set_cs_fence(ctx, cs0->hw_ip, queue_idx);
917
918 /* Submit the CS. */
919 r = radv_amdgpu_cs_submit(ctx, &request, sem_info);
920 if (r) {
921 if (r == -ENOMEM)
922 fprintf(stderr, "amdgpu: Not enough memory for command submission.\n");
923 else
924 fprintf(stderr, "amdgpu: The CS has been rejected, "
925 "see dmesg for more information.\n");
926 }
927
928 if (bo_list)
929 amdgpu_bo_list_destroy(bo_list);
930 free(ibs);
931
932 if (r)
933 return r;
934
935 if (fence)
936 radv_amdgpu_request_to_fence(ctx, fence, &request);
937
938 radv_assign_last_submit(ctx, &request);
939
940 return 0;
941 }
942
943 static int radv_amdgpu_winsys_cs_submit_sysmem(struct radeon_winsys_ctx *_ctx,
944 int queue_idx,
945 struct radv_winsys_sem_info *sem_info,
946 const struct radv_winsys_bo_list *radv_bo_list,
947 struct radeon_cmdbuf **cs_array,
948 unsigned cs_count,
949 struct radeon_cmdbuf *initial_preamble_cs,
950 struct radeon_cmdbuf *continue_preamble_cs,
951 struct radeon_winsys_fence *_fence)
952 {
953 int r;
954 struct radv_amdgpu_ctx *ctx = radv_amdgpu_ctx(_ctx);
955 struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
956 struct radv_amdgpu_cs *cs0 = radv_amdgpu_cs(cs_array[0]);
957 struct radeon_winsys *ws = (struct radeon_winsys*)cs0->ws;
958 amdgpu_bo_list_handle bo_list;
959 struct amdgpu_cs_request request;
960 uint32_t pad_word = 0xffff1000U;
961 bool emit_signal_sem = sem_info->cs_emit_signal;
962
963 if (radv_amdgpu_winsys(ws)->info.chip_class == SI)
964 pad_word = 0x80000000;
965
966 assert(cs_count);
967
968 for (unsigned i = 0; i < cs_count;) {
969 struct amdgpu_cs_ib_info ibs[AMDGPU_CS_MAX_IBS_PER_SUBMIT] = {0};
970 unsigned number_of_ibs = 1;
971 struct radeon_winsys_bo *bos[AMDGPU_CS_MAX_IBS_PER_SUBMIT] = {0};
972 struct radeon_cmdbuf *preamble_cs = i ? continue_preamble_cs : initial_preamble_cs;
973 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[i]);
974 uint32_t *ptr;
975 unsigned cnt = 0;
976 unsigned size = 0;
977 unsigned pad_words = 0;
978
979 if (cs->num_old_cs_buffers > 0) {
980 /* Special path when the maximum size in dwords has
981 * been reached because we need to handle more than one
982 * IB per submit.
983 */
984 unsigned new_cs_count = cs->num_old_cs_buffers + 1;
985 struct radeon_cmdbuf *new_cs_array[AMDGPU_CS_MAX_IBS_PER_SUBMIT];
986 unsigned idx = 0;
987
988 for (unsigned j = 0; j < cs->num_old_cs_buffers; j++)
989 new_cs_array[idx++] = &cs->old_cs_buffers[j];
990 new_cs_array[idx++] = cs_array[i];
991
992 for (unsigned j = 0; j < new_cs_count; j++) {
993 struct radeon_cmdbuf *rcs = new_cs_array[j];
994 bool needs_preamble = preamble_cs && j == 0;
995 unsigned size = 0;
996
997 if (needs_preamble)
998 size += preamble_cs->cdw;
999 size += rcs->cdw;
1000
1001 assert(size < 0xffff8);
1002
1003 while (!size || (size & 7)) {
1004 size++;
1005 pad_words++;
1006 }
1007
1008 bos[j] = ws->buffer_create(ws, 4 * size, 4096,
1009 RADEON_DOMAIN_GTT,
1010 RADEON_FLAG_CPU_ACCESS |
1011 RADEON_FLAG_NO_INTERPROCESS_SHARING |
1012 RADEON_FLAG_READ_ONLY);
1013 ptr = ws->buffer_map(bos[j]);
1014
1015 if (needs_preamble) {
1016 memcpy(ptr, preamble_cs->buf, preamble_cs->cdw * 4);
1017 ptr += preamble_cs->cdw;
1018 }
1019
1020 memcpy(ptr, rcs->buf, 4 * rcs->cdw);
1021 ptr += rcs->cdw;
1022
1023 for (unsigned k = 0; k < pad_words; ++k)
1024 *ptr++ = pad_word;
1025
1026 ibs[j].size = size;
1027 ibs[j].ib_mc_address = radv_buffer_get_va(bos[j]);
1028 }
1029
1030 number_of_ibs = new_cs_count;
1031 cnt++;
1032 } else {
1033 if (preamble_cs)
1034 size += preamble_cs->cdw;
1035
1036 while (i + cnt < cs_count && 0xffff8 - size >= radv_amdgpu_cs(cs_array[i + cnt])->base.cdw) {
1037 size += radv_amdgpu_cs(cs_array[i + cnt])->base.cdw;
1038 ++cnt;
1039 }
1040
1041 while (!size || (size & 7)) {
1042 size++;
1043 pad_words++;
1044 }
1045 assert(cnt);
1046
1047 bos[0] = ws->buffer_create(ws, 4 * size, 4096,
1048 RADEON_DOMAIN_GTT,
1049 RADEON_FLAG_CPU_ACCESS |
1050 RADEON_FLAG_NO_INTERPROCESS_SHARING |
1051 RADEON_FLAG_READ_ONLY);
1052 ptr = ws->buffer_map(bos[0]);
1053
1054 if (preamble_cs) {
1055 memcpy(ptr, preamble_cs->buf, preamble_cs->cdw * 4);
1056 ptr += preamble_cs->cdw;
1057 }
1058
1059 for (unsigned j = 0; j < cnt; ++j) {
1060 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[i + j]);
1061 memcpy(ptr, cs->base.buf, 4 * cs->base.cdw);
1062 ptr += cs->base.cdw;
1063
1064 }
1065
1066 for (unsigned j = 0; j < pad_words; ++j)
1067 *ptr++ = pad_word;
1068
1069 ibs[0].size = size;
1070 ibs[0].ib_mc_address = radv_buffer_get_va(bos[0]);
1071 }
1072
1073 r = radv_amdgpu_create_bo_list(cs0->ws, &cs_array[i], cnt,
1074 (struct radv_amdgpu_winsys_bo **)bos,
1075 number_of_ibs, preamble_cs,
1076 radv_bo_list, &bo_list);
1077 if (r) {
1078 fprintf(stderr, "amdgpu: buffer list creation failed "
1079 "for the sysmem submission (%d)\n", r);
1080 return r;
1081 }
1082
1083 memset(&request, 0, sizeof(request));
1084
1085 request.ip_type = cs0->hw_ip;
1086 request.ring = queue_idx;
1087 request.resources = bo_list;
1088 request.number_of_ibs = number_of_ibs;
1089 request.ibs = ibs;
1090 request.fence_info = radv_set_cs_fence(ctx, cs0->hw_ip, queue_idx);
1091
1092 sem_info->cs_emit_signal = (i == cs_count - cnt) ? emit_signal_sem : false;
1093 r = radv_amdgpu_cs_submit(ctx, &request, sem_info);
1094 if (r) {
1095 if (r == -ENOMEM)
1096 fprintf(stderr, "amdgpu: Not enough memory for command submission.\n");
1097 else
1098 fprintf(stderr, "amdgpu: The CS has been rejected, "
1099 "see dmesg for more information.\n");
1100 }
1101
1102 if (bo_list)
1103 amdgpu_bo_list_destroy(bo_list);
1104
1105 for (unsigned j = 0; j < number_of_ibs; j++) {
1106 ws->buffer_destroy(bos[j]);
1107 }
1108
1109 if (r)
1110 return r;
1111
1112 i += cnt;
1113 }
1114 if (fence)
1115 radv_amdgpu_request_to_fence(ctx, fence, &request);
1116
1117 radv_assign_last_submit(ctx, &request);
1118
1119 return 0;
1120 }
1121
1122 static int radv_amdgpu_winsys_cs_submit(struct radeon_winsys_ctx *_ctx,
1123 int queue_idx,
1124 struct radeon_cmdbuf **cs_array,
1125 unsigned cs_count,
1126 struct radeon_cmdbuf *initial_preamble_cs,
1127 struct radeon_cmdbuf *continue_preamble_cs,
1128 struct radv_winsys_sem_info *sem_info,
1129 const struct radv_winsys_bo_list *bo_list,
1130 bool can_patch,
1131 struct radeon_winsys_fence *_fence)
1132 {
1133 struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[0]);
1134 struct radv_amdgpu_ctx *ctx = radv_amdgpu_ctx(_ctx);
1135 int ret;
1136
1137 assert(sem_info);
1138 if (!cs->ws->use_ib_bos) {
1139 ret = radv_amdgpu_winsys_cs_submit_sysmem(_ctx, queue_idx, sem_info, bo_list, cs_array,
1140 cs_count, initial_preamble_cs, continue_preamble_cs, _fence);
1141 } else if (can_patch && cs->ws->batchchain) {
1142 ret = radv_amdgpu_winsys_cs_submit_chained(_ctx, queue_idx, sem_info, bo_list, cs_array,
1143 cs_count, initial_preamble_cs, continue_preamble_cs, _fence);
1144 } else {
1145 ret = radv_amdgpu_winsys_cs_submit_fallback(_ctx, queue_idx, sem_info, bo_list, cs_array,
1146 cs_count, initial_preamble_cs, continue_preamble_cs, _fence);
1147 }
1148
1149 radv_amdgpu_signal_sems(ctx, cs->hw_ip, queue_idx, sem_info);
1150 return ret;
1151 }
1152
1153 static void *radv_amdgpu_winsys_get_cpu_addr(void *_cs, uint64_t addr)
1154 {
1155 struct radv_amdgpu_cs *cs = (struct radv_amdgpu_cs *)_cs;
1156 void *ret = NULL;
1157
1158 if (!cs->ib_buffer)
1159 return NULL;
1160 for (unsigned i = 0; i <= cs->num_old_ib_buffers; ++i) {
1161 struct radv_amdgpu_winsys_bo *bo;
1162
1163 bo = (struct radv_amdgpu_winsys_bo*)
1164 (i == cs->num_old_ib_buffers ? cs->ib_buffer : cs->old_ib_buffers[i]);
1165 if (addr >= bo->base.va && addr - bo->base.va < bo->size) {
1166 if (amdgpu_bo_cpu_map(bo->bo, &ret) == 0)
1167 return (char *)ret + (addr - bo->base.va);
1168 }
1169 }
1170 if(cs->ws->debug_all_bos) {
1171 pthread_mutex_lock(&cs->ws->global_bo_list_lock);
1172 list_for_each_entry(struct radv_amdgpu_winsys_bo, bo,
1173 &cs->ws->global_bo_list, global_list_item) {
1174 if (addr >= bo->base.va && addr - bo->base.va < bo->size) {
1175 if (amdgpu_bo_cpu_map(bo->bo, &ret) == 0) {
1176 pthread_mutex_unlock(&cs->ws->global_bo_list_lock);
1177 return (char *)ret + (addr - bo->base.va);
1178 }
1179 }
1180 }
1181 pthread_mutex_unlock(&cs->ws->global_bo_list_lock);
1182 }
1183 return ret;
1184 }
1185
1186 static void radv_amdgpu_winsys_cs_dump(struct radeon_cmdbuf *_cs,
1187 FILE* file,
1188 const int *trace_ids, int trace_id_count)
1189 {
1190 struct radv_amdgpu_cs *cs = (struct radv_amdgpu_cs *)_cs;
1191 void *ib = cs->base.buf;
1192 int num_dw = cs->base.cdw;
1193
1194 if (cs->ws->use_ib_bos) {
1195 ib = radv_amdgpu_winsys_get_cpu_addr(cs, cs->ib.ib_mc_address);
1196 num_dw = cs->ib.size;
1197 }
1198 assert(ib);
1199 ac_parse_ib(file, ib, num_dw, trace_ids, trace_id_count, "main IB",
1200 cs->ws->info.chip_class, radv_amdgpu_winsys_get_cpu_addr, cs);
1201 }
1202
1203 static uint32_t radv_to_amdgpu_priority(enum radeon_ctx_priority radv_priority)
1204 {
1205 switch (radv_priority) {
1206 case RADEON_CTX_PRIORITY_REALTIME:
1207 return AMDGPU_CTX_PRIORITY_VERY_HIGH;
1208 case RADEON_CTX_PRIORITY_HIGH:
1209 return AMDGPU_CTX_PRIORITY_HIGH;
1210 case RADEON_CTX_PRIORITY_MEDIUM:
1211 return AMDGPU_CTX_PRIORITY_NORMAL;
1212 case RADEON_CTX_PRIORITY_LOW:
1213 return AMDGPU_CTX_PRIORITY_LOW;
1214 default:
1215 unreachable("Invalid context priority");
1216 }
1217 }
1218
1219 static struct radeon_winsys_ctx *radv_amdgpu_ctx_create(struct radeon_winsys *_ws,
1220 enum radeon_ctx_priority priority)
1221 {
1222 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1223 struct radv_amdgpu_ctx *ctx = CALLOC_STRUCT(radv_amdgpu_ctx);
1224 uint32_t amdgpu_priority = radv_to_amdgpu_priority(priority);
1225 int r;
1226
1227 if (!ctx)
1228 return NULL;
1229
1230 r = amdgpu_cs_ctx_create2(ws->dev, amdgpu_priority, &ctx->ctx);
1231 if (r) {
1232 fprintf(stderr, "amdgpu: radv_amdgpu_cs_ctx_create2 failed. (%i)\n", r);
1233 goto error_create;
1234 }
1235 ctx->ws = ws;
1236
1237 assert(AMDGPU_HW_IP_NUM * MAX_RINGS_PER_TYPE * sizeof(uint64_t) <= 4096);
1238 ctx->fence_bo = ws->base.buffer_create(&ws->base, 4096, 8,
1239 RADEON_DOMAIN_GTT,
1240 RADEON_FLAG_CPU_ACCESS|
1241 RADEON_FLAG_NO_INTERPROCESS_SHARING);
1242 if (ctx->fence_bo)
1243 ctx->fence_map = (uint64_t*)ws->base.buffer_map(ctx->fence_bo);
1244 if (ctx->fence_map)
1245 memset(ctx->fence_map, 0, 4096);
1246 return (struct radeon_winsys_ctx *)ctx;
1247 error_create:
1248 FREE(ctx);
1249 return NULL;
1250 }
1251
1252 static void radv_amdgpu_ctx_destroy(struct radeon_winsys_ctx *rwctx)
1253 {
1254 struct radv_amdgpu_ctx *ctx = (struct radv_amdgpu_ctx *)rwctx;
1255 ctx->ws->base.buffer_destroy(ctx->fence_bo);
1256 amdgpu_cs_ctx_free(ctx->ctx);
1257 FREE(ctx);
1258 }
1259
1260 static bool radv_amdgpu_ctx_wait_idle(struct radeon_winsys_ctx *rwctx,
1261 enum ring_type ring_type, int ring_index)
1262 {
1263 struct radv_amdgpu_ctx *ctx = (struct radv_amdgpu_ctx *)rwctx;
1264 int ip_type = ring_to_hw_ip(ring_type);
1265
1266 if (ctx->last_submission[ip_type][ring_index].fence.fence) {
1267 uint32_t expired;
1268 int ret = amdgpu_cs_query_fence_status(&ctx->last_submission[ip_type][ring_index].fence,
1269 1000000000ull, 0, &expired);
1270
1271 if (ret || !expired)
1272 return false;
1273 }
1274
1275 return true;
1276 }
1277
1278 static struct radeon_winsys_sem *radv_amdgpu_create_sem(struct radeon_winsys *_ws)
1279 {
1280 struct amdgpu_cs_fence *sem = CALLOC_STRUCT(amdgpu_cs_fence);
1281 if (!sem)
1282 return NULL;
1283
1284 return (struct radeon_winsys_sem *)sem;
1285 }
1286
1287 static void radv_amdgpu_destroy_sem(struct radeon_winsys_sem *_sem)
1288 {
1289 struct amdgpu_cs_fence *sem = (struct amdgpu_cs_fence *)_sem;
1290 FREE(sem);
1291 }
1292
1293 static int radv_amdgpu_signal_sems(struct radv_amdgpu_ctx *ctx,
1294 uint32_t ip_type,
1295 uint32_t ring,
1296 struct radv_winsys_sem_info *sem_info)
1297 {
1298 for (unsigned i = 0; i < sem_info->signal.sem_count; i++) {
1299 struct amdgpu_cs_fence *sem = (struct amdgpu_cs_fence *)(sem_info->signal.sem)[i];
1300
1301 if (sem->context)
1302 return -EINVAL;
1303
1304 *sem = ctx->last_submission[ip_type][ring].fence;
1305 }
1306 return 0;
1307 }
1308
1309 static struct drm_amdgpu_cs_chunk_sem *radv_amdgpu_cs_alloc_syncobj_chunk(struct radv_winsys_sem_counts *counts,
1310 struct drm_amdgpu_cs_chunk *chunk, int chunk_id)
1311 {
1312 struct drm_amdgpu_cs_chunk_sem *syncobj = malloc(sizeof(struct drm_amdgpu_cs_chunk_sem) * counts->syncobj_count);
1313 if (!syncobj)
1314 return NULL;
1315
1316 for (unsigned i = 0; i < counts->syncobj_count; i++) {
1317 struct drm_amdgpu_cs_chunk_sem *sem = &syncobj[i];
1318 sem->handle = counts->syncobj[i];
1319 }
1320
1321 chunk->chunk_id = chunk_id;
1322 chunk->length_dw = sizeof(struct drm_amdgpu_cs_chunk_sem) / 4 * counts->syncobj_count;
1323 chunk->chunk_data = (uint64_t)(uintptr_t)syncobj;
1324 return syncobj;
1325 }
1326
1327 static int radv_amdgpu_cs_submit(struct radv_amdgpu_ctx *ctx,
1328 struct amdgpu_cs_request *request,
1329 struct radv_winsys_sem_info *sem_info)
1330 {
1331 int r;
1332 int num_chunks;
1333 int size;
1334 bool user_fence;
1335 struct drm_amdgpu_cs_chunk *chunks;
1336 struct drm_amdgpu_cs_chunk_data *chunk_data;
1337 struct drm_amdgpu_cs_chunk_dep *sem_dependencies = NULL;
1338 struct drm_amdgpu_cs_chunk_sem *wait_syncobj = NULL, *signal_syncobj = NULL;
1339 int i;
1340 struct amdgpu_cs_fence *sem;
1341
1342 user_fence = (request->fence_info.handle != NULL);
1343 size = request->number_of_ibs + (user_fence ? 2 : 1) + 3;
1344
1345 chunks = alloca(sizeof(struct drm_amdgpu_cs_chunk) * size);
1346
1347 size = request->number_of_ibs + (user_fence ? 1 : 0);
1348
1349 chunk_data = alloca(sizeof(struct drm_amdgpu_cs_chunk_data) * size);
1350
1351 num_chunks = request->number_of_ibs;
1352 for (i = 0; i < request->number_of_ibs; i++) {
1353 struct amdgpu_cs_ib_info *ib;
1354 chunks[i].chunk_id = AMDGPU_CHUNK_ID_IB;
1355 chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
1356 chunks[i].chunk_data = (uint64_t)(uintptr_t)&chunk_data[i];
1357
1358 ib = &request->ibs[i];
1359
1360 chunk_data[i].ib_data._pad = 0;
1361 chunk_data[i].ib_data.va_start = ib->ib_mc_address;
1362 chunk_data[i].ib_data.ib_bytes = ib->size * 4;
1363 chunk_data[i].ib_data.ip_type = request->ip_type;
1364 chunk_data[i].ib_data.ip_instance = request->ip_instance;
1365 chunk_data[i].ib_data.ring = request->ring;
1366 chunk_data[i].ib_data.flags = ib->flags;
1367 }
1368
1369 if (user_fence) {
1370 i = num_chunks++;
1371
1372 chunks[i].chunk_id = AMDGPU_CHUNK_ID_FENCE;
1373 chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_fence) / 4;
1374 chunks[i].chunk_data = (uint64_t)(uintptr_t)&chunk_data[i];
1375
1376 amdgpu_cs_chunk_fence_info_to_data(&request->fence_info,
1377 &chunk_data[i]);
1378 }
1379
1380 if (sem_info->wait.syncobj_count && sem_info->cs_emit_wait) {
1381 wait_syncobj = radv_amdgpu_cs_alloc_syncobj_chunk(&sem_info->wait,
1382 &chunks[num_chunks],
1383 AMDGPU_CHUNK_ID_SYNCOBJ_IN);
1384 if (!wait_syncobj) {
1385 r = -ENOMEM;
1386 goto error_out;
1387 }
1388 num_chunks++;
1389
1390 if (sem_info->wait.sem_count == 0)
1391 sem_info->cs_emit_wait = false;
1392
1393 }
1394
1395 if (sem_info->wait.sem_count && sem_info->cs_emit_wait) {
1396 sem_dependencies = alloca(sizeof(struct drm_amdgpu_cs_chunk_dep) * sem_info->wait.sem_count);
1397 int sem_count = 0;
1398
1399 for (unsigned j = 0; j < sem_info->wait.sem_count; j++) {
1400 sem = (struct amdgpu_cs_fence *)sem_info->wait.sem[j];
1401 if (!sem->context)
1402 continue;
1403 struct drm_amdgpu_cs_chunk_dep *dep = &sem_dependencies[sem_count++];
1404
1405 amdgpu_cs_chunk_fence_to_dep(sem, dep);
1406
1407 sem->context = NULL;
1408 }
1409 i = num_chunks++;
1410
1411 /* dependencies chunk */
1412 chunks[i].chunk_id = AMDGPU_CHUNK_ID_DEPENDENCIES;
1413 chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_dep) / 4 * sem_count;
1414 chunks[i].chunk_data = (uint64_t)(uintptr_t)sem_dependencies;
1415
1416 sem_info->cs_emit_wait = false;
1417 }
1418
1419 if (sem_info->signal.syncobj_count && sem_info->cs_emit_signal) {
1420 signal_syncobj = radv_amdgpu_cs_alloc_syncobj_chunk(&sem_info->signal,
1421 &chunks[num_chunks],
1422 AMDGPU_CHUNK_ID_SYNCOBJ_OUT);
1423 if (!signal_syncobj) {
1424 r = -ENOMEM;
1425 goto error_out;
1426 }
1427 num_chunks++;
1428 }
1429
1430 r = amdgpu_cs_submit_raw(ctx->ws->dev,
1431 ctx->ctx,
1432 request->resources,
1433 num_chunks,
1434 chunks,
1435 &request->seq_no);
1436 error_out:
1437 free(wait_syncobj);
1438 free(signal_syncobj);
1439 return r;
1440 }
1441
1442 static int radv_amdgpu_create_syncobj(struct radeon_winsys *_ws,
1443 uint32_t *handle)
1444 {
1445 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1446 return amdgpu_cs_create_syncobj(ws->dev, handle);
1447 }
1448
1449 static void radv_amdgpu_destroy_syncobj(struct radeon_winsys *_ws,
1450 uint32_t handle)
1451 {
1452 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1453 amdgpu_cs_destroy_syncobj(ws->dev, handle);
1454 }
1455
1456 static void radv_amdgpu_reset_syncobj(struct radeon_winsys *_ws,
1457 uint32_t handle)
1458 {
1459 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1460 amdgpu_cs_syncobj_reset(ws->dev, &handle, 1);
1461 }
1462
1463 static void radv_amdgpu_signal_syncobj(struct radeon_winsys *_ws,
1464 uint32_t handle)
1465 {
1466 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1467 amdgpu_cs_syncobj_signal(ws->dev, &handle, 1);
1468 }
1469
1470 static bool radv_amdgpu_wait_syncobj(struct radeon_winsys *_ws, const uint32_t *handles,
1471 uint32_t handle_count, bool wait_all, uint64_t timeout)
1472 {
1473 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1474 uint32_t tmp;
1475
1476 /* The timeouts are signed, while vulkan timeouts are unsigned. */
1477 timeout = MIN2(timeout, INT64_MAX);
1478
1479 int ret = amdgpu_cs_syncobj_wait(ws->dev, (uint32_t*)handles, handle_count, timeout,
1480 DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT |
1481 (wait_all ? DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL : 0),
1482 &tmp);
1483 if (ret == 0) {
1484 return true;
1485 } else if (ret == -1 && errno == ETIME) {
1486 return false;
1487 } else {
1488 fprintf(stderr, "amdgpu: radv_amdgpu_wait_syncobj failed!\nerrno: %d\n", errno);
1489 return false;
1490 }
1491 }
1492
1493 static int radv_amdgpu_export_syncobj(struct radeon_winsys *_ws,
1494 uint32_t syncobj,
1495 int *fd)
1496 {
1497 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1498
1499 return amdgpu_cs_export_syncobj(ws->dev, syncobj, fd);
1500 }
1501
1502 static int radv_amdgpu_import_syncobj(struct radeon_winsys *_ws,
1503 int fd,
1504 uint32_t *syncobj)
1505 {
1506 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1507
1508 return amdgpu_cs_import_syncobj(ws->dev, fd, syncobj);
1509 }
1510
1511
1512 static int radv_amdgpu_export_syncobj_to_sync_file(struct radeon_winsys *_ws,
1513 uint32_t syncobj,
1514 int *fd)
1515 {
1516 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1517
1518 return amdgpu_cs_syncobj_export_sync_file(ws->dev, syncobj, fd);
1519 }
1520
1521 static int radv_amdgpu_import_syncobj_from_sync_file(struct radeon_winsys *_ws,
1522 uint32_t syncobj,
1523 int fd)
1524 {
1525 struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
1526
1527 return amdgpu_cs_syncobj_import_sync_file(ws->dev, syncobj, fd);
1528 }
1529
1530 void radv_amdgpu_cs_init_functions(struct radv_amdgpu_winsys *ws)
1531 {
1532 ws->base.ctx_create = radv_amdgpu_ctx_create;
1533 ws->base.ctx_destroy = radv_amdgpu_ctx_destroy;
1534 ws->base.ctx_wait_idle = radv_amdgpu_ctx_wait_idle;
1535 ws->base.cs_create = radv_amdgpu_cs_create;
1536 ws->base.cs_destroy = radv_amdgpu_cs_destroy;
1537 ws->base.cs_grow = radv_amdgpu_cs_grow;
1538 ws->base.cs_finalize = radv_amdgpu_cs_finalize;
1539 ws->base.cs_reset = radv_amdgpu_cs_reset;
1540 ws->base.cs_add_buffer = radv_amdgpu_cs_add_buffer;
1541 ws->base.cs_execute_secondary = radv_amdgpu_cs_execute_secondary;
1542 ws->base.cs_submit = radv_amdgpu_winsys_cs_submit;
1543 ws->base.cs_dump = radv_amdgpu_winsys_cs_dump;
1544 ws->base.create_fence = radv_amdgpu_create_fence;
1545 ws->base.destroy_fence = radv_amdgpu_destroy_fence;
1546 ws->base.create_sem = radv_amdgpu_create_sem;
1547 ws->base.destroy_sem = radv_amdgpu_destroy_sem;
1548 ws->base.create_syncobj = radv_amdgpu_create_syncobj;
1549 ws->base.destroy_syncobj = radv_amdgpu_destroy_syncobj;
1550 ws->base.reset_syncobj = radv_amdgpu_reset_syncobj;
1551 ws->base.signal_syncobj = radv_amdgpu_signal_syncobj;
1552 ws->base.wait_syncobj = radv_amdgpu_wait_syncobj;
1553 ws->base.export_syncobj = radv_amdgpu_export_syncobj;
1554 ws->base.import_syncobj = radv_amdgpu_import_syncobj;
1555 ws->base.export_syncobj_to_sync_file = radv_amdgpu_export_syncobj_to_sync_file;
1556 ws->base.import_syncobj_from_sync_file = radv_amdgpu_import_syncobj_from_sync_file;
1557 ws->base.fence_wait = radv_amdgpu_fence_wait;
1558 ws->base.fences_wait = radv_amdgpu_fences_wait;
1559 }