broadcom/compiler: Enable PER_QUAD for UBO and SSBO loads.
[mesa.git] / src / broadcom / compiler / nir_to_vir.c
1 /*
2 * Copyright © 2016 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <inttypes.h>
25 #include "util/format/u_format.h"
26 #include "util/u_helpers.h"
27 #include "util/u_math.h"
28 #include "util/u_memory.h"
29 #include "util/ralloc.h"
30 #include "util/hash_table.h"
31 #include "compiler/nir/nir.h"
32 #include "compiler/nir/nir_builder.h"
33 #include "common/v3d_device_info.h"
34 #include "v3d_compiler.h"
35
36 /* We don't do any address packing. */
37 #define __gen_user_data void
38 #define __gen_address_type uint32_t
39 #define __gen_address_offset(reloc) (*reloc)
40 #define __gen_emit_reloc(cl, reloc)
41 #include "cle/v3d_packet_v41_pack.h"
42
43 #define GENERAL_TMU_LOOKUP_PER_QUAD (0 << 7)
44 #define GENERAL_TMU_LOOKUP_PER_PIXEL (1 << 7)
45 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_I (0 << 0)
46 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_I (1 << 0)
47 #define GENERAL_TMU_LOOKUP_TYPE_VEC2 (2 << 0)
48 #define GENERAL_TMU_LOOKUP_TYPE_VEC3 (3 << 0)
49 #define GENERAL_TMU_LOOKUP_TYPE_VEC4 (4 << 0)
50 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_UI (5 << 0)
51 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_UI (6 << 0)
52 #define GENERAL_TMU_LOOKUP_TYPE_32BIT_UI (7 << 0)
53
54 #define V3D_TSY_SET_QUORUM 0
55 #define V3D_TSY_INC_WAITERS 1
56 #define V3D_TSY_DEC_WAITERS 2
57 #define V3D_TSY_INC_QUORUM 3
58 #define V3D_TSY_DEC_QUORUM 4
59 #define V3D_TSY_FREE_ALL 5
60 #define V3D_TSY_RELEASE 6
61 #define V3D_TSY_ACQUIRE 7
62 #define V3D_TSY_WAIT 8
63 #define V3D_TSY_WAIT_INC 9
64 #define V3D_TSY_WAIT_CHECK 10
65 #define V3D_TSY_WAIT_INC_CHECK 11
66 #define V3D_TSY_WAIT_CV 12
67 #define V3D_TSY_INC_SEMAPHORE 13
68 #define V3D_TSY_DEC_SEMAPHORE 14
69 #define V3D_TSY_SET_QUORUM_FREE_ALL 15
70
71 static void
72 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
73
74 static void
75 resize_qreg_array(struct v3d_compile *c,
76 struct qreg **regs,
77 uint32_t *size,
78 uint32_t decl_size)
79 {
80 if (*size >= decl_size)
81 return;
82
83 uint32_t old_size = *size;
84 *size = MAX2(*size * 2, decl_size);
85 *regs = reralloc(c, *regs, struct qreg, *size);
86 if (!*regs) {
87 fprintf(stderr, "Malloc failure\n");
88 abort();
89 }
90
91 for (uint32_t i = old_size; i < *size; i++)
92 (*regs)[i] = c->undef;
93 }
94
95 void
96 vir_emit_thrsw(struct v3d_compile *c)
97 {
98 if (c->threads == 1)
99 return;
100
101 /* Always thread switch after each texture operation for now.
102 *
103 * We could do better by batching a bunch of texture fetches up and
104 * then doing one thread switch and collecting all their results
105 * afterward.
106 */
107 c->last_thrsw = vir_NOP(c);
108 c->last_thrsw->qpu.sig.thrsw = true;
109 c->last_thrsw_at_top_level = !c->in_control_flow;
110
111 /* We need to lock the scoreboard before any tlb acess happens. If this
112 * thread switch comes after we have emitted a tlb load, then it means
113 * that we can't lock on the last thread switch any more.
114 */
115 if (c->emitted_tlb_load)
116 c->lock_scoreboard_on_first_thrsw = true;
117 }
118
119 uint32_t
120 v3d_get_op_for_atomic_add(nir_intrinsic_instr *instr, unsigned src)
121 {
122 if (nir_src_is_const(instr->src[src])) {
123 int64_t add_val = nir_src_as_int(instr->src[src]);
124 if (add_val == 1)
125 return V3D_TMU_OP_WRITE_AND_READ_INC;
126 else if (add_val == -1)
127 return V3D_TMU_OP_WRITE_OR_READ_DEC;
128 }
129
130 return V3D_TMU_OP_WRITE_ADD_READ_PREFETCH;
131 }
132
133 static uint32_t
134 v3d_general_tmu_op(nir_intrinsic_instr *instr)
135 {
136 switch (instr->intrinsic) {
137 case nir_intrinsic_load_ssbo:
138 case nir_intrinsic_load_ubo:
139 case nir_intrinsic_load_uniform:
140 case nir_intrinsic_load_shared:
141 case nir_intrinsic_load_scratch:
142 case nir_intrinsic_store_ssbo:
143 case nir_intrinsic_store_shared:
144 case nir_intrinsic_store_scratch:
145 return V3D_TMU_OP_REGULAR;
146 case nir_intrinsic_ssbo_atomic_add:
147 return v3d_get_op_for_atomic_add(instr, 2);
148 case nir_intrinsic_shared_atomic_add:
149 return v3d_get_op_for_atomic_add(instr, 1);
150 case nir_intrinsic_ssbo_atomic_imin:
151 case nir_intrinsic_shared_atomic_imin:
152 return V3D_TMU_OP_WRITE_SMIN;
153 case nir_intrinsic_ssbo_atomic_umin:
154 case nir_intrinsic_shared_atomic_umin:
155 return V3D_TMU_OP_WRITE_UMIN_FULL_L1_CLEAR;
156 case nir_intrinsic_ssbo_atomic_imax:
157 case nir_intrinsic_shared_atomic_imax:
158 return V3D_TMU_OP_WRITE_SMAX;
159 case nir_intrinsic_ssbo_atomic_umax:
160 case nir_intrinsic_shared_atomic_umax:
161 return V3D_TMU_OP_WRITE_UMAX;
162 case nir_intrinsic_ssbo_atomic_and:
163 case nir_intrinsic_shared_atomic_and:
164 return V3D_TMU_OP_WRITE_AND_READ_INC;
165 case nir_intrinsic_ssbo_atomic_or:
166 case nir_intrinsic_shared_atomic_or:
167 return V3D_TMU_OP_WRITE_OR_READ_DEC;
168 case nir_intrinsic_ssbo_atomic_xor:
169 case nir_intrinsic_shared_atomic_xor:
170 return V3D_TMU_OP_WRITE_XOR_READ_NOT;
171 case nir_intrinsic_ssbo_atomic_exchange:
172 case nir_intrinsic_shared_atomic_exchange:
173 return V3D_TMU_OP_WRITE_XCHG_READ_FLUSH;
174 case nir_intrinsic_ssbo_atomic_comp_swap:
175 case nir_intrinsic_shared_atomic_comp_swap:
176 return V3D_TMU_OP_WRITE_CMPXCHG_READ_FLUSH;
177 default:
178 unreachable("unknown intrinsic op");
179 }
180 }
181
182 /**
183 * Implements indirect uniform loads and SSBO accesses through the TMU general
184 * memory access interface.
185 */
186 static void
187 ntq_emit_tmu_general(struct v3d_compile *c, nir_intrinsic_instr *instr,
188 bool is_shared_or_scratch)
189 {
190 uint32_t tmu_op = v3d_general_tmu_op(instr);
191
192 /* If we were able to replace atomic_add for an inc/dec, then we
193 * need/can to do things slightly different, like not loading the
194 * amount to add/sub, as that is implicit.
195 */
196 bool atomic_add_replaced =
197 ((instr->intrinsic == nir_intrinsic_ssbo_atomic_add ||
198 instr->intrinsic == nir_intrinsic_shared_atomic_add) &&
199 (tmu_op == V3D_TMU_OP_WRITE_AND_READ_INC ||
200 tmu_op == V3D_TMU_OP_WRITE_OR_READ_DEC));
201
202 bool is_store = (instr->intrinsic == nir_intrinsic_store_ssbo ||
203 instr->intrinsic == nir_intrinsic_store_scratch ||
204 instr->intrinsic == nir_intrinsic_store_shared);
205
206 bool is_load = (instr->intrinsic == nir_intrinsic_load_uniform ||
207 instr->intrinsic == nir_intrinsic_load_ubo ||
208 instr->intrinsic == nir_intrinsic_load_ssbo ||
209 instr->intrinsic == nir_intrinsic_load_scratch ||
210 instr->intrinsic == nir_intrinsic_load_shared);
211
212 if (!is_load)
213 c->tmu_dirty_rcl = true;
214
215 bool has_index = !is_shared_or_scratch;
216
217 int offset_src;
218 if (instr->intrinsic == nir_intrinsic_load_uniform) {
219 offset_src = 0;
220 } else if (instr->intrinsic == nir_intrinsic_load_ssbo ||
221 instr->intrinsic == nir_intrinsic_load_ubo ||
222 instr->intrinsic == nir_intrinsic_load_scratch ||
223 instr->intrinsic == nir_intrinsic_load_shared ||
224 atomic_add_replaced) {
225 offset_src = 0 + has_index;
226 } else if (is_store) {
227 offset_src = 1 + has_index;
228 } else {
229 offset_src = 0 + has_index;
230 }
231
232 bool dynamic_src = !nir_src_is_const(instr->src[offset_src]);
233 uint32_t const_offset = 0;
234 if (!dynamic_src)
235 const_offset = nir_src_as_uint(instr->src[offset_src]);
236
237 struct qreg base_offset;
238 if (instr->intrinsic == nir_intrinsic_load_uniform) {
239 const_offset += nir_intrinsic_base(instr);
240 base_offset = vir_uniform(c, QUNIFORM_UBO_ADDR,
241 v3d_unit_data_create(0, const_offset));
242 const_offset = 0;
243 } else if (instr->intrinsic == nir_intrinsic_load_ubo) {
244 uint32_t index = nir_src_as_uint(instr->src[0]) + 1;
245 /* Note that QUNIFORM_UBO_ADDR takes a UBO index shifted up by
246 * 1 (0 is gallium's constant buffer 0).
247 */
248 base_offset =
249 vir_uniform(c, QUNIFORM_UBO_ADDR,
250 v3d_unit_data_create(index, const_offset));
251 const_offset = 0;
252 } else if (is_shared_or_scratch) {
253 /* Shared and scratch variables have no buffer index, and all
254 * start from a common base that we set up at the start of
255 * dispatch.
256 */
257 if (instr->intrinsic == nir_intrinsic_load_scratch ||
258 instr->intrinsic == nir_intrinsic_store_scratch) {
259 base_offset = c->spill_base;
260 } else {
261 base_offset = c->cs_shared_offset;
262 const_offset += nir_intrinsic_base(instr);
263 }
264 } else {
265 base_offset = vir_uniform(c, QUNIFORM_SSBO_OFFSET,
266 nir_src_as_uint(instr->src[is_store ?
267 1 : 0]));
268 }
269
270 struct qreg tmud = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD);
271 unsigned writemask = is_store ? nir_intrinsic_write_mask(instr) : 0;
272 uint32_t base_const_offset = const_offset;
273 int first_component = -1;
274 int last_component = -1;
275 do {
276 int tmu_writes = 1; /* address */
277
278 if (is_store) {
279 /* Find the first set of consecutive components that
280 * are enabled in the writemask and emit the TMUD
281 * instructions for them.
282 */
283 first_component = ffs(writemask) - 1;
284 last_component = first_component;
285 while (writemask & BITFIELD_BIT(last_component + 1))
286 last_component++;
287
288 assert(first_component >= 0 &&
289 first_component <= last_component &&
290 last_component < instr->num_components);
291
292 struct qreg tmud = vir_reg(QFILE_MAGIC,
293 V3D_QPU_WADDR_TMUD);
294 for (int i = first_component; i <= last_component; i++) {
295 struct qreg data =
296 ntq_get_src(c, instr->src[0], i);
297 vir_MOV_dest(c, tmud, data);
298 tmu_writes++;
299 }
300
301 /* Update the offset for the TMU write based on the
302 * the first component we are writing.
303 */
304 const_offset = base_const_offset + first_component * 4;
305
306 /* Clear these components from the writemask */
307 uint32_t written_mask =
308 BITFIELD_RANGE(first_component, tmu_writes - 1);
309 writemask &= ~written_mask;
310 } else if (!is_load && !atomic_add_replaced) {
311 struct qreg data =
312 ntq_get_src(c, instr->src[1 + has_index], 0);
313 vir_MOV_dest(c, tmud, data);
314 tmu_writes++;
315 if (tmu_op == V3D_TMU_OP_WRITE_CMPXCHG_READ_FLUSH) {
316 data = ntq_get_src(c, instr->src[2 + has_index],
317 0);
318 vir_MOV_dest(c, tmud, data);
319 tmu_writes++;
320 }
321 }
322
323 /* Make sure we won't exceed the 16-entry TMU fifo if each
324 * thread is storing at the same time.
325 */
326 while (tmu_writes > 16 / c->threads)
327 c->threads /= 2;
328
329 /* The spec says that for atomics, the TYPE field is ignored,
330 * but that doesn't seem to be the case for CMPXCHG. Just use
331 * the number of tmud writes we did to decide the type (or
332 * choose "32bit" for atomic reads, which has been fine).
333 */
334 uint32_t num_components;
335 if (is_load || atomic_add_replaced) {
336 num_components = instr->num_components;
337 } else {
338 assert(tmu_writes > 1);
339 num_components = tmu_writes - 1;
340 }
341
342 uint32_t perquad = is_load
343 ? GENERAL_TMU_LOOKUP_PER_QUAD
344 : GENERAL_TMU_LOOKUP_PER_PIXEL;
345 uint32_t config = (0xffffff00 |
346 tmu_op << 3|
347 perquad);
348 if (num_components == 1) {
349 config |= GENERAL_TMU_LOOKUP_TYPE_32BIT_UI;
350 } else {
351 config |= GENERAL_TMU_LOOKUP_TYPE_VEC2 +
352 num_components - 2;
353 }
354
355 if (vir_in_nonuniform_control_flow(c)) {
356 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
357 V3D_QPU_PF_PUSHZ);
358 }
359
360 struct qreg tmua;
361 if (config == ~0)
362 tmua = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUA);
363 else
364 tmua = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUAU);
365
366 struct qinst *tmu;
367 if (dynamic_src) {
368 struct qreg offset = base_offset;
369 if (const_offset != 0) {
370 offset = vir_ADD(c, offset,
371 vir_uniform_ui(c, const_offset));
372 }
373 struct qreg data =
374 ntq_get_src(c, instr->src[offset_src], 0);
375 tmu = vir_ADD_dest(c, tmua, offset, data);
376 } else {
377 if (const_offset != 0) {
378 tmu = vir_ADD_dest(c, tmua, base_offset,
379 vir_uniform_ui(c, const_offset));
380 } else {
381 tmu = vir_MOV_dest(c, tmua, base_offset);
382 }
383 }
384
385 if (config != ~0) {
386 tmu->uniform =
387 vir_get_uniform_index(c, QUNIFORM_CONSTANT,
388 config);
389 }
390
391 if (vir_in_nonuniform_control_flow(c))
392 vir_set_cond(tmu, V3D_QPU_COND_IFA);
393
394 vir_emit_thrsw(c);
395
396 /* Read the result, or wait for the TMU op to complete. */
397 for (int i = 0; i < nir_intrinsic_dest_components(instr); i++) {
398 ntq_store_dest(c, &instr->dest, i,
399 vir_MOV(c, vir_LDTMU(c)));
400 }
401
402 if (nir_intrinsic_dest_components(instr) == 0)
403 vir_TMUWT(c);
404 } while (is_store && writemask != 0);
405 }
406
407 static struct qreg *
408 ntq_init_ssa_def(struct v3d_compile *c, nir_ssa_def *def)
409 {
410 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
411 def->num_components);
412 _mesa_hash_table_insert(c->def_ht, def, qregs);
413 return qregs;
414 }
415
416 static bool
417 is_ld_signal(const struct v3d_qpu_sig *sig)
418 {
419 return (sig->ldunif ||
420 sig->ldunifa ||
421 sig->ldunifrf ||
422 sig->ldunifarf ||
423 sig->ldtmu ||
424 sig->ldvary ||
425 sig->ldvpm ||
426 sig->ldtlb ||
427 sig->ldtlbu);
428 }
429
430 /**
431 * This function is responsible for getting VIR results into the associated
432 * storage for a NIR instruction.
433 *
434 * If it's a NIR SSA def, then we just set the associated hash table entry to
435 * the new result.
436 *
437 * If it's a NIR reg, then we need to update the existing qreg assigned to the
438 * NIR destination with the incoming value. To do that without introducing
439 * new MOVs, we require that the incoming qreg either be a uniform, or be
440 * SSA-defined by the previous VIR instruction in the block and rewritable by
441 * this function. That lets us sneak ahead and insert the SF flag beforehand
442 * (knowing that the previous instruction doesn't depend on flags) and rewrite
443 * its destination to be the NIR reg's destination
444 */
445 void
446 ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int chan,
447 struct qreg result)
448 {
449 struct qinst *last_inst = NULL;
450 if (!list_is_empty(&c->cur_block->instructions))
451 last_inst = (struct qinst *)c->cur_block->instructions.prev;
452
453 assert((result.file == QFILE_TEMP &&
454 last_inst && last_inst == c->defs[result.index]));
455
456 if (dest->is_ssa) {
457 assert(chan < dest->ssa.num_components);
458
459 struct qreg *qregs;
460 struct hash_entry *entry =
461 _mesa_hash_table_search(c->def_ht, &dest->ssa);
462
463 if (entry)
464 qregs = entry->data;
465 else
466 qregs = ntq_init_ssa_def(c, &dest->ssa);
467
468 qregs[chan] = result;
469 } else {
470 nir_register *reg = dest->reg.reg;
471 assert(dest->reg.base_offset == 0);
472 assert(reg->num_array_elems == 0);
473 struct hash_entry *entry =
474 _mesa_hash_table_search(c->def_ht, reg);
475 struct qreg *qregs = entry->data;
476
477 /* If the previous instruction can't be predicated for
478 * the store into the nir_register, then emit a MOV
479 * that can be.
480 */
481 if (vir_in_nonuniform_control_flow(c) &&
482 is_ld_signal(&c->defs[last_inst->dst.index]->qpu.sig)) {
483 result = vir_MOV(c, result);
484 last_inst = c->defs[result.index];
485 }
486
487 /* We know they're both temps, so just rewrite index. */
488 c->defs[last_inst->dst.index] = NULL;
489 last_inst->dst.index = qregs[chan].index;
490
491 /* If we're in control flow, then make this update of the reg
492 * conditional on the execution mask.
493 */
494 if (vir_in_nonuniform_control_flow(c)) {
495 last_inst->dst.index = qregs[chan].index;
496
497 /* Set the flags to the current exec mask.
498 */
499 c->cursor = vir_before_inst(last_inst);
500 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
501 V3D_QPU_PF_PUSHZ);
502 c->cursor = vir_after_inst(last_inst);
503
504 vir_set_cond(last_inst, V3D_QPU_COND_IFA);
505 }
506 }
507 }
508
509 struct qreg
510 ntq_get_src(struct v3d_compile *c, nir_src src, int i)
511 {
512 struct hash_entry *entry;
513 if (src.is_ssa) {
514 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
515 assert(i < src.ssa->num_components);
516 } else {
517 nir_register *reg = src.reg.reg;
518 entry = _mesa_hash_table_search(c->def_ht, reg);
519 assert(reg->num_array_elems == 0);
520 assert(src.reg.base_offset == 0);
521 assert(i < reg->num_components);
522 }
523
524 struct qreg *qregs = entry->data;
525 return qregs[i];
526 }
527
528 static struct qreg
529 ntq_get_alu_src(struct v3d_compile *c, nir_alu_instr *instr,
530 unsigned src)
531 {
532 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
533 unsigned chan = ffs(instr->dest.write_mask) - 1;
534 struct qreg r = ntq_get_src(c, instr->src[src].src,
535 instr->src[src].swizzle[chan]);
536
537 assert(!instr->src[src].abs);
538 assert(!instr->src[src].negate);
539
540 return r;
541 };
542
543 static struct qreg
544 ntq_minify(struct v3d_compile *c, struct qreg size, struct qreg level)
545 {
546 return vir_MAX(c, vir_SHR(c, size, level), vir_uniform_ui(c, 1));
547 }
548
549 static void
550 ntq_emit_txs(struct v3d_compile *c, nir_tex_instr *instr)
551 {
552 unsigned unit = instr->texture_index;
553 int lod_index = nir_tex_instr_src_index(instr, nir_tex_src_lod);
554 int dest_size = nir_tex_instr_dest_size(instr);
555
556 struct qreg lod = c->undef;
557 if (lod_index != -1)
558 lod = ntq_get_src(c, instr->src[lod_index].src, 0);
559
560 for (int i = 0; i < dest_size; i++) {
561 assert(i < 3);
562 enum quniform_contents contents;
563
564 if (instr->is_array && i == dest_size - 1)
565 contents = QUNIFORM_TEXTURE_ARRAY_SIZE;
566 else
567 contents = QUNIFORM_TEXTURE_WIDTH + i;
568
569 struct qreg size = vir_uniform(c, contents, unit);
570
571 switch (instr->sampler_dim) {
572 case GLSL_SAMPLER_DIM_1D:
573 case GLSL_SAMPLER_DIM_2D:
574 case GLSL_SAMPLER_DIM_MS:
575 case GLSL_SAMPLER_DIM_3D:
576 case GLSL_SAMPLER_DIM_CUBE:
577 /* Don't minify the array size. */
578 if (!(instr->is_array && i == dest_size - 1)) {
579 size = ntq_minify(c, size, lod);
580 }
581 break;
582
583 case GLSL_SAMPLER_DIM_RECT:
584 /* There's no LOD field for rects */
585 break;
586
587 default:
588 unreachable("Bad sampler type");
589 }
590
591 ntq_store_dest(c, &instr->dest, i, size);
592 }
593 }
594
595 static void
596 ntq_emit_tex(struct v3d_compile *c, nir_tex_instr *instr)
597 {
598 unsigned unit = instr->texture_index;
599
600 /* Since each texture sampling op requires uploading uniforms to
601 * reference the texture, there's no HW support for texture size and
602 * you just upload uniforms containing the size.
603 */
604 switch (instr->op) {
605 case nir_texop_query_levels:
606 ntq_store_dest(c, &instr->dest, 0,
607 vir_uniform(c, QUNIFORM_TEXTURE_LEVELS, unit));
608 return;
609 case nir_texop_txs:
610 ntq_emit_txs(c, instr);
611 return;
612 default:
613 break;
614 }
615
616 if (c->devinfo->ver >= 40)
617 v3d40_vir_emit_tex(c, instr);
618 else
619 v3d33_vir_emit_tex(c, instr);
620 }
621
622 static struct qreg
623 ntq_fsincos(struct v3d_compile *c, struct qreg src, bool is_cos)
624 {
625 struct qreg input = vir_FMUL(c, src, vir_uniform_f(c, 1.0f / M_PI));
626 if (is_cos)
627 input = vir_FADD(c, input, vir_uniform_f(c, 0.5));
628
629 struct qreg periods = vir_FROUND(c, input);
630 struct qreg sin_output = vir_SIN(c, vir_FSUB(c, input, periods));
631 return vir_XOR(c, sin_output, vir_SHL(c,
632 vir_FTOIN(c, periods),
633 vir_uniform_ui(c, -1)));
634 }
635
636 static struct qreg
637 ntq_fsign(struct v3d_compile *c, struct qreg src)
638 {
639 struct qreg t = vir_get_temp(c);
640
641 vir_MOV_dest(c, t, vir_uniform_f(c, 0.0));
642 vir_set_pf(vir_FMOV_dest(c, vir_nop_reg(), src), V3D_QPU_PF_PUSHZ);
643 vir_MOV_cond(c, V3D_QPU_COND_IFNA, t, vir_uniform_f(c, 1.0));
644 vir_set_pf(vir_FMOV_dest(c, vir_nop_reg(), src), V3D_QPU_PF_PUSHN);
645 vir_MOV_cond(c, V3D_QPU_COND_IFA, t, vir_uniform_f(c, -1.0));
646 return vir_MOV(c, t);
647 }
648
649 static void
650 emit_fragcoord_input(struct v3d_compile *c, int attr)
651 {
652 c->inputs[attr * 4 + 0] = vir_FXCD(c);
653 c->inputs[attr * 4 + 1] = vir_FYCD(c);
654 c->inputs[attr * 4 + 2] = c->payload_z;
655 c->inputs[attr * 4 + 3] = vir_RECIP(c, c->payload_w);
656 }
657
658 static struct qreg
659 emit_fragment_varying(struct v3d_compile *c, nir_variable *var,
660 uint8_t swizzle, int array_index)
661 {
662 struct qreg r3 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R3);
663 struct qreg r5 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R5);
664
665 struct qreg vary;
666 if (c->devinfo->ver >= 41) {
667 struct qinst *ldvary = vir_add_inst(V3D_QPU_A_NOP, c->undef,
668 c->undef, c->undef);
669 ldvary->qpu.sig.ldvary = true;
670 vary = vir_emit_def(c, ldvary);
671 } else {
672 vir_NOP(c)->qpu.sig.ldvary = true;
673 vary = r3;
674 }
675
676 /* For gl_PointCoord input or distance along a line, we'll be called
677 * with no nir_variable, and we don't count toward VPM size so we
678 * don't track an input slot.
679 */
680 if (!var) {
681 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
682 }
683
684 int i = c->num_inputs++;
685 c->input_slots[i] =
686 v3d_slot_from_slot_and_component(var->data.location +
687 array_index, swizzle);
688
689 switch (var->data.interpolation) {
690 case INTERP_MODE_NONE:
691 /* If a gl_FrontColor or gl_BackColor input has no interp
692 * qualifier, then if we're using glShadeModel(GL_FLAT) it
693 * needs to be flat shaded.
694 */
695 switch (var->data.location + array_index) {
696 case VARYING_SLOT_COL0:
697 case VARYING_SLOT_COL1:
698 case VARYING_SLOT_BFC0:
699 case VARYING_SLOT_BFC1:
700 if (c->fs_key->shade_model_flat) {
701 BITSET_SET(c->flat_shade_flags, i);
702 vir_MOV_dest(c, c->undef, vary);
703 return vir_MOV(c, r5);
704 } else {
705 return vir_FADD(c, vir_FMUL(c, vary,
706 c->payload_w), r5);
707 }
708 default:
709 break;
710 }
711 /* FALLTHROUGH */
712 case INTERP_MODE_SMOOTH:
713 if (var->data.centroid) {
714 BITSET_SET(c->centroid_flags, i);
715 return vir_FADD(c, vir_FMUL(c, vary,
716 c->payload_w_centroid), r5);
717 } else {
718 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
719 }
720 case INTERP_MODE_NOPERSPECTIVE:
721 BITSET_SET(c->noperspective_flags, i);
722 return vir_FADD(c, vir_MOV(c, vary), r5);
723 case INTERP_MODE_FLAT:
724 BITSET_SET(c->flat_shade_flags, i);
725 vir_MOV_dest(c, c->undef, vary);
726 return vir_MOV(c, r5);
727 default:
728 unreachable("Bad interp mode");
729 }
730 }
731
732 static void
733 emit_fragment_input(struct v3d_compile *c, int attr, nir_variable *var,
734 int array_index)
735 {
736 for (int i = 0; i < glsl_get_vector_elements(var->type); i++) {
737 int chan = var->data.location_frac + i;
738 c->inputs[attr * 4 + chan] =
739 emit_fragment_varying(c, var, chan, array_index);
740 }
741 }
742
743 static void
744 emit_compact_fragment_input(struct v3d_compile *c, int attr, nir_variable *var,
745 int array_index)
746 {
747 /* Compact variables are scalar arrays where each set of 4 elements
748 * consumes a single location.
749 */
750 int loc_offset = array_index / 4;
751 int chan = var->data.location_frac + array_index % 4;
752 c->inputs[(attr + loc_offset) * 4 + chan] =
753 emit_fragment_varying(c, var, chan, loc_offset);
754 }
755
756 static void
757 add_output(struct v3d_compile *c,
758 uint32_t decl_offset,
759 uint8_t slot,
760 uint8_t swizzle)
761 {
762 uint32_t old_array_size = c->outputs_array_size;
763 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
764 decl_offset + 1);
765
766 if (old_array_size != c->outputs_array_size) {
767 c->output_slots = reralloc(c,
768 c->output_slots,
769 struct v3d_varying_slot,
770 c->outputs_array_size);
771 }
772
773 c->output_slots[decl_offset] =
774 v3d_slot_from_slot_and_component(slot, swizzle);
775 }
776
777 /**
778 * If compare_instr is a valid comparison instruction, emits the
779 * compare_instr's comparison and returns the sel_instr's return value based
780 * on the compare_instr's result.
781 */
782 static bool
783 ntq_emit_comparison(struct v3d_compile *c,
784 nir_alu_instr *compare_instr,
785 enum v3d_qpu_cond *out_cond)
786 {
787 struct qreg src0 = ntq_get_alu_src(c, compare_instr, 0);
788 struct qreg src1;
789 if (nir_op_infos[compare_instr->op].num_inputs > 1)
790 src1 = ntq_get_alu_src(c, compare_instr, 1);
791 bool cond_invert = false;
792 struct qreg nop = vir_nop_reg();
793
794 switch (compare_instr->op) {
795 case nir_op_feq32:
796 case nir_op_seq:
797 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
798 break;
799 case nir_op_ieq32:
800 vir_set_pf(vir_XOR_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
801 break;
802
803 case nir_op_fne32:
804 case nir_op_sne:
805 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
806 cond_invert = true;
807 break;
808 case nir_op_ine32:
809 vir_set_pf(vir_XOR_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
810 cond_invert = true;
811 break;
812
813 case nir_op_fge32:
814 case nir_op_sge:
815 vir_set_pf(vir_FCMP_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
816 break;
817 case nir_op_ige32:
818 vir_set_pf(vir_MIN_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
819 cond_invert = true;
820 break;
821 case nir_op_uge32:
822 vir_set_pf(vir_SUB_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHC);
823 cond_invert = true;
824 break;
825
826 case nir_op_slt:
827 case nir_op_flt32:
828 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHN);
829 break;
830 case nir_op_ilt32:
831 vir_set_pf(vir_MIN_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
832 break;
833 case nir_op_ult32:
834 vir_set_pf(vir_SUB_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHC);
835 break;
836
837 case nir_op_i2b32:
838 vir_set_pf(vir_MOV_dest(c, nop, src0), V3D_QPU_PF_PUSHZ);
839 cond_invert = true;
840 break;
841
842 case nir_op_f2b32:
843 vir_set_pf(vir_FMOV_dest(c, nop, src0), V3D_QPU_PF_PUSHZ);
844 cond_invert = true;
845 break;
846
847 default:
848 return false;
849 }
850
851 *out_cond = cond_invert ? V3D_QPU_COND_IFNA : V3D_QPU_COND_IFA;
852
853 return true;
854 }
855
856 /* Finds an ALU instruction that generates our src value that could
857 * (potentially) be greedily emitted in the consuming instruction.
858 */
859 static struct nir_alu_instr *
860 ntq_get_alu_parent(nir_src src)
861 {
862 if (!src.is_ssa || src.ssa->parent_instr->type != nir_instr_type_alu)
863 return NULL;
864 nir_alu_instr *instr = nir_instr_as_alu(src.ssa->parent_instr);
865 if (!instr)
866 return NULL;
867
868 /* If the ALU instr's srcs are non-SSA, then we would have to avoid
869 * moving emission of the ALU instr down past another write of the
870 * src.
871 */
872 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
873 if (!instr->src[i].src.is_ssa)
874 return NULL;
875 }
876
877 return instr;
878 }
879
880 /* Turns a NIR bool into a condition code to predicate on. */
881 static enum v3d_qpu_cond
882 ntq_emit_bool_to_cond(struct v3d_compile *c, nir_src src)
883 {
884 nir_alu_instr *compare = ntq_get_alu_parent(src);
885 if (!compare)
886 goto out;
887
888 enum v3d_qpu_cond cond;
889 if (ntq_emit_comparison(c, compare, &cond))
890 return cond;
891
892 out:
893 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), ntq_get_src(c, src, 0)),
894 V3D_QPU_PF_PUSHZ);
895 return V3D_QPU_COND_IFNA;
896 }
897
898 static void
899 ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr)
900 {
901 /* This should always be lowered to ALU operations for V3D. */
902 assert(!instr->dest.saturate);
903
904 /* Vectors are special in that they have non-scalarized writemasks,
905 * and just take the first swizzle channel for each argument in order
906 * into each writemask channel.
907 */
908 if (instr->op == nir_op_vec2 ||
909 instr->op == nir_op_vec3 ||
910 instr->op == nir_op_vec4) {
911 struct qreg srcs[4];
912 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
913 srcs[i] = ntq_get_src(c, instr->src[i].src,
914 instr->src[i].swizzle[0]);
915 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
916 ntq_store_dest(c, &instr->dest.dest, i,
917 vir_MOV(c, srcs[i]));
918 return;
919 }
920
921 /* General case: We can just grab the one used channel per src. */
922 struct qreg src[nir_op_infos[instr->op].num_inputs];
923 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
924 src[i] = ntq_get_alu_src(c, instr, i);
925 }
926
927 struct qreg result;
928
929 switch (instr->op) {
930 case nir_op_mov:
931 result = vir_MOV(c, src[0]);
932 break;
933
934 case nir_op_fneg:
935 result = vir_XOR(c, src[0], vir_uniform_ui(c, 1 << 31));
936 break;
937 case nir_op_ineg:
938 result = vir_NEG(c, src[0]);
939 break;
940
941 case nir_op_fmul:
942 result = vir_FMUL(c, src[0], src[1]);
943 break;
944 case nir_op_fadd:
945 result = vir_FADD(c, src[0], src[1]);
946 break;
947 case nir_op_fsub:
948 result = vir_FSUB(c, src[0], src[1]);
949 break;
950 case nir_op_fmin:
951 result = vir_FMIN(c, src[0], src[1]);
952 break;
953 case nir_op_fmax:
954 result = vir_FMAX(c, src[0], src[1]);
955 break;
956
957 case nir_op_f2i32: {
958 nir_alu_instr *src0_alu = ntq_get_alu_parent(instr->src[0].src);
959 if (src0_alu && src0_alu->op == nir_op_fround_even) {
960 result = vir_FTOIN(c, ntq_get_alu_src(c, src0_alu, 0));
961 } else {
962 result = vir_FTOIZ(c, src[0]);
963 }
964 break;
965 }
966
967 case nir_op_f2u32:
968 result = vir_FTOUZ(c, src[0]);
969 break;
970 case nir_op_i2f32:
971 result = vir_ITOF(c, src[0]);
972 break;
973 case nir_op_u2f32:
974 result = vir_UTOF(c, src[0]);
975 break;
976 case nir_op_b2f32:
977 result = vir_AND(c, src[0], vir_uniform_f(c, 1.0));
978 break;
979 case nir_op_b2i32:
980 result = vir_AND(c, src[0], vir_uniform_ui(c, 1));
981 break;
982
983 case nir_op_iadd:
984 result = vir_ADD(c, src[0], src[1]);
985 break;
986 case nir_op_ushr:
987 result = vir_SHR(c, src[0], src[1]);
988 break;
989 case nir_op_isub:
990 result = vir_SUB(c, src[0], src[1]);
991 break;
992 case nir_op_ishr:
993 result = vir_ASR(c, src[0], src[1]);
994 break;
995 case nir_op_ishl:
996 result = vir_SHL(c, src[0], src[1]);
997 break;
998 case nir_op_imin:
999 result = vir_MIN(c, src[0], src[1]);
1000 break;
1001 case nir_op_umin:
1002 result = vir_UMIN(c, src[0], src[1]);
1003 break;
1004 case nir_op_imax:
1005 result = vir_MAX(c, src[0], src[1]);
1006 break;
1007 case nir_op_umax:
1008 result = vir_UMAX(c, src[0], src[1]);
1009 break;
1010 case nir_op_iand:
1011 result = vir_AND(c, src[0], src[1]);
1012 break;
1013 case nir_op_ior:
1014 result = vir_OR(c, src[0], src[1]);
1015 break;
1016 case nir_op_ixor:
1017 result = vir_XOR(c, src[0], src[1]);
1018 break;
1019 case nir_op_inot:
1020 result = vir_NOT(c, src[0]);
1021 break;
1022
1023 case nir_op_ufind_msb:
1024 result = vir_SUB(c, vir_uniform_ui(c, 31), vir_CLZ(c, src[0]));
1025 break;
1026
1027 case nir_op_imul:
1028 result = vir_UMUL(c, src[0], src[1]);
1029 break;
1030
1031 case nir_op_seq:
1032 case nir_op_sne:
1033 case nir_op_sge:
1034 case nir_op_slt: {
1035 enum v3d_qpu_cond cond;
1036 ASSERTED bool ok = ntq_emit_comparison(c, instr, &cond);
1037 assert(ok);
1038 result = vir_MOV(c, vir_SEL(c, cond,
1039 vir_uniform_f(c, 1.0),
1040 vir_uniform_f(c, 0.0)));
1041 break;
1042 }
1043
1044 case nir_op_i2b32:
1045 case nir_op_f2b32:
1046 case nir_op_feq32:
1047 case nir_op_fne32:
1048 case nir_op_fge32:
1049 case nir_op_flt32:
1050 case nir_op_ieq32:
1051 case nir_op_ine32:
1052 case nir_op_ige32:
1053 case nir_op_uge32:
1054 case nir_op_ilt32:
1055 case nir_op_ult32: {
1056 enum v3d_qpu_cond cond;
1057 ASSERTED bool ok = ntq_emit_comparison(c, instr, &cond);
1058 assert(ok);
1059 result = vir_MOV(c, vir_SEL(c, cond,
1060 vir_uniform_ui(c, ~0),
1061 vir_uniform_ui(c, 0)));
1062 break;
1063 }
1064
1065 case nir_op_b32csel:
1066 result = vir_MOV(c,
1067 vir_SEL(c,
1068 ntq_emit_bool_to_cond(c, instr->src[0].src),
1069 src[1], src[2]));
1070 break;
1071
1072 case nir_op_fcsel:
1073 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), src[0]),
1074 V3D_QPU_PF_PUSHZ);
1075 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
1076 src[1], src[2]));
1077 break;
1078
1079 case nir_op_frcp:
1080 result = vir_RECIP(c, src[0]);
1081 break;
1082 case nir_op_frsq:
1083 result = vir_RSQRT(c, src[0]);
1084 break;
1085 case nir_op_fexp2:
1086 result = vir_EXP(c, src[0]);
1087 break;
1088 case nir_op_flog2:
1089 result = vir_LOG(c, src[0]);
1090 break;
1091
1092 case nir_op_fceil:
1093 result = vir_FCEIL(c, src[0]);
1094 break;
1095 case nir_op_ffloor:
1096 result = vir_FFLOOR(c, src[0]);
1097 break;
1098 case nir_op_fround_even:
1099 result = vir_FROUND(c, src[0]);
1100 break;
1101 case nir_op_ftrunc:
1102 result = vir_FTRUNC(c, src[0]);
1103 break;
1104
1105 case nir_op_fsin:
1106 result = ntq_fsincos(c, src[0], false);
1107 break;
1108 case nir_op_fcos:
1109 result = ntq_fsincos(c, src[0], true);
1110 break;
1111
1112 case nir_op_fsign:
1113 result = ntq_fsign(c, src[0]);
1114 break;
1115
1116 case nir_op_fabs: {
1117 result = vir_FMOV(c, src[0]);
1118 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_ABS);
1119 break;
1120 }
1121
1122 case nir_op_iabs:
1123 result = vir_MAX(c, src[0], vir_NEG(c, src[0]));
1124 break;
1125
1126 case nir_op_fddx:
1127 case nir_op_fddx_coarse:
1128 case nir_op_fddx_fine:
1129 result = vir_FDX(c, src[0]);
1130 break;
1131
1132 case nir_op_fddy:
1133 case nir_op_fddy_coarse:
1134 case nir_op_fddy_fine:
1135 result = vir_FDY(c, src[0]);
1136 break;
1137
1138 case nir_op_uadd_carry:
1139 vir_set_pf(vir_ADD_dest(c, vir_nop_reg(), src[0], src[1]),
1140 V3D_QPU_PF_PUSHC);
1141 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFA,
1142 vir_uniform_ui(c, ~0),
1143 vir_uniform_ui(c, 0)));
1144 break;
1145
1146 case nir_op_pack_half_2x16_split:
1147 result = vir_VFPACK(c, src[0], src[1]);
1148 break;
1149
1150 case nir_op_unpack_half_2x16_split_x:
1151 result = vir_FMOV(c, src[0]);
1152 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_L);
1153 break;
1154
1155 case nir_op_unpack_half_2x16_split_y:
1156 result = vir_FMOV(c, src[0]);
1157 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_H);
1158 break;
1159
1160 default:
1161 fprintf(stderr, "unknown NIR ALU inst: ");
1162 nir_print_instr(&instr->instr, stderr);
1163 fprintf(stderr, "\n");
1164 abort();
1165 }
1166
1167 /* We have a scalar result, so the instruction should only have a
1168 * single channel written to.
1169 */
1170 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
1171 ntq_store_dest(c, &instr->dest.dest,
1172 ffs(instr->dest.write_mask) - 1, result);
1173 }
1174
1175 /* Each TLB read/write setup (a render target or depth buffer) takes an 8-bit
1176 * specifier. They come from a register that's preloaded with 0xffffffff
1177 * (0xff gets you normal vec4 f16 RT0 writes), and when one is neaded the low
1178 * 8 bits are shifted off the bottom and 0xff shifted in from the top.
1179 */
1180 #define TLB_TYPE_F16_COLOR (3 << 6)
1181 #define TLB_TYPE_I32_COLOR (1 << 6)
1182 #define TLB_TYPE_F32_COLOR (0 << 6)
1183 #define TLB_RENDER_TARGET_SHIFT 3 /* Reversed! 7 = RT 0, 0 = RT 7. */
1184 #define TLB_SAMPLE_MODE_PER_SAMPLE (0 << 2)
1185 #define TLB_SAMPLE_MODE_PER_PIXEL (1 << 2)
1186 #define TLB_F16_SWAP_HI_LO (1 << 1)
1187 #define TLB_VEC_SIZE_4_F16 (1 << 0)
1188 #define TLB_VEC_SIZE_2_F16 (0 << 0)
1189 #define TLB_VEC_SIZE_MINUS_1_SHIFT 0
1190
1191 /* Triggers Z/Stencil testing, used when the shader state's "FS modifies Z"
1192 * flag is set.
1193 */
1194 #define TLB_TYPE_DEPTH ((2 << 6) | (0 << 4))
1195 #define TLB_DEPTH_TYPE_INVARIANT (0 << 2) /* Unmodified sideband input used */
1196 #define TLB_DEPTH_TYPE_PER_PIXEL (1 << 2) /* QPU result used */
1197 #define TLB_V42_DEPTH_TYPE_INVARIANT (0 << 3) /* Unmodified sideband input used */
1198 #define TLB_V42_DEPTH_TYPE_PER_PIXEL (1 << 3) /* QPU result used */
1199
1200 /* Stencil is a single 32-bit write. */
1201 #define TLB_TYPE_STENCIL_ALPHA ((2 << 6) | (1 << 4))
1202
1203 static void
1204 vir_emit_tlb_color_write(struct v3d_compile *c, unsigned rt)
1205 {
1206 if (!(c->fs_key->cbufs & (1 << rt)) || !c->output_color_var[rt])
1207 return;
1208
1209 struct qreg tlb_reg = vir_magic_reg(V3D_QPU_WADDR_TLB);
1210 struct qreg tlbu_reg = vir_magic_reg(V3D_QPU_WADDR_TLBU);
1211
1212 nir_variable *var = c->output_color_var[rt];
1213 int num_components = glsl_get_vector_elements(var->type);
1214 uint32_t conf = 0xffffff00;
1215 struct qinst *inst;
1216
1217 conf |= c->msaa_per_sample_output ? TLB_SAMPLE_MODE_PER_SAMPLE :
1218 TLB_SAMPLE_MODE_PER_PIXEL;
1219 conf |= (7 - rt) << TLB_RENDER_TARGET_SHIFT;
1220
1221 if (c->fs_key->swap_color_rb & (1 << rt))
1222 num_components = MAX2(num_components, 3);
1223 assert(num_components != 0);
1224
1225 enum glsl_base_type type = glsl_get_base_type(var->type);
1226 bool is_int_format = type == GLSL_TYPE_INT || type == GLSL_TYPE_UINT;
1227 bool is_32b_tlb_format = is_int_format ||
1228 (c->fs_key->f32_color_rb & (1 << rt));
1229
1230 if (is_int_format) {
1231 /* The F32 vs I32 distinction was dropped in 4.2. */
1232 if (c->devinfo->ver < 42)
1233 conf |= TLB_TYPE_I32_COLOR;
1234 else
1235 conf |= TLB_TYPE_F32_COLOR;
1236 conf |= ((num_components - 1) << TLB_VEC_SIZE_MINUS_1_SHIFT);
1237 } else {
1238 if (c->fs_key->f32_color_rb & (1 << rt)) {
1239 conf |= TLB_TYPE_F32_COLOR;
1240 conf |= ((num_components - 1) <<
1241 TLB_VEC_SIZE_MINUS_1_SHIFT);
1242 } else {
1243 conf |= TLB_TYPE_F16_COLOR;
1244 conf |= TLB_F16_SWAP_HI_LO;
1245 if (num_components >= 3)
1246 conf |= TLB_VEC_SIZE_4_F16;
1247 else
1248 conf |= TLB_VEC_SIZE_2_F16;
1249 }
1250 }
1251
1252 int num_samples = c->msaa_per_sample_output ? V3D_MAX_SAMPLES : 1;
1253 for (int i = 0; i < num_samples; i++) {
1254 struct qreg *color = c->msaa_per_sample_output ?
1255 &c->sample_colors[(rt * V3D_MAX_SAMPLES + i) * 4] :
1256 &c->outputs[var->data.driver_location * 4];
1257
1258 struct qreg r = color[0];
1259 struct qreg g = color[1];
1260 struct qreg b = color[2];
1261 struct qreg a = color[3];
1262
1263 if (c->fs_key->swap_color_rb & (1 << rt)) {
1264 r = color[2];
1265 b = color[0];
1266 }
1267
1268 if (c->fs_key->sample_alpha_to_one)
1269 a = vir_uniform_f(c, 1.0);
1270
1271 if (is_32b_tlb_format) {
1272 if (i == 0) {
1273 inst = vir_MOV_dest(c, tlbu_reg, r);
1274 inst->uniform =
1275 vir_get_uniform_index(c,
1276 QUNIFORM_CONSTANT,
1277 conf);
1278 } else {
1279 inst = vir_MOV_dest(c, tlb_reg, r);
1280 }
1281
1282 if (num_components >= 2)
1283 vir_MOV_dest(c, tlb_reg, g);
1284 if (num_components >= 3)
1285 vir_MOV_dest(c, tlb_reg, b);
1286 if (num_components >= 4)
1287 vir_MOV_dest(c, tlb_reg, a);
1288 } else {
1289 inst = vir_VFPACK_dest(c, tlb_reg, r, g);
1290 if (conf != ~0 && i == 0) {
1291 inst->dst = tlbu_reg;
1292 inst->uniform =
1293 vir_get_uniform_index(c,
1294 QUNIFORM_CONSTANT,
1295 conf);
1296 }
1297
1298 if (num_components >= 3)
1299 inst = vir_VFPACK_dest(c, tlb_reg, b, a);
1300 }
1301 }
1302 }
1303
1304 static void
1305 emit_frag_end(struct v3d_compile *c)
1306 {
1307 /* XXX
1308 if (c->output_sample_mask_index != -1) {
1309 vir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
1310 }
1311 */
1312
1313 bool has_any_tlb_color_write = false;
1314 for (int rt = 0; rt < V3D_MAX_DRAW_BUFFERS; rt++) {
1315 if (c->fs_key->cbufs & (1 << rt) && c->output_color_var[rt])
1316 has_any_tlb_color_write = true;
1317 }
1318
1319 if (c->fs_key->sample_alpha_to_coverage && c->output_color_var[0]) {
1320 struct nir_variable *var = c->output_color_var[0];
1321 struct qreg *color = &c->outputs[var->data.driver_location * 4];
1322
1323 vir_SETMSF_dest(c, vir_nop_reg(),
1324 vir_AND(c,
1325 vir_MSF(c),
1326 vir_FTOC(c, color[3])));
1327 }
1328
1329 struct qreg tlbu_reg = vir_magic_reg(V3D_QPU_WADDR_TLBU);
1330 if (c->output_position_index != -1) {
1331 struct qinst *inst = vir_MOV_dest(c, tlbu_reg,
1332 c->outputs[c->output_position_index]);
1333 uint8_t tlb_specifier = TLB_TYPE_DEPTH;
1334
1335 if (c->devinfo->ver >= 42) {
1336 tlb_specifier |= (TLB_V42_DEPTH_TYPE_PER_PIXEL |
1337 TLB_SAMPLE_MODE_PER_PIXEL);
1338 } else
1339 tlb_specifier |= TLB_DEPTH_TYPE_PER_PIXEL;
1340
1341 inst->uniform = vir_get_uniform_index(c, QUNIFORM_CONSTANT,
1342 tlb_specifier |
1343 0xffffff00);
1344 c->writes_z = true;
1345 } else if (c->s->info.fs.uses_discard ||
1346 !c->s->info.fs.early_fragment_tests ||
1347 c->fs_key->sample_alpha_to_coverage ||
1348 !has_any_tlb_color_write) {
1349 /* Emit passthrough Z if it needed to be delayed until shader
1350 * end due to potential discards.
1351 *
1352 * Since (single-threaded) fragment shaders always need a TLB
1353 * write, emit passthrouh Z if we didn't have any color
1354 * buffers and flag us as potentially discarding, so that we
1355 * can use Z as the TLB write.
1356 */
1357 c->s->info.fs.uses_discard = true;
1358
1359 struct qinst *inst = vir_MOV_dest(c, tlbu_reg,
1360 vir_nop_reg());
1361 uint8_t tlb_specifier = TLB_TYPE_DEPTH;
1362
1363 if (c->devinfo->ver >= 42) {
1364 /* The spec says the PER_PIXEL flag is ignored for
1365 * invariant writes, but the simulator demands it.
1366 */
1367 tlb_specifier |= (TLB_V42_DEPTH_TYPE_INVARIANT |
1368 TLB_SAMPLE_MODE_PER_PIXEL);
1369 } else {
1370 tlb_specifier |= TLB_DEPTH_TYPE_INVARIANT;
1371 }
1372
1373 inst->uniform = vir_get_uniform_index(c,
1374 QUNIFORM_CONSTANT,
1375 tlb_specifier |
1376 0xffffff00);
1377 c->writes_z = true;
1378 }
1379
1380 /* XXX: Performance improvement: Merge Z write and color writes TLB
1381 * uniform setup
1382 */
1383 for (int rt = 0; rt < V3D_MAX_DRAW_BUFFERS; rt++)
1384 vir_emit_tlb_color_write(c, rt);
1385 }
1386
1387 static inline void
1388 vir_VPM_WRITE_indirect(struct v3d_compile *c,
1389 struct qreg val,
1390 struct qreg vpm_index)
1391 {
1392 assert(c->devinfo->ver >= 40);
1393 vir_STVPMV(c, vpm_index, val);
1394 }
1395
1396 static void
1397 vir_VPM_WRITE(struct v3d_compile *c, struct qreg val, uint32_t vpm_index)
1398 {
1399 if (c->devinfo->ver >= 40) {
1400 vir_VPM_WRITE_indirect(c, val, vir_uniform_ui(c, vpm_index));
1401 } else {
1402 /* XXX: v3d33_vir_vpm_write_setup(c); */
1403 vir_MOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_VPM), val);
1404 }
1405 }
1406
1407 static void
1408 emit_vert_end(struct v3d_compile *c)
1409 {
1410 /* GFXH-1684: VPM writes need to be complete by the end of the shader.
1411 */
1412 if (c->devinfo->ver >= 40 && c->devinfo->ver <= 42)
1413 vir_VPMWT(c);
1414 }
1415
1416 static void
1417 emit_geom_end(struct v3d_compile *c)
1418 {
1419 /* GFXH-1684: VPM writes need to be complete by the end of the shader.
1420 */
1421 if (c->devinfo->ver >= 40 && c->devinfo->ver <= 42)
1422 vir_VPMWT(c);
1423 }
1424
1425 void
1426 v3d_optimize_nir(struct nir_shader *s)
1427 {
1428 bool progress;
1429 unsigned lower_flrp =
1430 (s->options->lower_flrp16 ? 16 : 0) |
1431 (s->options->lower_flrp32 ? 32 : 0) |
1432 (s->options->lower_flrp64 ? 64 : 0);
1433
1434 do {
1435 progress = false;
1436
1437 NIR_PASS_V(s, nir_lower_vars_to_ssa);
1438 NIR_PASS(progress, s, nir_lower_alu_to_scalar, NULL, NULL);
1439 NIR_PASS(progress, s, nir_lower_phis_to_scalar);
1440 NIR_PASS(progress, s, nir_copy_prop);
1441 NIR_PASS(progress, s, nir_opt_remove_phis);
1442 NIR_PASS(progress, s, nir_opt_dce);
1443 NIR_PASS(progress, s, nir_opt_dead_cf);
1444 NIR_PASS(progress, s, nir_opt_cse);
1445 NIR_PASS(progress, s, nir_opt_peephole_select, 8, true, true);
1446 NIR_PASS(progress, s, nir_opt_algebraic);
1447 NIR_PASS(progress, s, nir_opt_constant_folding);
1448
1449 if (lower_flrp != 0) {
1450 bool lower_flrp_progress = false;
1451
1452 NIR_PASS(lower_flrp_progress, s, nir_lower_flrp,
1453 lower_flrp,
1454 false /* always_precise */,
1455 s->options->lower_ffma);
1456 if (lower_flrp_progress) {
1457 NIR_PASS(progress, s, nir_opt_constant_folding);
1458 progress = true;
1459 }
1460
1461 /* Nothing should rematerialize any flrps, so we only
1462 * need to do this lowering once.
1463 */
1464 lower_flrp = 0;
1465 }
1466
1467 NIR_PASS(progress, s, nir_opt_undef);
1468 } while (progress);
1469
1470 NIR_PASS(progress, s, nir_opt_move, nir_move_load_ubo);
1471 }
1472
1473 static int
1474 driver_location_compare(const void *in_a, const void *in_b)
1475 {
1476 const nir_variable *const *a = in_a;
1477 const nir_variable *const *b = in_b;
1478
1479 if ((*a)->data.driver_location == (*b)->data.driver_location)
1480 return (*a)->data.location_frac - (*b)->data.location_frac;
1481
1482 return (*a)->data.driver_location - (*b)->data.driver_location;
1483 }
1484
1485 static struct qreg
1486 ntq_emit_vpm_read(struct v3d_compile *c,
1487 uint32_t *num_components_queued,
1488 uint32_t *remaining,
1489 uint32_t vpm_index)
1490 {
1491 struct qreg vpm = vir_reg(QFILE_VPM, vpm_index);
1492
1493 if (c->devinfo->ver >= 40 ) {
1494 return vir_LDVPMV_IN(c,
1495 vir_uniform_ui(c,
1496 (*num_components_queued)++));
1497 }
1498
1499 if (*num_components_queued != 0) {
1500 (*num_components_queued)--;
1501 return vir_MOV(c, vpm);
1502 }
1503
1504 uint32_t num_components = MIN2(*remaining, 32);
1505
1506 v3d33_vir_vpm_read_setup(c, num_components);
1507
1508 *num_components_queued = num_components - 1;
1509 *remaining -= num_components;
1510
1511 return vir_MOV(c, vpm);
1512 }
1513
1514 static void
1515 ntq_setup_vs_inputs(struct v3d_compile *c)
1516 {
1517 /* Figure out how many components of each vertex attribute the shader
1518 * uses. Each variable should have been split to individual
1519 * components and unused ones DCEed. The vertex fetcher will load
1520 * from the start of the attribute to the number of components we
1521 * declare we need in c->vattr_sizes[].
1522 */
1523 nir_foreach_shader_in_variable(var, c->s) {
1524 /* No VS attribute array support. */
1525 assert(MAX2(glsl_get_length(var->type), 1) == 1);
1526
1527 unsigned loc = var->data.driver_location;
1528 int start_component = var->data.location_frac;
1529 int num_components = glsl_get_components(var->type);
1530
1531 c->vattr_sizes[loc] = MAX2(c->vattr_sizes[loc],
1532 start_component + num_components);
1533 }
1534
1535 unsigned num_components = 0;
1536 uint32_t vpm_components_queued = 0;
1537 bool uses_iid = c->s->info.system_values_read &
1538 (1ull << SYSTEM_VALUE_INSTANCE_ID);
1539 bool uses_vid = c->s->info.system_values_read &
1540 (1ull << SYSTEM_VALUE_VERTEX_ID);
1541 num_components += uses_iid;
1542 num_components += uses_vid;
1543
1544 for (int i = 0; i < ARRAY_SIZE(c->vattr_sizes); i++)
1545 num_components += c->vattr_sizes[i];
1546
1547 if (uses_iid) {
1548 c->iid = ntq_emit_vpm_read(c, &vpm_components_queued,
1549 &num_components, ~0);
1550 }
1551
1552 if (uses_vid) {
1553 c->vid = ntq_emit_vpm_read(c, &vpm_components_queued,
1554 &num_components, ~0);
1555 }
1556
1557 /* The actual loads will happen directly in nir_intrinsic_load_input
1558 * on newer versions.
1559 */
1560 if (c->devinfo->ver >= 40)
1561 return;
1562
1563 for (int loc = 0; loc < ARRAY_SIZE(c->vattr_sizes); loc++) {
1564 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1565 (loc + 1) * 4);
1566
1567 for (int i = 0; i < c->vattr_sizes[loc]; i++) {
1568 c->inputs[loc * 4 + i] =
1569 ntq_emit_vpm_read(c,
1570 &vpm_components_queued,
1571 &num_components,
1572 loc * 4 + i);
1573
1574 }
1575 }
1576
1577 if (c->devinfo->ver >= 40) {
1578 assert(vpm_components_queued == num_components);
1579 } else {
1580 assert(vpm_components_queued == 0);
1581 assert(num_components == 0);
1582 }
1583 }
1584
1585 static bool
1586 program_reads_point_coord(struct v3d_compile *c)
1587 {
1588 nir_foreach_shader_in_variable(var, c->s) {
1589 if (util_varying_is_point_coord(var->data.location,
1590 c->fs_key->point_sprite_mask)) {
1591 return true;
1592 }
1593 }
1594
1595 return false;
1596 }
1597
1598 static void
1599 get_sorted_input_variables(struct v3d_compile *c,
1600 unsigned *num_entries,
1601 nir_variable ***vars)
1602 {
1603 *num_entries = 0;
1604 nir_foreach_shader_in_variable(var, c->s)
1605 (*num_entries)++;
1606
1607 *vars = ralloc_array(c, nir_variable *, *num_entries);
1608
1609 unsigned i = 0;
1610 nir_foreach_shader_in_variable(var, c->s)
1611 (*vars)[i++] = var;
1612
1613 /* Sort the variables so that we emit the input setup in
1614 * driver_location order. This is required for VPM reads, whose data
1615 * is fetched into the VPM in driver_location (TGSI register index)
1616 * order.
1617 */
1618 qsort(*vars, *num_entries, sizeof(**vars), driver_location_compare);
1619 }
1620
1621 static void
1622 ntq_setup_gs_inputs(struct v3d_compile *c)
1623 {
1624 nir_variable **vars;
1625 unsigned num_entries;
1626 get_sorted_input_variables(c, &num_entries, &vars);
1627
1628 for (unsigned i = 0; i < num_entries; i++) {
1629 nir_variable *var = vars[i];
1630
1631 /* All GS inputs are arrays with as many entries as vertices
1632 * in the input primitive, but here we only care about the
1633 * per-vertex input type.
1634 */
1635 const struct glsl_type *type = glsl_without_array(var->type);
1636 unsigned array_len = MAX2(glsl_get_length(type), 1);
1637 unsigned loc = var->data.driver_location;
1638
1639 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1640 (loc + array_len) * 4);
1641
1642 for (unsigned j = 0; j < array_len; j++) {
1643 unsigned num_elements = glsl_get_vector_elements(type);
1644 for (unsigned k = 0; k < num_elements; k++) {
1645 unsigned chan = var->data.location_frac + k;
1646 unsigned input_idx = c->num_inputs++;
1647 struct v3d_varying_slot slot =
1648 v3d_slot_from_slot_and_component(var->data.location + j, chan);
1649 c->input_slots[input_idx] = slot;
1650 }
1651 }
1652 }
1653 }
1654
1655
1656 static void
1657 ntq_setup_fs_inputs(struct v3d_compile *c)
1658 {
1659 nir_variable **vars;
1660 unsigned num_entries;
1661 get_sorted_input_variables(c, &num_entries, &vars);
1662
1663 for (unsigned i = 0; i < num_entries; i++) {
1664 nir_variable *var = vars[i];
1665 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1666 unsigned loc = var->data.driver_location;
1667
1668 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1669 (loc + array_len) * 4);
1670
1671 if (var->data.location == VARYING_SLOT_POS) {
1672 emit_fragcoord_input(c, loc);
1673 } else if (util_varying_is_point_coord(var->data.location,
1674 c->fs_key->point_sprite_mask)) {
1675 c->inputs[loc * 4 + 0] = c->point_x;
1676 c->inputs[loc * 4 + 1] = c->point_y;
1677 } else if (var->data.compact) {
1678 for (int j = 0; j < array_len; j++)
1679 emit_compact_fragment_input(c, loc, var, j);
1680 } else {
1681 for (int j = 0; j < array_len; j++)
1682 emit_fragment_input(c, loc + j, var, j);
1683 }
1684 }
1685 }
1686
1687 static void
1688 ntq_setup_outputs(struct v3d_compile *c)
1689 {
1690 if (c->s->info.stage != MESA_SHADER_FRAGMENT)
1691 return;
1692
1693 nir_foreach_shader_out_variable(var, c->s) {
1694 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1695 unsigned loc = var->data.driver_location * 4;
1696
1697 assert(array_len == 1);
1698 (void)array_len;
1699
1700 for (int i = 0; i < 4 - var->data.location_frac; i++) {
1701 add_output(c, loc + var->data.location_frac + i,
1702 var->data.location,
1703 var->data.location_frac + i);
1704 }
1705
1706 switch (var->data.location) {
1707 case FRAG_RESULT_COLOR:
1708 c->output_color_var[0] = var;
1709 c->output_color_var[1] = var;
1710 c->output_color_var[2] = var;
1711 c->output_color_var[3] = var;
1712 break;
1713 case FRAG_RESULT_DATA0:
1714 case FRAG_RESULT_DATA1:
1715 case FRAG_RESULT_DATA2:
1716 case FRAG_RESULT_DATA3:
1717 c->output_color_var[var->data.location -
1718 FRAG_RESULT_DATA0] = var;
1719 break;
1720 case FRAG_RESULT_DEPTH:
1721 c->output_position_index = loc;
1722 break;
1723 case FRAG_RESULT_SAMPLE_MASK:
1724 c->output_sample_mask_index = loc;
1725 break;
1726 }
1727 }
1728 }
1729
1730 /**
1731 * Sets up the mapping from nir_register to struct qreg *.
1732 *
1733 * Each nir_register gets a struct qreg per 32-bit component being stored.
1734 */
1735 static void
1736 ntq_setup_registers(struct v3d_compile *c, struct exec_list *list)
1737 {
1738 foreach_list_typed(nir_register, nir_reg, node, list) {
1739 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1740 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1741 array_len *
1742 nir_reg->num_components);
1743
1744 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1745
1746 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1747 qregs[i] = vir_get_temp(c);
1748 }
1749 }
1750
1751 static void
1752 ntq_emit_load_const(struct v3d_compile *c, nir_load_const_instr *instr)
1753 {
1754 /* XXX perf: Experiment with using immediate loads to avoid having
1755 * these end up in the uniform stream. Watch out for breaking the
1756 * small immediates optimization in the process!
1757 */
1758 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1759 for (int i = 0; i < instr->def.num_components; i++)
1760 qregs[i] = vir_uniform_ui(c, instr->value[i].u32);
1761
1762 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1763 }
1764
1765 static void
1766 ntq_emit_ssa_undef(struct v3d_compile *c, nir_ssa_undef_instr *instr)
1767 {
1768 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1769
1770 /* VIR needs there to be *some* value, so pick 0 (same as for
1771 * ntq_setup_registers().
1772 */
1773 for (int i = 0; i < instr->def.num_components; i++)
1774 qregs[i] = vir_uniform_ui(c, 0);
1775 }
1776
1777 static void
1778 ntq_emit_image_size(struct v3d_compile *c, nir_intrinsic_instr *instr)
1779 {
1780 unsigned image_index = nir_src_as_uint(instr->src[0]);
1781 bool is_array = nir_intrinsic_image_array(instr);
1782
1783 ntq_store_dest(c, &instr->dest, 0,
1784 vir_uniform(c, QUNIFORM_IMAGE_WIDTH, image_index));
1785 if (instr->num_components > 1) {
1786 ntq_store_dest(c, &instr->dest, 1,
1787 vir_uniform(c,
1788 instr->num_components == 2 && is_array ?
1789 QUNIFORM_IMAGE_ARRAY_SIZE :
1790 QUNIFORM_IMAGE_HEIGHT,
1791 image_index));
1792 }
1793 if (instr->num_components > 2) {
1794 ntq_store_dest(c, &instr->dest, 2,
1795 vir_uniform(c,
1796 is_array ?
1797 QUNIFORM_IMAGE_ARRAY_SIZE :
1798 QUNIFORM_IMAGE_DEPTH,
1799 image_index));
1800 }
1801 }
1802
1803 static void
1804 vir_emit_tlb_color_read(struct v3d_compile *c, nir_intrinsic_instr *instr)
1805 {
1806 assert(c->s->info.stage == MESA_SHADER_FRAGMENT);
1807
1808 int rt = nir_src_as_uint(instr->src[0]);
1809 assert(rt < V3D_MAX_DRAW_BUFFERS);
1810
1811 int sample_index = nir_intrinsic_base(instr) ;
1812 assert(sample_index < V3D_MAX_SAMPLES);
1813
1814 int component = nir_intrinsic_component(instr);
1815 assert(component < 4);
1816
1817 /* We need to emit our TLB reads after we have acquired the scoreboard
1818 * lock, or the GPU will hang. Usually, we do our scoreboard locking on
1819 * the last thread switch to improve parallelism, however, that is only
1820 * guaranteed to happen before the tlb color writes.
1821 *
1822 * To fix that, we make sure we always emit a thread switch before the
1823 * first tlb color read. If that happens to be the last thread switch
1824 * we emit, then everything is fine, but otherwsie, if any code after
1825 * this point needs to emit additional thread switches, then we will
1826 * switch the strategy to locking the scoreboard on the first thread
1827 * switch instead -- see vir_emit_thrsw().
1828 */
1829 if (!c->emitted_tlb_load) {
1830 if (!c->last_thrsw_at_top_level) {
1831 assert(c->devinfo->ver >= 41);
1832 vir_emit_thrsw(c);
1833 }
1834
1835 c->emitted_tlb_load = true;
1836 }
1837
1838 struct qreg *color_reads_for_sample =
1839 &c->color_reads[(rt * V3D_MAX_SAMPLES + sample_index) * 4];
1840
1841 if (color_reads_for_sample[component].file == QFILE_NULL) {
1842 enum pipe_format rt_format = c->fs_key->color_fmt[rt].format;
1843 int num_components =
1844 util_format_get_nr_components(rt_format);
1845
1846 const bool swap_rb = c->fs_key->swap_color_rb & (1 << rt);
1847 if (swap_rb)
1848 num_components = MAX2(num_components, 3);
1849
1850 nir_variable *var = c->output_color_var[rt];
1851 enum glsl_base_type type = glsl_get_base_type(var->type);
1852
1853 bool is_int_format = type == GLSL_TYPE_INT ||
1854 type == GLSL_TYPE_UINT;
1855
1856 bool is_32b_tlb_format = is_int_format ||
1857 (c->fs_key->f32_color_rb & (1 << rt));
1858
1859 int num_samples = c->fs_key->msaa ? V3D_MAX_SAMPLES : 1;
1860
1861 uint32_t conf = 0xffffff00;
1862 conf |= c->fs_key->msaa ? TLB_SAMPLE_MODE_PER_SAMPLE :
1863 TLB_SAMPLE_MODE_PER_PIXEL;
1864 conf |= (7 - rt) << TLB_RENDER_TARGET_SHIFT;
1865
1866 if (is_32b_tlb_format) {
1867 /* The F32 vs I32 distinction was dropped in 4.2. */
1868 conf |= (c->devinfo->ver < 42 && is_int_format) ?
1869 TLB_TYPE_I32_COLOR : TLB_TYPE_F32_COLOR;
1870
1871 conf |= ((num_components - 1) <<
1872 TLB_VEC_SIZE_MINUS_1_SHIFT);
1873 } else {
1874 conf |= TLB_TYPE_F16_COLOR;
1875 conf |= TLB_F16_SWAP_HI_LO;
1876
1877 if (num_components >= 3)
1878 conf |= TLB_VEC_SIZE_4_F16;
1879 else
1880 conf |= TLB_VEC_SIZE_2_F16;
1881 }
1882
1883
1884 for (int i = 0; i < num_samples; i++) {
1885 struct qreg r, g, b, a;
1886 if (is_32b_tlb_format) {
1887 r = conf != 0xffffffff && i == 0?
1888 vir_TLBU_COLOR_READ(c, conf) :
1889 vir_TLB_COLOR_READ(c);
1890 if (num_components >= 2)
1891 g = vir_TLB_COLOR_READ(c);
1892 if (num_components >= 3)
1893 b = vir_TLB_COLOR_READ(c);
1894 if (num_components >= 4)
1895 a = vir_TLB_COLOR_READ(c);
1896 } else {
1897 struct qreg rg = conf != 0xffffffff && i == 0 ?
1898 vir_TLBU_COLOR_READ(c, conf) :
1899 vir_TLB_COLOR_READ(c);
1900 r = vir_FMOV(c, rg);
1901 vir_set_unpack(c->defs[r.index], 0,
1902 V3D_QPU_UNPACK_L);
1903 g = vir_FMOV(c, rg);
1904 vir_set_unpack(c->defs[g.index], 0,
1905 V3D_QPU_UNPACK_H);
1906
1907 if (num_components > 2) {
1908 struct qreg ba = vir_TLB_COLOR_READ(c);
1909 b = vir_FMOV(c, ba);
1910 vir_set_unpack(c->defs[b.index], 0,
1911 V3D_QPU_UNPACK_L);
1912 a = vir_FMOV(c, ba);
1913 vir_set_unpack(c->defs[a.index], 0,
1914 V3D_QPU_UNPACK_H);
1915 }
1916 }
1917
1918 struct qreg *color_reads =
1919 &c->color_reads[(rt * V3D_MAX_SAMPLES + i) * 4];
1920
1921 color_reads[0] = swap_rb ? b : r;
1922 if (num_components >= 2)
1923 color_reads[1] = g;
1924 if (num_components >= 3)
1925 color_reads[2] = swap_rb ? r : b;
1926 if (num_components >= 4)
1927 color_reads[3] = a;
1928 }
1929 }
1930
1931 assert(color_reads_for_sample[component].file != QFILE_NULL);
1932 ntq_store_dest(c, &instr->dest, 0,
1933 vir_MOV(c, color_reads_for_sample[component]));
1934 }
1935
1936 static void
1937 ntq_emit_load_uniform(struct v3d_compile *c, nir_intrinsic_instr *instr)
1938 {
1939 if (nir_src_is_const(instr->src[0])) {
1940 int offset = (nir_intrinsic_base(instr) +
1941 nir_src_as_uint(instr->src[0]));
1942 assert(offset % 4 == 0);
1943 /* We need dwords */
1944 offset = offset / 4;
1945 for (int i = 0; i < instr->num_components; i++) {
1946 ntq_store_dest(c, &instr->dest, i,
1947 vir_uniform(c, QUNIFORM_UNIFORM,
1948 offset + i));
1949 }
1950 } else {
1951 ntq_emit_tmu_general(c, instr, false);
1952 }
1953 }
1954
1955 static void
1956 ntq_emit_load_input(struct v3d_compile *c, nir_intrinsic_instr *instr)
1957 {
1958 /* XXX: Use ldvpmv (uniform offset) or ldvpmd (non-uniform offset)
1959 * and enable PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR.
1960 */
1961 unsigned offset =
1962 nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[0]);
1963
1964 if (c->s->info.stage != MESA_SHADER_FRAGMENT && c->devinfo->ver >= 40) {
1965 /* Emit the LDVPM directly now, rather than at the top
1966 * of the shader like we did for V3D 3.x (which needs
1967 * vpmsetup when not just taking the next offset).
1968 *
1969 * Note that delaying like this may introduce stalls,
1970 * as LDVPMV takes a minimum of 1 instruction but may
1971 * be slower if the VPM unit is busy with another QPU.
1972 */
1973 int index = 0;
1974 if (c->s->info.system_values_read &
1975 (1ull << SYSTEM_VALUE_INSTANCE_ID)) {
1976 index++;
1977 }
1978 if (c->s->info.system_values_read &
1979 (1ull << SYSTEM_VALUE_VERTEX_ID)) {
1980 index++;
1981 }
1982 for (int i = 0; i < offset; i++)
1983 index += c->vattr_sizes[i];
1984 index += nir_intrinsic_component(instr);
1985 for (int i = 0; i < instr->num_components; i++) {
1986 struct qreg vpm_offset = vir_uniform_ui(c, index++);
1987 ntq_store_dest(c, &instr->dest, i,
1988 vir_LDVPMV_IN(c, vpm_offset));
1989 }
1990 } else {
1991 for (int i = 0; i < instr->num_components; i++) {
1992 int comp = nir_intrinsic_component(instr) + i;
1993 ntq_store_dest(c, &instr->dest, i,
1994 vir_MOV(c, c->inputs[offset * 4 + comp]));
1995 }
1996 }
1997 }
1998
1999 static void
2000 ntq_emit_per_sample_color_write(struct v3d_compile *c,
2001 nir_intrinsic_instr *instr)
2002 {
2003 assert(instr->intrinsic == nir_intrinsic_store_tlb_sample_color_v3d);
2004
2005 unsigned rt = nir_src_as_uint(instr->src[1]);
2006 assert(rt < V3D_MAX_DRAW_BUFFERS);
2007
2008 unsigned sample_idx = nir_intrinsic_base(instr);
2009 assert(sample_idx < V3D_MAX_SAMPLES);
2010
2011 unsigned offset = (rt * V3D_MAX_SAMPLES + sample_idx) * 4;
2012 for (int i = 0; i < instr->num_components; i++) {
2013 c->sample_colors[offset + i] =
2014 vir_MOV(c, ntq_get_src(c, instr->src[0], i));
2015 }
2016 }
2017
2018 static void
2019 ntq_emit_color_write(struct v3d_compile *c,
2020 nir_intrinsic_instr *instr)
2021 {
2022 unsigned offset = (nir_intrinsic_base(instr) +
2023 nir_src_as_uint(instr->src[1])) * 4 +
2024 nir_intrinsic_component(instr);
2025 for (int i = 0; i < instr->num_components; i++) {
2026 c->outputs[offset + i] =
2027 vir_MOV(c, ntq_get_src(c, instr->src[0], i));
2028 }
2029 }
2030
2031 static void
2032 emit_store_output_gs(struct v3d_compile *c, nir_intrinsic_instr *instr)
2033 {
2034 assert(instr->num_components == 1);
2035
2036 struct qreg offset = ntq_get_src(c, instr->src[1], 0);
2037
2038 uint32_t base_offset = nir_intrinsic_base(instr);
2039
2040 if (base_offset)
2041 offset = vir_ADD(c, vir_uniform_ui(c, base_offset), offset);
2042
2043 /* Usually, for VS or FS, we only emit outputs once at program end so
2044 * our VPM writes are never in non-uniform control flow, but this
2045 * is not true for GS, where we are emitting multiple vertices.
2046 */
2047 if (vir_in_nonuniform_control_flow(c)) {
2048 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2049 V3D_QPU_PF_PUSHZ);
2050 }
2051
2052 struct qreg val = ntq_get_src(c, instr->src[0], 0);
2053
2054 /* The offset isn’t necessarily dynamically uniform for a geometry
2055 * shader. This can happen if the shader sometimes doesn’t emit one of
2056 * the vertices. In that case subsequent vertices will be written to
2057 * different offsets in the VPM and we need to use the scatter write
2058 * instruction to have a different offset for each lane.
2059 */
2060 if (nir_src_is_dynamically_uniform(instr->src[1]))
2061 vir_VPM_WRITE_indirect(c, val, offset);
2062 else
2063 vir_STVPMD(c, offset, val);
2064
2065 if (vir_in_nonuniform_control_flow(c)) {
2066 struct qinst *last_inst =
2067 (struct qinst *)c->cur_block->instructions.prev;
2068 vir_set_cond(last_inst, V3D_QPU_COND_IFA);
2069 }
2070 }
2071
2072 static void
2073 ntq_emit_store_output(struct v3d_compile *c, nir_intrinsic_instr *instr)
2074 {
2075 /* XXX perf: Use stvpmv with uniform non-constant offsets and
2076 * stvpmd with non-uniform offsets and enable
2077 * PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR.
2078 */
2079 if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
2080 ntq_emit_color_write(c, instr);
2081 } else if (c->s->info.stage == MESA_SHADER_GEOMETRY) {
2082 emit_store_output_gs(c, instr);
2083 } else {
2084 assert(c->s->info.stage == MESA_SHADER_VERTEX);
2085 assert(instr->num_components == 1);
2086
2087 vir_VPM_WRITE(c,
2088 ntq_get_src(c, instr->src[0], 0),
2089 nir_intrinsic_base(instr));
2090 }
2091 }
2092
2093 static void
2094 ntq_emit_intrinsic(struct v3d_compile *c, nir_intrinsic_instr *instr)
2095 {
2096 switch (instr->intrinsic) {
2097 case nir_intrinsic_load_uniform:
2098 ntq_emit_load_uniform(c, instr);
2099 break;
2100
2101 case nir_intrinsic_load_ubo:
2102 ntq_emit_tmu_general(c, instr, false);
2103 break;
2104
2105 case nir_intrinsic_ssbo_atomic_add:
2106 case nir_intrinsic_ssbo_atomic_imin:
2107 case nir_intrinsic_ssbo_atomic_umin:
2108 case nir_intrinsic_ssbo_atomic_imax:
2109 case nir_intrinsic_ssbo_atomic_umax:
2110 case nir_intrinsic_ssbo_atomic_and:
2111 case nir_intrinsic_ssbo_atomic_or:
2112 case nir_intrinsic_ssbo_atomic_xor:
2113 case nir_intrinsic_ssbo_atomic_exchange:
2114 case nir_intrinsic_ssbo_atomic_comp_swap:
2115 case nir_intrinsic_load_ssbo:
2116 case nir_intrinsic_store_ssbo:
2117 ntq_emit_tmu_general(c, instr, false);
2118 break;
2119
2120 case nir_intrinsic_shared_atomic_add:
2121 case nir_intrinsic_shared_atomic_imin:
2122 case nir_intrinsic_shared_atomic_umin:
2123 case nir_intrinsic_shared_atomic_imax:
2124 case nir_intrinsic_shared_atomic_umax:
2125 case nir_intrinsic_shared_atomic_and:
2126 case nir_intrinsic_shared_atomic_or:
2127 case nir_intrinsic_shared_atomic_xor:
2128 case nir_intrinsic_shared_atomic_exchange:
2129 case nir_intrinsic_shared_atomic_comp_swap:
2130 case nir_intrinsic_load_shared:
2131 case nir_intrinsic_store_shared:
2132 case nir_intrinsic_load_scratch:
2133 case nir_intrinsic_store_scratch:
2134 ntq_emit_tmu_general(c, instr, true);
2135 break;
2136
2137 case nir_intrinsic_image_load:
2138 case nir_intrinsic_image_store:
2139 case nir_intrinsic_image_atomic_add:
2140 case nir_intrinsic_image_atomic_imin:
2141 case nir_intrinsic_image_atomic_umin:
2142 case nir_intrinsic_image_atomic_imax:
2143 case nir_intrinsic_image_atomic_umax:
2144 case nir_intrinsic_image_atomic_and:
2145 case nir_intrinsic_image_atomic_or:
2146 case nir_intrinsic_image_atomic_xor:
2147 case nir_intrinsic_image_atomic_exchange:
2148 case nir_intrinsic_image_atomic_comp_swap:
2149 v3d40_vir_emit_image_load_store(c, instr);
2150 break;
2151
2152 case nir_intrinsic_get_buffer_size:
2153 ntq_store_dest(c, &instr->dest, 0,
2154 vir_uniform(c, QUNIFORM_GET_BUFFER_SIZE,
2155 nir_src_as_uint(instr->src[0])));
2156 break;
2157
2158 case nir_intrinsic_load_user_clip_plane:
2159 for (int i = 0; i < nir_intrinsic_dest_components(instr); i++) {
2160 ntq_store_dest(c, &instr->dest, i,
2161 vir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
2162 nir_intrinsic_ucp_id(instr) *
2163 4 + i));
2164 }
2165 break;
2166
2167 case nir_intrinsic_load_viewport_x_scale:
2168 ntq_store_dest(c, &instr->dest, 0,
2169 vir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE, 0));
2170 break;
2171
2172 case nir_intrinsic_load_viewport_y_scale:
2173 ntq_store_dest(c, &instr->dest, 0,
2174 vir_uniform(c, QUNIFORM_VIEWPORT_Y_SCALE, 0));
2175 break;
2176
2177 case nir_intrinsic_load_viewport_z_scale:
2178 ntq_store_dest(c, &instr->dest, 0,
2179 vir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0));
2180 break;
2181
2182 case nir_intrinsic_load_viewport_z_offset:
2183 ntq_store_dest(c, &instr->dest, 0,
2184 vir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0));
2185 break;
2186
2187 case nir_intrinsic_load_alpha_ref_float:
2188 ntq_store_dest(c, &instr->dest, 0,
2189 vir_uniform(c, QUNIFORM_ALPHA_REF, 0));
2190 break;
2191
2192 case nir_intrinsic_load_line_coord:
2193 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->line_x));
2194 break;
2195
2196 case nir_intrinsic_load_line_width:
2197 ntq_store_dest(c, &instr->dest, 0,
2198 vir_uniform(c, QUNIFORM_LINE_WIDTH, 0));
2199 break;
2200
2201 case nir_intrinsic_load_aa_line_width:
2202 ntq_store_dest(c, &instr->dest, 0,
2203 vir_uniform(c, QUNIFORM_AA_LINE_WIDTH, 0));
2204 break;
2205
2206 case nir_intrinsic_load_sample_mask_in:
2207 ntq_store_dest(c, &instr->dest, 0, vir_MSF(c));
2208 break;
2209
2210 case nir_intrinsic_load_helper_invocation:
2211 vir_set_pf(vir_MSF_dest(c, vir_nop_reg()), V3D_QPU_PF_PUSHZ);
2212 ntq_store_dest(c, &instr->dest, 0,
2213 vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFA,
2214 vir_uniform_ui(c, ~0),
2215 vir_uniform_ui(c, 0))));
2216 break;
2217
2218 case nir_intrinsic_load_front_face:
2219 /* The register contains 0 (front) or 1 (back), and we need to
2220 * turn it into a NIR bool where true means front.
2221 */
2222 ntq_store_dest(c, &instr->dest, 0,
2223 vir_ADD(c,
2224 vir_uniform_ui(c, -1),
2225 vir_REVF(c)));
2226 break;
2227
2228 case nir_intrinsic_load_instance_id:
2229 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->iid));
2230 break;
2231
2232 case nir_intrinsic_load_vertex_id:
2233 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->vid));
2234 break;
2235
2236 case nir_intrinsic_load_tlb_color_v3d:
2237 vir_emit_tlb_color_read(c, instr);
2238 break;
2239
2240 case nir_intrinsic_load_input:
2241 ntq_emit_load_input(c, instr);
2242 break;
2243
2244 case nir_intrinsic_store_tlb_sample_color_v3d:
2245 ntq_emit_per_sample_color_write(c, instr);
2246 break;
2247
2248 case nir_intrinsic_store_output:
2249 ntq_emit_store_output(c, instr);
2250 break;
2251
2252 case nir_intrinsic_image_size:
2253 ntq_emit_image_size(c, instr);
2254 break;
2255
2256 case nir_intrinsic_discard:
2257 if (vir_in_nonuniform_control_flow(c)) {
2258 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2259 V3D_QPU_PF_PUSHZ);
2260 vir_set_cond(vir_SETMSF_dest(c, vir_nop_reg(),
2261 vir_uniform_ui(c, 0)),
2262 V3D_QPU_COND_IFA);
2263 } else {
2264 vir_SETMSF_dest(c, vir_nop_reg(),
2265 vir_uniform_ui(c, 0));
2266 }
2267 break;
2268
2269 case nir_intrinsic_discard_if: {
2270 enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, instr->src[0]);
2271
2272 if (vir_in_nonuniform_control_flow(c)) {
2273 struct qinst *exec_flag = vir_MOV_dest(c, vir_nop_reg(),
2274 c->execute);
2275 if (cond == V3D_QPU_COND_IFA) {
2276 vir_set_uf(exec_flag, V3D_QPU_UF_ANDZ);
2277 } else {
2278 vir_set_uf(exec_flag, V3D_QPU_UF_NORNZ);
2279 cond = V3D_QPU_COND_IFA;
2280 }
2281 }
2282
2283 vir_set_cond(vir_SETMSF_dest(c, vir_nop_reg(),
2284 vir_uniform_ui(c, 0)), cond);
2285
2286 break;
2287 }
2288
2289 case nir_intrinsic_memory_barrier:
2290 case nir_intrinsic_memory_barrier_buffer:
2291 case nir_intrinsic_memory_barrier_image:
2292 case nir_intrinsic_memory_barrier_shared:
2293 case nir_intrinsic_memory_barrier_tcs_patch:
2294 case nir_intrinsic_group_memory_barrier:
2295 /* We don't do any instruction scheduling of these NIR
2296 * instructions between each other, so we just need to make
2297 * sure that the TMU operations before the barrier are flushed
2298 * before the ones after the barrier. That is currently
2299 * handled by having a THRSW in each of them and a LDTMU
2300 * series or a TMUWT after.
2301 */
2302 break;
2303
2304 case nir_intrinsic_control_barrier:
2305 /* Emit a TSY op to get all invocations in the workgroup
2306 * (actually supergroup) to block until the last invocation
2307 * reaches the TSY op.
2308 */
2309 if (c->devinfo->ver >= 42) {
2310 vir_BARRIERID_dest(c, vir_reg(QFILE_MAGIC,
2311 V3D_QPU_WADDR_SYNCB));
2312 } else {
2313 struct qinst *sync =
2314 vir_BARRIERID_dest(c,
2315 vir_reg(QFILE_MAGIC,
2316 V3D_QPU_WADDR_SYNCU));
2317 sync->uniform =
2318 vir_get_uniform_index(c, QUNIFORM_CONSTANT,
2319 0xffffff00 |
2320 V3D_TSY_WAIT_INC_CHECK);
2321
2322 }
2323
2324 /* The blocking of a TSY op only happens at the next thread
2325 * switch. No texturing may be outstanding at the time of a
2326 * TSY blocking operation.
2327 */
2328 vir_emit_thrsw(c);
2329 break;
2330
2331 case nir_intrinsic_load_num_work_groups:
2332 for (int i = 0; i < 3; i++) {
2333 ntq_store_dest(c, &instr->dest, i,
2334 vir_uniform(c, QUNIFORM_NUM_WORK_GROUPS,
2335 i));
2336 }
2337 break;
2338
2339 case nir_intrinsic_load_local_invocation_index:
2340 ntq_store_dest(c, &instr->dest, 0,
2341 vir_SHR(c, c->cs_payload[1],
2342 vir_uniform_ui(c, 32 - c->local_invocation_index_bits)));
2343 break;
2344
2345 case nir_intrinsic_load_work_group_id:
2346 ntq_store_dest(c, &instr->dest, 0,
2347 vir_AND(c, c->cs_payload[0],
2348 vir_uniform_ui(c, 0xffff)));
2349 ntq_store_dest(c, &instr->dest, 1,
2350 vir_SHR(c, c->cs_payload[0],
2351 vir_uniform_ui(c, 16)));
2352 ntq_store_dest(c, &instr->dest, 2,
2353 vir_AND(c, c->cs_payload[1],
2354 vir_uniform_ui(c, 0xffff)));
2355 break;
2356
2357 case nir_intrinsic_load_subgroup_id:
2358 ntq_store_dest(c, &instr->dest, 0, vir_EIDX(c));
2359 break;
2360
2361 case nir_intrinsic_load_per_vertex_input: {
2362 /* col: vertex index, row = varying index */
2363 struct qreg col = ntq_get_src(c, instr->src[0], 0);
2364 uint32_t row_idx = nir_intrinsic_base(instr) * 4 +
2365 nir_intrinsic_component(instr);
2366 for (int i = 0; i < instr->num_components; i++) {
2367 struct qreg row = vir_uniform_ui(c, row_idx++);
2368 ntq_store_dest(c, &instr->dest, i,
2369 vir_LDVPMG_IN(c, row, col));
2370 }
2371 break;
2372 }
2373
2374 case nir_intrinsic_emit_vertex:
2375 case nir_intrinsic_end_primitive:
2376 unreachable("Should have been lowered in v3d_nir_lower_io");
2377 break;
2378
2379 case nir_intrinsic_load_primitive_id: {
2380 /* gl_PrimitiveIdIn is written by the GBG in the first word of
2381 * VPM output header. According to docs, we should read this
2382 * using ldvpm(v,d)_in (See Table 71).
2383 */
2384 ntq_store_dest(c, &instr->dest, 0,
2385 vir_LDVPMV_IN(c, vir_uniform_ui(c, 0)));
2386 break;
2387 }
2388
2389 case nir_intrinsic_load_invocation_id:
2390 ntq_store_dest(c, &instr->dest, 0, vir_IID(c));
2391 break;
2392
2393 case nir_intrinsic_load_fb_layers_v3d:
2394 ntq_store_dest(c, &instr->dest, 0,
2395 vir_uniform(c, QUNIFORM_FB_LAYERS, 0));
2396 break;
2397
2398 case nir_intrinsic_load_sample_id:
2399 ntq_store_dest(c, &instr->dest, 0, vir_SAMPID(c));
2400 break;
2401
2402 default:
2403 fprintf(stderr, "Unknown intrinsic: ");
2404 nir_print_instr(&instr->instr, stderr);
2405 fprintf(stderr, "\n");
2406 break;
2407 }
2408 }
2409
2410 /* Clears (activates) the execute flags for any channels whose jump target
2411 * matches this block.
2412 *
2413 * XXX perf: Could we be using flpush/flpop somehow for our execution channel
2414 * enabling?
2415 *
2416 * XXX perf: For uniform control flow, we should be able to skip c->execute
2417 * handling entirely.
2418 */
2419 static void
2420 ntq_activate_execute_for_block(struct v3d_compile *c)
2421 {
2422 vir_set_pf(vir_XOR_dest(c, vir_nop_reg(),
2423 c->execute, vir_uniform_ui(c, c->cur_block->index)),
2424 V3D_QPU_PF_PUSHZ);
2425
2426 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
2427 }
2428
2429 static void
2430 ntq_emit_uniform_if(struct v3d_compile *c, nir_if *if_stmt)
2431 {
2432 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
2433 bool empty_else_block =
2434 (nir_else_block == nir_if_last_else_block(if_stmt) &&
2435 exec_list_is_empty(&nir_else_block->instr_list));
2436
2437 struct qblock *then_block = vir_new_block(c);
2438 struct qblock *after_block = vir_new_block(c);
2439 struct qblock *else_block;
2440 if (empty_else_block)
2441 else_block = after_block;
2442 else
2443 else_block = vir_new_block(c);
2444
2445 /* Set up the flags for the IF condition (taking the THEN branch). */
2446 enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, if_stmt->condition);
2447
2448 /* Jump to ELSE. */
2449 vir_BRANCH(c, cond == V3D_QPU_COND_IFA ?
2450 V3D_QPU_BRANCH_COND_ALLNA :
2451 V3D_QPU_BRANCH_COND_ALLA);
2452 vir_link_blocks(c->cur_block, else_block);
2453 vir_link_blocks(c->cur_block, then_block);
2454
2455 /* Process the THEN block. */
2456 vir_set_emit_block(c, then_block);
2457 ntq_emit_cf_list(c, &if_stmt->then_list);
2458
2459 if (!empty_else_block) {
2460 /* At the end of the THEN block, jump to ENDIF */
2461 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALWAYS);
2462 vir_link_blocks(c->cur_block, after_block);
2463
2464 /* Emit the else block. */
2465 vir_set_emit_block(c, else_block);
2466 ntq_emit_cf_list(c, &if_stmt->else_list);
2467 }
2468
2469 vir_link_blocks(c->cur_block, after_block);
2470
2471 vir_set_emit_block(c, after_block);
2472 }
2473
2474 static void
2475 ntq_emit_nonuniform_if(struct v3d_compile *c, nir_if *if_stmt)
2476 {
2477 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
2478 bool empty_else_block =
2479 (nir_else_block == nir_if_last_else_block(if_stmt) &&
2480 exec_list_is_empty(&nir_else_block->instr_list));
2481
2482 struct qblock *then_block = vir_new_block(c);
2483 struct qblock *after_block = vir_new_block(c);
2484 struct qblock *else_block;
2485 if (empty_else_block)
2486 else_block = after_block;
2487 else
2488 else_block = vir_new_block(c);
2489
2490 bool was_uniform_control_flow = false;
2491 if (!vir_in_nonuniform_control_flow(c)) {
2492 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
2493 was_uniform_control_flow = true;
2494 }
2495
2496 /* Set up the flags for the IF condition (taking the THEN branch). */
2497 enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, if_stmt->condition);
2498
2499 /* Update the flags+cond to mean "Taking the ELSE branch (!cond) and
2500 * was previously active (execute Z) for updating the exec flags.
2501 */
2502 if (was_uniform_control_flow) {
2503 cond = v3d_qpu_cond_invert(cond);
2504 } else {
2505 struct qinst *inst = vir_MOV_dest(c, vir_nop_reg(), c->execute);
2506 if (cond == V3D_QPU_COND_IFA) {
2507 vir_set_uf(inst, V3D_QPU_UF_NORNZ);
2508 } else {
2509 vir_set_uf(inst, V3D_QPU_UF_ANDZ);
2510 cond = V3D_QPU_COND_IFA;
2511 }
2512 }
2513
2514 vir_MOV_cond(c, cond,
2515 c->execute,
2516 vir_uniform_ui(c, else_block->index));
2517
2518 /* Jump to ELSE if nothing is active for THEN, otherwise fall
2519 * through.
2520 */
2521 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute), V3D_QPU_PF_PUSHZ);
2522 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLNA);
2523 vir_link_blocks(c->cur_block, else_block);
2524 vir_link_blocks(c->cur_block, then_block);
2525
2526 /* Process the THEN block. */
2527 vir_set_emit_block(c, then_block);
2528 ntq_emit_cf_list(c, &if_stmt->then_list);
2529
2530 if (!empty_else_block) {
2531 /* Handle the end of the THEN block. First, all currently
2532 * active channels update their execute flags to point to
2533 * ENDIF
2534 */
2535 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2536 V3D_QPU_PF_PUSHZ);
2537 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2538 vir_uniform_ui(c, after_block->index));
2539
2540 /* If everything points at ENDIF, then jump there immediately. */
2541 vir_set_pf(vir_XOR_dest(c, vir_nop_reg(),
2542 c->execute,
2543 vir_uniform_ui(c, after_block->index)),
2544 V3D_QPU_PF_PUSHZ);
2545 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLA);
2546 vir_link_blocks(c->cur_block, after_block);
2547 vir_link_blocks(c->cur_block, else_block);
2548
2549 vir_set_emit_block(c, else_block);
2550 ntq_activate_execute_for_block(c);
2551 ntq_emit_cf_list(c, &if_stmt->else_list);
2552 }
2553
2554 vir_link_blocks(c->cur_block, after_block);
2555
2556 vir_set_emit_block(c, after_block);
2557 if (was_uniform_control_flow)
2558 c->execute = c->undef;
2559 else
2560 ntq_activate_execute_for_block(c);
2561 }
2562
2563 static void
2564 ntq_emit_if(struct v3d_compile *c, nir_if *nif)
2565 {
2566 bool was_in_control_flow = c->in_control_flow;
2567 c->in_control_flow = true;
2568 if (!vir_in_nonuniform_control_flow(c) &&
2569 nir_src_is_dynamically_uniform(nif->condition)) {
2570 ntq_emit_uniform_if(c, nif);
2571 } else {
2572 ntq_emit_nonuniform_if(c, nif);
2573 }
2574 c->in_control_flow = was_in_control_flow;
2575 }
2576
2577 static void
2578 ntq_emit_jump(struct v3d_compile *c, nir_jump_instr *jump)
2579 {
2580 switch (jump->type) {
2581 case nir_jump_break:
2582 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2583 V3D_QPU_PF_PUSHZ);
2584 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2585 vir_uniform_ui(c, c->loop_break_block->index));
2586 break;
2587
2588 case nir_jump_continue:
2589 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2590 V3D_QPU_PF_PUSHZ);
2591 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2592 vir_uniform_ui(c, c->loop_cont_block->index));
2593 break;
2594
2595 case nir_jump_return:
2596 unreachable("All returns shouold be lowered\n");
2597 break;
2598
2599 case nir_jump_goto:
2600 case nir_jump_goto_if:
2601 unreachable("not supported\n");
2602 break;
2603 }
2604 }
2605
2606 static void
2607 ntq_emit_instr(struct v3d_compile *c, nir_instr *instr)
2608 {
2609 switch (instr->type) {
2610 case nir_instr_type_alu:
2611 ntq_emit_alu(c, nir_instr_as_alu(instr));
2612 break;
2613
2614 case nir_instr_type_intrinsic:
2615 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
2616 break;
2617
2618 case nir_instr_type_load_const:
2619 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
2620 break;
2621
2622 case nir_instr_type_ssa_undef:
2623 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
2624 break;
2625
2626 case nir_instr_type_tex:
2627 ntq_emit_tex(c, nir_instr_as_tex(instr));
2628 break;
2629
2630 case nir_instr_type_jump:
2631 ntq_emit_jump(c, nir_instr_as_jump(instr));
2632 break;
2633
2634 default:
2635 fprintf(stderr, "Unknown NIR instr type: ");
2636 nir_print_instr(instr, stderr);
2637 fprintf(stderr, "\n");
2638 abort();
2639 }
2640 }
2641
2642 static void
2643 ntq_emit_block(struct v3d_compile *c, nir_block *block)
2644 {
2645 nir_foreach_instr(instr, block) {
2646 ntq_emit_instr(c, instr);
2647 }
2648 }
2649
2650 static void ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
2651
2652 static void
2653 ntq_emit_loop(struct v3d_compile *c, nir_loop *loop)
2654 {
2655 bool was_in_control_flow = c->in_control_flow;
2656 c->in_control_flow = true;
2657
2658 bool was_uniform_control_flow = false;
2659 if (!vir_in_nonuniform_control_flow(c)) {
2660 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
2661 was_uniform_control_flow = true;
2662 }
2663
2664 struct qblock *save_loop_cont_block = c->loop_cont_block;
2665 struct qblock *save_loop_break_block = c->loop_break_block;
2666
2667 c->loop_cont_block = vir_new_block(c);
2668 c->loop_break_block = vir_new_block(c);
2669
2670 vir_link_blocks(c->cur_block, c->loop_cont_block);
2671 vir_set_emit_block(c, c->loop_cont_block);
2672 ntq_activate_execute_for_block(c);
2673
2674 ntq_emit_cf_list(c, &loop->body);
2675
2676 /* Re-enable any previous continues now, so our ANYA check below
2677 * works.
2678 *
2679 * XXX: Use the .ORZ flags update, instead.
2680 */
2681 vir_set_pf(vir_XOR_dest(c,
2682 vir_nop_reg(),
2683 c->execute,
2684 vir_uniform_ui(c, c->loop_cont_block->index)),
2685 V3D_QPU_PF_PUSHZ);
2686 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
2687
2688 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute), V3D_QPU_PF_PUSHZ);
2689
2690 struct qinst *branch = vir_BRANCH(c, V3D_QPU_BRANCH_COND_ANYA);
2691 /* Pixels that were not dispatched or have been discarded should not
2692 * contribute to looping again.
2693 */
2694 branch->qpu.branch.msfign = V3D_QPU_MSFIGN_P;
2695 vir_link_blocks(c->cur_block, c->loop_cont_block);
2696 vir_link_blocks(c->cur_block, c->loop_break_block);
2697
2698 vir_set_emit_block(c, c->loop_break_block);
2699 if (was_uniform_control_flow)
2700 c->execute = c->undef;
2701 else
2702 ntq_activate_execute_for_block(c);
2703
2704 c->loop_break_block = save_loop_break_block;
2705 c->loop_cont_block = save_loop_cont_block;
2706
2707 c->loops++;
2708
2709 c->in_control_flow = was_in_control_flow;
2710 }
2711
2712 static void
2713 ntq_emit_function(struct v3d_compile *c, nir_function_impl *func)
2714 {
2715 fprintf(stderr, "FUNCTIONS not handled.\n");
2716 abort();
2717 }
2718
2719 static void
2720 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list)
2721 {
2722 foreach_list_typed(nir_cf_node, node, node, list) {
2723 switch (node->type) {
2724 case nir_cf_node_block:
2725 ntq_emit_block(c, nir_cf_node_as_block(node));
2726 break;
2727
2728 case nir_cf_node_if:
2729 ntq_emit_if(c, nir_cf_node_as_if(node));
2730 break;
2731
2732 case nir_cf_node_loop:
2733 ntq_emit_loop(c, nir_cf_node_as_loop(node));
2734 break;
2735
2736 case nir_cf_node_function:
2737 ntq_emit_function(c, nir_cf_node_as_function(node));
2738 break;
2739
2740 default:
2741 fprintf(stderr, "Unknown NIR node type\n");
2742 abort();
2743 }
2744 }
2745 }
2746
2747 static void
2748 ntq_emit_impl(struct v3d_compile *c, nir_function_impl *impl)
2749 {
2750 ntq_setup_registers(c, &impl->registers);
2751 ntq_emit_cf_list(c, &impl->body);
2752 }
2753
2754 static void
2755 nir_to_vir(struct v3d_compile *c)
2756 {
2757 switch (c->s->info.stage) {
2758 case MESA_SHADER_FRAGMENT:
2759 c->payload_w = vir_MOV(c, vir_reg(QFILE_REG, 0));
2760 c->payload_w_centroid = vir_MOV(c, vir_reg(QFILE_REG, 1));
2761 c->payload_z = vir_MOV(c, vir_reg(QFILE_REG, 2));
2762
2763 /* V3D 4.x can disable implicit point coordinate varyings if
2764 * they are not used.
2765 */
2766 if (c->fs_key->is_points &&
2767 (c->devinfo->ver < 40 || program_reads_point_coord(c))) {
2768 c->point_x = emit_fragment_varying(c, NULL, 0, 0);
2769 c->point_y = emit_fragment_varying(c, NULL, 0, 0);
2770 c->uses_implicit_point_line_varyings = true;
2771 } else if (c->fs_key->is_lines &&
2772 (c->devinfo->ver < 40 ||
2773 (c->s->info.system_values_read &
2774 BITFIELD64_BIT(SYSTEM_VALUE_LINE_COORD)))) {
2775 c->line_x = emit_fragment_varying(c, NULL, 0, 0);
2776 c->uses_implicit_point_line_varyings = true;
2777 }
2778 break;
2779 case MESA_SHADER_COMPUTE:
2780 /* Set up the TSO for barriers, assuming we do some. */
2781 if (c->devinfo->ver < 42) {
2782 vir_BARRIERID_dest(c, vir_reg(QFILE_MAGIC,
2783 V3D_QPU_WADDR_SYNC));
2784 }
2785
2786 c->cs_payload[0] = vir_MOV(c, vir_reg(QFILE_REG, 0));
2787 c->cs_payload[1] = vir_MOV(c, vir_reg(QFILE_REG, 2));
2788
2789 /* Set up the division between gl_LocalInvocationIndex and
2790 * wg_in_mem in the payload reg.
2791 */
2792 int wg_size = (c->s->info.cs.local_size[0] *
2793 c->s->info.cs.local_size[1] *
2794 c->s->info.cs.local_size[2]);
2795 c->local_invocation_index_bits =
2796 ffs(util_next_power_of_two(MAX2(wg_size, 64))) - 1;
2797 assert(c->local_invocation_index_bits <= 8);
2798
2799 if (c->s->info.cs.shared_size) {
2800 struct qreg wg_in_mem = vir_SHR(c, c->cs_payload[1],
2801 vir_uniform_ui(c, 16));
2802 if (c->s->info.cs.local_size[0] != 1 ||
2803 c->s->info.cs.local_size[1] != 1 ||
2804 c->s->info.cs.local_size[2] != 1) {
2805 int wg_bits = (16 -
2806 c->local_invocation_index_bits);
2807 int wg_mask = (1 << wg_bits) - 1;
2808 wg_in_mem = vir_AND(c, wg_in_mem,
2809 vir_uniform_ui(c, wg_mask));
2810 }
2811 struct qreg shared_per_wg =
2812 vir_uniform_ui(c, c->s->info.cs.shared_size);
2813
2814 c->cs_shared_offset =
2815 vir_ADD(c,
2816 vir_uniform(c, QUNIFORM_SHARED_OFFSET,0),
2817 vir_UMUL(c, wg_in_mem, shared_per_wg));
2818 }
2819 break;
2820 default:
2821 break;
2822 }
2823
2824 if (c->s->scratch_size) {
2825 v3d_setup_spill_base(c);
2826 c->spill_size += V3D_CHANNELS * c->s->scratch_size;
2827 }
2828
2829 switch (c->s->info.stage) {
2830 case MESA_SHADER_VERTEX:
2831 ntq_setup_vs_inputs(c);
2832 break;
2833 case MESA_SHADER_GEOMETRY:
2834 ntq_setup_gs_inputs(c);
2835 break;
2836 case MESA_SHADER_FRAGMENT:
2837 ntq_setup_fs_inputs(c);
2838 break;
2839 case MESA_SHADER_COMPUTE:
2840 break;
2841 default:
2842 unreachable("unsupported shader stage");
2843 }
2844
2845 ntq_setup_outputs(c);
2846
2847 /* Find the main function and emit the body. */
2848 nir_foreach_function(function, c->s) {
2849 assert(strcmp(function->name, "main") == 0);
2850 assert(function->impl);
2851 ntq_emit_impl(c, function->impl);
2852 }
2853 }
2854
2855 const nir_shader_compiler_options v3d_nir_options = {
2856 .lower_all_io_to_temps = true,
2857 .lower_extract_byte = true,
2858 .lower_extract_word = true,
2859 .lower_bitfield_insert_to_shifts = true,
2860 .lower_bitfield_extract_to_shifts = true,
2861 .lower_bitfield_reverse = true,
2862 .lower_bit_count = true,
2863 .lower_cs_local_id_from_index = true,
2864 .lower_ffract = true,
2865 .lower_fmod = true,
2866 .lower_pack_unorm_2x16 = true,
2867 .lower_pack_snorm_2x16 = true,
2868 .lower_pack_unorm_4x8 = true,
2869 .lower_pack_snorm_4x8 = true,
2870 .lower_unpack_unorm_4x8 = true,
2871 .lower_unpack_snorm_4x8 = true,
2872 .lower_pack_half_2x16 = true,
2873 .lower_unpack_half_2x16 = true,
2874 .lower_fdiv = true,
2875 .lower_find_lsb = true,
2876 .lower_ffma = true,
2877 .lower_flrp32 = true,
2878 .lower_fpow = true,
2879 .lower_fsat = true,
2880 .lower_fsqrt = true,
2881 .lower_ifind_msb = true,
2882 .lower_isign = true,
2883 .lower_ldexp = true,
2884 .lower_mul_high = true,
2885 .lower_wpos_pntc = true,
2886 .lower_rotate = true,
2887 .lower_to_scalar = true,
2888 };
2889
2890 /**
2891 * When demoting a shader down to single-threaded, removes the THRSW
2892 * instructions (one will still be inserted at v3d_vir_to_qpu() for the
2893 * program end).
2894 */
2895 static void
2896 vir_remove_thrsw(struct v3d_compile *c)
2897 {
2898 vir_for_each_block(block, c) {
2899 vir_for_each_inst_safe(inst, block) {
2900 if (inst->qpu.sig.thrsw)
2901 vir_remove_instruction(c, inst);
2902 }
2903 }
2904
2905 c->last_thrsw = NULL;
2906 }
2907
2908 void
2909 vir_emit_last_thrsw(struct v3d_compile *c)
2910 {
2911 /* On V3D before 4.1, we need a TMU op to be outstanding when thread
2912 * switching, so disable threads if we didn't do any TMU ops (each of
2913 * which would have emitted a THRSW).
2914 */
2915 if (!c->last_thrsw_at_top_level && c->devinfo->ver < 41) {
2916 c->threads = 1;
2917 if (c->last_thrsw)
2918 vir_remove_thrsw(c);
2919 return;
2920 }
2921
2922 /* If we're threaded and the last THRSW was in conditional code, then
2923 * we need to emit another one so that we can flag it as the last
2924 * thrsw.
2925 */
2926 if (c->last_thrsw && !c->last_thrsw_at_top_level) {
2927 assert(c->devinfo->ver >= 41);
2928 vir_emit_thrsw(c);
2929 }
2930
2931 /* If we're threaded, then we need to mark the last THRSW instruction
2932 * so we can emit a pair of them at QPU emit time.
2933 *
2934 * For V3D 4.x, we can spawn the non-fragment shaders already in the
2935 * post-last-THRSW state, so we can skip this.
2936 */
2937 if (!c->last_thrsw && c->s->info.stage == MESA_SHADER_FRAGMENT) {
2938 assert(c->devinfo->ver >= 41);
2939 vir_emit_thrsw(c);
2940 }
2941
2942 if (c->last_thrsw)
2943 c->last_thrsw->is_last_thrsw = true;
2944 }
2945
2946 /* There's a flag in the shader for "center W is needed for reasons other than
2947 * non-centroid varyings", so we just walk the program after VIR optimization
2948 * to see if it's used. It should be harmless to set even if we only use
2949 * center W for varyings.
2950 */
2951 static void
2952 vir_check_payload_w(struct v3d_compile *c)
2953 {
2954 if (c->s->info.stage != MESA_SHADER_FRAGMENT)
2955 return;
2956
2957 vir_for_each_inst_inorder(inst, c) {
2958 for (int i = 0; i < vir_get_nsrc(inst); i++) {
2959 if (inst->src[i].file == QFILE_REG &&
2960 inst->src[i].index == 0) {
2961 c->uses_center_w = true;
2962 return;
2963 }
2964 }
2965 }
2966
2967 }
2968
2969 void
2970 v3d_nir_to_vir(struct v3d_compile *c)
2971 {
2972 if (V3D_DEBUG & (V3D_DEBUG_NIR |
2973 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2974 fprintf(stderr, "%s prog %d/%d NIR:\n",
2975 vir_get_stage_name(c),
2976 c->program_id, c->variant_id);
2977 nir_print_shader(c->s, stderr);
2978 }
2979
2980 nir_to_vir(c);
2981
2982 /* Emit the last THRSW before STVPM and TLB writes. */
2983 vir_emit_last_thrsw(c);
2984
2985 switch (c->s->info.stage) {
2986 case MESA_SHADER_FRAGMENT:
2987 emit_frag_end(c);
2988 break;
2989 case MESA_SHADER_GEOMETRY:
2990 emit_geom_end(c);
2991 break;
2992 case MESA_SHADER_VERTEX:
2993 emit_vert_end(c);
2994 break;
2995 case MESA_SHADER_COMPUTE:
2996 break;
2997 default:
2998 unreachable("bad stage");
2999 }
3000
3001 if (V3D_DEBUG & (V3D_DEBUG_VIR |
3002 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
3003 fprintf(stderr, "%s prog %d/%d pre-opt VIR:\n",
3004 vir_get_stage_name(c),
3005 c->program_id, c->variant_id);
3006 vir_dump(c);
3007 fprintf(stderr, "\n");
3008 }
3009
3010 vir_optimize(c);
3011
3012 vir_check_payload_w(c);
3013
3014 /* XXX perf: On VC4, we do a VIR-level instruction scheduling here.
3015 * We used that on that platform to pipeline TMU writes and reduce the
3016 * number of thread switches, as well as try (mostly successfully) to
3017 * reduce maximum register pressure to allow more threads. We should
3018 * do something of that sort for V3D -- either instruction scheduling
3019 * here, or delay the the THRSW and LDTMUs from our texture
3020 * instructions until the results are needed.
3021 */
3022
3023 if (V3D_DEBUG & (V3D_DEBUG_VIR |
3024 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
3025 fprintf(stderr, "%s prog %d/%d VIR:\n",
3026 vir_get_stage_name(c),
3027 c->program_id, c->variant_id);
3028 vir_dump(c);
3029 fprintf(stderr, "\n");
3030 }
3031
3032 /* Attempt to allocate registers for the temporaries. If we fail,
3033 * reduce thread count and try again.
3034 */
3035 int min_threads = (c->devinfo->ver >= 41) ? 2 : 1;
3036 struct qpu_reg *temp_registers;
3037 while (true) {
3038 bool spilled;
3039 temp_registers = v3d_register_allocate(c, &spilled);
3040 if (spilled)
3041 continue;
3042
3043 if (temp_registers)
3044 break;
3045