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34c8d5438e14dd7d88a4a4813f6bd75f49fa26df
[mesa.git] / src / broadcom / compiler / nir_to_vir.c
1 /*
2 * Copyright © 2016 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <inttypes.h>
25 #include "util/u_format.h"
26 #include "util/u_math.h"
27 #include "util/u_memory.h"
28 #include "util/ralloc.h"
29 #include "util/hash_table.h"
30 #include "compiler/nir/nir.h"
31 #include "compiler/nir/nir_builder.h"
32 #include "common/v3d_device_info.h"
33 #include "v3d_compiler.h"
34
35 /* We don't do any address packing. */
36 #define __gen_user_data void
37 #define __gen_address_type uint32_t
38 #define __gen_address_offset(reloc) (*reloc)
39 #define __gen_emit_reloc(cl, reloc)
40 #include "cle/v3d_packet_v41_pack.h"
41
42 #define GENERAL_TMU_LOOKUP_PER_QUAD (0 << 7)
43 #define GENERAL_TMU_LOOKUP_PER_PIXEL (1 << 7)
44 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_I (0 << 0)
45 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_I (1 << 0)
46 #define GENERAL_TMU_LOOKUP_TYPE_VEC2 (2 << 0)
47 #define GENERAL_TMU_LOOKUP_TYPE_VEC3 (3 << 0)
48 #define GENERAL_TMU_LOOKUP_TYPE_VEC4 (4 << 0)
49 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_UI (5 << 0)
50 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_UI (6 << 0)
51 #define GENERAL_TMU_LOOKUP_TYPE_32BIT_UI (7 << 0)
52
53 #define V3D_TSY_SET_QUORUM 0
54 #define V3D_TSY_INC_WAITERS 1
55 #define V3D_TSY_DEC_WAITERS 2
56 #define V3D_TSY_INC_QUORUM 3
57 #define V3D_TSY_DEC_QUORUM 4
58 #define V3D_TSY_FREE_ALL 5
59 #define V3D_TSY_RELEASE 6
60 #define V3D_TSY_ACQUIRE 7
61 #define V3D_TSY_WAIT 8
62 #define V3D_TSY_WAIT_INC 9
63 #define V3D_TSY_WAIT_CHECK 10
64 #define V3D_TSY_WAIT_INC_CHECK 11
65 #define V3D_TSY_WAIT_CV 12
66 #define V3D_TSY_INC_SEMAPHORE 13
67 #define V3D_TSY_DEC_SEMAPHORE 14
68 #define V3D_TSY_SET_QUORUM_FREE_ALL 15
69
70 static void
71 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
72
73 static void
74 resize_qreg_array(struct v3d_compile *c,
75 struct qreg **regs,
76 uint32_t *size,
77 uint32_t decl_size)
78 {
79 if (*size >= decl_size)
80 return;
81
82 uint32_t old_size = *size;
83 *size = MAX2(*size * 2, decl_size);
84 *regs = reralloc(c, *regs, struct qreg, *size);
85 if (!*regs) {
86 fprintf(stderr, "Malloc failure\n");
87 abort();
88 }
89
90 for (uint32_t i = old_size; i < *size; i++)
91 (*regs)[i] = c->undef;
92 }
93
94 void
95 vir_emit_thrsw(struct v3d_compile *c)
96 {
97 if (c->threads == 1)
98 return;
99
100 /* Always thread switch after each texture operation for now.
101 *
102 * We could do better by batching a bunch of texture fetches up and
103 * then doing one thread switch and collecting all their results
104 * afterward.
105 */
106 c->last_thrsw = vir_NOP(c);
107 c->last_thrsw->qpu.sig.thrsw = true;
108 c->last_thrsw_at_top_level = !c->in_control_flow;
109
110 /* We need to lock the scoreboard before any tlb acess happens. If this
111 * thread switch comes after we have emitted a tlb load, then it means
112 * that we can't lock on the last thread switch any more.
113 */
114 if (c->emitted_tlb_load)
115 c->lock_scoreboard_on_first_thrsw = true;
116 }
117
118 uint32_t
119 v3d_get_op_for_atomic_add(nir_intrinsic_instr *instr, unsigned src)
120 {
121 if (nir_src_is_const(instr->src[src])) {
122 int64_t add_val = nir_src_as_int(instr->src[src]);
123 if (add_val == 1)
124 return V3D_TMU_OP_WRITE_AND_READ_INC;
125 else if (add_val == -1)
126 return V3D_TMU_OP_WRITE_OR_READ_DEC;
127 }
128
129 return V3D_TMU_OP_WRITE_ADD_READ_PREFETCH;
130 }
131
132 static uint32_t
133 v3d_general_tmu_op(nir_intrinsic_instr *instr)
134 {
135 switch (instr->intrinsic) {
136 case nir_intrinsic_load_ssbo:
137 case nir_intrinsic_load_ubo:
138 case nir_intrinsic_load_uniform:
139 case nir_intrinsic_load_shared:
140 case nir_intrinsic_load_scratch:
141 case nir_intrinsic_store_ssbo:
142 case nir_intrinsic_store_shared:
143 case nir_intrinsic_store_scratch:
144 return V3D_TMU_OP_REGULAR;
145 case nir_intrinsic_ssbo_atomic_add:
146 return v3d_get_op_for_atomic_add(instr, 2);
147 case nir_intrinsic_shared_atomic_add:
148 return v3d_get_op_for_atomic_add(instr, 1);
149 case nir_intrinsic_ssbo_atomic_imin:
150 case nir_intrinsic_shared_atomic_imin:
151 return V3D_TMU_OP_WRITE_SMIN;
152 case nir_intrinsic_ssbo_atomic_umin:
153 case nir_intrinsic_shared_atomic_umin:
154 return V3D_TMU_OP_WRITE_UMIN_FULL_L1_CLEAR;
155 case nir_intrinsic_ssbo_atomic_imax:
156 case nir_intrinsic_shared_atomic_imax:
157 return V3D_TMU_OP_WRITE_SMAX;
158 case nir_intrinsic_ssbo_atomic_umax:
159 case nir_intrinsic_shared_atomic_umax:
160 return V3D_TMU_OP_WRITE_UMAX;
161 case nir_intrinsic_ssbo_atomic_and:
162 case nir_intrinsic_shared_atomic_and:
163 return V3D_TMU_OP_WRITE_AND_READ_INC;
164 case nir_intrinsic_ssbo_atomic_or:
165 case nir_intrinsic_shared_atomic_or:
166 return V3D_TMU_OP_WRITE_OR_READ_DEC;
167 case nir_intrinsic_ssbo_atomic_xor:
168 case nir_intrinsic_shared_atomic_xor:
169 return V3D_TMU_OP_WRITE_XOR_READ_NOT;
170 case nir_intrinsic_ssbo_atomic_exchange:
171 case nir_intrinsic_shared_atomic_exchange:
172 return V3D_TMU_OP_WRITE_XCHG_READ_FLUSH;
173 case nir_intrinsic_ssbo_atomic_comp_swap:
174 case nir_intrinsic_shared_atomic_comp_swap:
175 return V3D_TMU_OP_WRITE_CMPXCHG_READ_FLUSH;
176 default:
177 unreachable("unknown intrinsic op");
178 }
179 }
180
181 /**
182 * Implements indirect uniform loads and SSBO accesses through the TMU general
183 * memory access interface.
184 */
185 static void
186 ntq_emit_tmu_general(struct v3d_compile *c, nir_intrinsic_instr *instr,
187 bool is_shared_or_scratch)
188 {
189 uint32_t tmu_op = v3d_general_tmu_op(instr);
190
191 /* If we were able to replace atomic_add for an inc/dec, then we
192 * need/can to do things slightly different, like not loading the
193 * amount to add/sub, as that is implicit.
194 */
195 bool atomic_add_replaced = ((instr->intrinsic == nir_intrinsic_ssbo_atomic_add ||
196 instr->intrinsic == nir_intrinsic_shared_atomic_add) &&
197 (tmu_op == V3D_TMU_OP_WRITE_AND_READ_INC ||
198 tmu_op == V3D_TMU_OP_WRITE_OR_READ_DEC));
199 bool is_store = (instr->intrinsic == nir_intrinsic_store_ssbo ||
200 instr->intrinsic == nir_intrinsic_store_scratch ||
201 instr->intrinsic == nir_intrinsic_store_shared);
202 bool has_index = !is_shared_or_scratch;
203
204 int offset_src;
205 int tmu_writes = 1; /* address */
206 if (instr->intrinsic == nir_intrinsic_load_uniform) {
207 offset_src = 0;
208 } else if (instr->intrinsic == nir_intrinsic_load_ssbo ||
209 instr->intrinsic == nir_intrinsic_load_ubo ||
210 instr->intrinsic == nir_intrinsic_load_scratch ||
211 instr->intrinsic == nir_intrinsic_load_shared ||
212 atomic_add_replaced) {
213 offset_src = 0 + has_index;
214 } else if (is_store) {
215 offset_src = 1 + has_index;
216 for (int i = 0; i < instr->num_components; i++) {
217 vir_MOV_dest(c,
218 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD),
219 ntq_get_src(c, instr->src[0], i));
220 tmu_writes++;
221 }
222 } else {
223 offset_src = 0 + has_index;
224 vir_MOV_dest(c,
225 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD),
226 ntq_get_src(c, instr->src[1 + has_index], 0));
227 tmu_writes++;
228 if (tmu_op == V3D_TMU_OP_WRITE_CMPXCHG_READ_FLUSH) {
229 vir_MOV_dest(c,
230 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD),
231 ntq_get_src(c, instr->src[2 + has_index],
232 0));
233 tmu_writes++;
234 }
235 }
236
237 bool dynamic_src = !nir_src_is_const(instr->src[offset_src]);
238 uint32_t const_offset = 0;
239 if (!dynamic_src)
240 const_offset = nir_src_as_uint(instr->src[offset_src]);
241
242 /* Make sure we won't exceed the 16-entry TMU fifo if each thread is
243 * storing at the same time.
244 */
245 while (tmu_writes > 16 / c->threads)
246 c->threads /= 2;
247
248 struct qreg offset;
249 if (instr->intrinsic == nir_intrinsic_load_uniform) {
250 const_offset += nir_intrinsic_base(instr);
251 offset = vir_uniform(c, QUNIFORM_UBO_ADDR,
252 v3d_unit_data_create(0, const_offset));
253 const_offset = 0;
254 } else if (instr->intrinsic == nir_intrinsic_load_ubo) {
255 uint32_t index = nir_src_as_uint(instr->src[0]) + 1;
256 /* Note that QUNIFORM_UBO_ADDR takes a UBO index shifted up by
257 * 1 (0 is gallium's constant buffer 0).
258 */
259 offset = vir_uniform(c, QUNIFORM_UBO_ADDR,
260 v3d_unit_data_create(index, const_offset));
261 const_offset = 0;
262 } else if (is_shared_or_scratch) {
263 /* Shared and scratch variables have no buffer index, and all
264 * start from a common base that we set up at the start of
265 * dispatch.
266 */
267 if (instr->intrinsic == nir_intrinsic_load_scratch ||
268 instr->intrinsic == nir_intrinsic_store_scratch) {
269 offset = c->spill_base;
270 } else {
271 offset = c->cs_shared_offset;
272 const_offset += nir_intrinsic_base(instr);
273 }
274 } else {
275 offset = vir_uniform(c, QUNIFORM_SSBO_OFFSET,
276 nir_src_as_uint(instr->src[is_store ?
277 1 : 0]));
278 }
279
280 /* The spec says that for atomics, the TYPE field is ignored, but that
281 * doesn't seem to be the case for CMPXCHG. Just use the number of
282 * tmud writes we did to decide the type (or choose "32bit" for atomic
283 * reads, which has been fine).
284 */
285 int num_components;
286 if (tmu_op == V3D_TMU_OP_WRITE_CMPXCHG_READ_FLUSH)
287 num_components = 2;
288 else
289 num_components = instr->num_components;
290
291 uint32_t config = (0xffffff00 |
292 tmu_op << 3|
293 GENERAL_TMU_LOOKUP_PER_PIXEL);
294 if (num_components == 1) {
295 config |= GENERAL_TMU_LOOKUP_TYPE_32BIT_UI;
296 } else {
297 config |= GENERAL_TMU_LOOKUP_TYPE_VEC2 + num_components - 2;
298 }
299
300 if (vir_in_nonuniform_control_flow(c)) {
301 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
302 V3D_QPU_PF_PUSHZ);
303 }
304
305 struct qreg tmua;
306 if (config == ~0)
307 tmua = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUA);
308 else
309 tmua = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUAU);
310
311 struct qinst *tmu;
312 if (dynamic_src) {
313 if (const_offset != 0) {
314 offset = vir_ADD(c, offset,
315 vir_uniform_ui(c, const_offset));
316 }
317 tmu = vir_ADD_dest(c, tmua, offset,
318 ntq_get_src(c, instr->src[offset_src], 0));
319 } else {
320 if (const_offset != 0) {
321 tmu = vir_ADD_dest(c, tmua, offset,
322 vir_uniform_ui(c, const_offset));
323 } else {
324 tmu = vir_MOV_dest(c, tmua, offset);
325 }
326 }
327
328 if (config != ~0) {
329 tmu->uniform = vir_get_uniform_index(c, QUNIFORM_CONSTANT,
330 config);
331 }
332
333 if (vir_in_nonuniform_control_flow(c))
334 vir_set_cond(tmu, V3D_QPU_COND_IFA);
335
336 vir_emit_thrsw(c);
337
338 /* Read the result, or wait for the TMU op to complete. */
339 for (int i = 0; i < nir_intrinsic_dest_components(instr); i++)
340 ntq_store_dest(c, &instr->dest, i, vir_MOV(c, vir_LDTMU(c)));
341
342 if (nir_intrinsic_dest_components(instr) == 0)
343 vir_TMUWT(c);
344 }
345
346 static struct qreg *
347 ntq_init_ssa_def(struct v3d_compile *c, nir_ssa_def *def)
348 {
349 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
350 def->num_components);
351 _mesa_hash_table_insert(c->def_ht, def, qregs);
352 return qregs;
353 }
354
355 /**
356 * This function is responsible for getting VIR results into the associated
357 * storage for a NIR instruction.
358 *
359 * If it's a NIR SSA def, then we just set the associated hash table entry to
360 * the new result.
361 *
362 * If it's a NIR reg, then we need to update the existing qreg assigned to the
363 * NIR destination with the incoming value. To do that without introducing
364 * new MOVs, we require that the incoming qreg either be a uniform, or be
365 * SSA-defined by the previous VIR instruction in the block and rewritable by
366 * this function. That lets us sneak ahead and insert the SF flag beforehand
367 * (knowing that the previous instruction doesn't depend on flags) and rewrite
368 * its destination to be the NIR reg's destination
369 */
370 void
371 ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int chan,
372 struct qreg result)
373 {
374 struct qinst *last_inst = NULL;
375 if (!list_empty(&c->cur_block->instructions))
376 last_inst = (struct qinst *)c->cur_block->instructions.prev;
377
378 assert((result.file == QFILE_TEMP &&
379 last_inst && last_inst == c->defs[result.index]));
380
381 if (dest->is_ssa) {
382 assert(chan < dest->ssa.num_components);
383
384 struct qreg *qregs;
385 struct hash_entry *entry =
386 _mesa_hash_table_search(c->def_ht, &dest->ssa);
387
388 if (entry)
389 qregs = entry->data;
390 else
391 qregs = ntq_init_ssa_def(c, &dest->ssa);
392
393 qregs[chan] = result;
394 } else {
395 nir_register *reg = dest->reg.reg;
396 assert(dest->reg.base_offset == 0);
397 assert(reg->num_array_elems == 0);
398 struct hash_entry *entry =
399 _mesa_hash_table_search(c->def_ht, reg);
400 struct qreg *qregs = entry->data;
401
402 /* Insert a MOV if the source wasn't an SSA def in the
403 * previous instruction.
404 */
405 if ((vir_in_nonuniform_control_flow(c) &&
406 c->defs[last_inst->dst.index]->qpu.sig.ldunif)) {
407 result = vir_MOV(c, result);
408 last_inst = c->defs[result.index];
409 }
410
411 /* We know they're both temps, so just rewrite index. */
412 c->defs[last_inst->dst.index] = NULL;
413 last_inst->dst.index = qregs[chan].index;
414
415 /* If we're in control flow, then make this update of the reg
416 * conditional on the execution mask.
417 */
418 if (vir_in_nonuniform_control_flow(c)) {
419 last_inst->dst.index = qregs[chan].index;
420
421 /* Set the flags to the current exec mask.
422 */
423 c->cursor = vir_before_inst(last_inst);
424 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
425 V3D_QPU_PF_PUSHZ);
426 c->cursor = vir_after_inst(last_inst);
427
428 vir_set_cond(last_inst, V3D_QPU_COND_IFA);
429 }
430 }
431 }
432
433 struct qreg
434 ntq_get_src(struct v3d_compile *c, nir_src src, int i)
435 {
436 struct hash_entry *entry;
437 if (src.is_ssa) {
438 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
439 assert(i < src.ssa->num_components);
440 } else {
441 nir_register *reg = src.reg.reg;
442 entry = _mesa_hash_table_search(c->def_ht, reg);
443 assert(reg->num_array_elems == 0);
444 assert(src.reg.base_offset == 0);
445 assert(i < reg->num_components);
446 }
447
448 struct qreg *qregs = entry->data;
449 return qregs[i];
450 }
451
452 static struct qreg
453 ntq_get_alu_src(struct v3d_compile *c, nir_alu_instr *instr,
454 unsigned src)
455 {
456 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
457 unsigned chan = ffs(instr->dest.write_mask) - 1;
458 struct qreg r = ntq_get_src(c, instr->src[src].src,
459 instr->src[src].swizzle[chan]);
460
461 assert(!instr->src[src].abs);
462 assert(!instr->src[src].negate);
463
464 return r;
465 };
466
467 static struct qreg
468 ntq_minify(struct v3d_compile *c, struct qreg size, struct qreg level)
469 {
470 return vir_MAX(c, vir_SHR(c, size, level), vir_uniform_ui(c, 1));
471 }
472
473 static void
474 ntq_emit_txs(struct v3d_compile *c, nir_tex_instr *instr)
475 {
476 unsigned unit = instr->texture_index;
477 int lod_index = nir_tex_instr_src_index(instr, nir_tex_src_lod);
478 int dest_size = nir_tex_instr_dest_size(instr);
479
480 struct qreg lod = c->undef;
481 if (lod_index != -1)
482 lod = ntq_get_src(c, instr->src[lod_index].src, 0);
483
484 for (int i = 0; i < dest_size; i++) {
485 assert(i < 3);
486 enum quniform_contents contents;
487
488 if (instr->is_array && i == dest_size - 1)
489 contents = QUNIFORM_TEXTURE_ARRAY_SIZE;
490 else
491 contents = QUNIFORM_TEXTURE_WIDTH + i;
492
493 struct qreg size = vir_uniform(c, contents, unit);
494
495 switch (instr->sampler_dim) {
496 case GLSL_SAMPLER_DIM_1D:
497 case GLSL_SAMPLER_DIM_2D:
498 case GLSL_SAMPLER_DIM_MS:
499 case GLSL_SAMPLER_DIM_3D:
500 case GLSL_SAMPLER_DIM_CUBE:
501 /* Don't minify the array size. */
502 if (!(instr->is_array && i == dest_size - 1)) {
503 size = ntq_minify(c, size, lod);
504 }
505 break;
506
507 case GLSL_SAMPLER_DIM_RECT:
508 /* There's no LOD field for rects */
509 break;
510
511 default:
512 unreachable("Bad sampler type");
513 }
514
515 ntq_store_dest(c, &instr->dest, i, size);
516 }
517 }
518
519 static void
520 ntq_emit_tex(struct v3d_compile *c, nir_tex_instr *instr)
521 {
522 unsigned unit = instr->texture_index;
523
524 /* Since each texture sampling op requires uploading uniforms to
525 * reference the texture, there's no HW support for texture size and
526 * you just upload uniforms containing the size.
527 */
528 switch (instr->op) {
529 case nir_texop_query_levels:
530 ntq_store_dest(c, &instr->dest, 0,
531 vir_uniform(c, QUNIFORM_TEXTURE_LEVELS, unit));
532 return;
533 case nir_texop_txs:
534 ntq_emit_txs(c, instr);
535 return;
536 default:
537 break;
538 }
539
540 if (c->devinfo->ver >= 40)
541 v3d40_vir_emit_tex(c, instr);
542 else
543 v3d33_vir_emit_tex(c, instr);
544 }
545
546 static struct qreg
547 ntq_fsincos(struct v3d_compile *c, struct qreg src, bool is_cos)
548 {
549 struct qreg input = vir_FMUL(c, src, vir_uniform_f(c, 1.0f / M_PI));
550 if (is_cos)
551 input = vir_FADD(c, input, vir_uniform_f(c, 0.5));
552
553 struct qreg periods = vir_FROUND(c, input);
554 struct qreg sin_output = vir_SIN(c, vir_FSUB(c, input, periods));
555 return vir_XOR(c, sin_output, vir_SHL(c,
556 vir_FTOIN(c, periods),
557 vir_uniform_ui(c, -1)));
558 }
559
560 static struct qreg
561 ntq_fsign(struct v3d_compile *c, struct qreg src)
562 {
563 struct qreg t = vir_get_temp(c);
564
565 vir_MOV_dest(c, t, vir_uniform_f(c, 0.0));
566 vir_set_pf(vir_FMOV_dest(c, vir_nop_reg(), src), V3D_QPU_PF_PUSHZ);
567 vir_MOV_cond(c, V3D_QPU_COND_IFNA, t, vir_uniform_f(c, 1.0));
568 vir_set_pf(vir_FMOV_dest(c, vir_nop_reg(), src), V3D_QPU_PF_PUSHN);
569 vir_MOV_cond(c, V3D_QPU_COND_IFA, t, vir_uniform_f(c, -1.0));
570 return vir_MOV(c, t);
571 }
572
573 static void
574 emit_fragcoord_input(struct v3d_compile *c, int attr)
575 {
576 c->inputs[attr * 4 + 0] = vir_FXCD(c);
577 c->inputs[attr * 4 + 1] = vir_FYCD(c);
578 c->inputs[attr * 4 + 2] = c->payload_z;
579 c->inputs[attr * 4 + 3] = vir_RECIP(c, c->payload_w);
580 }
581
582 static struct qreg
583 emit_fragment_varying(struct v3d_compile *c, nir_variable *var,
584 uint8_t swizzle, int array_index)
585 {
586 struct qreg r3 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R3);
587 struct qreg r5 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R5);
588
589 struct qreg vary;
590 if (c->devinfo->ver >= 41) {
591 struct qinst *ldvary = vir_add_inst(V3D_QPU_A_NOP, c->undef,
592 c->undef, c->undef);
593 ldvary->qpu.sig.ldvary = true;
594 vary = vir_emit_def(c, ldvary);
595 } else {
596 vir_NOP(c)->qpu.sig.ldvary = true;
597 vary = r3;
598 }
599
600 /* For gl_PointCoord input or distance along a line, we'll be called
601 * with no nir_variable, and we don't count toward VPM size so we
602 * don't track an input slot.
603 */
604 if (!var) {
605 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
606 }
607
608 int i = c->num_inputs++;
609 c->input_slots[i] =
610 v3d_slot_from_slot_and_component(var->data.location +
611 array_index, swizzle);
612
613 switch (var->data.interpolation) {
614 case INTERP_MODE_NONE:
615 /* If a gl_FrontColor or gl_BackColor input has no interp
616 * qualifier, then if we're using glShadeModel(GL_FLAT) it
617 * needs to be flat shaded.
618 */
619 switch (var->data.location + array_index) {
620 case VARYING_SLOT_COL0:
621 case VARYING_SLOT_COL1:
622 case VARYING_SLOT_BFC0:
623 case VARYING_SLOT_BFC1:
624 if (c->fs_key->shade_model_flat) {
625 BITSET_SET(c->flat_shade_flags, i);
626 vir_MOV_dest(c, c->undef, vary);
627 return vir_MOV(c, r5);
628 } else {
629 return vir_FADD(c, vir_FMUL(c, vary,
630 c->payload_w), r5);
631 }
632 default:
633 break;
634 }
635 /* FALLTHROUGH */
636 case INTERP_MODE_SMOOTH:
637 if (var->data.centroid) {
638 BITSET_SET(c->centroid_flags, i);
639 return vir_FADD(c, vir_FMUL(c, vary,
640 c->payload_w_centroid), r5);
641 } else {
642 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
643 }
644 case INTERP_MODE_NOPERSPECTIVE:
645 BITSET_SET(c->noperspective_flags, i);
646 return vir_FADD(c, vir_MOV(c, vary), r5);
647 case INTERP_MODE_FLAT:
648 BITSET_SET(c->flat_shade_flags, i);
649 vir_MOV_dest(c, c->undef, vary);
650 return vir_MOV(c, r5);
651 default:
652 unreachable("Bad interp mode");
653 }
654 }
655
656 static void
657 emit_fragment_input(struct v3d_compile *c, int attr, nir_variable *var,
658 int array_index)
659 {
660 for (int i = 0; i < glsl_get_vector_elements(var->type); i++) {
661 int chan = var->data.location_frac + i;
662 c->inputs[attr * 4 + chan] =
663 emit_fragment_varying(c, var, chan, array_index);
664 }
665 }
666
667 static void
668 add_output(struct v3d_compile *c,
669 uint32_t decl_offset,
670 uint8_t slot,
671 uint8_t swizzle)
672 {
673 uint32_t old_array_size = c->outputs_array_size;
674 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
675 decl_offset + 1);
676
677 if (old_array_size != c->outputs_array_size) {
678 c->output_slots = reralloc(c,
679 c->output_slots,
680 struct v3d_varying_slot,
681 c->outputs_array_size);
682 }
683
684 c->output_slots[decl_offset] =
685 v3d_slot_from_slot_and_component(slot, swizzle);
686 }
687
688 /**
689 * If compare_instr is a valid comparison instruction, emits the
690 * compare_instr's comparison and returns the sel_instr's return value based
691 * on the compare_instr's result.
692 */
693 static bool
694 ntq_emit_comparison(struct v3d_compile *c,
695 nir_alu_instr *compare_instr,
696 enum v3d_qpu_cond *out_cond)
697 {
698 struct qreg src0 = ntq_get_alu_src(c, compare_instr, 0);
699 struct qreg src1;
700 if (nir_op_infos[compare_instr->op].num_inputs > 1)
701 src1 = ntq_get_alu_src(c, compare_instr, 1);
702 bool cond_invert = false;
703 struct qreg nop = vir_nop_reg();
704
705 switch (compare_instr->op) {
706 case nir_op_feq32:
707 case nir_op_seq:
708 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
709 break;
710 case nir_op_ieq32:
711 vir_set_pf(vir_XOR_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
712 break;
713
714 case nir_op_fne32:
715 case nir_op_sne:
716 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
717 cond_invert = true;
718 break;
719 case nir_op_ine32:
720 vir_set_pf(vir_XOR_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
721 cond_invert = true;
722 break;
723
724 case nir_op_fge32:
725 case nir_op_sge:
726 vir_set_pf(vir_FCMP_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
727 break;
728 case nir_op_ige32:
729 vir_set_pf(vir_MIN_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
730 cond_invert = true;
731 break;
732 case nir_op_uge32:
733 vir_set_pf(vir_SUB_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHC);
734 cond_invert = true;
735 break;
736
737 case nir_op_slt:
738 case nir_op_flt32:
739 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHN);
740 break;
741 case nir_op_ilt32:
742 vir_set_pf(vir_MIN_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
743 break;
744 case nir_op_ult32:
745 vir_set_pf(vir_SUB_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHC);
746 break;
747
748 case nir_op_i2b32:
749 vir_set_pf(vir_MOV_dest(c, nop, src0), V3D_QPU_PF_PUSHZ);
750 cond_invert = true;
751 break;
752
753 case nir_op_f2b32:
754 vir_set_pf(vir_FMOV_dest(c, nop, src0), V3D_QPU_PF_PUSHZ);
755 cond_invert = true;
756 break;
757
758 default:
759 return false;
760 }
761
762 *out_cond = cond_invert ? V3D_QPU_COND_IFNA : V3D_QPU_COND_IFA;
763
764 return true;
765 }
766
767 /* Finds an ALU instruction that generates our src value that could
768 * (potentially) be greedily emitted in the consuming instruction.
769 */
770 static struct nir_alu_instr *
771 ntq_get_alu_parent(nir_src src)
772 {
773 if (!src.is_ssa || src.ssa->parent_instr->type != nir_instr_type_alu)
774 return NULL;
775 nir_alu_instr *instr = nir_instr_as_alu(src.ssa->parent_instr);
776 if (!instr)
777 return NULL;
778
779 /* If the ALU instr's srcs are non-SSA, then we would have to avoid
780 * moving emission of the ALU instr down past another write of the
781 * src.
782 */
783 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
784 if (!instr->src[i].src.is_ssa)
785 return NULL;
786 }
787
788 return instr;
789 }
790
791 /* Turns a NIR bool into a condition code to predicate on. */
792 static enum v3d_qpu_cond
793 ntq_emit_bool_to_cond(struct v3d_compile *c, nir_src src)
794 {
795 nir_alu_instr *compare = ntq_get_alu_parent(src);
796 if (!compare)
797 goto out;
798
799 enum v3d_qpu_cond cond;
800 if (ntq_emit_comparison(c, compare, &cond))
801 return cond;
802
803 out:
804 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), ntq_get_src(c, src, 0)),
805 V3D_QPU_PF_PUSHZ);
806 return V3D_QPU_COND_IFNA;
807 }
808
809 static void
810 ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr)
811 {
812 /* This should always be lowered to ALU operations for V3D. */
813 assert(!instr->dest.saturate);
814
815 /* Vectors are special in that they have non-scalarized writemasks,
816 * and just take the first swizzle channel for each argument in order
817 * into each writemask channel.
818 */
819 if (instr->op == nir_op_vec2 ||
820 instr->op == nir_op_vec3 ||
821 instr->op == nir_op_vec4) {
822 struct qreg srcs[4];
823 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
824 srcs[i] = ntq_get_src(c, instr->src[i].src,
825 instr->src[i].swizzle[0]);
826 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
827 ntq_store_dest(c, &instr->dest.dest, i,
828 vir_MOV(c, srcs[i]));
829 return;
830 }
831
832 /* General case: We can just grab the one used channel per src. */
833 struct qreg src[nir_op_infos[instr->op].num_inputs];
834 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
835 src[i] = ntq_get_alu_src(c, instr, i);
836 }
837
838 struct qreg result;
839
840 switch (instr->op) {
841 case nir_op_mov:
842 result = vir_MOV(c, src[0]);
843 break;
844
845 case nir_op_fneg:
846 result = vir_XOR(c, src[0], vir_uniform_ui(c, 1 << 31));
847 break;
848 case nir_op_ineg:
849 result = vir_NEG(c, src[0]);
850 break;
851
852 case nir_op_fmul:
853 result = vir_FMUL(c, src[0], src[1]);
854 break;
855 case nir_op_fadd:
856 result = vir_FADD(c, src[0], src[1]);
857 break;
858 case nir_op_fsub:
859 result = vir_FSUB(c, src[0], src[1]);
860 break;
861 case nir_op_fmin:
862 result = vir_FMIN(c, src[0], src[1]);
863 break;
864 case nir_op_fmax:
865 result = vir_FMAX(c, src[0], src[1]);
866 break;
867
868 case nir_op_f2i32: {
869 nir_alu_instr *src0_alu = ntq_get_alu_parent(instr->src[0].src);
870 if (src0_alu && src0_alu->op == nir_op_fround_even) {
871 result = vir_FTOIN(c, ntq_get_alu_src(c, src0_alu, 0));
872 } else {
873 result = vir_FTOIZ(c, src[0]);
874 }
875 break;
876 }
877
878 case nir_op_f2u32:
879 result = vir_FTOUZ(c, src[0]);
880 break;
881 case nir_op_i2f32:
882 result = vir_ITOF(c, src[0]);
883 break;
884 case nir_op_u2f32:
885 result = vir_UTOF(c, src[0]);
886 break;
887 case nir_op_b2f32:
888 result = vir_AND(c, src[0], vir_uniform_f(c, 1.0));
889 break;
890 case nir_op_b2i32:
891 result = vir_AND(c, src[0], vir_uniform_ui(c, 1));
892 break;
893
894 case nir_op_iadd:
895 result = vir_ADD(c, src[0], src[1]);
896 break;
897 case nir_op_ushr:
898 result = vir_SHR(c, src[0], src[1]);
899 break;
900 case nir_op_isub:
901 result = vir_SUB(c, src[0], src[1]);
902 break;
903 case nir_op_ishr:
904 result = vir_ASR(c, src[0], src[1]);
905 break;
906 case nir_op_ishl:
907 result = vir_SHL(c, src[0], src[1]);
908 break;
909 case nir_op_imin:
910 result = vir_MIN(c, src[0], src[1]);
911 break;
912 case nir_op_umin:
913 result = vir_UMIN(c, src[0], src[1]);
914 break;
915 case nir_op_imax:
916 result = vir_MAX(c, src[0], src[1]);
917 break;
918 case nir_op_umax:
919 result = vir_UMAX(c, src[0], src[1]);
920 break;
921 case nir_op_iand:
922 result = vir_AND(c, src[0], src[1]);
923 break;
924 case nir_op_ior:
925 result = vir_OR(c, src[0], src[1]);
926 break;
927 case nir_op_ixor:
928 result = vir_XOR(c, src[0], src[1]);
929 break;
930 case nir_op_inot:
931 result = vir_NOT(c, src[0]);
932 break;
933
934 case nir_op_ufind_msb:
935 result = vir_SUB(c, vir_uniform_ui(c, 31), vir_CLZ(c, src[0]));
936 break;
937
938 case nir_op_imul:
939 result = vir_UMUL(c, src[0], src[1]);
940 break;
941
942 case nir_op_seq:
943 case nir_op_sne:
944 case nir_op_sge:
945 case nir_op_slt: {
946 enum v3d_qpu_cond cond;
947 MAYBE_UNUSED bool ok = ntq_emit_comparison(c, instr, &cond);
948 assert(ok);
949 result = vir_MOV(c, vir_SEL(c, cond,
950 vir_uniform_f(c, 1.0),
951 vir_uniform_f(c, 0.0)));
952 break;
953 }
954
955 case nir_op_i2b32:
956 case nir_op_f2b32:
957 case nir_op_feq32:
958 case nir_op_fne32:
959 case nir_op_fge32:
960 case nir_op_flt32:
961 case nir_op_ieq32:
962 case nir_op_ine32:
963 case nir_op_ige32:
964 case nir_op_uge32:
965 case nir_op_ilt32:
966 case nir_op_ult32: {
967 enum v3d_qpu_cond cond;
968 MAYBE_UNUSED bool ok = ntq_emit_comparison(c, instr, &cond);
969 assert(ok);
970 result = vir_MOV(c, vir_SEL(c, cond,
971 vir_uniform_ui(c, ~0),
972 vir_uniform_ui(c, 0)));
973 break;
974 }
975
976 case nir_op_b32csel:
977 result = vir_MOV(c,
978 vir_SEL(c,
979 ntq_emit_bool_to_cond(c, instr->src[0].src),
980 src[1], src[2]));
981 break;
982
983 case nir_op_fcsel:
984 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), src[0]),
985 V3D_QPU_PF_PUSHZ);
986 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
987 src[1], src[2]));
988 break;
989
990 case nir_op_frcp:
991 result = vir_RECIP(c, src[0]);
992 break;
993 case nir_op_frsq:
994 result = vir_RSQRT(c, src[0]);
995 break;
996 case nir_op_fexp2:
997 result = vir_EXP(c, src[0]);
998 break;
999 case nir_op_flog2:
1000 result = vir_LOG(c, src[0]);
1001 break;
1002
1003 case nir_op_fceil:
1004 result = vir_FCEIL(c, src[0]);
1005 break;
1006 case nir_op_ffloor:
1007 result = vir_FFLOOR(c, src[0]);
1008 break;
1009 case nir_op_fround_even:
1010 result = vir_FROUND(c, src[0]);
1011 break;
1012 case nir_op_ftrunc:
1013 result = vir_FTRUNC(c, src[0]);
1014 break;
1015
1016 case nir_op_fsin:
1017 result = ntq_fsincos(c, src[0], false);
1018 break;
1019 case nir_op_fcos:
1020 result = ntq_fsincos(c, src[0], true);
1021 break;
1022
1023 case nir_op_fsign:
1024 result = ntq_fsign(c, src[0]);
1025 break;
1026
1027 case nir_op_fabs: {
1028 result = vir_FMOV(c, src[0]);
1029 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_ABS);
1030 break;
1031 }
1032
1033 case nir_op_iabs:
1034 result = vir_MAX(c, src[0], vir_NEG(c, src[0]));
1035 break;
1036
1037 case nir_op_fddx:
1038 case nir_op_fddx_coarse:
1039 case nir_op_fddx_fine:
1040 result = vir_FDX(c, src[0]);
1041 break;
1042
1043 case nir_op_fddy:
1044 case nir_op_fddy_coarse:
1045 case nir_op_fddy_fine:
1046 result = vir_FDY(c, src[0]);
1047 break;
1048
1049 case nir_op_uadd_carry:
1050 vir_set_pf(vir_ADD_dest(c, vir_nop_reg(), src[0], src[1]),
1051 V3D_QPU_PF_PUSHC);
1052 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFA,
1053 vir_uniform_ui(c, ~0),
1054 vir_uniform_ui(c, 0)));
1055 break;
1056
1057 case nir_op_pack_half_2x16_split:
1058 result = vir_VFPACK(c, src[0], src[1]);
1059 break;
1060
1061 case nir_op_unpack_half_2x16_split_x:
1062 result = vir_FMOV(c, src[0]);
1063 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_L);
1064 break;
1065
1066 case nir_op_unpack_half_2x16_split_y:
1067 result = vir_FMOV(c, src[0]);
1068 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_H);
1069 break;
1070
1071 default:
1072 fprintf(stderr, "unknown NIR ALU inst: ");
1073 nir_print_instr(&instr->instr, stderr);
1074 fprintf(stderr, "\n");
1075 abort();
1076 }
1077
1078 /* We have a scalar result, so the instruction should only have a
1079 * single channel written to.
1080 */
1081 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
1082 ntq_store_dest(c, &instr->dest.dest,
1083 ffs(instr->dest.write_mask) - 1, result);
1084 }
1085
1086 /* Each TLB read/write setup (a render target or depth buffer) takes an 8-bit
1087 * specifier. They come from a register that's preloaded with 0xffffffff
1088 * (0xff gets you normal vec4 f16 RT0 writes), and when one is neaded the low
1089 * 8 bits are shifted off the bottom and 0xff shifted in from the top.
1090 */
1091 #define TLB_TYPE_F16_COLOR (3 << 6)
1092 #define TLB_TYPE_I32_COLOR (1 << 6)
1093 #define TLB_TYPE_F32_COLOR (0 << 6)
1094 #define TLB_RENDER_TARGET_SHIFT 3 /* Reversed! 7 = RT 0, 0 = RT 7. */
1095 #define TLB_SAMPLE_MODE_PER_SAMPLE (0 << 2)
1096 #define TLB_SAMPLE_MODE_PER_PIXEL (1 << 2)
1097 #define TLB_F16_SWAP_HI_LO (1 << 1)
1098 #define TLB_VEC_SIZE_4_F16 (1 << 0)
1099 #define TLB_VEC_SIZE_2_F16 (0 << 0)
1100 #define TLB_VEC_SIZE_MINUS_1_SHIFT 0
1101
1102 /* Triggers Z/Stencil testing, used when the shader state's "FS modifies Z"
1103 * flag is set.
1104 */
1105 #define TLB_TYPE_DEPTH ((2 << 6) | (0 << 4))
1106 #define TLB_DEPTH_TYPE_INVARIANT (0 << 2) /* Unmodified sideband input used */
1107 #define TLB_DEPTH_TYPE_PER_PIXEL (1 << 2) /* QPU result used */
1108 #define TLB_V42_DEPTH_TYPE_INVARIANT (0 << 3) /* Unmodified sideband input used */
1109 #define TLB_V42_DEPTH_TYPE_PER_PIXEL (1 << 3) /* QPU result used */
1110
1111 /* Stencil is a single 32-bit write. */
1112 #define TLB_TYPE_STENCIL_ALPHA ((2 << 6) | (1 << 4))
1113
1114 static void
1115 vir_emit_tlb_color_write(struct v3d_compile *c, unsigned rt)
1116 {
1117 if (!(c->fs_key->cbufs & (1 << rt)) || !c->output_color_var[rt])
1118 return;
1119
1120 struct qreg tlb_reg = vir_magic_reg(V3D_QPU_WADDR_TLB);
1121 struct qreg tlbu_reg = vir_magic_reg(V3D_QPU_WADDR_TLBU);
1122
1123 nir_variable *var = c->output_color_var[rt];
1124 struct qreg *color = &c->outputs[var->data.driver_location * 4];
1125 int num_components = glsl_get_vector_elements(var->type);
1126 uint32_t conf = 0xffffff00;
1127 struct qinst *inst;
1128
1129 conf |= TLB_SAMPLE_MODE_PER_PIXEL;
1130 conf |= (7 - rt) << TLB_RENDER_TARGET_SHIFT;
1131
1132 if (c->fs_key->swap_color_rb & (1 << rt))
1133 num_components = MAX2(num_components, 3);
1134
1135 assert(num_components != 0);
1136 switch (glsl_get_base_type(var->type)) {
1137 case GLSL_TYPE_UINT:
1138 case GLSL_TYPE_INT:
1139 /* The F32 vs I32 distinction was dropped in 4.2. */
1140 if (c->devinfo->ver < 42)
1141 conf |= TLB_TYPE_I32_COLOR;
1142 else
1143 conf |= TLB_TYPE_F32_COLOR;
1144 conf |= ((num_components - 1) << TLB_VEC_SIZE_MINUS_1_SHIFT);
1145
1146 inst = vir_MOV_dest(c, tlbu_reg, color[0]);
1147 inst->uniform =
1148 vir_get_uniform_index(c, QUNIFORM_CONSTANT, conf);
1149
1150 for (int i = 1; i < num_components; i++)
1151 inst = vir_MOV_dest(c, tlb_reg, color[i]);
1152 break;
1153
1154 default: {
1155 struct qreg r = color[0];
1156 struct qreg g = color[1];
1157 struct qreg b = color[2];
1158 struct qreg a = color[3];
1159
1160 if (c->fs_key->f32_color_rb & (1 << rt)) {
1161 conf |= TLB_TYPE_F32_COLOR;
1162 conf |= ((num_components - 1) <<
1163 TLB_VEC_SIZE_MINUS_1_SHIFT);
1164 } else {
1165 conf |= TLB_TYPE_F16_COLOR;
1166 conf |= TLB_F16_SWAP_HI_LO;
1167 if (num_components >= 3)
1168 conf |= TLB_VEC_SIZE_4_F16;
1169 else
1170 conf |= TLB_VEC_SIZE_2_F16;
1171 }
1172
1173 if (c->fs_key->swap_color_rb & (1 << rt)) {
1174 r = color[2];
1175 b = color[0];
1176 }
1177
1178 if (c->fs_key->sample_alpha_to_one)
1179 a = vir_uniform_f(c, 1.0);
1180
1181 if (c->fs_key->f32_color_rb & (1 << rt)) {
1182 inst = vir_MOV_dest(c, tlbu_reg, r);
1183 inst->uniform =
1184 vir_get_uniform_index(c, QUNIFORM_CONSTANT,
1185 conf);
1186
1187 if (num_components >= 2)
1188 vir_MOV_dest(c, tlb_reg, g);
1189 if (num_components >= 3)
1190 vir_MOV_dest(c, tlb_reg, b);
1191 if (num_components >= 4)
1192 vir_MOV_dest(c, tlb_reg, a);
1193 } else {
1194 inst = vir_VFPACK_dest(c, tlb_reg, r, g);
1195 if (conf != ~0) {
1196 inst->dst = tlbu_reg;
1197 inst->uniform =
1198 vir_get_uniform_index(c,
1199 QUNIFORM_CONSTANT,
1200 conf);
1201 }
1202
1203 if (num_components >= 3)
1204 inst = vir_VFPACK_dest(c, tlb_reg, b, a);
1205 }
1206 break;
1207 } /* default */
1208 } /* Switch */
1209 }
1210
1211 static void
1212 emit_frag_end(struct v3d_compile *c)
1213 {
1214 /* XXX
1215 if (c->output_sample_mask_index != -1) {
1216 vir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
1217 }
1218 */
1219
1220 bool has_any_tlb_color_write = false;
1221 for (int rt = 0; rt < V3D_MAX_DRAW_BUFFERS; rt++) {
1222 if (c->fs_key->cbufs & (1 << rt) && c->output_color_var[rt])
1223 has_any_tlb_color_write = true;
1224 }
1225
1226 if (c->fs_key->sample_alpha_to_coverage && c->output_color_var[0]) {
1227 struct nir_variable *var = c->output_color_var[0];
1228 struct qreg *color = &c->outputs[var->data.driver_location * 4];
1229
1230 vir_SETMSF_dest(c, vir_nop_reg(),
1231 vir_AND(c,
1232 vir_MSF(c),
1233 vir_FTOC(c, color[3])));
1234 }
1235
1236 struct qreg tlbu_reg = vir_magic_reg(V3D_QPU_WADDR_TLBU);
1237 if (c->output_position_index != -1) {
1238 struct qinst *inst = vir_MOV_dest(c, tlbu_reg,
1239 c->outputs[c->output_position_index]);
1240 uint8_t tlb_specifier = TLB_TYPE_DEPTH;
1241
1242 if (c->devinfo->ver >= 42) {
1243 tlb_specifier |= (TLB_V42_DEPTH_TYPE_PER_PIXEL |
1244 TLB_SAMPLE_MODE_PER_PIXEL);
1245 } else
1246 tlb_specifier |= TLB_DEPTH_TYPE_PER_PIXEL;
1247
1248 inst->uniform = vir_get_uniform_index(c, QUNIFORM_CONSTANT,
1249 tlb_specifier |
1250 0xffffff00);
1251 c->writes_z = true;
1252 } else if (c->s->info.fs.uses_discard ||
1253 !c->s->info.fs.early_fragment_tests ||
1254 c->fs_key->sample_alpha_to_coverage ||
1255 !has_any_tlb_color_write) {
1256 /* Emit passthrough Z if it needed to be delayed until shader
1257 * end due to potential discards.
1258 *
1259 * Since (single-threaded) fragment shaders always need a TLB
1260 * write, emit passthrouh Z if we didn't have any color
1261 * buffers and flag us as potentially discarding, so that we
1262 * can use Z as the TLB write.
1263 */
1264 c->s->info.fs.uses_discard = true;
1265
1266 struct qinst *inst = vir_MOV_dest(c, tlbu_reg,
1267 vir_nop_reg());
1268 uint8_t tlb_specifier = TLB_TYPE_DEPTH;
1269
1270 if (c->devinfo->ver >= 42) {
1271 /* The spec says the PER_PIXEL flag is ignored for
1272 * invariant writes, but the simulator demands it.
1273 */
1274 tlb_specifier |= (TLB_V42_DEPTH_TYPE_INVARIANT |
1275 TLB_SAMPLE_MODE_PER_PIXEL);
1276 } else {
1277 tlb_specifier |= TLB_DEPTH_TYPE_INVARIANT;
1278 }
1279
1280 inst->uniform = vir_get_uniform_index(c,
1281 QUNIFORM_CONSTANT,
1282 tlb_specifier |
1283 0xffffff00);
1284 c->writes_z = true;
1285 }
1286
1287 /* XXX: Performance improvement: Merge Z write and color writes TLB
1288 * uniform setup
1289 */
1290 for (int rt = 0; rt < V3D_MAX_DRAW_BUFFERS; rt++)
1291 vir_emit_tlb_color_write(c, rt);
1292 }
1293
1294 static void
1295 vir_VPM_WRITE(struct v3d_compile *c, struct qreg val, uint32_t vpm_index)
1296 {
1297 if (c->devinfo->ver >= 40) {
1298 vir_STVPMV(c, vir_uniform_ui(c, vpm_index), val);
1299 } else {
1300 /* XXX: v3d33_vir_vpm_write_setup(c); */
1301 vir_MOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_VPM), val);
1302 }
1303 }
1304
1305 static void
1306 emit_vert_end(struct v3d_compile *c)
1307 {
1308 /* GFXH-1684: VPM writes need to be complete by the end of the shader.
1309 */
1310 if (c->devinfo->ver >= 40 && c->devinfo->ver <= 42)
1311 vir_VPMWT(c);
1312 }
1313
1314 void
1315 v3d_optimize_nir(struct nir_shader *s)
1316 {
1317 bool progress;
1318 unsigned lower_flrp =
1319 (s->options->lower_flrp16 ? 16 : 0) |
1320 (s->options->lower_flrp32 ? 32 : 0) |
1321 (s->options->lower_flrp64 ? 64 : 0);
1322
1323 do {
1324 progress = false;
1325
1326 NIR_PASS_V(s, nir_lower_vars_to_ssa);
1327 NIR_PASS(progress, s, nir_lower_alu_to_scalar, NULL);
1328 NIR_PASS(progress, s, nir_lower_phis_to_scalar);
1329 NIR_PASS(progress, s, nir_copy_prop);
1330 NIR_PASS(progress, s, nir_opt_remove_phis);
1331 NIR_PASS(progress, s, nir_opt_dce);
1332 NIR_PASS(progress, s, nir_opt_dead_cf);
1333 NIR_PASS(progress, s, nir_opt_cse);
1334 NIR_PASS(progress, s, nir_opt_peephole_select, 8, true, true);
1335 NIR_PASS(progress, s, nir_opt_algebraic);
1336 NIR_PASS(progress, s, nir_opt_constant_folding);
1337
1338 if (lower_flrp != 0) {
1339 bool lower_flrp_progress = false;
1340
1341 NIR_PASS(lower_flrp_progress, s, nir_lower_flrp,
1342 lower_flrp,
1343 false /* always_precise */,
1344 s->options->lower_ffma);
1345 if (lower_flrp_progress) {
1346 NIR_PASS(progress, s, nir_opt_constant_folding);
1347 progress = true;
1348 }
1349
1350 /* Nothing should rematerialize any flrps, so we only
1351 * need to do this lowering once.
1352 */
1353 lower_flrp = 0;
1354 }
1355
1356 NIR_PASS(progress, s, nir_opt_undef);
1357 } while (progress);
1358
1359 NIR_PASS(progress, s, nir_opt_move_load_ubo);
1360 }
1361
1362 static int
1363 driver_location_compare(const void *in_a, const void *in_b)
1364 {
1365 const nir_variable *const *a = in_a;
1366 const nir_variable *const *b = in_b;
1367
1368 return (*a)->data.driver_location - (*b)->data.driver_location;
1369 }
1370
1371 static struct qreg
1372 ntq_emit_vpm_read(struct v3d_compile *c,
1373 uint32_t *num_components_queued,
1374 uint32_t *remaining,
1375 uint32_t vpm_index)
1376 {
1377 struct qreg vpm = vir_reg(QFILE_VPM, vpm_index);
1378
1379 if (c->devinfo->ver >= 40 ) {
1380 return vir_LDVPMV_IN(c,
1381 vir_uniform_ui(c,
1382 (*num_components_queued)++));
1383 }
1384
1385 if (*num_components_queued != 0) {
1386 (*num_components_queued)--;
1387 return vir_MOV(c, vpm);
1388 }
1389
1390 uint32_t num_components = MIN2(*remaining, 32);
1391
1392 v3d33_vir_vpm_read_setup(c, num_components);
1393
1394 *num_components_queued = num_components - 1;
1395 *remaining -= num_components;
1396
1397 return vir_MOV(c, vpm);
1398 }
1399
1400 static void
1401 ntq_setup_vpm_inputs(struct v3d_compile *c)
1402 {
1403 /* Figure out how many components of each vertex attribute the shader
1404 * uses. Each variable should have been split to individual
1405 * components and unused ones DCEed. The vertex fetcher will load
1406 * from the start of the attribute to the number of components we
1407 * declare we need in c->vattr_sizes[].
1408 */
1409 nir_foreach_variable(var, &c->s->inputs) {
1410 /* No VS attribute array support. */
1411 assert(MAX2(glsl_get_length(var->type), 1) == 1);
1412
1413 unsigned loc = var->data.driver_location;
1414 int start_component = var->data.location_frac;
1415 int num_components = glsl_get_components(var->type);
1416
1417 c->vattr_sizes[loc] = MAX2(c->vattr_sizes[loc],
1418 start_component + num_components);
1419 }
1420
1421 unsigned num_components = 0;
1422 uint32_t vpm_components_queued = 0;
1423 bool uses_iid = c->s->info.system_values_read &
1424 (1ull << SYSTEM_VALUE_INSTANCE_ID);
1425 bool uses_vid = c->s->info.system_values_read &
1426 (1ull << SYSTEM_VALUE_VERTEX_ID);
1427 num_components += uses_iid;
1428 num_components += uses_vid;
1429
1430 for (int i = 0; i < ARRAY_SIZE(c->vattr_sizes); i++)
1431 num_components += c->vattr_sizes[i];
1432
1433 if (uses_iid) {
1434 c->iid = ntq_emit_vpm_read(c, &vpm_components_queued,
1435 &num_components, ~0);
1436 }
1437
1438 if (uses_vid) {
1439 c->vid = ntq_emit_vpm_read(c, &vpm_components_queued,
1440 &num_components, ~0);
1441 }
1442
1443 /* The actual loads will happen directly in nir_intrinsic_load_input
1444 * on newer versions.
1445 */
1446 if (c->devinfo->ver >= 40)
1447 return;
1448
1449 for (int loc = 0; loc < ARRAY_SIZE(c->vattr_sizes); loc++) {
1450 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1451 (loc + 1) * 4);
1452
1453 for (int i = 0; i < c->vattr_sizes[loc]; i++) {
1454 c->inputs[loc * 4 + i] =
1455 ntq_emit_vpm_read(c,
1456 &vpm_components_queued,
1457 &num_components,
1458 loc * 4 + i);
1459
1460 }
1461 }
1462
1463 if (c->devinfo->ver >= 40) {
1464 assert(vpm_components_queued == num_components);
1465 } else {
1466 assert(vpm_components_queued == 0);
1467 assert(num_components == 0);
1468 }
1469 }
1470
1471 static bool
1472 var_needs_point_coord(struct v3d_compile *c, nir_variable *var)
1473 {
1474 return (var->data.location == VARYING_SLOT_PNTC ||
1475 (var->data.location >= VARYING_SLOT_VAR0 &&
1476 (c->fs_key->point_sprite_mask &
1477 (1 << (var->data.location - VARYING_SLOT_VAR0)))));
1478 }
1479
1480 static bool
1481 program_reads_point_coord(struct v3d_compile *c)
1482 {
1483 nir_foreach_variable(var, &c->s->inputs) {
1484 if (var_needs_point_coord(c, var))
1485 return true;
1486 }
1487
1488 return false;
1489 }
1490
1491 static void
1492 ntq_setup_fs_inputs(struct v3d_compile *c)
1493 {
1494 unsigned num_entries = 0;
1495 unsigned num_components = 0;
1496 nir_foreach_variable(var, &c->s->inputs) {
1497 num_entries++;
1498 num_components += glsl_get_components(var->type);
1499 }
1500
1501 nir_variable *vars[num_entries];
1502
1503 unsigned i = 0;
1504 nir_foreach_variable(var, &c->s->inputs)
1505 vars[i++] = var;
1506
1507 /* Sort the variables so that we emit the input setup in
1508 * driver_location order. This is required for VPM reads, whose data
1509 * is fetched into the VPM in driver_location (TGSI register index)
1510 * order.
1511 */
1512 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1513
1514 for (unsigned i = 0; i < num_entries; i++) {
1515 nir_variable *var = vars[i];
1516 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1517 unsigned loc = var->data.driver_location;
1518
1519 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1520 (loc + array_len) * 4);
1521
1522 if (var->data.location == VARYING_SLOT_POS) {
1523 emit_fragcoord_input(c, loc);
1524 } else if (var_needs_point_coord(c, var)) {
1525 c->inputs[loc * 4 + 0] = c->point_x;
1526 c->inputs[loc * 4 + 1] = c->point_y;
1527 } else {
1528 for (int j = 0; j < array_len; j++)
1529 emit_fragment_input(c, loc + j, var, j);
1530 }
1531 }
1532 }
1533
1534 static void
1535 ntq_setup_outputs(struct v3d_compile *c)
1536 {
1537 if (c->s->info.stage != MESA_SHADER_FRAGMENT)
1538 return;
1539
1540 nir_foreach_variable(var, &c->s->outputs) {
1541 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1542 unsigned loc = var->data.driver_location * 4;
1543
1544 assert(array_len == 1);
1545 (void)array_len;
1546
1547 for (int i = 0; i < 4 - var->data.location_frac; i++) {
1548 add_output(c, loc + var->data.location_frac + i,
1549 var->data.location,
1550 var->data.location_frac + i);
1551 }
1552
1553 switch (var->data.location) {
1554 case FRAG_RESULT_COLOR:
1555 c->output_color_var[0] = var;
1556 c->output_color_var[1] = var;
1557 c->output_color_var[2] = var;
1558 c->output_color_var[3] = var;
1559 break;
1560 case FRAG_RESULT_DATA0:
1561 case FRAG_RESULT_DATA1:
1562 case FRAG_RESULT_DATA2:
1563 case FRAG_RESULT_DATA3:
1564 c->output_color_var[var->data.location -
1565 FRAG_RESULT_DATA0] = var;
1566 break;
1567 case FRAG_RESULT_DEPTH:
1568 c->output_position_index = loc;
1569 break;
1570 case FRAG_RESULT_SAMPLE_MASK:
1571 c->output_sample_mask_index = loc;
1572 break;
1573 }
1574 }
1575 }
1576
1577 /**
1578 * Sets up the mapping from nir_register to struct qreg *.
1579 *
1580 * Each nir_register gets a struct qreg per 32-bit component being stored.
1581 */
1582 static void
1583 ntq_setup_registers(struct v3d_compile *c, struct exec_list *list)
1584 {
1585 foreach_list_typed(nir_register, nir_reg, node, list) {
1586 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1587 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1588 array_len *
1589 nir_reg->num_components);
1590
1591 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1592
1593 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1594 qregs[i] = vir_get_temp(c);
1595 }
1596 }
1597
1598 static void
1599 ntq_emit_load_const(struct v3d_compile *c, nir_load_const_instr *instr)
1600 {
1601 /* XXX perf: Experiment with using immediate loads to avoid having
1602 * these end up in the uniform stream. Watch out for breaking the
1603 * small immediates optimization in the process!
1604 */
1605 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1606 for (int i = 0; i < instr->def.num_components; i++)
1607 qregs[i] = vir_uniform_ui(c, instr->value[i].u32);
1608
1609 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1610 }
1611
1612 static void
1613 ntq_emit_ssa_undef(struct v3d_compile *c, nir_ssa_undef_instr *instr)
1614 {
1615 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1616
1617 /* VIR needs there to be *some* value, so pick 0 (same as for
1618 * ntq_setup_registers().
1619 */
1620 for (int i = 0; i < instr->def.num_components; i++)
1621 qregs[i] = vir_uniform_ui(c, 0);
1622 }
1623
1624 static void
1625 ntq_emit_image_size(struct v3d_compile *c, nir_intrinsic_instr *instr)
1626 {
1627 assert(instr->intrinsic == nir_intrinsic_image_deref_size);
1628 nir_variable *var = nir_intrinsic_get_var(instr, 0);
1629 unsigned image_index = var->data.driver_location;
1630 const struct glsl_type *sampler_type = glsl_without_array(var->type);
1631 bool is_array = glsl_sampler_type_is_array(sampler_type);
1632
1633 ntq_store_dest(c, &instr->dest, 0,
1634 vir_uniform(c, QUNIFORM_IMAGE_WIDTH, image_index));
1635 if (instr->num_components > 1) {
1636 ntq_store_dest(c, &instr->dest, 1,
1637 vir_uniform(c, QUNIFORM_IMAGE_HEIGHT,
1638 image_index));
1639 }
1640 if (instr->num_components > 2) {
1641 ntq_store_dest(c, &instr->dest, 2,
1642 vir_uniform(c,
1643 is_array ?
1644 QUNIFORM_IMAGE_ARRAY_SIZE :
1645 QUNIFORM_IMAGE_DEPTH,
1646 image_index));
1647 }
1648 }
1649
1650 static void
1651 vir_emit_tlb_color_read(struct v3d_compile *c, nir_intrinsic_instr *instr)
1652 {
1653 assert(c->s->info.stage == MESA_SHADER_FRAGMENT);
1654
1655 int rt = nir_src_as_uint(instr->src[0]);
1656 assert(rt < V3D_MAX_DRAW_BUFFERS);
1657
1658 int sample_index = nir_intrinsic_base(instr) ;
1659 assert(sample_index < V3D_MAX_SAMPLES);
1660
1661 int component = nir_intrinsic_component(instr);
1662 assert(component < 4);
1663
1664 /* We need to emit our TLB reads after we have acquired the scoreboard
1665 * lock, or the GPU will hang. Usually, we do our scoreboard locking on
1666 * the last thread switch to improve parallelism, however, that is only
1667 * guaranteed to happen before the tlb color writes.
1668 *
1669 * To fix that, we make sure we always emit a thread switch before the
1670 * first tlb color read. If that happens to be the last thread switch
1671 * we emit, then everything is fine, but otherwsie, if any code after
1672 * this point needs to emit additional thread switches, then we will
1673 * switch the strategy to locking the scoreboard on the first thread
1674 * switch instead -- see vir_emit_thrsw().
1675 */
1676 if (!c->emitted_tlb_load) {
1677 if (!c->last_thrsw_at_top_level) {
1678 assert(c->devinfo->ver >= 41);
1679 vir_emit_thrsw(c);
1680 }
1681
1682 c->emitted_tlb_load = true;
1683 }
1684
1685 struct qreg *color_reads_for_sample =
1686 &c->color_reads[(rt * V3D_MAX_SAMPLES + sample_index) * 4];
1687
1688 if (color_reads_for_sample[component].file == QFILE_NULL) {
1689 enum pipe_format rt_format = c->fs_key->color_fmt[rt].format;
1690 int num_components =
1691 util_format_get_nr_components(rt_format);
1692
1693 const bool swap_rb = c->fs_key->swap_color_rb & (1 << rt);
1694 if (swap_rb)
1695 num_components = MAX2(num_components, 3);
1696
1697 nir_variable *var = c->output_color_var[rt];
1698 enum glsl_base_type type = glsl_get_base_type(var->type);
1699
1700 bool is_int_format = type == GLSL_TYPE_INT ||
1701 type == GLSL_TYPE_UINT;
1702
1703 bool is_32b_tlb_format = is_int_format ||
1704 (c->fs_key->f32_color_rb & (1 << rt));
1705
1706 int num_samples = c->fs_key->msaa ? V3D_MAX_SAMPLES : 1;
1707
1708 uint32_t conf = 0xffffff00;
1709 conf |= c->fs_key->msaa ? TLB_SAMPLE_MODE_PER_SAMPLE :
1710 TLB_SAMPLE_MODE_PER_PIXEL;
1711 conf |= (7 - rt) << TLB_RENDER_TARGET_SHIFT;
1712
1713 if (is_32b_tlb_format) {
1714 /* The F32 vs I32 distinction was dropped in 4.2. */
1715 conf |= (c->devinfo->ver < 42 && is_int_format) ?
1716 TLB_TYPE_I32_COLOR : TLB_TYPE_F32_COLOR;
1717
1718 conf |= ((num_components - 1) <<
1719 TLB_VEC_SIZE_MINUS_1_SHIFT);
1720 } else {
1721 conf |= TLB_TYPE_F16_COLOR;
1722 conf |= TLB_F16_SWAP_HI_LO;
1723
1724 if (num_components >= 3)
1725 conf |= TLB_VEC_SIZE_4_F16;
1726 else
1727 conf |= TLB_VEC_SIZE_2_F16;
1728 }
1729
1730
1731 for (int i = 0; i < num_samples; i++) {
1732 struct qreg r, g, b, a;
1733 if (is_32b_tlb_format) {
1734 r = conf != 0xffffffff && i == 0?
1735 vir_TLBU_COLOR_READ(c, conf) :
1736 vir_TLB_COLOR_READ(c);
1737 if (num_components >= 2)
1738 g = vir_TLB_COLOR_READ(c);
1739 if (num_components >= 3)
1740 b = vir_TLB_COLOR_READ(c);
1741 if (num_components >= 4)
1742 a = vir_TLB_COLOR_READ(c);
1743 } else {
1744 struct qreg rg = conf != 0xffffffff && i == 0 ?
1745 vir_TLBU_COLOR_READ(c, conf) :
1746 vir_TLB_COLOR_READ(c);
1747 r = vir_FMOV(c, rg);
1748 vir_set_unpack(c->defs[r.index], 0,
1749 V3D_QPU_UNPACK_L);
1750 g = vir_FMOV(c, rg);
1751 vir_set_unpack(c->defs[g.index], 0,
1752 V3D_QPU_UNPACK_H);
1753
1754 if (num_components > 2) {
1755 struct qreg ba = vir_TLB_COLOR_READ(c);
1756 b = vir_FMOV(c, ba);
1757 vir_set_unpack(c->defs[b.index], 0,
1758 V3D_QPU_UNPACK_L);
1759 a = vir_FMOV(c, ba);
1760 vir_set_unpack(c->defs[a.index], 0,
1761 V3D_QPU_UNPACK_H);
1762 }
1763 }
1764
1765 struct qreg *color_reads =
1766 &c->color_reads[(rt * V3D_MAX_SAMPLES + i) * 4];
1767
1768 color_reads[0] = swap_rb ? b : r;
1769 if (num_components >= 2)
1770 color_reads[1] = g;
1771 if (num_components >= 3)
1772 color_reads[2] = swap_rb ? r : b;
1773 if (num_components >= 4)
1774 color_reads[3] = a;
1775 }
1776 }
1777
1778 assert(color_reads_for_sample[component].file != QFILE_NULL);
1779 ntq_store_dest(c, &instr->dest, 0,
1780 vir_MOV(c, color_reads_for_sample[component]));
1781 }
1782
1783 static void
1784 ntq_emit_load_uniform(struct v3d_compile *c, nir_intrinsic_instr *instr)
1785 {
1786 if (nir_src_is_const(instr->src[0])) {
1787 int offset = (nir_intrinsic_base(instr) +
1788 nir_src_as_uint(instr->src[0]));
1789 assert(offset % 4 == 0);
1790 /* We need dwords */
1791 offset = offset / 4;
1792 for (int i = 0; i < instr->num_components; i++) {
1793 ntq_store_dest(c, &instr->dest, i,
1794 vir_uniform(c, QUNIFORM_UNIFORM,
1795 offset + i));
1796 }
1797 } else {
1798 ntq_emit_tmu_general(c, instr, false);
1799 }
1800 }
1801
1802 static void
1803 ntq_emit_load_input(struct v3d_compile *c, nir_intrinsic_instr *instr)
1804 {
1805 /* XXX: Use ldvpmv (uniform offset) or ldvpmd (non-uniform offset)
1806 * and enable PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR.
1807 */
1808 unsigned offset =
1809 nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[0]);
1810
1811 if (c->s->info.stage != MESA_SHADER_FRAGMENT && c->devinfo->ver >= 40) {
1812 /* Emit the LDVPM directly now, rather than at the top
1813 * of the shader like we did for V3D 3.x (which needs
1814 * vpmsetup when not just taking the next offset).
1815 *
1816 * Note that delaying like this may introduce stalls,
1817 * as LDVPMV takes a minimum of 1 instruction but may
1818 * be slower if the VPM unit is busy with another QPU.
1819 */
1820 int index = 0;
1821 if (c->s->info.system_values_read &
1822 (1ull << SYSTEM_VALUE_INSTANCE_ID)) {
1823 index++;
1824 }
1825 if (c->s->info.system_values_read &
1826 (1ull << SYSTEM_VALUE_VERTEX_ID)) {
1827 index++;
1828 }
1829 for (int i = 0; i < offset; i++)
1830 index += c->vattr_sizes[i];
1831 index += nir_intrinsic_component(instr);
1832 for (int i = 0; i < instr->num_components; i++) {
1833 struct qreg vpm_offset = vir_uniform_ui(c, index++);
1834 ntq_store_dest(c, &instr->dest, i,
1835 vir_LDVPMV_IN(c, vpm_offset));
1836 }
1837 } else {
1838 for (int i = 0; i < instr->num_components; i++) {
1839 int comp = nir_intrinsic_component(instr) + i;
1840 ntq_store_dest(c, &instr->dest, i,
1841 vir_MOV(c, c->inputs[offset * 4 + comp]));
1842 }
1843 }
1844 }
1845
1846 static void
1847 ntq_emit_store_output(struct v3d_compile *c, nir_intrinsic_instr *instr)
1848 {
1849 /* XXX perf: Use stvpmv with uniform non-constant offsets and
1850 * stvpmd with non-uniform offsets and enable
1851 * PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR.
1852 */
1853 if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
1854 unsigned offset = ((nir_intrinsic_base(instr) +
1855 nir_src_as_uint(instr->src[1])) * 4 +
1856 nir_intrinsic_component(instr));
1857 for (int i = 0; i < instr->num_components; i++) {
1858 c->outputs[offset + i] =
1859 vir_MOV(c, ntq_get_src(c, instr->src[0], i));
1860 }
1861 } else {
1862 assert(instr->num_components == 1);
1863
1864 vir_VPM_WRITE(c,
1865 ntq_get_src(c, instr->src[0], 0),
1866 nir_intrinsic_base(instr));
1867 }
1868 }
1869
1870 static void
1871 ntq_emit_intrinsic(struct v3d_compile *c, nir_intrinsic_instr *instr)
1872 {
1873 switch (instr->intrinsic) {
1874 case nir_intrinsic_load_uniform:
1875 ntq_emit_load_uniform(c, instr);
1876 break;
1877
1878 case nir_intrinsic_load_ubo:
1879 ntq_emit_tmu_general(c, instr, false);
1880 break;
1881
1882 case nir_intrinsic_ssbo_atomic_add:
1883 case nir_intrinsic_ssbo_atomic_imin:
1884 case nir_intrinsic_ssbo_atomic_umin:
1885 case nir_intrinsic_ssbo_atomic_imax:
1886 case nir_intrinsic_ssbo_atomic_umax:
1887 case nir_intrinsic_ssbo_atomic_and:
1888 case nir_intrinsic_ssbo_atomic_or:
1889 case nir_intrinsic_ssbo_atomic_xor:
1890 case nir_intrinsic_ssbo_atomic_exchange:
1891 case nir_intrinsic_ssbo_atomic_comp_swap:
1892 case nir_intrinsic_load_ssbo:
1893 case nir_intrinsic_store_ssbo:
1894 ntq_emit_tmu_general(c, instr, false);
1895 break;
1896
1897 case nir_intrinsic_shared_atomic_add:
1898 case nir_intrinsic_shared_atomic_imin:
1899 case nir_intrinsic_shared_atomic_umin:
1900 case nir_intrinsic_shared_atomic_imax:
1901 case nir_intrinsic_shared_atomic_umax:
1902 case nir_intrinsic_shared_atomic_and:
1903 case nir_intrinsic_shared_atomic_or:
1904 case nir_intrinsic_shared_atomic_xor:
1905 case nir_intrinsic_shared_atomic_exchange:
1906 case nir_intrinsic_shared_atomic_comp_swap:
1907 case nir_intrinsic_load_shared:
1908 case nir_intrinsic_store_shared:
1909 case nir_intrinsic_load_scratch:
1910 case nir_intrinsic_store_scratch:
1911 ntq_emit_tmu_general(c, instr, true);
1912 break;
1913
1914 case nir_intrinsic_image_deref_load:
1915 case nir_intrinsic_image_deref_store:
1916 case nir_intrinsic_image_deref_atomic_add:
1917 case nir_intrinsic_image_deref_atomic_min:
1918 case nir_intrinsic_image_deref_atomic_max:
1919 case nir_intrinsic_image_deref_atomic_and:
1920 case nir_intrinsic_image_deref_atomic_or:
1921 case nir_intrinsic_image_deref_atomic_xor:
1922 case nir_intrinsic_image_deref_atomic_exchange:
1923 case nir_intrinsic_image_deref_atomic_comp_swap:
1924 v3d40_vir_emit_image_load_store(c, instr);
1925 break;
1926
1927 case nir_intrinsic_get_buffer_size:
1928 ntq_store_dest(c, &instr->dest, 0,
1929 vir_uniform(c, QUNIFORM_GET_BUFFER_SIZE,
1930 nir_src_as_uint(instr->src[0])));
1931 break;
1932
1933 case nir_intrinsic_load_user_clip_plane:
1934 for (int i = 0; i < instr->num_components; i++) {
1935 ntq_store_dest(c, &instr->dest, i,
1936 vir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1937 nir_intrinsic_ucp_id(instr) *
1938 4 + i));
1939 }
1940 break;
1941
1942 case nir_intrinsic_load_viewport_x_scale:
1943 ntq_store_dest(c, &instr->dest, 0,
1944 vir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE, 0));
1945 break;
1946
1947 case nir_intrinsic_load_viewport_y_scale:
1948 ntq_store_dest(c, &instr->dest, 0,
1949 vir_uniform(c, QUNIFORM_VIEWPORT_Y_SCALE, 0));
1950 break;
1951
1952 case nir_intrinsic_load_viewport_z_scale:
1953 ntq_store_dest(c, &instr->dest, 0,
1954 vir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0));
1955 break;
1956
1957 case nir_intrinsic_load_viewport_z_offset:
1958 ntq_store_dest(c, &instr->dest, 0,
1959 vir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0));
1960 break;
1961
1962 case nir_intrinsic_load_alpha_ref_float:
1963 ntq_store_dest(c, &instr->dest, 0,
1964 vir_uniform(c, QUNIFORM_ALPHA_REF, 0));
1965 break;
1966
1967 case nir_intrinsic_load_sample_mask_in:
1968 ntq_store_dest(c, &instr->dest, 0, vir_MSF(c));
1969 break;
1970
1971 case nir_intrinsic_load_helper_invocation:
1972 vir_set_pf(vir_MSF_dest(c, vir_nop_reg()), V3D_QPU_PF_PUSHZ);
1973 ntq_store_dest(c, &instr->dest, 0,
1974 vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFA,
1975 vir_uniform_ui(c, ~0),
1976 vir_uniform_ui(c, 0))));
1977 break;
1978
1979 case nir_intrinsic_load_front_face:
1980 /* The register contains 0 (front) or 1 (back), and we need to
1981 * turn it into a NIR bool where true means front.
1982 */
1983 ntq_store_dest(c, &instr->dest, 0,
1984 vir_ADD(c,
1985 vir_uniform_ui(c, -1),
1986 vir_REVF(c)));
1987 break;
1988
1989 case nir_intrinsic_load_instance_id:
1990 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->iid));
1991 break;
1992
1993 case nir_intrinsic_load_vertex_id:
1994 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->vid));
1995 break;
1996
1997 case nir_intrinsic_load_tlb_color_v3d:
1998 vir_emit_tlb_color_read(c, instr);
1999 break;
2000
2001 case nir_intrinsic_load_input:
2002 ntq_emit_load_input(c, instr);
2003 break;
2004
2005 case nir_intrinsic_store_output:
2006 ntq_emit_store_output(c, instr);
2007 break;
2008
2009 case nir_intrinsic_image_deref_size:
2010 ntq_emit_image_size(c, instr);
2011 break;
2012
2013 case nir_intrinsic_discard:
2014 if (vir_in_nonuniform_control_flow(c)) {
2015 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2016 V3D_QPU_PF_PUSHZ);
2017 vir_set_cond(vir_SETMSF_dest(c, vir_nop_reg(),
2018 vir_uniform_ui(c, 0)),
2019 V3D_QPU_COND_IFA);
2020 } else {
2021 vir_SETMSF_dest(c, vir_nop_reg(),
2022 vir_uniform_ui(c, 0));
2023 }
2024 break;
2025
2026 case nir_intrinsic_discard_if: {
2027 enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, instr->src[0]);
2028
2029 if (vir_in_nonuniform_control_flow(c)) {
2030 struct qinst *exec_flag = vir_MOV_dest(c, vir_nop_reg(),
2031 c->execute);
2032 if (cond == V3D_QPU_COND_IFA) {
2033 vir_set_uf(exec_flag, V3D_QPU_UF_ANDZ);
2034 } else {
2035 vir_set_uf(exec_flag, V3D_QPU_UF_NORNZ);
2036 cond = V3D_QPU_COND_IFA;
2037 }
2038 }
2039
2040 vir_set_cond(vir_SETMSF_dest(c, vir_nop_reg(),
2041 vir_uniform_ui(c, 0)), cond);
2042
2043 break;
2044 }
2045
2046 case nir_intrinsic_memory_barrier:
2047 case nir_intrinsic_memory_barrier_atomic_counter:
2048 case nir_intrinsic_memory_barrier_buffer:
2049 case nir_intrinsic_memory_barrier_image:
2050 case nir_intrinsic_memory_barrier_shared:
2051 case nir_intrinsic_group_memory_barrier:
2052 /* We don't do any instruction scheduling of these NIR
2053 * instructions between each other, so we just need to make
2054 * sure that the TMU operations before the barrier are flushed
2055 * before the ones after the barrier. That is currently
2056 * handled by having a THRSW in each of them and a LDTMU
2057 * series or a TMUWT after.
2058 */
2059 break;
2060
2061 case nir_intrinsic_barrier:
2062 /* Emit a TSY op to get all invocations in the workgroup
2063 * (actually supergroup) to block until the last invocation
2064 * reaches the TSY op.
2065 */
2066 if (c->devinfo->ver >= 42) {
2067 vir_BARRIERID_dest(c, vir_reg(QFILE_MAGIC,
2068 V3D_QPU_WADDR_SYNCB));
2069 } else {
2070 struct qinst *sync =
2071 vir_BARRIERID_dest(c,
2072 vir_reg(QFILE_MAGIC,
2073 V3D_QPU_WADDR_SYNCU));
2074 sync->uniform =
2075 vir_get_uniform_index(c, QUNIFORM_CONSTANT,
2076 0xffffff00 |
2077 V3D_TSY_WAIT_INC_CHECK);
2078
2079 }
2080
2081 /* The blocking of a TSY op only happens at the next thread
2082 * switch. No texturing may be outstanding at the time of a
2083 * TSY blocking operation.
2084 */
2085 vir_emit_thrsw(c);
2086 break;
2087
2088 case nir_intrinsic_load_num_work_groups:
2089 for (int i = 0; i < 3; i++) {
2090 ntq_store_dest(c, &instr->dest, i,
2091 vir_uniform(c, QUNIFORM_NUM_WORK_GROUPS,
2092 i));
2093 }
2094 break;
2095
2096 case nir_intrinsic_load_local_invocation_index:
2097 ntq_store_dest(c, &instr->dest, 0,
2098 vir_SHR(c, c->cs_payload[1],
2099 vir_uniform_ui(c, 32 - c->local_invocation_index_bits)));
2100 break;
2101
2102 case nir_intrinsic_load_work_group_id:
2103 ntq_store_dest(c, &instr->dest, 0,
2104 vir_AND(c, c->cs_payload[0],
2105 vir_uniform_ui(c, 0xffff)));
2106 ntq_store_dest(c, &instr->dest, 1,
2107 vir_SHR(c, c->cs_payload[0],
2108 vir_uniform_ui(c, 16)));
2109 ntq_store_dest(c, &instr->dest, 2,
2110 vir_AND(c, c->cs_payload[1],
2111 vir_uniform_ui(c, 0xffff)));
2112 break;
2113
2114 case nir_intrinsic_load_subgroup_id:
2115 ntq_store_dest(c, &instr->dest, 0, vir_EIDX(c));
2116 break;
2117
2118 default:
2119 fprintf(stderr, "Unknown intrinsic: ");
2120 nir_print_instr(&instr->instr, stderr);
2121 fprintf(stderr, "\n");
2122 break;
2123 }
2124 }
2125
2126 /* Clears (activates) the execute flags for any channels whose jump target
2127 * matches this block.
2128 *
2129 * XXX perf: Could we be using flpush/flpop somehow for our execution channel
2130 * enabling?
2131 *
2132 * XXX perf: For uniform control flow, we should be able to skip c->execute
2133 * handling entirely.
2134 */
2135 static void
2136 ntq_activate_execute_for_block(struct v3d_compile *c)
2137 {
2138 vir_set_pf(vir_XOR_dest(c, vir_nop_reg(),
2139 c->execute, vir_uniform_ui(c, c->cur_block->index)),
2140 V3D_QPU_PF_PUSHZ);
2141
2142 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
2143 }
2144
2145 static void
2146 ntq_emit_uniform_if(struct v3d_compile *c, nir_if *if_stmt)
2147 {
2148 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
2149 bool empty_else_block =
2150 (nir_else_block == nir_if_last_else_block(if_stmt) &&
2151 exec_list_is_empty(&nir_else_block->instr_list));
2152
2153 struct qblock *then_block = vir_new_block(c);
2154 struct qblock *after_block = vir_new_block(c);
2155 struct qblock *else_block;
2156 if (empty_else_block)
2157 else_block = after_block;
2158 else
2159 else_block = vir_new_block(c);
2160
2161 /* Set up the flags for the IF condition (taking the THEN branch). */
2162 enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, if_stmt->condition);
2163
2164 /* Jump to ELSE. */
2165 vir_BRANCH(c, cond == V3D_QPU_COND_IFA ?
2166 V3D_QPU_BRANCH_COND_ALLNA :
2167 V3D_QPU_BRANCH_COND_ALLA);
2168 vir_link_blocks(c->cur_block, else_block);
2169 vir_link_blocks(c->cur_block, then_block);
2170
2171 /* Process the THEN block. */
2172 vir_set_emit_block(c, then_block);
2173 ntq_emit_cf_list(c, &if_stmt->then_list);
2174
2175 if (!empty_else_block) {
2176 /* At the end of the THEN block, jump to ENDIF */
2177 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALWAYS);
2178 vir_link_blocks(c->cur_block, after_block);
2179
2180 /* Emit the else block. */
2181 vir_set_emit_block(c, else_block);
2182 ntq_emit_cf_list(c, &if_stmt->else_list);
2183 }
2184
2185 vir_link_blocks(c->cur_block, after_block);
2186
2187 vir_set_emit_block(c, after_block);
2188 }
2189
2190 static void
2191 ntq_emit_nonuniform_if(struct v3d_compile *c, nir_if *if_stmt)
2192 {
2193 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
2194 bool empty_else_block =
2195 (nir_else_block == nir_if_last_else_block(if_stmt) &&
2196 exec_list_is_empty(&nir_else_block->instr_list));
2197
2198 struct qblock *then_block = vir_new_block(c);
2199 struct qblock *after_block = vir_new_block(c);
2200 struct qblock *else_block;
2201 if (empty_else_block)
2202 else_block = after_block;
2203 else
2204 else_block = vir_new_block(c);
2205
2206 bool was_uniform_control_flow = false;
2207 if (!vir_in_nonuniform_control_flow(c)) {
2208 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
2209 was_uniform_control_flow = true;
2210 }
2211
2212 /* Set up the flags for the IF condition (taking the THEN branch). */
2213 enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, if_stmt->condition);
2214
2215 /* Update the flags+cond to mean "Taking the ELSE branch (!cond) and
2216 * was previously active (execute Z) for updating the exec flags.
2217 */
2218 if (was_uniform_control_flow) {
2219 cond = v3d_qpu_cond_invert(cond);
2220 } else {
2221 struct qinst *inst = vir_MOV_dest(c, vir_nop_reg(), c->execute);
2222 if (cond == V3D_QPU_COND_IFA) {
2223 vir_set_uf(inst, V3D_QPU_UF_NORNZ);
2224 } else {
2225 vir_set_uf(inst, V3D_QPU_UF_ANDZ);
2226 cond = V3D_QPU_COND_IFA;
2227 }
2228 }
2229
2230 vir_MOV_cond(c, cond,
2231 c->execute,
2232 vir_uniform_ui(c, else_block->index));
2233
2234 /* Jump to ELSE if nothing is active for THEN, otherwise fall
2235 * through.
2236 */
2237 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute), V3D_QPU_PF_PUSHZ);
2238 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLNA);
2239 vir_link_blocks(c->cur_block, else_block);
2240 vir_link_blocks(c->cur_block, then_block);
2241
2242 /* Process the THEN block. */
2243 vir_set_emit_block(c, then_block);
2244 ntq_emit_cf_list(c, &if_stmt->then_list);
2245
2246 if (!empty_else_block) {
2247 /* Handle the end of the THEN block. First, all currently
2248 * active channels update their execute flags to point to
2249 * ENDIF
2250 */
2251 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2252 V3D_QPU_PF_PUSHZ);
2253 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2254 vir_uniform_ui(c, after_block->index));
2255
2256 /* If everything points at ENDIF, then jump there immediately. */
2257 vir_set_pf(vir_XOR_dest(c, vir_nop_reg(),
2258 c->execute,
2259 vir_uniform_ui(c, after_block->index)),
2260 V3D_QPU_PF_PUSHZ);
2261 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLA);
2262 vir_link_blocks(c->cur_block, after_block);
2263 vir_link_blocks(c->cur_block, else_block);
2264
2265 vir_set_emit_block(c, else_block);
2266 ntq_activate_execute_for_block(c);
2267 ntq_emit_cf_list(c, &if_stmt->else_list);
2268 }
2269
2270 vir_link_blocks(c->cur_block, after_block);
2271
2272 vir_set_emit_block(c, after_block);
2273 if (was_uniform_control_flow)
2274 c->execute = c->undef;
2275 else
2276 ntq_activate_execute_for_block(c);
2277 }
2278
2279 static void
2280 ntq_emit_if(struct v3d_compile *c, nir_if *nif)
2281 {
2282 bool was_in_control_flow = c->in_control_flow;
2283 c->in_control_flow = true;
2284 if (!vir_in_nonuniform_control_flow(c) &&
2285 nir_src_is_dynamically_uniform(nif->condition)) {
2286 ntq_emit_uniform_if(c, nif);
2287 } else {
2288 ntq_emit_nonuniform_if(c, nif);
2289 }
2290 c->in_control_flow = was_in_control_flow;
2291 }
2292
2293 static void
2294 ntq_emit_jump(struct v3d_compile *c, nir_jump_instr *jump)
2295 {
2296 switch (jump->type) {
2297 case nir_jump_break:
2298 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2299 V3D_QPU_PF_PUSHZ);
2300 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2301 vir_uniform_ui(c, c->loop_break_block->index));
2302 break;
2303
2304 case nir_jump_continue:
2305 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2306 V3D_QPU_PF_PUSHZ);
2307 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2308 vir_uniform_ui(c, c->loop_cont_block->index));
2309 break;
2310
2311 case nir_jump_return:
2312 unreachable("All returns shouold be lowered\n");
2313 }
2314 }
2315
2316 static void
2317 ntq_emit_instr(struct v3d_compile *c, nir_instr *instr)
2318 {
2319 switch (instr->type) {
2320 case nir_instr_type_deref:
2321 /* ignored, will be walked by the intrinsic using it. */
2322 break;
2323
2324 case nir_instr_type_alu:
2325 ntq_emit_alu(c, nir_instr_as_alu(instr));
2326 break;
2327
2328 case nir_instr_type_intrinsic:
2329 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
2330 break;
2331
2332 case nir_instr_type_load_const:
2333 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
2334 break;
2335
2336 case nir_instr_type_ssa_undef:
2337 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
2338 break;
2339
2340 case nir_instr_type_tex:
2341 ntq_emit_tex(c, nir_instr_as_tex(instr));
2342 break;
2343
2344 case nir_instr_type_jump:
2345 ntq_emit_jump(c, nir_instr_as_jump(instr));
2346 break;
2347
2348 default:
2349 fprintf(stderr, "Unknown NIR instr type: ");
2350 nir_print_instr(instr, stderr);
2351 fprintf(stderr, "\n");
2352 abort();
2353 }
2354 }
2355
2356 static void
2357 ntq_emit_block(struct v3d_compile *c, nir_block *block)
2358 {
2359 nir_foreach_instr(instr, block) {
2360 ntq_emit_instr(c, instr);
2361 }
2362 }
2363
2364 static void ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
2365
2366 static void
2367 ntq_emit_loop(struct v3d_compile *c, nir_loop *loop)
2368 {
2369 bool was_in_control_flow = c->in_control_flow;
2370 c->in_control_flow = true;
2371
2372 bool was_uniform_control_flow = false;
2373 if (!vir_in_nonuniform_control_flow(c)) {
2374 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
2375 was_uniform_control_flow = true;
2376 }
2377
2378 struct qblock *save_loop_cont_block = c->loop_cont_block;
2379 struct qblock *save_loop_break_block = c->loop_break_block;
2380
2381 c->loop_cont_block = vir_new_block(c);
2382 c->loop_break_block = vir_new_block(c);
2383
2384 vir_link_blocks(c->cur_block, c->loop_cont_block);
2385 vir_set_emit_block(c, c->loop_cont_block);
2386 ntq_activate_execute_for_block(c);
2387
2388 ntq_emit_cf_list(c, &loop->body);
2389
2390 /* Re-enable any previous continues now, so our ANYA check below
2391 * works.
2392 *
2393 * XXX: Use the .ORZ flags update, instead.
2394 */
2395 vir_set_pf(vir_XOR_dest(c,
2396 vir_nop_reg(),
2397 c->execute,
2398 vir_uniform_ui(c, c->loop_cont_block->index)),
2399 V3D_QPU_PF_PUSHZ);
2400 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
2401
2402 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute), V3D_QPU_PF_PUSHZ);
2403
2404 struct qinst *branch = vir_BRANCH(c, V3D_QPU_BRANCH_COND_ANYA);
2405 /* Pixels that were not dispatched or have been discarded should not
2406 * contribute to looping again.
2407 */
2408 branch->qpu.branch.msfign = V3D_QPU_MSFIGN_P;
2409 vir_link_blocks(c->cur_block, c->loop_cont_block);
2410 vir_link_blocks(c->cur_block, c->loop_break_block);
2411
2412 vir_set_emit_block(c, c->loop_break_block);
2413 if (was_uniform_control_flow)
2414 c->execute = c->undef;
2415 else
2416 ntq_activate_execute_for_block(c);
2417
2418 c->loop_break_block = save_loop_break_block;
2419 c->loop_cont_block = save_loop_cont_block;
2420
2421 c->loops++;
2422
2423 c->in_control_flow = was_in_control_flow;
2424 }
2425
2426 static void
2427 ntq_emit_function(struct v3d_compile *c, nir_function_impl *func)
2428 {
2429 fprintf(stderr, "FUNCTIONS not handled.\n");
2430 abort();
2431 }
2432
2433 static void
2434 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list)
2435 {
2436 foreach_list_typed(nir_cf_node, node, node, list) {
2437 switch (node->type) {
2438 case nir_cf_node_block:
2439 ntq_emit_block(c, nir_cf_node_as_block(node));
2440 break;
2441
2442 case nir_cf_node_if:
2443 ntq_emit_if(c, nir_cf_node_as_if(node));
2444 break;
2445
2446 case nir_cf_node_loop:
2447 ntq_emit_loop(c, nir_cf_node_as_loop(node));
2448 break;
2449
2450 case nir_cf_node_function:
2451 ntq_emit_function(c, nir_cf_node_as_function(node));
2452 break;
2453
2454 default:
2455 fprintf(stderr, "Unknown NIR node type\n");
2456 abort();
2457 }
2458 }
2459 }
2460
2461 static void
2462 ntq_emit_impl(struct v3d_compile *c, nir_function_impl *impl)
2463 {
2464 ntq_setup_registers(c, &impl->registers);
2465 ntq_emit_cf_list(c, &impl->body);
2466 }
2467
2468 static void
2469 nir_to_vir(struct v3d_compile *c)
2470 {
2471 switch (c->s->info.stage) {
2472 case MESA_SHADER_FRAGMENT:
2473 c->payload_w = vir_MOV(c, vir_reg(QFILE_REG, 0));
2474 c->payload_w_centroid = vir_MOV(c, vir_reg(QFILE_REG, 1));
2475 c->payload_z = vir_MOV(c, vir_reg(QFILE_REG, 2));
2476
2477 /* V3D 4.x can disable implicit point coordinate varyings if
2478 * they are not used.
2479 */
2480 if (c->fs_key->is_points &&
2481 (c->devinfo->ver < 40 || program_reads_point_coord(c))) {
2482 c->point_x = emit_fragment_varying(c, NULL, 0, 0);
2483 c->point_y = emit_fragment_varying(c, NULL, 0, 0);
2484 c->uses_implicit_point_line_varyings = true;
2485 } else if (c->fs_key->is_lines && c->devinfo->ver < 40) {
2486 c->line_x = emit_fragment_varying(c, NULL, 0, 0);
2487 c->uses_implicit_point_line_varyings = true;
2488 }
2489 break;
2490 case MESA_SHADER_COMPUTE:
2491 /* Set up the TSO for barriers, assuming we do some. */
2492 if (c->devinfo->ver < 42) {
2493 vir_BARRIERID_dest(c, vir_reg(QFILE_MAGIC,
2494 V3D_QPU_WADDR_SYNC));
2495 }
2496
2497 c->cs_payload[0] = vir_MOV(c, vir_reg(QFILE_REG, 0));
2498 c->cs_payload[1] = vir_MOV(c, vir_reg(QFILE_REG, 2));
2499
2500 /* Set up the division between gl_LocalInvocationIndex and
2501 * wg_in_mem in the payload reg.
2502 */
2503 int wg_size = (c->s->info.cs.local_size[0] *
2504 c->s->info.cs.local_size[1] *
2505 c->s->info.cs.local_size[2]);
2506 c->local_invocation_index_bits =
2507 ffs(util_next_power_of_two(MAX2(wg_size, 64))) - 1;
2508 assert(c->local_invocation_index_bits <= 8);
2509
2510 if (c->s->info.cs.shared_size) {
2511 struct qreg wg_in_mem = vir_SHR(c, c->cs_payload[1],
2512 vir_uniform_ui(c, 16));
2513 if (c->s->info.cs.local_size[0] != 1 ||
2514 c->s->info.cs.local_size[1] != 1 ||
2515 c->s->info.cs.local_size[2] != 1) {
2516 int wg_bits = (16 -
2517 c->local_invocation_index_bits);
2518 int wg_mask = (1 << wg_bits) - 1;
2519 wg_in_mem = vir_AND(c, wg_in_mem,
2520 vir_uniform_ui(c, wg_mask));
2521 }
2522 struct qreg shared_per_wg =
2523 vir_uniform_ui(c, c->s->info.cs.shared_size);
2524
2525 c->cs_shared_offset =
2526 vir_ADD(c,
2527 vir_uniform(c, QUNIFORM_SHARED_OFFSET,0),
2528 vir_UMUL(c, wg_in_mem, shared_per_wg));
2529 }
2530 break;
2531 default:
2532 break;
2533 }
2534
2535 if (c->s->scratch_size) {
2536 v3d_setup_spill_base(c);
2537 c->spill_size += V3D_CHANNELS * c->s->scratch_size;
2538 }
2539
2540 if (c->s->info.stage == MESA_SHADER_FRAGMENT)
2541 ntq_setup_fs_inputs(c);
2542 else
2543 ntq_setup_vpm_inputs(c);
2544
2545 ntq_setup_outputs(c);
2546
2547 /* Find the main function and emit the body. */
2548 nir_foreach_function(function, c->s) {
2549 assert(strcmp(function->name, "main") == 0);
2550 assert(function->impl);
2551 ntq_emit_impl(c, function->impl);
2552 }
2553 }
2554
2555 const nir_shader_compiler_options v3d_nir_options = {
2556 .lower_all_io_to_temps = true,
2557 .lower_extract_byte = true,
2558 .lower_extract_word = true,
2559 .lower_bitfield_insert_to_shifts = true,
2560 .lower_bitfield_extract_to_shifts = true,
2561 .lower_bitfield_reverse = true,
2562 .lower_bit_count = true,
2563 .lower_cs_local_id_from_index = true,
2564 .lower_ffract = true,
2565 .lower_fmod = true,
2566 .lower_pack_unorm_2x16 = true,
2567 .lower_pack_snorm_2x16 = true,
2568 .lower_pack_unorm_4x8 = true,
2569 .lower_pack_snorm_4x8 = true,
2570 .lower_unpack_unorm_4x8 = true,
2571 .lower_unpack_snorm_4x8 = true,
2572 .lower_pack_half_2x16 = true,
2573 .lower_unpack_half_2x16 = true,
2574 .lower_fdiv = true,
2575 .lower_find_lsb = true,
2576 .lower_ffma = true,
2577 .lower_flrp32 = true,
2578 .lower_fpow = true,
2579 .lower_fsat = true,
2580 .lower_fsqrt = true,
2581 .lower_ifind_msb = true,
2582 .lower_isign = true,
2583 .lower_ldexp = true,
2584 .lower_mul_high = true,
2585 .lower_wpos_pntc = true,
2586 .lower_rotate = true,
2587 };
2588
2589 /**
2590 * When demoting a shader down to single-threaded, removes the THRSW
2591 * instructions (one will still be inserted at v3d_vir_to_qpu() for the
2592 * program end).
2593 */
2594 static void
2595 vir_remove_thrsw(struct v3d_compile *c)
2596 {
2597 vir_for_each_block(block, c) {
2598 vir_for_each_inst_safe(inst, block) {
2599 if (inst->qpu.sig.thrsw)
2600 vir_remove_instruction(c, inst);
2601 }
2602 }
2603
2604 c->last_thrsw = NULL;
2605 }
2606
2607 void
2608 vir_emit_last_thrsw(struct v3d_compile *c)
2609 {
2610 /* On V3D before 4.1, we need a TMU op to be outstanding when thread
2611 * switching, so disable threads if we didn't do any TMU ops (each of
2612 * which would have emitted a THRSW).
2613 */
2614 if (!c->last_thrsw_at_top_level && c->devinfo->ver < 41) {
2615 c->threads = 1;
2616 if (c->last_thrsw)
2617 vir_remove_thrsw(c);
2618 return;
2619 }
2620
2621 /* If we're threaded and the last THRSW was in conditional code, then
2622 * we need to emit another one so that we can flag it as the last
2623 * thrsw.
2624 */
2625 if (c->last_thrsw && !c->last_thrsw_at_top_level) {
2626 assert(c->devinfo->ver >= 41);
2627 vir_emit_thrsw(c);
2628 }
2629
2630 /* If we're threaded, then we need to mark the last THRSW instruction
2631 * so we can emit a pair of them at QPU emit time.
2632 *
2633 * For V3D 4.x, we can spawn the non-fragment shaders already in the
2634 * post-last-THRSW state, so we can skip this.
2635 */
2636 if (!c->last_thrsw && c->s->info.stage == MESA_SHADER_FRAGMENT) {
2637 assert(c->devinfo->ver >= 41);
2638 vir_emit_thrsw(c);
2639 }
2640
2641 if (c->last_thrsw)
2642 c->last_thrsw->is_last_thrsw = true;
2643 }
2644
2645 /* There's a flag in the shader for "center W is needed for reasons other than
2646 * non-centroid varyings", so we just walk the program after VIR optimization
2647 * to see if it's used. It should be harmless to set even if we only use
2648 * center W for varyings.
2649 */
2650 static void
2651 vir_check_payload_w(struct v3d_compile *c)
2652 {
2653 if (c->s->info.stage != MESA_SHADER_FRAGMENT)
2654 return;
2655
2656 vir_for_each_inst_inorder(inst, c) {
2657 for (int i = 0; i < vir_get_nsrc(inst); i++) {
2658 if (inst->src[i].file == QFILE_REG &&
2659 inst->src[i].index == 0) {
2660 c->uses_center_w = true;
2661 return;
2662 }
2663 }
2664 }
2665
2666 }
2667
2668 void
2669 v3d_nir_to_vir(struct v3d_compile *c)
2670 {
2671 if (V3D_DEBUG & (V3D_DEBUG_NIR |
2672 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2673 fprintf(stderr, "%s prog %d/%d NIR:\n",
2674 vir_get_stage_name(c),
2675 c->program_id, c->variant_id);
2676 nir_print_shader(c->s, stderr);
2677 }
2678
2679 nir_to_vir(c);
2680
2681 /* Emit the last THRSW before STVPM and TLB writes. */
2682 vir_emit_last_thrsw(c);
2683
2684 switch (c->s->info.stage) {
2685 case MESA_SHADER_FRAGMENT:
2686 emit_frag_end(c);
2687 break;
2688 case MESA_SHADER_VERTEX:
2689 emit_vert_end(c);
2690 break;
2691 case MESA_SHADER_COMPUTE:
2692 break;
2693 default:
2694 unreachable("bad stage");
2695 }
2696
2697 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2698 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2699 fprintf(stderr, "%s prog %d/%d pre-opt VIR:\n",
2700 vir_get_stage_name(c),
2701 c->program_id, c->variant_id);
2702 vir_dump(c);
2703 fprintf(stderr, "\n");
2704 }
2705
2706 vir_optimize(c);
2707
2708 vir_check_payload_w(c);
2709
2710 /* XXX perf: On VC4, we do a VIR-level instruction scheduling here.
2711 * We used that on that platform to pipeline TMU writes and reduce the
2712 * number of thread switches, as well as try (mostly successfully) to
2713 * reduce maximum register pressure to allow more threads. We should
2714 * do something of that sort for V3D -- either instruction scheduling
2715 * here, or delay the the THRSW and LDTMUs from our texture
2716 * instructions until the results are needed.
2717 */
2718
2719 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2720 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2721 fprintf(stderr, "%s prog %d/%d VIR:\n",
2722 vir_get_stage_name(c),
2723 c->program_id, c->variant_id);
2724 vir_dump(c);
2725 fprintf(stderr, "\n");
2726 }
2727
2728 /* Attempt to allocate registers for the temporaries. If we fail,
2729 * reduce thread count and try again.
2730 */
2731 int min_threads = (c->devinfo->ver >= 41) ? 2 : 1;
2732 struct qpu_reg *temp_registers;
2733 while (true) {
2734 bool spilled;
2735 temp_registers = v3d_register_allocate(c, &spilled);
2736 if (spilled)
2737 continue;
2738
2739 if (temp_registers)
2740 break;
2741
2742 if (c->threads == min_threads) {
2743 fprintf(stderr, "Failed to register allocate at %d threads:\n",
2744 c->threads);
2745 vir_dump(c);
2746 c->failed = true;
2747 return;
2748 }
2749
2750 c->threads /= 2;
2751
2752 if (c->threads == 1)
2753 vir_remove_thrsw(c);
2754 }
2755
2756 if (c->spills &&
2757 (V3D_DEBUG & (V3D_DEBUG_VIR |
2758 v3d_debug_flag_for_shader_stage(c->s->info.stage)))) {
2759 fprintf(stderr, "%s prog %d/%d spilled VIR:\n",
2760 vir_get_stage_name(c),
2761 c->program_id, c->variant_id);
2762 vir_dump(c);
2763 fprintf(stderr, "\n");
2764 }
2765
2766 v3d_vir_to_qpu(c, temp_registers);
2767 }