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[mesa.git] / src / broadcom / compiler / nir_to_vir.c
1 /*
2 * Copyright © 2016 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <inttypes.h>
25 #include "util/u_format.h"
26 #include "util/u_math.h"
27 #include "util/u_memory.h"
28 #include "util/ralloc.h"
29 #include "util/hash_table.h"
30 #include "compiler/nir/nir.h"
31 #include "compiler/nir/nir_builder.h"
32 #include "common/v3d_device_info.h"
33 #include "v3d_compiler.h"
34
35 /* We don't do any address packing. */
36 #define __gen_user_data void
37 #define __gen_address_type uint32_t
38 #define __gen_address_offset(reloc) (*reloc)
39 #define __gen_emit_reloc(cl, reloc)
40 #include "cle/v3d_packet_v41_pack.h"
41
42 #define GENERAL_TMU_LOOKUP_PER_QUAD (0 << 7)
43 #define GENERAL_TMU_LOOKUP_PER_PIXEL (1 << 7)
44 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_I (0 << 0)
45 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_I (1 << 0)
46 #define GENERAL_TMU_LOOKUP_TYPE_VEC2 (2 << 0)
47 #define GENERAL_TMU_LOOKUP_TYPE_VEC3 (3 << 0)
48 #define GENERAL_TMU_LOOKUP_TYPE_VEC4 (4 << 0)
49 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_UI (5 << 0)
50 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_UI (6 << 0)
51 #define GENERAL_TMU_LOOKUP_TYPE_32BIT_UI (7 << 0)
52
53 #define V3D_TSY_SET_QUORUM 0
54 #define V3D_TSY_INC_WAITERS 1
55 #define V3D_TSY_DEC_WAITERS 2
56 #define V3D_TSY_INC_QUORUM 3
57 #define V3D_TSY_DEC_QUORUM 4
58 #define V3D_TSY_FREE_ALL 5
59 #define V3D_TSY_RELEASE 6
60 #define V3D_TSY_ACQUIRE 7
61 #define V3D_TSY_WAIT 8
62 #define V3D_TSY_WAIT_INC 9
63 #define V3D_TSY_WAIT_CHECK 10
64 #define V3D_TSY_WAIT_INC_CHECK 11
65 #define V3D_TSY_WAIT_CV 12
66 #define V3D_TSY_INC_SEMAPHORE 13
67 #define V3D_TSY_DEC_SEMAPHORE 14
68 #define V3D_TSY_SET_QUORUM_FREE_ALL 15
69
70 static void
71 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
72
73 static void
74 resize_qreg_array(struct v3d_compile *c,
75 struct qreg **regs,
76 uint32_t *size,
77 uint32_t decl_size)
78 {
79 if (*size >= decl_size)
80 return;
81
82 uint32_t old_size = *size;
83 *size = MAX2(*size * 2, decl_size);
84 *regs = reralloc(c, *regs, struct qreg, *size);
85 if (!*regs) {
86 fprintf(stderr, "Malloc failure\n");
87 abort();
88 }
89
90 for (uint32_t i = old_size; i < *size; i++)
91 (*regs)[i] = c->undef;
92 }
93
94 void
95 vir_emit_thrsw(struct v3d_compile *c)
96 {
97 if (c->threads == 1)
98 return;
99
100 /* Always thread switch after each texture operation for now.
101 *
102 * We could do better by batching a bunch of texture fetches up and
103 * then doing one thread switch and collecting all their results
104 * afterward.
105 */
106 c->last_thrsw = vir_NOP(c);
107 c->last_thrsw->qpu.sig.thrsw = true;
108 c->last_thrsw_at_top_level = !c->in_control_flow;
109
110 /* We need to lock the scoreboard before any tlb acess happens. If this
111 * thread switch comes after we have emitted a tlb load, then it means
112 * that we can't lock on the last thread switch any more.
113 */
114 if (c->emitted_tlb_load)
115 c->lock_scoreboard_on_first_thrsw = true;
116 }
117
118 static uint32_t
119 v3d_general_tmu_op(nir_intrinsic_instr *instr)
120 {
121 switch (instr->intrinsic) {
122 case nir_intrinsic_load_ssbo:
123 case nir_intrinsic_load_ubo:
124 case nir_intrinsic_load_uniform:
125 case nir_intrinsic_load_shared:
126 case nir_intrinsic_load_scratch:
127 case nir_intrinsic_store_ssbo:
128 case nir_intrinsic_store_shared:
129 case nir_intrinsic_store_scratch:
130 return V3D_TMU_OP_REGULAR;
131 case nir_intrinsic_ssbo_atomic_add:
132 case nir_intrinsic_shared_atomic_add:
133 return V3D_TMU_OP_WRITE_ADD_READ_PREFETCH;
134 case nir_intrinsic_ssbo_atomic_imin:
135 case nir_intrinsic_shared_atomic_imin:
136 return V3D_TMU_OP_WRITE_SMIN;
137 case nir_intrinsic_ssbo_atomic_umin:
138 case nir_intrinsic_shared_atomic_umin:
139 return V3D_TMU_OP_WRITE_UMIN_FULL_L1_CLEAR;
140 case nir_intrinsic_ssbo_atomic_imax:
141 case nir_intrinsic_shared_atomic_imax:
142 return V3D_TMU_OP_WRITE_SMAX;
143 case nir_intrinsic_ssbo_atomic_umax:
144 case nir_intrinsic_shared_atomic_umax:
145 return V3D_TMU_OP_WRITE_UMAX;
146 case nir_intrinsic_ssbo_atomic_and:
147 case nir_intrinsic_shared_atomic_and:
148 return V3D_TMU_OP_WRITE_AND_READ_INC;
149 case nir_intrinsic_ssbo_atomic_or:
150 case nir_intrinsic_shared_atomic_or:
151 return V3D_TMU_OP_WRITE_OR_READ_DEC;
152 case nir_intrinsic_ssbo_atomic_xor:
153 case nir_intrinsic_shared_atomic_xor:
154 return V3D_TMU_OP_WRITE_XOR_READ_NOT;
155 case nir_intrinsic_ssbo_atomic_exchange:
156 case nir_intrinsic_shared_atomic_exchange:
157 return V3D_TMU_OP_WRITE_XCHG_READ_FLUSH;
158 case nir_intrinsic_ssbo_atomic_comp_swap:
159 case nir_intrinsic_shared_atomic_comp_swap:
160 return V3D_TMU_OP_WRITE_CMPXCHG_READ_FLUSH;
161 default:
162 unreachable("unknown intrinsic op");
163 }
164 }
165
166 /**
167 * Implements indirect uniform loads and SSBO accesses through the TMU general
168 * memory access interface.
169 */
170 static void
171 ntq_emit_tmu_general(struct v3d_compile *c, nir_intrinsic_instr *instr,
172 bool is_shared_or_scratch)
173 {
174 /* XXX perf: We should turn add/sub of 1 to inc/dec. Perhaps NIR
175 * wants to have support for inc/dec?
176 */
177
178 uint32_t tmu_op = v3d_general_tmu_op(instr);
179 bool is_store = (instr->intrinsic == nir_intrinsic_store_ssbo ||
180 instr->intrinsic == nir_intrinsic_store_scratch ||
181 instr->intrinsic == nir_intrinsic_store_shared);
182 bool has_index = !is_shared_or_scratch;
183
184 int offset_src;
185 int tmu_writes = 1; /* address */
186 if (instr->intrinsic == nir_intrinsic_load_uniform) {
187 offset_src = 0;
188 } else if (instr->intrinsic == nir_intrinsic_load_ssbo ||
189 instr->intrinsic == nir_intrinsic_load_ubo ||
190 instr->intrinsic == nir_intrinsic_load_scratch ||
191 instr->intrinsic == nir_intrinsic_load_shared) {
192 offset_src = 0 + has_index;
193 } else if (is_store) {
194 offset_src = 1 + has_index;
195 for (int i = 0; i < instr->num_components; i++) {
196 vir_MOV_dest(c,
197 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD),
198 ntq_get_src(c, instr->src[0], i));
199 tmu_writes++;
200 }
201 } else {
202 offset_src = 0 + has_index;
203 vir_MOV_dest(c,
204 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD),
205 ntq_get_src(c, instr->src[1 + has_index], 0));
206 tmu_writes++;
207 if (tmu_op == V3D_TMU_OP_WRITE_CMPXCHG_READ_FLUSH) {
208 vir_MOV_dest(c,
209 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD),
210 ntq_get_src(c, instr->src[2 + has_index],
211 0));
212 tmu_writes++;
213 }
214 }
215
216 bool dynamic_src = !nir_src_is_const(instr->src[offset_src]);
217 uint32_t const_offset = 0;
218 if (!dynamic_src)
219 const_offset = nir_src_as_uint(instr->src[offset_src]);
220
221 /* Make sure we won't exceed the 16-entry TMU fifo if each thread is
222 * storing at the same time.
223 */
224 while (tmu_writes > 16 / c->threads)
225 c->threads /= 2;
226
227 struct qreg offset;
228 if (instr->intrinsic == nir_intrinsic_load_uniform) {
229 const_offset += nir_intrinsic_base(instr);
230 offset = vir_uniform(c, QUNIFORM_UBO_ADDR,
231 v3d_unit_data_create(0, const_offset));
232 const_offset = 0;
233 } else if (instr->intrinsic == nir_intrinsic_load_ubo) {
234 uint32_t index = nir_src_as_uint(instr->src[0]) + 1;
235 /* Note that QUNIFORM_UBO_ADDR takes a UBO index shifted up by
236 * 1 (0 is gallium's constant buffer 0).
237 */
238 offset = vir_uniform(c, QUNIFORM_UBO_ADDR,
239 v3d_unit_data_create(index, const_offset));
240 const_offset = 0;
241 } else if (is_shared_or_scratch) {
242 /* Shared and scratch variables have no buffer index, and all
243 * start from a common base that we set up at the start of
244 * dispatch.
245 */
246 if (instr->intrinsic == nir_intrinsic_load_scratch ||
247 instr->intrinsic == nir_intrinsic_store_scratch) {
248 offset = c->spill_base;
249 } else {
250 offset = c->cs_shared_offset;
251 const_offset += nir_intrinsic_base(instr);
252 }
253 } else {
254 offset = vir_uniform(c, QUNIFORM_SSBO_OFFSET,
255 nir_src_as_uint(instr->src[is_store ?
256 1 : 0]));
257 }
258
259 /* The spec says that for atomics, the TYPE field is ignored, but that
260 * doesn't seem to be the case for CMPXCHG. Just use the number of
261 * tmud writes we did to decide the type (or choose "32bit" for atomic
262 * reads, which has been fine).
263 */
264 int num_components;
265 if (tmu_op == V3D_TMU_OP_WRITE_CMPXCHG_READ_FLUSH)
266 num_components = 2;
267 else
268 num_components = instr->num_components;
269
270 uint32_t config = (0xffffff00 |
271 tmu_op << 3|
272 GENERAL_TMU_LOOKUP_PER_PIXEL);
273 if (num_components == 1) {
274 config |= GENERAL_TMU_LOOKUP_TYPE_32BIT_UI;
275 } else {
276 config |= GENERAL_TMU_LOOKUP_TYPE_VEC2 + num_components - 2;
277 }
278
279 if (vir_in_nonuniform_control_flow(c)) {
280 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
281 V3D_QPU_PF_PUSHZ);
282 }
283
284 struct qreg tmua;
285 if (config == ~0)
286 tmua = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUA);
287 else
288 tmua = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUAU);
289
290 struct qinst *tmu;
291 if (dynamic_src) {
292 if (const_offset != 0) {
293 offset = vir_ADD(c, offset,
294 vir_uniform_ui(c, const_offset));
295 }
296 tmu = vir_ADD_dest(c, tmua, offset,
297 ntq_get_src(c, instr->src[offset_src], 0));
298 } else {
299 if (const_offset != 0) {
300 tmu = vir_ADD_dest(c, tmua, offset,
301 vir_uniform_ui(c, const_offset));
302 } else {
303 tmu = vir_MOV_dest(c, tmua, offset);
304 }
305 }
306
307 if (config != ~0) {
308 tmu->uniform = vir_get_uniform_index(c, QUNIFORM_CONSTANT,
309 config);
310 }
311
312 if (vir_in_nonuniform_control_flow(c))
313 vir_set_cond(tmu, V3D_QPU_COND_IFA);
314
315 vir_emit_thrsw(c);
316
317 /* Read the result, or wait for the TMU op to complete. */
318 for (int i = 0; i < nir_intrinsic_dest_components(instr); i++)
319 ntq_store_dest(c, &instr->dest, i, vir_MOV(c, vir_LDTMU(c)));
320
321 if (nir_intrinsic_dest_components(instr) == 0)
322 vir_TMUWT(c);
323 }
324
325 static struct qreg *
326 ntq_init_ssa_def(struct v3d_compile *c, nir_ssa_def *def)
327 {
328 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
329 def->num_components);
330 _mesa_hash_table_insert(c->def_ht, def, qregs);
331 return qregs;
332 }
333
334 /**
335 * This function is responsible for getting VIR results into the associated
336 * storage for a NIR instruction.
337 *
338 * If it's a NIR SSA def, then we just set the associated hash table entry to
339 * the new result.
340 *
341 * If it's a NIR reg, then we need to update the existing qreg assigned to the
342 * NIR destination with the incoming value. To do that without introducing
343 * new MOVs, we require that the incoming qreg either be a uniform, or be
344 * SSA-defined by the previous VIR instruction in the block and rewritable by
345 * this function. That lets us sneak ahead and insert the SF flag beforehand
346 * (knowing that the previous instruction doesn't depend on flags) and rewrite
347 * its destination to be the NIR reg's destination
348 */
349 void
350 ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int chan,
351 struct qreg result)
352 {
353 struct qinst *last_inst = NULL;
354 if (!list_empty(&c->cur_block->instructions))
355 last_inst = (struct qinst *)c->cur_block->instructions.prev;
356
357 assert((result.file == QFILE_TEMP &&
358 last_inst && last_inst == c->defs[result.index]));
359
360 if (dest->is_ssa) {
361 assert(chan < dest->ssa.num_components);
362
363 struct qreg *qregs;
364 struct hash_entry *entry =
365 _mesa_hash_table_search(c->def_ht, &dest->ssa);
366
367 if (entry)
368 qregs = entry->data;
369 else
370 qregs = ntq_init_ssa_def(c, &dest->ssa);
371
372 qregs[chan] = result;
373 } else {
374 nir_register *reg = dest->reg.reg;
375 assert(dest->reg.base_offset == 0);
376 assert(reg->num_array_elems == 0);
377 struct hash_entry *entry =
378 _mesa_hash_table_search(c->def_ht, reg);
379 struct qreg *qregs = entry->data;
380
381 /* Insert a MOV if the source wasn't an SSA def in the
382 * previous instruction.
383 */
384 if ((vir_in_nonuniform_control_flow(c) &&
385 c->defs[last_inst->dst.index]->qpu.sig.ldunif)) {
386 result = vir_MOV(c, result);
387 last_inst = c->defs[result.index];
388 }
389
390 /* We know they're both temps, so just rewrite index. */
391 c->defs[last_inst->dst.index] = NULL;
392 last_inst->dst.index = qregs[chan].index;
393
394 /* If we're in control flow, then make this update of the reg
395 * conditional on the execution mask.
396 */
397 if (vir_in_nonuniform_control_flow(c)) {
398 last_inst->dst.index = qregs[chan].index;
399
400 /* Set the flags to the current exec mask.
401 */
402 c->cursor = vir_before_inst(last_inst);
403 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
404 V3D_QPU_PF_PUSHZ);
405 c->cursor = vir_after_inst(last_inst);
406
407 vir_set_cond(last_inst, V3D_QPU_COND_IFA);
408 }
409 }
410 }
411
412 struct qreg
413 ntq_get_src(struct v3d_compile *c, nir_src src, int i)
414 {
415 struct hash_entry *entry;
416 if (src.is_ssa) {
417 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
418 assert(i < src.ssa->num_components);
419 } else {
420 nir_register *reg = src.reg.reg;
421 entry = _mesa_hash_table_search(c->def_ht, reg);
422 assert(reg->num_array_elems == 0);
423 assert(src.reg.base_offset == 0);
424 assert(i < reg->num_components);
425 }
426
427 struct qreg *qregs = entry->data;
428 return qregs[i];
429 }
430
431 static struct qreg
432 ntq_get_alu_src(struct v3d_compile *c, nir_alu_instr *instr,
433 unsigned src)
434 {
435 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
436 unsigned chan = ffs(instr->dest.write_mask) - 1;
437 struct qreg r = ntq_get_src(c, instr->src[src].src,
438 instr->src[src].swizzle[chan]);
439
440 assert(!instr->src[src].abs);
441 assert(!instr->src[src].negate);
442
443 return r;
444 };
445
446 static struct qreg
447 ntq_minify(struct v3d_compile *c, struct qreg size, struct qreg level)
448 {
449 return vir_MAX(c, vir_SHR(c, size, level), vir_uniform_ui(c, 1));
450 }
451
452 static void
453 ntq_emit_txs(struct v3d_compile *c, nir_tex_instr *instr)
454 {
455 unsigned unit = instr->texture_index;
456 int lod_index = nir_tex_instr_src_index(instr, nir_tex_src_lod);
457 int dest_size = nir_tex_instr_dest_size(instr);
458
459 struct qreg lod = c->undef;
460 if (lod_index != -1)
461 lod = ntq_get_src(c, instr->src[lod_index].src, 0);
462
463 for (int i = 0; i < dest_size; i++) {
464 assert(i < 3);
465 enum quniform_contents contents;
466
467 if (instr->is_array && i == dest_size - 1)
468 contents = QUNIFORM_TEXTURE_ARRAY_SIZE;
469 else
470 contents = QUNIFORM_TEXTURE_WIDTH + i;
471
472 struct qreg size = vir_uniform(c, contents, unit);
473
474 switch (instr->sampler_dim) {
475 case GLSL_SAMPLER_DIM_1D:
476 case GLSL_SAMPLER_DIM_2D:
477 case GLSL_SAMPLER_DIM_MS:
478 case GLSL_SAMPLER_DIM_3D:
479 case GLSL_SAMPLER_DIM_CUBE:
480 /* Don't minify the array size. */
481 if (!(instr->is_array && i == dest_size - 1)) {
482 size = ntq_minify(c, size, lod);
483 }
484 break;
485
486 case GLSL_SAMPLER_DIM_RECT:
487 /* There's no LOD field for rects */
488 break;
489
490 default:
491 unreachable("Bad sampler type");
492 }
493
494 ntq_store_dest(c, &instr->dest, i, size);
495 }
496 }
497
498 static void
499 ntq_emit_tex(struct v3d_compile *c, nir_tex_instr *instr)
500 {
501 unsigned unit = instr->texture_index;
502
503 /* Since each texture sampling op requires uploading uniforms to
504 * reference the texture, there's no HW support for texture size and
505 * you just upload uniforms containing the size.
506 */
507 switch (instr->op) {
508 case nir_texop_query_levels:
509 ntq_store_dest(c, &instr->dest, 0,
510 vir_uniform(c, QUNIFORM_TEXTURE_LEVELS, unit));
511 return;
512 case nir_texop_txs:
513 ntq_emit_txs(c, instr);
514 return;
515 default:
516 break;
517 }
518
519 if (c->devinfo->ver >= 40)
520 v3d40_vir_emit_tex(c, instr);
521 else
522 v3d33_vir_emit_tex(c, instr);
523 }
524
525 static struct qreg
526 ntq_fsincos(struct v3d_compile *c, struct qreg src, bool is_cos)
527 {
528 struct qreg input = vir_FMUL(c, src, vir_uniform_f(c, 1.0f / M_PI));
529 if (is_cos)
530 input = vir_FADD(c, input, vir_uniform_f(c, 0.5));
531
532 struct qreg periods = vir_FROUND(c, input);
533 struct qreg sin_output = vir_SIN(c, vir_FSUB(c, input, periods));
534 return vir_XOR(c, sin_output, vir_SHL(c,
535 vir_FTOIN(c, periods),
536 vir_uniform_ui(c, -1)));
537 }
538
539 static struct qreg
540 ntq_fsign(struct v3d_compile *c, struct qreg src)
541 {
542 struct qreg t = vir_get_temp(c);
543
544 vir_MOV_dest(c, t, vir_uniform_f(c, 0.0));
545 vir_set_pf(vir_FMOV_dest(c, vir_nop_reg(), src), V3D_QPU_PF_PUSHZ);
546 vir_MOV_cond(c, V3D_QPU_COND_IFNA, t, vir_uniform_f(c, 1.0));
547 vir_set_pf(vir_FMOV_dest(c, vir_nop_reg(), src), V3D_QPU_PF_PUSHN);
548 vir_MOV_cond(c, V3D_QPU_COND_IFA, t, vir_uniform_f(c, -1.0));
549 return vir_MOV(c, t);
550 }
551
552 static void
553 emit_fragcoord_input(struct v3d_compile *c, int attr)
554 {
555 c->inputs[attr * 4 + 0] = vir_FXCD(c);
556 c->inputs[attr * 4 + 1] = vir_FYCD(c);
557 c->inputs[attr * 4 + 2] = c->payload_z;
558 c->inputs[attr * 4 + 3] = vir_RECIP(c, c->payload_w);
559 }
560
561 static struct qreg
562 emit_fragment_varying(struct v3d_compile *c, nir_variable *var,
563 uint8_t swizzle, int array_index)
564 {
565 struct qreg r3 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R3);
566 struct qreg r5 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R5);
567
568 struct qreg vary;
569 if (c->devinfo->ver >= 41) {
570 struct qinst *ldvary = vir_add_inst(V3D_QPU_A_NOP, c->undef,
571 c->undef, c->undef);
572 ldvary->qpu.sig.ldvary = true;
573 vary = vir_emit_def(c, ldvary);
574 } else {
575 vir_NOP(c)->qpu.sig.ldvary = true;
576 vary = r3;
577 }
578
579 /* For gl_PointCoord input or distance along a line, we'll be called
580 * with no nir_variable, and we don't count toward VPM size so we
581 * don't track an input slot.
582 */
583 if (!var) {
584 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
585 }
586
587 int i = c->num_inputs++;
588 c->input_slots[i] =
589 v3d_slot_from_slot_and_component(var->data.location +
590 array_index, swizzle);
591
592 switch (var->data.interpolation) {
593 case INTERP_MODE_NONE:
594 /* If a gl_FrontColor or gl_BackColor input has no interp
595 * qualifier, then if we're using glShadeModel(GL_FLAT) it
596 * needs to be flat shaded.
597 */
598 switch (var->data.location + array_index) {
599 case VARYING_SLOT_COL0:
600 case VARYING_SLOT_COL1:
601 case VARYING_SLOT_BFC0:
602 case VARYING_SLOT_BFC1:
603 if (c->fs_key->shade_model_flat) {
604 BITSET_SET(c->flat_shade_flags, i);
605 vir_MOV_dest(c, c->undef, vary);
606 return vir_MOV(c, r5);
607 } else {
608 return vir_FADD(c, vir_FMUL(c, vary,
609 c->payload_w), r5);
610 }
611 default:
612 break;
613 }
614 /* FALLTHROUGH */
615 case INTERP_MODE_SMOOTH:
616 if (var->data.centroid) {
617 BITSET_SET(c->centroid_flags, i);
618 return vir_FADD(c, vir_FMUL(c, vary,
619 c->payload_w_centroid), r5);
620 } else {
621 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
622 }
623 case INTERP_MODE_NOPERSPECTIVE:
624 BITSET_SET(c->noperspective_flags, i);
625 return vir_FADD(c, vir_MOV(c, vary), r5);
626 case INTERP_MODE_FLAT:
627 BITSET_SET(c->flat_shade_flags, i);
628 vir_MOV_dest(c, c->undef, vary);
629 return vir_MOV(c, r5);
630 default:
631 unreachable("Bad interp mode");
632 }
633 }
634
635 static void
636 emit_fragment_input(struct v3d_compile *c, int attr, nir_variable *var,
637 int array_index)
638 {
639 for (int i = 0; i < glsl_get_vector_elements(var->type); i++) {
640 int chan = var->data.location_frac + i;
641 c->inputs[attr * 4 + chan] =
642 emit_fragment_varying(c, var, chan, array_index);
643 }
644 }
645
646 static void
647 add_output(struct v3d_compile *c,
648 uint32_t decl_offset,
649 uint8_t slot,
650 uint8_t swizzle)
651 {
652 uint32_t old_array_size = c->outputs_array_size;
653 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
654 decl_offset + 1);
655
656 if (old_array_size != c->outputs_array_size) {
657 c->output_slots = reralloc(c,
658 c->output_slots,
659 struct v3d_varying_slot,
660 c->outputs_array_size);
661 }
662
663 c->output_slots[decl_offset] =
664 v3d_slot_from_slot_and_component(slot, swizzle);
665 }
666
667 /**
668 * If compare_instr is a valid comparison instruction, emits the
669 * compare_instr's comparison and returns the sel_instr's return value based
670 * on the compare_instr's result.
671 */
672 static bool
673 ntq_emit_comparison(struct v3d_compile *c,
674 nir_alu_instr *compare_instr,
675 enum v3d_qpu_cond *out_cond)
676 {
677 struct qreg src0 = ntq_get_alu_src(c, compare_instr, 0);
678 struct qreg src1;
679 if (nir_op_infos[compare_instr->op].num_inputs > 1)
680 src1 = ntq_get_alu_src(c, compare_instr, 1);
681 bool cond_invert = false;
682 struct qreg nop = vir_nop_reg();
683
684 switch (compare_instr->op) {
685 case nir_op_feq32:
686 case nir_op_seq:
687 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
688 break;
689 case nir_op_ieq32:
690 vir_set_pf(vir_XOR_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
691 break;
692
693 case nir_op_fne32:
694 case nir_op_sne:
695 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
696 cond_invert = true;
697 break;
698 case nir_op_ine32:
699 vir_set_pf(vir_XOR_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
700 cond_invert = true;
701 break;
702
703 case nir_op_fge32:
704 case nir_op_sge:
705 vir_set_pf(vir_FCMP_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
706 break;
707 case nir_op_ige32:
708 vir_set_pf(vir_MIN_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
709 cond_invert = true;
710 break;
711 case nir_op_uge32:
712 vir_set_pf(vir_SUB_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHC);
713 cond_invert = true;
714 break;
715
716 case nir_op_slt:
717 case nir_op_flt32:
718 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHN);
719 break;
720 case nir_op_ilt32:
721 vir_set_pf(vir_MIN_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
722 break;
723 case nir_op_ult32:
724 vir_set_pf(vir_SUB_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHC);
725 break;
726
727 case nir_op_i2b32:
728 vir_set_pf(vir_MOV_dest(c, nop, src0), V3D_QPU_PF_PUSHZ);
729 cond_invert = true;
730 break;
731
732 case nir_op_f2b32:
733 vir_set_pf(vir_FMOV_dest(c, nop, src0), V3D_QPU_PF_PUSHZ);
734 cond_invert = true;
735 break;
736
737 default:
738 return false;
739 }
740
741 *out_cond = cond_invert ? V3D_QPU_COND_IFNA : V3D_QPU_COND_IFA;
742
743 return true;
744 }
745
746 /* Finds an ALU instruction that generates our src value that could
747 * (potentially) be greedily emitted in the consuming instruction.
748 */
749 static struct nir_alu_instr *
750 ntq_get_alu_parent(nir_src src)
751 {
752 if (!src.is_ssa || src.ssa->parent_instr->type != nir_instr_type_alu)
753 return NULL;
754 nir_alu_instr *instr = nir_instr_as_alu(src.ssa->parent_instr);
755 if (!instr)
756 return NULL;
757
758 /* If the ALU instr's srcs are non-SSA, then we would have to avoid
759 * moving emission of the ALU instr down past another write of the
760 * src.
761 */
762 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
763 if (!instr->src[i].src.is_ssa)
764 return NULL;
765 }
766
767 return instr;
768 }
769
770 /* Turns a NIR bool into a condition code to predicate on. */
771 static enum v3d_qpu_cond
772 ntq_emit_bool_to_cond(struct v3d_compile *c, nir_src src)
773 {
774 nir_alu_instr *compare = ntq_get_alu_parent(src);
775 if (!compare)
776 goto out;
777
778 enum v3d_qpu_cond cond;
779 if (ntq_emit_comparison(c, compare, &cond))
780 return cond;
781
782 out:
783 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), ntq_get_src(c, src, 0)),
784 V3D_QPU_PF_PUSHZ);
785 return V3D_QPU_COND_IFNA;
786 }
787
788 static void
789 ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr)
790 {
791 /* This should always be lowered to ALU operations for V3D. */
792 assert(!instr->dest.saturate);
793
794 /* Vectors are special in that they have non-scalarized writemasks,
795 * and just take the first swizzle channel for each argument in order
796 * into each writemask channel.
797 */
798 if (instr->op == nir_op_vec2 ||
799 instr->op == nir_op_vec3 ||
800 instr->op == nir_op_vec4) {
801 struct qreg srcs[4];
802 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
803 srcs[i] = ntq_get_src(c, instr->src[i].src,
804 instr->src[i].swizzle[0]);
805 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
806 ntq_store_dest(c, &instr->dest.dest, i,
807 vir_MOV(c, srcs[i]));
808 return;
809 }
810
811 /* General case: We can just grab the one used channel per src. */
812 struct qreg src[nir_op_infos[instr->op].num_inputs];
813 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
814 src[i] = ntq_get_alu_src(c, instr, i);
815 }
816
817 struct qreg result;
818
819 switch (instr->op) {
820 case nir_op_mov:
821 result = vir_MOV(c, src[0]);
822 break;
823
824 case nir_op_fneg:
825 result = vir_XOR(c, src[0], vir_uniform_ui(c, 1 << 31));
826 break;
827 case nir_op_ineg:
828 result = vir_NEG(c, src[0]);
829 break;
830
831 case nir_op_fmul:
832 result = vir_FMUL(c, src[0], src[1]);
833 break;
834 case nir_op_fadd:
835 result = vir_FADD(c, src[0], src[1]);
836 break;
837 case nir_op_fsub:
838 result = vir_FSUB(c, src[0], src[1]);
839 break;
840 case nir_op_fmin:
841 result = vir_FMIN(c, src[0], src[1]);
842 break;
843 case nir_op_fmax:
844 result = vir_FMAX(c, src[0], src[1]);
845 break;
846
847 case nir_op_f2i32: {
848 nir_alu_instr *src0_alu = ntq_get_alu_parent(instr->src[0].src);
849 if (src0_alu && src0_alu->op == nir_op_fround_even) {
850 result = vir_FTOIN(c, ntq_get_alu_src(c, src0_alu, 0));
851 } else {
852 result = vir_FTOIZ(c, src[0]);
853 }
854 break;
855 }
856
857 case nir_op_f2u32:
858 result = vir_FTOUZ(c, src[0]);
859 break;
860 case nir_op_i2f32:
861 result = vir_ITOF(c, src[0]);
862 break;
863 case nir_op_u2f32:
864 result = vir_UTOF(c, src[0]);
865 break;
866 case nir_op_b2f32:
867 result = vir_AND(c, src[0], vir_uniform_f(c, 1.0));
868 break;
869 case nir_op_b2i32:
870 result = vir_AND(c, src[0], vir_uniform_ui(c, 1));
871 break;
872
873 case nir_op_iadd:
874 result = vir_ADD(c, src[0], src[1]);
875 break;
876 case nir_op_ushr:
877 result = vir_SHR(c, src[0], src[1]);
878 break;
879 case nir_op_isub:
880 result = vir_SUB(c, src[0], src[1]);
881 break;
882 case nir_op_ishr:
883 result = vir_ASR(c, src[0], src[1]);
884 break;
885 case nir_op_ishl:
886 result = vir_SHL(c, src[0], src[1]);
887 break;
888 case nir_op_imin:
889 result = vir_MIN(c, src[0], src[1]);
890 break;
891 case nir_op_umin:
892 result = vir_UMIN(c, src[0], src[1]);
893 break;
894 case nir_op_imax:
895 result = vir_MAX(c, src[0], src[1]);
896 break;
897 case nir_op_umax:
898 result = vir_UMAX(c, src[0], src[1]);
899 break;
900 case nir_op_iand:
901 result = vir_AND(c, src[0], src[1]);
902 break;
903 case nir_op_ior:
904 result = vir_OR(c, src[0], src[1]);
905 break;
906 case nir_op_ixor:
907 result = vir_XOR(c, src[0], src[1]);
908 break;
909 case nir_op_inot:
910 result = vir_NOT(c, src[0]);
911 break;
912
913 case nir_op_ufind_msb:
914 result = vir_SUB(c, vir_uniform_ui(c, 31), vir_CLZ(c, src[0]));
915 break;
916
917 case nir_op_imul:
918 result = vir_UMUL(c, src[0], src[1]);
919 break;
920
921 case nir_op_seq:
922 case nir_op_sne:
923 case nir_op_sge:
924 case nir_op_slt: {
925 enum v3d_qpu_cond cond;
926 MAYBE_UNUSED bool ok = ntq_emit_comparison(c, instr, &cond);
927 assert(ok);
928 result = vir_MOV(c, vir_SEL(c, cond,
929 vir_uniform_f(c, 1.0),
930 vir_uniform_f(c, 0.0)));
931 break;
932 }
933
934 case nir_op_i2b32:
935 case nir_op_f2b32:
936 case nir_op_feq32:
937 case nir_op_fne32:
938 case nir_op_fge32:
939 case nir_op_flt32:
940 case nir_op_ieq32:
941 case nir_op_ine32:
942 case nir_op_ige32:
943 case nir_op_uge32:
944 case nir_op_ilt32:
945 case nir_op_ult32: {
946 enum v3d_qpu_cond cond;
947 MAYBE_UNUSED bool ok = ntq_emit_comparison(c, instr, &cond);
948 assert(ok);
949 result = vir_MOV(c, vir_SEL(c, cond,
950 vir_uniform_ui(c, ~0),
951 vir_uniform_ui(c, 0)));
952 break;
953 }
954
955 case nir_op_b32csel:
956 result = vir_MOV(c,
957 vir_SEL(c,
958 ntq_emit_bool_to_cond(c, instr->src[0].src),
959 src[1], src[2]));
960 break;
961
962 case nir_op_fcsel:
963 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), src[0]),
964 V3D_QPU_PF_PUSHZ);
965 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
966 src[1], src[2]));
967 break;
968
969 case nir_op_frcp:
970 result = vir_RECIP(c, src[0]);
971 break;
972 case nir_op_frsq:
973 result = vir_RSQRT(c, src[0]);
974 break;
975 case nir_op_fexp2:
976 result = vir_EXP(c, src[0]);
977 break;
978 case nir_op_flog2:
979 result = vir_LOG(c, src[0]);
980 break;
981
982 case nir_op_fceil:
983 result = vir_FCEIL(c, src[0]);
984 break;
985 case nir_op_ffloor:
986 result = vir_FFLOOR(c, src[0]);
987 break;
988 case nir_op_fround_even:
989 result = vir_FROUND(c, src[0]);
990 break;
991 case nir_op_ftrunc:
992 result = vir_FTRUNC(c, src[0]);
993 break;
994
995 case nir_op_fsin:
996 result = ntq_fsincos(c, src[0], false);
997 break;
998 case nir_op_fcos:
999 result = ntq_fsincos(c, src[0], true);
1000 break;
1001
1002 case nir_op_fsign:
1003 result = ntq_fsign(c, src[0]);
1004 break;
1005
1006 case nir_op_fabs: {
1007 result = vir_FMOV(c, src[0]);
1008 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_ABS);
1009 break;
1010 }
1011
1012 case nir_op_iabs:
1013 result = vir_MAX(c, src[0], vir_NEG(c, src[0]));
1014 break;
1015
1016 case nir_op_fddx:
1017 case nir_op_fddx_coarse:
1018 case nir_op_fddx_fine:
1019 result = vir_FDX(c, src[0]);
1020 break;
1021
1022 case nir_op_fddy:
1023 case nir_op_fddy_coarse:
1024 case nir_op_fddy_fine:
1025 result = vir_FDY(c, src[0]);
1026 break;
1027
1028 case nir_op_uadd_carry:
1029 vir_set_pf(vir_ADD_dest(c, vir_nop_reg(), src[0], src[1]),
1030 V3D_QPU_PF_PUSHC);
1031 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFA,
1032 vir_uniform_ui(c, ~0),
1033 vir_uniform_ui(c, 0)));
1034 break;
1035
1036 case nir_op_pack_half_2x16_split:
1037 result = vir_VFPACK(c, src[0], src[1]);
1038 break;
1039
1040 case nir_op_unpack_half_2x16_split_x:
1041 result = vir_FMOV(c, src[0]);
1042 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_L);
1043 break;
1044
1045 case nir_op_unpack_half_2x16_split_y:
1046 result = vir_FMOV(c, src[0]);
1047 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_H);
1048 break;
1049
1050 default:
1051 fprintf(stderr, "unknown NIR ALU inst: ");
1052 nir_print_instr(&instr->instr, stderr);
1053 fprintf(stderr, "\n");
1054 abort();
1055 }
1056
1057 /* We have a scalar result, so the instruction should only have a
1058 * single channel written to.
1059 */
1060 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
1061 ntq_store_dest(c, &instr->dest.dest,
1062 ffs(instr->dest.write_mask) - 1, result);
1063 }
1064
1065 /* Each TLB read/write setup (a render target or depth buffer) takes an 8-bit
1066 * specifier. They come from a register that's preloaded with 0xffffffff
1067 * (0xff gets you normal vec4 f16 RT0 writes), and when one is neaded the low
1068 * 8 bits are shifted off the bottom and 0xff shifted in from the top.
1069 */
1070 #define TLB_TYPE_F16_COLOR (3 << 6)
1071 #define TLB_TYPE_I32_COLOR (1 << 6)
1072 #define TLB_TYPE_F32_COLOR (0 << 6)
1073 #define TLB_RENDER_TARGET_SHIFT 3 /* Reversed! 7 = RT 0, 0 = RT 7. */
1074 #define TLB_SAMPLE_MODE_PER_SAMPLE (0 << 2)
1075 #define TLB_SAMPLE_MODE_PER_PIXEL (1 << 2)
1076 #define TLB_F16_SWAP_HI_LO (1 << 1)
1077 #define TLB_VEC_SIZE_4_F16 (1 << 0)
1078 #define TLB_VEC_SIZE_2_F16 (0 << 0)
1079 #define TLB_VEC_SIZE_MINUS_1_SHIFT 0
1080
1081 /* Triggers Z/Stencil testing, used when the shader state's "FS modifies Z"
1082 * flag is set.
1083 */
1084 #define TLB_TYPE_DEPTH ((2 << 6) | (0 << 4))
1085 #define TLB_DEPTH_TYPE_INVARIANT (0 << 2) /* Unmodified sideband input used */
1086 #define TLB_DEPTH_TYPE_PER_PIXEL (1 << 2) /* QPU result used */
1087 #define TLB_V42_DEPTH_TYPE_INVARIANT (0 << 3) /* Unmodified sideband input used */
1088 #define TLB_V42_DEPTH_TYPE_PER_PIXEL (1 << 3) /* QPU result used */
1089
1090 /* Stencil is a single 32-bit write. */
1091 #define TLB_TYPE_STENCIL_ALPHA ((2 << 6) | (1 << 4))
1092
1093 static void
1094 emit_frag_end(struct v3d_compile *c)
1095 {
1096 /* XXX
1097 if (c->output_sample_mask_index != -1) {
1098 vir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
1099 }
1100 */
1101
1102 bool has_any_tlb_color_write = false;
1103 for (int rt = 0; rt < V3D_MAX_DRAW_BUFFERS; rt++) {
1104 if (c->fs_key->cbufs & (1 << rt) && c->output_color_var[rt])
1105 has_any_tlb_color_write = true;
1106 }
1107
1108 if (c->fs_key->sample_alpha_to_coverage && c->output_color_var[0]) {
1109 struct nir_variable *var = c->output_color_var[0];
1110 struct qreg *color = &c->outputs[var->data.driver_location * 4];
1111
1112 vir_SETMSF_dest(c, vir_nop_reg(),
1113 vir_AND(c,
1114 vir_MSF(c),
1115 vir_FTOC(c, color[3])));
1116 }
1117
1118 struct qreg tlb_reg = vir_magic_reg(V3D_QPU_WADDR_TLB);
1119 struct qreg tlbu_reg = vir_magic_reg(V3D_QPU_WADDR_TLBU);
1120 if (c->output_position_index != -1) {
1121 struct qinst *inst = vir_MOV_dest(c, tlbu_reg,
1122 c->outputs[c->output_position_index]);
1123 uint8_t tlb_specifier = TLB_TYPE_DEPTH;
1124
1125 if (c->devinfo->ver >= 42) {
1126 tlb_specifier |= (TLB_V42_DEPTH_TYPE_PER_PIXEL |
1127 TLB_SAMPLE_MODE_PER_PIXEL);
1128 } else
1129 tlb_specifier |= TLB_DEPTH_TYPE_PER_PIXEL;
1130
1131 inst->uniform = vir_get_uniform_index(c, QUNIFORM_CONSTANT,
1132 tlb_specifier |
1133 0xffffff00);
1134 c->writes_z = true;
1135 } else if (c->s->info.fs.uses_discard ||
1136 !c->s->info.fs.early_fragment_tests ||
1137 c->fs_key->sample_alpha_to_coverage ||
1138 !has_any_tlb_color_write) {
1139 /* Emit passthrough Z if it needed to be delayed until shader
1140 * end due to potential discards.
1141 *
1142 * Since (single-threaded) fragment shaders always need a TLB
1143 * write, emit passthrouh Z if we didn't have any color
1144 * buffers and flag us as potentially discarding, so that we
1145 * can use Z as the TLB write.
1146 */
1147 c->s->info.fs.uses_discard = true;
1148
1149 struct qinst *inst = vir_MOV_dest(c, tlbu_reg,
1150 vir_nop_reg());
1151 uint8_t tlb_specifier = TLB_TYPE_DEPTH;
1152
1153 if (c->devinfo->ver >= 42) {
1154 /* The spec says the PER_PIXEL flag is ignored for
1155 * invariant writes, but the simulator demands it.
1156 */
1157 tlb_specifier |= (TLB_V42_DEPTH_TYPE_INVARIANT |
1158 TLB_SAMPLE_MODE_PER_PIXEL);
1159 } else {
1160 tlb_specifier |= TLB_DEPTH_TYPE_INVARIANT;
1161 }
1162
1163 inst->uniform = vir_get_uniform_index(c,
1164 QUNIFORM_CONSTANT,
1165 tlb_specifier |
1166 0xffffff00);
1167 c->writes_z = true;
1168 }
1169
1170 /* XXX: Performance improvement: Merge Z write and color writes TLB
1171 * uniform setup
1172 */
1173
1174 for (int rt = 0; rt < V3D_MAX_DRAW_BUFFERS; rt++) {
1175 if (!(c->fs_key->cbufs & (1 << rt)) || !c->output_color_var[rt])
1176 continue;
1177
1178 nir_variable *var = c->output_color_var[rt];
1179 struct qreg *color = &c->outputs[var->data.driver_location * 4];
1180 int num_components = glsl_get_vector_elements(var->type);
1181 uint32_t conf = 0xffffff00;
1182 struct qinst *inst;
1183
1184 conf |= TLB_SAMPLE_MODE_PER_PIXEL;
1185 conf |= (7 - rt) << TLB_RENDER_TARGET_SHIFT;
1186
1187 if (c->fs_key->swap_color_rb & (1 << rt))
1188 num_components = MAX2(num_components, 3);
1189
1190 assert(num_components != 0);
1191 switch (glsl_get_base_type(var->type)) {
1192 case GLSL_TYPE_UINT:
1193 case GLSL_TYPE_INT:
1194 /* The F32 vs I32 distinction was dropped in 4.2. */
1195 if (c->devinfo->ver < 42)
1196 conf |= TLB_TYPE_I32_COLOR;
1197 else
1198 conf |= TLB_TYPE_F32_COLOR;
1199 conf |= ((num_components - 1) <<
1200 TLB_VEC_SIZE_MINUS_1_SHIFT);
1201
1202 inst = vir_MOV_dest(c, tlbu_reg, color[0]);
1203 inst->uniform = vir_get_uniform_index(c,
1204 QUNIFORM_CONSTANT,
1205 conf);
1206
1207 for (int i = 1; i < num_components; i++) {
1208 inst = vir_MOV_dest(c, tlb_reg, color[i]);
1209 }
1210 break;
1211
1212 default: {
1213 struct qreg r = color[0];
1214 struct qreg g = color[1];
1215 struct qreg b = color[2];
1216 struct qreg a = color[3];
1217
1218 if (c->fs_key->f32_color_rb & (1 << rt)) {
1219 conf |= TLB_TYPE_F32_COLOR;
1220 conf |= ((num_components - 1) <<
1221 TLB_VEC_SIZE_MINUS_1_SHIFT);
1222 } else {
1223 conf |= TLB_TYPE_F16_COLOR;
1224 conf |= TLB_F16_SWAP_HI_LO;
1225 if (num_components >= 3)
1226 conf |= TLB_VEC_SIZE_4_F16;
1227 else
1228 conf |= TLB_VEC_SIZE_2_F16;
1229 }
1230
1231 if (c->fs_key->swap_color_rb & (1 << rt)) {
1232 r = color[2];
1233 b = color[0];
1234 }
1235
1236 if (c->fs_key->sample_alpha_to_one)
1237 a = vir_uniform_f(c, 1.0);
1238
1239 if (c->fs_key->f32_color_rb & (1 << rt)) {
1240 inst = vir_MOV_dest(c, tlbu_reg, r);
1241 inst->uniform = vir_get_uniform_index(c,
1242 QUNIFORM_CONSTANT,
1243 conf);
1244
1245 if (num_components >= 2)
1246 vir_MOV_dest(c, tlb_reg, g);
1247 if (num_components >= 3)
1248 vir_MOV_dest(c, tlb_reg, b);
1249 if (num_components >= 4)
1250 vir_MOV_dest(c, tlb_reg, a);
1251 } else {
1252 inst = vir_VFPACK_dest(c, tlb_reg, r, g);
1253 if (conf != ~0) {
1254 inst->dst = tlbu_reg;
1255 inst->uniform = vir_get_uniform_index(c,
1256 QUNIFORM_CONSTANT,
1257 conf);
1258 }
1259
1260 if (num_components >= 3)
1261 inst = vir_VFPACK_dest(c, tlb_reg, b, a);
1262 }
1263 break;
1264 }
1265 }
1266 }
1267 }
1268
1269 static void
1270 vir_VPM_WRITE(struct v3d_compile *c, struct qreg val, uint32_t vpm_index)
1271 {
1272 if (c->devinfo->ver >= 40) {
1273 vir_STVPMV(c, vir_uniform_ui(c, vpm_index), val);
1274 } else {
1275 /* XXX: v3d33_vir_vpm_write_setup(c); */
1276 vir_MOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_VPM), val);
1277 }
1278 }
1279
1280 static void
1281 emit_vert_end(struct v3d_compile *c)
1282 {
1283 /* GFXH-1684: VPM writes need to be complete by the end of the shader.
1284 */
1285 if (c->devinfo->ver >= 40 && c->devinfo->ver <= 42)
1286 vir_VPMWT(c);
1287 }
1288
1289 void
1290 v3d_optimize_nir(struct nir_shader *s)
1291 {
1292 bool progress;
1293 unsigned lower_flrp =
1294 (s->options->lower_flrp16 ? 16 : 0) |
1295 (s->options->lower_flrp32 ? 32 : 0) |
1296 (s->options->lower_flrp64 ? 64 : 0);
1297
1298 do {
1299 progress = false;
1300
1301 NIR_PASS_V(s, nir_lower_vars_to_ssa);
1302 NIR_PASS(progress, s, nir_lower_alu_to_scalar, NULL);
1303 NIR_PASS(progress, s, nir_lower_phis_to_scalar);
1304 NIR_PASS(progress, s, nir_copy_prop);
1305 NIR_PASS(progress, s, nir_opt_remove_phis);
1306 NIR_PASS(progress, s, nir_opt_dce);
1307 NIR_PASS(progress, s, nir_opt_dead_cf);
1308 NIR_PASS(progress, s, nir_opt_cse);
1309 NIR_PASS(progress, s, nir_opt_peephole_select, 8, true, true);
1310 NIR_PASS(progress, s, nir_opt_algebraic);
1311 NIR_PASS(progress, s, nir_opt_constant_folding);
1312
1313 if (lower_flrp != 0) {
1314 bool lower_flrp_progress = false;
1315
1316 NIR_PASS(lower_flrp_progress, s, nir_lower_flrp,
1317 lower_flrp,
1318 false /* always_precise */,
1319 s->options->lower_ffma);
1320 if (lower_flrp_progress) {
1321 NIR_PASS(progress, s, nir_opt_constant_folding);
1322 progress = true;
1323 }
1324
1325 /* Nothing should rematerialize any flrps, so we only
1326 * need to do this lowering once.
1327 */
1328 lower_flrp = 0;
1329 }
1330
1331 NIR_PASS(progress, s, nir_opt_undef);
1332 } while (progress);
1333
1334 NIR_PASS(progress, s, nir_opt_move_load_ubo);
1335 }
1336
1337 static int
1338 driver_location_compare(const void *in_a, const void *in_b)
1339 {
1340 const nir_variable *const *a = in_a;
1341 const nir_variable *const *b = in_b;
1342
1343 return (*a)->data.driver_location - (*b)->data.driver_location;
1344 }
1345
1346 static struct qreg
1347 ntq_emit_vpm_read(struct v3d_compile *c,
1348 uint32_t *num_components_queued,
1349 uint32_t *remaining,
1350 uint32_t vpm_index)
1351 {
1352 struct qreg vpm = vir_reg(QFILE_VPM, vpm_index);
1353
1354 if (c->devinfo->ver >= 40 ) {
1355 return vir_LDVPMV_IN(c,
1356 vir_uniform_ui(c,
1357 (*num_components_queued)++));
1358 }
1359
1360 if (*num_components_queued != 0) {
1361 (*num_components_queued)--;
1362 return vir_MOV(c, vpm);
1363 }
1364
1365 uint32_t num_components = MIN2(*remaining, 32);
1366
1367 v3d33_vir_vpm_read_setup(c, num_components);
1368
1369 *num_components_queued = num_components - 1;
1370 *remaining -= num_components;
1371
1372 return vir_MOV(c, vpm);
1373 }
1374
1375 static void
1376 ntq_setup_vpm_inputs(struct v3d_compile *c)
1377 {
1378 /* Figure out how many components of each vertex attribute the shader
1379 * uses. Each variable should have been split to individual
1380 * components and unused ones DCEed. The vertex fetcher will load
1381 * from the start of the attribute to the number of components we
1382 * declare we need in c->vattr_sizes[].
1383 */
1384 nir_foreach_variable(var, &c->s->inputs) {
1385 /* No VS attribute array support. */
1386 assert(MAX2(glsl_get_length(var->type), 1) == 1);
1387
1388 unsigned loc = var->data.driver_location;
1389 int start_component = var->data.location_frac;
1390 int num_components = glsl_get_components(var->type);
1391
1392 c->vattr_sizes[loc] = MAX2(c->vattr_sizes[loc],
1393 start_component + num_components);
1394 }
1395
1396 unsigned num_components = 0;
1397 uint32_t vpm_components_queued = 0;
1398 bool uses_iid = c->s->info.system_values_read &
1399 (1ull << SYSTEM_VALUE_INSTANCE_ID);
1400 bool uses_vid = c->s->info.system_values_read &
1401 (1ull << SYSTEM_VALUE_VERTEX_ID);
1402 num_components += uses_iid;
1403 num_components += uses_vid;
1404
1405 for (int i = 0; i < ARRAY_SIZE(c->vattr_sizes); i++)
1406 num_components += c->vattr_sizes[i];
1407
1408 if (uses_iid) {
1409 c->iid = ntq_emit_vpm_read(c, &vpm_components_queued,
1410 &num_components, ~0);
1411 }
1412
1413 if (uses_vid) {
1414 c->vid = ntq_emit_vpm_read(c, &vpm_components_queued,
1415 &num_components, ~0);
1416 }
1417
1418 /* The actual loads will happen directly in nir_intrinsic_load_input
1419 * on newer versions.
1420 */
1421 if (c->devinfo->ver >= 40)
1422 return;
1423
1424 for (int loc = 0; loc < ARRAY_SIZE(c->vattr_sizes); loc++) {
1425 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1426 (loc + 1) * 4);
1427
1428 for (int i = 0; i < c->vattr_sizes[loc]; i++) {
1429 c->inputs[loc * 4 + i] =
1430 ntq_emit_vpm_read(c,
1431 &vpm_components_queued,
1432 &num_components,
1433 loc * 4 + i);
1434
1435 }
1436 }
1437
1438 if (c->devinfo->ver >= 40) {
1439 assert(vpm_components_queued == num_components);
1440 } else {
1441 assert(vpm_components_queued == 0);
1442 assert(num_components == 0);
1443 }
1444 }
1445
1446 static bool
1447 var_needs_point_coord(struct v3d_compile *c, nir_variable *var)
1448 {
1449 return (var->data.location == VARYING_SLOT_PNTC ||
1450 (var->data.location >= VARYING_SLOT_VAR0 &&
1451 (c->fs_key->point_sprite_mask &
1452 (1 << (var->data.location - VARYING_SLOT_VAR0)))));
1453 }
1454
1455 static bool
1456 program_reads_point_coord(struct v3d_compile *c)
1457 {
1458 nir_foreach_variable(var, &c->s->inputs) {
1459 if (var_needs_point_coord(c, var))
1460 return true;
1461 }
1462
1463 return false;
1464 }
1465
1466 static void
1467 ntq_setup_fs_inputs(struct v3d_compile *c)
1468 {
1469 unsigned num_entries = 0;
1470 unsigned num_components = 0;
1471 nir_foreach_variable(var, &c->s->inputs) {
1472 num_entries++;
1473 num_components += glsl_get_components(var->type);
1474 }
1475
1476 nir_variable *vars[num_entries];
1477
1478 unsigned i = 0;
1479 nir_foreach_variable(var, &c->s->inputs)
1480 vars[i++] = var;
1481
1482 /* Sort the variables so that we emit the input setup in
1483 * driver_location order. This is required for VPM reads, whose data
1484 * is fetched into the VPM in driver_location (TGSI register index)
1485 * order.
1486 */
1487 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1488
1489 for (unsigned i = 0; i < num_entries; i++) {
1490 nir_variable *var = vars[i];
1491 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1492 unsigned loc = var->data.driver_location;
1493
1494 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1495 (loc + array_len) * 4);
1496
1497 if (var->data.location == VARYING_SLOT_POS) {
1498 emit_fragcoord_input(c, loc);
1499 } else if (var_needs_point_coord(c, var)) {
1500 c->inputs[loc * 4 + 0] = c->point_x;
1501 c->inputs[loc * 4 + 1] = c->point_y;
1502 } else {
1503 for (int j = 0; j < array_len; j++)
1504 emit_fragment_input(c, loc + j, var, j);
1505 }
1506 }
1507 }
1508
1509 static void
1510 ntq_setup_outputs(struct v3d_compile *c)
1511 {
1512 if (c->s->info.stage != MESA_SHADER_FRAGMENT)
1513 return;
1514
1515 nir_foreach_variable(var, &c->s->outputs) {
1516 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1517 unsigned loc = var->data.driver_location * 4;
1518
1519 assert(array_len == 1);
1520 (void)array_len;
1521
1522 for (int i = 0; i < 4 - var->data.location_frac; i++) {
1523 add_output(c, loc + var->data.location_frac + i,
1524 var->data.location,
1525 var->data.location_frac + i);
1526 }
1527
1528 switch (var->data.location) {
1529 case FRAG_RESULT_COLOR:
1530 c->output_color_var[0] = var;
1531 c->output_color_var[1] = var;
1532 c->output_color_var[2] = var;
1533 c->output_color_var[3] = var;
1534 break;
1535 case FRAG_RESULT_DATA0:
1536 case FRAG_RESULT_DATA1:
1537 case FRAG_RESULT_DATA2:
1538 case FRAG_RESULT_DATA3:
1539 c->output_color_var[var->data.location -
1540 FRAG_RESULT_DATA0] = var;
1541 break;
1542 case FRAG_RESULT_DEPTH:
1543 c->output_position_index = loc;
1544 break;
1545 case FRAG_RESULT_SAMPLE_MASK:
1546 c->output_sample_mask_index = loc;
1547 break;
1548 }
1549 }
1550 }
1551
1552 /**
1553 * Sets up the mapping from nir_register to struct qreg *.
1554 *
1555 * Each nir_register gets a struct qreg per 32-bit component being stored.
1556 */
1557 static void
1558 ntq_setup_registers(struct v3d_compile *c, struct exec_list *list)
1559 {
1560 foreach_list_typed(nir_register, nir_reg, node, list) {
1561 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1562 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1563 array_len *
1564 nir_reg->num_components);
1565
1566 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1567
1568 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1569 qregs[i] = vir_get_temp(c);
1570 }
1571 }
1572
1573 static void
1574 ntq_emit_load_const(struct v3d_compile *c, nir_load_const_instr *instr)
1575 {
1576 /* XXX perf: Experiment with using immediate loads to avoid having
1577 * these end up in the uniform stream. Watch out for breaking the
1578 * small immediates optimization in the process!
1579 */
1580 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1581 for (int i = 0; i < instr->def.num_components; i++)
1582 qregs[i] = vir_uniform_ui(c, instr->value[i].u32);
1583
1584 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1585 }
1586
1587 static void
1588 ntq_emit_ssa_undef(struct v3d_compile *c, nir_ssa_undef_instr *instr)
1589 {
1590 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1591
1592 /* VIR needs there to be *some* value, so pick 0 (same as for
1593 * ntq_setup_registers().
1594 */
1595 for (int i = 0; i < instr->def.num_components; i++)
1596 qregs[i] = vir_uniform_ui(c, 0);
1597 }
1598
1599 static void
1600 ntq_emit_image_size(struct v3d_compile *c, nir_intrinsic_instr *instr)
1601 {
1602 assert(instr->intrinsic == nir_intrinsic_image_deref_size);
1603 nir_variable *var = nir_intrinsic_get_var(instr, 0);
1604 unsigned image_index = var->data.driver_location;
1605 const struct glsl_type *sampler_type = glsl_without_array(var->type);
1606 bool is_array = glsl_sampler_type_is_array(sampler_type);
1607
1608 ntq_store_dest(c, &instr->dest, 0,
1609 vir_uniform(c, QUNIFORM_IMAGE_WIDTH, image_index));
1610 if (instr->num_components > 1) {
1611 ntq_store_dest(c, &instr->dest, 1,
1612 vir_uniform(c, QUNIFORM_IMAGE_HEIGHT,
1613 image_index));
1614 }
1615 if (instr->num_components > 2) {
1616 ntq_store_dest(c, &instr->dest, 2,
1617 vir_uniform(c,
1618 is_array ?
1619 QUNIFORM_IMAGE_ARRAY_SIZE :
1620 QUNIFORM_IMAGE_DEPTH,
1621 image_index));
1622 }
1623 }
1624
1625 static void
1626 vir_emit_tlb_color_read(struct v3d_compile *c, nir_intrinsic_instr *instr)
1627 {
1628 assert(c->s->info.stage == MESA_SHADER_FRAGMENT);
1629
1630 int rt = nir_src_as_uint(instr->src[0]);
1631 assert(rt < V3D_MAX_DRAW_BUFFERS);
1632
1633 int sample_index = nir_intrinsic_base(instr) ;
1634 assert(sample_index == 0); /* XXX: multisample */
1635
1636 int component = nir_intrinsic_component(instr);
1637 assert(component < 4);
1638
1639 /* We need to emit our TLB reads after we have acquired the scoreboard
1640 * lock, or the GPU will hang. Usually, we do our scoreboard locking on
1641 * the last thread switch to improve parallelism, however, that is only
1642 * guaranteed to happen before the tlb color writes.
1643 *
1644 * To fix that, we make sure we always emit a thread switch before the
1645 * first tlb color read. If that happens to be the last thread switch
1646 * we emit, then everything is fine, but otherwsie, if any code after
1647 * this point needs to emit additional thread switches, then we will
1648 * switch the strategy to locking the scoreboard on the first thread
1649 * switch instead -- see vir_emit_thrsw().
1650 */
1651 if (!c->emitted_tlb_load) {
1652 if (!c->last_thrsw_at_top_level) {
1653 assert(c->devinfo->ver >= 41);
1654 vir_emit_thrsw(c);
1655 }
1656
1657 c->emitted_tlb_load = true;
1658 }
1659
1660 struct qreg *color_reads =
1661 &c->color_reads[(rt * V3D_MAX_SAMPLES + sample_index) * 4];
1662
1663 if (color_reads[component].file == QFILE_NULL) {
1664 enum pipe_format rt_format = c->fs_key->color_fmt[rt].format;
1665 int num_components =
1666 util_format_get_nr_components(rt_format);
1667
1668 const bool swap_rb = c->fs_key->swap_color_rb & (1 << rt);
1669 if (swap_rb)
1670 num_components = MAX2(num_components, 3);
1671
1672 nir_variable *var = c->output_color_var[rt];
1673 enum glsl_base_type type = glsl_get_base_type(var->type);
1674
1675 bool is_int_format = type == GLSL_TYPE_INT ||
1676 type == GLSL_TYPE_UINT;
1677
1678 bool is_32b_tlb_format = is_int_format ||
1679 (c->fs_key->f32_color_rb & (1 << rt));
1680
1681 uint32_t conf = 0xffffff00;
1682 conf |= TLB_SAMPLE_MODE_PER_PIXEL; /* XXX: multisample */
1683 conf |= (7 - rt) << TLB_RENDER_TARGET_SHIFT;
1684
1685 if (is_32b_tlb_format) {
1686 /* The F32 vs I32 distinction was dropped in 4.2. */
1687 conf |= (c->devinfo->ver < 42 && is_int_format) ?
1688 TLB_TYPE_I32_COLOR : TLB_TYPE_F32_COLOR;
1689
1690 conf |= ((num_components - 1) <<
1691 TLB_VEC_SIZE_MINUS_1_SHIFT);
1692 } else {
1693 conf |= TLB_TYPE_F16_COLOR;
1694 conf |= TLB_F16_SWAP_HI_LO;
1695
1696 if (num_components >= 3)
1697 conf |= TLB_VEC_SIZE_4_F16;
1698 else
1699 conf |= TLB_VEC_SIZE_2_F16;
1700 }
1701
1702 struct qreg r, g, b, a;
1703 if (is_32b_tlb_format) {
1704 r = conf != 0xffffffff ? vir_TLBU_COLOR_READ(c, conf) :
1705 vir_TLB_COLOR_READ(c);
1706 if (num_components >= 2)
1707 g = vir_TLB_COLOR_READ(c);
1708 if (num_components >= 3)
1709 b = vir_TLB_COLOR_READ(c);
1710 if (num_components >= 4)
1711 a = vir_TLB_COLOR_READ(c);
1712 } else {
1713 struct qreg rg = conf != 0xffffffff ?
1714 vir_TLBU_COLOR_READ(c, conf) :
1715 vir_TLB_COLOR_READ(c);
1716 r = vir_FMOV(c, rg);
1717 vir_set_unpack(c->defs[r.index], 0, V3D_QPU_UNPACK_L);
1718 g = vir_FMOV(c, rg);
1719 vir_set_unpack(c->defs[g.index], 0, V3D_QPU_UNPACK_H);
1720
1721 if (num_components > 2) {
1722 struct qreg ba = vir_TLB_COLOR_READ(c);
1723 b = vir_FMOV(c, ba);
1724 vir_set_unpack(c->defs[b.index], 0,
1725 V3D_QPU_UNPACK_L);
1726 a = vir_FMOV(c, ba);
1727 vir_set_unpack(c->defs[a.index], 0,
1728 V3D_QPU_UNPACK_H);
1729 }
1730 }
1731
1732 color_reads[0] = swap_rb ? b : r;
1733 if (num_components >= 2)
1734 color_reads[1] = g;
1735 if (num_components >= 3)
1736 color_reads[2] = swap_rb ? r : b;
1737 if (num_components >= 4)
1738 color_reads[3] = a;
1739 }
1740
1741 assert(color_reads[component].file != QFILE_NULL);
1742 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, color_reads[component]));
1743 }
1744
1745 static void
1746 ntq_emit_load_uniform(struct v3d_compile *c, nir_intrinsic_instr *instr)
1747 {
1748 if (nir_src_is_const(instr->src[0])) {
1749 int offset = (nir_intrinsic_base(instr) +
1750 nir_src_as_uint(instr->src[0]));
1751 assert(offset % 4 == 0);
1752 /* We need dwords */
1753 offset = offset / 4;
1754 for (int i = 0; i < instr->num_components; i++) {
1755 ntq_store_dest(c, &instr->dest, i,
1756 vir_uniform(c, QUNIFORM_UNIFORM,
1757 offset + i));
1758 }
1759 } else {
1760 ntq_emit_tmu_general(c, instr, false);
1761 }
1762 }
1763
1764 static void
1765 ntq_emit_load_input(struct v3d_compile *c, nir_intrinsic_instr *instr)
1766 {
1767 /* XXX: Use ldvpmv (uniform offset) or ldvpmd (non-uniform offset)
1768 * and enable PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR.
1769 */
1770 unsigned offset =
1771 nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[0]);
1772
1773 if (c->s->info.stage != MESA_SHADER_FRAGMENT && c->devinfo->ver >= 40) {
1774 /* Emit the LDVPM directly now, rather than at the top
1775 * of the shader like we did for V3D 3.x (which needs
1776 * vpmsetup when not just taking the next offset).
1777 *
1778 * Note that delaying like this may introduce stalls,
1779 * as LDVPMV takes a minimum of 1 instruction but may
1780 * be slower if the VPM unit is busy with another QPU.
1781 */
1782 int index = 0;
1783 if (c->s->info.system_values_read &
1784 (1ull << SYSTEM_VALUE_INSTANCE_ID)) {
1785 index++;
1786 }
1787 if (c->s->info.system_values_read &
1788 (1ull << SYSTEM_VALUE_VERTEX_ID)) {
1789 index++;
1790 }
1791 for (int i = 0; i < offset; i++)
1792 index += c->vattr_sizes[i];
1793 index += nir_intrinsic_component(instr);
1794 for (int i = 0; i < instr->num_components; i++) {
1795 struct qreg vpm_offset = vir_uniform_ui(c, index++);
1796 ntq_store_dest(c, &instr->dest, i,
1797 vir_LDVPMV_IN(c, vpm_offset));
1798 }
1799 } else {
1800 for (int i = 0; i < instr->num_components; i++) {
1801 int comp = nir_intrinsic_component(instr) + i;
1802 ntq_store_dest(c, &instr->dest, i,
1803 vir_MOV(c, c->inputs[offset * 4 + comp]));
1804 }
1805 }
1806 }
1807
1808 static void
1809 ntq_emit_store_output(struct v3d_compile *c, nir_intrinsic_instr *instr)
1810 {
1811 /* XXX perf: Use stvpmv with uniform non-constant offsets and
1812 * stvpmd with non-uniform offsets and enable
1813 * PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR.
1814 */
1815 if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
1816 unsigned offset = ((nir_intrinsic_base(instr) +
1817 nir_src_as_uint(instr->src[1])) * 4 +
1818 nir_intrinsic_component(instr));
1819 for (int i = 0; i < instr->num_components; i++) {
1820 c->outputs[offset + i] =
1821 vir_MOV(c, ntq_get_src(c, instr->src[0], i));
1822 }
1823 } else {
1824 assert(instr->num_components == 1);
1825
1826 vir_VPM_WRITE(c,
1827 ntq_get_src(c, instr->src[0], 0),
1828 nir_intrinsic_base(instr));
1829 }
1830 }
1831
1832 static void
1833 ntq_emit_intrinsic(struct v3d_compile *c, nir_intrinsic_instr *instr)
1834 {
1835 switch (instr->intrinsic) {
1836 case nir_intrinsic_load_uniform:
1837 ntq_emit_load_uniform(c, instr);
1838 break;
1839
1840 case nir_intrinsic_load_ubo:
1841 ntq_emit_tmu_general(c, instr, false);
1842 break;
1843
1844 case nir_intrinsic_ssbo_atomic_add:
1845 case nir_intrinsic_ssbo_atomic_imin:
1846 case nir_intrinsic_ssbo_atomic_umin:
1847 case nir_intrinsic_ssbo_atomic_imax:
1848 case nir_intrinsic_ssbo_atomic_umax:
1849 case nir_intrinsic_ssbo_atomic_and:
1850 case nir_intrinsic_ssbo_atomic_or:
1851 case nir_intrinsic_ssbo_atomic_xor:
1852 case nir_intrinsic_ssbo_atomic_exchange:
1853 case nir_intrinsic_ssbo_atomic_comp_swap:
1854 case nir_intrinsic_load_ssbo:
1855 case nir_intrinsic_store_ssbo:
1856 ntq_emit_tmu_general(c, instr, false);
1857 break;
1858
1859 case nir_intrinsic_shared_atomic_add:
1860 case nir_intrinsic_shared_atomic_imin:
1861 case nir_intrinsic_shared_atomic_umin:
1862 case nir_intrinsic_shared_atomic_imax:
1863 case nir_intrinsic_shared_atomic_umax:
1864 case nir_intrinsic_shared_atomic_and:
1865 case nir_intrinsic_shared_atomic_or:
1866 case nir_intrinsic_shared_atomic_xor:
1867 case nir_intrinsic_shared_atomic_exchange:
1868 case nir_intrinsic_shared_atomic_comp_swap:
1869 case nir_intrinsic_load_shared:
1870 case nir_intrinsic_store_shared:
1871 case nir_intrinsic_load_scratch:
1872 case nir_intrinsic_store_scratch:
1873 ntq_emit_tmu_general(c, instr, true);
1874 break;
1875
1876 case nir_intrinsic_image_deref_load:
1877 case nir_intrinsic_image_deref_store:
1878 case nir_intrinsic_image_deref_atomic_add:
1879 case nir_intrinsic_image_deref_atomic_min:
1880 case nir_intrinsic_image_deref_atomic_max:
1881 case nir_intrinsic_image_deref_atomic_and:
1882 case nir_intrinsic_image_deref_atomic_or:
1883 case nir_intrinsic_image_deref_atomic_xor:
1884 case nir_intrinsic_image_deref_atomic_exchange:
1885 case nir_intrinsic_image_deref_atomic_comp_swap:
1886 v3d40_vir_emit_image_load_store(c, instr);
1887 break;
1888
1889 case nir_intrinsic_get_buffer_size:
1890 ntq_store_dest(c, &instr->dest, 0,
1891 vir_uniform(c, QUNIFORM_GET_BUFFER_SIZE,
1892 nir_src_as_uint(instr->src[0])));
1893 break;
1894
1895 case nir_intrinsic_load_user_clip_plane:
1896 for (int i = 0; i < instr->num_components; i++) {
1897 ntq_store_dest(c, &instr->dest, i,
1898 vir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1899 nir_intrinsic_ucp_id(instr) *
1900 4 + i));
1901 }
1902 break;
1903
1904 case nir_intrinsic_load_viewport_x_scale:
1905 ntq_store_dest(c, &instr->dest, 0,
1906 vir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE, 0));
1907 break;
1908
1909 case nir_intrinsic_load_viewport_y_scale:
1910 ntq_store_dest(c, &instr->dest, 0,
1911 vir_uniform(c, QUNIFORM_VIEWPORT_Y_SCALE, 0));
1912 break;
1913
1914 case nir_intrinsic_load_viewport_z_scale:
1915 ntq_store_dest(c, &instr->dest, 0,
1916 vir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0));
1917 break;
1918
1919 case nir_intrinsic_load_viewport_z_offset:
1920 ntq_store_dest(c, &instr->dest, 0,
1921 vir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0));
1922 break;
1923
1924 case nir_intrinsic_load_alpha_ref_float:
1925 ntq_store_dest(c, &instr->dest, 0,
1926 vir_uniform(c, QUNIFORM_ALPHA_REF, 0));
1927 break;
1928
1929 case nir_intrinsic_load_sample_mask_in:
1930 ntq_store_dest(c, &instr->dest, 0, vir_MSF(c));
1931 break;
1932
1933 case nir_intrinsic_load_helper_invocation:
1934 vir_set_pf(vir_MSF_dest(c, vir_nop_reg()), V3D_QPU_PF_PUSHZ);
1935 ntq_store_dest(c, &instr->dest, 0,
1936 vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFA,
1937 vir_uniform_ui(c, ~0),
1938 vir_uniform_ui(c, 0))));
1939 break;
1940
1941 case nir_intrinsic_load_front_face:
1942 /* The register contains 0 (front) or 1 (back), and we need to
1943 * turn it into a NIR bool where true means front.
1944 */
1945 ntq_store_dest(c, &instr->dest, 0,
1946 vir_ADD(c,
1947 vir_uniform_ui(c, -1),
1948 vir_REVF(c)));
1949 break;
1950
1951 case nir_intrinsic_load_instance_id:
1952 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->iid));
1953 break;
1954
1955 case nir_intrinsic_load_vertex_id:
1956 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->vid));
1957 break;
1958
1959 case nir_intrinsic_load_tlb_color_v3d:
1960 vir_emit_tlb_color_read(c, instr);
1961 break;
1962
1963 case nir_intrinsic_load_input:
1964 ntq_emit_load_input(c, instr);
1965 break;
1966
1967 case nir_intrinsic_store_output:
1968 ntq_emit_store_output(c, instr);
1969 break;
1970
1971 case nir_intrinsic_image_deref_size:
1972 ntq_emit_image_size(c, instr);
1973 break;
1974
1975 case nir_intrinsic_discard:
1976 if (vir_in_nonuniform_control_flow(c)) {
1977 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
1978 V3D_QPU_PF_PUSHZ);
1979 vir_set_cond(vir_SETMSF_dest(c, vir_nop_reg(),
1980 vir_uniform_ui(c, 0)),
1981 V3D_QPU_COND_IFA);
1982 } else {
1983 vir_SETMSF_dest(c, vir_nop_reg(),
1984 vir_uniform_ui(c, 0));
1985 }
1986 break;
1987
1988 case nir_intrinsic_discard_if: {
1989 enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, instr->src[0]);
1990
1991 if (vir_in_nonuniform_control_flow(c)) {
1992 struct qinst *exec_flag = vir_MOV_dest(c, vir_nop_reg(),
1993 c->execute);
1994 if (cond == V3D_QPU_COND_IFA) {
1995 vir_set_uf(exec_flag, V3D_QPU_UF_ANDZ);
1996 } else {
1997 vir_set_uf(exec_flag, V3D_QPU_UF_NORNZ);
1998 cond = V3D_QPU_COND_IFA;
1999 }
2000 }
2001
2002 vir_set_cond(vir_SETMSF_dest(c, vir_nop_reg(),
2003 vir_uniform_ui(c, 0)), cond);
2004
2005 break;
2006 }
2007
2008 case nir_intrinsic_memory_barrier:
2009 case nir_intrinsic_memory_barrier_atomic_counter:
2010 case nir_intrinsic_memory_barrier_buffer:
2011 case nir_intrinsic_memory_barrier_image:
2012 case nir_intrinsic_memory_barrier_shared:
2013 case nir_intrinsic_group_memory_barrier:
2014 /* We don't do any instruction scheduling of these NIR
2015 * instructions between each other, so we just need to make
2016 * sure that the TMU operations before the barrier are flushed
2017 * before the ones after the barrier. That is currently
2018 * handled by having a THRSW in each of them and a LDTMU
2019 * series or a TMUWT after.
2020 */
2021 break;
2022
2023 case nir_intrinsic_barrier:
2024 /* Emit a TSY op to get all invocations in the workgroup
2025 * (actually supergroup) to block until the last invocation
2026 * reaches the TSY op.
2027 */
2028 if (c->devinfo->ver >= 42) {
2029 vir_BARRIERID_dest(c, vir_reg(QFILE_MAGIC,
2030 V3D_QPU_WADDR_SYNCB));
2031 } else {
2032 struct qinst *sync =
2033 vir_BARRIERID_dest(c,
2034 vir_reg(QFILE_MAGIC,
2035 V3D_QPU_WADDR_SYNCU));
2036 sync->uniform =
2037 vir_get_uniform_index(c, QUNIFORM_CONSTANT,
2038 0xffffff00 |
2039 V3D_TSY_WAIT_INC_CHECK);
2040
2041 }
2042
2043 /* The blocking of a TSY op only happens at the next thread
2044 * switch. No texturing may be outstanding at the time of a
2045 * TSY blocking operation.
2046 */
2047 vir_emit_thrsw(c);
2048 break;
2049
2050 case nir_intrinsic_load_num_work_groups:
2051 for (int i = 0; i < 3; i++) {
2052 ntq_store_dest(c, &instr->dest, i,
2053 vir_uniform(c, QUNIFORM_NUM_WORK_GROUPS,
2054 i));
2055 }
2056 break;
2057
2058 case nir_intrinsic_load_local_invocation_index:
2059 ntq_store_dest(c, &instr->dest, 0,
2060 vir_SHR(c, c->cs_payload[1],
2061 vir_uniform_ui(c, 32 - c->local_invocation_index_bits)));
2062 break;
2063
2064 case nir_intrinsic_load_work_group_id:
2065 ntq_store_dest(c, &instr->dest, 0,
2066 vir_AND(c, c->cs_payload[0],
2067 vir_uniform_ui(c, 0xffff)));
2068 ntq_store_dest(c, &instr->dest, 1,
2069 vir_SHR(c, c->cs_payload[0],
2070 vir_uniform_ui(c, 16)));
2071 ntq_store_dest(c, &instr->dest, 2,
2072 vir_AND(c, c->cs_payload[1],
2073 vir_uniform_ui(c, 0xffff)));
2074 break;
2075
2076 case nir_intrinsic_load_subgroup_id:
2077 ntq_store_dest(c, &instr->dest, 0, vir_EIDX(c));
2078 break;
2079
2080 default:
2081 fprintf(stderr, "Unknown intrinsic: ");
2082 nir_print_instr(&instr->instr, stderr);
2083 fprintf(stderr, "\n");
2084 break;
2085 }
2086 }
2087
2088 /* Clears (activates) the execute flags for any channels whose jump target
2089 * matches this block.
2090 *
2091 * XXX perf: Could we be using flpush/flpop somehow for our execution channel
2092 * enabling?
2093 *
2094 * XXX perf: For uniform control flow, we should be able to skip c->execute
2095 * handling entirely.
2096 */
2097 static void
2098 ntq_activate_execute_for_block(struct v3d_compile *c)
2099 {
2100 vir_set_pf(vir_XOR_dest(c, vir_nop_reg(),
2101 c->execute, vir_uniform_ui(c, c->cur_block->index)),
2102 V3D_QPU_PF_PUSHZ);
2103
2104 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
2105 }
2106
2107 static void
2108 ntq_emit_uniform_if(struct v3d_compile *c, nir_if *if_stmt)
2109 {
2110 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
2111 bool empty_else_block =
2112 (nir_else_block == nir_if_last_else_block(if_stmt) &&
2113 exec_list_is_empty(&nir_else_block->instr_list));
2114
2115 struct qblock *then_block = vir_new_block(c);
2116 struct qblock *after_block = vir_new_block(c);
2117 struct qblock *else_block;
2118 if (empty_else_block)
2119 else_block = after_block;
2120 else
2121 else_block = vir_new_block(c);
2122
2123 /* Set up the flags for the IF condition (taking the THEN branch). */
2124 enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, if_stmt->condition);
2125
2126 /* Jump to ELSE. */
2127 vir_BRANCH(c, cond == V3D_QPU_COND_IFA ?
2128 V3D_QPU_BRANCH_COND_ALLNA :
2129 V3D_QPU_BRANCH_COND_ALLA);
2130 vir_link_blocks(c->cur_block, else_block);
2131 vir_link_blocks(c->cur_block, then_block);
2132
2133 /* Process the THEN block. */
2134 vir_set_emit_block(c, then_block);
2135 ntq_emit_cf_list(c, &if_stmt->then_list);
2136
2137 if (!empty_else_block) {
2138 /* At the end of the THEN block, jump to ENDIF */
2139 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALWAYS);
2140 vir_link_blocks(c->cur_block, after_block);
2141
2142 /* Emit the else block. */
2143 vir_set_emit_block(c, else_block);
2144 ntq_emit_cf_list(c, &if_stmt->else_list);
2145 }
2146
2147 vir_link_blocks(c->cur_block, after_block);
2148
2149 vir_set_emit_block(c, after_block);
2150 }
2151
2152 static void
2153 ntq_emit_nonuniform_if(struct v3d_compile *c, nir_if *if_stmt)
2154 {
2155 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
2156 bool empty_else_block =
2157 (nir_else_block == nir_if_last_else_block(if_stmt) &&
2158 exec_list_is_empty(&nir_else_block->instr_list));
2159
2160 struct qblock *then_block = vir_new_block(c);
2161 struct qblock *after_block = vir_new_block(c);
2162 struct qblock *else_block;
2163 if (empty_else_block)
2164 else_block = after_block;
2165 else
2166 else_block = vir_new_block(c);
2167
2168 bool was_uniform_control_flow = false;
2169 if (!vir_in_nonuniform_control_flow(c)) {
2170 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
2171 was_uniform_control_flow = true;
2172 }
2173
2174 /* Set up the flags for the IF condition (taking the THEN branch). */
2175 enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, if_stmt->condition);
2176
2177 /* Update the flags+cond to mean "Taking the ELSE branch (!cond) and
2178 * was previously active (execute Z) for updating the exec flags.
2179 */
2180 if (was_uniform_control_flow) {
2181 cond = v3d_qpu_cond_invert(cond);
2182 } else {
2183 struct qinst *inst = vir_MOV_dest(c, vir_nop_reg(), c->execute);
2184 if (cond == V3D_QPU_COND_IFA) {
2185 vir_set_uf(inst, V3D_QPU_UF_NORNZ);
2186 } else {
2187 vir_set_uf(inst, V3D_QPU_UF_ANDZ);
2188 cond = V3D_QPU_COND_IFA;
2189 }
2190 }
2191
2192 vir_MOV_cond(c, cond,
2193 c->execute,
2194 vir_uniform_ui(c, else_block->index));
2195
2196 /* Jump to ELSE if nothing is active for THEN, otherwise fall
2197 * through.
2198 */
2199 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute), V3D_QPU_PF_PUSHZ);
2200 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLNA);
2201 vir_link_blocks(c->cur_block, else_block);
2202 vir_link_blocks(c->cur_block, then_block);
2203
2204 /* Process the THEN block. */
2205 vir_set_emit_block(c, then_block);
2206 ntq_emit_cf_list(c, &if_stmt->then_list);
2207
2208 if (!empty_else_block) {
2209 /* Handle the end of the THEN block. First, all currently
2210 * active channels update their execute flags to point to
2211 * ENDIF
2212 */
2213 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2214 V3D_QPU_PF_PUSHZ);
2215 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2216 vir_uniform_ui(c, after_block->index));
2217
2218 /* If everything points at ENDIF, then jump there immediately. */
2219 vir_set_pf(vir_XOR_dest(c, vir_nop_reg(),
2220 c->execute,
2221 vir_uniform_ui(c, after_block->index)),
2222 V3D_QPU_PF_PUSHZ);
2223 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLA);
2224 vir_link_blocks(c->cur_block, after_block);
2225 vir_link_blocks(c->cur_block, else_block);
2226
2227 vir_set_emit_block(c, else_block);
2228 ntq_activate_execute_for_block(c);
2229 ntq_emit_cf_list(c, &if_stmt->else_list);
2230 }
2231
2232 vir_link_blocks(c->cur_block, after_block);
2233
2234 vir_set_emit_block(c, after_block);
2235 if (was_uniform_control_flow)
2236 c->execute = c->undef;
2237 else
2238 ntq_activate_execute_for_block(c);
2239 }
2240
2241 static void
2242 ntq_emit_if(struct v3d_compile *c, nir_if *nif)
2243 {
2244 bool was_in_control_flow = c->in_control_flow;
2245 c->in_control_flow = true;
2246 if (!vir_in_nonuniform_control_flow(c) &&
2247 nir_src_is_dynamically_uniform(nif->condition)) {
2248 ntq_emit_uniform_if(c, nif);
2249 } else {
2250 ntq_emit_nonuniform_if(c, nif);
2251 }
2252 c->in_control_flow = was_in_control_flow;
2253 }
2254
2255 static void
2256 ntq_emit_jump(struct v3d_compile *c, nir_jump_instr *jump)
2257 {
2258 switch (jump->type) {
2259 case nir_jump_break:
2260 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2261 V3D_QPU_PF_PUSHZ);
2262 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2263 vir_uniform_ui(c, c->loop_break_block->index));
2264 break;
2265
2266 case nir_jump_continue:
2267 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2268 V3D_QPU_PF_PUSHZ);
2269 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2270 vir_uniform_ui(c, c->loop_cont_block->index));
2271 break;
2272
2273 case nir_jump_return:
2274 unreachable("All returns shouold be lowered\n");
2275 }
2276 }
2277
2278 static void
2279 ntq_emit_instr(struct v3d_compile *c, nir_instr *instr)
2280 {
2281 switch (instr->type) {
2282 case nir_instr_type_deref:
2283 /* ignored, will be walked by the intrinsic using it. */
2284 break;
2285
2286 case nir_instr_type_alu:
2287 ntq_emit_alu(c, nir_instr_as_alu(instr));
2288 break;
2289
2290 case nir_instr_type_intrinsic:
2291 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
2292 break;
2293
2294 case nir_instr_type_load_const:
2295 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
2296 break;
2297
2298 case nir_instr_type_ssa_undef:
2299 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
2300 break;
2301
2302 case nir_instr_type_tex:
2303 ntq_emit_tex(c, nir_instr_as_tex(instr));
2304 break;
2305
2306 case nir_instr_type_jump:
2307 ntq_emit_jump(c, nir_instr_as_jump(instr));
2308 break;
2309
2310 default:
2311 fprintf(stderr, "Unknown NIR instr type: ");
2312 nir_print_instr(instr, stderr);
2313 fprintf(stderr, "\n");
2314 abort();
2315 }
2316 }
2317
2318 static void
2319 ntq_emit_block(struct v3d_compile *c, nir_block *block)
2320 {
2321 nir_foreach_instr(instr, block) {
2322 ntq_emit_instr(c, instr);
2323 }
2324 }
2325
2326 static void ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
2327
2328 static void
2329 ntq_emit_loop(struct v3d_compile *c, nir_loop *loop)
2330 {
2331 bool was_in_control_flow = c->in_control_flow;
2332 c->in_control_flow = true;
2333
2334 bool was_uniform_control_flow = false;
2335 if (!vir_in_nonuniform_control_flow(c)) {
2336 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
2337 was_uniform_control_flow = true;
2338 }
2339
2340 struct qblock *save_loop_cont_block = c->loop_cont_block;
2341 struct qblock *save_loop_break_block = c->loop_break_block;
2342
2343 c->loop_cont_block = vir_new_block(c);
2344 c->loop_break_block = vir_new_block(c);
2345
2346 vir_link_blocks(c->cur_block, c->loop_cont_block);
2347 vir_set_emit_block(c, c->loop_cont_block);
2348 ntq_activate_execute_for_block(c);
2349
2350 ntq_emit_cf_list(c, &loop->body);
2351
2352 /* Re-enable any previous continues now, so our ANYA check below
2353 * works.
2354 *
2355 * XXX: Use the .ORZ flags update, instead.
2356 */
2357 vir_set_pf(vir_XOR_dest(c,
2358 vir_nop_reg(),
2359 c->execute,
2360 vir_uniform_ui(c, c->loop_cont_block->index)),
2361 V3D_QPU_PF_PUSHZ);
2362 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
2363
2364 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute), V3D_QPU_PF_PUSHZ);
2365
2366 struct qinst *branch = vir_BRANCH(c, V3D_QPU_BRANCH_COND_ANYA);
2367 /* Pixels that were not dispatched or have been discarded should not
2368 * contribute to looping again.
2369 */
2370 branch->qpu.branch.msfign = V3D_QPU_MSFIGN_P;
2371 vir_link_blocks(c->cur_block, c->loop_cont_block);
2372 vir_link_blocks(c->cur_block, c->loop_break_block);
2373
2374 vir_set_emit_block(c, c->loop_break_block);
2375 if (was_uniform_control_flow)
2376 c->execute = c->undef;
2377 else
2378 ntq_activate_execute_for_block(c);
2379
2380 c->loop_break_block = save_loop_break_block;
2381 c->loop_cont_block = save_loop_cont_block;
2382
2383 c->loops++;
2384
2385 c->in_control_flow = was_in_control_flow;
2386 }
2387
2388 static void
2389 ntq_emit_function(struct v3d_compile *c, nir_function_impl *func)
2390 {
2391 fprintf(stderr, "FUNCTIONS not handled.\n");
2392 abort();
2393 }
2394
2395 static void
2396 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list)
2397 {
2398 foreach_list_typed(nir_cf_node, node, node, list) {
2399 switch (node->type) {
2400 case nir_cf_node_block:
2401 ntq_emit_block(c, nir_cf_node_as_block(node));
2402 break;
2403
2404 case nir_cf_node_if:
2405 ntq_emit_if(c, nir_cf_node_as_if(node));
2406 break;
2407
2408 case nir_cf_node_loop:
2409 ntq_emit_loop(c, nir_cf_node_as_loop(node));
2410 break;
2411
2412 case nir_cf_node_function:
2413 ntq_emit_function(c, nir_cf_node_as_function(node));
2414 break;
2415
2416 default:
2417 fprintf(stderr, "Unknown NIR node type\n");
2418 abort();
2419 }
2420 }
2421 }
2422
2423 static void
2424 ntq_emit_impl(struct v3d_compile *c, nir_function_impl *impl)
2425 {
2426 ntq_setup_registers(c, &impl->registers);
2427 ntq_emit_cf_list(c, &impl->body);
2428 }
2429
2430 static void
2431 nir_to_vir(struct v3d_compile *c)
2432 {
2433 switch (c->s->info.stage) {
2434 case MESA_SHADER_FRAGMENT:
2435 c->payload_w = vir_MOV(c, vir_reg(QFILE_REG, 0));
2436 c->payload_w_centroid = vir_MOV(c, vir_reg(QFILE_REG, 1));
2437 c->payload_z = vir_MOV(c, vir_reg(QFILE_REG, 2));
2438
2439 /* V3D 4.x can disable implicit point coordinate varyings if
2440 * they are not used.
2441 */
2442 if (c->fs_key->is_points &&
2443 (c->devinfo->ver < 40 || program_reads_point_coord(c))) {
2444 c->point_x = emit_fragment_varying(c, NULL, 0, 0);
2445 c->point_y = emit_fragment_varying(c, NULL, 0, 0);
2446 c->uses_implicit_point_line_varyings = true;
2447 } else if (c->fs_key->is_lines && c->devinfo->ver < 40) {
2448 c->line_x = emit_fragment_varying(c, NULL, 0, 0);
2449 c->uses_implicit_point_line_varyings = true;
2450 }
2451 break;
2452 case MESA_SHADER_COMPUTE:
2453 /* Set up the TSO for barriers, assuming we do some. */
2454 if (c->devinfo->ver < 42) {
2455 vir_BARRIERID_dest(c, vir_reg(QFILE_MAGIC,
2456 V3D_QPU_WADDR_SYNC));
2457 }
2458
2459 c->cs_payload[0] = vir_MOV(c, vir_reg(QFILE_REG, 0));
2460 c->cs_payload[1] = vir_MOV(c, vir_reg(QFILE_REG, 2));
2461
2462 /* Set up the division between gl_LocalInvocationIndex and
2463 * wg_in_mem in the payload reg.
2464 */
2465 int wg_size = (c->s->info.cs.local_size[0] *
2466 c->s->info.cs.local_size[1] *
2467 c->s->info.cs.local_size[2]);
2468 c->local_invocation_index_bits =
2469 ffs(util_next_power_of_two(MAX2(wg_size, 64))) - 1;
2470 assert(c->local_invocation_index_bits <= 8);
2471
2472 if (c->s->info.cs.shared_size) {
2473 struct qreg wg_in_mem = vir_SHR(c, c->cs_payload[1],
2474 vir_uniform_ui(c, 16));
2475 if (c->s->info.cs.local_size[0] != 1 ||
2476 c->s->info.cs.local_size[1] != 1 ||
2477 c->s->info.cs.local_size[2] != 1) {
2478 int wg_bits = (16 -
2479 c->local_invocation_index_bits);
2480 int wg_mask = (1 << wg_bits) - 1;
2481 wg_in_mem = vir_AND(c, wg_in_mem,
2482 vir_uniform_ui(c, wg_mask));
2483 }
2484 struct qreg shared_per_wg =
2485 vir_uniform_ui(c, c->s->info.cs.shared_size);
2486
2487 c->cs_shared_offset =
2488 vir_ADD(c,
2489 vir_uniform(c, QUNIFORM_SHARED_OFFSET,0),
2490 vir_UMUL(c, wg_in_mem, shared_per_wg));
2491 }
2492 break;
2493 default:
2494 break;
2495 }
2496
2497 if (c->s->scratch_size) {
2498 v3d_setup_spill_base(c);
2499 c->spill_size += V3D_CHANNELS * c->s->scratch_size;
2500 }
2501
2502 if (c->s->info.stage == MESA_SHADER_FRAGMENT)
2503 ntq_setup_fs_inputs(c);
2504 else
2505 ntq_setup_vpm_inputs(c);
2506
2507 ntq_setup_outputs(c);
2508
2509 /* Find the main function and emit the body. */
2510 nir_foreach_function(function, c->s) {
2511 assert(strcmp(function->name, "main") == 0);
2512 assert(function->impl);
2513 ntq_emit_impl(c, function->impl);
2514 }
2515 }
2516
2517 const nir_shader_compiler_options v3d_nir_options = {
2518 .lower_all_io_to_temps = true,
2519 .lower_extract_byte = true,
2520 .lower_extract_word = true,
2521 .lower_bitfield_insert_to_shifts = true,
2522 .lower_bitfield_extract_to_shifts = true,
2523 .lower_bitfield_reverse = true,
2524 .lower_bit_count = true,
2525 .lower_cs_local_id_from_index = true,
2526 .lower_ffract = true,
2527 .lower_fmod = true,
2528 .lower_pack_unorm_2x16 = true,
2529 .lower_pack_snorm_2x16 = true,
2530 .lower_pack_unorm_4x8 = true,
2531 .lower_pack_snorm_4x8 = true,
2532 .lower_unpack_unorm_4x8 = true,
2533 .lower_unpack_snorm_4x8 = true,
2534 .lower_pack_half_2x16 = true,
2535 .lower_unpack_half_2x16 = true,
2536 .lower_fdiv = true,
2537 .lower_find_lsb = true,
2538 .lower_ffma = true,
2539 .lower_flrp32 = true,
2540 .lower_fpow = true,
2541 .lower_fsat = true,
2542 .lower_fsqrt = true,
2543 .lower_ifind_msb = true,
2544 .lower_isign = true,
2545 .lower_ldexp = true,
2546 .lower_mul_high = true,
2547 .lower_wpos_pntc = true,
2548 .lower_rotate = true,
2549 };
2550
2551 /**
2552 * When demoting a shader down to single-threaded, removes the THRSW
2553 * instructions (one will still be inserted at v3d_vir_to_qpu() for the
2554 * program end).
2555 */
2556 static void
2557 vir_remove_thrsw(struct v3d_compile *c)
2558 {
2559 vir_for_each_block(block, c) {
2560 vir_for_each_inst_safe(inst, block) {
2561 if (inst->qpu.sig.thrsw)
2562 vir_remove_instruction(c, inst);
2563 }
2564 }
2565
2566 c->last_thrsw = NULL;
2567 }
2568
2569 void
2570 vir_emit_last_thrsw(struct v3d_compile *c)
2571 {
2572 /* On V3D before 4.1, we need a TMU op to be outstanding when thread
2573 * switching, so disable threads if we didn't do any TMU ops (each of
2574 * which would have emitted a THRSW).
2575 */
2576 if (!c->last_thrsw_at_top_level && c->devinfo->ver < 41) {
2577 c->threads = 1;
2578 if (c->last_thrsw)
2579 vir_remove_thrsw(c);
2580 return;
2581 }
2582
2583 /* If we're threaded and the last THRSW was in conditional code, then
2584 * we need to emit another one so that we can flag it as the last
2585 * thrsw.
2586 */
2587 if (c->last_thrsw && !c->last_thrsw_at_top_level) {
2588 assert(c->devinfo->ver >= 41);
2589 vir_emit_thrsw(c);
2590 }
2591
2592 /* If we're threaded, then we need to mark the last THRSW instruction
2593 * so we can emit a pair of them at QPU emit time.
2594 *
2595 * For V3D 4.x, we can spawn the non-fragment shaders already in the
2596 * post-last-THRSW state, so we can skip this.
2597 */
2598 if (!c->last_thrsw && c->s->info.stage == MESA_SHADER_FRAGMENT) {
2599 assert(c->devinfo->ver >= 41);
2600 vir_emit_thrsw(c);
2601 }
2602
2603 if (c->last_thrsw)
2604 c->last_thrsw->is_last_thrsw = true;
2605 }
2606
2607 /* There's a flag in the shader for "center W is needed for reasons other than
2608 * non-centroid varyings", so we just walk the program after VIR optimization
2609 * to see if it's used. It should be harmless to set even if we only use
2610 * center W for varyings.
2611 */
2612 static void
2613 vir_check_payload_w(struct v3d_compile *c)
2614 {
2615 if (c->s->info.stage != MESA_SHADER_FRAGMENT)
2616 return;
2617
2618 vir_for_each_inst_inorder(inst, c) {
2619 for (int i = 0; i < vir_get_nsrc(inst); i++) {
2620 if (inst->src[i].file == QFILE_REG &&
2621 inst->src[i].index == 0) {
2622 c->uses_center_w = true;
2623 return;
2624 }
2625 }
2626 }
2627
2628 }
2629
2630 void
2631 v3d_nir_to_vir(struct v3d_compile *c)
2632 {
2633 if (V3D_DEBUG & (V3D_DEBUG_NIR |
2634 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2635 fprintf(stderr, "%s prog %d/%d NIR:\n",
2636 vir_get_stage_name(c),
2637 c->program_id, c->variant_id);
2638 nir_print_shader(c->s, stderr);
2639 }
2640
2641 nir_to_vir(c);
2642
2643 /* Emit the last THRSW before STVPM and TLB writes. */
2644 vir_emit_last_thrsw(c);
2645
2646 switch (c->s->info.stage) {
2647 case MESA_SHADER_FRAGMENT:
2648 emit_frag_end(c);
2649 break;
2650 case MESA_SHADER_VERTEX:
2651 emit_vert_end(c);
2652 break;
2653 case MESA_SHADER_COMPUTE:
2654 break;
2655 default:
2656 unreachable("bad stage");
2657 }
2658
2659 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2660 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2661 fprintf(stderr, "%s prog %d/%d pre-opt VIR:\n",
2662 vir_get_stage_name(c),
2663 c->program_id, c->variant_id);
2664 vir_dump(c);
2665 fprintf(stderr, "\n");
2666 }
2667
2668 vir_optimize(c);
2669
2670 vir_check_payload_w(c);
2671
2672 /* XXX perf: On VC4, we do a VIR-level instruction scheduling here.
2673 * We used that on that platform to pipeline TMU writes and reduce the
2674 * number of thread switches, as well as try (mostly successfully) to
2675 * reduce maximum register pressure to allow more threads. We should
2676 * do something of that sort for V3D -- either instruction scheduling
2677 * here, or delay the the THRSW and LDTMUs from our texture
2678 * instructions until the results are needed.
2679 */
2680
2681 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2682 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2683 fprintf(stderr, "%s prog %d/%d VIR:\n",
2684 vir_get_stage_name(c),
2685 c->program_id, c->variant_id);
2686 vir_dump(c);
2687 fprintf(stderr, "\n");
2688 }
2689
2690 /* Attempt to allocate registers for the temporaries. If we fail,
2691 * reduce thread count and try again.
2692 */
2693 int min_threads = (c->devinfo->ver >= 41) ? 2 : 1;
2694 struct qpu_reg *temp_registers;
2695 while (true) {
2696 bool spilled;
2697 temp_registers = v3d_register_allocate(c, &spilled);
2698 if (spilled)
2699 continue;
2700
2701 if (temp_registers)
2702 break;
2703
2704 if (c->threads == min_threads) {
2705 fprintf(stderr, "Failed to register allocate at %d threads:\n",
2706 c->threads);
2707 vir_dump(c);
2708 c->failed = true;
2709 return;
2710 }
2711
2712 c->threads /= 2;
2713
2714 if (c->threads == 1)
2715 vir_remove_thrsw(c);
2716 }
2717
2718 if (c->spills &&
2719 (V3D_DEBUG & (V3D_DEBUG_VIR |
2720 v3d_debug_flag_for_shader_stage(c->s->info.stage)))) {
2721 fprintf(stderr, "%s prog %d/%d spilled VIR:\n",
2722 vir_get_stage_name(c),
2723 c->program_id, c->variant_id);
2724 vir_dump(c);
2725 fprintf(stderr, "\n");
2726 }
2727
2728 v3d_vir_to_qpu(c, temp_registers);
2729 }