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[mesa.git] / src / broadcom / compiler / nir_to_vir.c
1 /*
2 * Copyright © 2016 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <inttypes.h>
25 #include "util/u_format.h"
26 #include "util/u_math.h"
27 #include "util/u_memory.h"
28 #include "util/ralloc.h"
29 #include "util/hash_table.h"
30 #include "compiler/nir/nir.h"
31 #include "compiler/nir/nir_builder.h"
32 #include "common/v3d_device_info.h"
33 #include "v3d_compiler.h"
34
35 static void
36 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
37
38 static void
39 resize_qreg_array(struct v3d_compile *c,
40 struct qreg **regs,
41 uint32_t *size,
42 uint32_t decl_size)
43 {
44 if (*size >= decl_size)
45 return;
46
47 uint32_t old_size = *size;
48 *size = MAX2(*size * 2, decl_size);
49 *regs = reralloc(c, *regs, struct qreg, *size);
50 if (!*regs) {
51 fprintf(stderr, "Malloc failure\n");
52 abort();
53 }
54
55 for (uint32_t i = old_size; i < *size; i++)
56 (*regs)[i] = c->undef;
57 }
58
59 void
60 vir_emit_thrsw(struct v3d_compile *c)
61 {
62 if (c->threads == 1)
63 return;
64
65 /* Always thread switch after each texture operation for now.
66 *
67 * We could do better by batching a bunch of texture fetches up and
68 * then doing one thread switch and collecting all their results
69 * afterward.
70 */
71 c->last_thrsw = vir_NOP(c);
72 c->last_thrsw->qpu.sig.thrsw = true;
73 c->last_thrsw_at_top_level = (c->execute.file == QFILE_NULL);
74 }
75
76 static struct qreg
77 vir_SFU(struct v3d_compile *c, int waddr, struct qreg src)
78 {
79 vir_FMOV_dest(c, vir_reg(QFILE_MAGIC, waddr), src);
80 return vir_FMOV(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4));
81 }
82
83 static struct qreg
84 indirect_uniform_load(struct v3d_compile *c, nir_intrinsic_instr *intr)
85 {
86 struct qreg indirect_offset = ntq_get_src(c, intr->src[0], 0);
87 uint32_t offset = nir_intrinsic_base(intr);
88 struct v3d_ubo_range *range = NULL;
89 unsigned i;
90
91 for (i = 0; i < c->num_ubo_ranges; i++) {
92 range = &c->ubo_ranges[i];
93 if (offset >= range->src_offset &&
94 offset < range->src_offset + range->size) {
95 break;
96 }
97 }
98 /* The driver-location-based offset always has to be within a declared
99 * uniform range.
100 */
101 assert(i != c->num_ubo_ranges);
102 if (!c->ubo_range_used[i]) {
103 c->ubo_range_used[i] = true;
104 range->dst_offset = c->next_ubo_dst_offset;
105 c->next_ubo_dst_offset += range->size;
106 }
107
108 offset -= range->src_offset;
109
110 if (range->dst_offset + offset != 0) {
111 indirect_offset = vir_ADD(c, indirect_offset,
112 vir_uniform_ui(c, range->dst_offset +
113 offset));
114 }
115
116 /* Adjust for where we stored the TGSI register base. */
117 vir_ADD_dest(c,
118 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUA),
119 vir_uniform(c, QUNIFORM_UBO_ADDR, 0),
120 indirect_offset);
121
122 vir_emit_thrsw(c);
123 return vir_LDTMU(c);
124 }
125
126 static struct qreg *
127 ntq_init_ssa_def(struct v3d_compile *c, nir_ssa_def *def)
128 {
129 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
130 def->num_components);
131 _mesa_hash_table_insert(c->def_ht, def, qregs);
132 return qregs;
133 }
134
135 /**
136 * This function is responsible for getting VIR results into the associated
137 * storage for a NIR instruction.
138 *
139 * If it's a NIR SSA def, then we just set the associated hash table entry to
140 * the new result.
141 *
142 * If it's a NIR reg, then we need to update the existing qreg assigned to the
143 * NIR destination with the incoming value. To do that without introducing
144 * new MOVs, we require that the incoming qreg either be a uniform, or be
145 * SSA-defined by the previous VIR instruction in the block and rewritable by
146 * this function. That lets us sneak ahead and insert the SF flag beforehand
147 * (knowing that the previous instruction doesn't depend on flags) and rewrite
148 * its destination to be the NIR reg's destination
149 */
150 void
151 ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int chan,
152 struct qreg result)
153 {
154 struct qinst *last_inst = NULL;
155 if (!list_empty(&c->cur_block->instructions))
156 last_inst = (struct qinst *)c->cur_block->instructions.prev;
157
158 assert(result.file == QFILE_UNIF ||
159 (result.file == QFILE_TEMP &&
160 last_inst && last_inst == c->defs[result.index]));
161
162 if (dest->is_ssa) {
163 assert(chan < dest->ssa.num_components);
164
165 struct qreg *qregs;
166 struct hash_entry *entry =
167 _mesa_hash_table_search(c->def_ht, &dest->ssa);
168
169 if (entry)
170 qregs = entry->data;
171 else
172 qregs = ntq_init_ssa_def(c, &dest->ssa);
173
174 qregs[chan] = result;
175 } else {
176 nir_register *reg = dest->reg.reg;
177 assert(dest->reg.base_offset == 0);
178 assert(reg->num_array_elems == 0);
179 struct hash_entry *entry =
180 _mesa_hash_table_search(c->def_ht, reg);
181 struct qreg *qregs = entry->data;
182
183 /* Insert a MOV if the source wasn't an SSA def in the
184 * previous instruction.
185 */
186 if (result.file == QFILE_UNIF) {
187 result = vir_MOV(c, result);
188 last_inst = c->defs[result.index];
189 }
190
191 /* We know they're both temps, so just rewrite index. */
192 c->defs[last_inst->dst.index] = NULL;
193 last_inst->dst.index = qregs[chan].index;
194
195 /* If we're in control flow, then make this update of the reg
196 * conditional on the execution mask.
197 */
198 if (c->execute.file != QFILE_NULL) {
199 last_inst->dst.index = qregs[chan].index;
200
201 /* Set the flags to the current exec mask.
202 */
203 c->cursor = vir_before_inst(last_inst);
204 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
205 c->cursor = vir_after_inst(last_inst);
206
207 vir_set_cond(last_inst, V3D_QPU_COND_IFA);
208 last_inst->cond_is_exec_mask = true;
209 }
210 }
211 }
212
213 struct qreg
214 ntq_get_src(struct v3d_compile *c, nir_src src, int i)
215 {
216 struct hash_entry *entry;
217 if (src.is_ssa) {
218 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
219 assert(i < src.ssa->num_components);
220 } else {
221 nir_register *reg = src.reg.reg;
222 entry = _mesa_hash_table_search(c->def_ht, reg);
223 assert(reg->num_array_elems == 0);
224 assert(src.reg.base_offset == 0);
225 assert(i < reg->num_components);
226 }
227
228 struct qreg *qregs = entry->data;
229 return qregs[i];
230 }
231
232 static struct qreg
233 ntq_get_alu_src(struct v3d_compile *c, nir_alu_instr *instr,
234 unsigned src)
235 {
236 assert(util_is_power_of_two(instr->dest.write_mask));
237 unsigned chan = ffs(instr->dest.write_mask) - 1;
238 struct qreg r = ntq_get_src(c, instr->src[src].src,
239 instr->src[src].swizzle[chan]);
240
241 assert(!instr->src[src].abs);
242 assert(!instr->src[src].negate);
243
244 return r;
245 };
246
247 static inline struct qreg
248 vir_SAT(struct v3d_compile *c, struct qreg val)
249 {
250 return vir_FMAX(c,
251 vir_FMIN(c, val, vir_uniform_f(c, 1.0)),
252 vir_uniform_f(c, 0.0));
253 }
254
255 static struct qreg
256 ntq_minify(struct v3d_compile *c, struct qreg size, struct qreg level)
257 {
258 return vir_MAX(c, vir_SHR(c, size, level), vir_uniform_ui(c, 1));
259 }
260
261 static void
262 ntq_emit_txs(struct v3d_compile *c, nir_tex_instr *instr)
263 {
264 unsigned unit = instr->texture_index;
265 int lod_index = nir_tex_instr_src_index(instr, nir_tex_src_lod);
266 int dest_size = nir_tex_instr_dest_size(instr);
267
268 struct qreg lod = c->undef;
269 if (lod_index != -1)
270 lod = ntq_get_src(c, instr->src[lod_index].src, 0);
271
272 for (int i = 0; i < dest_size; i++) {
273 assert(i < 3);
274 enum quniform_contents contents;
275
276 if (instr->is_array && i == dest_size - 1)
277 contents = QUNIFORM_TEXTURE_ARRAY_SIZE;
278 else
279 contents = QUNIFORM_TEXTURE_WIDTH + i;
280
281 struct qreg size = vir_uniform(c, contents, unit);
282
283 switch (instr->sampler_dim) {
284 case GLSL_SAMPLER_DIM_1D:
285 case GLSL_SAMPLER_DIM_2D:
286 case GLSL_SAMPLER_DIM_3D:
287 case GLSL_SAMPLER_DIM_CUBE:
288 /* Don't minify the array size. */
289 if (!(instr->is_array && i == dest_size - 1)) {
290 size = ntq_minify(c, size, lod);
291 }
292 break;
293
294 case GLSL_SAMPLER_DIM_RECT:
295 /* There's no LOD field for rects */
296 break;
297
298 default:
299 unreachable("Bad sampler type");
300 }
301
302 ntq_store_dest(c, &instr->dest, i, size);
303 }
304 }
305
306 static void
307 ntq_emit_tex(struct v3d_compile *c, nir_tex_instr *instr)
308 {
309 unsigned unit = instr->texture_index;
310
311 /* Since each texture sampling op requires uploading uniforms to
312 * reference the texture, there's no HW support for texture size and
313 * you just upload uniforms containing the size.
314 */
315 switch (instr->op) {
316 case nir_texop_query_levels:
317 ntq_store_dest(c, &instr->dest, 0,
318 vir_uniform(c, QUNIFORM_TEXTURE_LEVELS, unit));
319 return;
320 case nir_texop_txs:
321 ntq_emit_txs(c, instr);
322 return;
323 default:
324 break;
325 }
326
327 if (c->devinfo->ver >= 40)
328 v3d40_vir_emit_tex(c, instr);
329 else
330 v3d33_vir_emit_tex(c, instr);
331 }
332
333 static struct qreg
334 ntq_fsincos(struct v3d_compile *c, struct qreg src, bool is_cos)
335 {
336 struct qreg input = vir_FMUL(c, src, vir_uniform_f(c, 1.0f / M_PI));
337 if (is_cos)
338 input = vir_FADD(c, input, vir_uniform_f(c, 0.5));
339
340 struct qreg periods = vir_FROUND(c, input);
341 struct qreg sin_output = vir_SFU(c, V3D_QPU_WADDR_SIN,
342 vir_FSUB(c, input, periods));
343 return vir_XOR(c, sin_output, vir_SHL(c,
344 vir_FTOIN(c, periods),
345 vir_uniform_ui(c, -1)));
346 }
347
348 static struct qreg
349 ntq_fsign(struct v3d_compile *c, struct qreg src)
350 {
351 struct qreg t = vir_get_temp(c);
352
353 vir_MOV_dest(c, t, vir_uniform_f(c, 0.0));
354 vir_PF(c, vir_FMOV(c, src), V3D_QPU_PF_PUSHZ);
355 vir_MOV_cond(c, V3D_QPU_COND_IFNA, t, vir_uniform_f(c, 1.0));
356 vir_PF(c, vir_FMOV(c, src), V3D_QPU_PF_PUSHN);
357 vir_MOV_cond(c, V3D_QPU_COND_IFA, t, vir_uniform_f(c, -1.0));
358 return vir_MOV(c, t);
359 }
360
361 static struct qreg
362 ntq_isign(struct v3d_compile *c, struct qreg src)
363 {
364 struct qreg t = vir_get_temp(c);
365
366 vir_MOV_dest(c, t, vir_uniform_ui(c, 0));
367 vir_PF(c, vir_MOV(c, src), V3D_QPU_PF_PUSHZ);
368 vir_MOV_cond(c, V3D_QPU_COND_IFNA, t, vir_uniform_ui(c, 1));
369 vir_PF(c, vir_MOV(c, src), V3D_QPU_PF_PUSHN);
370 vir_MOV_cond(c, V3D_QPU_COND_IFA, t, vir_uniform_ui(c, -1));
371 return vir_MOV(c, t);
372 }
373
374 static void
375 emit_fragcoord_input(struct v3d_compile *c, int attr)
376 {
377 c->inputs[attr * 4 + 0] = vir_FXCD(c);
378 c->inputs[attr * 4 + 1] = vir_FYCD(c);
379 c->inputs[attr * 4 + 2] = c->payload_z;
380 c->inputs[attr * 4 + 3] = vir_SFU(c, V3D_QPU_WADDR_RECIP,
381 c->payload_w);
382 }
383
384 static struct qreg
385 emit_fragment_varying(struct v3d_compile *c, nir_variable *var,
386 uint8_t swizzle)
387 {
388 struct qreg r3 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R3);
389 struct qreg r5 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R5);
390
391 struct qreg vary;
392 if (c->devinfo->ver >= 41) {
393 struct qinst *ldvary = vir_add_inst(V3D_QPU_A_NOP, c->undef,
394 c->undef, c->undef);
395 ldvary->qpu.sig.ldvary = true;
396 vary = vir_emit_def(c, ldvary);
397 } else {
398 vir_NOP(c)->qpu.sig.ldvary = true;
399 vary = r3;
400 }
401
402 /* For gl_PointCoord input or distance along a line, we'll be called
403 * with no nir_variable, and we don't count toward VPM size so we
404 * don't track an input slot.
405 */
406 if (!var) {
407 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
408 }
409
410 int i = c->num_inputs++;
411 c->input_slots[i] = v3d_slot_from_slot_and_component(var->data.location,
412 swizzle);
413
414 switch (var->data.interpolation) {
415 case INTERP_MODE_NONE:
416 /* If a gl_FrontColor or gl_BackColor input has no interp
417 * qualifier, then if we're using glShadeModel(GL_FLAT) it
418 * needs to be flat shaded.
419 */
420 switch (var->data.location) {
421 case VARYING_SLOT_COL0:
422 case VARYING_SLOT_COL1:
423 case VARYING_SLOT_BFC0:
424 case VARYING_SLOT_BFC1:
425 if (c->fs_key->shade_model_flat) {
426 BITSET_SET(c->flat_shade_flags, i);
427 vir_MOV_dest(c, c->undef, vary);
428 return vir_MOV(c, r5);
429 } else {
430 return vir_FADD(c, vir_FMUL(c, vary,
431 c->payload_w), r5);
432 }
433 default:
434 break;
435 }
436 /* FALLTHROUGH */
437 case INTERP_MODE_SMOOTH:
438 if (var->data.centroid) {
439 return vir_FADD(c, vir_FMUL(c, vary,
440 c->payload_w_centroid), r5);
441 } else {
442 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
443 }
444 case INTERP_MODE_NOPERSPECTIVE:
445 /* C appears after the mov from the varying.
446 XXX: improve ldvary setup.
447 */
448 return vir_FADD(c, vir_MOV(c, vary), r5);
449 case INTERP_MODE_FLAT:
450 BITSET_SET(c->flat_shade_flags, i);
451 vir_MOV_dest(c, c->undef, vary);
452 return vir_MOV(c, r5);
453 default:
454 unreachable("Bad interp mode");
455 }
456 }
457
458 static void
459 emit_fragment_input(struct v3d_compile *c, int attr, nir_variable *var)
460 {
461 for (int i = 0; i < glsl_get_vector_elements(var->type); i++) {
462 int chan = var->data.location_frac + i;
463 c->inputs[attr * 4 + chan] =
464 emit_fragment_varying(c, var, chan);
465 }
466 }
467
468 static void
469 add_output(struct v3d_compile *c,
470 uint32_t decl_offset,
471 uint8_t slot,
472 uint8_t swizzle)
473 {
474 uint32_t old_array_size = c->outputs_array_size;
475 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
476 decl_offset + 1);
477
478 if (old_array_size != c->outputs_array_size) {
479 c->output_slots = reralloc(c,
480 c->output_slots,
481 struct v3d_varying_slot,
482 c->outputs_array_size);
483 }
484
485 c->output_slots[decl_offset] =
486 v3d_slot_from_slot_and_component(slot, swizzle);
487 }
488
489 static void
490 declare_uniform_range(struct v3d_compile *c, uint32_t start, uint32_t size)
491 {
492 unsigned array_id = c->num_ubo_ranges++;
493 if (array_id >= c->ubo_ranges_array_size) {
494 c->ubo_ranges_array_size = MAX2(c->ubo_ranges_array_size * 2,
495 array_id + 1);
496 c->ubo_ranges = reralloc(c, c->ubo_ranges,
497 struct v3d_ubo_range,
498 c->ubo_ranges_array_size);
499 c->ubo_range_used = reralloc(c, c->ubo_range_used,
500 bool,
501 c->ubo_ranges_array_size);
502 }
503
504 c->ubo_ranges[array_id].dst_offset = 0;
505 c->ubo_ranges[array_id].src_offset = start;
506 c->ubo_ranges[array_id].size = size;
507 c->ubo_range_used[array_id] = false;
508 }
509
510 /**
511 * If compare_instr is a valid comparison instruction, emits the
512 * compare_instr's comparison and returns the sel_instr's return value based
513 * on the compare_instr's result.
514 */
515 static bool
516 ntq_emit_comparison(struct v3d_compile *c, struct qreg *dest,
517 nir_alu_instr *compare_instr,
518 nir_alu_instr *sel_instr)
519 {
520 struct qreg src0 = ntq_get_alu_src(c, compare_instr, 0);
521 struct qreg src1;
522 if (nir_op_infos[compare_instr->op].num_inputs > 1)
523 src1 = ntq_get_alu_src(c, compare_instr, 1);
524 bool cond_invert = false;
525
526 switch (compare_instr->op) {
527 case nir_op_feq:
528 case nir_op_seq:
529 vir_PF(c, vir_FCMP(c, src0, src1), V3D_QPU_PF_PUSHZ);
530 break;
531 case nir_op_ieq:
532 vir_PF(c, vir_XOR(c, src0, src1), V3D_QPU_PF_PUSHZ);
533 break;
534
535 case nir_op_fne:
536 case nir_op_sne:
537 vir_PF(c, vir_FCMP(c, src0, src1), V3D_QPU_PF_PUSHZ);
538 cond_invert = true;
539 break;
540 case nir_op_ine:
541 vir_PF(c, vir_XOR(c, src0, src1), V3D_QPU_PF_PUSHZ);
542 cond_invert = true;
543 break;
544
545 case nir_op_fge:
546 case nir_op_sge:
547 vir_PF(c, vir_FCMP(c, src1, src0), V3D_QPU_PF_PUSHC);
548 break;
549 case nir_op_ige:
550 vir_PF(c, vir_MIN(c, src1, src0), V3D_QPU_PF_PUSHC);
551 cond_invert = true;
552 break;
553 case nir_op_uge:
554 vir_PF(c, vir_SUB(c, src0, src1), V3D_QPU_PF_PUSHC);
555 cond_invert = true;
556 break;
557
558 case nir_op_slt:
559 case nir_op_flt:
560 vir_PF(c, vir_FCMP(c, src0, src1), V3D_QPU_PF_PUSHN);
561 break;
562 case nir_op_ilt:
563 vir_PF(c, vir_MIN(c, src1, src0), V3D_QPU_PF_PUSHC);
564 break;
565 case nir_op_ult:
566 vir_PF(c, vir_SUB(c, src0, src1), V3D_QPU_PF_PUSHC);
567 break;
568
569 default:
570 return false;
571 }
572
573 enum v3d_qpu_cond cond = (cond_invert ?
574 V3D_QPU_COND_IFNA :
575 V3D_QPU_COND_IFA);
576
577 switch (sel_instr->op) {
578 case nir_op_seq:
579 case nir_op_sne:
580 case nir_op_sge:
581 case nir_op_slt:
582 *dest = vir_SEL(c, cond,
583 vir_uniform_f(c, 1.0), vir_uniform_f(c, 0.0));
584 break;
585
586 case nir_op_bcsel:
587 *dest = vir_SEL(c, cond,
588 ntq_get_alu_src(c, sel_instr, 1),
589 ntq_get_alu_src(c, sel_instr, 2));
590 break;
591
592 default:
593 *dest = vir_SEL(c, cond,
594 vir_uniform_ui(c, ~0), vir_uniform_ui(c, 0));
595 break;
596 }
597
598 /* Make the temporary for nir_store_dest(). */
599 *dest = vir_MOV(c, *dest);
600
601 return true;
602 }
603
604 /**
605 * Attempts to fold a comparison generating a boolean result into the
606 * condition code for selecting between two values, instead of comparing the
607 * boolean result against 0 to generate the condition code.
608 */
609 static struct qreg ntq_emit_bcsel(struct v3d_compile *c, nir_alu_instr *instr,
610 struct qreg *src)
611 {
612 if (!instr->src[0].src.is_ssa)
613 goto out;
614 if (instr->src[0].src.ssa->parent_instr->type != nir_instr_type_alu)
615 goto out;
616 nir_alu_instr *compare =
617 nir_instr_as_alu(instr->src[0].src.ssa->parent_instr);
618 if (!compare)
619 goto out;
620
621 struct qreg dest;
622 if (ntq_emit_comparison(c, &dest, compare, instr))
623 return dest;
624
625 out:
626 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
627 return vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA, src[1], src[2]));
628 }
629
630
631 static void
632 ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr)
633 {
634 /* This should always be lowered to ALU operations for V3D. */
635 assert(!instr->dest.saturate);
636
637 /* Vectors are special in that they have non-scalarized writemasks,
638 * and just take the first swizzle channel for each argument in order
639 * into each writemask channel.
640 */
641 if (instr->op == nir_op_vec2 ||
642 instr->op == nir_op_vec3 ||
643 instr->op == nir_op_vec4) {
644 struct qreg srcs[4];
645 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
646 srcs[i] = ntq_get_src(c, instr->src[i].src,
647 instr->src[i].swizzle[0]);
648 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
649 ntq_store_dest(c, &instr->dest.dest, i,
650 vir_MOV(c, srcs[i]));
651 return;
652 }
653
654 /* General case: We can just grab the one used channel per src. */
655 struct qreg src[nir_op_infos[instr->op].num_inputs];
656 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
657 src[i] = ntq_get_alu_src(c, instr, i);
658 }
659
660 struct qreg result;
661
662 switch (instr->op) {
663 case nir_op_fmov:
664 case nir_op_imov:
665 result = vir_MOV(c, src[0]);
666 break;
667
668 case nir_op_fneg:
669 result = vir_XOR(c, src[0], vir_uniform_ui(c, 1 << 31));
670 break;
671 case nir_op_ineg:
672 result = vir_NEG(c, src[0]);
673 break;
674
675 case nir_op_fmul:
676 result = vir_FMUL(c, src[0], src[1]);
677 break;
678 case nir_op_fadd:
679 result = vir_FADD(c, src[0], src[1]);
680 break;
681 case nir_op_fsub:
682 result = vir_FSUB(c, src[0], src[1]);
683 break;
684 case nir_op_fmin:
685 result = vir_FMIN(c, src[0], src[1]);
686 break;
687 case nir_op_fmax:
688 result = vir_FMAX(c, src[0], src[1]);
689 break;
690
691 case nir_op_f2i32:
692 result = vir_FTOIZ(c, src[0]);
693 break;
694 case nir_op_f2u32:
695 result = vir_FTOUZ(c, src[0]);
696 break;
697 case nir_op_i2f32:
698 result = vir_ITOF(c, src[0]);
699 break;
700 case nir_op_u2f32:
701 result = vir_UTOF(c, src[0]);
702 break;
703 case nir_op_b2f:
704 result = vir_AND(c, src[0], vir_uniform_f(c, 1.0));
705 break;
706 case nir_op_b2i:
707 result = vir_AND(c, src[0], vir_uniform_ui(c, 1));
708 break;
709 case nir_op_i2b:
710 case nir_op_f2b:
711 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
712 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
713 vir_uniform_ui(c, ~0),
714 vir_uniform_ui(c, 0)));
715 break;
716
717 case nir_op_iadd:
718 result = vir_ADD(c, src[0], src[1]);
719 break;
720 case nir_op_ushr:
721 result = vir_SHR(c, src[0], src[1]);
722 break;
723 case nir_op_isub:
724 result = vir_SUB(c, src[0], src[1]);
725 break;
726 case nir_op_ishr:
727 result = vir_ASR(c, src[0], src[1]);
728 break;
729 case nir_op_ishl:
730 result = vir_SHL(c, src[0], src[1]);
731 break;
732 case nir_op_imin:
733 result = vir_MIN(c, src[0], src[1]);
734 break;
735 case nir_op_umin:
736 result = vir_UMIN(c, src[0], src[1]);
737 break;
738 case nir_op_imax:
739 result = vir_MAX(c, src[0], src[1]);
740 break;
741 case nir_op_umax:
742 result = vir_UMAX(c, src[0], src[1]);
743 break;
744 case nir_op_iand:
745 result = vir_AND(c, src[0], src[1]);
746 break;
747 case nir_op_ior:
748 result = vir_OR(c, src[0], src[1]);
749 break;
750 case nir_op_ixor:
751 result = vir_XOR(c, src[0], src[1]);
752 break;
753 case nir_op_inot:
754 result = vir_NOT(c, src[0]);
755 break;
756
757 case nir_op_imul:
758 result = vir_UMUL(c, src[0], src[1]);
759 break;
760
761 case nir_op_seq:
762 case nir_op_sne:
763 case nir_op_sge:
764 case nir_op_slt:
765 case nir_op_feq:
766 case nir_op_fne:
767 case nir_op_fge:
768 case nir_op_flt:
769 case nir_op_ieq:
770 case nir_op_ine:
771 case nir_op_ige:
772 case nir_op_uge:
773 case nir_op_ilt:
774 case nir_op_ult:
775 if (!ntq_emit_comparison(c, &result, instr, instr)) {
776 fprintf(stderr, "Bad comparison instruction\n");
777 }
778 break;
779
780 case nir_op_bcsel:
781 result = ntq_emit_bcsel(c, instr, src);
782 break;
783 case nir_op_fcsel:
784 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
785 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
786 src[1], src[2]));
787 break;
788
789 case nir_op_frcp:
790 result = vir_SFU(c, V3D_QPU_WADDR_RECIP, src[0]);
791 break;
792 case nir_op_frsq:
793 result = vir_SFU(c, V3D_QPU_WADDR_RSQRT, src[0]);
794 break;
795 case nir_op_fexp2:
796 result = vir_SFU(c, V3D_QPU_WADDR_EXP, src[0]);
797 break;
798 case nir_op_flog2:
799 result = vir_SFU(c, V3D_QPU_WADDR_LOG, src[0]);
800 break;
801
802 case nir_op_fceil:
803 result = vir_FCEIL(c, src[0]);
804 break;
805 case nir_op_ffloor:
806 result = vir_FFLOOR(c, src[0]);
807 break;
808 case nir_op_fround_even:
809 result = vir_FROUND(c, src[0]);
810 break;
811 case nir_op_ftrunc:
812 result = vir_FTRUNC(c, src[0]);
813 break;
814 case nir_op_ffract:
815 result = vir_FSUB(c, src[0], vir_FFLOOR(c, src[0]));
816 break;
817
818 case nir_op_fsin:
819 result = ntq_fsincos(c, src[0], false);
820 break;
821 case nir_op_fcos:
822 result = ntq_fsincos(c, src[0], true);
823 break;
824
825 case nir_op_fsign:
826 result = ntq_fsign(c, src[0]);
827 break;
828 case nir_op_isign:
829 result = ntq_isign(c, src[0]);
830 break;
831
832 case nir_op_fabs: {
833 result = vir_FMOV(c, src[0]);
834 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_ABS);
835 break;
836 }
837
838 case nir_op_iabs:
839 result = vir_MAX(c, src[0],
840 vir_SUB(c, vir_uniform_ui(c, 0), src[0]));
841 break;
842
843 case nir_op_fddx:
844 case nir_op_fddx_coarse:
845 case nir_op_fddx_fine:
846 result = vir_FDX(c, src[0]);
847 break;
848
849 case nir_op_fddy:
850 case nir_op_fddy_coarse:
851 case nir_op_fddy_fine:
852 result = vir_FDY(c, src[0]);
853 break;
854
855 default:
856 fprintf(stderr, "unknown NIR ALU inst: ");
857 nir_print_instr(&instr->instr, stderr);
858 fprintf(stderr, "\n");
859 abort();
860 }
861
862 /* We have a scalar result, so the instruction should only have a
863 * single channel written to.
864 */
865 assert(util_is_power_of_two(instr->dest.write_mask));
866 ntq_store_dest(c, &instr->dest.dest,
867 ffs(instr->dest.write_mask) - 1, result);
868 }
869
870 /* Each TLB read/write setup (a render target or depth buffer) takes an 8-bit
871 * specifier. They come from a register that's preloaded with 0xffffffff
872 * (0xff gets you normal vec4 f16 RT0 writes), and when one is neaded the low
873 * 8 bits are shifted off the bottom and 0xff shifted in from the top.
874 */
875 #define TLB_TYPE_F16_COLOR (3 << 6)
876 #define TLB_TYPE_I32_COLOR (1 << 6)
877 #define TLB_TYPE_F32_COLOR (0 << 6)
878 #define TLB_RENDER_TARGET_SHIFT 3 /* Reversed! 7 = RT 0, 0 = RT 7. */
879 #define TLB_SAMPLE_MODE_PER_SAMPLE (0 << 2)
880 #define TLB_SAMPLE_MODE_PER_PIXEL (1 << 2)
881 #define TLB_F16_SWAP_HI_LO (1 << 1)
882 #define TLB_VEC_SIZE_4_F16 (1 << 0)
883 #define TLB_VEC_SIZE_2_F16 (0 << 0)
884 #define TLB_VEC_SIZE_MINUS_1_SHIFT 0
885
886 /* Triggers Z/Stencil testing, used when the shader state's "FS modifies Z"
887 * flag is set.
888 */
889 #define TLB_TYPE_DEPTH ((2 << 6) | (0 << 4))
890 #define TLB_DEPTH_TYPE_INVARIANT (0 << 2) /* Unmodified sideband input used */
891 #define TLB_DEPTH_TYPE_PER_PIXEL (1 << 2) /* QPU result used */
892
893 /* Stencil is a single 32-bit write. */
894 #define TLB_TYPE_STENCIL_ALPHA ((2 << 6) | (1 << 4))
895
896 static void
897 emit_frag_end(struct v3d_compile *c)
898 {
899 /* XXX
900 if (c->output_sample_mask_index != -1) {
901 vir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
902 }
903 */
904
905 bool has_any_tlb_color_write = false;
906 for (int rt = 0; rt < c->fs_key->nr_cbufs; rt++) {
907 if (c->output_color_var[rt])
908 has_any_tlb_color_write = true;
909 }
910
911 if (c->output_position_index != -1) {
912 struct qinst *inst = vir_MOV_dest(c,
913 vir_reg(QFILE_TLBU, 0),
914 c->outputs[c->output_position_index]);
915
916 inst->src[vir_get_implicit_uniform_src(inst)] =
917 vir_uniform_ui(c,
918 TLB_TYPE_DEPTH |
919 TLB_DEPTH_TYPE_PER_PIXEL |
920 0xffffff00);
921 } else if (c->s->info.fs.uses_discard || !has_any_tlb_color_write) {
922 /* Emit passthrough Z if it needed to be delayed until shader
923 * end due to potential discards.
924 *
925 * Since (single-threaded) fragment shaders always need a TLB
926 * write, emit passthrouh Z if we didn't have any color
927 * buffers and flag us as potentially discarding, so that we
928 * can use Z as the TLB write.
929 */
930 c->s->info.fs.uses_discard = true;
931
932 struct qinst *inst = vir_MOV_dest(c,
933 vir_reg(QFILE_TLBU, 0),
934 vir_reg(QFILE_NULL, 0));
935
936 inst->src[vir_get_implicit_uniform_src(inst)] =
937 vir_uniform_ui(c,
938 TLB_TYPE_DEPTH |
939 TLB_DEPTH_TYPE_INVARIANT |
940 0xffffff00);
941 }
942
943 /* XXX: Performance improvement: Merge Z write and color writes TLB
944 * uniform setup
945 */
946
947 for (int rt = 0; rt < c->fs_key->nr_cbufs; rt++) {
948 if (!c->output_color_var[rt])
949 continue;
950
951 nir_variable *var = c->output_color_var[rt];
952 struct qreg *color = &c->outputs[var->data.driver_location * 4];
953 int num_components = glsl_get_vector_elements(var->type);
954 uint32_t conf = 0xffffff00;
955 struct qinst *inst;
956
957 conf |= TLB_SAMPLE_MODE_PER_PIXEL;
958 conf |= (7 - rt) << TLB_RENDER_TARGET_SHIFT;
959
960 assert(num_components != 0);
961 switch (glsl_get_base_type(var->type)) {
962 case GLSL_TYPE_UINT:
963 case GLSL_TYPE_INT:
964 /* The F32 vs I32 distinction was dropped in 4.2. */
965 if (c->devinfo->ver < 42)
966 conf |= TLB_TYPE_I32_COLOR;
967 else
968 conf |= TLB_TYPE_F32_COLOR;
969 conf |= ((num_components - 1) <<
970 TLB_VEC_SIZE_MINUS_1_SHIFT);
971
972 inst = vir_MOV_dest(c, vir_reg(QFILE_TLBU, 0), color[0]);
973 inst->src[vir_get_implicit_uniform_src(inst)] =
974 vir_uniform_ui(c, conf);
975
976 for (int i = 1; i < num_components; i++) {
977 inst = vir_MOV_dest(c, vir_reg(QFILE_TLB, 0),
978 color[i]);
979 }
980 break;
981
982 default: {
983 struct qreg r = color[0];
984 struct qreg g = color[1];
985 struct qreg b = color[2];
986 struct qreg a = color[3];
987
988 if (c->fs_key->f32_color_rb) {
989 conf |= TLB_TYPE_F32_COLOR;
990 conf |= ((num_components - 1) <<
991 TLB_VEC_SIZE_MINUS_1_SHIFT);
992 } else {
993 conf |= TLB_TYPE_F16_COLOR;
994 conf |= TLB_F16_SWAP_HI_LO;
995 if (num_components >= 3)
996 conf |= TLB_VEC_SIZE_4_F16;
997 else
998 conf |= TLB_VEC_SIZE_2_F16;
999 }
1000
1001 if (c->fs_key->swap_color_rb & (1 << rt)) {
1002 r = color[2];
1003 b = color[0];
1004 }
1005
1006 if (c->fs_key->f32_color_rb & (1 << rt)) {
1007 inst = vir_MOV_dest(c, vir_reg(QFILE_TLBU, 0), color[0]);
1008 inst->src[vir_get_implicit_uniform_src(inst)] =
1009 vir_uniform_ui(c, conf);
1010
1011 for (int i = 1; i < num_components; i++) {
1012 inst = vir_MOV_dest(c, vir_reg(QFILE_TLB, 0),
1013 color[i]);
1014 }
1015 } else {
1016 inst = vir_VFPACK_dest(c, vir_reg(QFILE_TLB, 0), r, g);
1017 if (conf != ~0) {
1018 inst->dst.file = QFILE_TLBU;
1019 inst->src[vir_get_implicit_uniform_src(inst)] =
1020 vir_uniform_ui(c, conf);
1021 }
1022
1023 if (num_components >= 3)
1024 inst = vir_VFPACK_dest(c, vir_reg(QFILE_TLB, 0), b, a);
1025 }
1026 break;
1027 }
1028 }
1029 }
1030 }
1031
1032 static void
1033 vir_VPM_WRITE(struct v3d_compile *c, struct qreg val, uint32_t *vpm_index)
1034 {
1035 if (c->devinfo->ver >= 40) {
1036 vir_STVPMV(c, vir_uniform_ui(c, *vpm_index), val);
1037 *vpm_index = *vpm_index + 1;
1038 } else {
1039 vir_MOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_VPM), val);
1040 }
1041
1042 c->num_vpm_writes++;
1043 }
1044
1045 static void
1046 emit_scaled_viewport_write(struct v3d_compile *c, struct qreg rcp_w,
1047 uint32_t *vpm_index)
1048 {
1049 for (int i = 0; i < 2; i++) {
1050 struct qreg coord = c->outputs[c->output_position_index + i];
1051 coord = vir_FMUL(c, coord,
1052 vir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i,
1053 0));
1054 coord = vir_FMUL(c, coord, rcp_w);
1055 vir_VPM_WRITE(c, vir_FTOIN(c, coord), vpm_index);
1056 }
1057
1058 }
1059
1060 static void
1061 emit_zs_write(struct v3d_compile *c, struct qreg rcp_w, uint32_t *vpm_index)
1062 {
1063 struct qreg zscale = vir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1064 struct qreg zoffset = vir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1065
1066 struct qreg z = c->outputs[c->output_position_index + 2];
1067 z = vir_FMUL(c, z, zscale);
1068 z = vir_FMUL(c, z, rcp_w);
1069 z = vir_FADD(c, z, zoffset);
1070 vir_VPM_WRITE(c, z, vpm_index);
1071 }
1072
1073 static void
1074 emit_rcp_wc_write(struct v3d_compile *c, struct qreg rcp_w, uint32_t *vpm_index)
1075 {
1076 vir_VPM_WRITE(c, rcp_w, vpm_index);
1077 }
1078
1079 static void
1080 emit_point_size_write(struct v3d_compile *c, uint32_t *vpm_index)
1081 {
1082 struct qreg point_size;
1083
1084 if (c->output_point_size_index != -1)
1085 point_size = c->outputs[c->output_point_size_index];
1086 else
1087 point_size = vir_uniform_f(c, 1.0);
1088
1089 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1090 * BCM21553).
1091 */
1092 point_size = vir_FMAX(c, point_size, vir_uniform_f(c, .125));
1093
1094 vir_VPM_WRITE(c, point_size, vpm_index);
1095 }
1096
1097 static void
1098 emit_vpm_write_setup(struct v3d_compile *c)
1099 {
1100 if (c->devinfo->ver >= 40)
1101 return;
1102
1103 v3d33_vir_vpm_write_setup(c);
1104 }
1105
1106 /**
1107 * Sets up c->outputs[c->output_position_index] for the vertex shader
1108 * epilogue, if an output vertex position wasn't specified in the user's
1109 * shader. This may be the case for transform feedback with rasterizer
1110 * discard enabled.
1111 */
1112 static void
1113 setup_default_position(struct v3d_compile *c)
1114 {
1115 if (c->output_position_index != -1)
1116 return;
1117
1118 c->output_position_index = c->outputs_array_size;
1119 for (int i = 0; i < 4; i++) {
1120 add_output(c,
1121 c->output_position_index + i,
1122 VARYING_SLOT_POS, i);
1123 }
1124 }
1125
1126 static void
1127 emit_vert_end(struct v3d_compile *c)
1128 {
1129 setup_default_position(c);
1130
1131 uint32_t vpm_index = 0;
1132 struct qreg rcp_w = vir_SFU(c, V3D_QPU_WADDR_RECIP,
1133 c->outputs[c->output_position_index + 3]);
1134
1135 emit_vpm_write_setup(c);
1136
1137 if (c->vs_key->is_coord) {
1138 for (int i = 0; i < 4; i++)
1139 vir_VPM_WRITE(c, c->outputs[c->output_position_index + i],
1140 &vpm_index);
1141 emit_scaled_viewport_write(c, rcp_w, &vpm_index);
1142 if (c->vs_key->per_vertex_point_size) {
1143 emit_point_size_write(c, &vpm_index);
1144 /* emit_rcp_wc_write(c, rcp_w); */
1145 }
1146 /* XXX: Z-only rendering */
1147 if (0)
1148 emit_zs_write(c, rcp_w, &vpm_index);
1149 } else {
1150 emit_scaled_viewport_write(c, rcp_w, &vpm_index);
1151 emit_zs_write(c, rcp_w, &vpm_index);
1152 emit_rcp_wc_write(c, rcp_w, &vpm_index);
1153 if (c->vs_key->per_vertex_point_size)
1154 emit_point_size_write(c, &vpm_index);
1155 }
1156
1157 for (int i = 0; i < c->vs_key->num_fs_inputs; i++) {
1158 struct v3d_varying_slot input = c->vs_key->fs_inputs[i];
1159 int j;
1160
1161 for (j = 0; j < c->num_outputs; j++) {
1162 struct v3d_varying_slot output = c->output_slots[j];
1163
1164 if (!memcmp(&input, &output, sizeof(input))) {
1165 vir_VPM_WRITE(c, c->outputs[j],
1166 &vpm_index);
1167 break;
1168 }
1169 }
1170 /* Emit padding if we didn't find a declared VS output for
1171 * this FS input.
1172 */
1173 if (j == c->num_outputs)
1174 vir_VPM_WRITE(c, vir_uniform_f(c, 0.0),
1175 &vpm_index);
1176 }
1177
1178 /* GFXH-1684: VPM writes need to be complete by the end of the shader.
1179 */
1180 if (c->devinfo->ver >= 40 && c->devinfo->ver <= 42)
1181 vir_VPMWT(c);
1182 }
1183
1184 void
1185 v3d_optimize_nir(struct nir_shader *s)
1186 {
1187 bool progress;
1188
1189 do {
1190 progress = false;
1191
1192 NIR_PASS_V(s, nir_lower_vars_to_ssa);
1193 NIR_PASS(progress, s, nir_lower_alu_to_scalar);
1194 NIR_PASS(progress, s, nir_lower_phis_to_scalar);
1195 NIR_PASS(progress, s, nir_copy_prop);
1196 NIR_PASS(progress, s, nir_opt_remove_phis);
1197 NIR_PASS(progress, s, nir_opt_dce);
1198 NIR_PASS(progress, s, nir_opt_dead_cf);
1199 NIR_PASS(progress, s, nir_opt_cse);
1200 NIR_PASS(progress, s, nir_opt_peephole_select, 8);
1201 NIR_PASS(progress, s, nir_opt_algebraic);
1202 NIR_PASS(progress, s, nir_opt_constant_folding);
1203 NIR_PASS(progress, s, nir_opt_undef);
1204 } while (progress);
1205 }
1206
1207 static int
1208 driver_location_compare(const void *in_a, const void *in_b)
1209 {
1210 const nir_variable *const *a = in_a;
1211 const nir_variable *const *b = in_b;
1212
1213 return (*a)->data.driver_location - (*b)->data.driver_location;
1214 }
1215
1216 static struct qreg
1217 ntq_emit_vpm_read(struct v3d_compile *c,
1218 uint32_t *num_components_queued,
1219 uint32_t *remaining,
1220 uint32_t vpm_index)
1221 {
1222 struct qreg vpm = vir_reg(QFILE_VPM, vpm_index);
1223
1224 if (c->devinfo->ver >= 40 ) {
1225 return vir_LDVPMV_IN(c,
1226 vir_uniform_ui(c,
1227 (*num_components_queued)++));
1228 }
1229
1230 if (*num_components_queued != 0) {
1231 (*num_components_queued)--;
1232 c->num_inputs++;
1233 return vir_MOV(c, vpm);
1234 }
1235
1236 uint32_t num_components = MIN2(*remaining, 32);
1237
1238 v3d33_vir_vpm_read_setup(c, num_components);
1239
1240 *num_components_queued = num_components - 1;
1241 *remaining -= num_components;
1242 c->num_inputs++;
1243
1244 return vir_MOV(c, vpm);
1245 }
1246
1247 static void
1248 ntq_setup_inputs(struct v3d_compile *c)
1249 {
1250 unsigned num_entries = 0;
1251 unsigned num_components = 0;
1252 nir_foreach_variable(var, &c->s->inputs) {
1253 num_entries++;
1254 num_components += glsl_get_components(var->type);
1255 }
1256
1257 nir_variable *vars[num_entries];
1258
1259 unsigned i = 0;
1260 nir_foreach_variable(var, &c->s->inputs)
1261 vars[i++] = var;
1262
1263 /* Sort the variables so that we emit the input setup in
1264 * driver_location order. This is required for VPM reads, whose data
1265 * is fetched into the VPM in driver_location (TGSI register index)
1266 * order.
1267 */
1268 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1269
1270 uint32_t vpm_components_queued = 0;
1271 if (c->s->info.stage == MESA_SHADER_VERTEX) {
1272 bool uses_iid = c->s->info.system_values_read &
1273 (1ull << SYSTEM_VALUE_INSTANCE_ID);
1274 bool uses_vid = c->s->info.system_values_read &
1275 (1ull << SYSTEM_VALUE_VERTEX_ID);
1276
1277 num_components += uses_iid;
1278 num_components += uses_vid;
1279
1280 if (uses_iid) {
1281 c->iid = ntq_emit_vpm_read(c, &vpm_components_queued,
1282 &num_components, ~0);
1283 }
1284
1285 if (uses_vid) {
1286 c->vid = ntq_emit_vpm_read(c, &vpm_components_queued,
1287 &num_components, ~0);
1288 }
1289 }
1290
1291 for (unsigned i = 0; i < num_entries; i++) {
1292 nir_variable *var = vars[i];
1293 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1294 unsigned loc = var->data.driver_location;
1295
1296 assert(array_len == 1);
1297 (void)array_len;
1298 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1299 (loc + 1) * 4);
1300
1301 if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
1302 if (var->data.location == VARYING_SLOT_POS) {
1303 emit_fragcoord_input(c, loc);
1304 } else if (var->data.location == VARYING_SLOT_PNTC ||
1305 (var->data.location >= VARYING_SLOT_VAR0 &&
1306 (c->fs_key->point_sprite_mask &
1307 (1 << (var->data.location -
1308 VARYING_SLOT_VAR0))))) {
1309 c->inputs[loc * 4 + 0] = c->point_x;
1310 c->inputs[loc * 4 + 1] = c->point_y;
1311 } else {
1312 emit_fragment_input(c, loc, var);
1313 }
1314 } else {
1315 int var_components = glsl_get_components(var->type);
1316
1317 for (int i = 0; i < var_components; i++) {
1318 c->inputs[loc * 4 + i] =
1319 ntq_emit_vpm_read(c,
1320 &vpm_components_queued,
1321 &num_components,
1322 loc * 4 + i);
1323
1324 }
1325 c->vattr_sizes[loc] = var_components;
1326 }
1327 }
1328
1329 if (c->s->info.stage == MESA_SHADER_VERTEX) {
1330 if (c->devinfo->ver >= 40) {
1331 assert(vpm_components_queued == num_components);
1332 } else {
1333 assert(vpm_components_queued == 0);
1334 assert(num_components == 0);
1335 }
1336 }
1337 }
1338
1339 static void
1340 ntq_setup_outputs(struct v3d_compile *c)
1341 {
1342 nir_foreach_variable(var, &c->s->outputs) {
1343 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1344 unsigned loc = var->data.driver_location * 4;
1345
1346 assert(array_len == 1);
1347 (void)array_len;
1348
1349 for (int i = 0; i < glsl_get_vector_elements(var->type); i++) {
1350 add_output(c, loc + var->data.location_frac + i,
1351 var->data.location,
1352 var->data.location_frac + i);
1353 }
1354
1355 if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
1356 switch (var->data.location) {
1357 case FRAG_RESULT_COLOR:
1358 c->output_color_var[0] = var;
1359 c->output_color_var[1] = var;
1360 c->output_color_var[2] = var;
1361 c->output_color_var[3] = var;
1362 break;
1363 case FRAG_RESULT_DATA0:
1364 case FRAG_RESULT_DATA1:
1365 case FRAG_RESULT_DATA2:
1366 case FRAG_RESULT_DATA3:
1367 c->output_color_var[var->data.location -
1368 FRAG_RESULT_DATA0] = var;
1369 break;
1370 case FRAG_RESULT_DEPTH:
1371 c->output_position_index = loc;
1372 break;
1373 case FRAG_RESULT_SAMPLE_MASK:
1374 c->output_sample_mask_index = loc;
1375 break;
1376 }
1377 } else {
1378 switch (var->data.location) {
1379 case VARYING_SLOT_POS:
1380 c->output_position_index = loc;
1381 break;
1382 case VARYING_SLOT_PSIZ:
1383 c->output_point_size_index = loc;
1384 break;
1385 }
1386 }
1387 }
1388 }
1389
1390 static void
1391 ntq_setup_uniforms(struct v3d_compile *c)
1392 {
1393 nir_foreach_variable(var, &c->s->uniforms) {
1394 uint32_t vec4_count = glsl_count_attribute_slots(var->type,
1395 false);
1396 unsigned vec4_size = 4 * sizeof(float);
1397
1398 declare_uniform_range(c, var->data.driver_location * vec4_size,
1399 vec4_count * vec4_size);
1400
1401 }
1402 }
1403
1404 /**
1405 * Sets up the mapping from nir_register to struct qreg *.
1406 *
1407 * Each nir_register gets a struct qreg per 32-bit component being stored.
1408 */
1409 static void
1410 ntq_setup_registers(struct v3d_compile *c, struct exec_list *list)
1411 {
1412 foreach_list_typed(nir_register, nir_reg, node, list) {
1413 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1414 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1415 array_len *
1416 nir_reg->num_components);
1417
1418 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1419
1420 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1421 qregs[i] = vir_get_temp(c);
1422 }
1423 }
1424
1425 static void
1426 ntq_emit_load_const(struct v3d_compile *c, nir_load_const_instr *instr)
1427 {
1428 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1429 for (int i = 0; i < instr->def.num_components; i++)
1430 qregs[i] = vir_uniform_ui(c, instr->value.u32[i]);
1431
1432 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1433 }
1434
1435 static void
1436 ntq_emit_ssa_undef(struct v3d_compile *c, nir_ssa_undef_instr *instr)
1437 {
1438 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1439
1440 /* VIR needs there to be *some* value, so pick 0 (same as for
1441 * ntq_setup_registers().
1442 */
1443 for (int i = 0; i < instr->def.num_components; i++)
1444 qregs[i] = vir_uniform_ui(c, 0);
1445 }
1446
1447 static void
1448 ntq_emit_intrinsic(struct v3d_compile *c, nir_intrinsic_instr *instr)
1449 {
1450 nir_const_value *const_offset;
1451 unsigned offset;
1452
1453 switch (instr->intrinsic) {
1454 case nir_intrinsic_load_uniform:
1455 assert(instr->num_components == 1);
1456 const_offset = nir_src_as_const_value(instr->src[0]);
1457 if (const_offset) {
1458 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1459 assert(offset % 4 == 0);
1460 /* We need dwords */
1461 offset = offset / 4;
1462 ntq_store_dest(c, &instr->dest, 0,
1463 vir_uniform(c, QUNIFORM_UNIFORM,
1464 offset));
1465 } else {
1466 ntq_store_dest(c, &instr->dest, 0,
1467 indirect_uniform_load(c, instr));
1468 }
1469 break;
1470
1471 case nir_intrinsic_load_ubo:
1472 for (int i = 0; i < instr->num_components; i++) {
1473 int ubo = nir_src_as_const_value(instr->src[0])->u32[0];
1474
1475 /* Adjust for where we stored the TGSI register base. */
1476 vir_ADD_dest(c,
1477 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUA),
1478 vir_uniform(c, QUNIFORM_UBO_ADDR, 1 + ubo),
1479 vir_ADD(c,
1480 ntq_get_src(c, instr->src[1], 0),
1481 vir_uniform_ui(c, i * 4)));
1482
1483 vir_emit_thrsw(c);
1484
1485 ntq_store_dest(c, &instr->dest, i, vir_LDTMU(c));
1486 }
1487 break;
1488
1489 const_offset = nir_src_as_const_value(instr->src[0]);
1490 if (const_offset) {
1491 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1492 assert(offset % 4 == 0);
1493 /* We need dwords */
1494 offset = offset / 4;
1495 ntq_store_dest(c, &instr->dest, 0,
1496 vir_uniform(c, QUNIFORM_UNIFORM,
1497 offset));
1498 } else {
1499 ntq_store_dest(c, &instr->dest, 0,
1500 indirect_uniform_load(c, instr));
1501 }
1502 break;
1503
1504 case nir_intrinsic_load_user_clip_plane:
1505 for (int i = 0; i < instr->num_components; i++) {
1506 ntq_store_dest(c, &instr->dest, i,
1507 vir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1508 nir_intrinsic_ucp_id(instr) *
1509 4 + i));
1510 }
1511 break;
1512
1513 case nir_intrinsic_load_alpha_ref_float:
1514 ntq_store_dest(c, &instr->dest, 0,
1515 vir_uniform(c, QUNIFORM_ALPHA_REF, 0));
1516 break;
1517
1518 case nir_intrinsic_load_sample_mask_in:
1519 ntq_store_dest(c, &instr->dest, 0,
1520 vir_uniform(c, QUNIFORM_SAMPLE_MASK, 0));
1521 break;
1522
1523 case nir_intrinsic_load_front_face:
1524 /* The register contains 0 (front) or 1 (back), and we need to
1525 * turn it into a NIR bool where true means front.
1526 */
1527 ntq_store_dest(c, &instr->dest, 0,
1528 vir_ADD(c,
1529 vir_uniform_ui(c, -1),
1530 vir_REVF(c)));
1531 break;
1532
1533 case nir_intrinsic_load_instance_id:
1534 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->iid));
1535 break;
1536
1537 case nir_intrinsic_load_vertex_id:
1538 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->vid));
1539 break;
1540
1541 case nir_intrinsic_load_input:
1542 const_offset = nir_src_as_const_value(instr->src[0]);
1543 assert(const_offset && "v3d doesn't support indirect inputs");
1544 for (int i = 0; i < instr->num_components; i++) {
1545 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1546 int comp = nir_intrinsic_component(instr) + i;
1547 ntq_store_dest(c, &instr->dest, i,
1548 vir_MOV(c, c->inputs[offset * 4 + comp]));
1549 }
1550 break;
1551
1552 case nir_intrinsic_store_output:
1553 const_offset = nir_src_as_const_value(instr->src[1]);
1554 assert(const_offset && "v3d doesn't support indirect outputs");
1555 offset = ((nir_intrinsic_base(instr) +
1556 const_offset->u32[0]) * 4 +
1557 nir_intrinsic_component(instr));
1558
1559 for (int i = 0; i < instr->num_components; i++) {
1560 c->outputs[offset + i] =
1561 vir_MOV(c, ntq_get_src(c, instr->src[0], i));
1562 }
1563 c->num_outputs = MAX2(c->num_outputs,
1564 offset + instr->num_components);
1565 break;
1566
1567 case nir_intrinsic_discard:
1568 if (c->execute.file != QFILE_NULL) {
1569 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1570 vir_set_cond(vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1571 vir_uniform_ui(c, 0)),
1572 V3D_QPU_COND_IFA);
1573 } else {
1574 vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1575 vir_uniform_ui(c, 0));
1576 }
1577 break;
1578
1579 case nir_intrinsic_discard_if: {
1580 /* true (~0) if we're discarding */
1581 struct qreg cond = ntq_get_src(c, instr->src[0], 0);
1582
1583 if (c->execute.file != QFILE_NULL) {
1584 /* execute == 0 means the channel is active. Invert
1585 * the condition so that we can use zero as "executing
1586 * and discarding."
1587 */
1588 vir_PF(c, vir_OR(c, c->execute, vir_NOT(c, cond)),
1589 V3D_QPU_PF_PUSHZ);
1590 vir_set_cond(vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1591 vir_uniform_ui(c, 0)),
1592 V3D_QPU_COND_IFA);
1593 } else {
1594 vir_PF(c, cond, V3D_QPU_PF_PUSHZ);
1595 vir_set_cond(vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1596 vir_uniform_ui(c, 0)),
1597 V3D_QPU_COND_IFNA);
1598 }
1599
1600 break;
1601 }
1602
1603 default:
1604 fprintf(stderr, "Unknown intrinsic: ");
1605 nir_print_instr(&instr->instr, stderr);
1606 fprintf(stderr, "\n");
1607 break;
1608 }
1609 }
1610
1611 /* Clears (activates) the execute flags for any channels whose jump target
1612 * matches this block.
1613 */
1614 static void
1615 ntq_activate_execute_for_block(struct v3d_compile *c)
1616 {
1617 vir_PF(c, vir_XOR(c, c->execute, vir_uniform_ui(c, c->cur_block->index)),
1618 V3D_QPU_PF_PUSHZ);
1619
1620 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
1621 }
1622
1623 static void
1624 ntq_emit_if(struct v3d_compile *c, nir_if *if_stmt)
1625 {
1626 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
1627 bool empty_else_block =
1628 (nir_else_block == nir_if_last_else_block(if_stmt) &&
1629 exec_list_is_empty(&nir_else_block->instr_list));
1630
1631 struct qblock *then_block = vir_new_block(c);
1632 struct qblock *after_block = vir_new_block(c);
1633 struct qblock *else_block;
1634 if (empty_else_block)
1635 else_block = after_block;
1636 else
1637 else_block = vir_new_block(c);
1638
1639 bool was_top_level = false;
1640 if (c->execute.file == QFILE_NULL) {
1641 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
1642 was_top_level = true;
1643 }
1644
1645 /* Set A for executing (execute == 0) and jumping (if->condition ==
1646 * 0) channels, and then update execute flags for those to point to
1647 * the ELSE block.
1648 */
1649 vir_PF(c, vir_OR(c,
1650 c->execute,
1651 ntq_get_src(c, if_stmt->condition, 0)),
1652 V3D_QPU_PF_PUSHZ);
1653 vir_MOV_cond(c, V3D_QPU_COND_IFA,
1654 c->execute,
1655 vir_uniform_ui(c, else_block->index));
1656
1657 /* Jump to ELSE if nothing is active for THEN, otherwise fall
1658 * through.
1659 */
1660 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1661 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLNA);
1662 vir_link_blocks(c->cur_block, else_block);
1663 vir_link_blocks(c->cur_block, then_block);
1664
1665 /* Process the THEN block. */
1666 vir_set_emit_block(c, then_block);
1667 ntq_emit_cf_list(c, &if_stmt->then_list);
1668
1669 if (!empty_else_block) {
1670 /* Handle the end of the THEN block. First, all currently
1671 * active channels update their execute flags to point to
1672 * ENDIF
1673 */
1674 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1675 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
1676 vir_uniform_ui(c, after_block->index));
1677
1678 /* If everything points at ENDIF, then jump there immediately. */
1679 vir_PF(c, vir_XOR(c, c->execute,
1680 vir_uniform_ui(c, after_block->index)),
1681 V3D_QPU_PF_PUSHZ);
1682 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLA);
1683 vir_link_blocks(c->cur_block, after_block);
1684 vir_link_blocks(c->cur_block, else_block);
1685
1686 vir_set_emit_block(c, else_block);
1687 ntq_activate_execute_for_block(c);
1688 ntq_emit_cf_list(c, &if_stmt->else_list);
1689 }
1690
1691 vir_link_blocks(c->cur_block, after_block);
1692
1693 vir_set_emit_block(c, after_block);
1694 if (was_top_level)
1695 c->execute = c->undef;
1696 else
1697 ntq_activate_execute_for_block(c);
1698 }
1699
1700 static void
1701 ntq_emit_jump(struct v3d_compile *c, nir_jump_instr *jump)
1702 {
1703 switch (jump->type) {
1704 case nir_jump_break:
1705 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1706 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
1707 vir_uniform_ui(c, c->loop_break_block->index));
1708 break;
1709
1710 case nir_jump_continue:
1711 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1712 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
1713 vir_uniform_ui(c, c->loop_cont_block->index));
1714 break;
1715
1716 case nir_jump_return:
1717 unreachable("All returns shouold be lowered\n");
1718 }
1719 }
1720
1721 static void
1722 ntq_emit_instr(struct v3d_compile *c, nir_instr *instr)
1723 {
1724 switch (instr->type) {
1725 case nir_instr_type_alu:
1726 ntq_emit_alu(c, nir_instr_as_alu(instr));
1727 break;
1728
1729 case nir_instr_type_intrinsic:
1730 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
1731 break;
1732
1733 case nir_instr_type_load_const:
1734 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
1735 break;
1736
1737 case nir_instr_type_ssa_undef:
1738 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
1739 break;
1740
1741 case nir_instr_type_tex:
1742 ntq_emit_tex(c, nir_instr_as_tex(instr));
1743 break;
1744
1745 case nir_instr_type_jump:
1746 ntq_emit_jump(c, nir_instr_as_jump(instr));
1747 break;
1748
1749 default:
1750 fprintf(stderr, "Unknown NIR instr type: ");
1751 nir_print_instr(instr, stderr);
1752 fprintf(stderr, "\n");
1753 abort();
1754 }
1755 }
1756
1757 static void
1758 ntq_emit_block(struct v3d_compile *c, nir_block *block)
1759 {
1760 nir_foreach_instr(instr, block) {
1761 ntq_emit_instr(c, instr);
1762 }
1763 }
1764
1765 static void ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
1766
1767 static void
1768 ntq_emit_loop(struct v3d_compile *c, nir_loop *loop)
1769 {
1770 bool was_top_level = false;
1771 if (c->execute.file == QFILE_NULL) {
1772 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
1773 was_top_level = true;
1774 }
1775
1776 struct qblock *save_loop_cont_block = c->loop_cont_block;
1777 struct qblock *save_loop_break_block = c->loop_break_block;
1778
1779 c->loop_cont_block = vir_new_block(c);
1780 c->loop_break_block = vir_new_block(c);
1781
1782 vir_link_blocks(c->cur_block, c->loop_cont_block);
1783 vir_set_emit_block(c, c->loop_cont_block);
1784 ntq_activate_execute_for_block(c);
1785
1786 ntq_emit_cf_list(c, &loop->body);
1787
1788 /* Re-enable any previous continues now, so our ANYA check below
1789 * works.
1790 *
1791 * XXX: Use the .ORZ flags update, instead.
1792 */
1793 vir_PF(c, vir_XOR(c,
1794 c->execute,
1795 vir_uniform_ui(c, c->loop_cont_block->index)),
1796 V3D_QPU_PF_PUSHZ);
1797 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
1798
1799 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1800
1801 struct qinst *branch = vir_BRANCH(c, V3D_QPU_BRANCH_COND_ANYA);
1802 /* Pixels that were not dispatched or have been discarded should not
1803 * contribute to looping again.
1804 */
1805 branch->qpu.branch.msfign = V3D_QPU_MSFIGN_P;
1806 vir_link_blocks(c->cur_block, c->loop_cont_block);
1807 vir_link_blocks(c->cur_block, c->loop_break_block);
1808
1809 vir_set_emit_block(c, c->loop_break_block);
1810 if (was_top_level)
1811 c->execute = c->undef;
1812 else
1813 ntq_activate_execute_for_block(c);
1814
1815 c->loop_break_block = save_loop_break_block;
1816 c->loop_cont_block = save_loop_cont_block;
1817 }
1818
1819 static void
1820 ntq_emit_function(struct v3d_compile *c, nir_function_impl *func)
1821 {
1822 fprintf(stderr, "FUNCTIONS not handled.\n");
1823 abort();
1824 }
1825
1826 static void
1827 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list)
1828 {
1829 foreach_list_typed(nir_cf_node, node, node, list) {
1830 switch (node->type) {
1831 case nir_cf_node_block:
1832 ntq_emit_block(c, nir_cf_node_as_block(node));
1833 break;
1834
1835 case nir_cf_node_if:
1836 ntq_emit_if(c, nir_cf_node_as_if(node));
1837 break;
1838
1839 case nir_cf_node_loop:
1840 ntq_emit_loop(c, nir_cf_node_as_loop(node));
1841 break;
1842
1843 case nir_cf_node_function:
1844 ntq_emit_function(c, nir_cf_node_as_function(node));
1845 break;
1846
1847 default:
1848 fprintf(stderr, "Unknown NIR node type\n");
1849 abort();
1850 }
1851 }
1852 }
1853
1854 static void
1855 ntq_emit_impl(struct v3d_compile *c, nir_function_impl *impl)
1856 {
1857 ntq_setup_registers(c, &impl->registers);
1858 ntq_emit_cf_list(c, &impl->body);
1859 }
1860
1861 static void
1862 nir_to_vir(struct v3d_compile *c)
1863 {
1864 if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
1865 c->payload_w = vir_MOV(c, vir_reg(QFILE_REG, 0));
1866 c->payload_w_centroid = vir_MOV(c, vir_reg(QFILE_REG, 1));
1867 c->payload_z = vir_MOV(c, vir_reg(QFILE_REG, 2));
1868
1869 if (c->fs_key->is_points) {
1870 c->point_x = emit_fragment_varying(c, NULL, 0);
1871 c->point_y = emit_fragment_varying(c, NULL, 0);
1872 } else if (c->fs_key->is_lines) {
1873 c->line_x = emit_fragment_varying(c, NULL, 0);
1874 }
1875 }
1876
1877 ntq_setup_inputs(c);
1878 ntq_setup_outputs(c);
1879 ntq_setup_uniforms(c);
1880 ntq_setup_registers(c, &c->s->registers);
1881
1882 /* Find the main function and emit the body. */
1883 nir_foreach_function(function, c->s) {
1884 assert(strcmp(function->name, "main") == 0);
1885 assert(function->impl);
1886 ntq_emit_impl(c, function->impl);
1887 }
1888 }
1889
1890 const nir_shader_compiler_options v3d_nir_options = {
1891 .lower_all_io_to_temps = true,
1892 .lower_extract_byte = true,
1893 .lower_extract_word = true,
1894 .lower_bitfield_insert = true,
1895 .lower_bitfield_extract = true,
1896 .lower_pack_unorm_2x16 = true,
1897 .lower_pack_snorm_2x16 = true,
1898 .lower_pack_unorm_4x8 = true,
1899 .lower_pack_snorm_4x8 = true,
1900 .lower_unpack_unorm_4x8 = true,
1901 .lower_unpack_snorm_4x8 = true,
1902 .lower_fdiv = true,
1903 .lower_ffma = true,
1904 .lower_flrp32 = true,
1905 .lower_fpow = true,
1906 .lower_fsat = true,
1907 .lower_fsqrt = true,
1908 .lower_ldexp = true,
1909 .native_integers = true,
1910 };
1911
1912
1913 #if 0
1914 static int
1915 count_nir_instrs(nir_shader *nir)
1916 {
1917 int count = 0;
1918 nir_foreach_function(function, nir) {
1919 if (!function->impl)
1920 continue;
1921 nir_foreach_block(block, function->impl) {
1922 nir_foreach_instr(instr, block)
1923 count++;
1924 }
1925 }
1926 return count;
1927 }
1928 #endif
1929
1930 /**
1931 * When demoting a shader down to single-threaded, removes the THRSW
1932 * instructions (one will still be inserted at v3d_vir_to_qpu() for the
1933 * program end).
1934 */
1935 static void
1936 vir_remove_thrsw(struct v3d_compile *c)
1937 {
1938 vir_for_each_block(block, c) {
1939 vir_for_each_inst_safe(inst, block) {
1940 if (inst->qpu.sig.thrsw)
1941 vir_remove_instruction(c, inst);
1942 }
1943 }
1944
1945 c->last_thrsw = NULL;
1946 }
1947
1948 void
1949 vir_emit_last_thrsw(struct v3d_compile *c)
1950 {
1951 /* On V3D before 4.1, we need a TMU op to be outstanding when thread
1952 * switching, so disable threads if we didn't do any TMU ops (each of
1953 * which would have emitted a THRSW).
1954 */
1955 if (!c->last_thrsw_at_top_level && c->devinfo->ver < 41) {
1956 c->threads = 1;
1957 if (c->last_thrsw)
1958 vir_remove_thrsw(c);
1959 return;
1960 }
1961
1962 /* If we're threaded and the last THRSW was in conditional code, then
1963 * we need to emit another one so that we can flag it as the last
1964 * thrsw.
1965 */
1966 if (c->last_thrsw && !c->last_thrsw_at_top_level) {
1967 assert(c->devinfo->ver >= 41);
1968 vir_emit_thrsw(c);
1969 }
1970
1971 /* If we're threaded, then we need to mark the last THRSW instruction
1972 * so we can emit a pair of them at QPU emit time.
1973 *
1974 * For V3D 4.x, we can spawn the non-fragment shaders already in the
1975 * post-last-THRSW state, so we can skip this.
1976 */
1977 if (!c->last_thrsw && c->s->info.stage == MESA_SHADER_FRAGMENT) {
1978 assert(c->devinfo->ver >= 41);
1979 vir_emit_thrsw(c);
1980 }
1981
1982 if (c->last_thrsw)
1983 c->last_thrsw->is_last_thrsw = true;
1984 }
1985
1986 void
1987 v3d_nir_to_vir(struct v3d_compile *c)
1988 {
1989 if (V3D_DEBUG & (V3D_DEBUG_NIR |
1990 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
1991 fprintf(stderr, "%s prog %d/%d NIR:\n",
1992 vir_get_stage_name(c),
1993 c->program_id, c->variant_id);
1994 nir_print_shader(c->s, stderr);
1995 }
1996
1997 nir_to_vir(c);
1998
1999 /* Emit the last THRSW before STVPM and TLB writes. */
2000 vir_emit_last_thrsw(c);
2001
2002 switch (c->s->info.stage) {
2003 case MESA_SHADER_FRAGMENT:
2004 emit_frag_end(c);
2005 break;
2006 case MESA_SHADER_VERTEX:
2007 emit_vert_end(c);
2008 break;
2009 default:
2010 unreachable("bad stage");
2011 }
2012
2013 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2014 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2015 fprintf(stderr, "%s prog %d/%d pre-opt VIR:\n",
2016 vir_get_stage_name(c),
2017 c->program_id, c->variant_id);
2018 vir_dump(c);
2019 fprintf(stderr, "\n");
2020 }
2021
2022 vir_optimize(c);
2023 vir_lower_uniforms(c);
2024
2025 /* XXX: vir_schedule_instructions(c); */
2026
2027 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2028 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2029 fprintf(stderr, "%s prog %d/%d VIR:\n",
2030 vir_get_stage_name(c),
2031 c->program_id, c->variant_id);
2032 vir_dump(c);
2033 fprintf(stderr, "\n");
2034 }
2035
2036 /* Attempt to allocate registers for the temporaries. If we fail,
2037 * reduce thread count and try again.
2038 */
2039 int min_threads = (c->devinfo->ver >= 41) ? 2 : 1;
2040 struct qpu_reg *temp_registers;
2041 while (true) {
2042 bool spilled;
2043 temp_registers = v3d_register_allocate(c, &spilled);
2044 if (spilled)
2045 continue;
2046
2047 if (temp_registers)
2048 break;
2049
2050 if (c->threads == min_threads) {
2051 fprintf(stderr, "Failed to register allocate at %d threads:\n",
2052 c->threads);
2053 vir_dump(c);
2054 c->failed = true;
2055 return;
2056 }
2057
2058 c->threads /= 2;
2059
2060 if (c->threads == 1)
2061 vir_remove_thrsw(c);
2062 }
2063
2064 v3d_vir_to_qpu(c, temp_registers);
2065 }