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v3d: Add a helper function for getting a nop register.
[mesa.git] / src / broadcom / compiler / nir_to_vir.c
1 /*
2 * Copyright © 2016 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <inttypes.h>
25 #include "util/u_format.h"
26 #include "util/u_math.h"
27 #include "util/u_memory.h"
28 #include "util/ralloc.h"
29 #include "util/hash_table.h"
30 #include "compiler/nir/nir.h"
31 #include "compiler/nir/nir_builder.h"
32 #include "common/v3d_device_info.h"
33 #include "v3d_compiler.h"
34
35 #define GENERAL_TMU_LOOKUP_PER_QUAD (0 << 7)
36 #define GENERAL_TMU_LOOKUP_PER_PIXEL (1 << 7)
37 #define GENERAL_TMU_READ_OP_PREFETCH (0 << 3)
38 #define GENERAL_TMU_READ_OP_CACHE_CLEAR (1 << 3)
39 #define GENERAL_TMU_READ_OP_CACHE_FLUSH (3 << 3)
40 #define GENERAL_TMU_READ_OP_CACHE_CLEAN (3 << 3)
41 #define GENERAL_TMU_READ_OP_CACHE_L1T_CLEAR (4 << 3)
42 #define GENERAL_TMU_READ_OP_CACHE_L1T_FLUSH_AGGREGATION (5 << 3)
43 #define GENERAL_TMU_READ_OP_ATOMIC_INC (8 << 3)
44 #define GENERAL_TMU_READ_OP_ATOMIC_DEC (9 << 3)
45 #define GENERAL_TMU_READ_OP_ATOMIC_NOT (10 << 3)
46 #define GENERAL_TMU_READ_OP_READ (15 << 3)
47 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_I (0 << 0)
48 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_I (1 << 0)
49 #define GENERAL_TMU_LOOKUP_TYPE_VEC2 (2 << 0)
50 #define GENERAL_TMU_LOOKUP_TYPE_VEC3 (3 << 0)
51 #define GENERAL_TMU_LOOKUP_TYPE_VEC4 (4 << 0)
52 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_UI (5 << 0)
53 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_UI (6 << 0)
54 #define GENERAL_TMU_LOOKUP_TYPE_32BIT_UI (7 << 0)
55
56 #define GENERAL_TMU_WRITE_OP_ATOMIC_ADD_WRAP (0 << 3)
57 #define GENERAL_TMU_WRITE_OP_ATOMIC_SUB_WRAP (1 << 3)
58 #define GENERAL_TMU_WRITE_OP_ATOMIC_XCHG (2 << 3)
59 #define GENERAL_TMU_WRITE_OP_ATOMIC_CMPXCHG (3 << 3)
60 #define GENERAL_TMU_WRITE_OP_ATOMIC_UMIN (4 << 3)
61 #define GENERAL_TMU_WRITE_OP_ATOMIC_UMAX (5 << 3)
62 #define GENERAL_TMU_WRITE_OP_ATOMIC_SMIN (6 << 3)
63 #define GENERAL_TMU_WRITE_OP_ATOMIC_SMAX (7 << 3)
64 #define GENERAL_TMU_WRITE_OP_ATOMIC_AND (8 << 3)
65 #define GENERAL_TMU_WRITE_OP_ATOMIC_OR (9 << 3)
66 #define GENERAL_TMU_WRITE_OP_ATOMIC_XOR (10 << 3)
67 #define GENERAL_TMU_WRITE_OP_WRITE (15 << 3)
68
69 #define V3D_TSY_SET_QUORUM 0
70 #define V3D_TSY_INC_WAITERS 1
71 #define V3D_TSY_DEC_WAITERS 2
72 #define V3D_TSY_INC_QUORUM 3
73 #define V3D_TSY_DEC_QUORUM 4
74 #define V3D_TSY_FREE_ALL 5
75 #define V3D_TSY_RELEASE 6
76 #define V3D_TSY_ACQUIRE 7
77 #define V3D_TSY_WAIT 8
78 #define V3D_TSY_WAIT_INC 9
79 #define V3D_TSY_WAIT_CHECK 10
80 #define V3D_TSY_WAIT_INC_CHECK 11
81 #define V3D_TSY_WAIT_CV 12
82 #define V3D_TSY_INC_SEMAPHORE 13
83 #define V3D_TSY_DEC_SEMAPHORE 14
84 #define V3D_TSY_SET_QUORUM_FREE_ALL 15
85
86 static void
87 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
88
89 static void
90 resize_qreg_array(struct v3d_compile *c,
91 struct qreg **regs,
92 uint32_t *size,
93 uint32_t decl_size)
94 {
95 if (*size >= decl_size)
96 return;
97
98 uint32_t old_size = *size;
99 *size = MAX2(*size * 2, decl_size);
100 *regs = reralloc(c, *regs, struct qreg, *size);
101 if (!*regs) {
102 fprintf(stderr, "Malloc failure\n");
103 abort();
104 }
105
106 for (uint32_t i = old_size; i < *size; i++)
107 (*regs)[i] = c->undef;
108 }
109
110 void
111 vir_emit_thrsw(struct v3d_compile *c)
112 {
113 if (c->threads == 1)
114 return;
115
116 /* Always thread switch after each texture operation for now.
117 *
118 * We could do better by batching a bunch of texture fetches up and
119 * then doing one thread switch and collecting all their results
120 * afterward.
121 */
122 c->last_thrsw = vir_NOP(c);
123 c->last_thrsw->qpu.sig.thrsw = true;
124 c->last_thrsw_at_top_level = (c->execute.file == QFILE_NULL);
125 }
126
127 static uint32_t
128 v3d_general_tmu_op(nir_intrinsic_instr *instr)
129 {
130 switch (instr->intrinsic) {
131 case nir_intrinsic_load_ssbo:
132 case nir_intrinsic_load_ubo:
133 case nir_intrinsic_load_uniform:
134 case nir_intrinsic_load_shared:
135 return GENERAL_TMU_READ_OP_READ;
136 case nir_intrinsic_store_ssbo:
137 case nir_intrinsic_store_shared:
138 return GENERAL_TMU_WRITE_OP_WRITE;
139 case nir_intrinsic_ssbo_atomic_add:
140 case nir_intrinsic_shared_atomic_add:
141 return GENERAL_TMU_WRITE_OP_ATOMIC_ADD_WRAP;
142 case nir_intrinsic_ssbo_atomic_imin:
143 case nir_intrinsic_shared_atomic_imin:
144 return GENERAL_TMU_WRITE_OP_ATOMIC_SMIN;
145 case nir_intrinsic_ssbo_atomic_umin:
146 case nir_intrinsic_shared_atomic_umin:
147 return GENERAL_TMU_WRITE_OP_ATOMIC_UMIN;
148 case nir_intrinsic_ssbo_atomic_imax:
149 case nir_intrinsic_shared_atomic_imax:
150 return GENERAL_TMU_WRITE_OP_ATOMIC_SMAX;
151 case nir_intrinsic_ssbo_atomic_umax:
152 case nir_intrinsic_shared_atomic_umax:
153 return GENERAL_TMU_WRITE_OP_ATOMIC_UMAX;
154 case nir_intrinsic_ssbo_atomic_and:
155 case nir_intrinsic_shared_atomic_and:
156 return GENERAL_TMU_WRITE_OP_ATOMIC_AND;
157 case nir_intrinsic_ssbo_atomic_or:
158 case nir_intrinsic_shared_atomic_or:
159 return GENERAL_TMU_WRITE_OP_ATOMIC_OR;
160 case nir_intrinsic_ssbo_atomic_xor:
161 case nir_intrinsic_shared_atomic_xor:
162 return GENERAL_TMU_WRITE_OP_ATOMIC_XOR;
163 case nir_intrinsic_ssbo_atomic_exchange:
164 case nir_intrinsic_shared_atomic_exchange:
165 return GENERAL_TMU_WRITE_OP_ATOMIC_XCHG;
166 case nir_intrinsic_ssbo_atomic_comp_swap:
167 case nir_intrinsic_shared_atomic_comp_swap:
168 return GENERAL_TMU_WRITE_OP_ATOMIC_CMPXCHG;
169 default:
170 unreachable("unknown intrinsic op");
171 }
172 }
173
174 /**
175 * Implements indirect uniform loads and SSBO accesses through the TMU general
176 * memory access interface.
177 */
178 static void
179 ntq_emit_tmu_general(struct v3d_compile *c, nir_intrinsic_instr *instr,
180 bool is_shared)
181 {
182 /* XXX perf: We should turn add/sub of 1 to inc/dec. Perhaps NIR
183 * wants to have support for inc/dec?
184 */
185
186 uint32_t tmu_op = v3d_general_tmu_op(instr);
187 bool is_store = (instr->intrinsic == nir_intrinsic_store_ssbo ||
188 instr->intrinsic == nir_intrinsic_store_shared);
189 bool has_index = !is_shared;
190
191 int offset_src;
192 int tmu_writes = 1; /* address */
193 if (instr->intrinsic == nir_intrinsic_load_uniform) {
194 offset_src = 0;
195 } else if (instr->intrinsic == nir_intrinsic_load_ssbo ||
196 instr->intrinsic == nir_intrinsic_load_ubo ||
197 instr->intrinsic == nir_intrinsic_load_shared) {
198 offset_src = 0 + has_index;
199 } else if (is_store) {
200 offset_src = 1 + has_index;
201 for (int i = 0; i < instr->num_components; i++) {
202 vir_MOV_dest(c,
203 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD),
204 ntq_get_src(c, instr->src[0], i));
205 tmu_writes++;
206 }
207 } else {
208 offset_src = 0 + has_index;
209 vir_MOV_dest(c,
210 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD),
211 ntq_get_src(c, instr->src[1 + has_index], 0));
212 tmu_writes++;
213 if (tmu_op == GENERAL_TMU_WRITE_OP_ATOMIC_CMPXCHG) {
214 vir_MOV_dest(c,
215 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD),
216 ntq_get_src(c, instr->src[2 + has_index],
217 0));
218 tmu_writes++;
219 }
220 }
221
222 /* Make sure we won't exceed the 16-entry TMU fifo if each thread is
223 * storing at the same time.
224 */
225 while (tmu_writes > 16 / c->threads)
226 c->threads /= 2;
227
228 struct qreg offset;
229 if (instr->intrinsic == nir_intrinsic_load_uniform) {
230 offset = vir_uniform(c, QUNIFORM_UBO_ADDR, 0);
231
232 /* Find what variable in the default uniform block this
233 * uniform load is coming from.
234 */
235 uint32_t base = nir_intrinsic_base(instr);
236 int i;
237 struct v3d_ubo_range *range = NULL;
238 for (i = 0; i < c->num_ubo_ranges; i++) {
239 range = &c->ubo_ranges[i];
240 if (base >= range->src_offset &&
241 base < range->src_offset + range->size) {
242 break;
243 }
244 }
245 /* The driver-location-based offset always has to be within a
246 * declared uniform range.
247 */
248 assert(i != c->num_ubo_ranges);
249 if (!c->ubo_range_used[i]) {
250 c->ubo_range_used[i] = true;
251 range->dst_offset = c->next_ubo_dst_offset;
252 c->next_ubo_dst_offset += range->size;
253 }
254
255 base = base - range->src_offset + range->dst_offset;
256
257 if (base != 0)
258 offset = vir_ADD(c, offset, vir_uniform_ui(c, base));
259 } else if (instr->intrinsic == nir_intrinsic_load_ubo) {
260 /* Note that QUNIFORM_UBO_ADDR takes a UBO index shifted up by
261 * 1 (0 is gallium's constant buffer 0).
262 */
263 offset = vir_uniform(c, QUNIFORM_UBO_ADDR,
264 nir_src_as_uint(instr->src[0]) + 1);
265 } else if (is_shared) {
266 /* Shared variables have no buffer index, and all start from a
267 * common base that we set up at the start of dispatch
268 */
269 offset = c->cs_shared_offset;
270 } else {
271 offset = vir_uniform(c, QUNIFORM_SSBO_OFFSET,
272 nir_src_as_uint(instr->src[is_store ?
273 1 : 0]));
274 }
275
276 uint32_t config = (0xffffff00 |
277 tmu_op |
278 GENERAL_TMU_LOOKUP_PER_PIXEL);
279 if (instr->num_components == 1) {
280 config |= GENERAL_TMU_LOOKUP_TYPE_32BIT_UI;
281 } else {
282 config |= (GENERAL_TMU_LOOKUP_TYPE_VEC2 +
283 instr->num_components - 2);
284 }
285
286 if (c->execute.file != QFILE_NULL)
287 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
288
289 struct qreg dest;
290 if (config == ~0)
291 dest = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUA);
292 else
293 dest = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUAU);
294
295 struct qinst *tmu;
296 if (nir_src_is_const(instr->src[offset_src]) &&
297 nir_src_as_uint(instr->src[offset_src]) == 0) {
298 tmu = vir_MOV_dest(c, dest, offset);
299 } else {
300 tmu = vir_ADD_dest(c, dest,
301 offset,
302 ntq_get_src(c, instr->src[offset_src], 0));
303 }
304
305 if (config != ~0) {
306 tmu->src[vir_get_implicit_uniform_src(tmu)] =
307 vir_uniform_ui(c, config);
308 }
309
310 if (c->execute.file != QFILE_NULL)
311 vir_set_cond(tmu, V3D_QPU_COND_IFA);
312
313 vir_emit_thrsw(c);
314
315 /* Read the result, or wait for the TMU op to complete. */
316 for (int i = 0; i < nir_intrinsic_dest_components(instr); i++)
317 ntq_store_dest(c, &instr->dest, i, vir_MOV(c, vir_LDTMU(c)));
318
319 if (nir_intrinsic_dest_components(instr) == 0)
320 vir_TMUWT(c);
321 }
322
323 static struct qreg *
324 ntq_init_ssa_def(struct v3d_compile *c, nir_ssa_def *def)
325 {
326 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
327 def->num_components);
328 _mesa_hash_table_insert(c->def_ht, def, qregs);
329 return qregs;
330 }
331
332 /**
333 * This function is responsible for getting VIR results into the associated
334 * storage for a NIR instruction.
335 *
336 * If it's a NIR SSA def, then we just set the associated hash table entry to
337 * the new result.
338 *
339 * If it's a NIR reg, then we need to update the existing qreg assigned to the
340 * NIR destination with the incoming value. To do that without introducing
341 * new MOVs, we require that the incoming qreg either be a uniform, or be
342 * SSA-defined by the previous VIR instruction in the block and rewritable by
343 * this function. That lets us sneak ahead and insert the SF flag beforehand
344 * (knowing that the previous instruction doesn't depend on flags) and rewrite
345 * its destination to be the NIR reg's destination
346 */
347 void
348 ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int chan,
349 struct qreg result)
350 {
351 struct qinst *last_inst = NULL;
352 if (!list_empty(&c->cur_block->instructions))
353 last_inst = (struct qinst *)c->cur_block->instructions.prev;
354
355 assert(result.file == QFILE_UNIF ||
356 (result.file == QFILE_TEMP &&
357 last_inst && last_inst == c->defs[result.index]));
358
359 if (dest->is_ssa) {
360 assert(chan < dest->ssa.num_components);
361
362 struct qreg *qregs;
363 struct hash_entry *entry =
364 _mesa_hash_table_search(c->def_ht, &dest->ssa);
365
366 if (entry)
367 qregs = entry->data;
368 else
369 qregs = ntq_init_ssa_def(c, &dest->ssa);
370
371 qregs[chan] = result;
372 } else {
373 nir_register *reg = dest->reg.reg;
374 assert(dest->reg.base_offset == 0);
375 assert(reg->num_array_elems == 0);
376 struct hash_entry *entry =
377 _mesa_hash_table_search(c->def_ht, reg);
378 struct qreg *qregs = entry->data;
379
380 /* Insert a MOV if the source wasn't an SSA def in the
381 * previous instruction.
382 */
383 if (result.file == QFILE_UNIF) {
384 result = vir_MOV(c, result);
385 last_inst = c->defs[result.index];
386 }
387
388 /* We know they're both temps, so just rewrite index. */
389 c->defs[last_inst->dst.index] = NULL;
390 last_inst->dst.index = qregs[chan].index;
391
392 /* If we're in control flow, then make this update of the reg
393 * conditional on the execution mask.
394 */
395 if (c->execute.file != QFILE_NULL) {
396 last_inst->dst.index = qregs[chan].index;
397
398 /* Set the flags to the current exec mask.
399 */
400 c->cursor = vir_before_inst(last_inst);
401 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
402 c->cursor = vir_after_inst(last_inst);
403
404 vir_set_cond(last_inst, V3D_QPU_COND_IFA);
405 last_inst->cond_is_exec_mask = true;
406 }
407 }
408 }
409
410 struct qreg
411 ntq_get_src(struct v3d_compile *c, nir_src src, int i)
412 {
413 struct hash_entry *entry;
414 if (src.is_ssa) {
415 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
416 assert(i < src.ssa->num_components);
417 } else {
418 nir_register *reg = src.reg.reg;
419 entry = _mesa_hash_table_search(c->def_ht, reg);
420 assert(reg->num_array_elems == 0);
421 assert(src.reg.base_offset == 0);
422 assert(i < reg->num_components);
423 }
424
425 struct qreg *qregs = entry->data;
426 return qregs[i];
427 }
428
429 static struct qreg
430 ntq_get_alu_src(struct v3d_compile *c, nir_alu_instr *instr,
431 unsigned src)
432 {
433 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
434 unsigned chan = ffs(instr->dest.write_mask) - 1;
435 struct qreg r = ntq_get_src(c, instr->src[src].src,
436 instr->src[src].swizzle[chan]);
437
438 assert(!instr->src[src].abs);
439 assert(!instr->src[src].negate);
440
441 return r;
442 };
443
444 static struct qreg
445 ntq_minify(struct v3d_compile *c, struct qreg size, struct qreg level)
446 {
447 return vir_MAX(c, vir_SHR(c, size, level), vir_uniform_ui(c, 1));
448 }
449
450 static void
451 ntq_emit_txs(struct v3d_compile *c, nir_tex_instr *instr)
452 {
453 unsigned unit = instr->texture_index;
454 int lod_index = nir_tex_instr_src_index(instr, nir_tex_src_lod);
455 int dest_size = nir_tex_instr_dest_size(instr);
456
457 struct qreg lod = c->undef;
458 if (lod_index != -1)
459 lod = ntq_get_src(c, instr->src[lod_index].src, 0);
460
461 for (int i = 0; i < dest_size; i++) {
462 assert(i < 3);
463 enum quniform_contents contents;
464
465 if (instr->is_array && i == dest_size - 1)
466 contents = QUNIFORM_TEXTURE_ARRAY_SIZE;
467 else
468 contents = QUNIFORM_TEXTURE_WIDTH + i;
469
470 struct qreg size = vir_uniform(c, contents, unit);
471
472 switch (instr->sampler_dim) {
473 case GLSL_SAMPLER_DIM_1D:
474 case GLSL_SAMPLER_DIM_2D:
475 case GLSL_SAMPLER_DIM_MS:
476 case GLSL_SAMPLER_DIM_3D:
477 case GLSL_SAMPLER_DIM_CUBE:
478 /* Don't minify the array size. */
479 if (!(instr->is_array && i == dest_size - 1)) {
480 size = ntq_minify(c, size, lod);
481 }
482 break;
483
484 case GLSL_SAMPLER_DIM_RECT:
485 /* There's no LOD field for rects */
486 break;
487
488 default:
489 unreachable("Bad sampler type");
490 }
491
492 ntq_store_dest(c, &instr->dest, i, size);
493 }
494 }
495
496 static void
497 ntq_emit_tex(struct v3d_compile *c, nir_tex_instr *instr)
498 {
499 unsigned unit = instr->texture_index;
500
501 /* Since each texture sampling op requires uploading uniforms to
502 * reference the texture, there's no HW support for texture size and
503 * you just upload uniforms containing the size.
504 */
505 switch (instr->op) {
506 case nir_texop_query_levels:
507 ntq_store_dest(c, &instr->dest, 0,
508 vir_uniform(c, QUNIFORM_TEXTURE_LEVELS, unit));
509 return;
510 case nir_texop_txs:
511 ntq_emit_txs(c, instr);
512 return;
513 default:
514 break;
515 }
516
517 if (c->devinfo->ver >= 40)
518 v3d40_vir_emit_tex(c, instr);
519 else
520 v3d33_vir_emit_tex(c, instr);
521 }
522
523 static struct qreg
524 ntq_fsincos(struct v3d_compile *c, struct qreg src, bool is_cos)
525 {
526 struct qreg input = vir_FMUL(c, src, vir_uniform_f(c, 1.0f / M_PI));
527 if (is_cos)
528 input = vir_FADD(c, input, vir_uniform_f(c, 0.5));
529
530 struct qreg periods = vir_FROUND(c, input);
531 struct qreg sin_output = vir_SIN(c, vir_FSUB(c, input, periods));
532 return vir_XOR(c, sin_output, vir_SHL(c,
533 vir_FTOIN(c, periods),
534 vir_uniform_ui(c, -1)));
535 }
536
537 static struct qreg
538 ntq_fsign(struct v3d_compile *c, struct qreg src)
539 {
540 struct qreg t = vir_get_temp(c);
541
542 vir_MOV_dest(c, t, vir_uniform_f(c, 0.0));
543 vir_PF(c, vir_FMOV(c, src), V3D_QPU_PF_PUSHZ);
544 vir_MOV_cond(c, V3D_QPU_COND_IFNA, t, vir_uniform_f(c, 1.0));
545 vir_PF(c, vir_FMOV(c, src), V3D_QPU_PF_PUSHN);
546 vir_MOV_cond(c, V3D_QPU_COND_IFA, t, vir_uniform_f(c, -1.0));
547 return vir_MOV(c, t);
548 }
549
550 static void
551 emit_fragcoord_input(struct v3d_compile *c, int attr)
552 {
553 c->inputs[attr * 4 + 0] = vir_FXCD(c);
554 c->inputs[attr * 4 + 1] = vir_FYCD(c);
555 c->inputs[attr * 4 + 2] = c->payload_z;
556 c->inputs[attr * 4 + 3] = vir_RECIP(c, c->payload_w);
557 }
558
559 static struct qreg
560 emit_fragment_varying(struct v3d_compile *c, nir_variable *var,
561 uint8_t swizzle, int array_index)
562 {
563 struct qreg r3 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R3);
564 struct qreg r5 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R5);
565
566 struct qreg vary;
567 if (c->devinfo->ver >= 41) {
568 struct qinst *ldvary = vir_add_inst(V3D_QPU_A_NOP, c->undef,
569 c->undef, c->undef);
570 ldvary->qpu.sig.ldvary = true;
571 vary = vir_emit_def(c, ldvary);
572 } else {
573 vir_NOP(c)->qpu.sig.ldvary = true;
574 vary = r3;
575 }
576
577 /* For gl_PointCoord input or distance along a line, we'll be called
578 * with no nir_variable, and we don't count toward VPM size so we
579 * don't track an input slot.
580 */
581 if (!var) {
582 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
583 }
584
585 int i = c->num_inputs++;
586 c->input_slots[i] =
587 v3d_slot_from_slot_and_component(var->data.location +
588 array_index, swizzle);
589
590 switch (var->data.interpolation) {
591 case INTERP_MODE_NONE:
592 /* If a gl_FrontColor or gl_BackColor input has no interp
593 * qualifier, then if we're using glShadeModel(GL_FLAT) it
594 * needs to be flat shaded.
595 */
596 switch (var->data.location + array_index) {
597 case VARYING_SLOT_COL0:
598 case VARYING_SLOT_COL1:
599 case VARYING_SLOT_BFC0:
600 case VARYING_SLOT_BFC1:
601 if (c->fs_key->shade_model_flat) {
602 BITSET_SET(c->flat_shade_flags, i);
603 vir_MOV_dest(c, c->undef, vary);
604 return vir_MOV(c, r5);
605 } else {
606 return vir_FADD(c, vir_FMUL(c, vary,
607 c->payload_w), r5);
608 }
609 default:
610 break;
611 }
612 /* FALLTHROUGH */
613 case INTERP_MODE_SMOOTH:
614 if (var->data.centroid) {
615 BITSET_SET(c->centroid_flags, i);
616 return vir_FADD(c, vir_FMUL(c, vary,
617 c->payload_w_centroid), r5);
618 } else {
619 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
620 }
621 case INTERP_MODE_NOPERSPECTIVE:
622 BITSET_SET(c->noperspective_flags, i);
623 return vir_FADD(c, vir_MOV(c, vary), r5);
624 case INTERP_MODE_FLAT:
625 BITSET_SET(c->flat_shade_flags, i);
626 vir_MOV_dest(c, c->undef, vary);
627 return vir_MOV(c, r5);
628 default:
629 unreachable("Bad interp mode");
630 }
631 }
632
633 static void
634 emit_fragment_input(struct v3d_compile *c, int attr, nir_variable *var,
635 int array_index)
636 {
637 for (int i = 0; i < glsl_get_vector_elements(var->type); i++) {
638 int chan = var->data.location_frac + i;
639 c->inputs[attr * 4 + chan] =
640 emit_fragment_varying(c, var, chan, array_index);
641 }
642 }
643
644 static void
645 add_output(struct v3d_compile *c,
646 uint32_t decl_offset,
647 uint8_t slot,
648 uint8_t swizzle)
649 {
650 uint32_t old_array_size = c->outputs_array_size;
651 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
652 decl_offset + 1);
653
654 if (old_array_size != c->outputs_array_size) {
655 c->output_slots = reralloc(c,
656 c->output_slots,
657 struct v3d_varying_slot,
658 c->outputs_array_size);
659 }
660
661 c->output_slots[decl_offset] =
662 v3d_slot_from_slot_and_component(slot, swizzle);
663 }
664
665 static void
666 declare_uniform_range(struct v3d_compile *c, uint32_t start, uint32_t size)
667 {
668 unsigned array_id = c->num_ubo_ranges++;
669 if (array_id >= c->ubo_ranges_array_size) {
670 c->ubo_ranges_array_size = MAX2(c->ubo_ranges_array_size * 2,
671 array_id + 1);
672 c->ubo_ranges = reralloc(c, c->ubo_ranges,
673 struct v3d_ubo_range,
674 c->ubo_ranges_array_size);
675 c->ubo_range_used = reralloc(c, c->ubo_range_used,
676 bool,
677 c->ubo_ranges_array_size);
678 }
679
680 c->ubo_ranges[array_id].dst_offset = 0;
681 c->ubo_ranges[array_id].src_offset = start;
682 c->ubo_ranges[array_id].size = size;
683 c->ubo_range_used[array_id] = false;
684 }
685
686 /**
687 * If compare_instr is a valid comparison instruction, emits the
688 * compare_instr's comparison and returns the sel_instr's return value based
689 * on the compare_instr's result.
690 */
691 static bool
692 ntq_emit_comparison(struct v3d_compile *c,
693 nir_alu_instr *compare_instr,
694 enum v3d_qpu_cond *out_cond)
695 {
696 struct qreg src0 = ntq_get_alu_src(c, compare_instr, 0);
697 struct qreg src1;
698 if (nir_op_infos[compare_instr->op].num_inputs > 1)
699 src1 = ntq_get_alu_src(c, compare_instr, 1);
700 bool cond_invert = false;
701 struct qreg nop = vir_nop_reg();
702
703 switch (compare_instr->op) {
704 case nir_op_feq32:
705 case nir_op_seq:
706 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
707 break;
708 case nir_op_ieq32:
709 vir_set_pf(vir_XOR_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
710 break;
711
712 case nir_op_fne32:
713 case nir_op_sne:
714 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
715 cond_invert = true;
716 break;
717 case nir_op_ine32:
718 vir_set_pf(vir_XOR_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
719 cond_invert = true;
720 break;
721
722 case nir_op_fge32:
723 case nir_op_sge:
724 vir_set_pf(vir_FCMP_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
725 break;
726 case nir_op_ige32:
727 vir_set_pf(vir_MIN_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
728 cond_invert = true;
729 break;
730 case nir_op_uge32:
731 vir_set_pf(vir_SUB_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHC);
732 cond_invert = true;
733 break;
734
735 case nir_op_slt:
736 case nir_op_flt32:
737 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHN);
738 break;
739 case nir_op_ilt32:
740 vir_set_pf(vir_MIN_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
741 break;
742 case nir_op_ult32:
743 vir_set_pf(vir_SUB_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHC);
744 break;
745
746 default:
747 return false;
748 }
749
750 *out_cond = cond_invert ? V3D_QPU_COND_IFNA : V3D_QPU_COND_IFA;
751
752 return true;
753 }
754
755 /* Finds an ALU instruction that generates our src value that could
756 * (potentially) be greedily emitted in the consuming instruction.
757 */
758 static struct nir_alu_instr *
759 ntq_get_alu_parent(nir_src src)
760 {
761 if (!src.is_ssa || src.ssa->parent_instr->type != nir_instr_type_alu)
762 return NULL;
763 nir_alu_instr *instr = nir_instr_as_alu(src.ssa->parent_instr);
764 if (!instr)
765 return NULL;
766
767 /* If the ALU instr's srcs are non-SSA, then we would have to avoid
768 * moving emission of the ALU instr down past another write of the
769 * src.
770 */
771 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
772 if (!instr->src[i].src.is_ssa)
773 return NULL;
774 }
775
776 return instr;
777 }
778
779 /**
780 * Attempts to fold a comparison generating a boolean result into the
781 * condition code for selecting between two values, instead of comparing the
782 * boolean result against 0 to generate the condition code.
783 */
784 static struct qreg ntq_emit_bcsel(struct v3d_compile *c, nir_alu_instr *instr,
785 struct qreg *src)
786 {
787 nir_alu_instr *compare = ntq_get_alu_parent(instr->src[0].src);
788 if (!compare)
789 goto out;
790
791 enum v3d_qpu_cond cond;
792 if (ntq_emit_comparison(c, compare, &cond))
793 return vir_MOV(c, vir_SEL(c, cond, src[1], src[2]));
794
795 out:
796 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
797 return vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA, src[1], src[2]));
798 }
799
800
801 static void
802 ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr)
803 {
804 /* This should always be lowered to ALU operations for V3D. */
805 assert(!instr->dest.saturate);
806
807 /* Vectors are special in that they have non-scalarized writemasks,
808 * and just take the first swizzle channel for each argument in order
809 * into each writemask channel.
810 */
811 if (instr->op == nir_op_vec2 ||
812 instr->op == nir_op_vec3 ||
813 instr->op == nir_op_vec4) {
814 struct qreg srcs[4];
815 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
816 srcs[i] = ntq_get_src(c, instr->src[i].src,
817 instr->src[i].swizzle[0]);
818 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
819 ntq_store_dest(c, &instr->dest.dest, i,
820 vir_MOV(c, srcs[i]));
821 return;
822 }
823
824 /* General case: We can just grab the one used channel per src. */
825 struct qreg src[nir_op_infos[instr->op].num_inputs];
826 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
827 src[i] = ntq_get_alu_src(c, instr, i);
828 }
829
830 struct qreg result;
831
832 switch (instr->op) {
833 case nir_op_fmov:
834 case nir_op_imov:
835 result = vir_MOV(c, src[0]);
836 break;
837
838 case nir_op_fneg:
839 result = vir_XOR(c, src[0], vir_uniform_ui(c, 1 << 31));
840 break;
841 case nir_op_ineg:
842 result = vir_NEG(c, src[0]);
843 break;
844
845 case nir_op_fmul:
846 result = vir_FMUL(c, src[0], src[1]);
847 break;
848 case nir_op_fadd:
849 result = vir_FADD(c, src[0], src[1]);
850 break;
851 case nir_op_fsub:
852 result = vir_FSUB(c, src[0], src[1]);
853 break;
854 case nir_op_fmin:
855 result = vir_FMIN(c, src[0], src[1]);
856 break;
857 case nir_op_fmax:
858 result = vir_FMAX(c, src[0], src[1]);
859 break;
860
861 case nir_op_f2i32:
862 result = vir_FTOIZ(c, src[0]);
863 break;
864 case nir_op_f2u32:
865 result = vir_FTOUZ(c, src[0]);
866 break;
867 case nir_op_i2f32:
868 result = vir_ITOF(c, src[0]);
869 break;
870 case nir_op_u2f32:
871 result = vir_UTOF(c, src[0]);
872 break;
873 case nir_op_b2f32:
874 result = vir_AND(c, src[0], vir_uniform_f(c, 1.0));
875 break;
876 case nir_op_b2i32:
877 result = vir_AND(c, src[0], vir_uniform_ui(c, 1));
878 break;
879 case nir_op_i2b32:
880 case nir_op_f2b32:
881 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
882 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
883 vir_uniform_ui(c, ~0),
884 vir_uniform_ui(c, 0)));
885 break;
886
887 case nir_op_iadd:
888 result = vir_ADD(c, src[0], src[1]);
889 break;
890 case nir_op_ushr:
891 result = vir_SHR(c, src[0], src[1]);
892 break;
893 case nir_op_isub:
894 result = vir_SUB(c, src[0], src[1]);
895 break;
896 case nir_op_ishr:
897 result = vir_ASR(c, src[0], src[1]);
898 break;
899 case nir_op_ishl:
900 result = vir_SHL(c, src[0], src[1]);
901 break;
902 case nir_op_imin:
903 result = vir_MIN(c, src[0], src[1]);
904 break;
905 case nir_op_umin:
906 result = vir_UMIN(c, src[0], src[1]);
907 break;
908 case nir_op_imax:
909 result = vir_MAX(c, src[0], src[1]);
910 break;
911 case nir_op_umax:
912 result = vir_UMAX(c, src[0], src[1]);
913 break;
914 case nir_op_iand:
915 result = vir_AND(c, src[0], src[1]);
916 break;
917 case nir_op_ior:
918 result = vir_OR(c, src[0], src[1]);
919 break;
920 case nir_op_ixor:
921 result = vir_XOR(c, src[0], src[1]);
922 break;
923 case nir_op_inot:
924 result = vir_NOT(c, src[0]);
925 break;
926
927 case nir_op_ufind_msb:
928 result = vir_SUB(c, vir_uniform_ui(c, 31), vir_CLZ(c, src[0]));
929 break;
930
931 case nir_op_imul:
932 result = vir_UMUL(c, src[0], src[1]);
933 break;
934
935 case nir_op_seq:
936 case nir_op_sne:
937 case nir_op_sge:
938 case nir_op_slt: {
939 enum v3d_qpu_cond cond;
940 MAYBE_UNUSED bool ok = ntq_emit_comparison(c, instr, &cond);
941 assert(ok);
942 result = vir_MOV(c, vir_SEL(c, cond,
943 vir_uniform_f(c, 1.0),
944 vir_uniform_f(c, 0.0)));
945 break;
946 }
947
948 case nir_op_feq32:
949 case nir_op_fne32:
950 case nir_op_fge32:
951 case nir_op_flt32:
952 case nir_op_ieq32:
953 case nir_op_ine32:
954 case nir_op_ige32:
955 case nir_op_uge32:
956 case nir_op_ilt32:
957 case nir_op_ult32: {
958 enum v3d_qpu_cond cond;
959 MAYBE_UNUSED bool ok = ntq_emit_comparison(c, instr, &cond);
960 assert(ok);
961 result = vir_MOV(c, vir_SEL(c, cond,
962 vir_uniform_ui(c, ~0),
963 vir_uniform_ui(c, 0)));
964 break;
965 }
966
967 case nir_op_b32csel:
968 result = ntq_emit_bcsel(c, instr, src);
969 break;
970 case nir_op_fcsel:
971 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
972 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
973 src[1], src[2]));
974 break;
975
976 case nir_op_frcp:
977 result = vir_RECIP(c, src[0]);
978 break;
979 case nir_op_frsq:
980 result = vir_RSQRT(c, src[0]);
981 break;
982 case nir_op_fexp2:
983 result = vir_EXP(c, src[0]);
984 break;
985 case nir_op_flog2:
986 result = vir_LOG(c, src[0]);
987 break;
988
989 case nir_op_fceil:
990 result = vir_FCEIL(c, src[0]);
991 break;
992 case nir_op_ffloor:
993 result = vir_FFLOOR(c, src[0]);
994 break;
995 case nir_op_fround_even:
996 result = vir_FROUND(c, src[0]);
997 break;
998 case nir_op_ftrunc:
999 result = vir_FTRUNC(c, src[0]);
1000 break;
1001
1002 case nir_op_fsin:
1003 result = ntq_fsincos(c, src[0], false);
1004 break;
1005 case nir_op_fcos:
1006 result = ntq_fsincos(c, src[0], true);
1007 break;
1008
1009 case nir_op_fsign:
1010 result = ntq_fsign(c, src[0]);
1011 break;
1012
1013 case nir_op_fabs: {
1014 result = vir_FMOV(c, src[0]);
1015 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_ABS);
1016 break;
1017 }
1018
1019 case nir_op_iabs:
1020 result = vir_MAX(c, src[0],
1021 vir_SUB(c, vir_uniform_ui(c, 0), src[0]));
1022 break;
1023
1024 case nir_op_fddx:
1025 case nir_op_fddx_coarse:
1026 case nir_op_fddx_fine:
1027 result = vir_FDX(c, src[0]);
1028 break;
1029
1030 case nir_op_fddy:
1031 case nir_op_fddy_coarse:
1032 case nir_op_fddy_fine:
1033 result = vir_FDY(c, src[0]);
1034 break;
1035
1036 case nir_op_uadd_carry:
1037 vir_PF(c, vir_ADD(c, src[0], src[1]), V3D_QPU_PF_PUSHC);
1038 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFA,
1039 vir_uniform_ui(c, ~0),
1040 vir_uniform_ui(c, 0)));
1041 break;
1042
1043 case nir_op_pack_half_2x16_split:
1044 result = vir_VFPACK(c, src[0], src[1]);
1045 break;
1046
1047 case nir_op_unpack_half_2x16_split_x:
1048 result = vir_FMOV(c, src[0]);
1049 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_L);
1050 break;
1051
1052 case nir_op_unpack_half_2x16_split_y:
1053 result = vir_FMOV(c, src[0]);
1054 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_H);
1055 break;
1056
1057 default:
1058 fprintf(stderr, "unknown NIR ALU inst: ");
1059 nir_print_instr(&instr->instr, stderr);
1060 fprintf(stderr, "\n");
1061 abort();
1062 }
1063
1064 /* We have a scalar result, so the instruction should only have a
1065 * single channel written to.
1066 */
1067 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
1068 ntq_store_dest(c, &instr->dest.dest,
1069 ffs(instr->dest.write_mask) - 1, result);
1070 }
1071
1072 /* Each TLB read/write setup (a render target or depth buffer) takes an 8-bit
1073 * specifier. They come from a register that's preloaded with 0xffffffff
1074 * (0xff gets you normal vec4 f16 RT0 writes), and when one is neaded the low
1075 * 8 bits are shifted off the bottom and 0xff shifted in from the top.
1076 */
1077 #define TLB_TYPE_F16_COLOR (3 << 6)
1078 #define TLB_TYPE_I32_COLOR (1 << 6)
1079 #define TLB_TYPE_F32_COLOR (0 << 6)
1080 #define TLB_RENDER_TARGET_SHIFT 3 /* Reversed! 7 = RT 0, 0 = RT 7. */
1081 #define TLB_SAMPLE_MODE_PER_SAMPLE (0 << 2)
1082 #define TLB_SAMPLE_MODE_PER_PIXEL (1 << 2)
1083 #define TLB_F16_SWAP_HI_LO (1 << 1)
1084 #define TLB_VEC_SIZE_4_F16 (1 << 0)
1085 #define TLB_VEC_SIZE_2_F16 (0 << 0)
1086 #define TLB_VEC_SIZE_MINUS_1_SHIFT 0
1087
1088 /* Triggers Z/Stencil testing, used when the shader state's "FS modifies Z"
1089 * flag is set.
1090 */
1091 #define TLB_TYPE_DEPTH ((2 << 6) | (0 << 4))
1092 #define TLB_DEPTH_TYPE_INVARIANT (0 << 2) /* Unmodified sideband input used */
1093 #define TLB_DEPTH_TYPE_PER_PIXEL (1 << 2) /* QPU result used */
1094 #define TLB_V42_DEPTH_TYPE_INVARIANT (0 << 3) /* Unmodified sideband input used */
1095 #define TLB_V42_DEPTH_TYPE_PER_PIXEL (1 << 3) /* QPU result used */
1096
1097 /* Stencil is a single 32-bit write. */
1098 #define TLB_TYPE_STENCIL_ALPHA ((2 << 6) | (1 << 4))
1099
1100 static void
1101 emit_frag_end(struct v3d_compile *c)
1102 {
1103 /* XXX
1104 if (c->output_sample_mask_index != -1) {
1105 vir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
1106 }
1107 */
1108
1109 bool has_any_tlb_color_write = false;
1110 for (int rt = 0; rt < V3D_MAX_DRAW_BUFFERS; rt++) {
1111 if (c->fs_key->cbufs & (1 << rt) && c->output_color_var[rt])
1112 has_any_tlb_color_write = true;
1113 }
1114
1115 if (c->fs_key->sample_alpha_to_coverage && c->output_color_var[0]) {
1116 struct nir_variable *var = c->output_color_var[0];
1117 struct qreg *color = &c->outputs[var->data.driver_location * 4];
1118
1119 vir_SETMSF_dest(c, vir_nop_reg(),
1120 vir_AND(c,
1121 vir_MSF(c),
1122 vir_FTOC(c, color[3])));
1123 }
1124
1125 if (c->output_position_index != -1) {
1126 struct qinst *inst = vir_MOV_dest(c,
1127 vir_reg(QFILE_TLBU, 0),
1128 c->outputs[c->output_position_index]);
1129 uint8_t tlb_specifier = TLB_TYPE_DEPTH;
1130
1131 if (c->devinfo->ver >= 42) {
1132 tlb_specifier |= (TLB_V42_DEPTH_TYPE_PER_PIXEL |
1133 TLB_SAMPLE_MODE_PER_PIXEL);
1134 } else
1135 tlb_specifier |= TLB_DEPTH_TYPE_PER_PIXEL;
1136
1137 inst->src[vir_get_implicit_uniform_src(inst)] =
1138 vir_uniform_ui(c, tlb_specifier | 0xffffff00);
1139 c->writes_z = true;
1140 } else if (c->s->info.fs.uses_discard ||
1141 !c->s->info.fs.early_fragment_tests ||
1142 c->fs_key->sample_alpha_to_coverage ||
1143 !has_any_tlb_color_write) {
1144 /* Emit passthrough Z if it needed to be delayed until shader
1145 * end due to potential discards.
1146 *
1147 * Since (single-threaded) fragment shaders always need a TLB
1148 * write, emit passthrouh Z if we didn't have any color
1149 * buffers and flag us as potentially discarding, so that we
1150 * can use Z as the TLB write.
1151 */
1152 c->s->info.fs.uses_discard = true;
1153
1154 struct qinst *inst = vir_MOV_dest(c,
1155 vir_reg(QFILE_TLBU, 0),
1156 vir_nop_reg());
1157 uint8_t tlb_specifier = TLB_TYPE_DEPTH;
1158
1159 if (c->devinfo->ver >= 42) {
1160 /* The spec says the PER_PIXEL flag is ignored for
1161 * invariant writes, but the simulator demands it.
1162 */
1163 tlb_specifier |= (TLB_V42_DEPTH_TYPE_INVARIANT |
1164 TLB_SAMPLE_MODE_PER_PIXEL);
1165 } else {
1166 tlb_specifier |= TLB_DEPTH_TYPE_INVARIANT;
1167 }
1168
1169 inst->src[vir_get_implicit_uniform_src(inst)] =
1170 vir_uniform_ui(c, tlb_specifier | 0xffffff00);
1171 c->writes_z = true;
1172 }
1173
1174 /* XXX: Performance improvement: Merge Z write and color writes TLB
1175 * uniform setup
1176 */
1177
1178 for (int rt = 0; rt < V3D_MAX_DRAW_BUFFERS; rt++) {
1179 if (!(c->fs_key->cbufs & (1 << rt)) || !c->output_color_var[rt])
1180 continue;
1181
1182 nir_variable *var = c->output_color_var[rt];
1183 struct qreg *color = &c->outputs[var->data.driver_location * 4];
1184 int num_components = glsl_get_vector_elements(var->type);
1185 uint32_t conf = 0xffffff00;
1186 struct qinst *inst;
1187
1188 conf |= TLB_SAMPLE_MODE_PER_PIXEL;
1189 conf |= (7 - rt) << TLB_RENDER_TARGET_SHIFT;
1190
1191 if (c->fs_key->swap_color_rb & (1 << rt))
1192 num_components = MAX2(num_components, 3);
1193
1194 assert(num_components != 0);
1195 switch (glsl_get_base_type(var->type)) {
1196 case GLSL_TYPE_UINT:
1197 case GLSL_TYPE_INT:
1198 /* The F32 vs I32 distinction was dropped in 4.2. */
1199 if (c->devinfo->ver < 42)
1200 conf |= TLB_TYPE_I32_COLOR;
1201 else
1202 conf |= TLB_TYPE_F32_COLOR;
1203 conf |= ((num_components - 1) <<
1204 TLB_VEC_SIZE_MINUS_1_SHIFT);
1205
1206 inst = vir_MOV_dest(c, vir_reg(QFILE_TLBU, 0), color[0]);
1207 inst->src[vir_get_implicit_uniform_src(inst)] =
1208 vir_uniform_ui(c, conf);
1209
1210 for (int i = 1; i < num_components; i++) {
1211 inst = vir_MOV_dest(c, vir_reg(QFILE_TLB, 0),
1212 color[i]);
1213 }
1214 break;
1215
1216 default: {
1217 struct qreg r = color[0];
1218 struct qreg g = color[1];
1219 struct qreg b = color[2];
1220 struct qreg a = color[3];
1221
1222 if (c->fs_key->f32_color_rb & (1 << rt)) {
1223 conf |= TLB_TYPE_F32_COLOR;
1224 conf |= ((num_components - 1) <<
1225 TLB_VEC_SIZE_MINUS_1_SHIFT);
1226 } else {
1227 conf |= TLB_TYPE_F16_COLOR;
1228 conf |= TLB_F16_SWAP_HI_LO;
1229 if (num_components >= 3)
1230 conf |= TLB_VEC_SIZE_4_F16;
1231 else
1232 conf |= TLB_VEC_SIZE_2_F16;
1233 }
1234
1235 if (c->fs_key->swap_color_rb & (1 << rt)) {
1236 r = color[2];
1237 b = color[0];
1238 }
1239
1240 if (c->fs_key->sample_alpha_to_one)
1241 a = vir_uniform_f(c, 1.0);
1242
1243 if (c->fs_key->f32_color_rb & (1 << rt)) {
1244 inst = vir_MOV_dest(c, vir_reg(QFILE_TLBU, 0), r);
1245 inst->src[vir_get_implicit_uniform_src(inst)] =
1246 vir_uniform_ui(c, conf);
1247
1248 if (num_components >= 2)
1249 vir_MOV_dest(c, vir_reg(QFILE_TLB, 0), g);
1250 if (num_components >= 3)
1251 vir_MOV_dest(c, vir_reg(QFILE_TLB, 0), b);
1252 if (num_components >= 4)
1253 vir_MOV_dest(c, vir_reg(QFILE_TLB, 0), a);
1254 } else {
1255 inst = vir_VFPACK_dest(c, vir_reg(QFILE_TLB, 0), r, g);
1256 if (conf != ~0) {
1257 inst->dst.file = QFILE_TLBU;
1258 inst->src[vir_get_implicit_uniform_src(inst)] =
1259 vir_uniform_ui(c, conf);
1260 }
1261
1262 if (num_components >= 3)
1263 inst = vir_VFPACK_dest(c, vir_reg(QFILE_TLB, 0), b, a);
1264 }
1265 break;
1266 }
1267 }
1268 }
1269 }
1270
1271 static void
1272 vir_VPM_WRITE(struct v3d_compile *c, struct qreg val, uint32_t *vpm_index)
1273 {
1274 if (c->devinfo->ver >= 40) {
1275 vir_STVPMV(c, vir_uniform_ui(c, *vpm_index), val);
1276 *vpm_index = *vpm_index + 1;
1277 } else {
1278 vir_MOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_VPM), val);
1279 }
1280
1281 c->num_vpm_writes++;
1282 }
1283
1284 static void
1285 emit_scaled_viewport_write(struct v3d_compile *c, struct qreg rcp_w,
1286 uint32_t *vpm_index)
1287 {
1288 for (int i = 0; i < 2; i++) {
1289 struct qreg coord = c->outputs[c->output_position_index + i];
1290 coord = vir_FMUL(c, coord,
1291 vir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i,
1292 0));
1293 coord = vir_FMUL(c, coord, rcp_w);
1294 vir_VPM_WRITE(c, vir_FTOIN(c, coord), vpm_index);
1295 }
1296
1297 }
1298
1299 static void
1300 emit_zs_write(struct v3d_compile *c, struct qreg rcp_w, uint32_t *vpm_index)
1301 {
1302 struct qreg zscale = vir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1303 struct qreg zoffset = vir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1304
1305 struct qreg z = c->outputs[c->output_position_index + 2];
1306 z = vir_FMUL(c, z, zscale);
1307 z = vir_FMUL(c, z, rcp_w);
1308 z = vir_FADD(c, z, zoffset);
1309 vir_VPM_WRITE(c, z, vpm_index);
1310 }
1311
1312 static void
1313 emit_rcp_wc_write(struct v3d_compile *c, struct qreg rcp_w, uint32_t *vpm_index)
1314 {
1315 vir_VPM_WRITE(c, rcp_w, vpm_index);
1316 }
1317
1318 static void
1319 emit_point_size_write(struct v3d_compile *c, uint32_t *vpm_index)
1320 {
1321 struct qreg point_size;
1322
1323 if (c->output_point_size_index != -1)
1324 point_size = c->outputs[c->output_point_size_index];
1325 else
1326 point_size = vir_uniform_f(c, 1.0);
1327
1328 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1329 * BCM21553).
1330 */
1331 point_size = vir_FMAX(c, point_size, vir_uniform_f(c, .125));
1332
1333 vir_VPM_WRITE(c, point_size, vpm_index);
1334 }
1335
1336 static void
1337 emit_vpm_write_setup(struct v3d_compile *c)
1338 {
1339 if (c->devinfo->ver >= 40)
1340 return;
1341
1342 v3d33_vir_vpm_write_setup(c);
1343 }
1344
1345 /**
1346 * Sets up c->outputs[c->output_position_index] for the vertex shader
1347 * epilogue, if an output vertex position wasn't specified in the user's
1348 * shader. This may be the case for transform feedback with rasterizer
1349 * discard enabled.
1350 */
1351 static void
1352 setup_default_position(struct v3d_compile *c)
1353 {
1354 if (c->output_position_index != -1)
1355 return;
1356
1357 c->output_position_index = c->outputs_array_size;
1358 for (int i = 0; i < 4; i++) {
1359 add_output(c,
1360 c->output_position_index + i,
1361 VARYING_SLOT_POS, i);
1362 }
1363 }
1364
1365 static void
1366 emit_vert_end(struct v3d_compile *c)
1367 {
1368 setup_default_position(c);
1369
1370 uint32_t vpm_index = 0;
1371 struct qreg rcp_w = vir_RECIP(c,
1372 c->outputs[c->output_position_index + 3]);
1373
1374 emit_vpm_write_setup(c);
1375
1376 if (c->vs_key->is_coord) {
1377 for (int i = 0; i < 4; i++)
1378 vir_VPM_WRITE(c, c->outputs[c->output_position_index + i],
1379 &vpm_index);
1380 emit_scaled_viewport_write(c, rcp_w, &vpm_index);
1381 if (c->vs_key->per_vertex_point_size) {
1382 emit_point_size_write(c, &vpm_index);
1383 /* emit_rcp_wc_write(c, rcp_w); */
1384 }
1385 /* XXX: Z-only rendering */
1386 if (0)
1387 emit_zs_write(c, rcp_w, &vpm_index);
1388 } else {
1389 emit_scaled_viewport_write(c, rcp_w, &vpm_index);
1390 emit_zs_write(c, rcp_w, &vpm_index);
1391 emit_rcp_wc_write(c, rcp_w, &vpm_index);
1392 if (c->vs_key->per_vertex_point_size)
1393 emit_point_size_write(c, &vpm_index);
1394 }
1395
1396 for (int i = 0; i < c->vs_key->num_fs_inputs; i++) {
1397 struct v3d_varying_slot input = c->vs_key->fs_inputs[i];
1398 int j;
1399
1400 for (j = 0; j < c->num_outputs; j++) {
1401 struct v3d_varying_slot output = c->output_slots[j];
1402
1403 if (!memcmp(&input, &output, sizeof(input))) {
1404 vir_VPM_WRITE(c, c->outputs[j],
1405 &vpm_index);
1406 break;
1407 }
1408 }
1409 /* Emit padding if we didn't find a declared VS output for
1410 * this FS input.
1411 */
1412 if (j == c->num_outputs)
1413 vir_VPM_WRITE(c, vir_uniform_f(c, 0.0),
1414 &vpm_index);
1415 }
1416
1417 /* GFXH-1684: VPM writes need to be complete by the end of the shader.
1418 */
1419 if (c->devinfo->ver >= 40 && c->devinfo->ver <= 42)
1420 vir_VPMWT(c);
1421 }
1422
1423 void
1424 v3d_optimize_nir(struct nir_shader *s)
1425 {
1426 bool progress;
1427
1428 do {
1429 progress = false;
1430
1431 NIR_PASS_V(s, nir_lower_vars_to_ssa);
1432 NIR_PASS(progress, s, nir_lower_alu_to_scalar);
1433 NIR_PASS(progress, s, nir_lower_phis_to_scalar);
1434 NIR_PASS(progress, s, nir_copy_prop);
1435 NIR_PASS(progress, s, nir_opt_remove_phis);
1436 NIR_PASS(progress, s, nir_opt_dce);
1437 NIR_PASS(progress, s, nir_opt_dead_cf);
1438 NIR_PASS(progress, s, nir_opt_cse);
1439 NIR_PASS(progress, s, nir_opt_peephole_select, 8, true, true);
1440 NIR_PASS(progress, s, nir_opt_algebraic);
1441 NIR_PASS(progress, s, nir_opt_constant_folding);
1442 NIR_PASS(progress, s, nir_opt_undef);
1443 } while (progress);
1444
1445 NIR_PASS(progress, s, nir_opt_move_load_ubo);
1446 }
1447
1448 static int
1449 driver_location_compare(const void *in_a, const void *in_b)
1450 {
1451 const nir_variable *const *a = in_a;
1452 const nir_variable *const *b = in_b;
1453
1454 return (*a)->data.driver_location - (*b)->data.driver_location;
1455 }
1456
1457 static struct qreg
1458 ntq_emit_vpm_read(struct v3d_compile *c,
1459 uint32_t *num_components_queued,
1460 uint32_t *remaining,
1461 uint32_t vpm_index)
1462 {
1463 struct qreg vpm = vir_reg(QFILE_VPM, vpm_index);
1464
1465 if (c->devinfo->ver >= 40 ) {
1466 return vir_LDVPMV_IN(c,
1467 vir_uniform_ui(c,
1468 (*num_components_queued)++));
1469 }
1470
1471 if (*num_components_queued != 0) {
1472 (*num_components_queued)--;
1473 c->num_inputs++;
1474 return vir_MOV(c, vpm);
1475 }
1476
1477 uint32_t num_components = MIN2(*remaining, 32);
1478
1479 v3d33_vir_vpm_read_setup(c, num_components);
1480
1481 *num_components_queued = num_components - 1;
1482 *remaining -= num_components;
1483 c->num_inputs++;
1484
1485 return vir_MOV(c, vpm);
1486 }
1487
1488 static void
1489 ntq_setup_vpm_inputs(struct v3d_compile *c)
1490 {
1491 /* Figure out how many components of each vertex attribute the shader
1492 * uses. Each variable should have been split to individual
1493 * components and unused ones DCEed. The vertex fetcher will load
1494 * from the start of the attribute to the number of components we
1495 * declare we need in c->vattr_sizes[].
1496 */
1497 nir_foreach_variable(var, &c->s->inputs) {
1498 /* No VS attribute array support. */
1499 assert(MAX2(glsl_get_length(var->type), 1) == 1);
1500
1501 unsigned loc = var->data.driver_location;
1502 int start_component = var->data.location_frac;
1503 int num_components = glsl_get_components(var->type);
1504
1505 c->vattr_sizes[loc] = MAX2(c->vattr_sizes[loc],
1506 start_component + num_components);
1507 }
1508
1509 unsigned num_components = 0;
1510 uint32_t vpm_components_queued = 0;
1511 bool uses_iid = c->s->info.system_values_read &
1512 (1ull << SYSTEM_VALUE_INSTANCE_ID);
1513 bool uses_vid = c->s->info.system_values_read &
1514 (1ull << SYSTEM_VALUE_VERTEX_ID);
1515 num_components += uses_iid;
1516 num_components += uses_vid;
1517
1518 for (int i = 0; i < ARRAY_SIZE(c->vattr_sizes); i++)
1519 num_components += c->vattr_sizes[i];
1520
1521 if (uses_iid) {
1522 c->iid = ntq_emit_vpm_read(c, &vpm_components_queued,
1523 &num_components, ~0);
1524 }
1525
1526 if (uses_vid) {
1527 c->vid = ntq_emit_vpm_read(c, &vpm_components_queued,
1528 &num_components, ~0);
1529 }
1530
1531 for (int loc = 0; loc < ARRAY_SIZE(c->vattr_sizes); loc++) {
1532 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1533 (loc + 1) * 4);
1534
1535 for (int i = 0; i < c->vattr_sizes[loc]; i++) {
1536 c->inputs[loc * 4 + i] =
1537 ntq_emit_vpm_read(c,
1538 &vpm_components_queued,
1539 &num_components,
1540 loc * 4 + i);
1541
1542 }
1543 }
1544
1545 if (c->devinfo->ver >= 40) {
1546 assert(vpm_components_queued == num_components);
1547 } else {
1548 assert(vpm_components_queued == 0);
1549 assert(num_components == 0);
1550 }
1551 }
1552
1553 static void
1554 ntq_setup_fs_inputs(struct v3d_compile *c)
1555 {
1556 unsigned num_entries = 0;
1557 unsigned num_components = 0;
1558 nir_foreach_variable(var, &c->s->inputs) {
1559 num_entries++;
1560 num_components += glsl_get_components(var->type);
1561 }
1562
1563 nir_variable *vars[num_entries];
1564
1565 unsigned i = 0;
1566 nir_foreach_variable(var, &c->s->inputs)
1567 vars[i++] = var;
1568
1569 /* Sort the variables so that we emit the input setup in
1570 * driver_location order. This is required for VPM reads, whose data
1571 * is fetched into the VPM in driver_location (TGSI register index)
1572 * order.
1573 */
1574 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1575
1576 for (unsigned i = 0; i < num_entries; i++) {
1577 nir_variable *var = vars[i];
1578 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1579 unsigned loc = var->data.driver_location;
1580
1581 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1582 (loc + array_len) * 4);
1583
1584 if (var->data.location == VARYING_SLOT_POS) {
1585 emit_fragcoord_input(c, loc);
1586 } else if (var->data.location == VARYING_SLOT_PNTC ||
1587 (var->data.location >= VARYING_SLOT_VAR0 &&
1588 (c->fs_key->point_sprite_mask &
1589 (1 << (var->data.location -
1590 VARYING_SLOT_VAR0))))) {
1591 c->inputs[loc * 4 + 0] = c->point_x;
1592 c->inputs[loc * 4 + 1] = c->point_y;
1593 } else {
1594 for (int j = 0; j < array_len; j++)
1595 emit_fragment_input(c, loc + j, var, j);
1596 }
1597 }
1598 }
1599
1600 static void
1601 ntq_setup_outputs(struct v3d_compile *c)
1602 {
1603 nir_foreach_variable(var, &c->s->outputs) {
1604 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1605 unsigned loc = var->data.driver_location * 4;
1606
1607 assert(array_len == 1);
1608 (void)array_len;
1609
1610 for (int i = 0; i < 4 - var->data.location_frac; i++) {
1611 add_output(c, loc + var->data.location_frac + i,
1612 var->data.location,
1613 var->data.location_frac + i);
1614 }
1615
1616 if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
1617 switch (var->data.location) {
1618 case FRAG_RESULT_COLOR:
1619 c->output_color_var[0] = var;
1620 c->output_color_var[1] = var;
1621 c->output_color_var[2] = var;
1622 c->output_color_var[3] = var;
1623 break;
1624 case FRAG_RESULT_DATA0:
1625 case FRAG_RESULT_DATA1:
1626 case FRAG_RESULT_DATA2:
1627 case FRAG_RESULT_DATA3:
1628 c->output_color_var[var->data.location -
1629 FRAG_RESULT_DATA0] = var;
1630 break;
1631 case FRAG_RESULT_DEPTH:
1632 c->output_position_index = loc;
1633 break;
1634 case FRAG_RESULT_SAMPLE_MASK:
1635 c->output_sample_mask_index = loc;
1636 break;
1637 }
1638 } else {
1639 switch (var->data.location) {
1640 case VARYING_SLOT_POS:
1641 c->output_position_index = loc;
1642 break;
1643 case VARYING_SLOT_PSIZ:
1644 c->output_point_size_index = loc;
1645 break;
1646 }
1647 }
1648 }
1649 }
1650
1651 static void
1652 ntq_setup_uniforms(struct v3d_compile *c)
1653 {
1654 nir_foreach_variable(var, &c->s->uniforms) {
1655 uint32_t vec4_count = glsl_count_attribute_slots(var->type,
1656 false);
1657 unsigned vec4_size = 4 * sizeof(float);
1658
1659 if (var->data.mode != nir_var_uniform)
1660 continue;
1661
1662 declare_uniform_range(c, var->data.driver_location * vec4_size,
1663 vec4_count * vec4_size);
1664
1665 }
1666 }
1667
1668 /**
1669 * Sets up the mapping from nir_register to struct qreg *.
1670 *
1671 * Each nir_register gets a struct qreg per 32-bit component being stored.
1672 */
1673 static void
1674 ntq_setup_registers(struct v3d_compile *c, struct exec_list *list)
1675 {
1676 foreach_list_typed(nir_register, nir_reg, node, list) {
1677 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1678 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1679 array_len *
1680 nir_reg->num_components);
1681
1682 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1683
1684 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1685 qregs[i] = vir_get_temp(c);
1686 }
1687 }
1688
1689 static void
1690 ntq_emit_load_const(struct v3d_compile *c, nir_load_const_instr *instr)
1691 {
1692 /* XXX perf: Experiment with using immediate loads to avoid having
1693 * these end up in the uniform stream. Watch out for breaking the
1694 * small immediates optimization in the process!
1695 */
1696 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1697 for (int i = 0; i < instr->def.num_components; i++)
1698 qregs[i] = vir_uniform_ui(c, instr->value.u32[i]);
1699
1700 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1701 }
1702
1703 static void
1704 ntq_emit_ssa_undef(struct v3d_compile *c, nir_ssa_undef_instr *instr)
1705 {
1706 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1707
1708 /* VIR needs there to be *some* value, so pick 0 (same as for
1709 * ntq_setup_registers().
1710 */
1711 for (int i = 0; i < instr->def.num_components; i++)
1712 qregs[i] = vir_uniform_ui(c, 0);
1713 }
1714
1715 static void
1716 ntq_emit_image_size(struct v3d_compile *c, nir_intrinsic_instr *instr)
1717 {
1718 assert(instr->intrinsic == nir_intrinsic_image_deref_size);
1719 nir_variable *var = nir_intrinsic_get_var(instr, 0);
1720 unsigned image_index = var->data.driver_location;
1721 const struct glsl_type *sampler_type = glsl_without_array(var->type);
1722 bool is_array = glsl_sampler_type_is_array(sampler_type);
1723
1724 ntq_store_dest(c, &instr->dest, 0,
1725 vir_uniform(c, QUNIFORM_IMAGE_WIDTH, image_index));
1726 if (instr->num_components > 1) {
1727 ntq_store_dest(c, &instr->dest, 1,
1728 vir_uniform(c, QUNIFORM_IMAGE_HEIGHT,
1729 image_index));
1730 }
1731 if (instr->num_components > 2) {
1732 ntq_store_dest(c, &instr->dest, 2,
1733 vir_uniform(c,
1734 is_array ?
1735 QUNIFORM_IMAGE_ARRAY_SIZE :
1736 QUNIFORM_IMAGE_DEPTH,
1737 image_index));
1738 }
1739 }
1740
1741 static void
1742 ntq_emit_intrinsic(struct v3d_compile *c, nir_intrinsic_instr *instr)
1743 {
1744 unsigned offset;
1745
1746 switch (instr->intrinsic) {
1747 case nir_intrinsic_load_uniform:
1748 if (nir_src_is_const(instr->src[0])) {
1749 int offset = (nir_intrinsic_base(instr) +
1750 nir_src_as_uint(instr->src[0]));
1751 assert(offset % 4 == 0);
1752 /* We need dwords */
1753 offset = offset / 4;
1754 for (int i = 0; i < instr->num_components; i++) {
1755 ntq_store_dest(c, &instr->dest, i,
1756 vir_uniform(c, QUNIFORM_UNIFORM,
1757 offset + i));
1758 }
1759 } else {
1760 ntq_emit_tmu_general(c, instr, false);
1761 }
1762 break;
1763
1764 case nir_intrinsic_load_ubo:
1765 ntq_emit_tmu_general(c, instr, false);
1766 break;
1767
1768 case nir_intrinsic_ssbo_atomic_add:
1769 case nir_intrinsic_ssbo_atomic_imin:
1770 case nir_intrinsic_ssbo_atomic_umin:
1771 case nir_intrinsic_ssbo_atomic_imax:
1772 case nir_intrinsic_ssbo_atomic_umax:
1773 case nir_intrinsic_ssbo_atomic_and:
1774 case nir_intrinsic_ssbo_atomic_or:
1775 case nir_intrinsic_ssbo_atomic_xor:
1776 case nir_intrinsic_ssbo_atomic_exchange:
1777 case nir_intrinsic_ssbo_atomic_comp_swap:
1778 case nir_intrinsic_load_ssbo:
1779 case nir_intrinsic_store_ssbo:
1780 ntq_emit_tmu_general(c, instr, false);
1781 break;
1782
1783 case nir_intrinsic_shared_atomic_add:
1784 case nir_intrinsic_shared_atomic_imin:
1785 case nir_intrinsic_shared_atomic_umin:
1786 case nir_intrinsic_shared_atomic_imax:
1787 case nir_intrinsic_shared_atomic_umax:
1788 case nir_intrinsic_shared_atomic_and:
1789 case nir_intrinsic_shared_atomic_or:
1790 case nir_intrinsic_shared_atomic_xor:
1791 case nir_intrinsic_shared_atomic_exchange:
1792 case nir_intrinsic_shared_atomic_comp_swap:
1793 case nir_intrinsic_load_shared:
1794 case nir_intrinsic_store_shared:
1795 ntq_emit_tmu_general(c, instr, true);
1796 break;
1797
1798 case nir_intrinsic_image_deref_load:
1799 case nir_intrinsic_image_deref_store:
1800 case nir_intrinsic_image_deref_atomic_add:
1801 case nir_intrinsic_image_deref_atomic_min:
1802 case nir_intrinsic_image_deref_atomic_max:
1803 case nir_intrinsic_image_deref_atomic_and:
1804 case nir_intrinsic_image_deref_atomic_or:
1805 case nir_intrinsic_image_deref_atomic_xor:
1806 case nir_intrinsic_image_deref_atomic_exchange:
1807 case nir_intrinsic_image_deref_atomic_comp_swap:
1808 v3d40_vir_emit_image_load_store(c, instr);
1809 break;
1810
1811 case nir_intrinsic_get_buffer_size:
1812 ntq_store_dest(c, &instr->dest, 0,
1813 vir_uniform(c, QUNIFORM_GET_BUFFER_SIZE,
1814 nir_src_as_uint(instr->src[0])));
1815 break;
1816
1817 case nir_intrinsic_load_user_clip_plane:
1818 for (int i = 0; i < instr->num_components; i++) {
1819 ntq_store_dest(c, &instr->dest, i,
1820 vir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1821 nir_intrinsic_ucp_id(instr) *
1822 4 + i));
1823 }
1824 break;
1825
1826 case nir_intrinsic_load_alpha_ref_float:
1827 ntq_store_dest(c, &instr->dest, 0,
1828 vir_uniform(c, QUNIFORM_ALPHA_REF, 0));
1829 break;
1830
1831 case nir_intrinsic_load_sample_mask_in:
1832 ntq_store_dest(c, &instr->dest, 0, vir_MSF(c));
1833 break;
1834
1835 case nir_intrinsic_load_helper_invocation:
1836 vir_PF(c, vir_MSF(c), V3D_QPU_PF_PUSHZ);
1837 ntq_store_dest(c, &instr->dest, 0,
1838 vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFA,
1839 vir_uniform_ui(c, ~0),
1840 vir_uniform_ui(c, 0))));
1841 break;
1842
1843 case nir_intrinsic_load_front_face:
1844 /* The register contains 0 (front) or 1 (back), and we need to
1845 * turn it into a NIR bool where true means front.
1846 */
1847 ntq_store_dest(c, &instr->dest, 0,
1848 vir_ADD(c,
1849 vir_uniform_ui(c, -1),
1850 vir_REVF(c)));
1851 break;
1852
1853 case nir_intrinsic_load_instance_id:
1854 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->iid));
1855 break;
1856
1857 case nir_intrinsic_load_vertex_id:
1858 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->vid));
1859 break;
1860
1861 case nir_intrinsic_load_input:
1862 for (int i = 0; i < instr->num_components; i++) {
1863 offset = (nir_intrinsic_base(instr) +
1864 nir_src_as_uint(instr->src[0]));
1865 int comp = nir_intrinsic_component(instr) + i;
1866 ntq_store_dest(c, &instr->dest, i,
1867 vir_MOV(c, c->inputs[offset * 4 + comp]));
1868 }
1869 break;
1870
1871 case nir_intrinsic_store_output:
1872 offset = ((nir_intrinsic_base(instr) +
1873 nir_src_as_uint(instr->src[1])) * 4 +
1874 nir_intrinsic_component(instr));
1875
1876 for (int i = 0; i < instr->num_components; i++) {
1877 c->outputs[offset + i] =
1878 vir_MOV(c, ntq_get_src(c, instr->src[0], i));
1879 }
1880 c->num_outputs = MAX2(c->num_outputs,
1881 offset + instr->num_components);
1882 break;
1883
1884 case nir_intrinsic_image_deref_size:
1885 ntq_emit_image_size(c, instr);
1886 break;
1887
1888 case nir_intrinsic_discard:
1889 if (c->execute.file != QFILE_NULL) {
1890 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1891 vir_set_cond(vir_SETMSF_dest(c, vir_nop_reg(),
1892 vir_uniform_ui(c, 0)),
1893 V3D_QPU_COND_IFA);
1894 } else {
1895 vir_SETMSF_dest(c, vir_nop_reg(),
1896 vir_uniform_ui(c, 0));
1897 }
1898 break;
1899
1900 case nir_intrinsic_discard_if: {
1901 /* true (~0) if we're discarding */
1902 struct qreg cond = ntq_get_src(c, instr->src[0], 0);
1903
1904 if (c->execute.file != QFILE_NULL) {
1905 /* execute == 0 means the channel is active. Invert
1906 * the condition so that we can use zero as "executing
1907 * and discarding."
1908 */
1909 vir_PF(c, vir_OR(c, c->execute, vir_NOT(c, cond)),
1910 V3D_QPU_PF_PUSHZ);
1911 vir_set_cond(vir_SETMSF_dest(c, vir_nop_reg(),
1912 vir_uniform_ui(c, 0)),
1913 V3D_QPU_COND_IFA);
1914 } else {
1915 vir_PF(c, cond, V3D_QPU_PF_PUSHZ);
1916 vir_set_cond(vir_SETMSF_dest(c, vir_nop_reg(),
1917 vir_uniform_ui(c, 0)),
1918 V3D_QPU_COND_IFNA);
1919 }
1920
1921 break;
1922 }
1923
1924 case nir_intrinsic_memory_barrier:
1925 case nir_intrinsic_memory_barrier_atomic_counter:
1926 case nir_intrinsic_memory_barrier_buffer:
1927 case nir_intrinsic_memory_barrier_image:
1928 case nir_intrinsic_memory_barrier_shared:
1929 /* We don't do any instruction scheduling of these NIR
1930 * instructions between each other, so we just need to make
1931 * sure that the TMU operations before the barrier are flushed
1932 * before the ones after the barrier. That is currently
1933 * handled by having a THRSW in each of them and a LDTMU
1934 * series or a TMUWT after.
1935 */
1936 break;
1937
1938 case nir_intrinsic_barrier:
1939 /* Emit a TSY op to get all invocations in the workgroup
1940 * (actually supergroup) to block until the last invocation
1941 * reaches the TSY op.
1942 */
1943 if (c->devinfo->ver >= 42) {
1944 vir_BARRIERID_dest(c, vir_reg(QFILE_MAGIC,
1945 V3D_QPU_WADDR_SYNCB));
1946 } else {
1947 struct qinst *sync =
1948 vir_BARRIERID_dest(c,
1949 vir_reg(QFILE_MAGIC,
1950 V3D_QPU_WADDR_SYNCU));
1951 sync->src[vir_get_implicit_uniform_src(sync)] =
1952 vir_uniform_ui(c,
1953 0xffffff00 |
1954 V3D_TSY_WAIT_INC_CHECK);
1955
1956 }
1957
1958 /* The blocking of a TSY op only happens at the next thread
1959 * switch. No texturing may be outstanding at the time of a
1960 * TSY blocking operation.
1961 */
1962 vir_emit_thrsw(c);
1963 break;
1964
1965 case nir_intrinsic_load_num_work_groups:
1966 for (int i = 0; i < 3; i++) {
1967 ntq_store_dest(c, &instr->dest, i,
1968 vir_uniform(c, QUNIFORM_NUM_WORK_GROUPS,
1969 i));
1970 }
1971 break;
1972
1973 case nir_intrinsic_load_local_invocation_index:
1974 ntq_store_dest(c, &instr->dest, 0,
1975 vir_SHR(c, c->cs_payload[1],
1976 vir_uniform_ui(c, 32 - c->local_invocation_index_bits)));
1977 break;
1978
1979 case nir_intrinsic_load_work_group_id:
1980 ntq_store_dest(c, &instr->dest, 0,
1981 vir_AND(c, c->cs_payload[0],
1982 vir_uniform_ui(c, 0xffff)));
1983 ntq_store_dest(c, &instr->dest, 1,
1984 vir_SHR(c, c->cs_payload[0],
1985 vir_uniform_ui(c, 16)));
1986 ntq_store_dest(c, &instr->dest, 2,
1987 vir_AND(c, c->cs_payload[1],
1988 vir_uniform_ui(c, 0xffff)));
1989 break;
1990
1991 default:
1992 fprintf(stderr, "Unknown intrinsic: ");
1993 nir_print_instr(&instr->instr, stderr);
1994 fprintf(stderr, "\n");
1995 break;
1996 }
1997 }
1998
1999 /* Clears (activates) the execute flags for any channels whose jump target
2000 * matches this block.
2001 *
2002 * XXX perf: Could we be using flpush/flpop somehow for our execution channel
2003 * enabling?
2004 *
2005 * XXX perf: For uniform control flow, we should be able to skip c->execute
2006 * handling entirely.
2007 */
2008 static void
2009 ntq_activate_execute_for_block(struct v3d_compile *c)
2010 {
2011 vir_set_pf(vir_XOR_dest(c, vir_nop_reg(),
2012 c->execute, vir_uniform_ui(c, c->cur_block->index)),
2013 V3D_QPU_PF_PUSHZ);
2014
2015 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
2016 }
2017
2018 static void
2019 ntq_emit_uniform_if(struct v3d_compile *c, nir_if *if_stmt)
2020 {
2021 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
2022 bool empty_else_block =
2023 (nir_else_block == nir_if_last_else_block(if_stmt) &&
2024 exec_list_is_empty(&nir_else_block->instr_list));
2025
2026 struct qblock *then_block = vir_new_block(c);
2027 struct qblock *after_block = vir_new_block(c);
2028 struct qblock *else_block;
2029 if (empty_else_block)
2030 else_block = after_block;
2031 else
2032 else_block = vir_new_block(c);
2033
2034 /* Set up the flags for the IF condition (taking the THEN branch). */
2035 nir_alu_instr *if_condition_alu = ntq_get_alu_parent(if_stmt->condition);
2036 enum v3d_qpu_cond cond;
2037 if (!if_condition_alu ||
2038 !ntq_emit_comparison(c, if_condition_alu, &cond)) {
2039 vir_PF(c, ntq_get_src(c, if_stmt->condition, 0),
2040 V3D_QPU_PF_PUSHZ);
2041 cond = V3D_QPU_COND_IFNA;
2042 }
2043
2044 /* Jump to ELSE. */
2045 vir_BRANCH(c, cond == V3D_QPU_COND_IFA ?
2046 V3D_QPU_BRANCH_COND_ALLNA :
2047 V3D_QPU_BRANCH_COND_ALLA);
2048 vir_link_blocks(c->cur_block, else_block);
2049 vir_link_blocks(c->cur_block, then_block);
2050
2051 /* Process the THEN block. */
2052 vir_set_emit_block(c, then_block);
2053 ntq_emit_cf_list(c, &if_stmt->then_list);
2054
2055 if (!empty_else_block) {
2056 /* At the end of the THEN block, jump to ENDIF */
2057 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALWAYS);
2058 vir_link_blocks(c->cur_block, after_block);
2059
2060 /* Emit the else block. */
2061 vir_set_emit_block(c, else_block);
2062 ntq_activate_execute_for_block(c);
2063 ntq_emit_cf_list(c, &if_stmt->else_list);
2064 }
2065
2066 vir_link_blocks(c->cur_block, after_block);
2067
2068 vir_set_emit_block(c, after_block);
2069 }
2070
2071 static void
2072 ntq_emit_nonuniform_if(struct v3d_compile *c, nir_if *if_stmt)
2073 {
2074 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
2075 bool empty_else_block =
2076 (nir_else_block == nir_if_last_else_block(if_stmt) &&
2077 exec_list_is_empty(&nir_else_block->instr_list));
2078
2079 struct qblock *then_block = vir_new_block(c);
2080 struct qblock *after_block = vir_new_block(c);
2081 struct qblock *else_block;
2082 if (empty_else_block)
2083 else_block = after_block;
2084 else
2085 else_block = vir_new_block(c);
2086
2087 bool was_top_level = false;
2088 if (c->execute.file == QFILE_NULL) {
2089 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
2090 was_top_level = true;
2091 }
2092
2093 /* Set up the flags for the IF condition (taking the THEN branch). */
2094 nir_alu_instr *if_condition_alu = ntq_get_alu_parent(if_stmt->condition);
2095 enum v3d_qpu_cond cond;
2096 if (!if_condition_alu ||
2097 !ntq_emit_comparison(c, if_condition_alu, &cond)) {
2098 vir_PF(c, ntq_get_src(c, if_stmt->condition, 0),
2099 V3D_QPU_PF_PUSHZ);
2100 cond = V3D_QPU_COND_IFNA;
2101 }
2102
2103 /* Update the flags+cond to mean "Taking the ELSE branch (!cond) and
2104 * was previously active (execute Z) for updating the exec flags.
2105 */
2106 if (was_top_level) {
2107 cond = v3d_qpu_cond_invert(cond);
2108 } else {
2109 struct qinst *inst = vir_MOV_dest(c, vir_nop_reg(), c->execute);
2110 if (cond == V3D_QPU_COND_IFA) {
2111 vir_set_uf(inst, V3D_QPU_UF_NORNZ);
2112 } else {
2113 vir_set_uf(inst, V3D_QPU_UF_ANDZ);
2114 cond = V3D_QPU_COND_IFA;
2115 }
2116 }
2117
2118 vir_MOV_cond(c, cond,
2119 c->execute,
2120 vir_uniform_ui(c, else_block->index));
2121
2122 /* Jump to ELSE if nothing is active for THEN, otherwise fall
2123 * through.
2124 */
2125 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
2126 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLNA);
2127 vir_link_blocks(c->cur_block, else_block);
2128 vir_link_blocks(c->cur_block, then_block);
2129
2130 /* Process the THEN block. */
2131 vir_set_emit_block(c, then_block);
2132 ntq_emit_cf_list(c, &if_stmt->then_list);
2133
2134 if (!empty_else_block) {
2135 /* Handle the end of the THEN block. First, all currently
2136 * active channels update their execute flags to point to
2137 * ENDIF
2138 */
2139 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
2140 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2141 vir_uniform_ui(c, after_block->index));
2142
2143 /* If everything points at ENDIF, then jump there immediately. */
2144 vir_PF(c, vir_XOR(c, c->execute,
2145 vir_uniform_ui(c, after_block->index)),
2146 V3D_QPU_PF_PUSHZ);
2147 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLA);
2148 vir_link_blocks(c->cur_block, after_block);
2149 vir_link_blocks(c->cur_block, else_block);
2150
2151 vir_set_emit_block(c, else_block);
2152 ntq_activate_execute_for_block(c);
2153 ntq_emit_cf_list(c, &if_stmt->else_list);
2154 }
2155
2156 vir_link_blocks(c->cur_block, after_block);
2157
2158 vir_set_emit_block(c, after_block);
2159 if (was_top_level)
2160 c->execute = c->undef;
2161 else
2162 ntq_activate_execute_for_block(c);
2163 }
2164
2165 static void
2166 ntq_emit_if(struct v3d_compile *c, nir_if *nif)
2167 {
2168 if (c->execute.file == QFILE_NULL &&
2169 nir_src_is_dynamically_uniform(nif->condition)) {
2170 ntq_emit_uniform_if(c, nif);
2171 } else {
2172 ntq_emit_nonuniform_if(c, nif);
2173 }
2174 }
2175
2176 static void
2177 ntq_emit_jump(struct v3d_compile *c, nir_jump_instr *jump)
2178 {
2179 switch (jump->type) {
2180 case nir_jump_break:
2181 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
2182 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2183 vir_uniform_ui(c, c->loop_break_block->index));
2184 break;
2185
2186 case nir_jump_continue:
2187 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
2188 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2189 vir_uniform_ui(c, c->loop_cont_block->index));
2190 break;
2191
2192 case nir_jump_return:
2193 unreachable("All returns shouold be lowered\n");
2194 }
2195 }
2196
2197 static void
2198 ntq_emit_instr(struct v3d_compile *c, nir_instr *instr)
2199 {
2200 switch (instr->type) {
2201 case nir_instr_type_deref:
2202 /* ignored, will be walked by the intrinsic using it. */
2203 break;
2204
2205 case nir_instr_type_alu:
2206 ntq_emit_alu(c, nir_instr_as_alu(instr));
2207 break;
2208
2209 case nir_instr_type_intrinsic:
2210 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
2211 break;
2212
2213 case nir_instr_type_load_const:
2214 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
2215 break;
2216
2217 case nir_instr_type_ssa_undef:
2218 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
2219 break;
2220
2221 case nir_instr_type_tex:
2222 ntq_emit_tex(c, nir_instr_as_tex(instr));
2223 break;
2224
2225 case nir_instr_type_jump:
2226 ntq_emit_jump(c, nir_instr_as_jump(instr));
2227 break;
2228
2229 default:
2230 fprintf(stderr, "Unknown NIR instr type: ");
2231 nir_print_instr(instr, stderr);
2232 fprintf(stderr, "\n");
2233 abort();
2234 }
2235 }
2236
2237 static void
2238 ntq_emit_block(struct v3d_compile *c, nir_block *block)
2239 {
2240 nir_foreach_instr(instr, block) {
2241 ntq_emit_instr(c, instr);
2242 }
2243 }
2244
2245 static void ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
2246
2247 static void
2248 ntq_emit_loop(struct v3d_compile *c, nir_loop *loop)
2249 {
2250 bool was_top_level = false;
2251 if (c->execute.file == QFILE_NULL) {
2252 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
2253 was_top_level = true;
2254 }
2255
2256 struct qblock *save_loop_cont_block = c->loop_cont_block;
2257 struct qblock *save_loop_break_block = c->loop_break_block;
2258
2259 c->loop_cont_block = vir_new_block(c);
2260 c->loop_break_block = vir_new_block(c);
2261
2262 vir_link_blocks(c->cur_block, c->loop_cont_block);
2263 vir_set_emit_block(c, c->loop_cont_block);
2264 ntq_activate_execute_for_block(c);
2265
2266 ntq_emit_cf_list(c, &loop->body);
2267
2268 /* Re-enable any previous continues now, so our ANYA check below
2269 * works.
2270 *
2271 * XXX: Use the .ORZ flags update, instead.
2272 */
2273 vir_PF(c, vir_XOR(c,
2274 c->execute,
2275 vir_uniform_ui(c, c->loop_cont_block->index)),
2276 V3D_QPU_PF_PUSHZ);
2277 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
2278
2279 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
2280
2281 struct qinst *branch = vir_BRANCH(c, V3D_QPU_BRANCH_COND_ANYA);
2282 /* Pixels that were not dispatched or have been discarded should not
2283 * contribute to looping again.
2284 */
2285 branch->qpu.branch.msfign = V3D_QPU_MSFIGN_P;
2286 vir_link_blocks(c->cur_block, c->loop_cont_block);
2287 vir_link_blocks(c->cur_block, c->loop_break_block);
2288
2289 vir_set_emit_block(c, c->loop_break_block);
2290 if (was_top_level)
2291 c->execute = c->undef;
2292 else
2293 ntq_activate_execute_for_block(c);
2294
2295 c->loop_break_block = save_loop_break_block;
2296 c->loop_cont_block = save_loop_cont_block;
2297
2298 c->loops++;
2299 }
2300
2301 static void
2302 ntq_emit_function(struct v3d_compile *c, nir_function_impl *func)
2303 {
2304 fprintf(stderr, "FUNCTIONS not handled.\n");
2305 abort();
2306 }
2307
2308 static void
2309 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list)
2310 {
2311 foreach_list_typed(nir_cf_node, node, node, list) {
2312 switch (node->type) {
2313 case nir_cf_node_block:
2314 ntq_emit_block(c, nir_cf_node_as_block(node));
2315 break;
2316
2317 case nir_cf_node_if:
2318 ntq_emit_if(c, nir_cf_node_as_if(node));
2319 break;
2320
2321 case nir_cf_node_loop:
2322 ntq_emit_loop(c, nir_cf_node_as_loop(node));
2323 break;
2324
2325 case nir_cf_node_function:
2326 ntq_emit_function(c, nir_cf_node_as_function(node));
2327 break;
2328
2329 default:
2330 fprintf(stderr, "Unknown NIR node type\n");
2331 abort();
2332 }
2333 }
2334 }
2335
2336 static void
2337 ntq_emit_impl(struct v3d_compile *c, nir_function_impl *impl)
2338 {
2339 ntq_setup_registers(c, &impl->registers);
2340 ntq_emit_cf_list(c, &impl->body);
2341 }
2342
2343 static void
2344 nir_to_vir(struct v3d_compile *c)
2345 {
2346 switch (c->s->info.stage) {
2347 case MESA_SHADER_FRAGMENT:
2348 c->payload_w = vir_MOV(c, vir_reg(QFILE_REG, 0));
2349 c->payload_w_centroid = vir_MOV(c, vir_reg(QFILE_REG, 1));
2350 c->payload_z = vir_MOV(c, vir_reg(QFILE_REG, 2));
2351
2352 /* XXX perf: We could set the "disable implicit point/line
2353 * varyings" field in the shader record and not emit these, if
2354 * they're not going to be used.
2355 */
2356 if (c->fs_key->is_points) {
2357 c->point_x = emit_fragment_varying(c, NULL, 0, 0);
2358 c->point_y = emit_fragment_varying(c, NULL, 0, 0);
2359 } else if (c->fs_key->is_lines) {
2360 c->line_x = emit_fragment_varying(c, NULL, 0, 0);
2361 }
2362 break;
2363 case MESA_SHADER_COMPUTE:
2364 /* Set up the TSO for barriers, assuming we do some. */
2365 if (c->devinfo->ver < 42) {
2366 vir_BARRIERID_dest(c, vir_reg(QFILE_MAGIC,
2367 V3D_QPU_WADDR_SYNC));
2368 }
2369
2370 if (c->s->info.system_values_read &
2371 ((1ull << SYSTEM_VALUE_LOCAL_INVOCATION_INDEX) |
2372 (1ull << SYSTEM_VALUE_WORK_GROUP_ID))) {
2373 c->cs_payload[0] = vir_MOV(c, vir_reg(QFILE_REG, 0));
2374 }
2375 if ((c->s->info.system_values_read &
2376 ((1ull << SYSTEM_VALUE_WORK_GROUP_ID))) ||
2377 c->s->info.cs.shared_size) {
2378 c->cs_payload[1] = vir_MOV(c, vir_reg(QFILE_REG, 2));
2379 }
2380
2381 /* Set up the division between gl_LocalInvocationIndex and
2382 * wg_in_mem in the payload reg.
2383 */
2384 int wg_size = (c->s->info.cs.local_size[0] *
2385 c->s->info.cs.local_size[1] *
2386 c->s->info.cs.local_size[2]);
2387 c->local_invocation_index_bits =
2388 ffs(util_next_power_of_two(MAX2(wg_size, 64))) - 1;
2389 assert(c->local_invocation_index_bits <= 8);
2390
2391 if (c->s->info.cs.shared_size) {
2392 struct qreg wg_in_mem = vir_SHR(c, c->cs_payload[1],
2393 vir_uniform_ui(c, 16));
2394 if (c->s->info.cs.local_size[0] != 1 ||
2395 c->s->info.cs.local_size[1] != 1 ||
2396 c->s->info.cs.local_size[2] != 1) {
2397 int wg_bits = (16 -
2398 c->local_invocation_index_bits);
2399 int wg_mask = (1 << wg_bits) - 1;
2400 wg_in_mem = vir_AND(c, wg_in_mem,
2401 vir_uniform_ui(c, wg_mask));
2402 }
2403 struct qreg shared_per_wg =
2404 vir_uniform_ui(c, c->s->info.cs.shared_size);
2405
2406 c->cs_shared_offset =
2407 vir_ADD(c,
2408 vir_uniform(c, QUNIFORM_SHARED_OFFSET,0),
2409 vir_UMUL(c, wg_in_mem, shared_per_wg));
2410 }
2411 break;
2412 default:
2413 break;
2414 }
2415
2416 if (c->s->info.stage == MESA_SHADER_FRAGMENT)
2417 ntq_setup_fs_inputs(c);
2418 else
2419 ntq_setup_vpm_inputs(c);
2420
2421 ntq_setup_outputs(c);
2422 ntq_setup_uniforms(c);
2423 ntq_setup_registers(c, &c->s->registers);
2424
2425 /* Find the main function and emit the body. */
2426 nir_foreach_function(function, c->s) {
2427 assert(strcmp(function->name, "main") == 0);
2428 assert(function->impl);
2429 ntq_emit_impl(c, function->impl);
2430 }
2431 }
2432
2433 const nir_shader_compiler_options v3d_nir_options = {
2434 .lower_all_io_to_temps = true,
2435 .lower_extract_byte = true,
2436 .lower_extract_word = true,
2437 .lower_bfm = true,
2438 .lower_bitfield_insert_to_shifts = true,
2439 .lower_bitfield_extract_to_shifts = true,
2440 .lower_bitfield_reverse = true,
2441 .lower_bit_count = true,
2442 .lower_cs_local_id_from_index = true,
2443 .lower_ffract = true,
2444 .lower_pack_unorm_2x16 = true,
2445 .lower_pack_snorm_2x16 = true,
2446 .lower_pack_unorm_4x8 = true,
2447 .lower_pack_snorm_4x8 = true,
2448 .lower_unpack_unorm_4x8 = true,
2449 .lower_unpack_snorm_4x8 = true,
2450 .lower_pack_half_2x16 = true,
2451 .lower_unpack_half_2x16 = true,
2452 .lower_fdiv = true,
2453 .lower_find_lsb = true,
2454 .lower_ffma = true,
2455 .lower_flrp32 = true,
2456 .lower_fpow = true,
2457 .lower_fsat = true,
2458 .lower_fsqrt = true,
2459 .lower_ifind_msb = true,
2460 .lower_isign = true,
2461 .lower_ldexp = true,
2462 .lower_mul_high = true,
2463 .lower_wpos_pntc = true,
2464 .native_integers = true,
2465 };
2466
2467 /**
2468 * When demoting a shader down to single-threaded, removes the THRSW
2469 * instructions (one will still be inserted at v3d_vir_to_qpu() for the
2470 * program end).
2471 */
2472 static void
2473 vir_remove_thrsw(struct v3d_compile *c)
2474 {
2475 vir_for_each_block(block, c) {
2476 vir_for_each_inst_safe(inst, block) {
2477 if (inst->qpu.sig.thrsw)
2478 vir_remove_instruction(c, inst);
2479 }
2480 }
2481
2482 c->last_thrsw = NULL;
2483 }
2484
2485 void
2486 vir_emit_last_thrsw(struct v3d_compile *c)
2487 {
2488 /* On V3D before 4.1, we need a TMU op to be outstanding when thread
2489 * switching, so disable threads if we didn't do any TMU ops (each of
2490 * which would have emitted a THRSW).
2491 */
2492 if (!c->last_thrsw_at_top_level && c->devinfo->ver < 41) {
2493 c->threads = 1;
2494 if (c->last_thrsw)
2495 vir_remove_thrsw(c);
2496 return;
2497 }
2498
2499 /* If we're threaded and the last THRSW was in conditional code, then
2500 * we need to emit another one so that we can flag it as the last
2501 * thrsw.
2502 */
2503 if (c->last_thrsw && !c->last_thrsw_at_top_level) {
2504 assert(c->devinfo->ver >= 41);
2505 vir_emit_thrsw(c);
2506 }
2507
2508 /* If we're threaded, then we need to mark the last THRSW instruction
2509 * so we can emit a pair of them at QPU emit time.
2510 *
2511 * For V3D 4.x, we can spawn the non-fragment shaders already in the
2512 * post-last-THRSW state, so we can skip this.
2513 */
2514 if (!c->last_thrsw && c->s->info.stage == MESA_SHADER_FRAGMENT) {
2515 assert(c->devinfo->ver >= 41);
2516 vir_emit_thrsw(c);
2517 }
2518
2519 if (c->last_thrsw)
2520 c->last_thrsw->is_last_thrsw = true;
2521 }
2522
2523 /* There's a flag in the shader for "center W is needed for reasons other than
2524 * non-centroid varyings", so we just walk the program after VIR optimization
2525 * to see if it's used. It should be harmless to set even if we only use
2526 * center W for varyings.
2527 */
2528 static void
2529 vir_check_payload_w(struct v3d_compile *c)
2530 {
2531 if (c->s->info.stage != MESA_SHADER_FRAGMENT)
2532 return;
2533
2534 vir_for_each_inst_inorder(inst, c) {
2535 for (int i = 0; i < vir_get_nsrc(inst); i++) {
2536 if (inst->src[i].file == QFILE_REG &&
2537 inst->src[i].index == 0) {
2538 c->uses_center_w = true;
2539 return;
2540 }
2541 }
2542 }
2543
2544 }
2545
2546 void
2547 v3d_nir_to_vir(struct v3d_compile *c)
2548 {
2549 if (V3D_DEBUG & (V3D_DEBUG_NIR |
2550 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2551 fprintf(stderr, "%s prog %d/%d NIR:\n",
2552 vir_get_stage_name(c),
2553 c->program_id, c->variant_id);
2554 nir_print_shader(c->s, stderr);
2555 }
2556
2557 nir_to_vir(c);
2558
2559 /* Emit the last THRSW before STVPM and TLB writes. */
2560 vir_emit_last_thrsw(c);
2561
2562 switch (c->s->info.stage) {
2563 case MESA_SHADER_FRAGMENT:
2564 emit_frag_end(c);
2565 break;
2566 case MESA_SHADER_VERTEX:
2567 emit_vert_end(c);
2568 break;
2569 default:
2570 unreachable("bad stage");
2571 }
2572
2573 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2574 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2575 fprintf(stderr, "%s prog %d/%d pre-opt VIR:\n",
2576 vir_get_stage_name(c),
2577 c->program_id, c->variant_id);
2578 vir_dump(c);
2579 fprintf(stderr, "\n");
2580 }
2581
2582 vir_optimize(c);
2583 vir_lower_uniforms(c);
2584
2585 vir_check_payload_w(c);
2586
2587 /* XXX perf: On VC4, we do a VIR-level instruction scheduling here.
2588 * We used that on that platform to pipeline TMU writes and reduce the
2589 * number of thread switches, as well as try (mostly successfully) to
2590 * reduce maximum register pressure to allow more threads. We should
2591 * do something of that sort for V3D -- either instruction scheduling
2592 * here, or delay the the THRSW and LDTMUs from our texture
2593 * instructions until the results are needed.
2594 */
2595
2596 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2597 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2598 fprintf(stderr, "%s prog %d/%d VIR:\n",
2599 vir_get_stage_name(c),
2600 c->program_id, c->variant_id);
2601 vir_dump(c);
2602 fprintf(stderr, "\n");
2603 }
2604
2605 /* Attempt to allocate registers for the temporaries. If we fail,
2606 * reduce thread count and try again.
2607 */
2608 int min_threads = (c->devinfo->ver >= 41) ? 2 : 1;
2609 struct qpu_reg *temp_registers;
2610 while (true) {
2611 bool spilled;
2612 temp_registers = v3d_register_allocate(c, &spilled);
2613 if (spilled)
2614 continue;
2615
2616 if (temp_registers)
2617 break;
2618
2619 if (c->threads == min_threads) {
2620 fprintf(stderr, "Failed to register allocate at %d threads:\n",
2621 c->threads);
2622 vir_dump(c);
2623 c->failed = true;
2624 return;
2625 }
2626
2627 c->threads /= 2;
2628
2629 if (c->threads == 1)
2630 vir_remove_thrsw(c);
2631 }
2632
2633 v3d_vir_to_qpu(c, temp_registers);
2634 }